From 9840598aa31f2a89272f5bef6545e316f254f0c6 Mon Sep 17 00:00:00 2001 From: Andrew Turner Date: Tue, 23 Jul 2024 10:18:36 +0100 Subject: [PATCH] dev/uart: Add APMC0D08 as found in the Intel E2100 This uart has the requirement for 32-bit sized and aligned memory accesses. It is also described in the Serial Port Console Redirection Table (SPCR) with a different interface type value. Reviewed by: imp Sponsored by: Arm Ltd Differential Revision: https://reviews.freebsd.org/D45834 --- sys/dev/uart/uart_dev_ns8250.c | 1 + 1 file changed, 1 insertion(+) diff --git a/sys/dev/uart/uart_dev_ns8250.c b/sys/dev/uart/uart_dev_ns8250.c index 16c3cb2fc5a..1a58600c803 100644 --- a/sys/dev/uart/uart_dev_ns8250.c +++ b/sys/dev/uart/uart_dev_ns8250.c @@ -460,6 +460,7 @@ UART_CLASS(uart_ns8250_class); static struct acpi_uart_compat_data acpi_compat_data[] = { {"AMD0020", &uart_ns8250_class, 0, 2, 0, 48000000, UART_F_BUSY_DETECT, "AMD / Synopsys Designware UART"}, {"AMDI0020", &uart_ns8250_class, 0, 2, 0, 48000000, UART_F_BUSY_DETECT, "AMD / Synopsys Designware UART"}, + {"APMC0D08", &uart_ns8250_class, ACPI_DBG2_16550_COMPATIBLE, 2, 4, 0, 0, "APM compatible UART"}, {"MRVL0001", &uart_ns8250_class, ACPI_DBG2_16550_SUBSET, 2, 0, 200000000, UART_F_BUSY_DETECT, "Marvell / Synopsys Designware UART"}, {"SCX0006", &uart_ns8250_class, 0, 2, 0, 62500000, UART_F_BUSY_DETECT, "SynQuacer / Synopsys Designware UART"}, {"HISI0031", &uart_ns8250_class, 0, 2, 0, 200000000, UART_F_BUSY_DETECT, "HiSilicon / Synopsys Designware UART"},