diff --git a/sys/arm/include/armreg.h b/sys/arm/include/armreg.h
index b509d7d3d49..1d96edda521 100644
--- a/sys/arm/include/armreg.h
+++ b/sys/arm/include/armreg.h
@@ -144,7 +144,7 @@
 #define	 CPU_ID_CORTEXA9R2	(CPU_ID_CORTEXA9 | (2 << CPU_ID_VARIANT_SHIFT))
 #define	 CPU_ID_CORTEXA9R3	(CPU_ID_CORTEXA9 | (3 << CPU_ID_VARIANT_SHIFT))
 #define	 CPU_ID_CORTEXA9R4	(CPU_ID_CORTEXA9 | (4 << CPU_ID_VARIANT_SHIFT))
-/* XXX: Cortx-A12 is the old name for this part, it has been renamed the A17 */
+/* XXX: Cortex-A12 is the old name for this part, it has been renamed the A17 */
 #define	CPU_ID_CORTEXA12	(CPU_ID_ARM_LTD | CPU_ID_CPUID_SCHEME | 0xc0d0)
 #define	 CPU_ID_CORTEXA12R0	(CPU_ID_CORTEXA12 | (0 << CPU_ID_VARIANT_SHIFT))
 #define	CPU_ID_CORTEXA15	(CPU_ID_ARM_LTD | CPU_ID_CPUID_SCHEME | 0xc0f0)
diff --git a/sys/arm/include/cpu-v6.h b/sys/arm/include/cpu-v6.h
index 45a91316af2..fd2edac98ba 100644
--- a/sys/arm/include/cpu-v6.h
+++ b/sys/arm/include/cpu-v6.h
@@ -345,12 +345,18 @@ tlb_flush_range_local(vm_offset_t va, vm_size_t size)
 /* Broadcasting operations. */
 #if __ARM_ARCH >= 7 && defined SMP
 
+/* Used to detect SMP */
+extern int mp_ncpus;
+
 static __inline void
 tlb_flush_all(void)
 {
 
 	dsb();
-	_CP15_TLBIALLIS();
+	if (mp_ncpus == 1)
+		_CP15_TLBIALL();
+	else
+		_CP15_TLBIALLIS();
 	dsb();
 }
 
@@ -359,7 +365,10 @@ tlb_flush_all_ng(void)
 {
 
 	dsb();
-	_CP15_TLBIASIDIS(CPU_ASID_KERNEL);
+	if (mp_ncpus == 1)
+		_CP15_TLBIASID(CPU_ASID_KERNEL);
+	else
+		_CP15_TLBIASIDIS(CPU_ASID_KERNEL);
 	dsb();
 }
 
@@ -370,7 +379,10 @@ tlb_flush(vm_offset_t va)
 	KASSERT((va & PAGE_MASK) == 0, ("%s: va %#x not aligned", __func__, va));
 
 	dsb();
-	_CP15_TLBIMVAAIS(va);
+	if (mp_ncpus == 1)
+		_CP15_TLBIMVA(va | CPU_ASID_KERNEL);
+	else
+		_CP15_TLBIMVAAIS(va);
 	dsb();
 }
 
@@ -384,8 +396,13 @@ tlb_flush_range(vm_offset_t va,  vm_size_t size)
 	    size));
 
 	dsb();
-	for (; va < eva; va += PAGE_SIZE)
-		_CP15_TLBIMVAAIS(va);
+	if (mp_ncpus == 1) {
+		for (; va < eva; va += PAGE_SIZE)
+			_CP15_TLBIMVA(va | CPU_ASID_KERNEL);
+	} else {
+		for (; va < eva; va += PAGE_SIZE)
+			_CP15_TLBIMVAAIS(va);
+	}
 	dsb();
 }
 #else /* SMP */
@@ -411,17 +428,19 @@ icache_sync(vm_offset_t va, vm_size_t size)
 	va &= ~cpuinfo.dcache_line_mask;
 	for ( ; va < eva; va += cpuinfo.dcache_line_size) {
 #if __ARM_ARCH >= 7 && defined SMP
-		_CP15_DCCMVAU(va);
-#else
-		_CP15_DCCMVAC(va);
+		if (mp_ncpus > 1)
+			_CP15_DCCMVAU(va);
+		else
 #endif
+			_CP15_DCCMVAC(va);
 	}
 	dsb();
 #if __ARM_ARCH >= 7 && defined SMP
-	_CP15_ICIALLUIS();
-#else
-	_CP15_ICIALLU();
+	if (mp_ncpus > 1)
+		_CP15_ICIALLUIS();
+	else
 #endif
+		_CP15_ICIALLU();
 	dsb();
 	isb();
 }
@@ -431,10 +450,11 @@ static __inline void
 icache_inv_all(void)
 {
 #if __ARM_ARCH >= 7 && defined SMP
-	_CP15_ICIALLUIS();
-#else
-	_CP15_ICIALLU();
+	if (mp_ncpus > 1)
+		_CP15_ICIALLUIS();
+	else
 #endif
+		_CP15_ICIALLU();
 	dsb();
 	isb();
 }
@@ -444,10 +464,11 @@ static __inline void
 bpb_inv_all(void)
 {
 #if __ARM_ARCH >= 7 && defined SMP
-	_CP15_BPIALLIS();
-#else
-	_CP15_BPIALL();
+	if (mp_ncpus > 1)
+		_CP15_BPIALLIS();
+	else
 #endif
+		_CP15_BPIALL();
 	dsb();
 	isb();
 }
@@ -462,10 +483,11 @@ dcache_wb_pou(vm_offset_t va, vm_size_t size)
 	va &= ~cpuinfo.dcache_line_mask;
 	for ( ; va < eva; va += cpuinfo.dcache_line_size) {
 #if __ARM_ARCH >= 7 && defined SMP
-		_CP15_DCCMVAU(va);
-#else
-		_CP15_DCCMVAC(va);
+		if (mp_ncpus > 1)
+			_CP15_DCCMVAU(va);
+		else
 #endif
+			_CP15_DCCMVAC(va);
 	}
 	dsb();
 }