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arm64: Fix the gicv3 check in locore.S

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In locore.S we need to configure access to the GICv3. To check if it's
available we read the id_aa64pfr0_el1 register, however we then only
check if a GICv3.0 or 4.0 is present. If the system has a GICv4.1 this
check would fail.

Move to checking if the GICV3+ is not absent so this will still work if
the field is updated again.

Sponsored by:	Arm Ltd
Differential Revision:	https://reviews.freebsd.org/D45530

(cherry picked from commit 57ef7935eb114e98e7e554c5ffbded68fd038c04)
This commit is contained in:
Andrew Turner 2024-07-23 10:18:08 +01:00
parent 570fae59a8
commit 94865825c0
1 changed files with 2 additions and 3 deletions
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5
sys/arm64/arm64/locore.S
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@ -341,9 +341,8 @@ LENTRY(enter_kernel_el)
mrs x2, id_aa64pfr0_el1
/* Extract GIC bits from the register */
ubfx x2, x2, #ID_AA64PFR0_GIC_SHIFT, #ID_AA64PFR0_GIC_BITS
/* GIC[3:0] == 0001 - GIC CPU interface via special regs. supported */
cmp x2, #(ID_AA64PFR0_GIC_CPUIF_EN >> ID_AA64PFR0_GIC_SHIFT)
b.ne 2f
/* GIC[3:0] != 0000 - GIC CPU interface via special regs. supported */
cbz x2, 2f
mrs x2, icc_sre_el2
orr x2, x2, #ICC_SRE_EL2_EN /* Enable access from insecure EL1 */