From 93e26ff43853c83fcb690b4b4ab4e8f7e3e96a2e Mon Sep 17 00:00:00 2001 From: Adrian Chadd Date: Sat, 7 Jan 2012 04:13:25 +0000 Subject: [PATCH] Fix the ar724x shift calculation when writing to the PCI config space. This was preventing the ath driver from being loaded at runtime. It worked fine when compiled statically into the kernel but not when kldload'ed after the system booted. The root cause was that PCIR_INTLINE (register 60) was being overwritten by zeros when register 62 was being written to. A subsequent read of this register would return 0, and thus the rest of the PCI glue assumed an IRQ resource had already been allocated. This caused the device to fail to attach at runtime as the device itself didn't contain any IRQ resources. TODO: go back over the ar71xx and ar724x PCI config read/write code and ensure it's correct. --- sys/mips/atheros/ar724x_pci.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/sys/mips/atheros/ar724x_pci.c b/sys/mips/atheros/ar724x_pci.c index 59be9c0ad5b..f3519c65bcc 100644 --- a/sys/mips/atheros/ar724x_pci.c +++ b/sys/mips/atheros/ar724x_pci.c @@ -93,7 +93,7 @@ ar724x_pci_write(uint32_t reg, uint32_t offset, uint32_t data, int bytes) uint32_t val, mask, shift; /* Register access is 32-bit aligned */ - shift = 8 * (offset & (bytes % 4)); + shift = (offset & 3) * 8; if (bytes % 4) mask = (1 << (bytes * 8)) - 1; else