diff --git a/sys/mips/mediatek/mtk_intr_gic.c b/sys/mips/mediatek/mtk_intr_gic.c
index ab96cacb2fb..5c250453e84 100644
--- a/sys/mips/mediatek/mtk_intr_gic.c
+++ b/sys/mips/mediatek/mtk_intr_gic.c
@@ -95,7 +95,6 @@ struct mtk_gic_softc {
 
 static struct resource_spec mtk_gic_spec[] = {
 	{ SYS_RES_MEMORY,	0,	RF_ACTIVE },	/* Registers */
-	{ SYS_RES_IRQ,		0,	RF_ACTIVE },	/* Parent interrupt 1 */
 	{ -1, 0 }
 };
 
@@ -104,15 +103,8 @@ static struct ofw_compat_data compat_data[] = {
 	{ NULL,		0 }
 };
 
-#if 0
-#define	READ4(_sc, _reg)	\
-    bus_space_read_4((_sc)->bst, (_sc)->bsh, _reg)
-#define	WRITE4(_sc, _reg, _val) \
-    bus_space_write_4((_sc)->bst, (_sc)->bsh, _reg, _val)
-#else
 #define READ4(_sc, _reg)	bus_read_4((_sc)->gic_res[0], (_reg))
 #define WRITE4(_sc, _reg, _val)	bus_write_4((_sc)->gic_res[0], (_reg), (_val))
-#endif
 
 static int
 mtk_gic_probe(device_t dev)
@@ -226,12 +218,9 @@ mtk_gic_attach(device_t dev)
 		goto cleanup;
 	}
 
-	if (bus_setup_intr(dev, sc->gic_res[1], INTR_TYPE_CLK,
-	    mtk_gic_intr, NULL, sc, &sc->gic_intrhand)) {
-		device_printf(dev, "could not setup irq handler\n");
-		intr_pic_deregister(dev, xref);
-		goto cleanup;
-	}
+	cpu_establish_hardintr("gic", mtk_gic_intr, NULL, sc, 0, INTR_TYPE_CLK,
+	    NULL);
+
 	return (0);
 
 cleanup: