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https://github.com/opnsense/src.git
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Support for XLP4xx and XLP 8xx B0 revision
- Add 4xx processor IDs, add workaround in CPU detection code. - Update frequency detection code for XLP 8xx. - Add setting device frequency code. - Update processor ID checking code.
This commit is contained in:
Jayachandran C.
parent
7aeda475e5
commit
91339fd498
4 changed files with 159 additions and 54 deletions
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@ -55,33 +55,81 @@ int pic_irt_pcie_lnk2;
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int pic_irt_pcie_lnk3;
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uint32_t
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xlp_get_cpu_frequency(int core)
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xlp_get_cpu_frequency(int node, int core)
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{
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uint64_t sysbase = nlm_get_sys_regbase(nlm_nodeid());
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uint64_t num;
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uint64_t sysbase = nlm_get_sys_regbase(node);
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unsigned int pll_divf, pll_divr, dfs_div, ext_div;
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unsigned int rstval, dfsval, denom;
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unsigned int rstval, dfsval;
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rstval = nlm_read_sys_reg(sysbase, SYS_POWER_ON_RESET_CFG);
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dfsval = nlm_read_sys_reg(sysbase, SYS_CORE_DFS_DIV_VALUE);
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pll_divf = ((rstval >> 10) & 0x7f) + 1;
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pll_divr = ((rstval >> 8) & 0x3) + 1;
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ext_div = ((rstval >> 30) & 0x3) + 1;
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dfs_div = ((dfsval >> (core * 4)) & 0xf) + 1;
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if (!nlm_is_xlp8xx_ax())
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ext_div = ((rstval >> 30) & 0x3) + 1;
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else
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ext_div = 1;
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dfs_div = ((dfsval >> (core << 2)) & 0xf) + 1;
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num = 800000000ULL * pll_divf;
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denom = 3 * pll_divr * ext_div * dfs_div;
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num = num/denom;
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return (num);
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return ((800000000ULL * pll_divf)/(3 * pll_divr * ext_div * dfs_div));
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}
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static u_int
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nlm_get_device_frequency(uint64_t sysbase, int devtype)
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{
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uint32_t pllctrl, dfsdiv, spf, spr, div_val;
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int extra_div;
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pllctrl = nlm_read_sys_reg(sysbase, SYS_PLL_CTRL);
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if (devtype <= 7)
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div_val = nlm_read_sys_reg(sysbase, SYS_DFS_DIV_VALUE0);
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else {
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devtype -= 8;
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div_val = nlm_read_sys_reg(sysbase, SYS_DFS_DIV_VALUE1);
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}
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dfsdiv = ((div_val >> (devtype << 2)) & 0xf) + 1;
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spf = (pllctrl >> 3 & 0x7f) + 1;
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spr = (pllctrl >> 1 & 0x03) + 1;
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extra_div = nlm_is_xlp8xx_ax() ? 1 : 2;
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return ((400 * spf) / (3 * extra_div * spr * dfsdiv));
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}
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int
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nlm_set_device_frequency(int node, int devtype, int frequency)
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{
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uint64_t sysbase;
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u_int cur_freq;
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int dec_div;
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sysbase = nlm_get_sys_regbase(node);
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cur_freq = nlm_get_device_frequency(sysbase, devtype);
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if (cur_freq < (frequency - 5))
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dec_div = 1;
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else
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dec_div = 0;
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for(;;) {
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if ((cur_freq >= (frequency - 5)) && (cur_freq <= frequency))
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break;
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if (dec_div)
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nlm_write_sys_reg(sysbase, SYS_DFS_DIV_DEC_CTRL,
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(1 << devtype));
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else
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nlm_write_sys_reg(sysbase, SYS_DFS_DIV_INC_CTRL,
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(1 << devtype));
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cur_freq = nlm_get_device_frequency(sysbase, devtype);
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}
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return (nlm_get_device_frequency(sysbase, devtype));
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}
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void
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nlm_pic_irt_init(void)
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nlm_pic_irt_init(int node)
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{
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pic_irt_ehci0 = nlm_irtstart(nlm_get_usb_pcibase(nlm_nodeid(), 0));
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pic_irt_ehci1 = nlm_irtstart(nlm_get_usb_pcibase(nlm_nodeid(), 3));
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pic_irt_uart0 = nlm_irtstart(nlm_get_uart_pcibase(nlm_nodeid(), 0));
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pic_irt_uart1 = nlm_irtstart(nlm_get_uart_pcibase(nlm_nodeid(), 1));
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pic_irt_ehci0 = nlm_irtstart(nlm_get_usb_pcibase(node, 0));
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pic_irt_ehci1 = nlm_irtstart(nlm_get_usb_pcibase(node, 3));
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pic_irt_uart0 = nlm_irtstart(nlm_get_uart_pcibase(node, 0));
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pic_irt_uart1 = nlm_irtstart(nlm_get_uart_pcibase(node, 1));
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/* Hardcoding the PCIE IRT information as PIC doesn't
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understand any value other than 78,79,80,81 for PCIE0/1/2/3 */
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@ -107,24 +155,25 @@ int
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xlp_irt_to_irq(int irt)
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{
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if (irt == pic_irt_ehci0)
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return PIC_EHCI_0_IRQ;
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return PIC_EHCI_0_IRQ;
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else if (irt == pic_irt_ehci1)
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return PIC_EHCI_1_IRQ;
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return PIC_EHCI_1_IRQ;
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else if (irt == pic_irt_uart0)
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return PIC_UART_0_IRQ;
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return PIC_UART_0_IRQ;
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else if (irt == pic_irt_uart1)
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return PIC_UART_1_IRQ;
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return PIC_UART_1_IRQ;
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else if (irt == pic_irt_pcie_lnk0)
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return PIC_PCIE_0_IRQ;
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return PIC_PCIE_0_IRQ;
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else if (irt == pic_irt_pcie_lnk1)
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return PIC_PCIE_1_IRQ;
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return PIC_PCIE_1_IRQ;
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else if (irt == pic_irt_pcie_lnk2)
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return PIC_PCIE_2_IRQ;
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return PIC_PCIE_2_IRQ;
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else if (irt == pic_irt_pcie_lnk3)
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return PIC_PCIE_3_IRQ;
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return PIC_PCIE_3_IRQ;
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else {
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printf("Cannot find irq for IRT %d\n", irt);
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return 0;
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if (bootverbose)
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printf("Cannot find irq for IRT %d\n", irt);
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return 0;
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}
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}
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@ -156,15 +205,15 @@ int
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xlp_irq_is_picintr(int irq)
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{
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switch (irq) {
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case PIC_MMC_IRQ : return 1;
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case PIC_EHCI_0_IRQ : return 1;
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case PIC_EHCI_1_IRQ : return 1;
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case PIC_UART_0_IRQ : return 1;
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case PIC_UART_1_IRQ : return 1;
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case PIC_PCIE_0_IRQ : return 1;
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case PIC_PCIE_1_IRQ : return 1;
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case PIC_PCIE_2_IRQ : return 1;
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case PIC_PCIE_3_IRQ : return 1;
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default: return 0;
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case PIC_EHCI_0_IRQ :
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case PIC_EHCI_1_IRQ :
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case PIC_UART_0_IRQ :
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case PIC_UART_1_IRQ :
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case PIC_PCIE_0_IRQ :
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case PIC_PCIE_1_IRQ :
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case PIC_PCIE_2_IRQ :
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case PIC_PCIE_3_IRQ :
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return (1);
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default: return (0);
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}
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}
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@ -30,7 +30,7 @@
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*/
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#ifndef __NLM_HAL_SYS_H__
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#define __NLM_HAL_SYS_H__
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#define __NLM_HAL_SYS_H__
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/**
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* @file_name sys.h
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@ -121,5 +121,24 @@
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#define nlm_get_sys_pcibase(node) nlm_pcicfg_base(XLP_IO_SYS_OFFSET(node))
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#define nlm_get_sys_regbase(node) (nlm_get_sys_pcibase(node) + XLP_IO_PCI_HDRSZ)
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enum {
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/* Don't change order and it must start from zero */
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DFS_DEVICE_NAE = 0,
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DFS_DEVICE_SAE,
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DFS_DEVICE_RSA,
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DFS_DEVICE_DTRE,
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DFS_DEVICE_CMP,
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DFS_DEVICE_KBP,
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DFS_DEVICE_DMC,
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DFS_DEVICE_NAND,
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DFS_DEVICE_MMC,
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DFS_DEVICE_NOR,
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DFS_DEVICE_CORE,
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DFS_DEVICE_REGEX_SLOW,
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DFS_DEVICE_REGEX_FAST,
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DFS_DEVICE_SATA,
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INVALID_DFS_DEVICE = 0xFF
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};
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#endif
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#endif
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@ -34,21 +34,25 @@
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#include <mips/nlm/hal/mips-extns.h>
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#include <mips/nlm/hal/iomap.h>
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#define PIC_UART_0_IRQ 9
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#define PIC_UART_1_IRQ 10
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#define PIC_UART_0_IRQ 9
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#define PIC_UART_1_IRQ 10
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#define PIC_PCIE_0_IRQ 11
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#define PIC_PCIE_1_IRQ 12
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#define PIC_PCIE_2_IRQ 13
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#define PIC_PCIE_3_IRQ 14
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#define PIC_PCIE_0_IRQ 11
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#define PIC_PCIE_1_IRQ 12
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#define PIC_PCIE_2_IRQ 13
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#define PIC_PCIE_3_IRQ 14
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#define PIC_EHCI_0_IRQ 39
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/* 41 used by IRQ_SMP */
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#define PIC_EHCI_1_IRQ 42
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#define PIC_MMC_IRQ 43
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#define PIC_EHCI_0_IRQ 39
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#define PIC_EHCI_1_IRQ 42
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#define PIC_MMC_IRQ 43
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/* XLP 8xx/4xx A0, A1, A2 CPU COP0 PRIDs */
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#define CHIP_PROCESSOR_ID_XLP_8XX 0x10
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#define CHIP_PROCESSOR_ID_XLP_3XX 0x11
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#define CHIP_PROCESSOR_ID_XLP_416 0x94
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#define CHIP_PROCESSOR_ID_XLP_432 0x14
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/* Revision id's */
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#define XLP_REVISION_A0 0x00
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@ -69,24 +73,51 @@ extern int xlp_hwtid_to_cpuid[];
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#ifdef SMP
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extern void xlp_enable_threads(int code);
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#endif
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uint32_t xlp_get_cpu_frequency(int core);
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void nlm_pic_irt_init(void);
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uint32_t xlp_get_cpu_frequency(int node, int core);
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int nlm_set_device_frequency(int node, int devtype, int frequency);
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void nlm_pic_irt_init(int node);
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int xlp_irt_to_irq(int irt);
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int xlp_irq_to_irt(int irq);
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int xlp_irq_is_picintr(int irq);
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static __inline int nlm_processor_id(void)
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{
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return ((mips_rd_prid() >> 8) & 0xff);
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}
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static __inline int nlm_is_xlp3xx(void)
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{
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int prid = (mips_rd_prid() >> 8) & 0xff;
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return (prid == CHIP_PROCESSOR_ID_XLP_3XX);
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return (nlm_processor_id() == CHIP_PROCESSOR_ID_XLP_3XX);
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}
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static __inline int nlm_is_xlp4xx(void)
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{
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int prid = nlm_processor_id();
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return (prid == CHIP_PROCESSOR_ID_XLP_432 ||
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prid == CHIP_PROCESSOR_ID_XLP_416);
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}
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static __inline int nlm_is_xlp8xx(void)
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{
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int prid = (mips_rd_prid() >> 8) & 0xff;
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int prid = nlm_processor_id();
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return (prid == CHIP_PROCESSOR_ID_XLP_8XX);
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return (prid == CHIP_PROCESSOR_ID_XLP_8XX ||
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prid == CHIP_PROCESSOR_ID_XLP_432 ||
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prid == CHIP_PROCESSOR_ID_XLP_416);
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}
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static __inline int nlm_is_xlp8xx_ax(void)
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{
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uint32_t procid = mips_rd_prid();
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int prid = (procid >> 8) & 0xff;
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int rev = procid & 0xff;
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return ((prid == CHIP_PROCESSOR_ID_XLP_8XX ||
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prid == CHIP_PROCESSOR_ID_XLP_432 ||
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prid == CHIP_PROCESSOR_ID_XLP_416) &&
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(rev < XLP_REVISION_B0));
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}
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#endif /* LOCORE */
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@ -196,9 +196,15 @@ xlp_parse_mmu_options(void)
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goto unsupp;
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}
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/* Take out cores which do not exist on chip */
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/* Try to find the enabled cores from SYS block */
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sysbase = nlm_get_sys_regbase(0);
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cpu_rst_mask = nlm_read_sys_reg(sysbase, SYS_CPU_RESET) & 0xff;
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/* XLP 416 does not report this correctly, fix */
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if (nlm_processor_id() == CHIP_PROCESSOR_ID_XLP_416)
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cpu_rst_mask = 0xe;
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/* Take out cores which do not exist on chip */
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for (i = 1; i < XLP_MAX_CORES; i++) {
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if ((cpu_rst_mask & (1 << i)) == 0)
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cpu_map &= ~(0xfu << (4 * i));
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@ -515,12 +521,12 @@ platform_start(__register_t a0 __unused,
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/* initialize console so that we have printf */
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boothowto |= (RB_SERIAL | RB_MULTIPLE); /* Use multiple consoles */
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nlm_pic_irt_init(); /* complete before interrupts or console init */
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nlm_pic_irt_init(0); /* complete before interrupts or console init */
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init_static_kenv(boot1_env, sizeof(boot1_env));
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xlp_bootargs_init(a0);
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/* clockrate used by delay, so initialize it here */
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xlp_cpu_frequency = xlp_get_cpu_frequency(0);
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xlp_cpu_frequency = xlp_get_cpu_frequency(0, 0);
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cpu_clock = xlp_cpu_frequency / 1000000;
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mips_timer_early_init(xlp_cpu_frequency);
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