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https://github.com/opnsense/src.git
synced 2026-06-11 09:41:03 -04:00
Add in some AR9280 specific board configuration options.
* The existing radio config code was for the AR5416/AR9160 and missed out on some of the AR9280 specific stuff. Include said stuff from ath9k. * Refactor out the gain control settings into a new function, again pilfered from ath9k. * Use the analog register RMW macro when touching analog registers. Obtained from: Linux ath9k
This commit is contained in:
Adrian Chadd
parent
1a506b1a27
commit
8f6997190b
3 changed files with 119 additions and 39 deletions
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@ -180,7 +180,7 @@ ar5416Reset(struct ath_hal *ah, HAL_OPMODE opmode,
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val &= ~AR_PHY_RIFS_INIT_DELAY;
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OS_REG_WRITE(ah, AR_PHY_HEAVY_CLIP_FACTOR_RIFS, val);
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}
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AH5416(ah)->ah_writeIni(ah, chan);
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/* Setup 11n MAC/Phy mode registers */
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@ -1236,6 +1236,65 @@ ar5416InitPLL(struct ath_hal *ah, const struct ieee80211_channel *chan)
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OS_REG_WRITE(ah, AR_RTC_SLEEP_CLK, AR_RTC_SLEEP_DERIVED_CLK);
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}
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static void
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ar5416SetDefGainValues(struct ath_hal *ah,
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const MODAL_EEP_HEADER *pModal,
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const struct ar5416eeprom *eep,
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uint8_t txRxAttenLocal, int regChainOffset, int i)
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{
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if (IS_EEP_MINOR_V3(ah)) {
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txRxAttenLocal = pModal->txRxAttenCh[i];
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if (AR_SREV_MERLIN_20_OR_LATER(ah)) {
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OS_REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ + regChainOffset,
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AR_PHY_GAIN_2GHZ_XATTEN1_MARGIN,
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pModal->bswMargin[i]);
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OS_REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ + regChainOffset,
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AR_PHY_GAIN_2GHZ_XATTEN1_DB,
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pModal->bswAtten[i]);
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OS_REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ + regChainOffset,
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AR_PHY_GAIN_2GHZ_XATTEN2_MARGIN,
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pModal->xatten2Margin[i]);
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OS_REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ + regChainOffset,
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AR_PHY_GAIN_2GHZ_XATTEN2_DB,
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pModal->xatten2Db[i]);
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} else {
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OS_REG_WRITE(ah, AR_PHY_GAIN_2GHZ + regChainOffset,
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(OS_REG_READ(ah, AR_PHY_GAIN_2GHZ + regChainOffset) &
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~AR_PHY_GAIN_2GHZ_BSW_MARGIN)
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| SM(pModal-> bswMargin[i],
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AR_PHY_GAIN_2GHZ_BSW_MARGIN));
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OS_REG_WRITE(ah, AR_PHY_GAIN_2GHZ + regChainOffset,
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(OS_REG_READ(ah, AR_PHY_GAIN_2GHZ + regChainOffset) &
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~AR_PHY_GAIN_2GHZ_BSW_ATTEN)
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| SM(pModal->bswAtten[i],
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AR_PHY_GAIN_2GHZ_BSW_ATTEN));
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}
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}
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if (AR_SREV_MERLIN_20_OR_LATER(ah)) {
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OS_REG_RMW_FIELD(ah,
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AR_PHY_RXGAIN + regChainOffset,
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AR9280_PHY_RXGAIN_TXRX_ATTEN, txRxAttenLocal);
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OS_REG_RMW_FIELD(ah,
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AR_PHY_RXGAIN + regChainOffset,
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AR9280_PHY_RXGAIN_TXRX_MARGIN, pModal->rxTxMarginCh[i]);
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} else {
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OS_REG_WRITE(ah,
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AR_PHY_RXGAIN + regChainOffset,
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(OS_REG_READ(ah, AR_PHY_RXGAIN + regChainOffset) &
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~AR_PHY_RXGAIN_TXRX_ATTEN)
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| SM(txRxAttenLocal, AR_PHY_RXGAIN_TXRX_ATTEN));
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OS_REG_WRITE(ah,
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AR_PHY_GAIN_2GHZ + regChainOffset,
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(OS_REG_READ(ah, AR_PHY_GAIN_2GHZ + regChainOffset) &
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~AR_PHY_GAIN_2GHZ_RXTX_MARGIN) |
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SM(pModal->rxTxMarginCh[i], AR_PHY_GAIN_2GHZ_RXTX_MARGIN));
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}
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}
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/*
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* Read EEPROM header info and program the device for correct operation
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* given the channel value.
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@ -1272,6 +1331,7 @@ ar5416SetBoardValues(struct ath_hal *ah, const struct ieee80211_channel *chan)
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}
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OS_REG_WRITE(ah, AR_PHY_SWITCH_CHAIN_0 + regChainOffset, pModal->antCtrlChain[i]);
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OS_REG_WRITE(ah, AR_PHY_TIMING_CTRL4 + regChainOffset,
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(OS_REG_READ(ah, AR_PHY_TIMING_CTRL4 + regChainOffset) &
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~(AR_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF | AR_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF)) |
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@ -1283,21 +1343,34 @@ ar5416SetBoardValues(struct ath_hal *ah, const struct ieee80211_channel *chan)
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* XXX update
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*/
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if ((i == 0) || AR_SREV_OWL_20_OR_LATER(ah)) {
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OS_REG_WRITE(ah, AR_PHY_RXGAIN + regChainOffset,
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(OS_REG_READ(ah, AR_PHY_RXGAIN + regChainOffset) & ~AR_PHY_RXGAIN_TXRX_ATTEN) |
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SM(IS_EEP_MINOR_V3(ah) ? pModal->txRxAttenCh[i] : txRxAttenLocal,
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AR_PHY_RXGAIN_TXRX_ATTEN));
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if ((i == 0) || AR_SREV_OWL_20_OR_LATER(ah))
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ar5416SetDefGainValues(ah, pModal, eep, txRxAttenLocal, regChainOffset, i);
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OS_REG_WRITE(ah, AR_PHY_GAIN_2GHZ + regChainOffset,
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(OS_REG_READ(ah, AR_PHY_GAIN_2GHZ + regChainOffset) & ~AR_PHY_GAIN_2GHZ_RXTX_MARGIN) |
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SM(pModal->rxTxMarginCh[i], AR_PHY_GAIN_2GHZ_RXTX_MARGIN));
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}
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}
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if (AR_SREV_MERLIN_20_OR_LATER(ah)) {
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if (IEEE80211_IS_CHAN_2GHZ(chan)) {
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OS_A_REG_RMW_FIELD(ah, AR_AN_RF2G1_CH0, AR_AN_RF2G1_CH0_OB, pModal->ob);
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OS_A_REG_RMW_FIELD(ah, AR_AN_RF2G1_CH0, AR_AN_RF2G1_CH0_DB, pModal->db);
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OS_A_REG_RMW_FIELD(ah, AR_AN_RF2G1_CH1, AR_AN_RF2G1_CH1_OB, pModal->ob_ch1);
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OS_A_REG_RMW_FIELD(ah, AR_AN_RF2G1_CH1, AR_AN_RF2G1_CH1_DB, pModal->db_ch1);
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} else {
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OS_A_REG_RMW_FIELD(ah, AR_AN_RF5G1_CH0, AR_AN_RF5G1_CH0_OB5, pModal->ob);
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OS_A_REG_RMW_FIELD(ah, AR_AN_RF5G1_CH0, AR_AN_RF5G1_CH0_DB5, pModal->db);
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OS_A_REG_RMW_FIELD(ah, AR_AN_RF5G1_CH1, AR_AN_RF5G1_CH1_OB5, pModal->ob_ch1);
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OS_A_REG_RMW_FIELD(ah, AR_AN_RF5G1_CH1, AR_AN_RF5G1_CH1_DB5, pModal->db_ch1);
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}
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OS_A_REG_RMW_FIELD(ah, AR_AN_TOP2, AR_AN_TOP2_XPABIAS_LVL, pModal->xpaBiasLvl);
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OS_A_REG_RMW_FIELD(ah, AR_AN_TOP2, AR_AN_TOP2_LOCALBIAS, pModal->flagBits & AR5416_EEP_FLAG_LOCALBIAS);
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OS_A_REG_RMW_FIELD(ah, AR_PHY_XPA_CFG, AR_PHY_FORCE_XPA_CFG, pModal->flagBits & AR5416_EEP_FLAG_FORCEXPAON);
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}
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OS_REG_RMW_FIELD(ah, AR_PHY_SETTLING, AR_PHY_SETTLING_SWITCH, pModal->switchSettling);
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OS_REG_RMW_FIELD(ah, AR_PHY_DESIRED_SZ, AR_PHY_DESIRED_SZ_ADC, pModal->adcDesiredSize);
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OS_REG_RMW_FIELD(ah, AR_PHY_DESIRED_SZ, AR_PHY_DESIRED_SZ_PGA, pModal->pgaDesiredSize);
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if (! AR_SREV_MERLIN_20_OR_LATER(ah))
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OS_REG_RMW_FIELD(ah, AR_PHY_DESIRED_SZ, AR_PHY_DESIRED_SZ_PGA, pModal->pgaDesiredSize);
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OS_REG_WRITE(ah, AR_PHY_RF_CTL4,
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SM(pModal->txEndToXpaOff, AR_PHY_RF_CTL4_TX_END_XPAA_OFF)
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| SM(pModal->txEndToXpaOff, AR_PHY_RF_CTL4_TX_END_XPAB_OFF)
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@ -1323,37 +1396,26 @@ ar5416SetBoardValues(struct ath_hal *ah, const struct ieee80211_channel *chan)
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OS_REG_RMW_FIELD(ah, AR_PHY_RF_CTL2, AR_PHY_TX_FRAME_TO_DATA_START, pModal->txFrameToDataStart);
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OS_REG_RMW_FIELD(ah, AR_PHY_RF_CTL2, AR_PHY_TX_FRAME_TO_PA_ON, pModal->txFrameToPaOn);
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}
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if (IS_EEP_MINOR_V3(ah)) {
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if (IEEE80211_IS_CHAN_HT40(chan)) {
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if (IS_EEP_MINOR_V3(ah) && IEEE80211_IS_CHAN_HT40(chan))
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/* Overwrite switch settling with HT40 value */
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OS_REG_RMW_FIELD(ah, AR_PHY_SETTLING, AR_PHY_SETTLING_SWITCH, pModal->swSettleHt40);
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}
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if ((AR_SREV_OWL_20_OR_LATER(ah)) &&
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( AH5416(ah)->ah_rx_chainmask == 0x5 || AH5416(ah)->ah_tx_chainmask == 0x5)){
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/* Reg Offsets are swapped for logical mapping */
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OS_REG_WRITE(ah, AR_PHY_GAIN_2GHZ + 0x1000, (OS_REG_READ(ah, AR_PHY_GAIN_2GHZ + 0x1000) & ~AR_PHY_GAIN_2GHZ_BSW_MARGIN) |
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SM(pModal->bswMargin[2], AR_PHY_GAIN_2GHZ_BSW_MARGIN));
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OS_REG_WRITE(ah, AR_PHY_GAIN_2GHZ + 0x1000, (OS_REG_READ(ah, AR_PHY_GAIN_2GHZ + 0x1000) & ~AR_PHY_GAIN_2GHZ_BSW_ATTEN) |
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SM(pModal->bswAtten[2], AR_PHY_GAIN_2GHZ_BSW_ATTEN));
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OS_REG_WRITE(ah, AR_PHY_GAIN_2GHZ + 0x2000, (OS_REG_READ(ah, AR_PHY_GAIN_2GHZ + 0x2000) & ~AR_PHY_GAIN_2GHZ_BSW_MARGIN) |
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SM(pModal->bswMargin[1], AR_PHY_GAIN_2GHZ_BSW_MARGIN));
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OS_REG_WRITE(ah, AR_PHY_GAIN_2GHZ + 0x2000, (OS_REG_READ(ah, AR_PHY_GAIN_2GHZ + 0x2000) & ~AR_PHY_GAIN_2GHZ_BSW_ATTEN) |
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SM(pModal->bswAtten[1], AR_PHY_GAIN_2GHZ_BSW_ATTEN));
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} else {
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OS_REG_WRITE(ah, AR_PHY_GAIN_2GHZ + 0x1000, (OS_REG_READ(ah, AR_PHY_GAIN_2GHZ + 0x1000) & ~AR_PHY_GAIN_2GHZ_BSW_MARGIN) |
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SM(pModal->bswMargin[1], AR_PHY_GAIN_2GHZ_BSW_MARGIN));
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OS_REG_WRITE(ah, AR_PHY_GAIN_2GHZ + 0x1000, (OS_REG_READ(ah, AR_PHY_GAIN_2GHZ + 0x1000) & ~AR_PHY_GAIN_2GHZ_BSW_ATTEN) |
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SM(pModal->bswAtten[1], AR_PHY_GAIN_2GHZ_BSW_ATTEN));
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OS_REG_WRITE(ah, AR_PHY_GAIN_2GHZ + 0x2000, (OS_REG_READ(ah, AR_PHY_GAIN_2GHZ + 0x2000) & ~AR_PHY_GAIN_2GHZ_BSW_MARGIN) |
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SM(pModal->bswMargin[2],AR_PHY_GAIN_2GHZ_BSW_MARGIN));
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OS_REG_WRITE(ah, AR_PHY_GAIN_2GHZ + 0x2000, (OS_REG_READ(ah, AR_PHY_GAIN_2GHZ + 0x2000) & ~AR_PHY_GAIN_2GHZ_BSW_ATTEN) |
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SM(pModal->bswAtten[2], AR_PHY_GAIN_2GHZ_BSW_ATTEN));
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if (AR_SREV_MERLIN_20_OR_LATER(ah) && EEP_MINOR(ah) >= AR5416_EEP_MINOR_VER_19)
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OS_REG_RMW_FIELD(ah, AR_PHY_CCK_TX_CTRL, AR_PHY_CCK_TX_CTRL_TX_DAC_SCALE_CCK, pModal->miscBits);
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if (AR_SREV_MERLIN_20(ah) && EEP_MINOR(ah) >= AR5416_EEP_MINOR_VER_20) {
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if (IEEE80211_IS_CHAN_2GHZ(chan))
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OS_A_REG_RMW_FIELD(ah, AR_AN_TOP1, AR_AN_TOP1_DACIPMODE, eep->baseEepHeader.dacLpMode);
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else if (eep->baseEepHeader.dacHiPwrMode_5G)
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OS_A_REG_RMW_FIELD(ah, AR_AN_TOP1, AR_AN_TOP1_DACIPMODE, 0);
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else
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OS_A_REG_RMW_FIELD(ah, AR_AN_TOP1, AR_AN_TOP1_DACIPMODE, eep->baseEepHeader.dacLpMode);
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OS_REG_RMW_FIELD(ah, AR_PHY_FRAME_CTL, AR_PHY_FRAME_CTL_TX_CLIP, pModal->miscBits >> 2);
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OS_REG_RMW_FIELD(ah, AR_PHY_TX_PWRCTRL9, AR_PHY_TX_DESIRED_SCALE_CCK, eep->baseEepHeader.desiredScaleCCK);
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}
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OS_REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ, AR_PHY_GAIN_2GHZ_BSW_MARGIN, pModal->bswMargin[0]);
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OS_REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ, AR_PHY_GAIN_2GHZ_BSW_ATTEN, pModal->bswAtten[0]);
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}
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return AH_TRUE;
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}
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@ -278,4 +278,18 @@
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#define AR_PHY_CCA_MAX_GOOD_VAL_5416_2GHZ -80
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#define AR_PHY_CCA_MAX_GOOD_VAL_5416_5GHZ -90
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/* ar9280 specific? */
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#define AR_PHY_XPA_CFG 0xA3D8
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#define AR_PHY_FORCE_XPA_CFG 0x000000001
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#define AR_PHY_FORCE_XPA_CFG_S 0
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#define AR_PHY_CCK_TX_CTRL_TX_DAC_SCALE_CCK 0x0000000C
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#define AR_PHY_CCK_TX_CTRL_TX_DAC_SCALE_CCK_S 2
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#define AR_PHY_TX_PWRCTRL9 0xa27C
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#define AR_PHY_TX_DESIRED_SCALE_CCK 0x00007C00
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#define AR_PHY_TX_DESIRED_SCALE_CCK_S 10
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#define AR_PHY_TX_PWRCTRL9_RES_DC_REMOVAL 0x80000000
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#define AR_PHY_TX_PWRCTRL9_RES_DC_REMOVAL_S 31
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#endif /* _DEV_ATH_AR5416PHY_H_ */
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@ -365,6 +365,10 @@
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#define AR_AN_RF5G1_CH1_DB5 0x00380000
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#define AR_AN_RF5G1_CH1_DB5_S 19
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#define AR_AN_TOP1 0x7890
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#define AR_AN_TOP1_DACIPMODE 0x00040000
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#define AR_AN_TOP1_DACIPMODE_S 18
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#define AR_AN_TOP2_XPABIAS_LVL 0xC0000000
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#define AR_AN_TOP2_XPABIAS_LVL_S 30
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#define AR_AN_TOP2_LOCALBIAS 0x00200000
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