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https://github.com/opnsense/src.git
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Save a few cycles in context switch.
Update comments to reflect reality.
This commit is contained in:
Olivier Houchard
parent
90f794aaaf
commit
8ecf6f65d9
1 changed files with 36 additions and 90 deletions
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@ -78,12 +78,13 @@
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*
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*/
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#include "assym.s"
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#include <machine/asm.h>
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#include <machine/asmacros.h>
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#include <machine/armreg.h>
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__FBSDID("$FreeBSD$");
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#include "assym.s"
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/*
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* New experimental definitions of IRQdisable and IRQenable
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@ -118,8 +119,6 @@ __FBSDID("$FreeBSD$");
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bic r14, r14, #(I32_bit | F32_bit) ; \
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msr cpsr_c, r14
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.Lpcpu:
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.word _C_LABEL(__pcpu)
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.Lcurpcb:
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.word _C_LABEL(__pcpu) + PC_CURPCB
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.Lcpufuncs:
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@ -130,35 +129,22 @@ __FBSDID("$FreeBSD$");
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.word _C_LABEL(cpu_do_powersave)
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ENTRY(cpu_throw)
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mov r4, r0
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ldr r0, .Lcurthread
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mov r5, r1
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/*
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* r4 = lwp
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* r5 = lwp0
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* r4 = oldtd
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* r5 = newtd
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*/
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mov r2, #0x00000000 /* curthread = NULL */
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str r2, [r0]
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/*
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* We're about to clear both the cache and the TLB.
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* Make sure to zap the 'last cache state' pointer since the
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* pmap might be about to go away. Also ensure the outgoing
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* VM space's cache state is marked as NOT resident in the
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* cache, and that lwp0's cache state IS resident.
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*/
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ldr r7, [r4, #(TD_PCB)] /* r7 = old lwp's PCB */
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ldr r7, [r5, #(TD_PCB)] /* r7 = new thread's PCB */
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/* Switch to lwp0 context */
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ldr r9, .Lcpufuncs
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mov lr, pc
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ldr pc, [r9, #CF_IDCACHE_WBINV_ALL]
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ldr r0, [r7, #(PCB_PL1VEC)]
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ldr r1, [r7, #(PCB_DACR)]
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/*
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* r0 = Pointer to L1 slot for vector_page (or NULL)
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* r1 = lwp0's DACR
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@ -201,8 +187,6 @@ ENTRY(cpu_throw)
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mov lr, pc
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ldr pc, [r9, #CF_CONTEXT_SWITCH]
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ldr r0, .Lcurpcb
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/* Restore all the save registers */
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#ifndef __XSCALE__
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add r1, r7, #PCB_R8
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@ -215,46 +199,35 @@ ENTRY(cpu_throw)
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ldr r12, [r7, #(PCB_R12)]
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ldr r13, [r7, #(PCB_SP)]
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#endif
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str r7, [r0] /* curpcb = lwp0's PCB */
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mov r1, #0x00000000 /* r5 = old lwp = NULL */
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mov r6, r5
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mov r0, #0x00000000 /* r5 = old lwp = NULL */
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mov r1, r5
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b .Lswitch_resume
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ENTRY(cpu_switch)
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stmfd sp!, {r4-r7, lr}
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mov r6, r1
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mov r1, r0
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.Lswitch_resume:
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/* rem: r1 = old lwp */
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/* rem: r4 = return value [not used if came from cpu_switchto()] */
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/* rem: r6 = new process */
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/* rem: r0 = old lwp */
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/* rem: interrupts are disabled */
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#ifdef MULTIPROCESSOR
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/* XXX use curcpu() */
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ldr r0, .Lcpu_info_store
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str r0, [r6, #(L_CPU)]
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ldr r2, .Lcpu_info_store
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str r2, [r6, #(L_CPU)]
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#endif
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/* Process is now on a processor. */
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/* We have a new curthread now so make a note it */
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ldr r7, .Lcurthread
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str r6, [r7]
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str r1, [r7]
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/* Hook in a new pcb */
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ldr r7, .Lcurpcb
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ldr r0, [r6, #(TD_PCB)]
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str r0, [r7]
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ldr r2, [r1, #TD_PCB]
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str r2, [r7]
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/* rem: r1 = old lwp */
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/* rem: r4 = return value */
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/* rem: r6 = new process */
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/* Remember the old thread in r0 */
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mov r0, r1
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/*
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* If the old lwp on entry to cpu_switch was zero then the
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@ -263,26 +236,24 @@ ENTRY(cpu_switch)
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* straight to restoring the context for the new process.
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*/
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teq r0, #0x00000000
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beq .Lswitch_exited
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beq .Lswitch_return
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/* rem: r0 = old lwp */
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/* rem: r4 = return value */
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/* rem: r6 = new process */
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/* rem: r1 = new process */
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/* rem: interrupts are enabled */
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/* Stage two : Save old context */
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/* Get the user structure for the old lwp. */
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ldr r1, [r0, #(TD_PCB)]
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ldr r2, [r0, #(TD_PCB)]
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/* Save all the registers in the old lwp's pcb */
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#ifndef __XSCALE__
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add r7, r1, #(PCB_R8)
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add r7, r2, #(PCB_R8)
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stmia r7, {r8-r13}
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#else
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strd r8, [r1, #(PCB_R8)]
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strd r10, [r1, #(PCB_R10)]
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strd r12, [r1, #(PCB_R12)]
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strd r8, [r2, #(PCB_R8)]
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strd r10, [r2, #(PCB_R10)]
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strd r12, [r2, #(PCB_R12)]
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#endif
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/*
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@ -291,12 +262,13 @@ ENTRY(cpu_switch)
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*/
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/* Remember the old PCB. */
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mov r8, r1
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mov r8, r2
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/* r1 now free! */
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/* Get the user structure for the new process in r9 */
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ldr r9, [r6, #(TD_PCB)]
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ldr r9, [r1, #(TD_PCB)]
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/* r1 now free! */
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/*
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* This can be optimised... We know we want to go from SVC32
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@ -310,9 +282,6 @@ ENTRY(cpu_switch)
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str sp, [r8, #(PCB_UND_SP)]
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msr cpsr_c, r3 /* Restore the old mode */
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/* rem: r0 = old lwp */
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/* rem: r4 = return value */
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/* rem: r6 = new process */
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/* rem: r8 = old PCB */
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/* rem: r9 = new PCB */
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/* rem: interrupts are enabled */
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@ -321,9 +290,6 @@ ENTRY(cpu_switch)
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/* Third phase : restore saved context */
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/* rem: r0 = old lwp */
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/* rem: r4 = return value */
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/* rem: r6 = new lwp */
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/* rem: r8 = old PCB */
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/* rem: r9 = new PCB */
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/* rem: interrupts are enabled */
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@ -342,16 +308,18 @@ ENTRY(cpu_switch)
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ldr r0, [r8, #(PCB_DACR)] /* r0 = old DACR */
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ldr r1, [r9, #(PCB_DACR)] /* r1 = new DACR */
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ldr r5, [r9, #(PCB_DACR)] /* r1 = new DACR */
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teq r10, r11 /* Same L1? */
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cmpeq r0, r1 /* Same DACR? */
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cmpeq r0, r5 /* Same DACR? */
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beq .Lcs_context_switched /* yes! */
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ldr r3, .Lblock_userspace_access
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ldr r4, .Lblock_userspace_access
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mov r2, #DOMAIN_CLIENT
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cmp r1, r2, lsl #(PMAP_DOMAIN_KERNEL * 2) /* Sw to kernel thread? */
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beq .Lcs_cache_purge_skipped /* Yup. Don't flush cache */
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mov r2, #DOMAIN_CLIENT
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cmp r5, r2, lsl #(PMAP_DOMAIN_KERNEL * 2) /* Sw to kernel thread? */
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beq .Lcs_cache_purge_skipped /* Yup. Don't flush cache */
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/*
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* Definately need to flush the cache.
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*/
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@ -360,17 +328,13 @@ ENTRY(cpu_switch)
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* Don't allow user space access between the purge and the switch.
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*/
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mov r2, #0x00000001
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str r2, [r3]
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str r2, [r4]
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stmfd sp!, {r0-r3}
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ldr r1, .Lcpufuncs
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mov lr, pc
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ldr pc, [r1, #CF_IDCACHE_WBINV_ALL]
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ldmfd sp!, {r0-r3}
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.Lcs_cache_purge_skipped:
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/* rem: r1 = new DACR */
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/* rem: r3 = &block_userspace_access */
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/* rem: r4 = return value */
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/* rem: r4 = &block_userspace_access */
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/* rem: r6 = new lwp */
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/* rem: r9 = new PCB */
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/* rem: r10 = old L1 */
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@ -384,7 +348,7 @@ ENTRY(cpu_switch)
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* as none will occur until interrupts are re-enabled after the
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* switch.
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*/
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str r2, [r3]
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str r2, [r4]
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/*
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* Ensure the vector table is accessible by fixing up the L1
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@ -392,7 +356,7 @@ ENTRY(cpu_switch)
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cmp r7, #0 /* No need to fixup vector table? */
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ldrne r2, [r7] /* But if yes, fetch current value */
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ldrne r0, [r9, #(PCB_L1VEC)] /* Fetch new vector_page value */
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mcr p15, 0, r1, c3, c0, 0 /* Update DACR for new context */
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mcr p15, 0, r5, c3, c0, 0 /* Update DACR for new context */
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cmpne r2, r0 /* Stuffing the same value? */
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#ifndef PMAP_INCLUDE_PTE_SYNC
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strne r0, [r7] /* Nope, update it */
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@ -440,8 +404,6 @@ ENTRY(cpu_switch)
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/* XXXSCW: Safe to re-enable FIQs here */
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/* rem: r4 = return value */
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/* rem: r6 = new lwp */
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/* rem: r9 = new PCB */
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/*
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@ -471,8 +433,6 @@ ENTRY(cpu_switch)
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ldr r13, [r7, #(PCB_SP)]
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#endif
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/* rem: r4 = return value */
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/* rem: r5 = new lwp's proc */
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/* rem: r6 = new lwp */
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/* rem: r7 = new pcb */
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@ -482,7 +442,6 @@ ENTRY(cpu_switch)
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bl _C_LABEL(arm_fpe_core_changecontext)
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#endif
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/* rem: r4 = return value */
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/* rem: r5 = new lwp's proc */
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/* rem: r6 = new lwp */
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/* rem: r7 = new PCB */
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@ -494,19 +453,6 @@ ENTRY(cpu_switch)
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* cpu_switch() was called and return.
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*/
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ldmfd sp!, {r4-r7, pc}
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.Lswitch_exited:
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/*
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* We skip the cache purge because cpu_throw() already did it.
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* Load up registers the way .Lcs_cache_purge_skipped expects.
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* Userspace access already blocked by cpu_throw().
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*/
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ldr r9, [r6, #(TD_PCB)] /* r9 = new PCB */
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ldr r3, .Lblock_userspace_access
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mrc p15, 0, r10, c2, c0, 0 /* r10 = old L1 */
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mov r5, #0 /* No previous cache state */
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ldr r1, [r9, #(PCB_DACR)] /* r1 = new DACR */
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ldr r11, [r9, #(PCB_PAGEDIR)] /* r11 = new L1 */
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b .Lcs_cache_purge_skipped
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#ifdef DIAGNOSTIC
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.Lswitch_bogons:
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adr r0, .Lswitch_panic_str
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