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Revert part of rev 1.230 and assume that all EISA IRQs use active high

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polarity rather than assuming that level triggered IRQs use active low and
edge triggered IRQs use active high.  Both the MultiProcessor 1.4
and ACPI 2.0 Specifications state in their examples that level triggered
EISA IRQs are active low, but in practice they seem to be active high.

Reported by:	Nik Azim Azam nskyline_r35 at yahoo dot com
This commit is contained in:
John Baldwin 2004-05-24 15:51:46 +00:00
parent 5f3ba2f5d4
commit 87ca48b6b8
1 changed files with 1 additions and 8 deletions
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9
sys/i386/i386/mptable.c
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@ -549,17 +549,10 @@ conforming_polarity(u_char src_bus, u_char src_bus_irq)
KASSERT(src_bus <= mptable_maxbusid, ("bus id %d too large", src_bus));
switch (busses[src_bus].bus_type) {
case ISA:
case EISA:
return (INTR_POLARITY_HIGH);
case PCI:
return (INTR_POLARITY_LOW);
#ifndef PC98
case EISA:
KASSERT(src_bus_irq < 16, ("Invalid EISA IRQ %d", src_bus_irq));
if (elcr_read_trigger(src_bus_irq) == INTR_TRIGGER_LEVEL)
return (INTR_POLARITY_LOW);
else
return (INTR_POLARITY_HIGH);
#endif
default:
panic("%s: unknown bus type %d", __func__,
busses[src_bus].bus_type);