From c7a3c7298ff5bdae6341330a1d94ab10e010beac Mon Sep 17 00:00:00 2001 From: Emmanuel Vadot Date: Thu, 1 Jul 2021 17:39:42 +0200 Subject: [PATCH] Import device-tree files from Linux 5.12 --- Bindings/hwmon/ntc_thermistor.txt | 2 +- Bindings/i2c/i2c-gpio.yaml | 2 +- Bindings/i2c/i2c-imx.yaml | 2 +- Bindings/iio/adc/ingenic,adc.yaml | 5 +- Bindings/input/adc-joystick.yaml | 4 +- .../input/touchscreen/resistive-adc-touch.txt | 5 +- Bindings/leds/cznic,turris-omnia-leds.yaml | 2 +- Bindings/mfd/ab8500.txt | 4 +- Bindings/mfd/motorola-cpcap.txt | 16 ++-- Bindings/net/brcm,bcm4908-enet.yaml | 2 +- Bindings/net/ethernet-controller.yaml | 2 +- Bindings/net/micrel-ksz90x1.txt | 96 ++++++++++++++++++- include/dt-bindings/bus/moxtet.h | 2 +- src/arc/haps_hs.dts | 2 +- src/arm/am33xx.dtsi | 3 + src/arm/armada-385-turris-omnia.dts | 4 +- src/arm/at91-sam9x60ek.dts | 8 -- src/arm/at91-sama5d27_som1.dtsi | 4 +- src/arm/bcm2711.dtsi | 12 --- src/arm/imx6qdl-phytec-pfla02.dtsi | 2 + src/arm/imx6ul-14x14-evk.dtsi | 22 +++-- src/arm/imx6ull-myir-mys-6ulx-eval.dts | 1 + src/arm/omap3.dtsi | 3 + src/arm/omap4.dtsi | 5 + src/arm/omap44xx-clocks.dtsi | 8 -- src/arm/omap5.dtsi | 5 + src/arm/sam9x60.dtsi | 9 ++ src/arm64/allwinner/sun50i-a64-pine64-lts.dts | 4 + src/arm64/allwinner/sun50i-a64-sopine.dtsi | 2 +- src/arm64/allwinner/sun50i-h6-beelink-gs1.dts | 4 - src/arm64/allwinner/sun50i-h6.dtsi | 4 +- src/arm64/freescale/fsl-ls1012a.dtsi | 1 + src/arm64/freescale/fsl-ls1043a.dtsi | 1 + src/arm64/freescale/fsl-ls1046a.dtsi | 1 + src/arm64/freescale/imx8mm-pinfunc.h | 2 +- .../freescale/imx8mp-phyboard-pollux-rdk.dts | 2 +- src/arm64/freescale/imx8mp-phycore-som.dtsi | 2 +- src/arm64/freescale/imx8mq-pinfunc.h | 2 +- src/arm64/marvell/armada-3720-turris-mox.dts | 2 +- src/arm64/marvell/armada-cp11x.dtsi | 6 +- src/arm64/nvidia/tegra186-p2771-0000.dts | 2 +- src/arm64/nvidia/tegra186-p3310.dtsi | 2 +- src/arm64/nvidia/tegra186.dtsi | 2 +- src/arm64/nvidia/tegra194-p2972-0000.dts | 3 +- src/arm64/nvidia/tegra194-p3668-0000.dtsi | 4 + src/arm64/nvidia/tegra194-p3668-0001.dtsi | 4 + src/arm64/nvidia/tegra194-p3668.dtsi | 1 - 47 files changed, 203 insertions(+), 80 deletions(-) diff --git a/Bindings/hwmon/ntc_thermistor.txt b/Bindings/hwmon/ntc_thermistor.txt index 37f18d684f6..4c5c3712970 100644 --- a/Bindings/hwmon/ntc_thermistor.txt +++ b/Bindings/hwmon/ntc_thermistor.txt @@ -32,7 +32,7 @@ Optional node properties: - "#thermal-sensor-cells" Used to expose itself to thermal fw. Read more about iio bindings at - Documentation/devicetree/bindings/iio/iio-bindings.txt + https://github.com/devicetree-org/dt-schema/blob/master/schemas/iio/ Example: ncp15wb473@0 { diff --git a/Bindings/i2c/i2c-gpio.yaml b/Bindings/i2c/i2c-gpio.yaml index ff99344788a..fd040284561 100644 --- a/Bindings/i2c/i2c-gpio.yaml +++ b/Bindings/i2c/i2c-gpio.yaml @@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: Bindings for GPIO bitbanged I2C maintainers: - - Wolfram Sang + - Wolfram Sang allOf: - $ref: /schemas/i2c/i2c-controller.yaml# diff --git a/Bindings/i2c/i2c-imx.yaml b/Bindings/i2c/i2c-imx.yaml index f23966b0d6c..3592d49235e 100644 --- a/Bindings/i2c/i2c-imx.yaml +++ b/Bindings/i2c/i2c-imx.yaml @@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: Freescale Inter IC (I2C) and High Speed Inter IC (HS-I2C) for i.MX maintainers: - - Wolfram Sang + - Oleksij Rempel allOf: - $ref: /schemas/i2c/i2c-controller.yaml# diff --git a/Bindings/iio/adc/ingenic,adc.yaml b/Bindings/iio/adc/ingenic,adc.yaml index 9f414dbdae8..433a3fb55a2 100644 --- a/Bindings/iio/adc/ingenic,adc.yaml +++ b/Bindings/iio/adc/ingenic,adc.yaml @@ -14,8 +14,9 @@ description: > Industrial I/O subsystem bindings for ADC controller found in Ingenic JZ47xx SoCs. - ADC clients must use the format described in iio-bindings.txt, giving - a phandle and IIO specifier pair ("io-channels") to the ADC controller. + ADC clients must use the format described in + https://github.com/devicetree-org/dt-schema/blob/master/schemas/iio/iio-consumer.yaml, + giving a phandle and IIO specifier pair ("io-channels") to the ADC controller. properties: compatible: diff --git a/Bindings/input/adc-joystick.yaml b/Bindings/input/adc-joystick.yaml index 054406bbd22..721878d5b7a 100644 --- a/Bindings/input/adc-joystick.yaml +++ b/Bindings/input/adc-joystick.yaml @@ -24,7 +24,9 @@ properties: description: > List of phandle and IIO specifier pairs. Each pair defines one ADC channel to which a joystick axis is connected. - See Documentation/devicetree/bindings/iio/iio-bindings.txt for details. + See + https://github.com/devicetree-org/dt-schema/blob/master/schemas/iio/iio-consumer.yaml + for details. '#address-cells': const: 1 diff --git a/Bindings/input/touchscreen/resistive-adc-touch.txt b/Bindings/input/touchscreen/resistive-adc-touch.txt index 51456c0e9a2..af5223bb5bd 100644 --- a/Bindings/input/touchscreen/resistive-adc-touch.txt +++ b/Bindings/input/touchscreen/resistive-adc-touch.txt @@ -5,7 +5,10 @@ Required properties: - compatible: must be "resistive-adc-touch" The device must be connected to an ADC device that provides channels for position measurement and optional pressure. -Refer to ../iio/iio-bindings.txt for details +Refer to +https://github.com/devicetree-org/dt-schema/blob/master/schemas/iio/iio-consumer.yaml +for details + - iio-channels: must have at least two channels connected to an ADC device. These should correspond to the channels exposed by the ADC device and should have the right index as the ADC device registers them. These channels diff --git a/Bindings/leds/cznic,turris-omnia-leds.yaml b/Bindings/leds/cznic,turris-omnia-leds.yaml index fe7fa25877f..c7ed2871da0 100644 --- a/Bindings/leds/cznic,turris-omnia-leds.yaml +++ b/Bindings/leds/cznic,turris-omnia-leds.yaml @@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: CZ.NIC's Turris Omnia LEDs driver maintainers: - - Marek Behún + - Marek Behún description: This module adds support for the RGB LEDs found on the front panel of the diff --git a/Bindings/mfd/ab8500.txt b/Bindings/mfd/ab8500.txt index d2a6e835c25..937b3e5505e 100644 --- a/Bindings/mfd/ab8500.txt +++ b/Bindings/mfd/ab8500.txt @@ -72,7 +72,9 @@ Required child device properties: pwm|regulator|rtc|sysctrl|usb]"; A few child devices require ADC channels from the GPADC node. Those follow the - standard bindings from iio/iio-bindings.txt and iio/adc/adc.txt + standard bindings from + https://github.com/devicetree-org/dt-schema/blob/master/schemas/iio/iio-consumer.yaml + and Documentation/devicetree/bindings/iio/adc/adc.yaml abx500-temp : io-channels "aux1" and "aux2" for measuring external temperatures. diff --git a/Bindings/mfd/motorola-cpcap.txt b/Bindings/mfd/motorola-cpcap.txt index 5ddcc8f4feb..b52e7a33f0f 100644 --- a/Bindings/mfd/motorola-cpcap.txt +++ b/Bindings/mfd/motorola-cpcap.txt @@ -16,14 +16,14 @@ Optional subnodes: The sub-functions of CPCAP get their own node with their own compatible values, which are described in the following files: -- ../power/supply/cpcap-battery.txt -- ../power/supply/cpcap-charger.txt -- ../regulator/cpcap-regulator.txt -- ../phy/phy-cpcap-usb.txt -- ../input/cpcap-pwrbutton.txt -- ../rtc/cpcap-rtc.txt -- ../leds/leds-cpcap.txt -- ../iio/adc/cpcap-adc.txt +- Documentation/devicetree/bindings/power/supply/cpcap-battery.txt +- Documentation/devicetree/bindings/power/supply/cpcap-charger.txt +- Documentation/devicetree/bindings/regulator/cpcap-regulator.txt +- Documentation/devicetree/bindings/phy/phy-cpcap-usb.txt +- Documentation/devicetree/bindings/input/cpcap-pwrbutton.txt +- Documentation/devicetree/bindings/rtc/cpcap-rtc.txt +- Documentation/devicetree/bindings/leds/leds-cpcap.txt +- Documentation/devicetree/bindings/iio/adc/motorola,cpcap-adc.yaml The only exception is the audio codec. Instead of a compatible value its node must be named "audio-codec". diff --git a/Bindings/net/brcm,bcm4908-enet.yaml b/Bindings/net/brcm,bcm4908-enet.yaml index 79c38ea1423..13c26f23a82 100644 --- a/Bindings/net/brcm,bcm4908-enet.yaml +++ b/Bindings/net/brcm,bcm4908-enet.yaml @@ -32,7 +32,7 @@ required: - interrupts - interrupt-names -additionalProperties: false +unevaluatedProperties: false examples: - | diff --git a/Bindings/net/ethernet-controller.yaml b/Bindings/net/ethernet-controller.yaml index 4b7d1e5d003..e8f04687a3e 100644 --- a/Bindings/net/ethernet-controller.yaml +++ b/Bindings/net/ethernet-controller.yaml @@ -49,7 +49,7 @@ properties: description: Reference to an nvmem node for the MAC address - nvmem-cells-names: + nvmem-cell-names: const: mac-address phy-connection-type: diff --git a/Bindings/net/micrel-ksz90x1.txt b/Bindings/net/micrel-ksz90x1.txt index b921731cd97..df9e844dd6b 100644 --- a/Bindings/net/micrel-ksz90x1.txt +++ b/Bindings/net/micrel-ksz90x1.txt @@ -65,6 +65,71 @@ KSZ9031: step is 60ps. The default value is the neutral setting, so setting rxc-skew-ps=<0> actually results in -900 picoseconds adjustment. + The KSZ9031 hardware supports a range of skew values from negative to + positive, where the specific range is property dependent. All values + specified in the devicetree are offset by the minimum value so they + can be represented as positive integers in the devicetree since it's + difficult to represent a negative number in the devictree. + + The following 5-bit values table apply to rxc-skew-ps and txc-skew-ps. + + Pad Skew Value Delay (ps) Devicetree Value + ------------------------------------------------------ + 0_0000 -900ps 0 + 0_0001 -840ps 60 + 0_0010 -780ps 120 + 0_0011 -720ps 180 + 0_0100 -660ps 240 + 0_0101 -600ps 300 + 0_0110 -540ps 360 + 0_0111 -480ps 420 + 0_1000 -420ps 480 + 0_1001 -360ps 540 + 0_1010 -300ps 600 + 0_1011 -240ps 660 + 0_1100 -180ps 720 + 0_1101 -120ps 780 + 0_1110 -60ps 840 + 0_1111 0ps 900 + 1_0000 60ps 960 + 1_0001 120ps 1020 + 1_0010 180ps 1080 + 1_0011 240ps 1140 + 1_0100 300ps 1200 + 1_0101 360ps 1260 + 1_0110 420ps 1320 + 1_0111 480ps 1380 + 1_1000 540ps 1440 + 1_1001 600ps 1500 + 1_1010 660ps 1560 + 1_1011 720ps 1620 + 1_1100 780ps 1680 + 1_1101 840ps 1740 + 1_1110 900ps 1800 + 1_1111 960ps 1860 + + The following 4-bit values table apply to the txdX-skew-ps, rxdX-skew-ps + data pads, and the rxdv-skew-ps, txen-skew-ps control pads. + + Pad Skew Value Delay (ps) Devicetree Value + ------------------------------------------------------ + 0000 -420ps 0 + 0001 -360ps 60 + 0010 -300ps 120 + 0011 -240ps 180 + 0100 -180ps 240 + 0101 -120ps 300 + 0110 -60ps 360 + 0111 0ps 420 + 1000 60ps 480 + 1001 120ps 540 + 1010 180ps 600 + 1011 240ps 660 + 1100 300ps 720 + 1101 360ps 780 + 1110 420ps 840 + 1111 480ps 900 + Optional properties: Maximum value of 1860, default value 900: @@ -120,11 +185,21 @@ KSZ9131: Examples: + /* Attach to an Ethernet device with autodetected PHY */ + &enet { + rxc-skew-ps = <1800>; + rxdv-skew-ps = <0>; + txc-skew-ps = <1800>; + txen-skew-ps = <0>; + status = "okay"; + }; + + /* Attach to an explicitly-specified PHY */ mdio { phy0: ethernet-phy@0 { - rxc-skew-ps = <3000>; + rxc-skew-ps = <1800>; rxdv-skew-ps = <0>; - txc-skew-ps = <3000>; + txc-skew-ps = <1800>; txen-skew-ps = <0>; reg = <0>; }; @@ -133,3 +208,20 @@ Examples: phy = <&phy0>; phy-mode = "rgmii-id"; }; + +References + + Micrel ksz9021rl/rn Data Sheet, Revision 1.2. Dated 2/13/2014. + http://www.micrel.com/_PDF/Ethernet/datasheets/ksz9021rl-rn_ds.pdf + + Micrel ksz9031rnx Data Sheet, Revision 2.1. Dated 11/20/2014. + http://www.micrel.com/_PDF/Ethernet/datasheets/KSZ9031RNX.pdf + +Notes: + + Note that a previous version of the Micrel ksz9021rl/rn Data Sheet + was missing extended register 106 (transmit data pad skews), and + incorrectly specified the ps per step as 200ps/step instead of + 120ps/step. The latest update to this document reflects the latest + revision of the Micrel specification even though usage in the kernel + still reflects that incorrect document. diff --git a/include/dt-bindings/bus/moxtet.h b/include/dt-bindings/bus/moxtet.h index dc9345440eb..10528de7b3e 100644 --- a/include/dt-bindings/bus/moxtet.h +++ b/include/dt-bindings/bus/moxtet.h @@ -2,7 +2,7 @@ /* * Constant for device tree bindings for Turris Mox module configuration bus * - * Copyright (C) 2019 Marek Behun + * Copyright (C) 2019 Marek Behún */ #ifndef _DT_BINDINGS_BUS_MOXTET_H diff --git a/src/arc/haps_hs.dts b/src/arc/haps_hs.dts index 60d578e2781..76ad527a084 100644 --- a/src/arc/haps_hs.dts +++ b/src/arc/haps_hs.dts @@ -16,7 +16,7 @@ memory { device_type = "memory"; /* CONFIG_LINUX_RAM_BASE needs to match low mem start */ - reg = <0x0 0x80000000 0x0 0x20000000 /* 512 MB low mem */ + reg = <0x0 0x80000000 0x0 0x40000000 /* 1 GB low mem */ 0x1 0x00000000 0x0 0x40000000>; /* 1 GB highmem */ }; diff --git a/src/arm/am33xx.dtsi b/src/arm/am33xx.dtsi index 5b213a1e68b..5e33d0e88f5 100644 --- a/src/arm/am33xx.dtsi +++ b/src/arm/am33xx.dtsi @@ -40,6 +40,9 @@ ethernet1 = &cpsw_emac1; spi0 = &spi0; spi1 = &spi1; + mmc0 = &mmc1; + mmc1 = &mmc2; + mmc2 = &mmc3; }; cpus { diff --git a/src/arm/armada-385-turris-omnia.dts b/src/arm/armada-385-turris-omnia.dts index 646a06420c7..5bd6a66d2c2 100644 --- a/src/arm/armada-385-turris-omnia.dts +++ b/src/arm/armada-385-turris-omnia.dts @@ -32,7 +32,8 @@ ranges = ; + MBUS_ID(0x09, 0x15) 0 0xf1110000 0x10000 + MBUS_ID(0x0c, 0x04) 0 0xf1200000 0x100000>; internal-regs { @@ -389,6 +390,7 @@ phy1: ethernet-phy@1 { compatible = "ethernet-phy-ieee802.3-c22"; reg = <1>; + marvell,reg-init = <3 18 0 0x4985>; /* irq is connected to &pcawan pin 7 */ }; diff --git a/src/arm/at91-sam9x60ek.dts b/src/arm/at91-sam9x60ek.dts index 73b6b1f89de..775ceb3acb6 100644 --- a/src/arm/at91-sam9x60ek.dts +++ b/src/arm/at91-sam9x60ek.dts @@ -334,14 +334,6 @@ }; &pinctrl { - atmel,mux-mask = < - /* A B C */ - 0xFFFFFE7F 0xC0E0397F 0xEF00019D /* pioA */ - 0x03FFFFFF 0x02FC7E68 0x00780000 /* pioB */ - 0xffffffff 0xF83FFFFF 0xB800F3FC /* pioC */ - 0x003FFFFF 0x003F8000 0x00000000 /* pioD */ - >; - adc { pinctrl_adc_default: adc_default { atmel,pins = ; diff --git a/src/arm/at91-sama5d27_som1.dtsi b/src/arm/at91-sama5d27_som1.dtsi index 1b1163858b1..e3251f3e3ea 100644 --- a/src/arm/at91-sama5d27_som1.dtsi +++ b/src/arm/at91-sama5d27_som1.dtsi @@ -84,8 +84,8 @@ pinctrl-0 = <&pinctrl_macb0_default>; phy-mode = "rmii"; - ethernet-phy@0 { - reg = <0x0>; + ethernet-phy@7 { + reg = <0x7>; interrupt-parent = <&pioA>; interrupts = ; pinctrl-names = "default"; diff --git a/src/arm/bcm2711.dtsi b/src/arm/bcm2711.dtsi index 462b1dfb038..720beec54d6 100644 --- a/src/arm/bcm2711.dtsi +++ b/src/arm/bcm2711.dtsi @@ -308,14 +308,6 @@ #reset-cells = <1>; }; - bsc_intr: interrupt-controller@7ef00040 { - compatible = "brcm,bcm2711-l2-intc", "brcm,l2-intc"; - reg = <0x7ef00040 0x30>; - interrupts = ; - interrupt-controller; - #interrupt-cells = <1>; - }; - aon_intr: interrupt-controller@7ef00100 { compatible = "brcm,bcm2711-l2-intc", "brcm,l2-intc"; reg = <0x7ef00100 0x30>; @@ -362,8 +354,6 @@ reg = <0x7ef04500 0x100>, <0x7ef00b00 0x300>; reg-names = "bsc", "auto-i2c"; clock-frequency = <97500>; - interrupt-parent = <&bsc_intr>; - interrupts = <0>; status = "disabled"; }; @@ -405,8 +395,6 @@ reg = <0x7ef09500 0x100>, <0x7ef05b00 0x300>; reg-names = "bsc", "auto-i2c"; clock-frequency = <97500>; - interrupt-parent = <&bsc_intr>; - interrupts = <1>; status = "disabled"; }; }; diff --git a/src/arm/imx6qdl-phytec-pfla02.dtsi b/src/arm/imx6qdl-phytec-pfla02.dtsi index 7a1e5319578..f28a96fcf23 100644 --- a/src/arm/imx6qdl-phytec-pfla02.dtsi +++ b/src/arm/imx6qdl-phytec-pfla02.dtsi @@ -433,6 +433,7 @@ pinctrl-0 = <&pinctrl_usdhc2>; cd-gpios = <&gpio1 4 GPIO_ACTIVE_LOW>; wp-gpios = <&gpio1 2 GPIO_ACTIVE_HIGH>; + vmmc-supply = <&vdd_sd1_reg>; status = "disabled"; }; @@ -442,5 +443,6 @@ &pinctrl_usdhc3_cdwp>; cd-gpios = <&gpio1 27 GPIO_ACTIVE_LOW>; wp-gpios = <&gpio1 29 GPIO_ACTIVE_HIGH>; + vmmc-supply = <&vdd_sd0_reg>; status = "disabled"; }; diff --git a/src/arm/imx6ul-14x14-evk.dtsi b/src/arm/imx6ul-14x14-evk.dtsi index c593597b211..5a1e10def6e 100644 --- a/src/arm/imx6ul-14x14-evk.dtsi +++ b/src/arm/imx6ul-14x14-evk.dtsi @@ -210,9 +210,6 @@ micrel,led-mode = <1>; clocks = <&clks IMX6UL_CLK_ENET_REF>; clock-names = "rmii-ref"; - reset-gpios = <&gpio_spi 1 GPIO_ACTIVE_LOW>; - reset-assert-us = <10000>; - reset-deassert-us = <100>; }; @@ -222,9 +219,6 @@ micrel,led-mode = <1>; clocks = <&clks IMX6UL_CLK_ENET2_REF>; clock-names = "rmii-ref"; - reset-gpios = <&gpio_spi 2 GPIO_ACTIVE_LOW>; - reset-assert-us = <10000>; - reset-deassert-us = <100>; }; }; }; @@ -243,6 +237,22 @@ status = "okay"; }; +&gpio_spi { + eth0-phy-hog { + gpio-hog; + gpios = <1 GPIO_ACTIVE_HIGH>; + output-high; + line-name = "eth0-phy"; + }; + + eth1-phy-hog { + gpio-hog; + gpios = <2 GPIO_ACTIVE_HIGH>; + output-high; + line-name = "eth1-phy"; + }; +}; + &i2c1 { clock-frequency = <100000>; pinctrl-names = "default"; diff --git a/src/arm/imx6ull-myir-mys-6ulx-eval.dts b/src/arm/imx6ull-myir-mys-6ulx-eval.dts index ecbb2cc5b9a..79cc45728cd 100644 --- a/src/arm/imx6ull-myir-mys-6ulx-eval.dts +++ b/src/arm/imx6ull-myir-mys-6ulx-eval.dts @@ -14,5 +14,6 @@ }; &gpmi { + fsl,use-minimum-ecc; status = "okay"; }; diff --git a/src/arm/omap3.dtsi b/src/arm/omap3.dtsi index 9dcae1f2bc9..c5b9da0d7e6 100644 --- a/src/arm/omap3.dtsi +++ b/src/arm/omap3.dtsi @@ -24,6 +24,9 @@ i2c0 = &i2c1; i2c1 = &i2c2; i2c2 = &i2c3; + mmc0 = &mmc1; + mmc1 = &mmc2; + mmc2 = &mmc3; serial0 = &uart1; serial1 = &uart2; serial2 = &uart3; diff --git a/src/arm/omap4.dtsi b/src/arm/omap4.dtsi index 72e4f648177..4a9f9496a86 100644 --- a/src/arm/omap4.dtsi +++ b/src/arm/omap4.dtsi @@ -22,6 +22,11 @@ i2c1 = &i2c2; i2c2 = &i2c3; i2c3 = &i2c4; + mmc0 = &mmc1; + mmc1 = &mmc2; + mmc2 = &mmc3; + mmc3 = &mmc4; + mmc4 = &mmc5; serial0 = &uart1; serial1 = &uart2; serial2 = &uart3; diff --git a/src/arm/omap44xx-clocks.dtsi b/src/arm/omap44xx-clocks.dtsi index 53286859110..1f1c04d8f47 100644 --- a/src/arm/omap44xx-clocks.dtsi +++ b/src/arm/omap44xx-clocks.dtsi @@ -770,14 +770,6 @@ ti,max-div = <2>; }; - sha2md5_fck: sha2md5_fck@15c8 { - #clock-cells = <0>; - compatible = "ti,gate-clock"; - clocks = <&l3_div_ck>; - ti,bit-shift = <1>; - reg = <0x15c8>; - }; - usb_phy_cm_clk32k: usb_phy_cm_clk32k@640 { #clock-cells = <0>; compatible = "ti,gate-clock"; diff --git a/src/arm/omap5.dtsi b/src/arm/omap5.dtsi index e025b7c9a35..ee821d0ab36 100644 --- a/src/arm/omap5.dtsi +++ b/src/arm/omap5.dtsi @@ -25,6 +25,11 @@ i2c2 = &i2c3; i2c3 = &i2c4; i2c4 = &i2c5; + mmc0 = &mmc1; + mmc1 = &mmc2; + mmc2 = &mmc3; + mmc3 = &mmc4; + mmc4 = &mmc5; serial0 = &uart1; serial1 = &uart2; serial2 = &uart3; diff --git a/src/arm/sam9x60.dtsi b/src/arm/sam9x60.dtsi index 84066c1298d..ec45ced3cde 100644 --- a/src/arm/sam9x60.dtsi +++ b/src/arm/sam9x60.dtsi @@ -606,6 +606,15 @@ compatible = "microchip,sam9x60-pinctrl", "atmel,at91sam9x5-pinctrl", "atmel,at91rm9200-pinctrl", "simple-bus"; ranges = <0xfffff400 0xfffff400 0x800>; + /* mux-mask corresponding to sam9x60 SoC in TFBGA228L package */ + atmel,mux-mask = < + /* A B C */ + 0xffffffff 0xffe03fff 0xef00019d /* pioA */ + 0x03ffffff 0x02fc7e7f 0x00780000 /* pioB */ + 0xffffffff 0xffffffff 0xf83fffff /* pioC */ + 0x003fffff 0x003f8000 0x00000000 /* pioD */ + >; + pioA: gpio@fffff400 { compatible = "microchip,sam9x60-gpio", "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; reg = <0xfffff400 0x200>; diff --git a/src/arm64/allwinner/sun50i-a64-pine64-lts.dts b/src/arm64/allwinner/sun50i-a64-pine64-lts.dts index 437ffe3628a..596a2590743 100644 --- a/src/arm64/allwinner/sun50i-a64-pine64-lts.dts +++ b/src/arm64/allwinner/sun50i-a64-pine64-lts.dts @@ -19,3 +19,7 @@ }; }; }; + +&mmc0 { + broken-cd; /* card detect is broken on *some* boards */ +}; diff --git a/src/arm64/allwinner/sun50i-a64-sopine.dtsi b/src/arm64/allwinner/sun50i-a64-sopine.dtsi index 3402cec8703..df62044ff7a 100644 --- a/src/arm64/allwinner/sun50i-a64-sopine.dtsi +++ b/src/arm64/allwinner/sun50i-a64-sopine.dtsi @@ -34,7 +34,7 @@ vmmc-supply = <®_dcdc1>; disable-wp; bus-width = <4>; - cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; /* PF6 */ + cd-gpios = <&pio 5 6 GPIO_ACTIVE_HIGH>; /* PF6 push-pull switch */ status = "okay"; }; diff --git a/src/arm64/allwinner/sun50i-h6-beelink-gs1.dts b/src/arm64/allwinner/sun50i-h6-beelink-gs1.dts index 4f4755152fc..b5808047d6e 100644 --- a/src/arm64/allwinner/sun50i-h6-beelink-gs1.dts +++ b/src/arm64/allwinner/sun50i-h6-beelink-gs1.dts @@ -289,10 +289,6 @@ vcc-pm-supply = <®_aldo1>; }; -&rtc { - clocks = <&ext_osc32k>; -}; - &spdif { status = "okay"; }; diff --git a/src/arm64/allwinner/sun50i-h6.dtsi b/src/arm64/allwinner/sun50i-h6.dtsi index 49e97979409..af8b7d0ef75 100644 --- a/src/arm64/allwinner/sun50i-h6.dtsi +++ b/src/arm64/allwinner/sun50i-h6.dtsi @@ -995,9 +995,9 @@ compatible = "allwinner,sun8i-a23-rsb"; reg = <0x07083000 0x400>; interrupts = ; - clocks = <&r_ccu 13>; + clocks = <&r_ccu CLK_R_APB2_RSB>; clock-frequency = <3000000>; - resets = <&r_ccu 7>; + resets = <&r_ccu RST_R_APB2_RSB>; pinctrl-names = "default"; pinctrl-0 = <&r_rsb_pins>; status = "disabled"; diff --git a/src/arm64/freescale/fsl-ls1012a.dtsi b/src/arm64/freescale/fsl-ls1012a.dtsi index 7de6b376d79..9058cfa4980 100644 --- a/src/arm64/freescale/fsl-ls1012a.dtsi +++ b/src/arm64/freescale/fsl-ls1012a.dtsi @@ -198,6 +198,7 @@ ranges = <0x0 0x00 0x1700000 0x100000>; reg = <0x00 0x1700000 0x0 0x100000>; interrupts = ; + dma-coherent; sec_jr0: jr@10000 { compatible = "fsl,sec-v5.4-job-ring", diff --git a/src/arm64/freescale/fsl-ls1043a.dtsi b/src/arm64/freescale/fsl-ls1043a.dtsi index 5a8a1dc4262..28c51e521cb 100644 --- a/src/arm64/freescale/fsl-ls1043a.dtsi +++ b/src/arm64/freescale/fsl-ls1043a.dtsi @@ -348,6 +348,7 @@ ranges = <0x0 0x00 0x1700000 0x100000>; reg = <0x00 0x1700000 0x0 0x100000>; interrupts = <0 75 0x4>; + dma-coherent; sec_jr0: jr@10000 { compatible = "fsl,sec-v5.4-job-ring", diff --git a/src/arm64/freescale/fsl-ls1046a.dtsi b/src/arm64/freescale/fsl-ls1046a.dtsi index 1d6dfd189c7..39458305e33 100644 --- a/src/arm64/freescale/fsl-ls1046a.dtsi +++ b/src/arm64/freescale/fsl-ls1046a.dtsi @@ -354,6 +354,7 @@ ranges = <0x0 0x00 0x1700000 0x100000>; reg = <0x00 0x1700000 0x0 0x100000>; interrupts = ; + dma-coherent; sec_jr0: jr@10000 { compatible = "fsl,sec-v5.4-job-ring", diff --git a/src/arm64/freescale/imx8mm-pinfunc.h b/src/arm64/freescale/imx8mm-pinfunc.h index 5ccc4cc9195..a003e6af335 100644 --- a/src/arm64/freescale/imx8mm-pinfunc.h +++ b/src/arm64/freescale/imx8mm-pinfunc.h @@ -124,7 +124,7 @@ #define MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x0A4 0x30C 0x000 0x0 0x0 #define MX8MM_IOMUXC_SD1_CMD_GPIO2_IO1 0x0A4 0x30C 0x000 0x5 0x0 #define MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x0A8 0x310 0x000 0x0 0x0 -#define MX8MM_IOMUXC_SD1_DATA0_GPIO2_IO2 0x0A8 0x31 0x000 0x5 0x0 +#define MX8MM_IOMUXC_SD1_DATA0_GPIO2_IO2 0x0A8 0x310 0x000 0x5 0x0 #define MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x0AC 0x314 0x000 0x0 0x0 #define MX8MM_IOMUXC_SD1_DATA1_GPIO2_IO3 0x0AC 0x314 0x000 0x5 0x0 #define MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x0B0 0x318 0x000 0x0 0x0 diff --git a/src/arm64/freescale/imx8mp-phyboard-pollux-rdk.dts b/src/arm64/freescale/imx8mp-phyboard-pollux-rdk.dts index 0e1a6d95338..122c95ddad3 100644 --- a/src/arm64/freescale/imx8mp-phyboard-pollux-rdk.dts +++ b/src/arm64/freescale/imx8mp-phyboard-pollux-rdk.dts @@ -35,7 +35,7 @@ &i2c2 { clock-frequency = <400000>; - pinctrl-names = "default"; + pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c2>; pinctrl-1 = <&pinctrl_i2c2_gpio>; sda-gpios = <&gpio5 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; diff --git a/src/arm64/freescale/imx8mp-phycore-som.dtsi b/src/arm64/freescale/imx8mp-phycore-som.dtsi index 44a8c2337ce..f3965ec5b31 100644 --- a/src/arm64/freescale/imx8mp-phycore-som.dtsi +++ b/src/arm64/freescale/imx8mp-phycore-som.dtsi @@ -67,7 +67,7 @@ &i2c1 { clock-frequency = <400000>; - pinctrl-names = "default"; + pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c1>; pinctrl-1 = <&pinctrl_i2c1_gpio>; sda-gpios = <&gpio5 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; diff --git a/src/arm64/freescale/imx8mq-pinfunc.h b/src/arm64/freescale/imx8mq-pinfunc.h index b94b02080a3..68e8fa17297 100644 --- a/src/arm64/freescale/imx8mq-pinfunc.h +++ b/src/arm64/freescale/imx8mq-pinfunc.h @@ -130,7 +130,7 @@ #define MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0x0A4 0x30C 0x000 0x0 0x0 #define MX8MQ_IOMUXC_SD1_CMD_GPIO2_IO1 0x0A4 0x30C 0x000 0x5 0x0 #define MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x0A8 0x310 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_SD1_DATA0_GPIO2_IO2 0x0A8 0x31 0x000 0x5 0x0 +#define MX8MQ_IOMUXC_SD1_DATA0_GPIO2_IO2 0x0A8 0x310 0x000 0x5 0x0 #define MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x0AC 0x314 0x000 0x0 0x0 #define MX8MQ_IOMUXC_SD1_DATA1_GPIO2_IO3 0x0AC 0x314 0x000 0x5 0x0 #define MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x0B0 0x318 0x000 0x0 0x0 diff --git a/src/arm64/marvell/armada-3720-turris-mox.dts b/src/arm64/marvell/armada-3720-turris-mox.dts index d239ab70ed9..53e817c5f6f 100644 --- a/src/arm64/marvell/armada-3720-turris-mox.dts +++ b/src/arm64/marvell/armada-3720-turris-mox.dts @@ -1,7 +1,7 @@ // SPDX-License-Identifier: (GPL-2.0+ OR MIT) /* * Device Tree file for CZ.NIC Turris Mox Board - * 2019 by Marek Behun + * 2019 by Marek Behún */ /dts-v1/; diff --git a/src/arm64/marvell/armada-cp11x.dtsi b/src/arm64/marvell/armada-cp11x.dtsi index 64179a372ec..c6f5df2decc 100644 --- a/src/arm64/marvell/armada-cp11x.dtsi +++ b/src/arm64/marvell/armada-cp11x.dtsi @@ -310,9 +310,11 @@ }; CP11X_LABEL(sata0): sata@540000 { - compatible = "marvell,armada-8k-ahci"; + compatible = "marvell,armada-8k-ahci", + "generic-ahci"; reg = <0x540000 0x30000>; dma-coherent; + interrupts = <107 IRQ_TYPE_LEVEL_HIGH>; clocks = <&CP11X_LABEL(clk) 1 15>, <&CP11X_LABEL(clk) 1 16>; #address-cells = <1>; @@ -320,12 +322,10 @@ status = "disabled"; sata-port@0 { - interrupts = <109 IRQ_TYPE_LEVEL_HIGH>; reg = <0>; }; sata-port@1 { - interrupts = <107 IRQ_TYPE_LEVEL_HIGH>; reg = <1>; }; }; diff --git a/src/arm64/nvidia/tegra186-p2771-0000.dts b/src/arm64/nvidia/tegra186-p2771-0000.dts index 9f5f5e1fa82..683743f8184 100644 --- a/src/arm64/nvidia/tegra186-p2771-0000.dts +++ b/src/arm64/nvidia/tegra186-p2771-0000.dts @@ -10,7 +10,7 @@ model = "NVIDIA Jetson TX2 Developer Kit"; compatible = "nvidia,p2771-0000", "nvidia,tegra186"; - aconnect { + aconnect@2900000 { status = "okay"; dma-controller@2930000 { diff --git a/src/arm64/nvidia/tegra186-p3310.dtsi b/src/arm64/nvidia/tegra186-p3310.dtsi index fd917744771..fcd71bfc670 100644 --- a/src/arm64/nvidia/tegra186-p3310.dtsi +++ b/src/arm64/nvidia/tegra186-p3310.dtsi @@ -23,7 +23,7 @@ }; chosen { - bootargs = "earlycon console=ttyS0,115200n8"; + bootargs = "earlycon console=ttyS0,115200n8 fw_devlink=on"; stdout-path = "serial0:115200n8"; }; diff --git a/src/arm64/nvidia/tegra186.dtsi b/src/arm64/nvidia/tegra186.dtsi index 02b26b39ced..9f75bbf00cf 100644 --- a/src/arm64/nvidia/tegra186.dtsi +++ b/src/arm64/nvidia/tegra186.dtsi @@ -73,7 +73,7 @@ snps,rxpbl = <8>; }; - aconnect { + aconnect@2900000 { compatible = "nvidia,tegra186-aconnect", "nvidia,tegra210-aconnect"; clocks = <&bpmp TEGRA186_CLK_APE>, diff --git a/src/arm64/nvidia/tegra194-p2972-0000.dts b/src/arm64/nvidia/tegra194-p2972-0000.dts index 2888efc42ba..d618f197a1d 100644 --- a/src/arm64/nvidia/tegra194-p2972-0000.dts +++ b/src/arm64/nvidia/tegra194-p2972-0000.dts @@ -651,6 +651,8 @@ reg = <0x1a>; interrupt-parent = <&gpio>; interrupts = ; + clocks = <&bpmp TEGRA194_CLK_AUD_MCLK>; + clock-names = "mclk"; realtek,jd-src = <2>; sound-name-prefix = "CVB-RT"; @@ -658,7 +660,6 @@ rt5658_ep: endpoint { remote-endpoint = <&i2s1_dap_ep>; mclk-fs = <256>; - clocks = <&bpmp TEGRA194_CLK_AUD_MCLK>; }; }; }; diff --git a/src/arm64/nvidia/tegra194-p3668-0000.dtsi b/src/arm64/nvidia/tegra194-p3668-0000.dtsi index 7da3d48cb41..14da4206ea6 100644 --- a/src/arm64/nvidia/tegra194-p3668-0000.dtsi +++ b/src/arm64/nvidia/tegra194-p3668-0000.dtsi @@ -5,6 +5,10 @@ model = "NVIDIA Jetson Xavier NX (SD-card)"; compatible = "nvidia,p3668-0000", "nvidia,tegra194"; + aliases { + mmc0 = "/bus@0/mmc@3400000"; + }; + bus@0 { /* SDMMC1 (SD/MMC) */ mmc@3400000 { diff --git a/src/arm64/nvidia/tegra194-p3668-0001.dtsi b/src/arm64/nvidia/tegra194-p3668-0001.dtsi index b7808648cfe..f5a9ebbfb12 100644 --- a/src/arm64/nvidia/tegra194-p3668-0001.dtsi +++ b/src/arm64/nvidia/tegra194-p3668-0001.dtsi @@ -5,6 +5,10 @@ model = "NVIDIA Jetson Xavier NX (eMMC)"; compatible = "nvidia,p3668-0001", "nvidia,tegra194"; + aliases { + mmc0 = "/bus@0/mmc@3460000"; + }; + bus@0 { /* SDMMC4 (eMMC) */ mmc@3460000 { diff --git a/src/arm64/nvidia/tegra194-p3668.dtsi b/src/arm64/nvidia/tegra194-p3668.dtsi index 4f12721c332..f16b0aa8a37 100644 --- a/src/arm64/nvidia/tegra194-p3668.dtsi +++ b/src/arm64/nvidia/tegra194-p3668.dtsi @@ -14,7 +14,6 @@ i2c5 = "/bus@0/i2c@31c0000"; i2c6 = "/bus@0/i2c@c250000"; i2c7 = "/bus@0/i2c@31e0000"; - mmc0 = "/bus@0/mmc@3460000"; rtc0 = "/bpmp/i2c/pmic@3c"; rtc1 = "/bus@0/rtc@c2a0000"; serial0 = &tcu;