mirror of
https://github.com/opnsense/src.git
synced 2026-05-28 04:12:45 -04:00
Add rudimentary WOL support. While I'm here remove enabling
busmastering/memory address in resume path. Bus driver will handle that.
This commit is contained in:
Pyun YongHyeon
parent
45e564a90b
commit
7fc94bc4e0
3 changed files with 227 additions and 17 deletions
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@ -157,6 +157,7 @@ static int vge_suspend(device_t);
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static void vge_cam_clear(struct vge_softc *);
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static int vge_cam_set(struct vge_softc *, uint8_t *);
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static void vge_clrwol(struct vge_softc *);
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static void vge_discard_rxbuf(struct vge_softc *, int);
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static int vge_dma_alloc(struct vge_softc *);
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static void vge_dma_free(struct vge_softc *);
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@ -190,6 +191,7 @@ static int vge_rx_list_init(struct vge_softc *);
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static int vge_rxeof(struct vge_softc *, int);
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static void vge_rxfilter(struct vge_softc *);
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static void vge_setvlan(struct vge_softc *);
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static void vge_setwol(struct vge_softc *);
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static void vge_start(struct ifnet *);
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static void vge_start_locked(struct ifnet *);
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static void vge_stats_clear(struct vge_softc *);
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@ -1012,6 +1014,10 @@ vge_attach(device_t dev)
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sc->vge_flags |= VGE_FLAG_PCIE;
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sc->vge_expcap = cap;
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}
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if (pci_find_extcap(dev, PCIY_PMG, &cap) == 0) {
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sc->vge_flags |= VGE_FLAG_PMCAP;
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sc->vge_pmcap = cap;
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}
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rid = 0;
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msic = pci_msi_count(dev);
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if (msi_disable == 0 && msic > 0) {
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@ -1069,6 +1075,8 @@ vge_attach(device_t dev)
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else
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sc->vge_phyaddr = CSR_READ_1(sc, VGE_MIICFG) &
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VGE_MIICFG_PHYADDR;
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/* Clear WOL and take hardware from powerdown. */
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vge_clrwol(sc);
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vge_sysctl_node(sc);
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error = vge_dma_alloc(sc);
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if (error)
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@ -1098,6 +1106,8 @@ vge_attach(device_t dev)
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ifp->if_hwassist = VGE_CSUM_FEATURES;
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ifp->if_capabilities |= IFCAP_HWCSUM | IFCAP_VLAN_HWCSUM |
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IFCAP_VLAN_HWTAGGING;
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if ((sc->vge_flags & VGE_FLAG_PMCAP) != 0)
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ifp->if_capabilities |= IFCAP_WOL;
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ifp->if_capenable = ifp->if_capabilities;
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#ifdef DEVICE_POLLING
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ifp->if_capabilities |= IFCAP_POLLING;
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@ -2279,6 +2289,15 @@ vge_ioctl(struct ifnet *ifp, u_long command, caddr_t data)
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if ((mask & IFCAP_RXCSUM) != 0 &&
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(ifp->if_capabilities & IFCAP_RXCSUM) != 0)
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ifp->if_capenable ^= IFCAP_RXCSUM;
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if ((mask & IFCAP_WOL_UCAST) != 0 &&
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(ifp->if_capabilities & IFCAP_WOL_UCAST) != 0)
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ifp->if_capenable ^= IFCAP_WOL_UCAST;
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if ((mask & IFCAP_WOL_MCAST) != 0 &&
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(ifp->if_capabilities & IFCAP_WOL_MCAST) != 0)
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ifp->if_capenable ^= IFCAP_WOL_MCAST;
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if ((mask & IFCAP_WOL_MAGIC) != 0 &&
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(ifp->if_capabilities & IFCAP_WOL_MAGIC) != 0)
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ifp->if_capenable ^= IFCAP_WOL_MAGIC;
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if ((mask & IFCAP_VLAN_HWCSUM) != 0 &&
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(ifp->if_capabilities & IFCAP_VLAN_HWCSUM) != 0)
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ifp->if_capenable ^= IFCAP_VLAN_HWCSUM;
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@ -2365,7 +2384,7 @@ vge_suspend(device_t dev)
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VGE_LOCK(sc);
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vge_stop(sc);
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vge_setwol(sc);
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sc->vge_flags |= VGE_FLAG_SUSPENDED;
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VGE_UNLOCK(sc);
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@ -2382,17 +2401,26 @@ vge_resume(device_t dev)
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{
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struct vge_softc *sc;
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struct ifnet *ifp;
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uint16_t pmstat;
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sc = device_get_softc(dev);
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ifp = sc->vge_ifp;
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/* reenable busmastering */
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pci_enable_busmaster(dev);
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pci_enable_io(dev, SYS_RES_MEMORY);
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/* reinitialize interface if necessary */
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VGE_LOCK(sc);
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if (ifp->if_flags & IFF_UP) {
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if ((sc->vge_flags & VGE_FLAG_PMCAP) != 0) {
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/* Disable PME and clear PME status. */
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pmstat = pci_read_config(sc->vge_dev,
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sc->vge_pmcap + PCIR_POWER_STATUS, 2);
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if ((pmstat & PCIM_PSTAT_PMEENABLE) != 0) {
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pmstat &= ~PCIM_PSTAT_PMEENABLE;
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pci_write_config(sc->vge_dev,
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sc->vge_pmcap + PCIR_POWER_STATUS, pmstat, 2);
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}
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}
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vge_clrwol(sc);
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/* Restart MII auto-polling. */
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vge_miipoll_start(sc);
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ifp = sc->vge_ifp;
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/* Reinitialize interface if necessary. */
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if ((ifp->if_flags & IFF_UP) != 0) {
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ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
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vge_init_locked(sc);
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}
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@ -2409,15 +2437,8 @@ vge_resume(device_t dev)
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static int
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vge_shutdown(device_t dev)
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{
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struct vge_softc *sc;
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sc = device_get_softc(dev);
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VGE_LOCK(sc);
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vge_stop(sc);
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VGE_UNLOCK(sc);
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return (0);
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return (vge_suspend(dev));
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}
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#define VGE_SYSCTL_STAT_ADD32(c, h, n, p, d) \
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@ -2706,3 +2727,154 @@ vge_intr_holdoff(struct vge_softc *sc)
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CSR_WRITE_1(sc, VGE_CRS3, VGE_CR3_INT_HOLDOFF);
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}
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}
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static void
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vge_setlinkspeed(struct vge_softc *sc)
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{
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struct mii_data *mii;
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int aneg, i;
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VGE_LOCK_ASSERT(sc);
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mii = device_get_softc(sc->vge_miibus);
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mii_pollstat(mii);
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aneg = 0;
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if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) ==
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(IFM_ACTIVE | IFM_AVALID)) {
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switch IFM_SUBTYPE(mii->mii_media_active) {
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case IFM_10_T:
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case IFM_100_TX:
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return;
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case IFM_1000_T:
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aneg++;
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default:
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break;
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}
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}
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vge_miibus_writereg(sc->vge_dev, sc->vge_phyaddr, MII_100T2CR, 0);
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vge_miibus_writereg(sc->vge_dev, sc->vge_phyaddr, MII_ANAR,
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ANAR_TX_FD | ANAR_TX | ANAR_10_FD | ANAR_10 | ANAR_CSMA);
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vge_miibus_writereg(sc->vge_dev, sc->vge_phyaddr, MII_BMCR,
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BMCR_AUTOEN | BMCR_STARTNEG);
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DELAY(1000);
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if (aneg != 0) {
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/* Poll link state until vge(4) get a 10/100 link. */
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for (i = 0; i < MII_ANEGTICKS_GIGE; i++) {
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mii_pollstat(mii);
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if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID))
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== (IFM_ACTIVE | IFM_AVALID)) {
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switch (IFM_SUBTYPE(mii->mii_media_active)) {
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case IFM_10_T:
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case IFM_100_TX:
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return;
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default:
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break;
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}
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}
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VGE_UNLOCK(sc);
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pause("vgelnk", hz);
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VGE_LOCK(sc);
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}
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if (i == MII_ANEGTICKS_GIGE)
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device_printf(sc->vge_dev, "establishing link failed, "
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"WOL may not work!");
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}
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/*
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* No link, force MAC to have 100Mbps, full-duplex link.
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* This is the last resort and may/may not work.
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*/
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mii->mii_media_status = IFM_AVALID | IFM_ACTIVE;
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mii->mii_media_active = IFM_ETHER | IFM_100_TX | IFM_FDX;
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}
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static void
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vge_setwol(struct vge_softc *sc)
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{
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struct ifnet *ifp;
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uint16_t pmstat;
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uint8_t val;
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VGE_LOCK_ASSERT(sc);
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if ((sc->vge_flags & VGE_FLAG_PMCAP) == 0) {
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/* No PME capability, PHY power down. */
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vge_miibus_writereg(sc->vge_dev, sc->vge_phyaddr, MII_BMCR,
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BMCR_PDOWN);
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vge_miipoll_stop(sc);
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return;
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}
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ifp = sc->vge_ifp;
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/* Clear WOL on pattern match. */
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CSR_WRITE_1(sc, VGE_WOLCR0C, VGE_WOLCR0_PATTERN_ALL);
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/* Disable WOL on magic/unicast packet. */
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CSR_WRITE_1(sc, VGE_WOLCR1C, 0x0F);
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CSR_WRITE_1(sc, VGE_WOLCFGC, VGE_WOLCFG_SAB | VGE_WOLCFG_SAM |
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VGE_WOLCFG_PMEOVR);
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if ((ifp->if_capenable & IFCAP_WOL) != 0) {
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vge_setlinkspeed(sc);
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val = 0;
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if ((ifp->if_capenable & IFCAP_WOL_UCAST) != 0)
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val |= VGE_WOLCR1_UCAST;
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if ((ifp->if_capenable & IFCAP_WOL_MAGIC) != 0)
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val |= VGE_WOLCR1_MAGIC;
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CSR_WRITE_1(sc, VGE_WOLCR1S, val);
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val = 0;
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if ((ifp->if_capenable & IFCAP_WOL_MCAST) != 0)
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val |= VGE_WOLCFG_SAM | VGE_WOLCFG_SAB;
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CSR_WRITE_1(sc, VGE_WOLCFGS, val | VGE_WOLCFG_PMEOVR);
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/* Disable MII auto-polling. */
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vge_miipoll_stop(sc);
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}
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CSR_SETBIT_1(sc, VGE_DIAGCTL,
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VGE_DIAGCTL_MACFORCE | VGE_DIAGCTL_FDXFORCE);
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CSR_CLRBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_GMII);
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/* Clear WOL status on pattern match. */
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CSR_WRITE_1(sc, VGE_WOLSR0C, 0xFF);
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CSR_WRITE_1(sc, VGE_WOLSR1C, 0xFF);
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val = CSR_READ_1(sc, VGE_PWRSTAT);
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val |= VGE_STICKHW_SWPTAG;
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CSR_WRITE_1(sc, VGE_PWRSTAT, val);
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/* Put hardware into sleep. */
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val = CSR_READ_1(sc, VGE_PWRSTAT);
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val |= VGE_STICKHW_DS0 | VGE_STICKHW_DS1;
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CSR_WRITE_1(sc, VGE_PWRSTAT, val);
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/* Request PME if WOL is requested. */
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pmstat = pci_read_config(sc->vge_dev, sc->vge_pmcap +
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PCIR_POWER_STATUS, 2);
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pmstat &= ~(PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE);
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if ((ifp->if_capenable & IFCAP_WOL) != 0)
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pmstat |= PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE;
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pci_write_config(sc->vge_dev, sc->vge_pmcap + PCIR_POWER_STATUS,
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pmstat, 2);
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}
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static void
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vge_clrwol(struct vge_softc *sc)
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{
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uint8_t val;
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val = CSR_READ_1(sc, VGE_PWRSTAT);
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val &= ~VGE_STICKHW_SWPTAG;
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CSR_WRITE_1(sc, VGE_PWRSTAT, val);
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/* Disable WOL and clear power state indicator. */
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val = CSR_READ_1(sc, VGE_PWRSTAT);
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val &= ~(VGE_STICKHW_DS0 | VGE_STICKHW_DS1);
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CSR_WRITE_1(sc, VGE_PWRSTAT, val);
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CSR_CLRBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_GMII);
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CSR_CLRBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_MACFORCE);
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/* Clear WOL on pattern match. */
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CSR_WRITE_1(sc, VGE_WOLCR0C, VGE_WOLCR0_PATTERN_ALL);
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/* Disable WOL on magic/unicast packet. */
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CSR_WRITE_1(sc, VGE_WOLCR1C, 0x0F);
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CSR_WRITE_1(sc, VGE_WOLCFGC, VGE_WOLCFG_SAB | VGE_WOLCFG_SAM |
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VGE_WOLCFG_PMEOVR);
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/* Clear WOL status on pattern match. */
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CSR_WRITE_1(sc, VGE_WOLSR0C, 0xFF);
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CSR_WRITE_1(sc, VGE_WOLSR1C, 0xFF);
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}
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@ -590,6 +590,42 @@
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#define VGE_MIB_DATA_MASK 0x00FFFFFF
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#define VGE_MIB_DATA_IDX(x) ((x) >> 24)
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/* Sticky bit shadow register */
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#define VGE_STICKHW_DS0 0x01
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#define VGE_STICKHW_DS1 0x02
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#define VGE_STICKHW_WOL_ENB 0x04
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#define VGE_STICKHW_WOL_STS 0x08
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#define VGE_STICKHW_SWPTAG 0x10
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/* WOL pattern control */
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#define VGE_WOLCR0_PATTERN0 0x01
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#define VGE_WOLCR0_PATTERN1 0x02
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#define VGE_WOLCR0_PATTERN2 0x04
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#define VGE_WOLCR0_PATTERN3 0x08
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#define VGE_WOLCR0_PATTERN4 0x10
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#define VGE_WOLCR0_PATTERN5 0x20
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#define VGE_WOLCR0_PATTERN6 0x40
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#define VGE_WOLCR0_PATTERN7 0x80
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#define VGE_WOLCR0_PATTERN_ALL 0xFF
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/* WOL event control */
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#define VGE_WOLCR1_UCAST 0x01
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#define VGE_WOLCR1_MAGIC 0x02
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#define VGE_WOLCR1_LINKON 0x04
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#define VGE_WOLCR1_LINKOFF 0x08
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/* Poweer management config */
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#define VGE_PWRCFG_LEGACY_WOLEN 0x01
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#define VGE_PWRCFG_WOL_PULSE 0x20
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#define VGE_PWRCFG_WOL_BUTTON 0x00
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/* WOL config register */
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#define VGE_WOLCFG_PHYINT_ENB 0x01
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#define VGE_WOLCFG_SAB 0x10
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#define VGE_WOLCFG_SAM 0x20
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#define VGE_WOLCFG_PMEOVR 0x80
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/* EEPROM control/status register */
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#define VGE_EECSR_EDO 0x01 /* data out pin */
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@ -186,9 +186,11 @@ struct vge_softc {
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int vge_flags;
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#define VGE_FLAG_PCIE 0x0001
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#define VGE_FLAG_MSI 0x0002
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#define VGE_FLAG_PMCAP 0x0004
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#define VGE_FLAG_SUSPENDED 0x4000
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#define VGE_FLAG_LINK 0x8000
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int vge_expcap;
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int vge_pmcap;
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int vge_camidx;
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int vge_int_holdoff;
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int vge_rx_coal_pkt;
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