From 7cb146ae26315b9ca1237c4b5b6f68f99e01d1cb Mon Sep 17 00:00:00 2001 From: Ian Lepore Date: Mon, 15 Sep 2014 15:36:00 +0000 Subject: [PATCH] The private peripheral interrupts start at offset 16, not 0. Also, use names rather than inline mystery constants for these offsets. Pointed out by: andrew --- sys/arm/arm/gic.c | 10 +++++++--- 1 file changed, 7 insertions(+), 3 deletions(-) diff --git a/sys/arm/arm/gic.c b/sys/arm/arm/gic.c index a138d2d1c91..9e15f8bc285 100644 --- a/sys/arm/arm/gic.c +++ b/sys/arm/arm/gic.c @@ -83,7 +83,11 @@ __FBSDID("$FreeBSD$"); #define GICC_ABPR 0x001C /* v1 ICCABPR */ #define GICC_IIDR 0x00FC /* v1 ICCIIDR*/ -#define GIC_LAST_IPI 15 /* Irqs 0-15 are IPIs. */ +#define GIC_FIRST_IPI 0 /* Irqs 0-15 are SGIs/IPIs. */ +#define GIC_LAST_IPI 15 +#define GIC_FIRST_PPI 16 /* Irqs 16-31 are private (per */ +#define GIC_LAST_PPI 31 /* core) peripheral interrupts. */ +#define GIC_FIRST_SPI 32 /* Irqs 32+ are shared peripherals. */ /* First bit is a polarity bit (0 - low, 1 - high) */ #define GICD_ICFGR_POL_LOW (0 << 0) @@ -205,9 +209,9 @@ gic_decode_fdt(uint32_t iparent, uint32_t *intr, int *interrupt, *pol = INTR_POLARITY_CONFORM; } else { if (intr[0] == 0) - *interrupt = fdt32_to_cpu(intr[1]) + 32; + *interrupt = fdt32_to_cpu(intr[1]) + GIC_FIRST_SPI; else - *interrupt = fdt32_to_cpu(intr[1]); + *interrupt = fdt32_to_cpu(intr[1]) + GIC_FIRST_PPI; /* * In intr[2], bits[3:0] are trigger type and level flags. * 1 = low-to-high edge triggered