diff --git a/sys/dev/mii/rgephy.c b/sys/dev/mii/rgephy.c
index 289eeabe369..bb60fa92fe1 100644
--- a/sys/dev/mii/rgephy.c
+++ b/sys/dev/mii/rgephy.c
@@ -90,6 +90,7 @@ static void	rgephy_reset(struct mii_softc *);
 static int	rgephy_linkup(struct mii_softc *);
 static void	rgephy_loop(struct mii_softc *);
 static void	rgephy_load_dspcode(struct mii_softc *);
+static void	rgephy_disable_eee(struct mii_softc *);
 
 static const struct mii_phydesc rgephys[] = {
 	MII_PHY_DESC(REALTEK, RTL8169S),
@@ -517,10 +518,9 @@ rgephy_reset(struct mii_softc *sc)
 	switch (sc->mii_mpd_rev) {
 	case RGEPHY_8211F:
 		pcr = PHY_READ(sc, RGEPHY_F_MII_PCR1);
-		if ((pcr & RGEPHY_F_PCR1_MDI_MM) != 0) {
-			pcr &= ~RGEPHY_F_PCR1_MDI_MM;
-			PHY_WRITE(sc, RGEPHY_F_MII_PCR1, pcr);
-		}
+		pcr &= ~(RGEPHY_F_PCR1_MDI_MM | RGEPHY_F_PCR1_ALDPS_EN);
+		PHY_WRITE(sc, RGEPHY_F_MII_PCR1, pcr);
+		rgephy_disable_eee(sc);
 		break;
 	case RGEPHY_8211C:
 		if ((sc->mii_flags & MIIF_PHYPRIV0) == 0) {
@@ -548,3 +548,29 @@ rgephy_reset(struct mii_softc *sc)
 	DELAY(1000);
 	rgephy_load_dspcode(sc);
 }
+
+static void
+rgephy_disable_eee(struct mii_softc *sc)
+{
+	uint16_t anar;
+
+	PHY_WRITE(sc, RGEPHY_F_EPAGSR, 0x0000);
+	PHY_WRITE(sc, MII_MMDACR, MMDACR_FN_ADDRESS |
+	    (MMDACR_DADDRMASK & RGEPHY_F_MMD_DEV_7));
+	PHY_WRITE(sc, MII_MMDAADR, RGEPHY_F_MMD_EEEAR);
+	PHY_WRITE(sc, MII_MMDACR, MMDACR_FN_DATANPI |
+	    (MMDACR_DADDRMASK & RGEPHY_F_MMD_DEV_7));
+	PHY_WRITE(sc, MII_MMDAADR, 0x0000);
+	PHY_WRITE(sc, MII_MMDACR, 0x0000);
+	/*
+	 * XXX
+	 * Restart auto-negotiation to take changes effect.
+	 * This may result in link establishment.
+	 */
+	anar = BMSR_MEDIA_TO_ANAR(sc->mii_capabilities) | ANAR_CSMA;
+	PHY_WRITE(sc, RGEPHY_MII_ANAR, anar);
+	PHY_WRITE(sc, RGEPHY_MII_1000CTL, RGEPHY_1000CTL_AHD |
+	    RGEPHY_1000CTL_AFD);
+	PHY_WRITE(sc, RGEPHY_MII_BMCR, RGEPHY_BMCR_RESET |
+	    RGEPHY_BMCR_AUTOEN | RGEPHY_BMCR_STARTNEG);
+}
diff --git a/sys/dev/mii/rgephyreg.h b/sys/dev/mii/rgephyreg.h
index 2a00517ea40..7c24a1f7cbb 100644
--- a/sys/dev/mii/rgephyreg.h
+++ b/sys/dev/mii/rgephyreg.h
@@ -183,4 +183,20 @@
 #define	RGEPHY_F_SSR_MDI	0x0002	/* MDI/MDIX */
 #define	RGEPHY_F_SSR_JABBER	0x0001	/* Jabber */
 
+/* RTL8211F */
+#define	RGEPHY_F_EPAGSR		0x1F	/* Extension page select register */
+
+/* RTL8211F */
+#define	RGEPHY_F_MMD_DEV_7	0x07
+
+/* RTL8211F MMD device 7 */
+#define	RGEPHY_F_MMD_EEEAR	0x3C	/* EEE advertisement */
+#define	EEEAR_1000T		0x0004	/* adv. 1000baseT EEE */
+#define	EEEAR_100TX		0x0002	/* adv. 100baseTX EEE */
+
+/* RTL8211F MMD device 7 */
+#define	RGEPHY_F_MMD_EEELPAR	0x3D	/* EEE link partner abilities */
+#define	EEELPAR_1000T		0x0004	/* link partner 1000baseT EEE capable */
+#define	EEELPAR_100TX		0x0002	/* link partner 100baseTX EEE capable */
+
 #endif /* _DEV_RGEPHY_MIIREG_H_ */