From 4df029cc74e5ec124f14a5682e44999ce4f086df Mon Sep 17 00:00:00 2001 From: Dimitry Andric Date: Wed, 24 Jan 2024 20:11:41 +0100 Subject: [PATCH] Vendor import of llvm-project main llvmorg-18-init-18359-g93248729cfae, the last commit before the upstream release/18.x branch was created. --- clang/include/clang/AST/APNumericStorage.h | 71 + clang/include/clang/AST/Decl.h | 25 +- clang/include/clang/AST/DeclBase.h | 9 +- clang/include/clang/AST/DeclCXX.h | 41 +- clang/include/clang/AST/Expr.h | 64 +- clang/include/clang/AST/ExprCXX.h | 19 +- clang/include/clang/AST/ODRHash.h | 3 + clang/include/clang/AST/PropertiesBase.td | 14 + clang/include/clang/AST/RecursiveASTVisitor.h | 2 + clang/include/clang/AST/Stmt.h | 8 +- .../clang/AST/TemplateArgumentVisitor.h | 2 + clang/include/clang/AST/TemplateBase.h | 86 +- clang/include/clang/AST/Type.h | 90 +- clang/include/clang/ASTMatchers/ASTMatchers.h | 205 +- .../clang/ASTMatchers/ASTMatchersInternal.h | 3 + .../FlowSensitive/ControlFlowContext.h | 3 +- .../Analysis/FlowSensitive/DataflowAnalysis.h | 21 +- .../FlowSensitive/DataflowEnvironment.h | 3 +- .../clang/Analysis/FlowSensitive/Formula.h | 4 + .../clang/Analysis/FlowSensitive/Transfer.h | 13 +- .../TypeErasedDataflowAnalysis.h | 9 +- clang/include/clang/Basic/Attr.td | 100 +- clang/include/clang/Basic/AttrDocs.td | 84 +- .../include/clang/Basic/AttributeCommonInfo.h | 13 + clang/include/clang/Basic/BuiltinsAMDGPU.def | 28 +- .../clang/Basic/BuiltinsLoongArchBase.def | 5 + .../clang/Basic/BuiltinsLoongArchLASX.def | 6 + .../clang/Basic/BuiltinsLoongArchLSX.def | 6 + clang/include/clang/Basic/BuiltinsPPC.def | 4 + clang/include/clang/Basic/CodeGenOptions.def | 15 +- clang/include/clang/Basic/CodeGenOptions.h | 3 + .../clang/Basic/DiagnosticCommonKinds.td | 8 +- .../clang/Basic/DiagnosticDriverKinds.td | 15 +- .../clang/Basic/DiagnosticParseKinds.td | 12 + .../clang/Basic/DiagnosticSemaKinds.td | 41 +- .../Basic/DiagnosticSerializationKinds.td | 6 +- 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| 10 +- clang/lib/AST/Interp/ByteCodeExprGen.cpp | 96 +- clang/lib/AST/Interp/ByteCodeExprGen.h | 6 +- clang/lib/AST/Interp/ByteCodeStmtGen.cpp | 68 +- clang/lib/AST/Interp/Context.cpp | 108 +- clang/lib/AST/Interp/Context.h | 3 + clang/lib/AST/Interp/EvalEmitter.cpp | 174 +- clang/lib/AST/Interp/EvalEmitter.h | 15 +- clang/lib/AST/Interp/EvaluationResult.cpp | 196 + clang/lib/AST/Interp/EvaluationResult.h | 111 + clang/lib/AST/Interp/IntegralAP.h | 12 +- clang/lib/AST/Interp/Interp.cpp | 166 +- clang/lib/AST/Interp/Interp.h | 37 +- clang/lib/AST/Interp/Opcodes.td | 9 +- clang/lib/AST/Interp/Pointer.cpp | 162 +- clang/lib/AST/Interp/Pointer.h | 3 +- clang/lib/AST/ItaniumMangle.cpp | 40 +- clang/lib/AST/JSONNodeDumper.cpp | 7 +- clang/lib/AST/Mangle.cpp | 2 +- clang/lib/AST/MicrosoftMangle.cpp | 78 +- clang/lib/AST/ODRDiagsEmitter.cpp | 4 +- clang/lib/AST/ODRHash.cpp | 120 +- clang/lib/AST/RecordLayoutBuilder.cpp | 4 +- clang/lib/AST/StmtPrinter.cpp | 5 +- clang/lib/AST/StmtProfile.cpp | 6 + clang/lib/AST/TemplateBase.cpp | 113 +- clang/lib/AST/TextNodeDumper.cpp | 2 +- clang/lib/AST/Type.cpp | 12 +- clang/lib/AST/TypeLoc.cpp | 1 + clang/lib/AST/TypePrinter.cpp | 39 +- clang/lib/AST/VTableBuilder.cpp | 18 +- clang/lib/ASTMatchers/ASTMatchersInternal.cpp | 1 + clang/lib/ASTMatchers/Dynamic/Registry.cpp | 7 + clang/lib/Analysis/ExprMutationAnalyzer.cpp | 17 +- .../FlowSensitive/ControlFlowContext.cpp | 2 +- .../FlowSensitive/DataflowAnalysisContext.cpp | 8 +- .../FlowSensitive/DataflowEnvironment.cpp | 24 +- .../FlowSensitive/SimplifyConstraints.cpp | 4 +- clang/lib/Analysis/FlowSensitive/Transfer.cpp | 2 + .../TypeErasedDataflowAnalysis.cpp | 92 +- clang/lib/Analysis/FlowSensitive/Value.cpp | 14 +- clang/lib/Analysis/RetainSummaryManager.cpp | 2 +- clang/lib/Analysis/UnsafeBufferUsage.cpp | 5 +- clang/lib/Basic/CodeGenOptions.cpp | 2 + clang/lib/Basic/FileManager.cpp | 2 +- clang/lib/Basic/Targets.cpp | 2 + clang/lib/Basic/Targets/AArch64.cpp | 27 +- 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| 49 +- llvm/lib/IR/DebugInfo.cpp | 254 +- llvm/lib/IR/DebugProgramInstruction.cpp | 190 +- llvm/lib/IR/Dominators.cpp | 5 +- llvm/lib/IR/Globals.cpp | 3 +- llvm/lib/IR/Instruction.cpp | 6 +- llvm/lib/IR/Instructions.cpp | 4 +- llvm/lib/IR/Metadata.cpp | 103 +- llvm/lib/IR/StructuralHash.cpp | 9 +- .../VFABIDemangler.cpp} | 133 +- llvm/lib/IR/Value.cpp | 6 +- llvm/lib/IR/Verifier.cpp | 28 + llvm/lib/InterfaceStub/IFSHandler.cpp | 6 + llvm/lib/InterfaceStub/IFSStub.cpp | 3 +- llvm/lib/LTO/LTO.cpp | 2 +- llvm/lib/LTO/ThinLTOCodeGenerator.cpp | 6 +- llvm/lib/LineEditor/LineEditor.cpp | 2 +- llvm/lib/MC/ELFObjectWriter.cpp | 11 +- llvm/lib/MC/MCFragment.cpp | 2 +- llvm/lib/MC/MCObjectFileInfo.cpp | 4 + llvm/lib/MC/MCParser/DarwinAsmParser.cpp | 2 + llvm/lib/MC/MCStreamer.cpp | 9 + llvm/lib/MC/WasmObjectWriter.cpp | 2 +- llvm/lib/ObjCopy/CommonConfig.cpp | 6 +- llvm/lib/Object/Archive.cpp | 2 +- llvm/lib/Object/ArchiveWriter.cpp | 2 +- llvm/lib/Object/Binary.cpp | 1 + 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llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp | 21 +- llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.h | 2 +- llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp | 35 + llvm/lib/Target/AMDGPU/AMDGPUISelLowering.h | 8 + .../AMDGPU/AMDGPUInstCombineIntrinsic.cpp | 38 +- .../AMDGPU/AMDGPUInstructionSelector.cpp | 28 +- .../Target/AMDGPU/AMDGPUInstructionSelector.h | 6 +- llvm/lib/Target/AMDGPU/AMDGPUInstructions.td | 3 + .../AMDGPU/AMDGPULateCodeGenPrepare.cpp | 10 + .../lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp | 63 +- .../AMDGPU/AMDGPULowerKernelArguments.cpp | 3 +- .../AMDGPU/AMDGPULowerKernelAttributes.cpp | 5 +- .../AMDGPU/AMDGPUMachineCFGStructurizer.cpp | 2 +- .../AMDGPU/AMDGPUMarkLastScratchLoad.cpp | 142 + .../AMDGPU/AMDGPUPostLegalizerCombiner.cpp | 6 + .../Target/AMDGPU/AMDGPURegisterBankInfo.cpp | 42 +- .../AMDGPURemoveIncompatibleFunctions.cpp | 3 +- .../AMDGPU/AMDGPUResourceUsageAnalysis.cpp | 2 +- .../Target/AMDGPU/AMDGPUSearchableTables.td | 10 + llvm/lib/Target/AMDGPU/AMDGPUSubtarget.cpp | 2 +- .../lib/Target/AMDGPU/AMDGPUTargetMachine.cpp | 3 + .../AMDGPU/AsmParser/AMDGPUAsmParser.cpp | 144 +- llvm/lib/Target/AMDGPU/BUFInstructions.td | 96 +- llvm/lib/Target/AMDGPU/DSInstructions.td | 41 +- .../Disassembler/AMDGPUDisassembler.cpp | 7 +- llvm/lib/Target/AMDGPU/FLATInstructions.td | 189 +- llvm/lib/Target/AMDGPU/GCNDPPCombine.cpp | 28 +- .../lib/Target/AMDGPU/GCNHazardRecognizer.cpp | 31 +- llvm/lib/Target/AMDGPU/GCNNSAReassign.cpp | 2 +- llvm/lib/Target/AMDGPU/GCNSubtarget.h | 49 +- .../AMDGPU/MCTargetDesc/AMDGPUAsmBackend.cpp | 14 +- .../MCTargetDesc/AMDGPUELFObjectWriter.cpp | 19 +- .../AMDGPU/MCTargetDesc/AMDGPUInstPrinter.cpp | 17 +- .../MCTargetDesc/AMDGPUMCCodeEmitter.cpp | 43 +- .../AMDGPU/MCTargetDesc/AMDGPUMCTargetDesc.h | 4 +- .../MCTargetDesc/AMDGPUTargetStreamer.cpp | 134 +- .../MCTargetDesc/AMDGPUTargetStreamer.h | 59 +- llvm/lib/Target/AMDGPU/MIMGInstructions.td | 5 + llvm/lib/Target/AMDGPU/R600ISelLowering.cpp | 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llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h | 152 +- llvm/lib/Target/AMDGPU/VOP1Instructions.td | 8 +- llvm/lib/Target/AMDGPU/VOP2Instructions.td | 45 +- llvm/lib/Target/AMDGPU/VOP3Instructions.td | 4 +- llvm/lib/Target/AMDGPU/VOP3PInstructions.td | 83 +- llvm/lib/Target/AMDGPU/VOPCInstructions.td | 44 +- llvm/lib/Target/AMDGPU/VOPInstructions.td | 19 +- llvm/lib/Target/ARM/ARM.td | 18 + llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp | 19 +- llvm/lib/Target/ARM/ARMCallLowering.cpp | 6 +- llvm/lib/Target/ARM/ARMISelLowering.cpp | 11 +- llvm/lib/Target/ARM/ARMInstrMVE.td | 2 +- llvm/lib/Target/ARM/ARMSubtarget.h | 1 + .../lib/Target/ARM/AsmParser/ARMAsmParser.cpp | 14 +- .../Target/ARM/MCTargetDesc/ARMAsmBackend.cpp | 20 +- .../ARM/MCTargetDesc/ARMELFStreamer.cpp | 1 + .../Target/ARM/MCTargetDesc/ARMFixupKinds.h | 2 +- .../Target/ARM/MVEGatherScatterLowering.cpp | 4 +- llvm/lib/Target/ARM/Thumb1InstrInfo.cpp | 4 +- llvm/lib/Target/ARM/Thumb2InstrInfo.cpp | 6 +- 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llvm/lib/Target/Mips/MipsCallLowering.cpp | 2 +- llvm/lib/Target/Mips/MipsRegisterBankInfo.cpp | 8 +- llvm/lib/Target/NVPTX/NVPTXISelDAGToDAG.cpp | 24 + llvm/lib/Target/NVPTX/NVPTXISelLowering.cpp | 50 +- llvm/lib/Target/NVPTX/NVPTXISelLowering.h | 10 +- llvm/lib/Target/NVPTX/NVPTXIntrinsics.td | 95 +- .../Target/NVPTX/NVPTXReplaceImageHandles.cpp | 12 + llvm/lib/Target/PowerPC/PPCISelLowering.cpp | 12 +- llvm/lib/Target/PowerPC/PPCInstrInfo.cpp | 19 +- llvm/lib/Target/PowerPC/PPCInstrInfo.td | 4 + .../Target/PowerPC/PPCTargetTransformInfo.cpp | 5 +- .../Target/RISCV/AsmParser/RISCVAsmParser.cpp | 63 +- .../Target/RISCV/GISel/RISCVCallLowering.cpp | 8 +- .../RISCV/GISel/RISCVInstructionSelector.cpp | 80 +- .../RISCV/MCTargetDesc/RISCVAsmBackend.cpp | 10 + .../RISCV/MCTargetDesc/RISCVBaseInfo.cpp | 5 + .../Target/RISCV/MCTargetDesc/RISCVBaseInfo.h | 6 +- .../MCTargetDesc/RISCVELFObjectWriter.cpp | 15 + .../RISCV/MCTargetDesc/RISCVFixupKinds.h | 6 + .../RISCV/MCTargetDesc/RISCVMCCodeEmitter.cpp | 40 + .../Target/RISCV/MCTargetDesc/RISCVMCExpr.cpp | 18 + .../Target/RISCV/MCTargetDesc/RISCVMCExpr.h | 4 + .../MCTargetDesc/RISCVTargetStreamer.cpp | 13 +- llvm/lib/Target/RISCV/RISCV.td | 1 + llvm/lib/Target/RISCV/RISCVAsmPrinter.cpp | 17 +- llvm/lib/Target/RISCV/RISCVCallingConv.td | 16 +- llvm/lib/Target/RISCV/RISCVCodeGenPrepare.cpp | 76 +- .../Target/RISCV/RISCVExpandPseudoInsts.cpp | 51 + llvm/lib/Target/RISCV/RISCVFeatures.td | 1126 +- llvm/lib/Target/RISCV/RISCVFrameLowering.cpp | 39 +- llvm/lib/Target/RISCV/RISCVFrameLowering.h | 7 +- .../RISCV/RISCVGatherScatterLowering.cpp | 11 +- llvm/lib/Target/RISCV/RISCVISelLowering.cpp | 702 +- llvm/lib/Target/RISCV/RISCVISelLowering.h | 3 +- llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp | 32 +- llvm/lib/Target/RISCV/RISCVInstrInfo.cpp | 45 +- llvm/lib/Target/RISCV/RISCVInstrInfo.td | 29 + .../Target/RISCV/RISCVInstrInfoVPseudos.td | 60 +- .../Target/RISCV/RISCVInstrInfoVVLPatterns.td | 26 +- llvm/lib/Target/RISCV/RISCVInstrInfoZfh.td | 48 +- .../lib/Target/RISCV/RISCVMergeBaseOffset.cpp | 103 +- llvm/lib/Target/RISCV/RISCVOptWInstrs.cpp | 8 +- llvm/lib/Target/RISCV/RISCVProcessors.td | 53 +- llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp | 69 +- llvm/lib/Target/RISCV/RISCVSchedSiFiveP400.td | 354 + llvm/lib/Target/RISCV/RISCVTargetMachine.cpp | 19 +- .../Target/RISCV/RISCVTargetObjectFile.cpp | 12 + llvm/lib/Target/RISCV/RISCVTargetObjectFile.h | 6 + .../Target/RISCV/RISCVTargetTransformInfo.cpp | 574 +- .../Target/RISCV/RISCVTargetTransformInfo.h | 3 +- llvm/lib/Target/SPIRV/SPIRV.h | 1 + llvm/lib/Target/SPIRV/SPIRVEmitIntrinsics.cpp | 4 +- llvm/lib/Target/SPIRV/SPIRVModuleAnalysis.cpp | 85 +- .../SPIRV/SPIRVStripConvergentIntrinsics.cpp | 86 + llvm/lib/Target/SPIRV/SPIRVTargetMachine.cpp | 1 + .../Target/Sparc/AsmParser/SparcAsmParser.cpp | 20 +- llvm/lib/Target/Sparc/Sparc.td | 18 +- llvm/lib/Target/Sparc/SparcAsmPrinter.cpp | 25 +- llvm/lib/Target/Sparc/SparcSubtarget.cpp | 19 +- llvm/lib/Target/Sparc/SparcSubtarget.h | 8 +- llvm/lib/Target/Sparc/SparcTargetMachine.cpp | 7 +- .../lib/Target/SystemZ/SystemZElimCompare.cpp | 22 +- .../Target/SystemZ/SystemZISelLowering.cpp | 9 +- llvm/lib/Target/SystemZ/SystemZInstrFP.td | 37 +- .../lib/Target/SystemZ/SystemZInstrFormats.td | 12 - llvm/lib/Target/SystemZ/SystemZInstrInfo.cpp | 3 - llvm/lib/Target/SystemZ/SystemZPatterns.td | 7 +- .../Target/SystemZ/SystemZRegisterInfo.cpp | 3 +- llvm/lib/Target/SystemZ/SystemZScheduleZ13.td | 4 +- llvm/lib/Target/SystemZ/SystemZScheduleZ14.td | 4 +- llvm/lib/Target/SystemZ/SystemZScheduleZ15.td | 4 +- llvm/lib/Target/SystemZ/SystemZScheduleZ16.td | 4 +- .../lib/Target/SystemZ/SystemZScheduleZ196.td | 3 +- .../Target/SystemZ/SystemZScheduleZEC12.td | 3 +- .../SystemZ/SystemZTargetTransformInfo.cpp | 106 +- .../SystemZ/SystemZTargetTransformInfo.h | 2 + llvm/lib/Target/TargetMachine.cpp | 31 +- .../AsmParser/WebAssemblyAsmParser.cpp | 2 +- .../WebAssemblyDebugValueManager.cpp | 4 + .../WebAssembly/WebAssemblyUtilities.cpp | 2 +- .../lib/Target/X86/MCTargetDesc/X86BaseInfo.h | 7 +- .../X86/MCTargetDesc/X86InstComments.cpp | 32 +- .../X86/MCTargetDesc/X86InstPrinterCommon.cpp | 4 +- llvm/lib/Target/X86/X86AsmPrinter.cpp | 8 + llvm/lib/Target/X86/X86CodeGenPassBuilder.cpp | 56 + llvm/lib/Target/X86/X86CompressEVEX.cpp | 98 +- llvm/lib/Target/X86/X86ExpandPseudo.cpp | 11 +- .../Target/X86/X86FixupVectorConstants.cpp | 102 +- llvm/lib/Target/X86/X86ISelDAGToDAG.cpp | 61 +- llvm/lib/Target/X86/X86ISelLowering.cpp | 92 +- llvm/lib/Target/X86/X86InstrArithmetic.td | 16 +- llvm/lib/Target/X86/X86InstrCompiler.td | 274 +- llvm/lib/Target/X86/X86InstrInfo.cpp | 376 +- llvm/lib/Target/X86/X86InstrInfo.h | 14 +- llvm/lib/Target/X86/X86InstrMisc.td | 103 +- llvm/lib/Target/X86/X86InstrSSE.td | 8 +- llvm/lib/Target/X86/X86InstrShiftRotate.td | 1397 +- llvm/lib/Target/X86/X86InstrUtils.td | 69 +- .../X86LoadValueInjectionLoadHardening.cpp | 5 +- llvm/lib/Target/X86/X86LowerTileCopy.cpp | 6 +- llvm/lib/Target/X86/X86MCInstLower.cpp | 413 +- llvm/lib/Target/X86/X86PfmCounters.td | 14 +- .../X86/X86SpeculativeLoadHardening.cpp | 25 +- llvm/lib/Target/X86/X86TargetMachine.cpp | 3 + llvm/lib/Target/X86/X86TargetMachine.h | 6 + llvm/lib/Target/X86/X86TargetObjectFile.cpp | 2 +- llvm/lib/Target/X86/X86TargetObjectFile.h | 12 +- llvm/lib/TargetParser/AArch64TargetParser.cpp | 171 +- llvm/lib/TargetParser/ARMTargetParser.cpp | 3 + llvm/lib/TargetParser/Host.cpp | 7 + llvm/lib/TargetParser/TargetParser.cpp | 7 +- llvm/lib/TargetParser/Triple.cpp | 48 +- llvm/lib/TargetParser/X86TargetParser.cpp | 10 +- llvm/lib/TextAPI/Platform.cpp | 4 + llvm/lib/TextAPI/RecordsSlice.cpp | 5 +- llvm/lib/ToolDrivers/llvm-lib/LibDriver.cpp | 2 +- .../AggressiveInstCombine.cpp | 4 +- llvm/lib/Transforms/Coroutines/CoroEarly.cpp | 2 +- llvm/lib/Transforms/Coroutines/CoroFrame.cpp | 34 +- llvm/lib/Transforms/IPO/ArgumentPromotion.cpp | 2 +- .../Transforms/IPO/AttributorAttributes.cpp | 4 +- llvm/lib/Transforms/IPO/EmbedBitcodePass.cpp | 12 +- llvm/lib/Transforms/IPO/IROutliner.cpp | 3 +- .../IPO/MemProfContextDisambiguation.cpp | 18 +- .../lib/Transforms/IPO/SampleProfileProbe.cpp | 4 +- .../lib/Transforms/IPO/WholeProgramDevirt.cpp | 6 +- .../InstCombine/InstCombineAddSub.cpp | 6 + .../InstCombine/InstCombineAndOrXor.cpp | 7 + .../InstCombine/InstCombineCalls.cpp | 10 +- .../InstCombine/InstCombineCasts.cpp | 13 + .../InstCombine/InstCombineCompares.cpp | 3 + .../InstCombine/InstCombineInternal.h | 4 + .../InstCombine/InstCombineMulDivRem.cpp | 13 + .../InstCombine/InstCombineShifts.cpp | 16 +- .../InstCombine/InstructionCombining.cpp | 89 +- .../Instrumentation/AddressSanitizer.cpp | 5 +- .../Transforms/Instrumentation/CGProfile.cpp | 8 +- .../Instrumentation/GCOVProfiling.cpp | 4 +- .../Instrumentation/HWAddressSanitizer.cpp | 2 +- .../Instrumentation/MemorySanitizer.cpp | 31 +- .../Instrumentation/SanitizerCoverage.cpp | 4 +- .../Transforms/ObjCARC/DependencyAnalysis.cpp | 2 +- llvm/lib/Transforms/Scalar/ADCE.cpp | 5 + .../Transforms/Scalar/ConstantHoisting.cpp | 7 +- .../Scalar/ConstraintElimination.cpp | 13 +- .../Transforms/Scalar/DFAJumpThreading.cpp | 32 +- .../Scalar/DeadStoreElimination.cpp | 35 +- llvm/lib/Transforms/Scalar/LICM.cpp | 4 +- llvm/lib/Transforms/Scalar/LoopDeletion.cpp | 14 +- .../Transforms/Scalar/LoopStrengthReduce.cpp | 245 +- .../Transforms/Scalar/LoopVersioningLICM.cpp | 6 +- .../lib/Transforms/Scalar/MemCpyOptimizer.cpp | 6 +- .../Scalar/RewriteStatepointsForGC.cpp | 112 +- llvm/lib/Transforms/Scalar/SROA.cpp | 303 +- .../Scalar/SeparateConstOffsetFromGEP.cpp | 11 +- .../Scalar/StraightLineStrengthReduce.cpp | 3 +- llvm/lib/Transforms/Utils/BasicBlockUtils.cpp | 73 +- llvm/lib/Transforms/Utils/CodeExtractor.cpp | 15 +- .../Transforms/Utils/InjectTLIMappings.cpp | 1 + llvm/lib/Transforms/Utils/InlineFunction.cpp | 18 +- llvm/lib/Transforms/Utils/Local.cpp | 56 +- llvm/lib/Transforms/Utils/MemoryOpRemark.cpp | 7 +- llvm/lib/Transforms/Utils/ModuleUtils.cpp | 29 - llvm/lib/Transforms/Utils/MoveAutoInit.cpp | 8 +- llvm/lib/Transforms/Utils/NameAnonGlobals.cpp | 2 +- .../Utils/PromoteMemoryToRegister.cpp | 116 +- .../Utils/ScalarEvolutionExpander.cpp | 16 +- llvm/lib/Transforms/Utils/SimplifyCFG.cpp | 54 +- llvm/lib/Transforms/Utils/SimplifyIndVar.cpp | 2 +- .../lib/Transforms/Utils/SimplifyLibCalls.cpp | 8 +- llvm/lib/Transforms/Utils/ValueMapper.cpp | 12 +- .../Vectorize/LoopVectorizationPlanner.h | 11 +- .../Transforms/Vectorize/LoopVectorize.cpp | 69 +- .../Transforms/Vectorize/SLPVectorizer.cpp | 43 +- llvm/lib/Transforms/Vectorize/VPlan.cpp | 21 +- llvm/lib/Transforms/Vectorize/VPlan.h | 193 +- .../Transforms/Vectorize/VPlanHCFGBuilder.cpp | 2 +- .../lib/Transforms/Vectorize/VPlanRecipes.cpp | 21 +- .../Transforms/Vectorize/VPlanTransforms.cpp | 74 +- llvm/lib/WindowsDriver/MSVCPaths.cpp | 10 +- llvm/lib/XRay/Trace.cpp | 3 + llvm/tools/bugpoint/ExecutionDriver.cpp | 4 +- llvm/tools/bugpoint/Miscompilation.cpp | 17 +- llvm/tools/bugpoint/OptimizerDriver.cpp | 2 +- llvm/tools/bugpoint/ToolRunner.cpp | 4 +- llvm/tools/llc/NewPMDriver.cpp | 236 + llvm/tools/llc/NewPMDriver.h | 49 + llvm/tools/llc/llc.cpp | 84 +- llvm/tools/lli/ExecutionUtils.cpp | 122 - llvm/tools/lli/ExecutionUtils.h | 60 - llvm/tools/lli/lli.cpp | 135 +- llvm/tools/llvm-ar/llvm-ar.cpp | 2 - llvm/tools/llvm-cov/SourceCoverageView.cpp | 6 +- llvm/tools/llvm-cov/gcov.cpp | 10 +- llvm/tools/llvm-cxxfilt/llvm-cxxfilt.cpp | 2 - llvm/tools/llvm-diff/lib/DifferenceEngine.cpp | 8 +- llvm/tools/llvm-dwarfdump/llvm-dwarfdump.cpp | 28 +- llvm/tools/llvm-dwarfutil/DebugInfoLinker.cpp | 33 +- llvm/tools/llvm-dwarfutil/Options.h | 2 +- llvm/tools/llvm-dwarfutil/Options.td | 2 +- llvm/tools/llvm-dwarfutil/llvm-dwarfutil.cpp | 8 +- llvm/tools/llvm-dwp/llvm-dwp.cpp | 3 - llvm/tools/llvm-lto/llvm-lto.cpp | 2 +- llvm/tools/llvm-nm/llvm-nm.cpp | 2 - llvm/tools/llvm-objcopy/llvm-objcopy.cpp | 2 - llvm/tools/llvm-objdump/llvm-objdump.cpp | 102 +- llvm/tools/llvm-pdbutil/llvm-pdbutil.cpp | 2 +- llvm/tools/llvm-profdata/llvm-profdata.cpp | 75 +- llvm/tools/llvm-readobj/COFFImportDumper.cpp | 2 +- llvm/tools/llvm-readobj/llvm-readobj.cpp | 2 - llvm/tools/llvm-rtdyld/llvm-rtdyld.cpp | 11 +- llvm/tools/llvm-size/llvm-size.cpp | 2 - .../tools/llvm-symbolizer/llvm-symbolizer.cpp | 2 - llvm/tools/opt/opt.cpp | 2 +- llvm/utils/TableGen/CodeGenTarget.cpp | 1 + llvm/utils/TableGen/CodeGenTarget.h | 6 + llvm/utils/TableGen/DAGISelMatcherEmitter.cpp | 108 +- .../TableGen/GlobalISel/CodeExpander.cpp | 7 +- .../TableGen/GlobalISelCombinerEmitter.cpp | 11 +- llvm/utils/TableGen/GlobalISelEmitter.cpp | 43 +- llvm/utils/TableGen/GlobalISelMatchTable.cpp | 9 +- llvm/utils/TableGen/SubtargetEmitter.cpp | 23 + .../TableGen/X86CompressEVEXTablesEmitter.cpp | 34 +- openmp/runtime/src/include/omp_lib.h.var | 6 +- openmp/runtime/src/kmp_affinity.cpp | 25 +- openmp/runtime/src/kmp_barrier.cpp | 8 +- openmp/runtime/src/kmp_io.cpp | 19 - openmp/runtime/src/kmp_os.h | 16 + openmp/runtime/src/kmp_settings.cpp | 19 +- openmp/runtime/src/kmp_wait_release.h | 6 - openmp/runtime/src/z_Windows_NT_util.cpp | 3 +- 1191 files changed, 53530 insertions(+), 35943 deletions(-) create mode 100644 clang/include/clang/AST/APNumericStorage.h create mode 100644 clang/lib/AST/Interp/EvaluationResult.cpp create mode 100644 clang/lib/AST/Interp/EvaluationResult.h create mode 100644 compiler-rt/include/profile/instr_prof_interface.h create mode 100644 compiler-rt/lib/builtins/aarch64/sme-libc-routines.c create mode 100644 libcxx/include/__numeric/saturation_arithmetic.h create mode 100644 libcxx/modules/modules.json.in create mode 100644 libcxx/src/include/overridable_function.h create mode 100644 libcxx/vendor/llvm/default_assertion_handler.in create mode 100644 lldb/include/lldb/Utility/SupportFile.h create mode 100644 llvm/include/llvm/CodeGen/GlobalMerge.h rename llvm/{lib/DWARFLinker/Parallel => include/llvm/DWARFLinker}/IndexedValuesMap.h (80%) create mode 100644 llvm/include/llvm/Frontend/Offloading/OffloadWrapper.h create mode 100644 llvm/include/llvm/IR/VFABIDemangler.h create mode 100644 llvm/lib/DWARFLinker/DWARFLinkerBase.cpp create mode 100644 llvm/lib/Frontend/Offloading/OffloadWrapper.cpp rename llvm/lib/{Analysis/VFABIDemangling.cpp => IR/VFABIDemangler.cpp} (80%) create mode 100644 llvm/lib/Target/AArch64/AArch64Arm64ECCallLowering.cpp create mode 100644 llvm/lib/Target/AMDGPU/AMDGPUMarkLastScratchLoad.cpp create mode 100644 llvm/lib/Target/RISCV/RISCVSchedSiFiveP400.td create mode 100644 llvm/lib/Target/SPIRV/SPIRVStripConvergentIntrinsics.cpp create mode 100644 llvm/lib/Target/X86/X86CodeGenPassBuilder.cpp create mode 100644 llvm/tools/llc/NewPMDriver.cpp create mode 100644 llvm/tools/llc/NewPMDriver.h delete mode 100644 llvm/tools/lli/ExecutionUtils.cpp delete mode 100644 llvm/tools/lli/ExecutionUtils.h diff --git a/clang/include/clang/AST/APNumericStorage.h b/clang/include/clang/AST/APNumericStorage.h new file mode 100644 index 00000000000..95eddbcd86e --- /dev/null +++ b/clang/include/clang/AST/APNumericStorage.h @@ -0,0 +1,71 @@ +//===--- APNumericStorage.h - Store APInt/APFloat in ASTContext -*- C++ -*-===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +#ifndef LLVM_CLANG_AST_APNUMERICSTORAGE_H +#define LLVM_CLANG_AST_APNUMERICSTORAGE_H + +#include "llvm/ADT/APFloat.h" +#include "llvm/ADT/APInt.h" + +namespace clang { +class ASTContext; + +/// Used by IntegerLiteral/FloatingLiteral/EnumConstantDecl to store the +/// numeric without leaking memory. +/// +/// For large floats/integers, APFloat/APInt will allocate memory from the heap +/// to represent these numbers. Unfortunately, when we use a BumpPtrAllocator +/// to allocate IntegerLiteral/FloatingLiteral nodes the memory associated with +/// the APFloat/APInt values will never get freed. APNumericStorage uses +/// ASTContext's allocator for memory allocation. +class APNumericStorage { + union { + uint64_t VAL; ///< Used to store the <= 64 bits integer value. + uint64_t *pVal; ///< Used to store the >64 bits integer value. + }; + unsigned BitWidth; + + bool hasAllocation() const { return llvm::APInt::getNumWords(BitWidth) > 1; } + + APNumericStorage(const APNumericStorage &) = delete; + void operator=(const APNumericStorage &) = delete; + +protected: + APNumericStorage() : VAL(0), BitWidth(0) {} + + llvm::APInt getIntValue() const { + unsigned NumWords = llvm::APInt::getNumWords(BitWidth); + if (NumWords > 1) + return llvm::APInt(BitWidth, NumWords, pVal); + else + return llvm::APInt(BitWidth, VAL); + } + void setIntValue(const ASTContext &C, const llvm::APInt &Val); +}; + +class APIntStorage : private APNumericStorage { +public: + llvm::APInt getValue() const { return getIntValue(); } + void setValue(const ASTContext &C, const llvm::APInt &Val) { + setIntValue(C, Val); + } +}; + +class APFloatStorage : private APNumericStorage { +public: + llvm::APFloat getValue(const llvm::fltSemantics &Semantics) const { + return llvm::APFloat(Semantics, getIntValue()); + } + void setValue(const ASTContext &C, const llvm::APFloat &Val) { + setIntValue(C, Val.bitcastToAPInt()); + } +}; + +} // end namespace clang + +#endif // LLVM_CLANG_AST_APNUMERICSTORAGE_H diff --git a/clang/include/clang/AST/Decl.h b/clang/include/clang/AST/Decl.h index a807bcdd76b..f26fb5ad5f1 100644 --- a/clang/include/clang/AST/Decl.h +++ b/clang/include/clang/AST/Decl.h @@ -13,6 +13,7 @@ #ifndef LLVM_CLANG_AST_DECL_H #define LLVM_CLANG_AST_DECL_H +#include "clang/AST/APNumericStorage.h" #include "clang/AST/APValue.h" #include "clang/AST/ASTContextAllocate.h" #include "clang/AST/DeclAccessPair.h" @@ -2293,8 +2294,8 @@ public: /// Whether this virtual function is pure, i.e. makes the containing class /// abstract. - bool isPure() const { return FunctionDeclBits.IsPure; } - void setPure(bool P = true); + bool isPureVirtual() const { return FunctionDeclBits.IsPureVirtual; } + void setIsPureVirtual(bool P = true); /// Whether this templated function will be late parsed. bool isLateTemplateParsed() const { @@ -3251,15 +3252,16 @@ public: /// that is defined. For example, in "enum X {a,b}", each of a/b are /// EnumConstantDecl's, X is an instance of EnumDecl, and the type of a/b is a /// TagType for the X EnumDecl. -class EnumConstantDecl : public ValueDecl, public Mergeable { +class EnumConstantDecl : public ValueDecl, + public Mergeable, + public APIntStorage { Stmt *Init; // an integer constant expression - llvm::APSInt Val; // The value. + bool IsUnsigned; protected: - EnumConstantDecl(DeclContext *DC, SourceLocation L, + EnumConstantDecl(const ASTContext &C, DeclContext *DC, SourceLocation L, IdentifierInfo *Id, QualType T, Expr *E, - const llvm::APSInt &V) - : ValueDecl(EnumConstant, DC, L, Id, T), Init((Stmt*)E), Val(V) {} + const llvm::APSInt &V); public: friend class StmtIteratorBase; @@ -3272,10 +3274,15 @@ public: const Expr *getInitExpr() const { return (const Expr*) Init; } Expr *getInitExpr() { return (Expr*) Init; } - const llvm::APSInt &getInitVal() const { return Val; } + llvm::APSInt getInitVal() const { + return llvm::APSInt(getValue(), IsUnsigned); + } void setInitExpr(Expr *E) { Init = (Stmt*) E; } - void setInitVal(const llvm::APSInt &V) { Val = V; } + void setInitVal(const ASTContext &C, const llvm::APSInt &V) { + setValue(C, V); + IsUnsigned = V.isUnsigned(); + } SourceRange getSourceRange() const override LLVM_READONLY; diff --git a/clang/include/clang/AST/DeclBase.h b/clang/include/clang/AST/DeclBase.h index 5b1038582bc..9a4736019d1 100644 --- a/clang/include/clang/AST/DeclBase.h +++ b/clang/include/clang/AST/DeclBase.h @@ -548,17 +548,18 @@ public: return hasAttrs() ? getAttrs().end() : nullptr; } - template - void dropAttr() { + template void dropAttrs() { if (!HasAttrs) return; AttrVec &Vec = getAttrs(); - llvm::erase_if(Vec, [](Attr *A) { return isa(A); }); + llvm::erase_if(Vec, [](Attr *A) { return isa(A); }); if (Vec.empty()) HasAttrs = false; } + template void dropAttr() { dropAttrs(); } + template llvm::iterator_range> specific_attrs() const { return llvm::make_range(specific_attr_begin(), specific_attr_end()); @@ -1707,7 +1708,7 @@ class DeclContext { LLVM_PREFERRED_TYPE(bool) uint64_t IsVirtualAsWritten : 1; LLVM_PREFERRED_TYPE(bool) - uint64_t IsPure : 1; + uint64_t IsPureVirtual : 1; LLVM_PREFERRED_TYPE(bool) uint64_t HasInheritedPrototype : 1; LLVM_PREFERRED_TYPE(bool) diff --git a/clang/include/clang/AST/DeclCXX.h b/clang/include/clang/AST/DeclCXX.h index 648f5f94640..9cebaff63bb 100644 --- a/clang/include/clang/AST/DeclCXX.h +++ b/clang/include/clang/AST/DeclCXX.h @@ -266,7 +266,7 @@ class CXXRecordDecl : public RecordDecl { friend class LambdaExpr; friend class ODRDiagsEmitter; - friend void FunctionDecl::setPure(bool); + friend void FunctionDecl::setIsPureVirtual(bool); friend void TagDecl::startDefinition(); /// Values used in DefinitionData fields to represent special members. @@ -1439,31 +1439,20 @@ public: /// Determine whether this class is a literal type. /// - /// C++11 [basic.types]p10: + /// C++20 [basic.types]p10: /// A class type that has all the following properties: - /// - it has a trivial destructor - /// - every constructor call and full-expression in the - /// brace-or-equal-intializers for non-static data members (if any) is - /// a constant expression. - /// - it is an aggregate type or has at least one constexpr constructor - /// or constructor template that is not a copy or move constructor, and - /// - all of its non-static data members and base classes are of literal - /// types - /// - /// We resolve DR1361 by ignoring the second bullet. We resolve DR1452 by - /// treating types with trivial default constructors as literal types. - /// - /// Only in C++17 and beyond, are lambdas literal types. - bool isLiteral() const { - const LangOptions &LangOpts = getLangOpts(); - return (LangOpts.CPlusPlus20 ? hasConstexprDestructor() - : hasTrivialDestructor()) && - (!isLambda() || LangOpts.CPlusPlus17) && - !hasNonLiteralTypeFieldsOrBases() && - (isAggregate() || isLambda() || - hasConstexprNonCopyMoveConstructor() || - hasTrivialDefaultConstructor()); - } + /// - it has a constexpr destructor + /// - all of its non-static non-variant data members and base classes + /// are of non-volatile literal types, and it: + /// - is a closure type + /// - is an aggregate union type that has either no variant members + /// or at least one variant member of non-volatile literal type + /// - is a non-union aggregate type for which each of its anonymous + /// union members satisfies the above requirements for an aggregate + /// union type, or + /// - has at least one constexpr constructor or constructor template + /// that is not a copy or move constructor. + bool isLiteral() const; /// Determine whether this is a structural type. bool isStructural() const { @@ -2121,7 +2110,7 @@ public: // Member function is virtual if it is marked explicitly so, or if it is // declared in __interface -- then it is automatically pure virtual. - if (CD->isVirtualAsWritten() || CD->isPure()) + if (CD->isVirtualAsWritten() || CD->isPureVirtual()) return true; return CD->size_overridden_methods() != 0; diff --git a/clang/include/clang/AST/Expr.h b/clang/include/clang/AST/Expr.h index a41f2d66b37..9820bd11da8 100644 --- a/clang/include/clang/AST/Expr.h +++ b/clang/include/clang/AST/Expr.h @@ -13,6 +13,7 @@ #ifndef LLVM_CLANG_AST_EXPR_H #define LLVM_CLANG_AST_EXPR_H +#include "clang/AST/APNumericStorage.h" #include "clang/AST/APValue.h" #include "clang/AST/ASTVector.h" #include "clang/AST/ComputeDependence.h" @@ -1135,7 +1136,6 @@ public: return ConstantExprBits.APValueKind != APValue::None; } APValue getAPValueResult() const; - APValue &getResultAsAPValue() const { return APValueResult(); } llvm::APSInt getResultAsAPSInt() const; // Iterators child_range children() { return child_range(&SubExpr, &SubExpr+1); } @@ -1479,57 +1479,6 @@ public: } }; -/// Used by IntegerLiteral/FloatingLiteral to store the numeric without -/// leaking memory. -/// -/// For large floats/integers, APFloat/APInt will allocate memory from the heap -/// to represent these numbers. Unfortunately, when we use a BumpPtrAllocator -/// to allocate IntegerLiteral/FloatingLiteral nodes the memory associated with -/// the APFloat/APInt values will never get freed. APNumericStorage uses -/// ASTContext's allocator for memory allocation. -class APNumericStorage { - union { - uint64_t VAL; ///< Used to store the <= 64 bits integer value. - uint64_t *pVal; ///< Used to store the >64 bits integer value. - }; - unsigned BitWidth; - - bool hasAllocation() const { return llvm::APInt::getNumWords(BitWidth) > 1; } - - APNumericStorage(const APNumericStorage &) = delete; - void operator=(const APNumericStorage &) = delete; - -protected: - APNumericStorage() : VAL(0), BitWidth(0) { } - - llvm::APInt getIntValue() const { - unsigned NumWords = llvm::APInt::getNumWords(BitWidth); - if (NumWords > 1) - return llvm::APInt(BitWidth, NumWords, pVal); - else - return llvm::APInt(BitWidth, VAL); - } - void setIntValue(const ASTContext &C, const llvm::APInt &Val); -}; - -class APIntStorage : private APNumericStorage { -public: - llvm::APInt getValue() const { return getIntValue(); } - void setValue(const ASTContext &C, const llvm::APInt &Val) { - setIntValue(C, Val); - } -}; - -class APFloatStorage : private APNumericStorage { -public: - llvm::APFloat getValue(const llvm::fltSemantics &Semantics) const { - return llvm::APFloat(Semantics, getIntValue()); - } - void setValue(const ASTContext &C, const llvm::APFloat &Val) { - setIntValue(C, Val.bitcastToAPInt()); - } -}; - class IntegerLiteral : public Expr, public APIntStorage { SourceLocation Loc; @@ -4806,6 +4755,17 @@ public: return T->getStmtClass() == SourceLocExprClass; } + static bool MayBeDependent(SourceLocIdentKind Kind) { + switch (Kind) { + case SourceLocIdentKind::Function: + case SourceLocIdentKind::FuncSig: + case SourceLocIdentKind::SourceLocStruct: + return true; + default: + return false; + } + } + private: friend class ASTStmtReader; }; diff --git a/clang/include/clang/AST/ExprCXX.h b/clang/include/clang/AST/ExprCXX.h index 24278016431..9a7c632c36c 100644 --- a/clang/include/clang/AST/ExprCXX.h +++ b/clang/include/clang/AST/ExprCXX.h @@ -2210,14 +2210,11 @@ enum class CXXNewInitializationStyle { /// New-expression has no initializer as written. None, - /// New-expression has no written initializer, but has an implicit one. - Implicit, - /// New-expression has a C++98 paren-delimited initializer. - Call, + Parens, /// New-expression has a C++11 list-initializer. - List + Braces }; /// Represents a new-expression for memory allocation and constructor @@ -2388,17 +2385,7 @@ public: bool isGlobalNew() const { return CXXNewExprBits.IsGlobalNew; } /// Whether this new-expression has any initializer at all. - bool hasInitializer() const { - switch (getInitializationStyle()) { - case CXXNewInitializationStyle::None: - return false; - case CXXNewInitializationStyle::Implicit: - case CXXNewInitializationStyle::Call: - case CXXNewInitializationStyle::List: - return true; - } - llvm_unreachable("Unknown initializer"); - } + bool hasInitializer() const { return CXXNewExprBits.HasInitializer; } /// The kind of initializer this new-expression has. CXXNewInitializationStyle getInitializationStyle() const { diff --git a/clang/include/clang/AST/ODRHash.h b/clang/include/clang/AST/ODRHash.h index cedf644520f..a1caa6d39a8 100644 --- a/clang/include/clang/AST/ODRHash.h +++ b/clang/include/clang/AST/ODRHash.h @@ -25,6 +25,7 @@ namespace clang { +class APValue; class Decl; class IdentifierInfo; class NestedNameSpecifier; @@ -101,6 +102,8 @@ public: // Save booleans until the end to lower the size of data to process. void AddBoolean(bool value); + void AddStructuralValue(const APValue &); + static bool isSubDeclToBeProcessed(const Decl *D, const DeclContext *Parent); private: diff --git a/clang/include/clang/AST/PropertiesBase.td b/clang/include/clang/AST/PropertiesBase.td index d86c4eba6a2..0270c086d06 100644 --- a/clang/include/clang/AST/PropertiesBase.td +++ b/clang/include/clang/AST/PropertiesBase.td @@ -808,6 +808,20 @@ let Class = PropertyTypeCase in { return TemplateArgument(ctx, value, type, isDefaulted); }]>; } +let Class = PropertyTypeCase in { + def : Property<"value", APValue> { + let Read = [{ node.getAsStructuralValue() }]; + } + def : Property<"type", QualType> { + let Read = [{ node.getStructuralValueType() }]; + } + def : Property<"isDefaulted", Bool> { + let Read = [{ node.getIsDefaulted() }]; + } + def : Creator<[{ + return TemplateArgument(ctx, type, value, isDefaulted); + }]>; +} let Class = PropertyTypeCase in { def : Property<"name", TemplateName> { let Read = [{ node.getAsTemplateOrTemplatePattern() }]; diff --git a/clang/include/clang/AST/RecursiveASTVisitor.h b/clang/include/clang/AST/RecursiveASTVisitor.h index 8f2714e142b..2aee6a94714 100644 --- a/clang/include/clang/AST/RecursiveASTVisitor.h +++ b/clang/include/clang/AST/RecursiveASTVisitor.h @@ -850,6 +850,7 @@ bool RecursiveASTVisitor::TraverseTemplateArgument( case TemplateArgument::Declaration: case TemplateArgument::Integral: case TemplateArgument::NullPtr: + case TemplateArgument::StructuralValue: return true; case TemplateArgument::Type: @@ -882,6 +883,7 @@ bool RecursiveASTVisitor::TraverseTemplateArgumentLoc( case TemplateArgument::Declaration: case TemplateArgument::Integral: case TemplateArgument::NullPtr: + case TemplateArgument::StructuralValue: return true; case TemplateArgument::Type: { diff --git a/clang/include/clang/AST/Stmt.h b/clang/include/clang/AST/Stmt.h index e1fde24e647..55eca4007d1 100644 --- a/clang/include/clang/AST/Stmt.h +++ b/clang/include/clang/AST/Stmt.h @@ -868,9 +868,11 @@ protected: LLVM_PREFERRED_TYPE(bool) unsigned UsualArrayDeleteWantsSize : 1; - /// What kind of initializer do we have? Could be none, parens, or braces. - /// In storage, we distinguish between "none, and no initializer expr", and - /// "none, but an implicit initializer expr". + // Is initializer expr present? + LLVM_PREFERRED_TYPE(bool) + unsigned HasInitializer : 1; + + /// What kind of initializer syntax used? Could be none, parens, or braces. LLVM_PREFERRED_TYPE(CXXNewInitializationStyle) unsigned StoredInitializationStyle : 2; diff --git a/clang/include/clang/AST/TemplateArgumentVisitor.h b/clang/include/clang/AST/TemplateArgumentVisitor.h index 190aa97adf4..cf0d3220158 100644 --- a/clang/include/clang/AST/TemplateArgumentVisitor.h +++ b/clang/include/clang/AST/TemplateArgumentVisitor.h @@ -37,6 +37,7 @@ public: DISPATCH(Declaration); DISPATCH(NullPtr); DISPATCH(Integral); + DISPATCH(StructuralValue); DISPATCH(Template); DISPATCH(TemplateExpansion); DISPATCH(Expression); @@ -59,6 +60,7 @@ public: VISIT_METHOD(Declaration); VISIT_METHOD(NullPtr); VISIT_METHOD(Integral); + VISIT_METHOD(StructuralValue); VISIT_METHOD(Template); VISIT_METHOD(TemplateExpansion); VISIT_METHOD(Expression); diff --git a/clang/include/clang/AST/TemplateBase.h b/clang/include/clang/AST/TemplateBase.h index b7cd71f17c9..fea2c8ccfee 100644 --- a/clang/include/clang/AST/TemplateBase.h +++ b/clang/include/clang/AST/TemplateBase.h @@ -50,6 +50,7 @@ template <> struct PointerLikeTypeTraits { namespace clang { +class APValue; class ASTContext; class Expr; struct PrintingPolicy; @@ -80,6 +81,13 @@ public: /// that was provided for an integral non-type template parameter. Integral, + /// The template argument is a non-type template argument that can't be + /// represented by the special-case Declaration, NullPtr, or Integral + /// forms. These values are only ever produced by constant evaluation, + /// so cannot be dependent. + /// TODO: merge Declaration, NullPtr and Integral into this? + StructuralValue, + /// The template argument is a template name that was provided for a /// template template parameter. Template, @@ -130,6 +138,14 @@ private: }; void *Type; }; + struct V { + LLVM_PREFERRED_TYPE(ArgKind) + unsigned Kind : 31; + LLVM_PREFERRED_TYPE(bool) + unsigned IsDefaulted : 1; + APValue *Value; + void *Type; + }; struct A { LLVM_PREFERRED_TYPE(ArgKind) unsigned Kind : 31; @@ -156,11 +172,19 @@ private: union { struct DA DeclArg; struct I Integer; + struct V Value; struct A Args; struct TA TemplateArg; struct TV TypeOrValue; }; + void initFromType(QualType T, bool IsNullPtr, bool IsDefaulted); + void initFromDeclaration(ValueDecl *D, QualType QT, bool IsDefaulted); + void initFromIntegral(const ASTContext &Ctx, const llvm::APSInt &Value, + QualType Type, bool IsDefaulted); + void initFromStructural(const ASTContext &Ctx, QualType Type, + const APValue &V, bool IsDefaulted); + public: /// Construct an empty, invalid template argument. constexpr TemplateArgument() : TypeOrValue({Null, 0, /* IsDefaulted */ 0}) {} @@ -168,25 +192,22 @@ public: /// Construct a template type argument. TemplateArgument(QualType T, bool isNullPtr = false, bool IsDefaulted = false) { - TypeOrValue.Kind = isNullPtr ? NullPtr : Type; - TypeOrValue.IsDefaulted = IsDefaulted; - TypeOrValue.V = reinterpret_cast(T.getAsOpaquePtr()); + initFromType(T, isNullPtr, IsDefaulted); } - /// Construct a template argument that refers to a - /// declaration, which is either an external declaration or a - /// template declaration. + /// Construct a template argument that refers to a (non-dependent) + /// declaration. TemplateArgument(ValueDecl *D, QualType QT, bool IsDefaulted = false) { - assert(D && "Expected decl"); - DeclArg.Kind = Declaration; - DeclArg.IsDefaulted = IsDefaulted; - DeclArg.QT = QT.getAsOpaquePtr(); - DeclArg.D = D; + initFromDeclaration(D, QT, IsDefaulted); } /// Construct an integral constant template argument. The memory to /// store the value is allocated with Ctx. - TemplateArgument(ASTContext &Ctx, const llvm::APSInt &Value, QualType Type, + TemplateArgument(const ASTContext &Ctx, const llvm::APSInt &Value, + QualType Type, bool IsDefaulted = false); + + /// Construct a template argument from an arbitrary constant value. + TemplateArgument(const ASTContext &Ctx, QualType Type, const APValue &Value, bool IsDefaulted = false); /// Construct an integral constant template argument with the same @@ -297,7 +318,7 @@ public: /// Retrieve the type for a type template argument. QualType getAsType() const { assert(getKind() == Type && "Unexpected kind"); - return QualType::getFromOpaquePtr(reinterpret_cast(TypeOrValue.V)); + return QualType::getFromOpaquePtr(reinterpret_cast(TypeOrValue.V)); } /// Retrieve the declaration for a declaration non-type @@ -315,7 +336,7 @@ public: /// Retrieve the type for null non-type template argument. QualType getNullPtrType() const { assert(getKind() == NullPtr && "Unexpected kind"); - return QualType::getFromOpaquePtr(reinterpret_cast(TypeOrValue.V)); + return QualType::getFromOpaquePtr(reinterpret_cast(TypeOrValue.V)); } /// Retrieve the template name for a template name argument. @@ -371,6 +392,14 @@ public: /// default template parameter. bool getIsDefaulted() const { return (bool)TypeOrValue.IsDefaulted; } + /// Get the value of a StructuralValue. + const APValue &getAsStructuralValue() const { return *Value.Value; } + + /// Get the type of a StructuralValue. + QualType getStructuralValueType() const { + return QualType::getFromOpaquePtr(Value.Type); + } + /// If this is a non-type template argument, get its type. Otherwise, /// returns a null QualType. QualType getNonTypeTemplateArgumentType() const; @@ -516,6 +545,7 @@ public: assert(Argument.getKind() == TemplateArgument::NullPtr || Argument.getKind() == TemplateArgument::Integral || Argument.getKind() == TemplateArgument::Declaration || + Argument.getKind() == TemplateArgument::StructuralValue || Argument.getKind() == TemplateArgument::Expression); } @@ -541,13 +571,9 @@ public: /// - Fetches the full source range of the argument. SourceRange getSourceRange() const LLVM_READONLY; - const TemplateArgument &getArgument() const { - return Argument; - } + const TemplateArgument &getArgument() const { return Argument; } - TemplateArgumentLocInfo getLocInfo() const { - return LocInfo; - } + TemplateArgumentLocInfo getLocInfo() const { return LocInfo; } TypeSourceInfo *getTypeSourceInfo() const { if (Argument.getKind() != TemplateArgument::Type) @@ -575,6 +601,11 @@ public: return LocInfo.getAsExpr(); } + Expr *getSourceStructuralValueExpression() const { + assert(Argument.getKind() == TemplateArgument::StructuralValue); + return LocInfo.getAsExpr(); + } + NestedNameSpecifierLoc getTemplateQualifierLoc() const { if (Argument.getKind() != TemplateArgument::Template && Argument.getKind() != TemplateArgument::TemplateExpansion) @@ -606,8 +637,7 @@ class TemplateArgumentListInfo { public: TemplateArgumentListInfo() = default; - TemplateArgumentListInfo(SourceLocation LAngleLoc, - SourceLocation RAngleLoc) + TemplateArgumentListInfo(SourceLocation LAngleLoc, SourceLocation RAngleLoc) : LAngleLoc(LAngleLoc), RAngleLoc(RAngleLoc) {} // This can leak if used in an AST node, use ASTTemplateArgumentListInfo @@ -626,21 +656,15 @@ public: return Arguments.data(); } - llvm::ArrayRef arguments() const { - return Arguments; - } + llvm::ArrayRef arguments() const { return Arguments; } const TemplateArgumentLoc &operator[](unsigned I) const { return Arguments[I]; } - TemplateArgumentLoc &operator[](unsigned I) { - return Arguments[I]; - } + TemplateArgumentLoc &operator[](unsigned I) { return Arguments[I]; } - void addArgument(const TemplateArgumentLoc &Loc) { - Arguments.push_back(Loc); - } + void addArgument(const TemplateArgumentLoc &Loc) { Arguments.push_back(Loc); } }; /// Represents an explicit template argument list in C++, e.g., diff --git a/clang/include/clang/AST/Type.h b/clang/include/clang/AST/Type.h index d4e5310fb3a..ea425791fc9 100644 --- a/clang/include/clang/AST/Type.h +++ b/clang/include/clang/AST/Type.h @@ -4029,19 +4029,6 @@ public: /// because TrailingObjects cannot handle repeated types. struct ExceptionType { QualType Type; }; - /// The AArch64 SME ACLE (Arm C/C++ Language Extensions) define a number - /// of function type attributes that can be set on function types, including - /// function pointers. - enum AArch64SMETypeAttributes : unsigned { - SME_NormalFunction = 0, - SME_PStateSMEnabledMask = 1 << 0, - SME_PStateSMCompatibleMask = 1 << 1, - SME_PStateZASharedMask = 1 << 2, - SME_PStateZAPreservedMask = 1 << 3, - SME_AttributeMask = 0b111'111 // We only support maximum 6 bits because of the - // bitmask in FunctionTypeExtraBitfields. - }; - /// A simple holder for various uncommon bits which do not fit in /// FunctionTypeBitfields. Aligned to alignof(void *) to maintain the /// alignment of subsequent objects in TrailingObjects. @@ -4051,11 +4038,57 @@ public: /// [implimits] 8 bits would be enough here. unsigned NumExceptionType : 10; + LLVM_PREFERRED_TYPE(bool) + unsigned HasArmTypeAttributes : 1; + + FunctionTypeExtraBitfields() + : NumExceptionType(0), HasArmTypeAttributes(false) {} + }; + + /// The AArch64 SME ACLE (Arm C/C++ Language Extensions) define a number + /// of function type attributes that can be set on function types, including + /// function pointers. + enum AArch64SMETypeAttributes : unsigned { + SME_NormalFunction = 0, + SME_PStateSMEnabledMask = 1 << 0, + SME_PStateSMCompatibleMask = 1 << 1, + + // Describes the value of the state using ArmStateValue. + SME_ZAShift = 2, + SME_ZAMask = 0b111 << SME_ZAShift, + SME_ZT0Shift = 5, + SME_ZT0Mask = 0b111 << SME_ZT0Shift, + + SME_AttributeMask = + 0b111'111'11 // We can't support more than 8 bits because of + // the bitmask in FunctionTypeExtraBitfields. + }; + + enum ArmStateValue : unsigned { + ARM_None = 0, + ARM_Preserves = 1, + ARM_In = 2, + ARM_Out = 3, + ARM_InOut = 4, + }; + + static ArmStateValue getArmZAState(unsigned AttrBits) { + return (ArmStateValue)((AttrBits & SME_ZAMask) >> SME_ZAShift); + } + + static ArmStateValue getArmZT0State(unsigned AttrBits) { + return (ArmStateValue)((AttrBits & SME_ZT0Mask) >> SME_ZT0Shift); + } + + /// A holder for Arm type attributes as described in the Arm C/C++ + /// Language extensions which are not particularly common to all + /// types and therefore accounted separately from FunctionTypeBitfields. + struct alignas(void *) FunctionTypeArmAttributes { /// Any AArch64 SME ACLE type attributes that need to be propagated /// on declarations and function pointers. - unsigned AArch64SMEAttributes : 6; - FunctionTypeExtraBitfields() - : NumExceptionType(0), AArch64SMEAttributes(SME_NormalFunction) {} + unsigned AArch64SMEAttributes : 8; + + FunctionTypeArmAttributes() : AArch64SMEAttributes(SME_NormalFunction) {} }; protected: @@ -4154,7 +4187,8 @@ class FunctionProtoType final public llvm::FoldingSetNode, private llvm::TrailingObjects< FunctionProtoType, QualType, SourceLocation, - FunctionType::FunctionTypeExtraBitfields, FunctionType::ExceptionType, + FunctionType::FunctionTypeExtraBitfields, + FunctionType::FunctionTypeArmAttributes, FunctionType::ExceptionType, Expr *, FunctionDecl *, FunctionType::ExtParameterInfo, Qualifiers> { friend class ASTContext; // ASTContext creates these. friend TrailingObjects; @@ -4238,7 +4272,7 @@ public: FunctionType::ExtInfo ExtInfo; unsigned Variadic : 1; unsigned HasTrailingReturn : 1; - unsigned AArch64SMEAttributes : 6; + unsigned AArch64SMEAttributes : 8; Qualifiers TypeQuals; RefQualifierKind RefQualifier = RQ_None; ExceptionSpecInfo ExceptionSpec; @@ -4261,7 +4295,11 @@ public: bool requiresFunctionProtoTypeExtraBitfields() const { return ExceptionSpec.Type == EST_Dynamic || - AArch64SMEAttributes != SME_NormalFunction; + requiresFunctionProtoTypeArmAttributes(); + } + + bool requiresFunctionProtoTypeArmAttributes() const { + return AArch64SMEAttributes != SME_NormalFunction; } void setArmSMEAttribute(AArch64SMETypeAttributes Kind, bool Enable = true) { @@ -4281,6 +4319,10 @@ private: return isVariadic(); } + unsigned numTrailingObjects(OverloadToken) const { + return hasArmTypeAttributes(); + } + unsigned numTrailingObjects(OverloadToken) const { return hasExtraBitfields(); } @@ -4369,6 +4411,12 @@ private: } + bool hasArmTypeAttributes() const { + return FunctionTypeBits.HasExtraBitfields && + getTrailingObjects() + ->HasArmTypeAttributes; + } + bool hasExtQualifiers() const { return FunctionTypeBits.HasExtQuals; } @@ -4580,9 +4628,9 @@ public: /// Return a bitmask describing the SME attributes on the function type, see /// AArch64SMETypeAttributes for their values. unsigned getAArch64SMEAttributes() const { - if (!hasExtraBitfields()) + if (!hasArmTypeAttributes()) return SME_NormalFunction; - return getTrailingObjects() + return getTrailingObjects() ->AArch64SMEAttributes; } diff --git a/clang/include/clang/ASTMatchers/ASTMatchers.h b/clang/include/clang/ASTMatchers/ASTMatchers.h index 82a26356c58..dc1f49525a0 100644 --- a/clang/include/clang/ASTMatchers/ASTMatchers.h +++ b/clang/include/clang/ASTMatchers/ASTMatchers.h @@ -2062,6 +2062,18 @@ extern const internal::VariadicDynCastAllOfMatcher extern const internal::VariadicDynCastAllOfMatcher cxxOperatorCallExpr; +/// Matches C++17 fold expressions. +/// +/// Example matches `(0 + ... + args)`: +/// \code +/// template +/// auto sum(Args... args) { +/// return (0 + ... + args); +/// } +/// \endcode +extern const internal::VariadicDynCastAllOfMatcher + cxxFoldExpr; + /// Matches rewritten binary operators /// /// Example matches use of "<": @@ -3881,7 +3893,7 @@ AST_MATCHER_P(ObjCMessageExpr, numSelectorArgs, unsigned, N) { return Node.getSelector().getNumArgs() == N; } -/// Matches if the call expression's callee expression matches. +/// Matches if the call or fold expression's callee expression matches. /// /// Given /// \code @@ -3893,13 +3905,32 @@ AST_MATCHER_P(ObjCMessageExpr, numSelectorArgs, unsigned, N) { /// with callee(...) /// matching this->x, x, y.x, f respectively /// +/// Given +/// \code +/// template +/// auto sum(Args... args) { +/// return (0 + ... + args); +/// } +/// +/// template +/// auto multiply(Args... args) { +/// return (args * ... * 1); +/// } +/// \endcode +/// cxxFoldExpr(callee(expr())) +/// matches (args * ... * 1) +/// with callee(...) +/// matching * +/// /// Note: Callee cannot take the more general internal::Matcher /// because this introduces ambiguous overloads with calls to Callee taking a /// internal::Matcher, as the matcher hierarchy is purely /// implemented in terms of implicit casts. -AST_MATCHER_P(CallExpr, callee, internal::Matcher, - InnerMatcher) { - const Expr *ExprNode = Node.getCallee(); +AST_POLYMORPHIC_MATCHER_P_OVERLOAD(callee, + AST_POLYMORPHIC_SUPPORTED_TYPES(CallExpr, + CXXFoldExpr), + internal::Matcher, InnerMatcher, 0) { + const auto *ExprNode = Node.getCallee(); return (ExprNode != nullptr && InnerMatcher.matches(*ExprNode, Finder, Builder)); } @@ -4532,6 +4563,121 @@ AST_POLYMORPHIC_MATCHER_P2(hasArgument, return InnerMatcher.matches(*Arg->IgnoreParenImpCasts(), Finder, Builder); } +/// Matches the operand that does not contain the parameter pack. +/// +/// Example matches `(0 + ... + args)` and `(args * ... * 1)` +/// (matcher = cxxFoldExpr(hasFoldInit(expr()))) +/// with hasFoldInit(...) +/// matching `0` and `1` respectively +/// \code +/// template +/// auto sum(Args... args) { +/// return (0 + ... + args); +/// } +/// +/// template +/// auto multiply(Args... args) { +/// return (args * ... * 1); +/// } +/// \endcode +AST_MATCHER_P(CXXFoldExpr, hasFoldInit, ast_matchers::internal::Matcher, + InnerMacher) { + const auto *const Init = Node.getInit(); + return Init && InnerMacher.matches(*Init, Finder, Builder); +} + +/// Matches the operand that contains the parameter pack. +/// +/// Example matches `(0 + ... + args)` +/// (matcher = cxxFoldExpr(hasPattern(expr()))) +/// with hasPattern(...) +/// matching `args` +/// \code +/// template +/// auto sum(Args... args) { +/// return (0 + ... + args); +/// } +/// +/// template +/// auto multiply(Args... args) { +/// return (args * ... * 1); +/// } +/// \endcode +AST_MATCHER_P(CXXFoldExpr, hasPattern, ast_matchers::internal::Matcher, + InnerMacher) { + const Expr *const Pattern = Node.getPattern(); + return Pattern && InnerMacher.matches(*Pattern, Finder, Builder); +} + +/// Matches right-folding fold expressions. +/// +/// Example matches `(args * ... * 1)` +/// (matcher = cxxFoldExpr(isRightFold())) +/// \code +/// template +/// auto sum(Args... args) { +/// return (0 + ... + args); +/// } +/// +/// template +/// auto multiply(Args... args) { +/// return (args * ... * 1); +/// } +/// \endcode +AST_MATCHER(CXXFoldExpr, isRightFold) { return Node.isRightFold(); } + +/// Matches left-folding fold expressions. +/// +/// Example matches `(0 + ... + args)` +/// (matcher = cxxFoldExpr(isLeftFold())) +/// \code +/// template +/// auto sum(Args... args) { +/// return (0 + ... + args); +/// } +/// +/// template +/// auto multiply(Args... args) { +/// return (args * ... * 1); +/// } +/// \endcode +AST_MATCHER(CXXFoldExpr, isLeftFold) { return Node.isLeftFold(); } + +/// Matches unary fold expressions, i.e. fold expressions without an +/// initializer. +/// +/// Example matches `(args * ...)` +/// (matcher = cxxFoldExpr(isUnaryFold())) +/// \code +/// template +/// auto sum(Args... args) { +/// return (0 + ... + args); +/// } +/// +/// template +/// auto multiply(Args... args) { +/// return (args * ...); +/// } +/// \endcode +AST_MATCHER(CXXFoldExpr, isUnaryFold) { return Node.getInit() == nullptr; } + +/// Matches binary fold expressions, i.e. fold expressions with an initializer. +/// +/// Example matches `(0 + ... + args)` +/// (matcher = cxxFoldExpr(isBinaryFold())) +/// \code +/// template +/// auto sum(Args... args) { +/// return (0 + ... + args); +/// } +/// +/// template +/// auto multiply(Args... args) { +/// return (args * ...); +/// } +/// \endcode +AST_MATCHER(CXXFoldExpr, isBinaryFold) { return Node.getInit() != nullptr; } + /// Matches the n'th item of an initializer list expression. /// /// Example matches y. @@ -5709,17 +5855,27 @@ AST_POLYMORPHIC_MATCHER_P_OVERLOAD(equals, .matchesNode(Node); } -/// Matches the operator Name of operator expressions (binary or -/// unary). +/// Matches the operator Name of operator expressions and fold expressions +/// (binary or unary). /// /// Example matches a || b (matcher = binaryOperator(hasOperatorName("||"))) /// \code /// !(a || b) /// \endcode +/// +/// Example matches `(0 + ... + args)` +/// (matcher = cxxFoldExpr(hasOperatorName("+"))) +/// \code +/// template +/// auto sum(Args... args) { +/// return (0 + ... + args); +/// } +/// \endcode AST_POLYMORPHIC_MATCHER_P( hasOperatorName, AST_POLYMORPHIC_SUPPORTED_TYPES(BinaryOperator, CXXOperatorCallExpr, - CXXRewrittenBinaryOperator, UnaryOperator), + CXXRewrittenBinaryOperator, CXXFoldExpr, + UnaryOperator), std::string, Name) { if (std::optional OpName = internal::getOpName(Node)) return *OpName == Name; @@ -5789,11 +5945,12 @@ AST_POLYMORPHIC_MATCHER( /// \code /// a || b /// \endcode -AST_POLYMORPHIC_MATCHER_P(hasLHS, - AST_POLYMORPHIC_SUPPORTED_TYPES( - BinaryOperator, CXXOperatorCallExpr, - CXXRewrittenBinaryOperator, ArraySubscriptExpr), - internal::Matcher, InnerMatcher) { +AST_POLYMORPHIC_MATCHER_P( + hasLHS, + AST_POLYMORPHIC_SUPPORTED_TYPES(BinaryOperator, CXXOperatorCallExpr, + CXXRewrittenBinaryOperator, + ArraySubscriptExpr, CXXFoldExpr), + internal::Matcher, InnerMatcher) { const Expr *LeftHandSide = internal::getLHS(Node); return (LeftHandSide != nullptr && InnerMatcher.matches(*LeftHandSide, Finder, Builder)); @@ -5805,29 +5962,31 @@ AST_POLYMORPHIC_MATCHER_P(hasLHS, /// \code /// a || b /// \endcode -AST_POLYMORPHIC_MATCHER_P(hasRHS, - AST_POLYMORPHIC_SUPPORTED_TYPES( - BinaryOperator, CXXOperatorCallExpr, - CXXRewrittenBinaryOperator, ArraySubscriptExpr), - internal::Matcher, InnerMatcher) { +AST_POLYMORPHIC_MATCHER_P( + hasRHS, + AST_POLYMORPHIC_SUPPORTED_TYPES(BinaryOperator, CXXOperatorCallExpr, + CXXRewrittenBinaryOperator, + ArraySubscriptExpr, CXXFoldExpr), + internal::Matcher, InnerMatcher) { const Expr *RightHandSide = internal::getRHS(Node); return (RightHandSide != nullptr && InnerMatcher.matches(*RightHandSide, Finder, Builder)); } /// Matches if either the left hand side or the right hand side of a -/// binary operator matches. +/// binary operator or fold expression matches. AST_POLYMORPHIC_MATCHER_P( hasEitherOperand, AST_POLYMORPHIC_SUPPORTED_TYPES(BinaryOperator, CXXOperatorCallExpr, - CXXRewrittenBinaryOperator), + CXXFoldExpr, CXXRewrittenBinaryOperator), internal::Matcher, InnerMatcher) { return internal::VariadicDynCastAllOfMatcher()( anyOf(hasLHS(InnerMatcher), hasRHS(InnerMatcher))) .matches(Node, Finder, Builder); } -/// Matches if both matchers match with opposite sides of the binary operator. +/// Matches if both matchers match with opposite sides of the binary operator +/// or fold expression. /// /// Example matcher = binaryOperator(hasOperands(integerLiteral(equals(1), /// integerLiteral(equals(2))) @@ -5840,7 +5999,7 @@ AST_POLYMORPHIC_MATCHER_P( AST_POLYMORPHIC_MATCHER_P2( hasOperands, AST_POLYMORPHIC_SUPPORTED_TYPES(BinaryOperator, CXXOperatorCallExpr, - CXXRewrittenBinaryOperator), + CXXFoldExpr, CXXRewrittenBinaryOperator), internal::Matcher, Matcher1, internal::Matcher, Matcher2) { return internal::VariadicDynCastAllOfMatcher()( anyOf(allOf(hasLHS(Matcher1), hasRHS(Matcher2)), @@ -6192,9 +6351,7 @@ AST_POLYMORPHIC_MATCHER(isFinal, /// }; /// \endcode /// matches A::x -AST_MATCHER(CXXMethodDecl, isPure) { - return Node.isPure(); -} +AST_MATCHER(CXXMethodDecl, isPure) { return Node.isPureVirtual(); } /// Matches if the given method declaration is const. /// diff --git a/clang/include/clang/ASTMatchers/ASTMatchersInternal.h b/clang/include/clang/ASTMatchers/ASTMatchersInternal.h index 7136d0d2fe0..47d912c73dd 100644 --- a/clang/include/clang/ASTMatchers/ASTMatchersInternal.h +++ b/clang/include/clang/ASTMatchers/ASTMatchersInternal.h @@ -2195,6 +2195,9 @@ inline std::optional getOpName(const CXXOperatorCallExpr &Node) { } return BinaryOperator::getOpcodeStr(*optBinaryOpcode); } +inline StringRef getOpName(const CXXFoldExpr &Node) { + return BinaryOperator::getOpcodeStr(Node.getOperator()); +} /// Matches overloaded operators with a specific name. /// diff --git a/clang/include/clang/Analysis/FlowSensitive/ControlFlowContext.h b/clang/include/clang/Analysis/FlowSensitive/ControlFlowContext.h index 768387a121b..405e93287a0 100644 --- a/clang/include/clang/Analysis/FlowSensitive/ControlFlowContext.h +++ b/clang/include/clang/Analysis/FlowSensitive/ControlFlowContext.h @@ -32,7 +32,8 @@ namespace dataflow { class ControlFlowContext { public: /// Builds a ControlFlowContext from a `FunctionDecl`. - /// `Func.hasBody()` must be true, and `Func.isTemplated()` must be false. + /// `Func.doesThisDeclarationHaveABody()` must be true, and + /// `Func.isTemplated()` must be false. static llvm::Expected build(const FunctionDecl &Func); /// Builds a ControlFlowContext from an AST node. `D` is the function in which diff --git a/clang/include/clang/Analysis/FlowSensitive/DataflowAnalysis.h b/clang/include/clang/Analysis/FlowSensitive/DataflowAnalysis.h index 1dffbe8a09c..b95095d2184 100644 --- a/clang/include/clang/Analysis/FlowSensitive/DataflowAnalysis.h +++ b/clang/include/clang/Analysis/FlowSensitive/DataflowAnalysis.h @@ -186,6 +186,12 @@ template struct DataflowAnalysisState { /// the dataflow analysis cannot be performed successfully. Otherwise, calls /// `PostVisitCFG` on each CFG element with the final analysis results at that /// program point. +/// +/// `MaxBlockVisits` caps the number of block visits during analysis. See +/// `runTypeErasedDataflowAnalysis` for a full description. The default value is +/// essentially arbitrary -- large enough to accommodate what seems like any +/// reasonable CFG, but still small enough to limit the cost of hitting the +/// limit. template llvm::Expected>>> @@ -194,7 +200,8 @@ runDataflowAnalysis( const Environment &InitEnv, std::function &)> - PostVisitCFG = nullptr) { + PostVisitCFG = nullptr, + std::int32_t MaxBlockVisits = 20'000) { std::function PostVisitCFGClosure = nullptr; @@ -212,7 +219,7 @@ runDataflowAnalysis( } auto TypeErasedBlockStates = runTypeErasedDataflowAnalysis( - CFCtx, Analysis, InitEnv, PostVisitCFGClosure); + CFCtx, Analysis, InitEnv, PostVisitCFGClosure, MaxBlockVisits); if (!TypeErasedBlockStates) return TypeErasedBlockStates.takeError(); @@ -261,6 +268,10 @@ auto createAnalysis(ASTContext &ASTCtx, Environment &Env) /// iterations. /// - This limit is still low enough to keep runtimes acceptable (on typical /// machines) in cases where we hit the limit. +/// +/// `MaxBlockVisits` caps the number of block visits during analysis. See +/// `runDataflowAnalysis` for a full description and explanation of the default +/// value. template llvm::Expected> diagnoseFunction( const FunctionDecl &FuncDecl, ASTContext &ASTCtx, @@ -268,7 +279,8 @@ llvm::Expected> diagnoseFunction( const CFGElement &, ASTContext &, const TransferStateForDiagnostics &)> Diagnoser, - std::int64_t MaxSATIterations = 1'000'000'000) { + std::int64_t MaxSATIterations = 1'000'000'000, + std::int32_t MaxBlockVisits = 20'000) { llvm::Expected Context = ControlFlowContext::build(FuncDecl); if (!Context) @@ -293,7 +305,8 @@ llvm::Expected> diagnoseFunction( State.Lattice.Value), State.Env)); llvm::move(EltDiagnostics, std::back_inserter(Diagnostics)); - }) + }, + MaxBlockVisits) .takeError()) return std::move(Err); diff --git a/clang/include/clang/Analysis/FlowSensitive/DataflowEnvironment.h b/clang/include/clang/Analysis/FlowSensitive/DataflowEnvironment.h index e8c27d6c120..1543f900e40 100644 --- a/clang/include/clang/Analysis/FlowSensitive/DataflowEnvironment.h +++ b/clang/include/clang/Analysis/FlowSensitive/DataflowEnvironment.h @@ -172,7 +172,8 @@ public: /// /// Requirements: /// - /// The function must have a body. + /// The function must have a body, i.e. + /// `FunctionDecl::doesThisDecalarationHaveABody()` must be true. void initialize(); /// Returns a new environment that is a copy of this one. diff --git a/clang/include/clang/Analysis/FlowSensitive/Formula.h b/clang/include/clang/Analysis/FlowSensitive/Formula.h index 982e400c1de..0e6352403a8 100644 --- a/clang/include/clang/Analysis/FlowSensitive/Formula.h +++ b/clang/include/clang/Analysis/FlowSensitive/Formula.h @@ -75,6 +75,10 @@ public: return static_cast(Value); } + bool isLiteral(bool b) const { + return kind() == Literal && static_cast(Value) == b; + } + ArrayRef operands() const { return ArrayRef(reinterpret_cast(this + 1), numOperands(kind())); diff --git a/clang/include/clang/Analysis/FlowSensitive/Transfer.h b/clang/include/clang/Analysis/FlowSensitive/Transfer.h index 58bb77c4905..7713df747cb 100644 --- a/clang/include/clang/Analysis/FlowSensitive/Transfer.h +++ b/clang/include/clang/Analysis/FlowSensitive/Transfer.h @@ -25,10 +25,17 @@ namespace dataflow { /// Maps statements to the environments of basic blocks that contain them. class StmtToEnvMap { public: + // `CurBlockID` is the ID of the block currently being processed, and + // `CurState` is the pending state currently associated with this block. These + // are supplied separately as the pending state for the current block may not + // yet be represented in `BlockToState`. StmtToEnvMap(const ControlFlowContext &CFCtx, llvm::ArrayRef> - BlockToState) - : CFCtx(CFCtx), BlockToState(BlockToState) {} + BlockToState, + unsigned CurBlockID, + const TypeErasedDataflowAnalysisState &CurState) + : CFCtx(CFCtx), BlockToState(BlockToState), CurBlockID(CurBlockID), + CurState(CurState) {} /// Returns the environment of the basic block that contains `S`. /// The result is guaranteed never to be null. @@ -37,6 +44,8 @@ public: private: const ControlFlowContext &CFCtx; llvm::ArrayRef> BlockToState; + unsigned CurBlockID; + const TypeErasedDataflowAnalysisState &CurState; }; /// Evaluates `S` and updates `Env` accordingly. diff --git a/clang/include/clang/Analysis/FlowSensitive/TypeErasedDataflowAnalysis.h b/clang/include/clang/Analysis/FlowSensitive/TypeErasedDataflowAnalysis.h index 67c323dbf45..a0ca7440230 100644 --- a/clang/include/clang/Analysis/FlowSensitive/TypeErasedDataflowAnalysis.h +++ b/clang/include/clang/Analysis/FlowSensitive/TypeErasedDataflowAnalysis.h @@ -138,13 +138,20 @@ struct TypeErasedDataflowAnalysisState { /// dataflow analysis cannot be performed successfully. Otherwise, calls /// `PostVisitCFG` on each CFG element with the final analysis results at that /// program point. +/// +/// `MaxBlockVisits` caps the number of block visits during analysis. It doesn't +/// distinguish between repeat visits to the same block and visits to distinct +/// blocks. This parameter is a backstop to prevent infinite loops, in the case +/// of bugs in the lattice and/or transfer functions that prevent the analysis +/// from converging. llvm::Expected>> runTypeErasedDataflowAnalysis( const ControlFlowContext &CFCtx, TypeErasedDataflowAnalysis &Analysis, const Environment &InitEnv, std::function - PostVisitCFG = nullptr); + PostVisitCFG, + std::int32_t MaxBlockVisits); } // namespace dataflow } // namespace clang diff --git a/clang/include/clang/Basic/Attr.td b/clang/include/clang/Basic/Attr.td index a03b0e44e15..58838b01b4f 100644 --- a/clang/include/clang/Basic/Attr.td +++ b/clang/include/clang/Basic/Attr.td @@ -306,6 +306,9 @@ class VariadicEnumArgument values, bit IsExternalType = isExternalType; } +// Represents an attribute wrapped by another attribute. +class WrappedAttr : Argument; + // This handles one spelling of an attribute. class Spelling { string Name = name; @@ -2291,7 +2294,7 @@ def ObjCBridgeRelated : InheritableAttr { def NSErrorDomain : InheritableAttr { let Spellings = [GNU<"ns_error_domain">]; let Subjects = SubjectList<[Enum], ErrorDiag>; - let Args = [DeclArgument]; + let Args = [IdentifierArgument<"ErrorDomain">]; let Documentation = [NSErrorDomainDocs]; } @@ -2539,16 +2542,48 @@ def ArmStreamingCompatible : TypeAttr, TargetSpecificAttr { let Documentation = [ArmSmeStreamingCompatibleDocs]; } -def ArmSharedZA : TypeAttr, TargetSpecificAttr { - let Spellings = [RegularKeyword<"__arm_shared_za">]; - let Subjects = SubjectList<[HasFunctionProto], ErrorDiag>; - let Documentation = [ArmSmeSharedZADocs]; +def ArmNew : InheritableAttr, TargetSpecificAttr { + let Spellings = [RegularKeyword<"__arm_new">]; + let Args = [VariadicStringArgument<"NewArgs">]; + let Subjects = SubjectList<[Function], ErrorDiag>; + let Documentation = [ArmNewDocs]; + + let AdditionalMembers = [{ + bool isNewZA() const { + return llvm::is_contained(newArgs(), "za"); + } + bool isNewZT0() const { + return llvm::is_contained(newArgs(), "zt0"); + } + }]; } -def ArmPreservesZA : TypeAttr, TargetSpecificAttr { - let Spellings = [RegularKeyword<"__arm_preserves_za">]; +def ArmIn : TypeAttr, TargetSpecificAttr { + let Spellings = [RegularKeyword<"__arm_in">]; + let Args = [VariadicStringArgument<"InArgs">]; let Subjects = SubjectList<[HasFunctionProto], ErrorDiag>; - let Documentation = [ArmSmePreservesZADocs]; + let Documentation = [ArmInDocs]; +} + +def ArmOut : TypeAttr, TargetSpecificAttr { + let Spellings = [RegularKeyword<"__arm_out">]; + let Args = [VariadicStringArgument<"OutArgs">]; + let Subjects = SubjectList<[HasFunctionProto], ErrorDiag>; + let Documentation = [ArmOutDocs]; +} + +def ArmInOut : TypeAttr, TargetSpecificAttr { + let Spellings = [RegularKeyword<"__arm_inout">]; + let Args = [VariadicStringArgument<"InOutArgs">]; + let Subjects = SubjectList<[HasFunctionProto], ErrorDiag>; + let Documentation = [ArmInOutDocs]; +} + +def ArmPreserves : TypeAttr, TargetSpecificAttr { + let Spellings = [RegularKeyword<"__arm_preserves">]; + let Args = [VariadicStringArgument<"PreserveArgs">]; + let Subjects = SubjectList<[HasFunctionProto], ErrorDiag>; + let Documentation = [ArmPreservesDocs]; } def ArmLocallyStreaming : InheritableAttr, TargetSpecificAttr { @@ -2557,14 +2592,6 @@ def ArmLocallyStreaming : InheritableAttr, TargetSpecificAttr { let Documentation = [ArmSmeLocallyStreamingDocs]; } -def ArmNewZA : InheritableAttr, TargetSpecificAttr { - let Spellings = [RegularKeyword<"__arm_new_za">]; - let Subjects = SubjectList<[Function], ErrorDiag>; - let Documentation = [ArmSmeNewZADocs]; -} -def : MutualExclusions<[ArmNewZA, ArmSharedZA]>; -def : MutualExclusions<[ArmNewZA, ArmPreservesZA]>; - def Pure : InheritableAttr { let Spellings = [GCC<"pure">]; @@ -2627,6 +2654,22 @@ def SwiftError : InheritableAttr { let Documentation = [SwiftErrorDocs]; } +def SwiftImportAsNonGeneric : InheritableAttr { + // This attribute has no spellings as it is only ever created implicitly + // from API notes. + let Spellings = []; + let SemaHandler = 0; + let Documentation = [InternalOnly]; +} + +def SwiftImportPropertyAsAccessors : InheritableAttr { + // This attribute has no spellings as it is only ever created implicitly + // from API notes. + let Spellings = []; + let SemaHandler = 0; + let Documentation = [InternalOnly]; +} + def SwiftName : InheritableAttr { let Spellings = [GNU<"swift_name">]; let Args = [StringArgument<"Name">]; @@ -2648,6 +2691,31 @@ def SwiftPrivate : InheritableAttr { let SimpleHandler = 1; } +def SwiftVersionedAddition : Attr { + // This attribute has no spellings as it is only ever created implicitly + // from API notes. + let Spellings = []; + let Args = [VersionArgument<"Version">, WrappedAttr<"AdditionalAttr">, + BoolArgument<"IsReplacedByActive">]; + let SemaHandler = 0; + let Documentation = [InternalOnly]; +} + +def SwiftVersionedRemoval : Attr { + // This attribute has no spellings as it is only ever created implicitly + // from API notes. + let Spellings = []; + let Args = [VersionArgument<"Version">, UnsignedArgument<"RawKind">, + BoolArgument<"IsReplacedByActive">]; + let SemaHandler = 0; + let Documentation = [InternalOnly]; + let AdditionalMembers = [{ + attr::Kind getAttrKindToRemove() const { + return static_cast(getRawKind()); + } + }]; +} + def NoDeref : TypeAttr { let Spellings = [Clang<"noderef">]; let Documentation = [NoDerefDocs]; diff --git a/clang/include/clang/Basic/AttrDocs.td b/clang/include/clang/Basic/AttrDocs.td index 2e8d7752c97..7e633f8e263 100644 --- a/clang/include/clang/Basic/AttrDocs.td +++ b/clang/include/clang/Basic/AttrDocs.td @@ -3621,7 +3621,7 @@ Attribute ``trivial_abi`` has no effect in the following cases: def MSInheritanceDocs : Documentation { let Category = DocCatDecl; - let Heading = "__single_inhertiance, __multiple_inheritance, __virtual_inheritance"; + let Heading = "__single_inheritance, __multiple_inheritance, __virtual_inheritance"; let Content = [{ This collection of keywords is enabled under ``-fms-extensions`` and controls the pointer-to-member representation used on ``*-*-win32`` targets. @@ -6861,30 +6861,73 @@ without changing modes. }]; } -def ArmSmeSharedZADocs : Documentation { +def ArmInDocs : Documentation { let Category = DocCatArmSmeAttributes; let Content = [{ -The ``__arm_shared_za`` keyword applies to prototyped function types and specifies -that the function shares SME's matrix storage (ZA) with its caller. This -means that: +The ``__arm_in`` keyword applies to prototyped function types and specifies +that the function shares a given state S with its caller. For ``__arm_in``, the +function takes the state S as input and returns with the state S unchanged. -* the function requires that the processor implements the Scalable Matrix - Extension (SME). +The attribute takes string arguments to instruct the compiler which state +is shared. The supported states for S are: -* the function enters with ZA in an active state. +* ``"za"`` for Matrix Storage (requires SME) -* the function returns with ZA in an active state. +The attributes ``__arm_in(S)``, ``__arm_out(S)``, ``__arm_inout(S)`` and +``__arm_preserves(S)`` are all mutually exclusive for the same state S. }]; } -def ArmSmePreservesZADocs : Documentation { +def ArmOutDocs : Documentation { let Category = DocCatArmSmeAttributes; let Content = [{ -The ``__arm_preserves_za`` keyword applies to prototyped function types and -specifies that the function does not modify ZA state. +The ``__arm_out`` keyword applies to prototyped function types and specifies +that the function shares a given state S with its caller. For ``__arm_out``, +the function ignores the incoming state for S and returns new state for S. + +The attribute takes string arguments to instruct the compiler which state +is shared. The supported states for S are: + +* ``"za"`` for Matrix Storage (requires SME) + +The attributes ``__arm_in(S)``, ``__arm_out(S)``, ``__arm_inout(S)`` and +``__arm_preserves(S)`` are all mutually exclusive for the same state S. }]; } +def ArmInOutDocs : Documentation { + let Category = DocCatArmSmeAttributes; + let Content = [{ +The ``__arm_inout`` keyword applies to prototyped function types and specifies +that the function shares a given state S with its caller. For ``__arm_inout``, +the function takes the state S as input and returns new state for S. + +The attribute takes string arguments to instruct the compiler which state +is shared. The supported states for S are: + +* ``"za"`` for Matrix Storage (requires SME) + +The attributes ``__arm_in(S)``, ``__arm_out(S)``, ``__arm_inout(S)`` and +``__arm_preserves(S)`` are all mutually exclusive for the same state S. + }]; +} + +def ArmPreservesDocs : Documentation { + let Category = DocCatArmSmeAttributes; + let Content = [{ +The ``__arm_preserves`` keyword applies to prototyped function types and +specifies that the function does not read a given state S and returns +with state S unchanged. + +The attribute takes string arguments to instruct the compiler which state +is shared. The supported states for S are: + +* ``"za"`` for Matrix Storage (requires SME) + +The attributes ``__arm_in(S)``, ``__arm_out(S)``, ``__arm_inout(S)`` and +``__arm_preserves(S)`` are all mutually exclusive for the same state S. + }]; +} def ArmSmeLocallyStreamingDocs : Documentation { let Category = DocCatArmSmeAttributes; @@ -6907,13 +6950,18 @@ at the end of the function. }]; } -def ArmSmeNewZADocs : Documentation { +def ArmNewDocs : Documentation { let Category = DocCatArmSmeAttributes; let Content = [{ -The ``__arm_new_za`` keyword applies to function declarations and specifies -that the function will be set up with a fresh ZA context. +The ``__arm_new`` keyword applies to function declarations and specifies +that the function will create a new scope for state S. -This means that: +The attribute takes string arguments to instruct the compiler for which state +to create new scope. The supported states for S are: + +* ``"za"`` for Matrix Storage (requires SME) + +For state ``"za"``, this means that: * the function requires that the target processor implements the Scalable Matrix Extension (SME). @@ -6924,8 +6972,8 @@ This means that: * the function will disable PSTATE.ZA (by setting it to 0) before returning. -For ``__arm_new_za`` functions Clang will set up the ZA context automatically -on entry to the function, and disable it before returning. For example, if ZA is +For ``__arm_new("za")`` functions Clang will set up the ZA context automatically +on entry to the function and disable it before returning. For example, if ZA is in a dormant state Clang will generate the code to commit a lazy-save and set up a new ZA state before executing user code. }]; diff --git a/clang/include/clang/Basic/AttributeCommonInfo.h b/clang/include/clang/Basic/AttributeCommonInfo.h index 018b92fdc11..ef2ddf525c9 100644 --- a/clang/include/clang/Basic/AttributeCommonInfo.h +++ b/clang/include/clang/Basic/AttributeCommonInfo.h @@ -255,6 +255,19 @@ protected: return SpellingIndex != SpellingNotCalculated; } }; + +inline bool doesKeywordAttributeTakeArgs(tok::TokenKind Kind) { + switch (Kind) { + default: + return false; +#define KEYWORD_ATTRIBUTE(NAME, HASARG, ...) \ + case tok::kw_##NAME: \ + return HASARG; +#include "clang/Basic/RegularKeywordAttrInfo.inc" +#undef KEYWORD_ATTRIBUTE + } +} + } // namespace clang #endif // LLVM_CLANG_BASIC_ATTRIBUTECOMMONINFO_H diff --git a/clang/include/clang/Basic/BuiltinsAMDGPU.def b/clang/include/clang/Basic/BuiltinsAMDGPU.def index e562ef04a30..d208342d9c5 100644 --- a/clang/include/clang/Basic/BuiltinsAMDGPU.def +++ b/clang/include/clang/Basic/BuiltinsAMDGPU.def @@ -255,6 +255,10 @@ TARGET_BUILTIN(__builtin_amdgcn_sudot4, "iIbiIbiiIb", "nc", "dot8-insts") TARGET_BUILTIN(__builtin_amdgcn_sdot8, "SiSiSiSiIb", "nc", "dot1-insts") TARGET_BUILTIN(__builtin_amdgcn_udot8, "UiUiUiUiIb", "nc", "dot7-insts") TARGET_BUILTIN(__builtin_amdgcn_sudot8, "iIbiIbiiIb", "nc", "dot8-insts") +TARGET_BUILTIN(__builtin_amdgcn_dot4_f32_fp8_bf8, "fUiUif", "nc", "gfx12-insts") +TARGET_BUILTIN(__builtin_amdgcn_dot4_f32_bf8_fp8, "fUiUif", "nc", "gfx12-insts") +TARGET_BUILTIN(__builtin_amdgcn_dot4_f32_fp8_fp8, "fUiUif", "nc", "gfx12-insts") +TARGET_BUILTIN(__builtin_amdgcn_dot4_f32_bf8_bf8, "fUiUif", "nc", "gfx12-insts") //===----------------------------------------------------------------------===// // GFX10+ only builtins. @@ -397,19 +401,20 @@ TARGET_BUILTIN(__builtin_amdgcn_smfmac_f32_32x32x32_bf8_fp8, "V16fV2iV4iV16fiIiI TARGET_BUILTIN(__builtin_amdgcn_smfmac_f32_32x32x32_fp8_bf8, "V16fV2iV4iV16fiIiIi", "nc", "fp8-insts") TARGET_BUILTIN(__builtin_amdgcn_smfmac_f32_32x32x32_fp8_fp8, "V16fV2iV4iV16fiIiIi", "nc", "fp8-insts") -TARGET_BUILTIN(__builtin_amdgcn_cvt_f32_bf8, "fiIi", "nc", "fp8-insts") -TARGET_BUILTIN(__builtin_amdgcn_cvt_f32_fp8, "fiIi", "nc", "fp8-insts") -TARGET_BUILTIN(__builtin_amdgcn_cvt_pk_f32_bf8, "V2fiIb", "nc", "fp8-insts") -TARGET_BUILTIN(__builtin_amdgcn_cvt_pk_f32_fp8, "V2fiIb", "nc", "fp8-insts") -TARGET_BUILTIN(__builtin_amdgcn_cvt_pk_bf8_f32, "iffiIb", "nc", "fp8-insts") -TARGET_BUILTIN(__builtin_amdgcn_cvt_pk_fp8_f32, "iffiIb", "nc", "fp8-insts") -TARGET_BUILTIN(__builtin_amdgcn_cvt_sr_bf8_f32, "ifiiIi", "nc", "fp8-insts") -TARGET_BUILTIN(__builtin_amdgcn_cvt_sr_fp8_f32, "ifiiIi", "nc", "fp8-insts") +TARGET_BUILTIN(__builtin_amdgcn_cvt_f32_bf8, "fiIi", "nc", "fp8-conversion-insts") +TARGET_BUILTIN(__builtin_amdgcn_cvt_f32_fp8, "fiIi", "nc", "fp8-conversion-insts") +TARGET_BUILTIN(__builtin_amdgcn_cvt_pk_f32_bf8, "V2fiIb", "nc", "fp8-conversion-insts") +TARGET_BUILTIN(__builtin_amdgcn_cvt_pk_f32_fp8, "V2fiIb", "nc", "fp8-conversion-insts") +TARGET_BUILTIN(__builtin_amdgcn_cvt_pk_bf8_f32, "iffiIb", "nc", "fp8-conversion-insts") +TARGET_BUILTIN(__builtin_amdgcn_cvt_pk_fp8_f32, "iffiIb", "nc", "fp8-conversion-insts") +TARGET_BUILTIN(__builtin_amdgcn_cvt_sr_bf8_f32, "ifiiIi", "nc", "fp8-conversion-insts") +TARGET_BUILTIN(__builtin_amdgcn_cvt_sr_fp8_f32, "ifiiIi", "nc", "fp8-conversion-insts") //===----------------------------------------------------------------------===// // GFX12+ only builtins. //===----------------------------------------------------------------------===// +TARGET_BUILTIN(__builtin_amdgcn_s_sleep_var, "vUi", "n", "gfx12-insts") TARGET_BUILTIN(__builtin_amdgcn_permlane16_var, "UiUiUiUiIbIb", "nc", "gfx12-insts") TARGET_BUILTIN(__builtin_amdgcn_permlanex16_var, "UiUiUiUiIbIb", "nc", "gfx12-insts") TARGET_BUILTIN(__builtin_amdgcn_s_barrier_signal, "vIi", "n", "gfx12-insts") @@ -423,6 +428,13 @@ TARGET_BUILTIN(__builtin_amdgcn_s_wakeup_barrier, "vi", "n", "gfx12-insts") TARGET_BUILTIN(__builtin_amdgcn_s_barrier_leave, "b", "n", "gfx12-insts") TARGET_BUILTIN(__builtin_amdgcn_s_get_barrier_state, "Uii", "n", "gfx12-insts") +TARGET_BUILTIN(__builtin_amdgcn_global_load_tr_v2i32, "V2iV2i*1", "nc", "gfx12-insts,wavefrontsize32") +TARGET_BUILTIN(__builtin_amdgcn_global_load_tr_v8i16, "V8sV8s*1", "nc", "gfx12-insts,wavefrontsize32") +TARGET_BUILTIN(__builtin_amdgcn_global_load_tr_v8f16, "V8hV8h*1", "nc", "gfx12-insts,wavefrontsize32") + +TARGET_BUILTIN(__builtin_amdgcn_global_load_tr_i32, "ii*1", "nc", "gfx12-insts,wavefrontsize64") +TARGET_BUILTIN(__builtin_amdgcn_global_load_tr_v4i16, "V4sV4s*1", "nc", "gfx12-insts,wavefrontsize64") +TARGET_BUILTIN(__builtin_amdgcn_global_load_tr_v4f16, "V4hV4h*1", "nc", "gfx12-insts,wavefrontsize64") #undef BUILTIN #undef TARGET_BUILTIN diff --git a/clang/include/clang/Basic/BuiltinsLoongArchBase.def b/clang/include/clang/Basic/BuiltinsLoongArchBase.def index cbb239223aa..a5a07c16790 100644 --- a/clang/include/clang/Basic/BuiltinsLoongArchBase.def +++ b/clang/include/clang/Basic/BuiltinsLoongArchBase.def @@ -51,3 +51,8 @@ TARGET_BUILTIN(__builtin_loongarch_iocsrwr_d, "vUWiUi", "nc", "64bit") TARGET_BUILTIN(__builtin_loongarch_lddir_d, "WiWiIUWi", "nc", "64bit") TARGET_BUILTIN(__builtin_loongarch_ldpte_d, "vWiIUWi", "nc", "64bit") + +TARGET_BUILTIN(__builtin_loongarch_frecipe_s, "ff", "nc", "f,frecipe") +TARGET_BUILTIN(__builtin_loongarch_frecipe_d, "dd", "nc", "d,frecipe") +TARGET_BUILTIN(__builtin_loongarch_frsqrte_s, "ff", "nc", "f,frecipe") +TARGET_BUILTIN(__builtin_loongarch_frsqrte_d, "dd", "nc", "d,frecipe") diff --git a/clang/include/clang/Basic/BuiltinsLoongArchLASX.def b/clang/include/clang/Basic/BuiltinsLoongArchLASX.def index 3de200f665b..4cf51cc000f 100644 --- a/clang/include/clang/Basic/BuiltinsLoongArchLASX.def +++ b/clang/include/clang/Basic/BuiltinsLoongArchLASX.def @@ -657,9 +657,15 @@ TARGET_BUILTIN(__builtin_lasx_xvfsqrt_d, "V4dV4d", "nc", "lasx") TARGET_BUILTIN(__builtin_lasx_xvfrecip_s, "V8fV8f", "nc", "lasx") TARGET_BUILTIN(__builtin_lasx_xvfrecip_d, "V4dV4d", "nc", "lasx") +TARGET_BUILTIN(__builtin_lasx_xvfrecipe_s, "V8fV8f", "nc", "lasx,frecipe") +TARGET_BUILTIN(__builtin_lasx_xvfrecipe_d, "V4dV4d", "nc", "lasx,frecipe") + TARGET_BUILTIN(__builtin_lasx_xvfrsqrt_s, "V8fV8f", "nc", "lasx") TARGET_BUILTIN(__builtin_lasx_xvfrsqrt_d, "V4dV4d", "nc", "lasx") +TARGET_BUILTIN(__builtin_lasx_xvfrsqrte_s, "V8fV8f", "nc", "lasx,frecipe") +TARGET_BUILTIN(__builtin_lasx_xvfrsqrte_d, "V4dV4d", "nc", "lasx,frecipe") + TARGET_BUILTIN(__builtin_lasx_xvfcvtl_s_h, "V8fV16s", "nc", "lasx") TARGET_BUILTIN(__builtin_lasx_xvfcvth_s_h, "V8fV16s", "nc", "lasx") TARGET_BUILTIN(__builtin_lasx_xvfcvtl_d_s, "V4dV8f", "nc", "lasx") diff --git a/clang/include/clang/Basic/BuiltinsLoongArchLSX.def b/clang/include/clang/Basic/BuiltinsLoongArchLSX.def index 8e6aec886c5..c90f4dc5458 100644 --- a/clang/include/clang/Basic/BuiltinsLoongArchLSX.def +++ b/clang/include/clang/Basic/BuiltinsLoongArchLSX.def @@ -641,9 +641,15 @@ TARGET_BUILTIN(__builtin_lsx_vfsqrt_d, "V2dV2d", "nc", "lsx") TARGET_BUILTIN(__builtin_lsx_vfrecip_s, "V4fV4f", "nc", "lsx") TARGET_BUILTIN(__builtin_lsx_vfrecip_d, "V2dV2d", "nc", "lsx") +TARGET_BUILTIN(__builtin_lsx_vfrecipe_s, "V4fV4f", "nc", "lsx,frecipe") +TARGET_BUILTIN(__builtin_lsx_vfrecipe_d, "V2dV2d", "nc", "lsx,frecipe") + TARGET_BUILTIN(__builtin_lsx_vfrsqrt_s, "V4fV4f", "nc", "lsx") TARGET_BUILTIN(__builtin_lsx_vfrsqrt_d, "V2dV2d", "nc", "lsx") +TARGET_BUILTIN(__builtin_lsx_vfrsqrte_s, "V4fV4f", "nc", "lsx,frecipe") +TARGET_BUILTIN(__builtin_lsx_vfrsqrte_d, "V2dV2d", "nc", "lsx,frecipe") + TARGET_BUILTIN(__builtin_lsx_vfcvtl_s_h, "V4fV8s", "nc", "lsx") TARGET_BUILTIN(__builtin_lsx_vfcvtl_d_s, "V2dV4f", "nc", "lsx") diff --git a/clang/include/clang/Basic/BuiltinsPPC.def b/clang/include/clang/Basic/BuiltinsPPC.def index a35488ed3df..88ae0ce9408 100644 --- a/clang/include/clang/Basic/BuiltinsPPC.def +++ b/clang/include/clang/Basic/BuiltinsPPC.def @@ -110,6 +110,10 @@ BUILTIN(__builtin_ppc_fctiw, "dd", "") BUILTIN(__builtin_ppc_fctiwz, "dd", "") BUILTIN(__builtin_ppc_fctudz, "dd", "") BUILTIN(__builtin_ppc_fctuwz, "dd", "") + +// fence builtin prevents all instructions moved across it +BUILTIN(__builtin_ppc_fence, "v", "") + BUILTIN(__builtin_ppc_swdiv_nochk, "ddd", "") BUILTIN(__builtin_ppc_swdivs_nochk, "fff", "") BUILTIN(__builtin_ppc_alignx, "vIivC*", "nc") diff --git a/clang/include/clang/Basic/CodeGenOptions.def b/clang/include/clang/Basic/CodeGenOptions.def index 2c4fb6745bc..2f2e45d5cf6 100644 --- a/clang/include/clang/Basic/CodeGenOptions.def +++ b/clang/include/clang/Basic/CodeGenOptions.def @@ -12,6 +12,9 @@ // that have enumeration type and VALUE_CODEGENOPT is a code // generation option that describes a value rather than a flag. // +// AFFECTING_VALUE_CODEGENOPT is used for code generation options that can +// affect the AST. +// //===----------------------------------------------------------------------===// #ifndef CODEGENOPT # error Define the CODEGENOPT macro to handle language options @@ -27,6 +30,11 @@ CODEGENOPT(Name, Bits, Default) CODEGENOPT(Name, Bits, Default) #endif +#ifndef AFFECTING_VALUE_CODEGENOPT +# define AFFECTING_VALUE_CODEGENOPT(Name, Bits, Default) \ +VALUE_CODEGENOPT(Name, Bits, Default) +#endif + CODEGENOPT(DisableIntegratedAS, 1, 0) ///< -no-integrated-as CODEGENOPT(RelaxELFRelocations, 1, 1) ///< -Wa,-mrelax-relocations={yes,no} CODEGENOPT(AsmVerbose , 1, 0) ///< -dA, -fverbose-asm. @@ -193,8 +201,10 @@ ENUM_CODEGENOPT(ObjCDispatchMethod, ObjCDispatchMethodKind, 2, Legacy) CODEGENOPT(ObjCConvertMessagesToRuntimeCalls , 1, 1) CODEGENOPT(ObjCAvoidHeapifyLocalBlocks, 1, 0) -VALUE_CODEGENOPT(OptimizationLevel, 2, 0) ///< The -O[0-3] option specified. -VALUE_CODEGENOPT(OptimizeSize, 2, 0) ///< If -Os (==1) or -Oz (==2) is specified. + +// The optimization options affect frontend options, whicn in turn do affect the AST. +AFFECTING_VALUE_CODEGENOPT(OptimizationLevel, 2, 0) ///< The -O[0-3] option specified. +AFFECTING_VALUE_CODEGENOPT(OptimizeSize, 2, 0) ///< If -Os (==1) or -Oz (==2) is specified. CODEGENOPT(AtomicProfileUpdate , 1, 0) ///< Set -fprofile-update=atomic /// Choose profile instrumenation kind or no instrumentation. @@ -437,3 +447,4 @@ CODEGENOPT(CtorDtorReturnThis, 1, 0) #undef CODEGENOPT #undef ENUM_CODEGENOPT #undef VALUE_CODEGENOPT +#undef AFFECTING_VALUE_CODEGENOPT diff --git a/clang/include/clang/Basic/CodeGenOptions.h b/clang/include/clang/Basic/CodeGenOptions.h index 6952b48e898..3f8fe385fef 100644 --- a/clang/include/clang/Basic/CodeGenOptions.h +++ b/clang/include/clang/Basic/CodeGenOptions.h @@ -494,6 +494,9 @@ public: return getProfileInstr() == ProfileCSIRInstr; } + /// Check if any form of instrumentation is on. + bool hasProfileInstr() const { return getProfileInstr() != ProfileNone; } + /// Check if Clang profile use is on. bool hasProfileClangUse() const { return getProfileUse() == ProfileClangInstr; diff --git a/clang/include/clang/Basic/DiagnosticCommonKinds.td b/clang/include/clang/Basic/DiagnosticCommonKinds.td index 72952b08c04..b1bada65cb6 100644 --- a/clang/include/clang/Basic/DiagnosticCommonKinds.td +++ b/clang/include/clang/Basic/DiagnosticCommonKinds.td @@ -70,6 +70,10 @@ def warn_pragma_debug_missing_argument : Warning< def warn_pragma_debug_unexpected_argument : Warning< "unexpected argument to debug command">, InGroup; +def warn_fp_nan_inf_when_disabled : Warning< + "use of %select{infinity|NaN}0%select{| via a macro}1 is undefined behavior " + "due to the currently enabled floating-point options">, + InGroup>; } // Parse && Sema @@ -358,9 +362,9 @@ def err_cannot_open_file : Error<"cannot open file '%0': %1">, DefaultFatal; def err_file_modified : Error< "file '%0' modified since it was first processed">, DefaultFatal; def err_file_too_large : Error< - "sorry, unsupported: file '%0' is too large for Clang to process">; + "file '%0' is too large for Clang to process">; def err_sloc_space_too_large : Error< - "sorry, the translation unit is too large for Clang to process: ran out of source locations">, DefaultFatal; + "translation unit is too large for Clang to process: ran out of source locations">, DefaultFatal; def err_unsupported_bom : Error<"%0 byte order mark detected in '%1', but " "encoding is not supported">, DefaultFatal; def err_unable_to_rename_temp : Error< diff --git a/clang/include/clang/Basic/DiagnosticDriverKinds.td b/clang/include/clang/Basic/DiagnosticDriverKinds.td index 0a8a77fadbe..094fe195094 100644 --- a/clang/include/clang/Basic/DiagnosticDriverKinds.td +++ b/clang/include/clang/Basic/DiagnosticDriverKinds.td @@ -427,6 +427,8 @@ def warn_drv_clang_unsupported : Warning< "the clang compiler does not support '%0'">; def warn_drv_deprecated_arg : Warning< "argument '%0' is deprecated, use '%1' instead">, InGroup; +def warn_drv_deprecated_custom : Warning< + "argument '%0' is deprecated, %1">, InGroup; def warn_drv_assuming_mfloat_abi_is : Warning< "unknown platform, assuming -mfloat-abi=%0">; def warn_drv_unsupported_float_abi_by_lib : Warning< @@ -472,7 +474,7 @@ def warn_unsupported_branch_protection: Warning < def err_sls_hardening_arm_not_supported : Error< "-mharden-sls is only supported on armv7-a or later">; def warn_drv_large_data_threshold_invalid_code_model: Warning< - "'%0' only applies to medium code model">, + "'%0' only applies to medium and large code models">, InGroup; def note_drv_command_failed_diag_msg : Note< @@ -656,6 +658,13 @@ def err_drv_trivial_auto_var_init_stop_after_missing_dependency : Error< def err_drv_trivial_auto_var_init_stop_after_invalid_value : Error< "'-ftrivial-auto-var-init-stop-after=*' only accepts positive integers">; +def err_drv_trivial_auto_var_init_max_size_missing_dependency : Error< + "'-ftrivial-auto-var-init-max-size=*' is used without " + "'-ftrivial-auto-var-init=zero' or '-ftrivial-auto-var-init=pattern'">; + +def err_drv_trivial_auto_var_init_max_size_invalid_value : Error< + "'-ftrivial-auto-var-init-max-size=*' only accepts positive integers (in bytes)">; + def warn_drv_msp430_hwmult_unsupported : Warning< "the given MCU does not support hardware multiply, but '-mhwmult' is set to " "%0">, InGroup; @@ -735,10 +744,10 @@ def err_drv_dxc_missing_target_profile : Error< def err_drv_hlsl_unsupported_target : Error< "HLSL code generation is unsupported for target '%0'">; def err_drv_hlsl_bad_shader_required_in_target : Error< - "shader %select{model|stage}0 is required in target '%1' for HLSL code generation">; + "%select{shader model|Vulkan environment|shader stage}0 is required as %select{OS|environment}1 in target '%2' for HLSL code generation">; def err_drv_hlsl_bad_shader_unsupported : Error< - "shader %select{model|stage}0 '%1' in target '%2' is invalid for HLSL code generation">; + "%select{shader model|Vulkan environment|shader stage}0 '%1' in target '%2' is invalid for HLSL code generation">; def warn_drv_dxc_missing_dxv : Warning<"dxv not found. " "Resulting DXIL will not be validated or signed for use in release environments.">, InGroup; diff --git a/clang/include/clang/Basic/DiagnosticParseKinds.td b/clang/include/clang/Basic/DiagnosticParseKinds.td index 088f8b74983..a30ab27566e 100644 --- a/clang/include/clang/Basic/DiagnosticParseKinds.td +++ b/clang/include/clang/Basic/DiagnosticParseKinds.td @@ -1366,6 +1366,15 @@ def err_acc_invalid_open_paren : Error<"expected clause-list or newline in OpenACC directive">; def err_acc_invalid_default_clause_kind : Error<"invalid value for 'default' clause; expected 'present' or 'none'">; +def err_acc_invalid_tag_kind + : Error<"invalid tag %0 on '%1' %select{directive|clause}2">; +def err_acc_expected_reduction_operator + : Error<"missing reduction operator, expected '+', '*', 'max', 'min', '&', " + "'|', '^', '&&', or '||', follwed by a ':'">; +def err_acc_invalid_reduction_operator + : Error<"invalid reduction operator, expected '+', '*', 'max', 'min', " + "'&', '|', '^', '&&', or '||'">; +def err_acc_incorrect_bind_arg : Error<"expected identifier or string literal">; // OpenMP support. def warn_pragma_omp_ignored : Warning< @@ -1609,6 +1618,9 @@ def err_pragma_invalid_keyword : Error< def err_pragma_pipeline_invalid_keyword : Error< "invalid argument; expected 'disable'">; +// API notes. +def err_type_unparsed : Error<"unparsed tokens following type">; + // Pragma unroll support. def warn_pragma_unroll_cuda_value_in_parens : Warning< "argument to '#pragma unroll' should not be in parentheses in CUDA C/C++">, diff --git a/clang/include/clang/Basic/DiagnosticSemaKinds.td b/clang/include/clang/Basic/DiagnosticSemaKinds.td index 1a79892e400..a1c32abb4dc 100644 --- a/clang/include/clang/Basic/DiagnosticSemaKinds.td +++ b/clang/include/clang/Basic/DiagnosticSemaKinds.td @@ -692,6 +692,13 @@ def warn_maybe_falloff_nonvoid_function : Warning< def warn_falloff_nonvoid_function : Warning< "non-void function does not return a value">, InGroup; +def warn_const_attr_with_pure_attr : Warning< + "'const' attribute imposes more restrictions; 'pure' attribute ignored">, + InGroup; +def warn_pure_function_returns_void : Warning< + "'%select{pure|const}0' attribute on function returning 'void'; attribute ignored">, + InGroup; + def err_maybe_falloff_nonvoid_block : Error< "non-void block does not return a value in all control paths">; def err_falloff_nonvoid_block : Error< @@ -2411,7 +2418,8 @@ def err_auto_not_allowed : Error< "|in type allocated by 'new'|in K&R-style function parameter" "|in template parameter|in friend declaration|in function prototype that is " "not a function declaration|in requires expression parameter" - "|in array declaration}1">; + "|in array declaration" + "|in declaration of conversion function template}1">; def err_dependent_deduced_tst : Error< "typename specifier refers to " "%select{class template|function template|variable template|alias template|" @@ -3113,6 +3121,8 @@ def err_musttail_scope : Error< "cannot perform a tail call from this return statement">; def err_musttail_no_variadic : Error< "%0 attribute may not be used with variadic functions">; +def err_musttail_no_return : Error< + "%0 attribute may not be used with no-return-attribute functions">; def err_nsobject_attribute : Error< "'NSObject' attribute is for pointer types only">; @@ -3160,6 +3170,9 @@ def warn_attribute_arm_sm_incompat_builtin : Warning< def warn_attribute_arm_za_builtin_no_za_state : Warning< "builtin call is not valid when calling from a function without active ZA state">, InGroup>; +def warn_attribute_arm_zt0_builtin_no_zt0_state : Warning< + "builtin call is not valid when calling from a function without active ZT0 state">, + InGroup>; def err_sve_vector_in_non_sve_target : Error< "SVE vector type %0 cannot be used in a target without sve">; def err_attribute_riscv_rvv_bits_unsupported : Error< @@ -3696,10 +3709,20 @@ def err_sme_call_in_non_sme_target : Error< "call to a streaming function requires 'sme'">; def err_sme_za_call_no_za_state : Error< "call to a shared ZA function requires the caller to have ZA state">; +def err_sme_zt0_call_no_zt0_state : Error< + "call to a shared ZT0 function requires the caller to have ZT0 state">; def err_sme_definition_using_sm_in_non_sme_target : Error< "function executed in streaming-SVE mode requires 'sme'">; def err_sme_definition_using_za_in_non_sme_target : Error< "function using ZA state requires 'sme'">; +def err_sme_definition_using_zt0_in_non_sme2_target : Error< + "function using ZT0 state requires 'sme2'">; +def err_conflicting_attributes_arm_state : Error< + "conflicting attributes for state '%0'">; +def err_unknown_arm_state : Error< + "unknown state '%0'">; +def err_missing_arm_state : Error< + "missing state for %0">; def err_cconv_change : Error< "function declared '%0' here was previously declared " "%select{'%2'|without calling convention}1">; @@ -5138,8 +5161,6 @@ def err_non_type_template_arg_subobject : Error< "non-type template argument refers to subobject '%0'">; def err_non_type_template_arg_addr_label_diff : Error< "template argument / label address difference / what did you expect?">; -def err_non_type_template_arg_unsupported : Error< - "sorry, non-type template argument of type %0 is not yet supported">; def err_template_arg_not_convertible : Error< "non-type template argument of type %0 cannot be converted to a value " "of type %1">; @@ -5191,9 +5212,6 @@ def err_template_arg_not_object_or_func : Error< "non-type template argument does not refer to an object or function">; def err_template_arg_not_pointer_to_member_form : Error< "non-type template argument is not a pointer to member constant">; -def err_template_arg_member_ptr_base_derived_not_supported : Error< - "sorry, non-type template argument of pointer-to-member type %1 that refers " - "to member %q0 of a different class is not supported yet">; def err_template_arg_invalid : Error< "non-type template argument '%0' is invalid">; def ext_template_arg_extra_parens : ExtWarn< @@ -7000,6 +7018,11 @@ def err_member_decl_does_not_match : Error< "does not match any declaration in %1">; def err_friend_decl_with_def_arg_must_be_def : Error< "friend declaration specifying a default argument must be a definition">; +def err_friend_decl_with_enclosing_temp_constraint_must_be_def : Error< + "friend declaration with a constraint that depends on an enclosing " + "template parameter must be a definition">; +def err_non_temp_friend_decl_with_requires_clause_must_be_def : Error< + "non-template friend declaration with a requires clause must be a definition">; def err_friend_decl_with_def_arg_redeclared : Error< "friend declaration specifying a default argument must be the only declaration">; def err_friend_decl_does_not_match : Error< @@ -9926,10 +9949,10 @@ def warn_new_dangling_initializer_list : Warning< "will be destroyed at the end of the full-expression">, InGroup; def warn_unsupported_lifetime_extension : Warning< - "sorry, lifetime extension of " + "lifetime extension of " "%select{temporary|backing array of initializer list}0 created " - "by aggregate initialization using default member initializer " - "is not supported; lifetime of %select{temporary|backing array}0 " + "by aggregate initialization using a default member initializer " + "is not yet supported; lifetime of %select{temporary|backing array}0 " "will end at the end of the full-expression">, InGroup; // For non-floating point, expressions of the form x == x or x != x diff --git a/clang/include/clang/Basic/DiagnosticSerializationKinds.td b/clang/include/clang/Basic/DiagnosticSerializationKinds.td index 3cb2cd32cf6..11c706ebf84 100644 --- a/clang/include/clang/Basic/DiagnosticSerializationKinds.td +++ b/clang/include/clang/Basic/DiagnosticSerializationKinds.td @@ -129,10 +129,8 @@ def warn_module_system_bit_conflict : Warning< "as a non-system module; any difference in diagnostic options will be ignored">, InGroup; -def warn_reading_std_cxx_module_by_implicit_paths : Warning< - "it is deprecated to read module '%0' implicitly; it is going to be removed in clang 18; " - "consider to specify the dependencies explicitly">, - InGroup>; +def err_failed_to_find_module_file : Error< + "failed to find module file for module '%0'">; } // let CategoryName let CategoryName = "AST Serialization Issue" in { diff --git a/clang/include/clang/Basic/Features.def b/clang/include/clang/Basic/Features.def index 06efac0cf1a..5fad5fc3623 100644 --- a/clang/include/clang/Basic/Features.def +++ b/clang/include/clang/Basic/Features.def @@ -269,6 +269,10 @@ EXTENSION(cxx_fixed_enum, true) EXTENSION(cxx_binary_literals, true) EXTENSION(cxx_init_captures, LangOpts.CPlusPlus11) EXTENSION(cxx_variable_templates, LangOpts.CPlusPlus) +//C++20 +EXTENSION(cxx_generalized_nttp, LangOpts.CPlusPlus20) +//C++23 +EXTENSION(cxx_explicit_this_parameter, LangOpts.CPlusPlus23) // Miscellaneous language extensions EXTENSION(overloadable_unmarked, true) EXTENSION(pragma_clang_attribute_namespaces, true) diff --git a/clang/include/clang/Basic/LangOptions.def b/clang/include/clang/Basic/LangOptions.def index 0428b70c602..8fc75e1cca0 100644 --- a/clang/include/clang/Basic/LangOptions.def +++ b/clang/include/clang/Basic/LangOptions.def @@ -220,7 +220,7 @@ BENIGN_LANGOPT(NoSignedZero , 1, 0, "Permit Floating Point optimization wit BENIGN_LANGOPT(AllowRecip , 1, 0, "Permit Floating Point reciprocal") BENIGN_LANGOPT(ApproxFunc , 1, 0, "Permit Floating Point approximation") -ENUM_LANGOPT(ComplexRange, ComplexRangeKind, 2, CX_Full, "Enable use of range reduction for complex arithmetics.") +ENUM_LANGOPT(ComplexRange, ComplexRangeKind, 2, CX_None, "Enable use of range reduction for complex arithmetics.") BENIGN_LANGOPT(ObjCGCBitmapPrint , 1, 0, "printing of GC's bitmap layout for __weak/__strong ivars") @@ -260,6 +260,7 @@ LANGOPT(OpenMPTeamSubscription , 1, 0, "Assume distributed loops do not have mo LANGOPT(OpenMPNoThreadState , 1, 0, "Assume that no thread in a parallel region will modify an ICV.") LANGOPT(OpenMPNoNestedParallelism , 1, 0, "Assume that no thread in a parallel region will encounter a parallel region") LANGOPT(OpenMPOffloadMandatory , 1, 0, "Assert that offloading is mandatory and do not create a host fallback.") +LANGOPT(OpenMPForceUSM , 1, 0, "Enable OpenMP unified shared memory mode via compiler.") LANGOPT(NoGPULib , 1, 0, "Indicate a build without the standard GPU libraries.") LANGOPT(RenderScript , 1, 0, "RenderScript") @@ -308,7 +309,8 @@ BENIGN_LANGOPT(IgnoreXCOFFVisibility, 1, 0, "All the visibility attributes that BENIGN_LANGOPT(VisibilityInlinesHiddenStaticLocalVar, 1, 0, "hidden visibility for static local variables in inline C++ " "methods when -fvisibility-inlines hidden is enabled") -LANGOPT(GlobalAllocationFunctionVisibilityHidden , 1, 0, "hidden visibility for global operator new and delete declaration") +ENUM_LANGOPT(GlobalAllocationFunctionVisibility, VisibilityForcedKinds, 3, VisibilityForcedKinds::ForceDefault, + "How to apply visibility to global operator new and delete declarations") LANGOPT(NewInfallible , 1, 0, "Treats throwing global C++ operator new as always returning valid memory (annotates with __attribute__((returns_nonnull)) and throw()). This is detectable in source.") BENIGN_LANGOPT(ParseUnknownAnytype, 1, 0, "__unknown_anytype") BENIGN_LANGOPT(DebuggerSupport , 1, 0, "debugger support") @@ -359,16 +361,16 @@ BENIGN_ENUM_LANGOPT(TypeVisibilityMode, Visibility, 3, DefaultVisibility, "default visibility for types [-ftype-visibility]") LANGOPT(SetVisibilityForExternDecls, 1, 0, "apply global symbol visibility to external declarations without an explicit visibility") -LANGOPT(VisibilityFromDLLStorageClass, 1, 0, - "set the visiblity of globals from their DLL storage class [-fvisibility-from-dllstorageclass]") -ENUM_LANGOPT(DLLExportVisibility, Visibility, 3, DefaultVisibility, - "visibility for functions and variables with dllexport annotations [-fvisibility-from-dllstorageclass]") -ENUM_LANGOPT(NoDLLStorageClassVisibility, Visibility, 3, HiddenVisibility, - "visibility for functions and variables without an explicit DLL storage class [-fvisibility-from-dllstorageclass]") -ENUM_LANGOPT(ExternDeclDLLImportVisibility, Visibility, 3, DefaultVisibility, - "visibility for external declarations with dllimport annotations [-fvisibility-from-dllstorageclass]") -ENUM_LANGOPT(ExternDeclNoDLLStorageClassVisibility, Visibility, 3, HiddenVisibility, - "visibility for external declarations without an explicit DLL storage class [-fvisibility-from-dllstorageclass]") +BENIGN_LANGOPT(VisibilityFromDLLStorageClass, 1, 0, + "override the visibility of globals based on their final DLL storage class [-fvisibility-from-dllstorageclass]") +BENIGN_ENUM_LANGOPT(DLLExportVisibility, VisibilityFromDLLStorageClassKinds, 3, VisibilityFromDLLStorageClassKinds::Default, + "how to adjust the visibility for functions and variables with dllexport annotations [-fvisibility-dllexport]") +BENIGN_ENUM_LANGOPT(NoDLLStorageClassVisibility, VisibilityFromDLLStorageClassKinds, 3, VisibilityFromDLLStorageClassKinds::Hidden, + "how to adjust the visibility for functions and variables without an explicit DLL storage class [-fvisibility-nodllstorageclass]") +BENIGN_ENUM_LANGOPT(ExternDeclDLLImportVisibility, VisibilityFromDLLStorageClassKinds, 3, VisibilityFromDLLStorageClassKinds::Default, + "how to adjust the visibility for external declarations with dllimport annotations [-fvisibility-externs-dllimport]") +BENIGN_ENUM_LANGOPT(ExternDeclNoDLLStorageClassVisibility, VisibilityFromDLLStorageClassKinds, 3, VisibilityFromDLLStorageClassKinds::Hidden, + "how to adjust the visibility for external declarations without an explicit DLL storage class [-fvisibility-externs-nodllstorageclass]") BENIGN_LANGOPT(SemanticInterposition , 1, 0, "semantic interposition") BENIGN_LANGOPT(HalfNoSemanticInterposition, 1, 0, "Like -fno-semantic-interposition but don't use local aliases") @@ -378,6 +380,8 @@ ENUM_LANGOPT(TrivialAutoVarInit, TrivialAutoVarInitKind, 2, TrivialAutoVarInitKi "trivial automatic variable initialization") VALUE_LANGOPT(TrivialAutoVarInitStopAfter, 32, 0, "stop trivial automatic variable initialization after the specified number of instances. Must be greater than 0.") +VALUE_LANGOPT(TrivialAutoVarInitMaxSize, 32, 0, + "stop trivial automatic variable initialization if var size exceeds the specified size (in bytes). Must be greater than 0.") ENUM_LANGOPT(SignedOverflowBehavior, SignedOverflowBehaviorTy, 2, SOB_Undefined, "signed integer overflow handling") ENUM_LANGOPT(ThreadModel , ThreadModelKind, 2, ThreadModelKind::POSIX, "Thread Model") diff --git a/clang/include/clang/Basic/LangOptions.h b/clang/include/clang/Basic/LangOptions.h index 9f986fce2d4..c1cc5548ef1 100644 --- a/clang/include/clang/Basic/LangOptions.h +++ b/clang/include/clang/Basic/LangOptions.h @@ -381,6 +381,28 @@ public: All, }; + enum class VisibilityForcedKinds { + /// Force hidden visibility + ForceHidden, + /// Force protected visibility + ForceProtected, + /// Force default visibility + ForceDefault, + /// Don't alter the visibility + Source, + }; + + enum class VisibilityFromDLLStorageClassKinds { + /// Keep the IR-gen assigned visibility. + Keep, + /// Override the IR-gen assigned visibility with default visibility. + Default, + /// Override the IR-gen assigned visibility with hidden visibility. + Hidden, + /// Override the IR-gen assigned visibility with protected visibility. + Protected, + }; + enum class StrictFlexArraysLevelKind { /// Any trailing array member is a FAM. Default = 0, @@ -392,7 +414,7 @@ public: IncompleteOnly = 3, }; - enum ComplexRangeKind { CX_Full, CX_Limited, CX_Fortran }; + enum ComplexRangeKind { CX_Full, CX_Limited, CX_Fortran, CX_None }; public: /// The used language standard. @@ -662,6 +684,26 @@ public: DefaultVisiblityExportMapping::All; } + bool hasGlobalAllocationFunctionVisibility() const { + return getGlobalAllocationFunctionVisibility() != + VisibilityForcedKinds::Source; + } + + bool hasDefaultGlobalAllocationFunctionVisibility() const { + return getGlobalAllocationFunctionVisibility() == + VisibilityForcedKinds::ForceDefault; + } + + bool hasProtectedGlobalAllocationFunctionVisibility() const { + return getGlobalAllocationFunctionVisibility() == + VisibilityForcedKinds::ForceProtected; + } + + bool hasHiddenGlobalAllocationFunctionVisibility() const { + return getGlobalAllocationFunctionVisibility() == + VisibilityForcedKinds::ForceHidden; + } + /// Remap path prefix according to -fmacro-prefix-path option. void remapPathPrefix(SmallVectorImpl &Path) const; diff --git a/clang/include/clang/Basic/ObjCRuntime.h b/clang/include/clang/Basic/ObjCRuntime.h index f05debe6fea..1ccf60f0b7b 100644 --- a/clang/include/clang/Basic/ObjCRuntime.h +++ b/clang/include/clang/Basic/ObjCRuntime.h @@ -211,7 +211,13 @@ public: case GCC: return false; case GNUstep: - return false; + // This could be enabled for all versions, except for the fact that the + // implementation of `objc_retain` and friends prior to 2.2 call [object + // retain] in their fall-back paths, which leads to infinite recursion if + // the runtime is built with this enabled. Since distributions typically + // build all Objective-C things with the same compiler version and flags, + // it's better to be conservative here. + return (getVersion() >= VersionTuple(2, 2)); case ObjFW: return false; } @@ -248,7 +254,7 @@ public: case GCC: return false; case GNUstep: - return false; + return getVersion() >= VersionTuple(2, 2); case ObjFW: return false; } @@ -266,6 +272,8 @@ public: return getVersion() >= VersionTuple(12, 2); case WatchOS: return getVersion() >= VersionTuple(5, 2); + case GNUstep: + return getVersion() >= VersionTuple(2, 2); default: return false; } @@ -463,7 +471,8 @@ public: case iOS: return true; case WatchOS: return true; case GCC: return false; - case GNUstep: return false; + case GNUstep: + return (getVersion() >= VersionTuple(2, 2)); case ObjFW: return false; } llvm_unreachable("bad kind"); diff --git a/clang/include/clang/Basic/OpenACCKinds.h b/clang/include/clang/Basic/OpenACCKinds.h index b0c157e0023..6487a95910e 100644 --- a/clang/include/clang/Basic/OpenACCKinds.h +++ b/clang/include/clang/Basic/OpenACCKinds.h @@ -14,6 +14,9 @@ #ifndef LLVM_CLANG_BASIC_OPENACCKINDS_H #define LLVM_CLANG_BASIC_OPENACCKINDS_H +#include "clang/Basic/Diagnostic.h" +#include "llvm/Support/ErrorHandling.h" + namespace clang { // Represents the Construct/Directive kind of a pragma directive. Note the // OpenACC standard is inconsistent between calling these Construct vs @@ -62,6 +65,75 @@ enum class OpenACCDirectiveKind { Invalid, }; +inline const StreamingDiagnostic &operator<<(const StreamingDiagnostic &Out, + OpenACCDirectiveKind K) { + switch (K) { + case OpenACCDirectiveKind::Parallel: + return Out << "parallel"; + + case OpenACCDirectiveKind::Serial: + return Out << "serial"; + + case OpenACCDirectiveKind::Kernels: + return Out << "kernels"; + + case OpenACCDirectiveKind::Data: + return Out << "data"; + + case OpenACCDirectiveKind::EnterData: + return Out << "enter data"; + + case OpenACCDirectiveKind::ExitData: + return Out << "exit data"; + + case OpenACCDirectiveKind::HostData: + return Out << "host_data"; + + case OpenACCDirectiveKind::Loop: + return Out << "loop"; + + case OpenACCDirectiveKind::Cache: + return Out << "cache"; + + case OpenACCDirectiveKind::ParallelLoop: + return Out << "parallel loop"; + + case OpenACCDirectiveKind::SerialLoop: + return Out << "serial loop"; + + case OpenACCDirectiveKind::KernelsLoop: + return Out << "kernels loop"; + + case OpenACCDirectiveKind::Atomic: + return Out << "atomic"; + + case OpenACCDirectiveKind::Declare: + return Out << "declare"; + + case OpenACCDirectiveKind::Init: + return Out << "init"; + + case OpenACCDirectiveKind::Shutdown: + return Out << "shutdown"; + + case OpenACCDirectiveKind::Set: + return Out << "set"; + + case OpenACCDirectiveKind::Update: + return Out << "update"; + + case OpenACCDirectiveKind::Wait: + return Out << "wait"; + + case OpenACCDirectiveKind::Routine: + return Out << "routine"; + + case OpenACCDirectiveKind::Invalid: + return Out << ""; + } + llvm_unreachable("Uncovered directive kind"); +} + enum class OpenACCAtomicKind { Read, Write, @@ -82,11 +154,9 @@ enum class OpenACCClauseKind { Independent, /// 'auto' clause, allowed on 'loop' directives. Auto, - /// 'worker' clause, allowed on 'loop' and 'routine' directives. + /// 'worker' clause, allowed on 'loop', Combined, and 'routine' directives. Worker, - /// 'vector' clause, allowed on 'loop' and 'routine' directives. Takes no - /// arguments for 'routine', so the 'loop' version is not yet implemented - /// completely. + /// 'vector' clause, allowed on 'loop', Combined, and 'routine' directives. Vector, /// 'nohost' clause, allowed on 'routine' directives. NoHost, @@ -98,10 +168,203 @@ enum class OpenACCClauseKind { If, /// 'self' clause, allowed on Compute and Combined Constructs, plus 'update'. Self, + /// 'copy' clause, allowed on Compute and Combined Constructs, plus 'data' and + /// 'declare'. + Copy, + /// 'use_device' clause, allowed on 'host_data' construct. + UseDevice, + /// 'attach' clause, allowed on Compute and Combined constructs, plus 'data' + /// and 'enter data'. + Attach, + /// 'delete' clause, allowed on the 'exit data' construct. + Delete, + /// 'detach' clause, allowed on the 'exit data' construct. + Detach, + /// 'device' clause, allowed on the 'update' construct. + Device, + /// 'deviceptr' clause, allowed on Compute and Combined Constructs, plus + /// 'data' and 'declare'. + DevicePtr, + /// 'device_resident' clause, allowed on the 'declare' construct. + DeviceResident, + /// 'firstprivate' clause, allowed on 'parallel', 'serial', 'parallel loop', + /// and 'serial loop' constructs. + FirstPrivate, + /// 'host' clause, allowed on 'update' construct. + Host, + /// 'link' clause, allowed on 'declare' construct. + Link, + /// 'no_create' clause, allowed on allowed on Compute and Combined constructs, + /// plus 'data'. + NoCreate, + /// 'present' clause, allowed on Compute and Combined constructs, plus 'data' + /// and 'declare'. + Present, + /// 'private' clause, allowed on 'parallel', 'serial', 'loop', 'parallel + /// loop', and 'serial loop' constructs. + Private, + /// 'copyout' clause, allowed on Compute and Combined constructs, plus 'data', + /// 'exit data', and 'declare'. + CopyOut, + /// 'copyin' clause, allowed on Compute and Combined constructs, plus 'data', + /// 'enter data', and 'declare'. + CopyIn, + /// 'copyin' clause, allowed on Compute and Combined constructs, plus 'data', + /// 'enter data', and 'declare'. + Create, + /// 'reduction' clause, allowed on Parallel, Serial, Loop, and the combined + /// constructs. + Reduction, + /// 'collapse' clause, allowed on 'loop' and Combined constructs. + Collapse, + /// 'bind' clause, allowed on routine constructs. + Bind, + /// 'vector_length' clause, allowed on 'parallel', 'kernels', 'parallel loop', + /// and 'kernels loop' constructs. + VectorLength, + /// 'num_gangs' clause, allowed on 'parallel', 'kernels', parallel loop', and + /// 'kernels loop' constructs. + NumGangs, + /// 'num_workers' clause, allowed on 'parallel', 'kernels', parallel loop', + /// and 'kernels loop' constructs. + NumWorkers, + /// 'device_num' clause, allowed on 'init', 'shutdown', and 'set' constructs. + DeviceNum, + /// 'default_async' clause, allowed on 'set' construct. + DefaultAsync, + /// 'device_type' clause, allowed on Constructs, 'data', 'init', 'shutdown', + /// 'set', update', 'loop', 'routine', and Combined constructs. + DeviceType, + /// 'dtype' clause, an alias for 'device_type', stored separately for + /// diagnostic purposes. + DType, + /// Represents an invalid clause, for the purposes of parsing. Invalid, }; +inline const StreamingDiagnostic &operator<<(const StreamingDiagnostic &Out, + OpenACCClauseKind K) { + switch (K) { + case OpenACCClauseKind::Finalize: + return Out << "finalize"; + + case OpenACCClauseKind::IfPresent: + return Out << "if_present"; + + case OpenACCClauseKind::Seq: + return Out << "seq"; + + case OpenACCClauseKind::Independent: + return Out << "independent"; + + case OpenACCClauseKind::Auto: + return Out << "auto"; + + case OpenACCClauseKind::Worker: + return Out << "worker"; + + case OpenACCClauseKind::Vector: + return Out << "vector"; + + case OpenACCClauseKind::NoHost: + return Out << "nohost"; + + case OpenACCClauseKind::Default: + return Out << "default"; + + case OpenACCClauseKind::If: + return Out << "if"; + + case OpenACCClauseKind::Self: + return Out << "self"; + + case OpenACCClauseKind::Copy: + return Out << "copy"; + + case OpenACCClauseKind::UseDevice: + return Out << "use_device"; + + case OpenACCClauseKind::Attach: + return Out << "attach"; + + case OpenACCClauseKind::Delete: + return Out << "delete"; + + case OpenACCClauseKind::Detach: + return Out << "detach"; + + case OpenACCClauseKind::Device: + return Out << "device"; + + case OpenACCClauseKind::DevicePtr: + return Out << "deviceptr"; + + case OpenACCClauseKind::DeviceResident: + return Out << "device_resident"; + + case OpenACCClauseKind::FirstPrivate: + return Out << "firstprivate"; + + case OpenACCClauseKind::Host: + return Out << "host"; + + case OpenACCClauseKind::Link: + return Out << "link"; + + case OpenACCClauseKind::NoCreate: + return Out << "no_create"; + + case OpenACCClauseKind::Present: + return Out << "present"; + + case OpenACCClauseKind::Private: + return Out << "private"; + + case OpenACCClauseKind::CopyOut: + return Out << "copyout"; + + case OpenACCClauseKind::CopyIn: + return Out << "copyin"; + + case OpenACCClauseKind::Create: + return Out << "create"; + + case OpenACCClauseKind::Reduction: + return Out << "reduction"; + + case OpenACCClauseKind::Collapse: + return Out << "collapse"; + + case OpenACCClauseKind::Bind: + return Out << "bind"; + + case OpenACCClauseKind::VectorLength: + return Out << "vector_length"; + + case OpenACCClauseKind::NumGangs: + return Out << "num_gangs"; + + case OpenACCClauseKind::NumWorkers: + return Out << "num_workers"; + + case OpenACCClauseKind::DeviceNum: + return Out << "device_num"; + + case OpenACCClauseKind::DefaultAsync: + return Out << "default_async"; + + case OpenACCClauseKind::DeviceType: + return Out << "device_type"; + + case OpenACCClauseKind::DType: + return Out << "dtype"; + + case OpenACCClauseKind::Invalid: + return Out << ""; + } + llvm_unreachable("Uncovered clause kind"); +} enum class OpenACCDefaultClauseKind { /// 'none' option. None, @@ -110,6 +373,29 @@ enum class OpenACCDefaultClauseKind { /// Not a valid option. Invalid, }; + +enum class OpenACCReductionOperator { + /// '+'. + Addition, + /// '*'. + Multiplication, + /// 'max'. + Max, + /// 'min'. + Min, + /// '&'. + BitwiseAnd, + /// '|'. + BitwiseOr, + /// '^'. + BitwiseXOr, + /// '&&'. + And, + /// '||'. + Or, + /// Invalid Reduction Clause Kind. + Invalid, +}; } // namespace clang #endif // LLVM_CLANG_BASIC_OPENACCKINDS_H diff --git a/clang/include/clang/Basic/TargetBuiltins.h b/clang/include/clang/Basic/TargetBuiltins.h index c9f9cbec749..c31834fb52a 100644 --- a/clang/include/clang/Basic/TargetBuiltins.h +++ b/clang/include/clang/Basic/TargetBuiltins.h @@ -291,7 +291,9 @@ namespace clang { bool isZExtReturn() const { return Flags & IsZExtReturn; } bool isByteIndexed() const { return Flags & IsByteIndexed; } bool isOverloadNone() const { return Flags & IsOverloadNone; } - bool isOverloadWhile() const { return Flags & IsOverloadWhile; } + bool isOverloadWhileOrMultiVecCvt() const { + return Flags & IsOverloadWhileOrMultiVecCvt; + } bool isOverloadDefault() const { return !(Flags & OverloadKindMask); } bool isOverloadWhileRW() const { return Flags & IsOverloadWhileRW; } bool isOverloadCvt() const { return Flags & IsOverloadCvt; } diff --git a/clang/include/clang/Basic/TokenKinds.def b/clang/include/clang/Basic/TokenKinds.def index 3f0e1e1a7d4..c10e2adfbe6 100644 --- a/clang/include/clang/Basic/TokenKinds.def +++ b/clang/include/clang/Basic/TokenKinds.def @@ -760,10 +760,11 @@ KEYWORD(__builtin_available , KEYALL) KEYWORD(__builtin_sycl_unique_stable_name, KEYSYCL) // Keywords defined by Attr.td. +// The "EMPTY ## X" is used to prevent early macro-expansion of the keyword. #ifndef KEYWORD_ATTRIBUTE -#define KEYWORD_ATTRIBUTE(X) KEYWORD(X, KEYALL) +#define KEYWORD_ATTRIBUTE(X, HASARG, EMPTY) KEYWORD(EMPTY ## X, KEYALL) #endif -#include "clang/Basic/AttrTokenKinds.inc" +#include "clang/Basic/RegularKeywordAttrInfo.inc" // Clang-specific keywords enabled only in testing. TESTING_KEYWORD(__unknown_anytype , KEYALL) diff --git a/clang/include/clang/Basic/TokenKinds.h b/clang/include/clang/Basic/TokenKinds.h index e4857405bc7..7529b922619 100644 --- a/clang/include/clang/Basic/TokenKinds.h +++ b/clang/include/clang/Basic/TokenKinds.h @@ -109,8 +109,8 @@ bool isPragmaAnnotation(TokenKind K); inline constexpr bool isRegularKeywordAttribute(TokenKind K) { return (false -#define KEYWORD_ATTRIBUTE(X) || (K == tok::kw_##X) -#include "clang/Basic/AttrTokenKinds.inc" +#define KEYWORD_ATTRIBUTE(X, ...) || (K == tok::kw_##X) +#include "clang/Basic/RegularKeywordAttrInfo.inc" ); } diff --git a/clang/include/clang/Basic/arm_sme.td b/clang/include/clang/Basic/arm_sme.td index aac3bd486de..695e1bddf9f 100644 --- a/clang/include/clang/Basic/arm_sme.td +++ b/clang/include/clang/Basic/arm_sme.td @@ -21,19 +21,19 @@ include "arm_sve_sme_incl.td" multiclass ZALoad ch> { let TargetGuard = "sme" in { def NAME # _H : MInst<"svld1_hor_" # n_suffix, "vimPQ", t, - [IsLoad, IsOverloadNone, IsStreaming, IsSharedZA], + [IsLoad, IsOverloadNone, IsStreaming, IsInOutZA], MemEltTyDefault, i_prefix # "_horiz", ch>; def NAME # _H_VNUM : MInst<"svld1_hor_vnum_" # n_suffix, "vimPQl", t, - [IsLoad, IsOverloadNone, IsStreaming, IsSharedZA], + [IsLoad, IsOverloadNone, IsStreaming, IsInOutZA], MemEltTyDefault, i_prefix # "_horiz", ch>; def NAME # _V : MInst<"svld1_ver_" # n_suffix, "vimPQ", t, - [IsLoad, IsOverloadNone, IsStreaming, IsSharedZA], + [IsLoad, IsOverloadNone, IsStreaming, IsInOutZA], MemEltTyDefault, i_prefix # "_vert", ch>; def NAME # _V_VNUM : MInst<"svld1_ver_vnum_" # n_suffix, "vimPQl", t, - [IsLoad, IsOverloadNone, IsStreaming, IsSharedZA], + [IsLoad, IsOverloadNone, IsStreaming, IsInOutZA], MemEltTyDefault, i_prefix # "_vert", ch>; } } @@ -45,11 +45,11 @@ defm SVLD1_ZA64 : ZALoad<"za64", "l", "aarch64_sme_ld1d", [ImmCheck<0, ImmCheck0 defm SVLD1_ZA128 : ZALoad<"za128", "q", "aarch64_sme_ld1q", [ImmCheck<0, ImmCheck0_15>]>; def SVLDR_VNUM_ZA : MInst<"svldr_vnum_za", "vmQl", "", - [IsOverloadNone, IsStreamingCompatible, IsSharedZA], + [IsOverloadNone, IsStreamingCompatible, IsInOutZA], MemEltTyDefault, "aarch64_sme_ldr">; def SVLDR_ZA : MInst<"svldr_za", "vmQ", "", - [IsOverloadNone, IsStreamingCompatible, IsSharedZA], + [IsOverloadNone, IsStreamingCompatible, IsInOutZA], MemEltTyDefault, "aarch64_sme_ldr", []>; //////////////////////////////////////////////////////////////////////////////// @@ -58,19 +58,19 @@ def SVLDR_ZA : MInst<"svldr_za", "vmQ", "", multiclass ZAStore ch> { let TargetGuard = "sme" in { def NAME # _H : MInst<"svst1_hor_" # n_suffix, "vimP%", t, - [IsStore, IsOverloadNone, IsStreaming, IsSharedZA, IsPreservesZA], + [IsStore, IsOverloadNone, IsStreaming, IsInZA], MemEltTyDefault, i_prefix # "_horiz", ch>; def NAME # _H_VNUM : MInst<"svst1_hor_vnum_" # n_suffix, "vimP%l", t, - [IsStore, IsOverloadNone, IsStreaming, IsSharedZA, IsPreservesZA], + [IsStore, IsOverloadNone, IsStreaming, IsInZA], MemEltTyDefault, i_prefix # "_horiz", ch>; def NAME # _V : MInst<"svst1_ver_" # n_suffix, "vimP%", t, - [IsStore, IsOverloadNone, IsStreaming, IsSharedZA, IsPreservesZA], + [IsStore, IsOverloadNone, IsStreaming, IsInZA], MemEltTyDefault, i_prefix # "_vert", ch>; def NAME # _V_VNUM : MInst<"svst1_ver_vnum_" # n_suffix, "vimP%l", t, - [IsStore, IsOverloadNone, IsStreaming, IsSharedZA, IsPreservesZA], + [IsStore, IsOverloadNone, IsStreaming, IsInZA], MemEltTyDefault, i_prefix # "_vert", ch>; } } @@ -82,11 +82,11 @@ defm SVST1_ZA64 : ZAStore<"za64", "l", "aarch64_sme_st1d", [ImmCheck<0, ImmCheck defm SVST1_ZA128 : ZAStore<"za128", "q", "aarch64_sme_st1q", [ImmCheck<0, ImmCheck0_15>]>; def SVSTR_VNUM_ZA : MInst<"svstr_vnum_za", "vm%l", "", - [IsOverloadNone, IsStreamingCompatible, IsSharedZA, IsPreservesZA], + [IsOverloadNone, IsStreamingCompatible, IsInZA], MemEltTyDefault, "aarch64_sme_str">; def SVSTR_ZA : MInst<"svstr_za", "vm%", "", - [IsOverloadNone, IsStreamingCompatible, IsSharedZA, IsPreservesZA], + [IsOverloadNone, IsStreamingCompatible, IsInZA], MemEltTyDefault, "aarch64_sme_str", []>; //////////////////////////////////////////////////////////////////////////////// @@ -96,11 +96,11 @@ multiclass ZARead ch> let TargetGuard = "sme" in { def NAME # _H : SInst<"svread_hor_" # n_suffix # "[_{d}]", "ddPim", t, MergeOp1, i_prefix # "_horiz", - [IsReadZA, IsStreaming, IsSharedZA, IsPreservesZA], ch>; + [IsReadZA, IsStreaming, IsInZA], ch>; def NAME # _V : SInst<"svread_ver_" # n_suffix # "[_{d}]", "ddPim", t, MergeOp1, i_prefix # "_vert", - [IsReadZA, IsStreaming, IsSharedZA, IsPreservesZA], ch>; + [IsReadZA, IsStreaming, IsInZA], ch>; } } @@ -117,11 +117,11 @@ multiclass ZAWrite ch let TargetGuard = "sme" in { def NAME # _H : SInst<"svwrite_hor_" # n_suffix # "[_{d}]", "vimPd", t, MergeOp1, i_prefix # "_horiz", - [IsWriteZA, IsStreaming, IsSharedZA], ch>; + [IsWriteZA, IsStreaming, IsInOutZA], ch>; def NAME # _V : SInst<"svwrite_ver_" # n_suffix # "[_{d}]", "vimPd", t, MergeOp1, i_prefix # "_vert", - [IsWriteZA, IsStreaming, IsSharedZA], ch>; + [IsWriteZA, IsStreaming, IsInOutZA], ch>; } } @@ -136,10 +136,10 @@ defm SVWRITE_ZA128 : ZAWrite<"za128", "csilUcUsUiUlhbfd", "aarch64_sme_writeq", let TargetGuard = "sme" in { def SVZERO_MASK_ZA : SInst<"svzero_mask_za", "vi", "", MergeNone, "aarch64_sme_zero", - [IsOverloadNone, IsStreamingCompatible, IsSharedZA], + [IsOverloadNone, IsStreamingCompatible, IsInOutZA], [ImmCheck<0, ImmCheck0_255>]>; def SVZERO_ZA : SInst<"svzero_za", "v", "", MergeNone, "aarch64_sme_zero", - [IsOverloadNone, IsStreamingCompatible, IsSharedZA]>; + [IsOverloadNone, IsStreamingCompatible, IsOutZA]>; } //////////////////////////////////////////////////////////////////////////////// @@ -149,7 +149,7 @@ multiclass ZACount { let TargetGuard = "sme" in { def NAME : SInst<"sv" # n_suffix, "nv", "", MergeNone, "aarch64_sme_" # n_suffix, - [IsOverloadNone, IsStreamingCompatible, IsPreservesZA]>; + [IsOverloadNone, IsStreamingCompatible]>; } } @@ -164,13 +164,13 @@ defm SVCNTSD : ZACount<"cntsd">; multiclass ZAAdd { let TargetGuard = "sme" in { def NAME # _ZA32: SInst<"sv" # n_suffix # "_za32[_{d}]", "viPPd", "iUi", MergeOp1, - "aarch64_sme_" # n_suffix, [IsStreaming, IsSharedZA], + "aarch64_sme_" # n_suffix, [IsStreaming, IsInOutZA], [ImmCheck<0, ImmCheck0_3>]>; } let TargetGuard = "sme-i16i64" in { def NAME # _ZA64: SInst<"sv" # n_suffix # "_za64[_{d}]", "viPPd", "lUl", MergeOp1, - "aarch64_sme_" # n_suffix, [IsStreaming, IsSharedZA], + "aarch64_sme_" # n_suffix, [IsStreaming, IsInOutZA], [ImmCheck<0, ImmCheck0_7>]>; } } @@ -186,7 +186,7 @@ multiclass ZAIntOuterProd { def NAME # _ZA32_B: SInst<"sv" # n_suffix2 # "_za32[_{d}]", "viPPdd", !cond(!eq(n_suffix1, "s") : "", true: "U") # "c", MergeOp1, "aarch64_sme_" # n_suffix1 # n_suffix2 # "_wide", - [IsStreaming, IsSharedZA], + [IsStreaming, IsInOutZA], [ImmCheck<0, ImmCheck0_3>]>; } @@ -194,7 +194,7 @@ multiclass ZAIntOuterProd { def NAME # _ZA64_H: SInst<"sv" # n_suffix2 # "_za64[_{d}]", "viPPdd", !cond(!eq(n_suffix1, "s") : "", true: "U") # "s", MergeOp1, "aarch64_sme_" # n_suffix1 # n_suffix2 # "_wide", - [IsStreaming, IsSharedZA], + [IsStreaming, IsInOutZA], [ImmCheck<0, ImmCheck0_7>]>; } } @@ -213,7 +213,7 @@ multiclass ZAIntOuterProdMixedSigns { "viPPd" # !cond(!eq(n_suffix1, "su") : "u", true: "x"), !cond(!eq(n_suffix1, "su") : "", true: "U") # "c", MergeOp1, "aarch64_sme_" # n_suffix1 # n_suffix2 # "_wide", - [IsStreaming, IsSharedZA], + [IsStreaming, IsInOutZA], [ImmCheck<0, ImmCheck0_3>]>; } @@ -222,7 +222,7 @@ multiclass ZAIntOuterProdMixedSigns { "viPPd" # !cond(!eq(n_suffix1, "su") : "u", true: "x"), !cond(!eq(n_suffix1, "su") : "", true: "U") # "s", MergeOp1, "aarch64_sme_" # n_suffix1 # n_suffix2 # "_wide", - [IsStreaming, IsSharedZA], + [IsStreaming, IsInOutZA], [ImmCheck<0, ImmCheck0_7>]>; } } @@ -239,24 +239,24 @@ multiclass ZAFPOuterProd { let TargetGuard = "sme" in { def NAME # _ZA32_B: SInst<"sv" # n_suffix # "_za32[_{d}]", "viPPdd", "h", MergeOp1, "aarch64_sme_" # n_suffix # "_wide", - [IsStreaming, IsSharedZA], + [IsStreaming, IsInOutZA], [ImmCheck<0, ImmCheck0_3>]>; def NAME # _ZA32_H: SInst<"sv" # n_suffix # "_za32[_{d}]", "viPPdd", "b", MergeOp1, "aarch64_sme_" # n_suffix # "_wide", - [IsStreaming, IsSharedZA], + [IsStreaming, IsInOutZA], [ImmCheck<0, ImmCheck0_3>]>; def NAME # _ZA32_S: SInst<"sv" # n_suffix # "_za32[_{d}]", "viPPdd", "f", MergeOp1, "aarch64_sme_" # n_suffix, - [IsStreaming, IsSharedZA], + [IsStreaming, IsInOutZA], [ImmCheck<0, ImmCheck0_3>]>; } let TargetGuard = "sme-f64f64" in { def NAME # _ZA64_D: SInst<"sv" # n_suffix # "_za64[_{d}]", "viPPdd", "d", MergeOp1, "aarch64_sme_" # n_suffix, - [IsStreaming, IsSharedZA], + [IsStreaming, IsInOutZA], [ImmCheck<0, ImmCheck0_7>]>; } } @@ -269,29 +269,29 @@ defm SVMOPS : ZAFPOuterProd<"mops">; multiclass ZAAddSub { let TargetGuard = "sme2" in { - def NAME # _WRITE_SINGLE_ZA32_VG1X2_I32 : Inst<"sv" # n_suffix # "_write[_single]_za32[_{d}]_vg1x2", "vm2d", "iUi", MergeNone, "aarch64_sme_" # n_suffix # "_write_single_za_vg1x2", [IsStreaming, IsSharedZA], []>; - def NAME # _WRITE_SINGLE_ZA32_VG1X4_I32 : Inst<"sv" # n_suffix # "_write[_single]_za32[_{d}]_vg1x4", "vm4d", "iUi", MergeNone, "aarch64_sme_" # n_suffix # "_write_single_za_vg1x4", [IsStreaming, IsSharedZA], []>; + def NAME # _WRITE_SINGLE_ZA32_VG1X2_I32 : Inst<"sv" # n_suffix # "_write[_single]_za32[_{d}]_vg1x2", "vm2d", "iUi", MergeNone, "aarch64_sme_" # n_suffix # "_write_single_za_vg1x2", [IsStreaming, IsInOutZA], []>; + def NAME # _WRITE_SINGLE_ZA32_VG1X4_I32 : Inst<"sv" # n_suffix # "_write[_single]_za32[_{d}]_vg1x4", "vm4d", "iUi", MergeNone, "aarch64_sme_" # n_suffix # "_write_single_za_vg1x4", [IsStreaming, IsInOutZA], []>; - def NAME # _WRITE_ZA32_VG1X2_I32 : Inst<"sv" # n_suffix # "_write_za32[_{d}]_vg1x2", "vm22", "iUi", MergeNone, "aarch64_sme_" # n_suffix # "_write_za_vg1x2", [IsStreaming, IsSharedZA], []>; - def NAME # _WRITE_ZA32_VG1X4_I32 : Inst<"sv" # n_suffix # "_write_za32[_{d}]_vg1x4", "vm44", "iUi", MergeNone, "aarch64_sme_" # n_suffix # "_write_za_vg1x4", [IsStreaming, IsSharedZA], []>; + def NAME # _WRITE_ZA32_VG1X2_I32 : Inst<"sv" # n_suffix # "_write_za32[_{d}]_vg1x2", "vm22", "iUi", MergeNone, "aarch64_sme_" # n_suffix # "_write_za_vg1x2", [IsStreaming, IsInOutZA], []>; + def NAME # _WRITE_ZA32_VG1X4_I32 : Inst<"sv" # n_suffix # "_write_za32[_{d}]_vg1x4", "vm44", "iUi", MergeNone, "aarch64_sme_" # n_suffix # "_write_za_vg1x4", [IsStreaming, IsInOutZA], []>; - def NAME # _ZA32_VG1x2_I32 : Inst<"sv" # n_suffix # "_za32[_{d}]_vg1x2", "vm2", "iUif", MergeNone, "aarch64_sme_" # n_suffix # "_za32_vg1x2", [IsStreaming, IsSharedZA], []>; - def NAME # _ZA32_VG1X4_I32 : Inst<"sv" # n_suffix # "_za32[_{d}]_vg1x4", "vm4", "iUif", MergeNone, "aarch64_sme_" # n_suffix # "_za32_vg1x4", [IsStreaming, IsSharedZA], []>; + def NAME # _ZA32_VG1x2_I32 : Inst<"sv" # n_suffix # "_za32[_{d}]_vg1x2", "vm2", "iUif", MergeNone, "aarch64_sme_" # n_suffix # "_za32_vg1x2", [IsStreaming, IsInOutZA], []>; + def NAME # _ZA32_VG1X4_I32 : Inst<"sv" # n_suffix # "_za32[_{d}]_vg1x4", "vm4", "iUif", MergeNone, "aarch64_sme_" # n_suffix # "_za32_vg1x4", [IsStreaming, IsInOutZA], []>; let TargetGuard = "sme-i16i64" in { - def NAME # _WRITE_SINGLE_ZA64_VG1X2_I64 : Inst<"sv" # n_suffix # "_write[_single]_za64[_{d}]_vg1x2", "vm2d", "lUl", MergeNone, "aarch64_sme_" # n_suffix # "_write_single_za_vg1x2", [IsStreaming, IsSharedZA], []>; - def NAME # _WRITE_SINGLE_ZA64_VG1X4_I64 : Inst<"sv" # n_suffix # "_write[_single]_za64[_{d}]_vg1x4", "vm4d", "lUl", MergeNone, "aarch64_sme_" # n_suffix # "_write_single_za_vg1x4", [IsStreaming, IsSharedZA], []>; + def NAME # _WRITE_SINGLE_ZA64_VG1X2_I64 : Inst<"sv" # n_suffix # "_write[_single]_za64[_{d}]_vg1x2", "vm2d", "lUl", MergeNone, "aarch64_sme_" # n_suffix # "_write_single_za_vg1x2", [IsStreaming, IsInOutZA], []>; + def NAME # _WRITE_SINGLE_ZA64_VG1X4_I64 : Inst<"sv" # n_suffix # "_write[_single]_za64[_{d}]_vg1x4", "vm4d", "lUl", MergeNone, "aarch64_sme_" # n_suffix # "_write_single_za_vg1x4", [IsStreaming, IsInOutZA], []>; - def NAME # _WRITE_ZA64_VG1x2_I64 : Inst<"sv" # n_suffix # "_write_za64[_{d}]_vg1x2", "vm22", "lUl", MergeNone, "aarch64_sme_" # n_suffix # "_write_za_vg1x2", [IsStreaming, IsSharedZA], []>; - def NAME # _WRITE_ZA64_VG1x4_I64 : Inst<"sv" # n_suffix # "_write_za64[_{d}]_vg1x4", "vm44", "lUl", MergeNone, "aarch64_sme_" # n_suffix # "_write_za_vg1x4", [IsStreaming, IsSharedZA], []>; + def NAME # _WRITE_ZA64_VG1x2_I64 : Inst<"sv" # n_suffix # "_write_za64[_{d}]_vg1x2", "vm22", "lUl", MergeNone, "aarch64_sme_" # n_suffix # "_write_za_vg1x2", [IsStreaming, IsInOutZA], []>; + def NAME # _WRITE_ZA64_VG1x4_I64 : Inst<"sv" # n_suffix # "_write_za64[_{d}]_vg1x4", "vm44", "lUl", MergeNone, "aarch64_sme_" # n_suffix # "_write_za_vg1x4", [IsStreaming, IsInOutZA], []>; - def NAME # _ZA64_VG1X2_I64 : Inst<"sv" # n_suffix # "_za64[_{d}]_vg1x2", "vm2", "lUl", MergeNone, "aarch64_sme_" # n_suffix # "_za64_vg1x2", [IsStreaming, IsSharedZA], []>; - def NAME # _ZA64_VG1X4_I64 : Inst<"sv" # n_suffix # "_za64[_{d}]_vg1x4", "vm4", "lUl", MergeNone, "aarch64_sme_" # n_suffix # "_za64_vg1x4", [IsStreaming, IsSharedZA], []>; + def NAME # _ZA64_VG1X2_I64 : Inst<"sv" # n_suffix # "_za64[_{d}]_vg1x2", "vm2", "lUl", MergeNone, "aarch64_sme_" # n_suffix # "_za64_vg1x2", [IsStreaming, IsInOutZA], []>; + def NAME # _ZA64_VG1X4_I64 : Inst<"sv" # n_suffix # "_za64[_{d}]_vg1x4", "vm4", "lUl", MergeNone, "aarch64_sme_" # n_suffix # "_za64_vg1x4", [IsStreaming, IsInOutZA], []>; } let TargetGuard = "sme-f64f64" in { - def NAME # _ZA64_VG1X2_F64 : Inst<"sv" # n_suffix # "_za64[_{d}]_vg1x2", "vm2", "d", MergeNone, "aarch64_sme_" # n_suffix # "_za64_vg1x2", [IsStreaming, IsSharedZA], []>; - def NAME # _ZA64_VG1X4_F64 : Inst<"sv" # n_suffix # "_za64[_{d}]_vg1x4", "vm4", "d", MergeNone, "aarch64_sme_" # n_suffix # "_za64_vg1x4", [IsStreaming, IsSharedZA], []>; + def NAME # _ZA64_VG1X2_F64 : Inst<"sv" # n_suffix # "_za64[_{d}]_vg1x2", "vm2", "d", MergeNone, "aarch64_sme_" # n_suffix # "_za64_vg1x2", [IsStreaming, IsInOutZA], []>; + def NAME # _ZA64_VG1X4_F64 : Inst<"sv" # n_suffix # "_za64[_{d}]_vg1x4", "vm4", "d", MergeNone, "aarch64_sme_" # n_suffix # "_za64_vg1x4", [IsStreaming, IsInOutZA], []>; } } } @@ -306,12 +306,12 @@ defm SVSUB : ZAAddSub<"sub">; // multiclass ZAWrite_VG checks> { - def NAME # _VG2_H : Inst<"svwrite_hor_" # n # "[_{d}]_vg2", "vim2", t, MergeNone, i # "_hor_vg2", [IsSharedZA, IsStreaming], checks>; - def NAME # _VG2_V : Inst<"svwrite_ver_" # n # "[_{d}]_vg2", "vim2", t, MergeNone, i # "_ver_vg2", [IsSharedZA, IsStreaming], checks>; - def NAME # _VG4_H : Inst<"svwrite_hor_" # n # "[_{d}]_vg4", "vim4", t, MergeNone, i # "_hor_vg4", [IsSharedZA, IsStreaming], checks>; - def NAME # _VG4_V : Inst<"svwrite_ver_" # n # "[_{d}]_vg4", "vim4", t, MergeNone, i # "_ver_vg4", [IsSharedZA, IsStreaming], checks>; - def NAME # _VG1x2 : Inst<"svwrite_" # n # "[_{d}]_vg1x2", "vm2", t, MergeNone, i # "_vg1x2", [IsSharedZA, IsStreaming], []>; - def NAME # _VG1x4 : Inst<"svwrite_" # n # "[_{d}]_vg1x4", "vm4", t, MergeNone, i # "_vg1x4", [IsSharedZA, IsStreaming], []>; + def NAME # _VG2_H : Inst<"svwrite_hor_" # n # "[_{d}]_vg2", "vim2", t, MergeNone, i # "_hor_vg2", [IsInOutZA, IsStreaming], checks>; + def NAME # _VG2_V : Inst<"svwrite_ver_" # n # "[_{d}]_vg2", "vim2", t, MergeNone, i # "_ver_vg2", [IsInOutZA, IsStreaming], checks>; + def NAME # _VG4_H : Inst<"svwrite_hor_" # n # "[_{d}]_vg4", "vim4", t, MergeNone, i # "_hor_vg4", [IsInOutZA, IsStreaming], checks>; + def NAME # _VG4_V : Inst<"svwrite_ver_" # n # "[_{d}]_vg4", "vim4", t, MergeNone, i # "_ver_vg4", [IsInOutZA, IsStreaming], checks>; + def NAME # _VG1x2 : Inst<"svwrite_" # n # "[_{d}]_vg1x2", "vm2", t, MergeNone, i # "_vg1x2", [IsInOutZA, IsStreaming], []>; + def NAME # _VG1x4 : Inst<"svwrite_" # n # "[_{d}]_vg1x4", "vm4", t, MergeNone, i # "_vg1x4", [IsInOutZA, IsStreaming], []>; } let TargetGuard = "sme2" in { @@ -322,12 +322,12 @@ let TargetGuard = "sme2" in { } multiclass ZARead_VG checks> { - def NAME # _VG2_H : Inst<"svread_hor_" # n # "_{d}_vg2", "2im", t, MergeNone, i # "_hor_vg2", [IsSharedZA, IsPreservesZA, IsStreaming], checks>; - def NAME # _VG2_V : Inst<"svread_ver_" # n # "_{d}_vg2", "2im", t, MergeNone, i # "_ver_vg2", [IsSharedZA, IsPreservesZA, IsStreaming], checks>; - def NAME # _VG4_H : Inst<"svread_hor_" # n # "_{d}_vg4", "4im", t, MergeNone, i # "_hor_vg4", [IsSharedZA, IsPreservesZA, IsStreaming], checks>; - def NAME # _VG4_V : Inst<"svread_ver_" # n # "_{d}_vg4", "4im", t, MergeNone, i # "_ver_vg4", [IsSharedZA, IsPreservesZA, IsStreaming], checks>; - def NAME # _VG1x2 : Inst<"svread_" # n # "_{d}_vg1x2", "2m", t, MergeNone, i # "_vg1x2", [IsSharedZA, IsPreservesZA, IsStreaming], []>; - def NAME # _VG1x4 : Inst<"svread_" # n # "_{d}_vg1x4", "4m", t, MergeNone, i # "_vg1x4", [IsSharedZA, IsPreservesZA, IsStreaming], []>; + def NAME # _VG2_H : Inst<"svread_hor_" # n # "_{d}_vg2", "2im", t, MergeNone, i # "_hor_vg2", [IsInZA, IsStreaming], checks>; + def NAME # _VG2_V : Inst<"svread_ver_" # n # "_{d}_vg2", "2im", t, MergeNone, i # "_ver_vg2", [IsInZA, IsStreaming], checks>; + def NAME # _VG4_H : Inst<"svread_hor_" # n # "_{d}_vg4", "4im", t, MergeNone, i # "_hor_vg4", [IsInZA, IsStreaming], checks>; + def NAME # _VG4_V : Inst<"svread_ver_" # n # "_{d}_vg4", "4im", t, MergeNone, i # "_ver_vg4", [IsInZA, IsStreaming], checks>; + def NAME # _VG1x2 : Inst<"svread_" # n # "_{d}_vg1x2", "2m", t, MergeNone, i # "_vg1x2", [IsInZA, IsStreaming], []>; + def NAME # _VG1x4 : Inst<"svread_" # n # "_{d}_vg1x4", "4m", t, MergeNone, i # "_vg1x4", [IsInZA, IsStreaming], []>; } let TargetGuard = "sme2" in { @@ -342,331 +342,331 @@ let TargetGuard = "sme2" in { // let TargetGuard = "sme2" in { - def SVSMOPA : Inst<"svmopa_za32[_{d}]_m", "viPPdd", "s", MergeNone, "aarch64_sme_smopa_za32", [IsSharedZA, IsStreaming], [ImmCheck<0, ImmCheck0_3>]>; - def SVUSMOPA : Inst<"svmopa_za32[_{d}]_m", "viPPdd", "Us", MergeNone, "aarch64_sme_umopa_za32", [IsSharedZA, IsStreaming], [ImmCheck<0, ImmCheck0_3>]>; + def SVSMOPA : Inst<"svmopa_za32[_{d}]_m", "viPPdd", "s", MergeNone, "aarch64_sme_smopa_za32", [IsInOutZA, IsStreaming], [ImmCheck<0, ImmCheck0_3>]>; + def SVUSMOPA : Inst<"svmopa_za32[_{d}]_m", "viPPdd", "Us", MergeNone, "aarch64_sme_umopa_za32", [IsInOutZA, IsStreaming], [ImmCheck<0, ImmCheck0_3>]>; - def SVSMOPS : Inst<"svmops_za32[_{d}]_m", "viPPdd", "s", MergeNone, "aarch64_sme_smops_za32", [IsSharedZA, IsStreaming], [ImmCheck<0, ImmCheck0_3>]>; - def SVUSMOPS : Inst<"svmops_za32[_{d}]_m", "viPPdd", "Us", MergeNone, "aarch64_sme_umops_za32", [IsSharedZA, IsStreaming], [ImmCheck<0, ImmCheck0_3>]>; + def SVSMOPS : Inst<"svmops_za32[_{d}]_m", "viPPdd", "s", MergeNone, "aarch64_sme_smops_za32", [IsInOutZA, IsStreaming], [ImmCheck<0, ImmCheck0_3>]>; + def SVUSMOPS : Inst<"svmops_za32[_{d}]_m", "viPPdd", "Us", MergeNone, "aarch64_sme_umops_za32", [IsInOutZA, IsStreaming], [ImmCheck<0, ImmCheck0_3>]>; - def SVBMOPA : Inst<"svbmopa_za32[_{d}]_m", "viPPdd", "iUi", MergeNone, "aarch64_sme_bmopa_za32", [IsSharedZA, IsStreaming], [ImmCheck<0, ImmCheck0_3>]>; + def SVBMOPA : Inst<"svbmopa_za32[_{d}]_m", "viPPdd", "iUi", MergeNone, "aarch64_sme_bmopa_za32", [IsInOutZA, IsStreaming], [ImmCheck<0, ImmCheck0_3>]>; - def SVBMOPS : Inst<"svbmops_za32[_{d}]_m", "viPPdd", "iUi", MergeNone, "aarch64_sme_bmops_za32", [IsSharedZA, IsStreaming], [ImmCheck<0, ImmCheck0_3>]>; + def SVBMOPS : Inst<"svbmops_za32[_{d}]_m", "viPPdd", "iUi", MergeNone, "aarch64_sme_bmops_za32", [IsInOutZA, IsStreaming], [ImmCheck<0, ImmCheck0_3>]>; // VERTICAL DOT-PRODUCT - def SVVDOT_LANE_ZA32_VG1x2_S : Inst<"svvdot_lane_za32[_{d}]_vg1x2", "vm2di", "s", MergeNone, "aarch64_sme_svdot_lane_za32_vg1x2", [IsStreaming, IsSharedZA], [ImmCheck<3, ImmCheck0_3>]>; - def SVVDOT_LANE_ZA32_VG1x4_S : Inst<"svvdot_lane_za32[_{d}]_vg1x4", "vm4di", "c", MergeNone, "aarch64_sme_svdot_lane_za32_vg1x4", [IsStreaming, IsSharedZA], [ImmCheck<3, ImmCheck0_3>]>; - def SVVDOT_LANE_ZA32_VG1x2_U : Inst<"svvdot_lane_za32[_{d}]_vg1x2", "vm2di", "Us", MergeNone, "aarch64_sme_uvdot_lane_za32_vg1x2", [IsStreaming, IsSharedZA], [ImmCheck<3, ImmCheck0_3>]>; - def SVVDOT_LANE_ZA32_VG1x4_U : Inst<"svvdot_lane_za32[_{d}]_vg1x4", "vm4di", "Uc", MergeNone, "aarch64_sme_uvdot_lane_za32_vg1x4", [IsStreaming, IsSharedZA], [ImmCheck<3, ImmCheck0_3>]>; - def SVVDOT_LANE_ZA32_VG1x2_F : Inst<"svvdot_lane_za32[_{d}]_vg1x2", "vm2di", "hb", MergeNone, "aarch64_sme_fvdot_lane_za32_vg1x2", [IsStreaming, IsSharedZA], [ImmCheck<3, ImmCheck0_3>]>; - def SVSUVDOT_LANE_ZA32_VG1x4 : Inst<"svsuvdot_lane_za32[_{d}]_vg1x4", "vm4di", "c", MergeNone, "aarch64_sme_suvdot_lane_za32_vg1x4", [IsStreaming, IsSharedZA], [ImmCheck<3, ImmCheck0_3>]>; - def SVUSVDOT_LANE_ZA32_VG1x4 : Inst<"svusvdot_lane_za32[_{d}]_vg1x4", "vm4di", "Uc", MergeNone, "aarch64_sme_usvdot_lane_za32_vg1x4", [IsStreaming, IsSharedZA], [ImmCheck<3, ImmCheck0_3>]>; + def SVVDOT_LANE_ZA32_VG1x2_S : Inst<"svvdot_lane_za32[_{d}]_vg1x2", "vm2di", "s", MergeNone, "aarch64_sme_svdot_lane_za32_vg1x2", [IsStreaming, IsInOutZA], [ImmCheck<3, ImmCheck0_3>]>; + def SVVDOT_LANE_ZA32_VG1x4_S : Inst<"svvdot_lane_za32[_{d}]_vg1x4", "vm4di", "c", MergeNone, "aarch64_sme_svdot_lane_za32_vg1x4", [IsStreaming, IsInOutZA], [ImmCheck<3, ImmCheck0_3>]>; + def SVVDOT_LANE_ZA32_VG1x2_U : Inst<"svvdot_lane_za32[_{d}]_vg1x2", "vm2di", "Us", MergeNone, "aarch64_sme_uvdot_lane_za32_vg1x2", [IsStreaming, IsInOutZA], [ImmCheck<3, ImmCheck0_3>]>; + def SVVDOT_LANE_ZA32_VG1x4_U : Inst<"svvdot_lane_za32[_{d}]_vg1x4", "vm4di", "Uc", MergeNone, "aarch64_sme_uvdot_lane_za32_vg1x4", [IsStreaming, IsInOutZA], [ImmCheck<3, ImmCheck0_3>]>; + def SVVDOT_LANE_ZA32_VG1x2_F : Inst<"svvdot_lane_za32[_{d}]_vg1x2", "vm2di", "hb", MergeNone, "aarch64_sme_fvdot_lane_za32_vg1x2", [IsStreaming, IsInOutZA], [ImmCheck<3, ImmCheck0_3>]>; + def SVSUVDOT_LANE_ZA32_VG1x4 : Inst<"svsuvdot_lane_za32[_{d}]_vg1x4", "vm4di", "c", MergeNone, "aarch64_sme_suvdot_lane_za32_vg1x4", [IsStreaming, IsInOutZA], [ImmCheck<3, ImmCheck0_3>]>; + def SVUSVDOT_LANE_ZA32_VG1x4 : Inst<"svusvdot_lane_za32[_{d}]_vg1x4", "vm4di", "Uc", MergeNone, "aarch64_sme_usvdot_lane_za32_vg1x4", [IsStreaming, IsInOutZA], [ImmCheck<3, ImmCheck0_3>]>; // Multi-vector signed & unsigned integer dot-product - def SVDOT_MULTI_ZA32_VG1x2_S : Inst<"svdot_za32[_{d}]_vg1x2", "vm22", "cs", MergeNone, "aarch64_sme_sdot_za32_vg1x2", [IsStreaming, IsSharedZA], []>; - def SVDOT_MULTI_ZA32_VG1x4_S : Inst<"svdot_za32[_{d}]_vg1x4", "vm44", "cs", MergeNone, "aarch64_sme_sdot_za32_vg1x4", [IsStreaming, IsSharedZA], []>; - def SVDOT_MULTI_ZA32_VG1x2_U : Inst<"svdot_za32[_{d}]_vg1x2", "vm22", "UcUs", MergeNone, "aarch64_sme_udot_za32_vg1x2", [IsStreaming, IsSharedZA], []>; - def SVDOT_MULTI_ZA32_VG1x4_U : Inst<"svdot_za32[_{d}]_vg1x4", "vm44", "UcUs", MergeNone, "aarch64_sme_udot_za32_vg1x4", [IsStreaming, IsSharedZA], []>; - def SVDOT_SINGLE_ZA32_VG1x2_S : Inst<"svdot[_single]_za32[_{d}]_vg1x2", "vm2d", "cs", MergeNone, "aarch64_sme_sdot_single_za32_vg1x2", [IsStreaming, IsSharedZA], []>; - def SVDOT_SINGLE_ZA32_VG1x4_S : Inst<"svdot[_single]_za32[_{d}]_vg1x4", "vm4d", "cs", MergeNone, "aarch64_sme_sdot_single_za32_vg1x4", [IsStreaming, IsSharedZA], []>; - def SVDOT_SINGLE_ZA32_VG1x2_U : Inst<"svdot[_single]_za32[_{d}]_vg1x2", "vm2d", "UcUs", MergeNone, "aarch64_sme_udot_single_za32_vg1x2", [IsStreaming, IsSharedZA], []>; - def SVDOT_SINGLE_ZA32_VG1x4_U : Inst<"svdot[_single]_za32[_{d}]_vg1x4", "vm4d", "UcUs", MergeNone, "aarch64_sme_udot_single_za32_vg1x4", [IsStreaming, IsSharedZA], []>; - def SVDOT_LANE_ZA32_VG1x2_S : Inst<"svdot_lane_za32[_{d}]_vg1x2", "vm2di", "cs", MergeNone, "aarch64_sme_sdot_lane_za32_vg1x2", [IsStreaming, IsSharedZA], [ImmCheck<3, ImmCheck0_3>]>; - def SVDOT_LANE_ZA32_VG1x4_S : Inst<"svdot_lane_za32[_{d}]_vg1x4", "vm4di", "cs", MergeNone, "aarch64_sme_sdot_lane_za32_vg1x4", [IsStreaming, IsSharedZA], [ImmCheck<3, ImmCheck0_3>]>; - def SVDOT_LANE_ZA32_VG1x2_U : Inst<"svdot_lane_za32[_{d}]_vg1x2", "vm2di", "UcUs", MergeNone, "aarch64_sme_udot_lane_za32_vg1x2", [IsStreaming, IsSharedZA], [ImmCheck<3, ImmCheck0_3>]>; - def SVDOT_LANE_ZA32_VG1x4_U : Inst<"svdot_lane_za32[_{d}]_vg1x4", "vm4di", "UcUs", MergeNone, "aarch64_sme_udot_lane_za32_vg1x4", [IsStreaming, IsSharedZA], [ImmCheck<3, ImmCheck0_3>]>; + def SVDOT_MULTI_ZA32_VG1x2_S : Inst<"svdot_za32[_{d}]_vg1x2", "vm22", "cs", MergeNone, "aarch64_sme_sdot_za32_vg1x2", [IsStreaming, IsInOutZA], []>; + def SVDOT_MULTI_ZA32_VG1x4_S : Inst<"svdot_za32[_{d}]_vg1x4", "vm44", "cs", MergeNone, "aarch64_sme_sdot_za32_vg1x4", [IsStreaming, IsInOutZA], []>; + def SVDOT_MULTI_ZA32_VG1x2_U : Inst<"svdot_za32[_{d}]_vg1x2", "vm22", "UcUs", MergeNone, "aarch64_sme_udot_za32_vg1x2", [IsStreaming, IsInOutZA], []>; + def SVDOT_MULTI_ZA32_VG1x4_U : Inst<"svdot_za32[_{d}]_vg1x4", "vm44", "UcUs", MergeNone, "aarch64_sme_udot_za32_vg1x4", [IsStreaming, IsInOutZA], []>; + def SVDOT_SINGLE_ZA32_VG1x2_S : Inst<"svdot[_single]_za32[_{d}]_vg1x2", "vm2d", "cs", MergeNone, "aarch64_sme_sdot_single_za32_vg1x2", [IsStreaming, IsInOutZA], []>; + def SVDOT_SINGLE_ZA32_VG1x4_S : Inst<"svdot[_single]_za32[_{d}]_vg1x4", "vm4d", "cs", MergeNone, "aarch64_sme_sdot_single_za32_vg1x4", [IsStreaming, IsInOutZA], []>; + def SVDOT_SINGLE_ZA32_VG1x2_U : Inst<"svdot[_single]_za32[_{d}]_vg1x2", "vm2d", "UcUs", MergeNone, "aarch64_sme_udot_single_za32_vg1x2", [IsStreaming, IsInOutZA], []>; + def SVDOT_SINGLE_ZA32_VG1x4_U : Inst<"svdot[_single]_za32[_{d}]_vg1x4", "vm4d", "UcUs", MergeNone, "aarch64_sme_udot_single_za32_vg1x4", [IsStreaming, IsInOutZA], []>; + def SVDOT_LANE_ZA32_VG1x2_S : Inst<"svdot_lane_za32[_{d}]_vg1x2", "vm2di", "cs", MergeNone, "aarch64_sme_sdot_lane_za32_vg1x2", [IsStreaming, IsInOutZA], [ImmCheck<3, ImmCheck0_3>]>; + def SVDOT_LANE_ZA32_VG1x4_S : Inst<"svdot_lane_za32[_{d}]_vg1x4", "vm4di", "cs", MergeNone, "aarch64_sme_sdot_lane_za32_vg1x4", [IsStreaming, IsInOutZA], [ImmCheck<3, ImmCheck0_3>]>; + def SVDOT_LANE_ZA32_VG1x2_U : Inst<"svdot_lane_za32[_{d}]_vg1x2", "vm2di", "UcUs", MergeNone, "aarch64_sme_udot_lane_za32_vg1x2", [IsStreaming, IsInOutZA], [ImmCheck<3, ImmCheck0_3>]>; + def SVDOT_LANE_ZA32_VG1x4_U : Inst<"svdot_lane_za32[_{d}]_vg1x4", "vm4di", "UcUs", MergeNone, "aarch64_sme_udot_lane_za32_vg1x4", [IsStreaming, IsInOutZA], [ImmCheck<3, ImmCheck0_3>]>; - def SVUSDOT_SINGLE_ZA32_VG1x2 : Inst<"svusdot[_single]_za32[_{d}]_vg1x2", "vm2.dx", "Uc", MergeNone, "aarch64_sme_usdot_single_za32_vg1x2", [IsStreaming, IsSharedZA], []>; - def SVUSDOT_SINGLE_ZA32_VG1x4 : Inst<"svusdot[_single]_za32[_{d}]_vg1x4", "vm4.dx", "Uc", MergeNone, "aarch64_sme_usdot_single_za32_vg1x4", [IsStreaming, IsSharedZA], []>; - def SVUSDOT_MULTI_ZA32_VG1x2 : Inst<"svusdot_za32[_{d}]_vg1x2", "vm2.d2.x", "Uc", MergeNone, "aarch64_sme_usdot_za32_vg1x2", [IsStreaming, IsSharedZA], []>; - def SVUSDOT_MULTI_ZA32_VG1x4 : Inst<"svusdot_za32[_{d}]_vg1x4", "vm4.d4.x", "Uc", MergeNone, "aarch64_sme_usdot_za32_vg1x4", [IsStreaming, IsSharedZA], []>; - def SVUSDOT_LANE_ZA32_VG1x2 : Inst<"svusdot_lane_za32[_{d}]_vg1x2", "vm2.dxi", "Uc", MergeNone, "aarch64_sme_usdot_lane_za32_vg1x2", [IsStreaming, IsSharedZA], [ImmCheck<3, ImmCheck0_3>]>; - def SVUSDOT_LANE_ZA32_VG1x4 : Inst<"svusdot_lane_za32[_{d}]_vg1x4", "vm4.dxi", "Uc", MergeNone, "aarch64_sme_usdot_lane_za32_vg1x4", [IsStreaming, IsSharedZA], [ImmCheck<3, ImmCheck0_3>]>; + def SVUSDOT_SINGLE_ZA32_VG1x2 : Inst<"svusdot[_single]_za32[_{d}]_vg1x2", "vm2.dx", "Uc", MergeNone, "aarch64_sme_usdot_single_za32_vg1x2", [IsStreaming, IsInOutZA], []>; + def SVUSDOT_SINGLE_ZA32_VG1x4 : Inst<"svusdot[_single]_za32[_{d}]_vg1x4", "vm4.dx", "Uc", MergeNone, "aarch64_sme_usdot_single_za32_vg1x4", [IsStreaming, IsInOutZA], []>; + def SVUSDOT_MULTI_ZA32_VG1x2 : Inst<"svusdot_za32[_{d}]_vg1x2", "vm2.d2.x", "Uc", MergeNone, "aarch64_sme_usdot_za32_vg1x2", [IsStreaming, IsInOutZA], []>; + def SVUSDOT_MULTI_ZA32_VG1x4 : Inst<"svusdot_za32[_{d}]_vg1x4", "vm4.d4.x", "Uc", MergeNone, "aarch64_sme_usdot_za32_vg1x4", [IsStreaming, IsInOutZA], []>; + def SVUSDOT_LANE_ZA32_VG1x2 : Inst<"svusdot_lane_za32[_{d}]_vg1x2", "vm2.dxi", "Uc", MergeNone, "aarch64_sme_usdot_lane_za32_vg1x2", [IsStreaming, IsInOutZA], [ImmCheck<3, ImmCheck0_3>]>; + def SVUSDOT_LANE_ZA32_VG1x4 : Inst<"svusdot_lane_za32[_{d}]_vg1x4", "vm4.dxi", "Uc", MergeNone, "aarch64_sme_usdot_lane_za32_vg1x4", [IsStreaming, IsInOutZA], [ImmCheck<3, ImmCheck0_3>]>; - def SVSUDOT_SINGLE_ZA32_VG1x2 : Inst<"svsudot[_single]_za32[_{d}]_vg1x2", "vm2.du", "c", MergeNone, "aarch64_sme_sudot_single_za32_vg1x2", [IsStreaming, IsSharedZA], []>; - def SVSUDOT_SINGLE_ZA32_VG1x4 : Inst<"svsudot[_single]_za32[_{d}]_vg1x4", "vm4.du", "c", MergeNone, "aarch64_sme_sudot_single_za32_vg1x4", [IsStreaming, IsSharedZA], []>; + def SVSUDOT_SINGLE_ZA32_VG1x2 : Inst<"svsudot[_single]_za32[_{d}]_vg1x2", "vm2.du", "c", MergeNone, "aarch64_sme_sudot_single_za32_vg1x2", [IsStreaming, IsInOutZA], []>; + def SVSUDOT_SINGLE_ZA32_VG1x4 : Inst<"svsudot[_single]_za32[_{d}]_vg1x4", "vm4.du", "c", MergeNone, "aarch64_sme_sudot_single_za32_vg1x4", [IsStreaming, IsInOutZA], []>; // Multi-multi sudot builtins are mapped to usdot, with zn & zm operands swapped - def SVSUDOT_MULTI_ZA32_VG1x2 : Inst<"svsudot_za32[_{d}]_vg1x2", "vm2.d2.u", "c", MergeNone, "aarch64_sme_usdot_za32_vg1x2", [IsStreaming, IsSharedZA], []>; - def SVSUDOT_MULTI_ZA32_VG1x4 : Inst<"svsudot_za32[_{d}]_vg1x4", "vm4.d4.u", "c", MergeNone, "aarch64_sme_usdot_za32_vg1x4", [IsStreaming, IsSharedZA], []>; + def SVSUDOT_MULTI_ZA32_VG1x2 : Inst<"svsudot_za32[_{d}]_vg1x2", "vm2.d2.u", "c", MergeNone, "aarch64_sme_usdot_za32_vg1x2", [IsStreaming, IsInOutZA], []>; + def SVSUDOT_MULTI_ZA32_VG1x4 : Inst<"svsudot_za32[_{d}]_vg1x4", "vm4.d4.u", "c", MergeNone, "aarch64_sme_usdot_za32_vg1x4", [IsStreaming, IsInOutZA], []>; - def SVSUDOT_LANE_ZA32_VG1x2 : Inst<"svsudot_lane_za32[_{d}]_vg1x2", "vm2.dui", "c", MergeNone, "aarch64_sme_sudot_lane_za32_vg1x2", [IsStreaming, IsSharedZA], [ImmCheck<3, ImmCheck0_3>]>; - def SVSUDOT_LANE_ZA32_VG1x4 : Inst<"svsudot_lane_za32[_{d}]_vg1x4", "vm4.dui", "c", MergeNone, "aarch64_sme_sudot_lane_za32_vg1x4", [IsStreaming, IsSharedZA], [ImmCheck<3, ImmCheck0_3>]>; + def SVSUDOT_LANE_ZA32_VG1x2 : Inst<"svsudot_lane_za32[_{d}]_vg1x2", "vm2.dui", "c", MergeNone, "aarch64_sme_sudot_lane_za32_vg1x2", [IsStreaming, IsInOutZA], [ImmCheck<3, ImmCheck0_3>]>; + def SVSUDOT_LANE_ZA32_VG1x4 : Inst<"svsudot_lane_za32[_{d}]_vg1x4", "vm4.dui", "c", MergeNone, "aarch64_sme_sudot_lane_za32_vg1x4", [IsStreaming, IsInOutZA], [ImmCheck<3, ImmCheck0_3>]>; // Multi-vector half-precision/BFloat16 floating-point dot-product - def SVDOT_MULTI_ZA32_VG1x2_F16 : Inst<"svdot_za32[_{d}]_vg1x2", "vm22", "bh", MergeNone, "aarch64_sme_fdot_za32_vg1x2", [IsStreaming, IsSharedZA], []>; - def SVDOT_MULTI_ZA32_VG1x4_F16 : Inst<"svdot_za32[_{d}]_vg1x4", "vm44", "bh", MergeNone, "aarch64_sme_fdot_za32_vg1x4", [IsStreaming, IsSharedZA], []>; - def SVDOT_SINGLE_ZA32_VG1x2_F16 : Inst<"svdot[_single]_za32[_{d}]_vg1x2", "vm2d", "bh", MergeNone, "aarch64_sme_fdot_single_za32_vg1x2", [IsStreaming, IsSharedZA], []>; - def SVDOT_SINGLE_ZA32_VG1x4_F16 : Inst<"svdot[_single]_za32[_{d}]_vg1x4", "vm4d", "bh", MergeNone, "aarch64_sme_fdot_single_za32_vg1x4", [IsStreaming, IsSharedZA], []>; - def SVDOT_LANE_ZA32_VG1x2_F16 : Inst<"svdot_lane_za32[_{d}]_vg1x2", "vm2di", "bh", MergeNone, "aarch64_sme_fdot_lane_za32_vg1x2", [IsStreaming, IsSharedZA], [ImmCheck<3, ImmCheck0_3>]>; - def SVDOT_LANE_ZA32_VG1x4_F16 : Inst<"svdot_lane_za32[_{d}]_vg1x4", "vm4di", "bh", MergeNone, "aarch64_sme_fdot_lane_za32_vg1x4", [IsStreaming, IsSharedZA], [ImmCheck<3, ImmCheck0_3>]>; + def SVDOT_MULTI_ZA32_VG1x2_F16 : Inst<"svdot_za32[_{d}]_vg1x2", "vm22", "bh", MergeNone, "aarch64_sme_fdot_za32_vg1x2", [IsStreaming, IsInOutZA], []>; + def SVDOT_MULTI_ZA32_VG1x4_F16 : Inst<"svdot_za32[_{d}]_vg1x4", "vm44", "bh", MergeNone, "aarch64_sme_fdot_za32_vg1x4", [IsStreaming, IsInOutZA], []>; + def SVDOT_SINGLE_ZA32_VG1x2_F16 : Inst<"svdot[_single]_za32[_{d}]_vg1x2", "vm2d", "bh", MergeNone, "aarch64_sme_fdot_single_za32_vg1x2", [IsStreaming, IsInOutZA], []>; + def SVDOT_SINGLE_ZA32_VG1x4_F16 : Inst<"svdot[_single]_za32[_{d}]_vg1x4", "vm4d", "bh", MergeNone, "aarch64_sme_fdot_single_za32_vg1x4", [IsStreaming, IsInOutZA], []>; + def SVDOT_LANE_ZA32_VG1x2_F16 : Inst<"svdot_lane_za32[_{d}]_vg1x2", "vm2di", "bh", MergeNone, "aarch64_sme_fdot_lane_za32_vg1x2", [IsStreaming, IsInOutZA], [ImmCheck<3, ImmCheck0_3>]>; + def SVDOT_LANE_ZA32_VG1x4_F16 : Inst<"svdot_lane_za32[_{d}]_vg1x4", "vm4di", "bh", MergeNone, "aarch64_sme_fdot_lane_za32_vg1x4", [IsStreaming, IsInOutZA], [ImmCheck<3, ImmCheck0_3>]>; } let TargetGuard = "sme2,sme-i16i64" in { - def SVVDOT_LANE_ZA64_VG1x4_S : Inst<"svvdot_lane_za64[_{d}]_vg1x4", "vm4di", "s", MergeNone, "aarch64_sme_svdot_lane_za64_vg1x4", [IsStreaming, IsSharedZA], [ImmCheck<3, ImmCheck0_1>]>; - def SVVDOT_LANE_ZA64_VG1x4_U : Inst<"svvdot_lane_za64[_{d}]_vg1x4", "vm4di", "Us", MergeNone, "aarch64_sme_uvdot_lane_za64_vg1x4", [IsStreaming, IsSharedZA], [ImmCheck<3, ImmCheck0_1>]>; + def SVVDOT_LANE_ZA64_VG1x4_S : Inst<"svvdot_lane_za64[_{d}]_vg1x4", "vm4di", "s", MergeNone, "aarch64_sme_svdot_lane_za64_vg1x4", [IsStreaming, IsInOutZA], [ImmCheck<3, ImmCheck0_1>]>; + def SVVDOT_LANE_ZA64_VG1x4_U : Inst<"svvdot_lane_za64[_{d}]_vg1x4", "vm4di", "Us", MergeNone, "aarch64_sme_uvdot_lane_za64_vg1x4", [IsStreaming, IsInOutZA], [ImmCheck<3, ImmCheck0_1>]>; - def SVDOT_MULTI_ZA64_VG1x2_S16 : Inst<"svdot_za64[_{d}]_vg1x2", "vm22", "s", MergeNone, "aarch64_sme_sdot_za64_vg1x2", [IsStreaming, IsSharedZA], []>; - def SVDOT_MULTI_ZA64_VG1x4_S16 : Inst<"svdot_za64[_{d}]_vg1x4", "vm44", "s", MergeNone, "aarch64_sme_sdot_za64_vg1x4", [IsStreaming, IsSharedZA], []>; - def SVDOT_MULTI_ZA64_VG1x2_U16 : Inst<"svdot_za64[_{d}]_vg1x2", "vm22", "Us", MergeNone, "aarch64_sme_udot_za64_vg1x2", [IsStreaming, IsSharedZA], []>; - def SVDOT_MULTI_ZA64_VG1x4_U16 : Inst<"svdot_za64[_{d}]_vg1x4", "vm44", "Us", MergeNone, "aarch64_sme_udot_za64_vg1x4", [IsStreaming, IsSharedZA], []>; - def SVDOT_SINGLE_ZA64_VG1x2_S16 : Inst<"svdot[_single]_za64[_{d}]_vg1x2", "vm2d", "s", MergeNone, "aarch64_sme_sdot_single_za64_vg1x2", [IsStreaming, IsSharedZA], []>; - def SVDOT_SINGLE_ZA64_VG1x4_S16 : Inst<"svdot[_single]_za64[_{d}]_vg1x4", "vm4d", "s", MergeNone, "aarch64_sme_sdot_single_za64_vg1x4", [IsStreaming, IsSharedZA], []>; - def SVDOT_SINGLE_ZA64_VG1x2_U16 : Inst<"svdot[_single]_za64[_{d}]_vg1x2", "vm2d", "Us", MergeNone, "aarch64_sme_udot_single_za64_vg1x2", [IsStreaming, IsSharedZA], []>; - def SVDOT_SINGLE_ZA64_VG1x4_U16 : Inst<"svdot[_single]_za64[_{d}]_vg1x4", "vm4d", "Us", MergeNone, "aarch64_sme_udot_single_za64_vg1x4", [IsStreaming, IsSharedZA], []>; - def SVDOT_LANE_ZA64_VG1x2_S16 : Inst<"svdot_lane_za64[_{d}]_vg1x2", "vm2di", "s", MergeNone, "aarch64_sme_sdot_lane_za64_vg1x2", [IsStreaming, IsSharedZA], [ImmCheck<3, ImmCheck0_1>]>; - def SVDOT_LANE_ZA64_VG1x4_S16 : Inst<"svdot_lane_za64[_{d}]_vg1x4", "vm4di", "s", MergeNone, "aarch64_sme_sdot_lane_za64_vg1x4", [IsStreaming, IsSharedZA], [ImmCheck<3, ImmCheck0_1>]>; - def SVDOT_LANE_ZA64_VG1x2_U16 : Inst<"svdot_lane_za64[_{d}]_vg1x2", "vm2di", "Us", MergeNone, "aarch64_sme_udot_lane_za64_vg1x2", [IsStreaming, IsSharedZA], [ImmCheck<3, ImmCheck0_1>]>; - def SVDOT_LANE_ZA64_VG1x4_U16 : Inst<"svdot_lane_za64[_{d}]_vg1x4", "vm4di", "Us", MergeNone, "aarch64_sme_udot_lane_za64_vg1x4", [IsStreaming, IsSharedZA], [ImmCheck<3, ImmCheck0_1>]>; + def SVDOT_MULTI_ZA64_VG1x2_S16 : Inst<"svdot_za64[_{d}]_vg1x2", "vm22", "s", MergeNone, "aarch64_sme_sdot_za64_vg1x2", [IsStreaming, IsInOutZA], []>; + def SVDOT_MULTI_ZA64_VG1x4_S16 : Inst<"svdot_za64[_{d}]_vg1x4", "vm44", "s", MergeNone, "aarch64_sme_sdot_za64_vg1x4", [IsStreaming, IsInOutZA], []>; + def SVDOT_MULTI_ZA64_VG1x2_U16 : Inst<"svdot_za64[_{d}]_vg1x2", "vm22", "Us", MergeNone, "aarch64_sme_udot_za64_vg1x2", [IsStreaming, IsInOutZA], []>; + def SVDOT_MULTI_ZA64_VG1x4_U16 : Inst<"svdot_za64[_{d}]_vg1x4", "vm44", "Us", MergeNone, "aarch64_sme_udot_za64_vg1x4", [IsStreaming, IsInOutZA], []>; + def SVDOT_SINGLE_ZA64_VG1x2_S16 : Inst<"svdot[_single]_za64[_{d}]_vg1x2", "vm2d", "s", MergeNone, "aarch64_sme_sdot_single_za64_vg1x2", [IsStreaming, IsInOutZA], []>; + def SVDOT_SINGLE_ZA64_VG1x4_S16 : Inst<"svdot[_single]_za64[_{d}]_vg1x4", "vm4d", "s", MergeNone, "aarch64_sme_sdot_single_za64_vg1x4", [IsStreaming, IsInOutZA], []>; + def SVDOT_SINGLE_ZA64_VG1x2_U16 : Inst<"svdot[_single]_za64[_{d}]_vg1x2", "vm2d", "Us", MergeNone, "aarch64_sme_udot_single_za64_vg1x2", [IsStreaming, IsInOutZA], []>; + def SVDOT_SINGLE_ZA64_VG1x4_U16 : Inst<"svdot[_single]_za64[_{d}]_vg1x4", "vm4d", "Us", MergeNone, "aarch64_sme_udot_single_za64_vg1x4", [IsStreaming, IsInOutZA], []>; + def SVDOT_LANE_ZA64_VG1x2_S16 : Inst<"svdot_lane_za64[_{d}]_vg1x2", "vm2di", "s", MergeNone, "aarch64_sme_sdot_lane_za64_vg1x2", [IsStreaming, IsInOutZA], [ImmCheck<3, ImmCheck0_1>]>; + def SVDOT_LANE_ZA64_VG1x4_S16 : Inst<"svdot_lane_za64[_{d}]_vg1x4", "vm4di", "s", MergeNone, "aarch64_sme_sdot_lane_za64_vg1x4", [IsStreaming, IsInOutZA], [ImmCheck<3, ImmCheck0_1>]>; + def SVDOT_LANE_ZA64_VG1x2_U16 : Inst<"svdot_lane_za64[_{d}]_vg1x2", "vm2di", "Us", MergeNone, "aarch64_sme_udot_lane_za64_vg1x2", [IsStreaming, IsInOutZA], [ImmCheck<3, ImmCheck0_1>]>; + def SVDOT_LANE_ZA64_VG1x4_U16 : Inst<"svdot_lane_za64[_{d}]_vg1x4", "vm4di", "Us", MergeNone, "aarch64_sme_udot_lane_za64_vg1x4", [IsStreaming, IsInOutZA], [ImmCheck<3, ImmCheck0_1>]>; } // FMLA/FMLS let TargetGuard = "sme2" in { - def SVMLA_MULTI_VG1x2_F32 : Inst<"svmla_za32[_{d}]_vg1x2", "vm22", "f", MergeNone, "aarch64_sme_fmla_vg1x2", [IsStreaming, IsSharedZA], []>; - def SVMLA_MULTI_VG1x4_F32 : Inst<"svmla_za32[_{d}]_vg1x4", "vm44", "f", MergeNone, "aarch64_sme_fmla_vg1x4", [IsStreaming, IsSharedZA], []>; - def SVMLS_MULTI_VG1x2_F32 : Inst<"svmls_za32[_{d}]_vg1x2", "vm22", "f", MergeNone, "aarch64_sme_fmls_vg1x2", [IsStreaming, IsSharedZA], []>; - def SVMLS_MULTI_VG1x4_F32 : Inst<"svmls_za32[_{d}]_vg1x4", "vm44", "f", MergeNone, "aarch64_sme_fmls_vg1x4", [IsStreaming, IsSharedZA], []>; + def SVMLA_MULTI_VG1x2_F32 : Inst<"svmla_za32[_{d}]_vg1x2", "vm22", "f", MergeNone, "aarch64_sme_fmla_vg1x2", [IsStreaming, IsInOutZA], []>; + def SVMLA_MULTI_VG1x4_F32 : Inst<"svmla_za32[_{d}]_vg1x4", "vm44", "f", MergeNone, "aarch64_sme_fmla_vg1x4", [IsStreaming, IsInOutZA], []>; + def SVMLS_MULTI_VG1x2_F32 : Inst<"svmls_za32[_{d}]_vg1x2", "vm22", "f", MergeNone, "aarch64_sme_fmls_vg1x2", [IsStreaming, IsInOutZA], []>; + def SVMLS_MULTI_VG1x4_F32 : Inst<"svmls_za32[_{d}]_vg1x4", "vm44", "f", MergeNone, "aarch64_sme_fmls_vg1x4", [IsStreaming, IsInOutZA], []>; - def SVMLA_SINGLE_VG1x2_F32 : Inst<"svmla[_single]_za32[_{d}]_vg1x2", "vm2d", "f", MergeNone, "aarch64_sme_fmla_single_vg1x2", [IsStreaming, IsSharedZA], []>; - def SVMLA_SINGLE_VG1x4_F32 : Inst<"svmla[_single]_za32[_{d}]_vg1x4", "vm4d", "f", MergeNone, "aarch64_sme_fmla_single_vg1x4", [IsStreaming, IsSharedZA], []>; - def SVMLS_SINGLE_VG1x2_F32 : Inst<"svmls[_single]_za32[_{d}]_vg1x2", "vm2d", "f", MergeNone, "aarch64_sme_fmls_single_vg1x2", [IsStreaming, IsSharedZA], []>; - def SVMLS_SINGLE_VG1x4_F32 : Inst<"svmls[_single]_za32[_{d}]_vg1x4", "vm4d", "f", MergeNone, "aarch64_sme_fmls_single_vg1x4", [IsStreaming, IsSharedZA], []>; + def SVMLA_SINGLE_VG1x2_F32 : Inst<"svmla[_single]_za32[_{d}]_vg1x2", "vm2d", "f", MergeNone, "aarch64_sme_fmla_single_vg1x2", [IsStreaming, IsInOutZA], []>; + def SVMLA_SINGLE_VG1x4_F32 : Inst<"svmla[_single]_za32[_{d}]_vg1x4", "vm4d", "f", MergeNone, "aarch64_sme_fmla_single_vg1x4", [IsStreaming, IsInOutZA], []>; + def SVMLS_SINGLE_VG1x2_F32 : Inst<"svmls[_single]_za32[_{d}]_vg1x2", "vm2d", "f", MergeNone, "aarch64_sme_fmls_single_vg1x2", [IsStreaming, IsInOutZA], []>; + def SVMLS_SINGLE_VG1x4_F32 : Inst<"svmls[_single]_za32[_{d}]_vg1x4", "vm4d", "f", MergeNone, "aarch64_sme_fmls_single_vg1x4", [IsStreaming, IsInOutZA], []>; - def SVMLA_LANE_VG1x2_F32 : Inst<"svmla_lane_za32[_{d}]_vg1x2", "vm2di", "f", MergeNone, "aarch64_sme_fmla_lane_vg1x2", [IsStreaming, IsSharedZA], [ImmCheck<3, ImmCheck0_3>]>; - def SVMLA_LANE_VG1x4_F32 : Inst<"svmla_lane_za32[_{d}]_vg1x4", "vm4di", "f", MergeNone, "aarch64_sme_fmla_lane_vg1x4", [IsStreaming, IsSharedZA], [ImmCheck<3, ImmCheck0_3>]>; - def SVMLS_LANE_VG1x2_F32 : Inst<"svmls_lane_za32[_{d}]_vg1x2", "vm2di", "f", MergeNone, "aarch64_sme_fmls_lane_vg1x2", [IsStreaming, IsSharedZA], [ImmCheck<3, ImmCheck0_3>]>; - def SVMLS_LANE_VG1x4_F32 : Inst<"svmls_lane_za32[_{d}]_vg1x4", "vm4di", "f", MergeNone, "aarch64_sme_fmls_lane_vg1x4", [IsStreaming, IsSharedZA], [ImmCheck<3, ImmCheck0_3>]>; + def SVMLA_LANE_VG1x2_F32 : Inst<"svmla_lane_za32[_{d}]_vg1x2", "vm2di", "f", MergeNone, "aarch64_sme_fmla_lane_vg1x2", [IsStreaming, IsInOutZA], [ImmCheck<3, ImmCheck0_3>]>; + def SVMLA_LANE_VG1x4_F32 : Inst<"svmla_lane_za32[_{d}]_vg1x4", "vm4di", "f", MergeNone, "aarch64_sme_fmla_lane_vg1x4", [IsStreaming, IsInOutZA], [ImmCheck<3, ImmCheck0_3>]>; + def SVMLS_LANE_VG1x2_F32 : Inst<"svmls_lane_za32[_{d}]_vg1x2", "vm2di", "f", MergeNone, "aarch64_sme_fmls_lane_vg1x2", [IsStreaming, IsInOutZA], [ImmCheck<3, ImmCheck0_3>]>; + def SVMLS_LANE_VG1x4_F32 : Inst<"svmls_lane_za32[_{d}]_vg1x4", "vm4di", "f", MergeNone, "aarch64_sme_fmls_lane_vg1x4", [IsStreaming, IsInOutZA], [ImmCheck<3, ImmCheck0_3>]>; } let TargetGuard = "sme2,sme-f64f64" in { - def SVMLA_MULTI_VG1x2_F64 : Inst<"svmla_za64[_{d}]_vg1x2", "vm22", "d", MergeNone, "aarch64_sme_fmla_vg1x2", [IsStreaming, IsSharedZA], []>; - def SVMLA_MULTI_VG1x4_F64 : Inst<"svmla_za64[_{d}]_vg1x4", "vm44", "d", MergeNone, "aarch64_sme_fmla_vg1x4", [IsStreaming, IsSharedZA], []>; - def SVMLS_MULTI_VG1x2_F64 : Inst<"svmls_za64[_{d}]_vg1x2", "vm22", "d", MergeNone, "aarch64_sme_fmls_vg1x2", [IsStreaming, IsSharedZA], []>; - def SVMLS_MULTI_VG1x4_F64 : Inst<"svmls_za64[_{d}]_vg1x4", "vm44", "d", MergeNone, "aarch64_sme_fmls_vg1x4", [IsStreaming, IsSharedZA], []>; + def SVMLA_MULTI_VG1x2_F64 : Inst<"svmla_za64[_{d}]_vg1x2", "vm22", "d", MergeNone, "aarch64_sme_fmla_vg1x2", [IsStreaming, IsInOutZA], []>; + def SVMLA_MULTI_VG1x4_F64 : Inst<"svmla_za64[_{d}]_vg1x4", "vm44", "d", MergeNone, "aarch64_sme_fmla_vg1x4", [IsStreaming, IsInOutZA], []>; + def SVMLS_MULTI_VG1x2_F64 : Inst<"svmls_za64[_{d}]_vg1x2", "vm22", "d", MergeNone, "aarch64_sme_fmls_vg1x2", [IsStreaming, IsInOutZA], []>; + def SVMLS_MULTI_VG1x4_F64 : Inst<"svmls_za64[_{d}]_vg1x4", "vm44", "d", MergeNone, "aarch64_sme_fmls_vg1x4", [IsStreaming, IsInOutZA], []>; - def SVMLA_SINGLE_VG1x2_F64 : Inst<"svmla[_single]_za64[_{d}]_vg1x2", "vm2d", "d", MergeNone, "aarch64_sme_fmla_single_vg1x2", [IsStreaming, IsSharedZA], []>; - def SVMLA_SINGLE_VG1x4_F64 : Inst<"svmla[_single]_za64[_{d}]_vg1x4", "vm4d", "d", MergeNone, "aarch64_sme_fmla_single_vg1x4", [IsStreaming, IsSharedZA], []>; - def SVMLS_SINGLE_VG1x2_F64 : Inst<"svmls[_single]_za64[_{d}]_vg1x2", "vm2d", "d", MergeNone, "aarch64_sme_fmls_single_vg1x2", [IsStreaming, IsSharedZA], []>; - def SVMLS_SINGLE_VG1x4_F64 : Inst<"svmls[_single]_za64[_{d}]_vg1x4", "vm4d", "d", MergeNone, "aarch64_sme_fmls_single_vg1x4", [IsStreaming, IsSharedZA], []>; + def SVMLA_SINGLE_VG1x2_F64 : Inst<"svmla[_single]_za64[_{d}]_vg1x2", "vm2d", "d", MergeNone, "aarch64_sme_fmla_single_vg1x2", [IsStreaming, IsInOutZA], []>; + def SVMLA_SINGLE_VG1x4_F64 : Inst<"svmla[_single]_za64[_{d}]_vg1x4", "vm4d", "d", MergeNone, "aarch64_sme_fmla_single_vg1x4", [IsStreaming, IsInOutZA], []>; + def SVMLS_SINGLE_VG1x2_F64 : Inst<"svmls[_single]_za64[_{d}]_vg1x2", "vm2d", "d", MergeNone, "aarch64_sme_fmls_single_vg1x2", [IsStreaming, IsInOutZA], []>; + def SVMLS_SINGLE_VG1x4_F64 : Inst<"svmls[_single]_za64[_{d}]_vg1x4", "vm4d", "d", MergeNone, "aarch64_sme_fmls_single_vg1x4", [IsStreaming, IsInOutZA], []>; - def SVMLA_LANE_VG1x2_F64 : Inst<"svmla_lane_za64[_{d}]_vg1x2", "vm2di", "d", MergeNone, "aarch64_sme_fmla_lane_vg1x2", [IsStreaming, IsSharedZA], [ImmCheck<3, ImmCheck0_1>]>; - def SVMLA_LANE_VG1x4_F64 : Inst<"svmla_lane_za64[_{d}]_vg1x4", "vm4di", "d", MergeNone, "aarch64_sme_fmla_lane_vg1x4", [IsStreaming, IsSharedZA], [ImmCheck<3, ImmCheck0_1>]>; - def SVMLS_LANE_VG1x2_F64 : Inst<"svmls_lane_za64[_{d}]_vg1x2", "vm2di", "d", MergeNone, "aarch64_sme_fmls_lane_vg1x2", [IsStreaming, IsSharedZA], [ImmCheck<3, ImmCheck0_1>]>; - def SVMLS_LANE_VG1x4_F64 : Inst<"svmls_lane_za64[_{d}]_vg1x4", "vm4di", "d", MergeNone, "aarch64_sme_fmls_lane_vg1x4", [IsStreaming, IsSharedZA], [ImmCheck<3, ImmCheck0_1>]>; + def SVMLA_LANE_VG1x2_F64 : Inst<"svmla_lane_za64[_{d}]_vg1x2", "vm2di", "d", MergeNone, "aarch64_sme_fmla_lane_vg1x2", [IsStreaming, IsInOutZA], [ImmCheck<3, ImmCheck0_1>]>; + def SVMLA_LANE_VG1x4_F64 : Inst<"svmla_lane_za64[_{d}]_vg1x4", "vm4di", "d", MergeNone, "aarch64_sme_fmla_lane_vg1x4", [IsStreaming, IsInOutZA], [ImmCheck<3, ImmCheck0_1>]>; + def SVMLS_LANE_VG1x2_F64 : Inst<"svmls_lane_za64[_{d}]_vg1x2", "vm2di", "d", MergeNone, "aarch64_sme_fmls_lane_vg1x2", [IsStreaming, IsInOutZA], [ImmCheck<3, ImmCheck0_1>]>; + def SVMLS_LANE_VG1x4_F64 : Inst<"svmls_lane_za64[_{d}]_vg1x4", "vm4di", "d", MergeNone, "aarch64_sme_fmls_lane_vg1x4", [IsStreaming, IsInOutZA], [ImmCheck<3, ImmCheck0_1>]>; } // FMLAL/FMLSL/UMLAL/SMLAL // SMLALL/UMLALL/USMLALL/SUMLALL let TargetGuard = "sme2" in { // MULTI MLAL - def SVMLAL_MULTI_VG2x2_F16 : Inst<"svmla_za32[_{d}]_vg2x2", "vm22", "bh", MergeNone, "aarch64_sme_fmlal_vg2x2", [IsStreaming, IsSharedZA], []>; - def SVMLAL_MULTI_VG2x4_F16 : Inst<"svmla_za32[_{d}]_vg2x4", "vm44", "bh", MergeNone, "aarch64_sme_fmlal_vg2x4", [IsStreaming, IsSharedZA], []>; - def SVMLAL_MULTI_VG2x2_S16 : Inst<"svmla_za32[_{d}]_vg2x2", "vm22", "s", MergeNone, "aarch64_sme_smlal_vg2x2", [IsStreaming, IsSharedZA], []>; - def SVMLAL_MULTI_VG2x4_S16 : Inst<"svmla_za32[_{d}]_vg2x4", "vm44", "s", MergeNone, "aarch64_sme_smlal_vg2x4", [IsStreaming, IsSharedZA], []>; - def SVMLAL_MULTI_VG2x2_U16 : Inst<"svmla_za32[_{d}]_vg2x2", "vm22", "Us", MergeNone, "aarch64_sme_umlal_vg2x2", [IsStreaming, IsSharedZA], []>; - def SVMLAL_MULTI_VG2x4_U16 : Inst<"svmla_za32[_{d}]_vg2x4", "vm44", "Us", MergeNone, "aarch64_sme_umlal_vg2x4", [IsStreaming, IsSharedZA], []>; + def SVMLAL_MULTI_VG2x2_F16 : Inst<"svmla_za32[_{d}]_vg2x2", "vm22", "bh", MergeNone, "aarch64_sme_fmlal_vg2x2", [IsStreaming, IsInOutZA], []>; + def SVMLAL_MULTI_VG2x4_F16 : Inst<"svmla_za32[_{d}]_vg2x4", "vm44", "bh", MergeNone, "aarch64_sme_fmlal_vg2x4", [IsStreaming, IsInOutZA], []>; + def SVMLAL_MULTI_VG2x2_S16 : Inst<"svmla_za32[_{d}]_vg2x2", "vm22", "s", MergeNone, "aarch64_sme_smlal_vg2x2", [IsStreaming, IsInOutZA], []>; + def SVMLAL_MULTI_VG2x4_S16 : Inst<"svmla_za32[_{d}]_vg2x4", "vm44", "s", MergeNone, "aarch64_sme_smlal_vg2x4", [IsStreaming, IsInOutZA], []>; + def SVMLAL_MULTI_VG2x2_U16 : Inst<"svmla_za32[_{d}]_vg2x2", "vm22", "Us", MergeNone, "aarch64_sme_umlal_vg2x2", [IsStreaming, IsInOutZA], []>; + def SVMLAL_MULTI_VG2x4_U16 : Inst<"svmla_za32[_{d}]_vg2x4", "vm44", "Us", MergeNone, "aarch64_sme_umlal_vg2x4", [IsStreaming, IsInOutZA], []>; - def SVMLAL_MULTI_VG4x2_S8 : Inst<"svmla_za32[_{d}]_vg4x2", "vm22", "c", MergeNone, "aarch64_sme_smla_za32_vg4x2", [IsStreaming, IsSharedZA], []>; - def SVMLAL_MULTI_VG4x2_U8 : Inst<"svmla_za32[_{d}]_vg4x2", "vm22", "Uc", MergeNone, "aarch64_sme_umla_za32_vg4x2", [IsStreaming, IsSharedZA], []>; - def SVMLAL_MULTI_VG4x4_S8 : Inst<"svmla_za32[_{d}]_vg4x4", "vm44", "c", MergeNone, "aarch64_sme_smla_za32_vg4x4", [IsStreaming, IsSharedZA], []>; - def SVMLAL_MULTI_VG4x4_U8 : Inst<"svmla_za32[_{d}]_vg4x4", "vm44", "Uc", MergeNone, "aarch64_sme_umla_za32_vg4x4", [IsStreaming, IsSharedZA], []>; + def SVMLAL_MULTI_VG4x2_S8 : Inst<"svmla_za32[_{d}]_vg4x2", "vm22", "c", MergeNone, "aarch64_sme_smla_za32_vg4x2", [IsStreaming, IsInOutZA], []>; + def SVMLAL_MULTI_VG4x2_U8 : Inst<"svmla_za32[_{d}]_vg4x2", "vm22", "Uc", MergeNone, "aarch64_sme_umla_za32_vg4x2", [IsStreaming, IsInOutZA], []>; + def SVMLAL_MULTI_VG4x4_S8 : Inst<"svmla_za32[_{d}]_vg4x4", "vm44", "c", MergeNone, "aarch64_sme_smla_za32_vg4x4", [IsStreaming, IsInOutZA], []>; + def SVMLAL_MULTI_VG4x4_U8 : Inst<"svmla_za32[_{d}]_vg4x4", "vm44", "Uc", MergeNone, "aarch64_sme_umla_za32_vg4x4", [IsStreaming, IsInOutZA], []>; // MULTI MLSL - def SVMLSL_MULTI_VG2x2_F16 : Inst<"svmls_za32[_{d}]_vg2x2", "vm22", "bh", MergeNone, "aarch64_sme_fmlsl_vg2x2", [IsStreaming, IsSharedZA], []>; - def SVMLSL_MULTI_VG2x4_F16 : Inst<"svmls_za32[_{d}]_vg2x4", "vm44", "bh", MergeNone, "aarch64_sme_fmlsl_vg2x4", [IsStreaming, IsSharedZA], []>; - def SVMLSL_MULTI_VG2x2_S16 : Inst<"svmls_za32[_{d}]_vg2x2", "vm22", "s", MergeNone, "aarch64_sme_smlsl_vg2x2", [IsStreaming, IsSharedZA], []>; - def SVMLSL_MULTI_VG2x4_S16 : Inst<"svmls_za32[_{d}]_vg2x4", "vm44", "s", MergeNone, "aarch64_sme_smlsl_vg2x4", [IsStreaming, IsSharedZA], []>; - def SVMLSL_MULTI_VG2x2_U16 : Inst<"svmls_za32[_{d}]_vg2x2", "vm22", "Us", MergeNone, "aarch64_sme_umlsl_vg2x2", [IsStreaming, IsSharedZA], []>; - def SVMLSL_MULTI_VG2x4_U16 : Inst<"svmls_za32[_{d}]_vg2x4", "vm44", "Us", MergeNone, "aarch64_sme_umlsl_vg2x4", [IsStreaming, IsSharedZA], []>; + def SVMLSL_MULTI_VG2x2_F16 : Inst<"svmls_za32[_{d}]_vg2x2", "vm22", "bh", MergeNone, "aarch64_sme_fmlsl_vg2x2", [IsStreaming, IsInOutZA], []>; + def SVMLSL_MULTI_VG2x4_F16 : Inst<"svmls_za32[_{d}]_vg2x4", "vm44", "bh", MergeNone, "aarch64_sme_fmlsl_vg2x4", [IsStreaming, IsInOutZA], []>; + def SVMLSL_MULTI_VG2x2_S16 : Inst<"svmls_za32[_{d}]_vg2x2", "vm22", "s", MergeNone, "aarch64_sme_smlsl_vg2x2", [IsStreaming, IsInOutZA], []>; + def SVMLSL_MULTI_VG2x4_S16 : Inst<"svmls_za32[_{d}]_vg2x4", "vm44", "s", MergeNone, "aarch64_sme_smlsl_vg2x4", [IsStreaming, IsInOutZA], []>; + def SVMLSL_MULTI_VG2x2_U16 : Inst<"svmls_za32[_{d}]_vg2x2", "vm22", "Us", MergeNone, "aarch64_sme_umlsl_vg2x2", [IsStreaming, IsInOutZA], []>; + def SVMLSL_MULTI_VG2x4_U16 : Inst<"svmls_za32[_{d}]_vg2x4", "vm44", "Us", MergeNone, "aarch64_sme_umlsl_vg2x4", [IsStreaming, IsInOutZA], []>; - def SVMLSL_MULTI_VG4x2_S8 : Inst<"svmls_za32[_{d}]_vg4x2", "vm22", "c", MergeNone, "aarch64_sme_smls_za32_vg4x2", [IsStreaming, IsSharedZA], []>; - def SVMLSL_MULTI_VG4x2_U8 : Inst<"svmls_za32[_{d}]_vg4x2", "vm22", "Uc", MergeNone, "aarch64_sme_umls_za32_vg4x2", [IsStreaming, IsSharedZA], []>; - def SVMLSL_MULTI_VG4x4_S8 : Inst<"svmls_za32[_{d}]_vg4x4", "vm44", "c", MergeNone, "aarch64_sme_smls_za32_vg4x4", [IsStreaming, IsSharedZA], []>; - def SVMLSL_MULTI_VG4x4_U8 : Inst<"svmls_za32[_{d}]_vg4x4", "vm44", "Uc", MergeNone, "aarch64_sme_umls_za32_vg4x4", [IsStreaming, IsSharedZA], []>; + def SVMLSL_MULTI_VG4x2_S8 : Inst<"svmls_za32[_{d}]_vg4x2", "vm22", "c", MergeNone, "aarch64_sme_smls_za32_vg4x2", [IsStreaming, IsInOutZA], []>; + def SVMLSL_MULTI_VG4x2_U8 : Inst<"svmls_za32[_{d}]_vg4x2", "vm22", "Uc", MergeNone, "aarch64_sme_umls_za32_vg4x2", [IsStreaming, IsInOutZA], []>; + def SVMLSL_MULTI_VG4x4_S8 : Inst<"svmls_za32[_{d}]_vg4x4", "vm44", "c", MergeNone, "aarch64_sme_smls_za32_vg4x4", [IsStreaming, IsInOutZA], []>; + def SVMLSL_MULTI_VG4x4_U8 : Inst<"svmls_za32[_{d}]_vg4x4", "vm44", "Uc", MergeNone, "aarch64_sme_umls_za32_vg4x4", [IsStreaming, IsInOutZA], []>; // SINGLE MLAL - def SVMLAL_SINGLE_VG2x1_F16 : Inst<"svmla_za32[_{d}]_vg2x1", "vmdd", "bh", MergeNone, "aarch64_sme_fmlal_single_vg2x1", [IsStreaming, IsSharedZA], []>; - def SVMLAL_SINGLE_VG2x2_F16 : Inst<"svmla[_single]_za32[_{d}]_vg2x2", "vm2d", "bh", MergeNone, "aarch64_sme_fmlal_single_vg2x2", [IsStreaming, IsSharedZA], []>; - def SVMLAL_SINGLE_VG2x4_F16 : Inst<"svmla[_single]_za32[_{d}]_vg2x4", "vm4d", "bh", MergeNone, "aarch64_sme_fmlal_single_vg2x4", [IsStreaming, IsSharedZA], []>; - def SVMLAL_SINGLE_VG2x1_S16 : Inst<"svmla_za32[_{d}]_vg2x1", "vmdd", "s", MergeNone, "aarch64_sme_smlal_single_vg2x1", [IsStreaming, IsSharedZA], []>; - def SVMLAL_SINGLE_VG2x2_S16 : Inst<"svmla[_single]_za32[_{d}]_vg2x2", "vm2d", "s", MergeNone, "aarch64_sme_smlal_single_vg2x2", [IsStreaming, IsSharedZA], []>; - def SVMLAL_SINGLE_VG2x4_S16 : Inst<"svmla[_single]_za32[_{d}]_vg2x4", "vm4d", "s", MergeNone, "aarch64_sme_smlal_single_vg2x4", [IsStreaming, IsSharedZA], []>; - def SVMLAL_SINGLE_VG2x1_U16 : Inst<"svmla_za32[_{d}]_vg2x1", "vmdd", "Us", MergeNone, "aarch64_sme_umlal_single_vg2x1", [IsStreaming, IsSharedZA], []>; - def SVMLAL_SINGLE_VG2x2_U16 : Inst<"svmla[_single]_za32[_{d}]_vg2x2", "vm2d", "Us", MergeNone, "aarch64_sme_umlal_single_vg2x2", [IsStreaming, IsSharedZA], []>; - def SVMLAL_SINGLE_VG2x4_U16 : Inst<"svmla[_single]_za32[_{d}]_vg2x4", "vm4d", "Us", MergeNone, "aarch64_sme_umlal_single_vg2x4", [IsStreaming, IsSharedZA], []>; + def SVMLAL_SINGLE_VG2x1_F16 : Inst<"svmla_za32[_{d}]_vg2x1", "vmdd", "bh", MergeNone, "aarch64_sme_fmlal_single_vg2x1", [IsStreaming, IsInOutZA], []>; + def SVMLAL_SINGLE_VG2x2_F16 : Inst<"svmla[_single]_za32[_{d}]_vg2x2", "vm2d", "bh", MergeNone, "aarch64_sme_fmlal_single_vg2x2", [IsStreaming, IsInOutZA], []>; + def SVMLAL_SINGLE_VG2x4_F16 : Inst<"svmla[_single]_za32[_{d}]_vg2x4", "vm4d", "bh", MergeNone, "aarch64_sme_fmlal_single_vg2x4", [IsStreaming, IsInOutZA], []>; + def SVMLAL_SINGLE_VG2x1_S16 : Inst<"svmla_za32[_{d}]_vg2x1", "vmdd", "s", MergeNone, "aarch64_sme_smlal_single_vg2x1", [IsStreaming, IsInOutZA], []>; + def SVMLAL_SINGLE_VG2x2_S16 : Inst<"svmla[_single]_za32[_{d}]_vg2x2", "vm2d", "s", MergeNone, "aarch64_sme_smlal_single_vg2x2", [IsStreaming, IsInOutZA], []>; + def SVMLAL_SINGLE_VG2x4_S16 : Inst<"svmla[_single]_za32[_{d}]_vg2x4", "vm4d", "s", MergeNone, "aarch64_sme_smlal_single_vg2x4", [IsStreaming, IsInOutZA], []>; + def SVMLAL_SINGLE_VG2x1_U16 : Inst<"svmla_za32[_{d}]_vg2x1", "vmdd", "Us", MergeNone, "aarch64_sme_umlal_single_vg2x1", [IsStreaming, IsInOutZA], []>; + def SVMLAL_SINGLE_VG2x2_U16 : Inst<"svmla[_single]_za32[_{d}]_vg2x2", "vm2d", "Us", MergeNone, "aarch64_sme_umlal_single_vg2x2", [IsStreaming, IsInOutZA], []>; + def SVMLAL_SINGLE_VG2x4_U16 : Inst<"svmla[_single]_za32[_{d}]_vg2x4", "vm4d", "Us", MergeNone, "aarch64_sme_umlal_single_vg2x4", [IsStreaming, IsInOutZA], []>; - def SVMLAL_SINGLE_VG4x1_S8 : Inst<"svmla_za32[_{d}]_vg4x1", "vmdd", "c", MergeNone, "aarch64_sme_smla_za32_single_vg4x1", [IsStreaming, IsSharedZA], []>; - def SVMLAL_SINGLE_VG4x1_U8 : Inst<"svmla_za32[_{d}]_vg4x1", "vmdd", "Uc", MergeNone, "aarch64_sme_umla_za32_single_vg4x1", [IsStreaming, IsSharedZA], []>; - def SVMLAL_SINGLE_VG4x2_S8 : Inst<"svmla[_single]_za32[_{d}]_vg4x2", "vm2d", "c", MergeNone, "aarch64_sme_smla_za32_single_vg4x2", [IsStreaming, IsSharedZA], []>; - def SVMLAL_SINGLE_VG4x2_U8 : Inst<"svmla[_single]_za32[_{d}]_vg4x2", "vm2d", "Uc", MergeNone, "aarch64_sme_umla_za32_single_vg4x2", [IsStreaming, IsSharedZA], []>; - def SVMLAL_SINGLE_VG4x4_S8 : Inst<"svmla[_single]_za32[_{d}]_vg4x4", "vm4d", "c", MergeNone, "aarch64_sme_smla_za32_single_vg4x4", [IsStreaming, IsSharedZA], []>; - def SVMLAL_SINGLE_VG4x4_U8 : Inst<"svmla[_single]_za32[_{d}]_vg4x4", "vm4d", "Uc", MergeNone, "aarch64_sme_umla_za32_single_vg4x4", [IsStreaming, IsSharedZA], []>; + def SVMLAL_SINGLE_VG4x1_S8 : Inst<"svmla_za32[_{d}]_vg4x1", "vmdd", "c", MergeNone, "aarch64_sme_smla_za32_single_vg4x1", [IsStreaming, IsInOutZA], []>; + def SVMLAL_SINGLE_VG4x1_U8 : Inst<"svmla_za32[_{d}]_vg4x1", "vmdd", "Uc", MergeNone, "aarch64_sme_umla_za32_single_vg4x1", [IsStreaming, IsInOutZA], []>; + def SVMLAL_SINGLE_VG4x2_S8 : Inst<"svmla[_single]_za32[_{d}]_vg4x2", "vm2d", "c", MergeNone, "aarch64_sme_smla_za32_single_vg4x2", [IsStreaming, IsInOutZA], []>; + def SVMLAL_SINGLE_VG4x2_U8 : Inst<"svmla[_single]_za32[_{d}]_vg4x2", "vm2d", "Uc", MergeNone, "aarch64_sme_umla_za32_single_vg4x2", [IsStreaming, IsInOutZA], []>; + def SVMLAL_SINGLE_VG4x4_S8 : Inst<"svmla[_single]_za32[_{d}]_vg4x4", "vm4d", "c", MergeNone, "aarch64_sme_smla_za32_single_vg4x4", [IsStreaming, IsInOutZA], []>; + def SVMLAL_SINGLE_VG4x4_U8 : Inst<"svmla[_single]_za32[_{d}]_vg4x4", "vm4d", "Uc", MergeNone, "aarch64_sme_umla_za32_single_vg4x4", [IsStreaming, IsInOutZA], []>; // SINGLE MLSL - def SVMLSL_SINGLE_VG2x1_F16 : Inst<"svmls_za32[_{d}]_vg2x1", "vmdd", "bh", MergeNone, "aarch64_sme_fmlsl_single_vg2x1", [IsStreaming, IsSharedZA], []>; - def SVMLSL_SINGLE_VG2x2_F16 : Inst<"svmls[_single]_za32[_{d}]_vg2x2", "vm2d", "bh", MergeNone, "aarch64_sme_fmlsl_single_vg2x2", [IsStreaming, IsSharedZA], []>; - def SVMLSL_SINGLE_VG2x4_F16 : Inst<"svmls[_single]_za32[_{d}]_vg2x4", "vm4d", "bh", MergeNone, "aarch64_sme_fmlsl_single_vg2x4", [IsStreaming, IsSharedZA], []>; - def SVMLSL_SINGLE_VG2x1_S16 : Inst<"svmls_za32[_{d}]_vg2x1", "vmdd", "s", MergeNone, "aarch64_sme_smlsl_single_vg2x1", [IsStreaming, IsSharedZA], []>; - def SVMLSL_SINGLE_VG2x2_S16 : Inst<"svmls[_single]_za32[_{d}]_vg2x2", "vm2d", "s", MergeNone, "aarch64_sme_smlsl_single_vg2x2", [IsStreaming, IsSharedZA], []>; - def SVMLSL_SINGLE_VG2x4_S16 : Inst<"svmls[_single]_za32[_{d}]_vg2x4", "vm4d", "s", MergeNone, "aarch64_sme_smlsl_single_vg2x4", [IsStreaming, IsSharedZA], []>; - def SVMLSL_SINGLE_VG2x1_U16 : Inst<"svmls_za32[_{d}]_vg2x1", "vmdd", "Us", MergeNone, "aarch64_sme_umlsl_single_vg2x1", [IsStreaming, IsSharedZA], []>; - def SVMLSL_SINGLE_VG2x2_U16 : Inst<"svmls[_single]_za32[_{d}]_vg2x2", "vm2d", "Us", MergeNone, "aarch64_sme_umlsl_single_vg2x2", [IsStreaming, IsSharedZA], []>; - def SVMLSL_SINGLE_VG2x4_U16 : Inst<"svmls[_single]_za32[_{d}]_vg2x4", "vm4d", "Us", MergeNone, "aarch64_sme_umlsl_single_vg2x4", [IsStreaming, IsSharedZA], []>; + def SVMLSL_SINGLE_VG2x1_F16 : Inst<"svmls_za32[_{d}]_vg2x1", "vmdd", "bh", MergeNone, "aarch64_sme_fmlsl_single_vg2x1", [IsStreaming, IsInOutZA], []>; + def SVMLSL_SINGLE_VG2x2_F16 : Inst<"svmls[_single]_za32[_{d}]_vg2x2", "vm2d", "bh", MergeNone, "aarch64_sme_fmlsl_single_vg2x2", [IsStreaming, IsInOutZA], []>; + def SVMLSL_SINGLE_VG2x4_F16 : Inst<"svmls[_single]_za32[_{d}]_vg2x4", "vm4d", "bh", MergeNone, "aarch64_sme_fmlsl_single_vg2x4", [IsStreaming, IsInOutZA], []>; + def SVMLSL_SINGLE_VG2x1_S16 : Inst<"svmls_za32[_{d}]_vg2x1", "vmdd", "s", MergeNone, "aarch64_sme_smlsl_single_vg2x1", [IsStreaming, IsInOutZA], []>; + def SVMLSL_SINGLE_VG2x2_S16 : Inst<"svmls[_single]_za32[_{d}]_vg2x2", "vm2d", "s", MergeNone, "aarch64_sme_smlsl_single_vg2x2", [IsStreaming, IsInOutZA], []>; + def SVMLSL_SINGLE_VG2x4_S16 : Inst<"svmls[_single]_za32[_{d}]_vg2x4", "vm4d", "s", MergeNone, "aarch64_sme_smlsl_single_vg2x4", [IsStreaming, IsInOutZA], []>; + def SVMLSL_SINGLE_VG2x1_U16 : Inst<"svmls_za32[_{d}]_vg2x1", "vmdd", "Us", MergeNone, "aarch64_sme_umlsl_single_vg2x1", [IsStreaming, IsInOutZA], []>; + def SVMLSL_SINGLE_VG2x2_U16 : Inst<"svmls[_single]_za32[_{d}]_vg2x2", "vm2d", "Us", MergeNone, "aarch64_sme_umlsl_single_vg2x2", [IsStreaming, IsInOutZA], []>; + def SVMLSL_SINGLE_VG2x4_U16 : Inst<"svmls[_single]_za32[_{d}]_vg2x4", "vm4d", "Us", MergeNone, "aarch64_sme_umlsl_single_vg2x4", [IsStreaming, IsInOutZA], []>; - def SVMLSL_SINGLE_VG4x1_S8 : Inst<"svmls_za32[_{d}]_vg4x1", "vmdd", "c", MergeNone, "aarch64_sme_smls_za32_single_vg4x1", [IsStreaming, IsSharedZA], []>; - def SVMLSL_SINGLE_VG4x1_U8 : Inst<"svmls_za32[_{d}]_vg4x1", "vmdd", "Uc", MergeNone, "aarch64_sme_umls_za32_single_vg4x1", [IsStreaming, IsSharedZA], []>; - def SVMLSL_SINGLE_VG4x2_S8 : Inst<"svmls[_single]_za32[_{d}]_vg4x2", "vm2d", "c", MergeNone, "aarch64_sme_smls_za32_single_vg4x2", [IsStreaming, IsSharedZA], []>; - def SVMLSL_SINGLE_VG4x2_U8 : Inst<"svmls[_single]_za32[_{d}]_vg4x2", "vm2d", "Uc", MergeNone, "aarch64_sme_umls_za32_single_vg4x2", [IsStreaming, IsSharedZA], []>; - def SVMLSL_SINGLE_VG4x4_S8 : Inst<"svmls[_single]_za32[_{d}]_vg4x4", "vm4d", "c", MergeNone, "aarch64_sme_smls_za32_single_vg4x4", [IsStreaming, IsSharedZA], []>; - def SVMLSL_SINGLE_VG4x4_U8 : Inst<"svmls[_single]_za32[_{d}]_vg4x4", "vm4d", "Uc", MergeNone, "aarch64_sme_umls_za32_single_vg4x4", [IsStreaming, IsSharedZA], []>; + def SVMLSL_SINGLE_VG4x1_S8 : Inst<"svmls_za32[_{d}]_vg4x1", "vmdd", "c", MergeNone, "aarch64_sme_smls_za32_single_vg4x1", [IsStreaming, IsInOutZA], []>; + def SVMLSL_SINGLE_VG4x1_U8 : Inst<"svmls_za32[_{d}]_vg4x1", "vmdd", "Uc", MergeNone, "aarch64_sme_umls_za32_single_vg4x1", [IsStreaming, IsInOutZA], []>; + def SVMLSL_SINGLE_VG4x2_S8 : Inst<"svmls[_single]_za32[_{d}]_vg4x2", "vm2d", "c", MergeNone, "aarch64_sme_smls_za32_single_vg4x2", [IsStreaming, IsInOutZA], []>; + def SVMLSL_SINGLE_VG4x2_U8 : Inst<"svmls[_single]_za32[_{d}]_vg4x2", "vm2d", "Uc", MergeNone, "aarch64_sme_umls_za32_single_vg4x2", [IsStreaming, IsInOutZA], []>; + def SVMLSL_SINGLE_VG4x4_S8 : Inst<"svmls[_single]_za32[_{d}]_vg4x4", "vm4d", "c", MergeNone, "aarch64_sme_smls_za32_single_vg4x4", [IsStreaming, IsInOutZA], []>; + def SVMLSL_SINGLE_VG4x4_U8 : Inst<"svmls[_single]_za32[_{d}]_vg4x4", "vm4d", "Uc", MergeNone, "aarch64_sme_umls_za32_single_vg4x4", [IsStreaming, IsInOutZA], []>; // INDEXED MLAL - def SVMLAL_LANE_VG2x1_F16 : Inst<"svmla_lane_za32[_{d}]_vg2x1", "vmddi", "bh", MergeNone, "aarch64_sme_fmlal_lane_vg2x1", [IsStreaming, IsSharedZA], [ImmCheck<3, ImmCheck0_7>]>; - def SVMLAL_LANE_VG2x2_F16 : Inst<"svmla_lane_za32[_{d}]_vg2x2", "vm2di", "bh", MergeNone, "aarch64_sme_fmlal_lane_vg2x2", [IsStreaming, IsSharedZA], [ImmCheck<3, ImmCheck0_7>]>; - def SVMLAL_LANE_VG2x4_F16 : Inst<"svmla_lane_za32[_{d}]_vg2x4", "vm4di", "bh", MergeNone, "aarch64_sme_fmlal_lane_vg2x4", [IsStreaming, IsSharedZA], [ImmCheck<3, ImmCheck0_7>]>; - def SVMLAL_LANE_VG2x1_S16 : Inst<"svmla_lane_za32[_{d}]_vg2x1", "vmddi", "s", MergeNone, "aarch64_sme_smlal_lane_vg2x1", [IsStreaming, IsSharedZA], [ImmCheck<3, ImmCheck0_7>]>; - def SVMLAL_LANE_VG2x2_S16 : Inst<"svmla_lane_za32[_{d}]_vg2x2", "vm2di", "s", MergeNone, "aarch64_sme_smlal_lane_vg2x2", [IsStreaming, IsSharedZA], [ImmCheck<3, ImmCheck0_7>]>; - def SVMLAL_LANE_VG2x4_S16 : Inst<"svmla_lane_za32[_{d}]_vg2x4", "vm4di", "s", MergeNone, "aarch64_sme_smlal_lane_vg2x4", [IsStreaming, IsSharedZA], [ImmCheck<3, ImmCheck0_7>]>; - def SVMLAL_LANE_VG2x1_U16 : Inst<"svmla_lane_za32[_{d}]_vg2x1", "vmddi", "Us", MergeNone, "aarch64_sme_umlal_lane_vg2x1", [IsStreaming, IsSharedZA], [ImmCheck<3, ImmCheck0_7>]>; - def SVMLAL_LANE_VG2x2_U16 : Inst<"svmla_lane_za32[_{d}]_vg2x2", "vm2di", "Us", MergeNone, "aarch64_sme_umlal_lane_vg2x2", [IsStreaming, IsSharedZA], [ImmCheck<3, ImmCheck0_7>]>; - def SVMLAL_LANE_VG2x4_U16 : Inst<"svmla_lane_za32[_{d}]_vg2x4", "vm4di", "Us", MergeNone, "aarch64_sme_umlal_lane_vg2x4", [IsStreaming, IsSharedZA], [ImmCheck<3, ImmCheck0_7>]>; + def SVMLAL_LANE_VG2x1_F16 : Inst<"svmla_lane_za32[_{d}]_vg2x1", "vmddi", "bh", MergeNone, "aarch64_sme_fmlal_lane_vg2x1", [IsStreaming, IsInOutZA], [ImmCheck<3, ImmCheck0_7>]>; + def SVMLAL_LANE_VG2x2_F16 : Inst<"svmla_lane_za32[_{d}]_vg2x2", "vm2di", "bh", MergeNone, "aarch64_sme_fmlal_lane_vg2x2", [IsStreaming, IsInOutZA], [ImmCheck<3, ImmCheck0_7>]>; + def SVMLAL_LANE_VG2x4_F16 : Inst<"svmla_lane_za32[_{d}]_vg2x4", "vm4di", "bh", MergeNone, "aarch64_sme_fmlal_lane_vg2x4", [IsStreaming, IsInOutZA], [ImmCheck<3, ImmCheck0_7>]>; + def SVMLAL_LANE_VG2x1_S16 : Inst<"svmla_lane_za32[_{d}]_vg2x1", "vmddi", "s", MergeNone, "aarch64_sme_smlal_lane_vg2x1", [IsStreaming, IsInOutZA], [ImmCheck<3, ImmCheck0_7>]>; + def SVMLAL_LANE_VG2x2_S16 : Inst<"svmla_lane_za32[_{d}]_vg2x2", "vm2di", "s", MergeNone, "aarch64_sme_smlal_lane_vg2x2", [IsStreaming, IsInOutZA], [ImmCheck<3, ImmCheck0_7>]>; + def SVMLAL_LANE_VG2x4_S16 : Inst<"svmla_lane_za32[_{d}]_vg2x4", "vm4di", "s", MergeNone, "aarch64_sme_smlal_lane_vg2x4", [IsStreaming, IsInOutZA], [ImmCheck<3, ImmCheck0_7>]>; + def SVMLAL_LANE_VG2x1_U16 : Inst<"svmla_lane_za32[_{d}]_vg2x1", "vmddi", "Us", MergeNone, "aarch64_sme_umlal_lane_vg2x1", [IsStreaming, IsInOutZA], [ImmCheck<3, ImmCheck0_7>]>; + def SVMLAL_LANE_VG2x2_U16 : Inst<"svmla_lane_za32[_{d}]_vg2x2", "vm2di", "Us", MergeNone, "aarch64_sme_umlal_lane_vg2x2", [IsStreaming, IsInOutZA], [ImmCheck<3, ImmCheck0_7>]>; + def SVMLAL_LANE_VG2x4_U16 : Inst<"svmla_lane_za32[_{d}]_vg2x4", "vm4di", "Us", MergeNone, "aarch64_sme_umlal_lane_vg2x4", [IsStreaming, IsInOutZA], [ImmCheck<3, ImmCheck0_7>]>; - def SVMLAL_LANE_VG4x1_S8 : Inst<"svmla_lane_za32[_{d}]_vg4x1", "vmddi", "c", MergeNone, "aarch64_sme_smla_za32_lane_vg4x1", [IsStreaming, IsSharedZA], [ImmCheck<3, ImmCheck0_15>]>; - def SVMLAL_LANE_VG4x1_U8 : Inst<"svmla_lane_za32[_{d}]_vg4x1", "vmddi", "Uc", MergeNone, "aarch64_sme_umla_za32_lane_vg4x1", [IsStreaming, IsSharedZA], [ImmCheck<3, ImmCheck0_15>]>; - def SVMLAL_LANE_VG4x2_S8 : Inst<"svmla_lane_za32[_{d}]_vg4x2", "vm2di", "c", MergeNone, "aarch64_sme_smla_za32_lane_vg4x2", [IsStreaming, IsSharedZA], [ImmCheck<3, ImmCheck0_15>]>; - def SVMLAL_LANE_VG4x2_U8 : Inst<"svmla_lane_za32[_{d}]_vg4x2", "vm2di", "Uc", MergeNone, "aarch64_sme_umla_za32_lane_vg4x2", [IsStreaming, IsSharedZA], [ImmCheck<3, ImmCheck0_15>]>; - def SVMLAL_LANE_VG4x4_S8 : Inst<"svmla_lane_za32[_{d}]_vg4x4", "vm4di", "c", MergeNone, "aarch64_sme_smla_za32_lane_vg4x4", [IsStreaming, IsSharedZA], [ImmCheck<3, ImmCheck0_15>]>; - def SVMLAL_LANE_VG4x4_U8 : Inst<"svmla_lane_za32[_{d}]_vg4x4", "vm4di", "Uc", MergeNone, "aarch64_sme_umla_za32_lane_vg4x4", [IsStreaming, IsSharedZA], [ImmCheck<3, ImmCheck0_15>]>; + def SVMLAL_LANE_VG4x1_S8 : Inst<"svmla_lane_za32[_{d}]_vg4x1", "vmddi", "c", MergeNone, "aarch64_sme_smla_za32_lane_vg4x1", [IsStreaming, IsInOutZA], [ImmCheck<3, ImmCheck0_15>]>; + def SVMLAL_LANE_VG4x1_U8 : Inst<"svmla_lane_za32[_{d}]_vg4x1", "vmddi", "Uc", MergeNone, "aarch64_sme_umla_za32_lane_vg4x1", [IsStreaming, IsInOutZA], [ImmCheck<3, ImmCheck0_15>]>; + def SVMLAL_LANE_VG4x2_S8 : Inst<"svmla_lane_za32[_{d}]_vg4x2", "vm2di", "c", MergeNone, "aarch64_sme_smla_za32_lane_vg4x2", [IsStreaming, IsInOutZA], [ImmCheck<3, ImmCheck0_15>]>; + def SVMLAL_LANE_VG4x2_U8 : Inst<"svmla_lane_za32[_{d}]_vg4x2", "vm2di", "Uc", MergeNone, "aarch64_sme_umla_za32_lane_vg4x2", [IsStreaming, IsInOutZA], [ImmCheck<3, ImmCheck0_15>]>; + def SVMLAL_LANE_VG4x4_S8 : Inst<"svmla_lane_za32[_{d}]_vg4x4", "vm4di", "c", MergeNone, "aarch64_sme_smla_za32_lane_vg4x4", [IsStreaming, IsInOutZA], [ImmCheck<3, ImmCheck0_15>]>; + def SVMLAL_LANE_VG4x4_U8 : Inst<"svmla_lane_za32[_{d}]_vg4x4", "vm4di", "Uc", MergeNone, "aarch64_sme_umla_za32_lane_vg4x4", [IsStreaming, IsInOutZA], [ImmCheck<3, ImmCheck0_15>]>; // INDEXED MLSL - def SVMLSL_LANE_VG2x1_F16 : Inst<"svmls_lane_za32[_{d}]_vg2x1", "vmddi", "bh", MergeNone, "aarch64_sme_fmlsl_lane_vg2x1", [IsStreaming, IsSharedZA], [ImmCheck<3, ImmCheck0_7>]>; - def SVMLSL_LANE_VG2x2_F16 : Inst<"svmls_lane_za32[_{d}]_vg2x2", "vm2di", "bh", MergeNone, "aarch64_sme_fmlsl_lane_vg2x2", [IsStreaming, IsSharedZA], [ImmCheck<3, ImmCheck0_7>]>; - def SVMLSL_LANE_VG2x4_F16 : Inst<"svmls_lane_za32[_{d}]_vg2x4", "vm4di", "bh", MergeNone, "aarch64_sme_fmlsl_lane_vg2x4", [IsStreaming, IsSharedZA], [ImmCheck<3, ImmCheck0_7>]>; - def SVMLSL_LANE_VG2x1_S16 : Inst<"svmls_lane_za32[_{d}]_vg2x1", "vmddi", "s", MergeNone, "aarch64_sme_smlsl_lane_vg2x1", [IsStreaming, IsSharedZA], [ImmCheck<3, ImmCheck0_7>]>; - def SVMLSL_LANE_VG2x2_S16 : Inst<"svmls_lane_za32[_{d}]_vg2x2", "vm2di", "s", MergeNone, "aarch64_sme_smlsl_lane_vg2x2", [IsStreaming, IsSharedZA], [ImmCheck<3, ImmCheck0_7>]>; - def SVMLSL_LANE_VG2x4_S16 : Inst<"svmls_lane_za32[_{d}]_vg2x4", "vm4di", "s", MergeNone, "aarch64_sme_smlsl_lane_vg2x4", [IsStreaming, IsSharedZA], [ImmCheck<3, ImmCheck0_7>]>; - def SVMLSL_LANE_VG2x1_U16 : Inst<"svmls_lane_za32[_{d}]_vg2x1", "vmddi", "Us", MergeNone, "aarch64_sme_umlsl_lane_vg2x1", [IsStreaming, IsSharedZA], [ImmCheck<3, ImmCheck0_7>]>; - def SVMLSL_LANE_VG2x2_U16 : Inst<"svmls_lane_za32[_{d}]_vg2x2", "vm2di", "Us", MergeNone, "aarch64_sme_umlsl_lane_vg2x2", [IsStreaming, IsSharedZA], [ImmCheck<3, ImmCheck0_7>]>; - def SVMLSL_LANE_VG2x4_U16 : Inst<"svmls_lane_za32[_{d}]_vg2x4", "vm4di", "Us", MergeNone, "aarch64_sme_umlsl_lane_vg2x4", [IsStreaming, IsSharedZA], [ImmCheck<3, ImmCheck0_7>]>; + def SVMLSL_LANE_VG2x1_F16 : Inst<"svmls_lane_za32[_{d}]_vg2x1", "vmddi", "bh", MergeNone, "aarch64_sme_fmlsl_lane_vg2x1", [IsStreaming, IsInOutZA], [ImmCheck<3, ImmCheck0_7>]>; + def SVMLSL_LANE_VG2x2_F16 : Inst<"svmls_lane_za32[_{d}]_vg2x2", "vm2di", "bh", MergeNone, "aarch64_sme_fmlsl_lane_vg2x2", [IsStreaming, IsInOutZA], [ImmCheck<3, ImmCheck0_7>]>; + def SVMLSL_LANE_VG2x4_F16 : Inst<"svmls_lane_za32[_{d}]_vg2x4", "vm4di", "bh", MergeNone, "aarch64_sme_fmlsl_lane_vg2x4", [IsStreaming, IsInOutZA], [ImmCheck<3, ImmCheck0_7>]>; + def SVMLSL_LANE_VG2x1_S16 : Inst<"svmls_lane_za32[_{d}]_vg2x1", "vmddi", "s", MergeNone, "aarch64_sme_smlsl_lane_vg2x1", [IsStreaming, IsInOutZA], [ImmCheck<3, ImmCheck0_7>]>; + def SVMLSL_LANE_VG2x2_S16 : Inst<"svmls_lane_za32[_{d}]_vg2x2", "vm2di", "s", MergeNone, "aarch64_sme_smlsl_lane_vg2x2", [IsStreaming, IsInOutZA], [ImmCheck<3, ImmCheck0_7>]>; + def SVMLSL_LANE_VG2x4_S16 : Inst<"svmls_lane_za32[_{d}]_vg2x4", "vm4di", "s", MergeNone, "aarch64_sme_smlsl_lane_vg2x4", [IsStreaming, IsInOutZA], [ImmCheck<3, ImmCheck0_7>]>; + def SVMLSL_LANE_VG2x1_U16 : Inst<"svmls_lane_za32[_{d}]_vg2x1", "vmddi", "Us", MergeNone, "aarch64_sme_umlsl_lane_vg2x1", [IsStreaming, IsInOutZA], [ImmCheck<3, ImmCheck0_7>]>; + def SVMLSL_LANE_VG2x2_U16 : Inst<"svmls_lane_za32[_{d}]_vg2x2", "vm2di", "Us", MergeNone, "aarch64_sme_umlsl_lane_vg2x2", [IsStreaming, IsInOutZA], [ImmCheck<3, ImmCheck0_7>]>; + def SVMLSL_LANE_VG2x4_U16 : Inst<"svmls_lane_za32[_{d}]_vg2x4", "vm4di", "Us", MergeNone, "aarch64_sme_umlsl_lane_vg2x4", [IsStreaming, IsInOutZA], [ImmCheck<3, ImmCheck0_7>]>; - def SVMLSL_LANE_VG4x1_S8 : Inst<"svmls_lane_za32[_{d}]_vg4x1", "vmddi", "c", MergeNone, "aarch64_sme_smls_za32_lane_vg4x1", [IsStreaming, IsSharedZA], [ImmCheck<3, ImmCheck0_15>]>; - def SVMLSL_LANE_VG4x1_U8 : Inst<"svmls_lane_za32[_{d}]_vg4x1", "vmddi", "Uc", MergeNone, "aarch64_sme_umls_za32_lane_vg4x1", [IsStreaming, IsSharedZA], [ImmCheck<3, ImmCheck0_15>]>; - def SVMLSL_LANE_VG4x2_S8 : Inst<"svmls_lane_za32[_{d}]_vg4x2", "vm2di", "c", MergeNone, "aarch64_sme_smls_za32_lane_vg4x2", [IsStreaming, IsSharedZA], [ImmCheck<3, ImmCheck0_15>]>; - def SVMLSL_LANE_VG4x2_U8 : Inst<"svmls_lane_za32[_{d}]_vg4x2", "vm2di", "Uc", MergeNone, "aarch64_sme_umls_za32_lane_vg4x2", [IsStreaming, IsSharedZA], [ImmCheck<3, ImmCheck0_15>]>; - def SVMLSL_LANE_VG4x4_S8 : Inst<"svmls_lane_za32[_{d}]_vg4x4", "vm4di", "c", MergeNone, "aarch64_sme_smls_za32_lane_vg4x4", [IsStreaming, IsSharedZA], [ImmCheck<3, ImmCheck0_15>]>; - def SVMLSL_LANE_VG4x4_U8 : Inst<"svmls_lane_za32[_{d}]_vg4x4", "vm4di", "Uc", MergeNone, "aarch64_sme_umls_za32_lane_vg4x4", [IsStreaming, IsSharedZA], [ImmCheck<3, ImmCheck0_15>]>; + def SVMLSL_LANE_VG4x1_S8 : Inst<"svmls_lane_za32[_{d}]_vg4x1", "vmddi", "c", MergeNone, "aarch64_sme_smls_za32_lane_vg4x1", [IsStreaming, IsInOutZA], [ImmCheck<3, ImmCheck0_15>]>; + def SVMLSL_LANE_VG4x1_U8 : Inst<"svmls_lane_za32[_{d}]_vg4x1", "vmddi", "Uc", MergeNone, "aarch64_sme_umls_za32_lane_vg4x1", [IsStreaming, IsInOutZA], [ImmCheck<3, ImmCheck0_15>]>; + def SVMLSL_LANE_VG4x2_S8 : Inst<"svmls_lane_za32[_{d}]_vg4x2", "vm2di", "c", MergeNone, "aarch64_sme_smls_za32_lane_vg4x2", [IsStreaming, IsInOutZA], [ImmCheck<3, ImmCheck0_15>]>; + def SVMLSL_LANE_VG4x2_U8 : Inst<"svmls_lane_za32[_{d}]_vg4x2", "vm2di", "Uc", MergeNone, "aarch64_sme_umls_za32_lane_vg4x2", [IsStreaming, IsInOutZA], [ImmCheck<3, ImmCheck0_15>]>; + def SVMLSL_LANE_VG4x4_S8 : Inst<"svmls_lane_za32[_{d}]_vg4x4", "vm4di", "c", MergeNone, "aarch64_sme_smls_za32_lane_vg4x4", [IsStreaming, IsInOutZA], [ImmCheck<3, ImmCheck0_15>]>; + def SVMLSL_LANE_VG4x4_U8 : Inst<"svmls_lane_za32[_{d}]_vg4x4", "vm4di", "Uc", MergeNone, "aarch64_sme_umls_za32_lane_vg4x4", [IsStreaming, IsInOutZA], [ImmCheck<3, ImmCheck0_15>]>; // SINGLE SUMLALL // Single sumla maps to usmla, with zn & zm operands swapped - def SVSUMLALL_SINGLE_VG4x1 : Inst<"svsumla_za32[_{d}]_vg4x1", "vmdu", "c", MergeNone, "aarch64_sme_usmla_za32_single_vg4x1", [IsStreaming, IsSharedZA], []>; + def SVSUMLALL_SINGLE_VG4x1 : Inst<"svsumla_za32[_{d}]_vg4x1", "vmdu", "c", MergeNone, "aarch64_sme_usmla_za32_single_vg4x1", [IsStreaming, IsInOutZA], []>; - def SVSUMLALL_SINGLE_VG4x2 : Inst<"svsumla[_single]_za32[_{d}]_vg4x2", "vm2.du", "c", MergeNone, "aarch64_sme_sumla_za32_single_vg4x2", [IsStreaming, IsSharedZA], []>; - def SVSUMLALL_SINGLE_VG4x4 : Inst<"svsumla[_single]_za32[_{d}]_vg4x4", "vm4.du", "c", MergeNone, "aarch64_sme_sumla_za32_single_vg4x4", [IsStreaming, IsSharedZA], []>; + def SVSUMLALL_SINGLE_VG4x2 : Inst<"svsumla[_single]_za32[_{d}]_vg4x2", "vm2.du", "c", MergeNone, "aarch64_sme_sumla_za32_single_vg4x2", [IsStreaming, IsInOutZA], []>; + def SVSUMLALL_SINGLE_VG4x4 : Inst<"svsumla[_single]_za32[_{d}]_vg4x4", "vm4.du", "c", MergeNone, "aarch64_sme_sumla_za32_single_vg4x4", [IsStreaming, IsInOutZA], []>; // Multi-multi sumla builtins are mapped to usmla, with zn & zm operands swapped - def SVSUMLALL_MULTI_VG4x2 : Inst<"svsumla_za32[_{d}]_vg4x2", "vm2.d2.u", "c", MergeNone, "aarch64_sme_usmla_za32_vg4x2", [IsStreaming, IsSharedZA], []>; - def SVSUMLALL_MULTI_VG4x4 : Inst<"svsumla_za32[_{d}]_vg4x4", "vm4.d4.u", "c", MergeNone, "aarch64_sme_usmla_za32_vg4x4", [IsStreaming, IsSharedZA], []>; + def SVSUMLALL_MULTI_VG4x2 : Inst<"svsumla_za32[_{d}]_vg4x2", "vm2.d2.u", "c", MergeNone, "aarch64_sme_usmla_za32_vg4x2", [IsStreaming, IsInOutZA], []>; + def SVSUMLALL_MULTI_VG4x4 : Inst<"svsumla_za32[_{d}]_vg4x4", "vm4.d4.u", "c", MergeNone, "aarch64_sme_usmla_za32_vg4x4", [IsStreaming, IsInOutZA], []>; // INDEXED SUMLALL - def SVSUMLALL_LANE_VG4x1 : Inst<"svsumla_lane_za32[_{d}]_vg4x1", "vmdui", "c", MergeNone, "aarch64_sme_sumla_za32_lane_vg4x1", [IsStreaming, IsSharedZA], [ImmCheck<3, ImmCheck0_15>]>; - def SVSUMLALL_LANE_VG4x2 : Inst<"svsumla_lane_za32[_{d}]_vg4x2", "vm2ui", "c", MergeNone, "aarch64_sme_sumla_za32_lane_vg4x2", [IsStreaming, IsSharedZA], [ImmCheck<3, ImmCheck0_15>]>; - def SVSUMLALL_LANE_VG4x4 : Inst<"svsumla_lane_za32[_{d}]_vg4x4", "vm4ui", "c", MergeNone, "aarch64_sme_sumla_za32_lane_vg4x4", [IsStreaming, IsSharedZA], [ImmCheck<3, ImmCheck0_15>]>; + def SVSUMLALL_LANE_VG4x1 : Inst<"svsumla_lane_za32[_{d}]_vg4x1", "vmdui", "c", MergeNone, "aarch64_sme_sumla_za32_lane_vg4x1", [IsStreaming, IsInOutZA], [ImmCheck<3, ImmCheck0_15>]>; + def SVSUMLALL_LANE_VG4x2 : Inst<"svsumla_lane_za32[_{d}]_vg4x2", "vm2ui", "c", MergeNone, "aarch64_sme_sumla_za32_lane_vg4x2", [IsStreaming, IsInOutZA], [ImmCheck<3, ImmCheck0_15>]>; + def SVSUMLALL_LANE_VG4x4 : Inst<"svsumla_lane_za32[_{d}]_vg4x4", "vm4ui", "c", MergeNone, "aarch64_sme_sumla_za32_lane_vg4x4", [IsStreaming, IsInOutZA], [ImmCheck<3, ImmCheck0_15>]>; // SINGLE USMLALL - def SVUSMLALL_SINGLE_VG4x1 : Inst<"svusmla_za32[_{d}]_vg4x1", "vmdx", "Uc", MergeNone, "aarch64_sme_usmla_za32_single_vg4x1", [IsStreaming, IsSharedZA], []>; - def SVUSMLALL_SINGLE_VG4x2 : Inst<"svusmla[_single]_za32[_{d}]_vg4x2", "vm2.dx", "Uc", MergeNone, "aarch64_sme_usmla_za32_single_vg4x2", [IsStreaming, IsSharedZA], []>; - def SVUSMLALL_SINGLE_VG4x4 : Inst<"svusmla[_single]_za32[_{d}]_vg4x4", "vm4.dx", "Uc", MergeNone, "aarch64_sme_usmla_za32_single_vg4x4", [IsStreaming, IsSharedZA], []>; + def SVUSMLALL_SINGLE_VG4x1 : Inst<"svusmla_za32[_{d}]_vg4x1", "vmdx", "Uc", MergeNone, "aarch64_sme_usmla_za32_single_vg4x1", [IsStreaming, IsInOutZA], []>; + def SVUSMLALL_SINGLE_VG4x2 : Inst<"svusmla[_single]_za32[_{d}]_vg4x2", "vm2.dx", "Uc", MergeNone, "aarch64_sme_usmla_za32_single_vg4x2", [IsStreaming, IsInOutZA], []>; + def SVUSMLALL_SINGLE_VG4x4 : Inst<"svusmla[_single]_za32[_{d}]_vg4x4", "vm4.dx", "Uc", MergeNone, "aarch64_sme_usmla_za32_single_vg4x4", [IsStreaming, IsInOutZA], []>; // MULTI USMLALL - def SVUSMLALL_MULTI_VG4x2 : Inst<"svusmla_za32[_{d}]_vg4x2", "vm2.d2.x", "Uc", MergeNone, "aarch64_sme_usmla_za32_vg4x2", [IsStreaming, IsSharedZA], []>; - def SVUSMLALL_MULTI_VG4x4 : Inst<"svusmla_za32[_{d}]_vg4x4", "vm4.d4.x", "Uc", MergeNone, "aarch64_sme_usmla_za32_vg4x4", [IsStreaming, IsSharedZA], []>; + def SVUSMLALL_MULTI_VG4x2 : Inst<"svusmla_za32[_{d}]_vg4x2", "vm2.d2.x", "Uc", MergeNone, "aarch64_sme_usmla_za32_vg4x2", [IsStreaming, IsInOutZA], []>; + def SVUSMLALL_MULTI_VG4x4 : Inst<"svusmla_za32[_{d}]_vg4x4", "vm4.d4.x", "Uc", MergeNone, "aarch64_sme_usmla_za32_vg4x4", [IsStreaming, IsInOutZA], []>; // INDEXED USMLALL - def SVUSMLALL_LANE_VG4x1 : Inst<"svusmla_lane_za32[_{d}]_vg4x1", "vmdxi", "Uc", MergeNone, "aarch64_sme_usmla_za32_lane_vg4x1", [IsStreaming, IsSharedZA], [ImmCheck<3, ImmCheck0_15>]>; - def SVUSMLALL_LANE_VG4x2 : Inst<"svusmla_lane_za32[_{d}]_vg4x2", "vm2xi", "Uc", MergeNone, "aarch64_sme_usmla_za32_lane_vg4x2", [IsStreaming, IsSharedZA], [ImmCheck<3, ImmCheck0_15>]>; - def SVUSMLALL_LANE_VG4x4 : Inst<"svusmla_lane_za32[_{d}]_vg4x4", "vm4xi", "Uc", MergeNone, "aarch64_sme_usmla_za32_lane_vg4x4", [IsStreaming, IsSharedZA], [ImmCheck<3, ImmCheck0_15>]>; + def SVUSMLALL_LANE_VG4x1 : Inst<"svusmla_lane_za32[_{d}]_vg4x1", "vmdxi", "Uc", MergeNone, "aarch64_sme_usmla_za32_lane_vg4x1", [IsStreaming, IsInOutZA], [ImmCheck<3, ImmCheck0_15>]>; + def SVUSMLALL_LANE_VG4x2 : Inst<"svusmla_lane_za32[_{d}]_vg4x2", "vm2xi", "Uc", MergeNone, "aarch64_sme_usmla_za32_lane_vg4x2", [IsStreaming, IsInOutZA], [ImmCheck<3, ImmCheck0_15>]>; + def SVUSMLALL_LANE_VG4x4 : Inst<"svusmla_lane_za32[_{d}]_vg4x4", "vm4xi", "Uc", MergeNone, "aarch64_sme_usmla_za32_lane_vg4x4", [IsStreaming, IsInOutZA], [ImmCheck<3, ImmCheck0_15>]>; } let TargetGuard = "sme2,sme-i16i64" in { // MULTI MLAL - def SVMLAL_MULTI_VG4x2_S16 : Inst<"svmla_za64[_{d}]_vg4x2", "vm22", "s", MergeNone, "aarch64_sme_smla_za64_vg4x2", [IsStreaming, IsSharedZA], []>; - def SVMLAL_MULTI_VG4x2_U16 : Inst<"svmla_za64[_{d}]_vg4x2", "vm22", "Us", MergeNone, "aarch64_sme_umla_za64_vg4x2", [IsStreaming, IsSharedZA], []>; - def SVMLAL_MULTI_VG4x4_S16 : Inst<"svmla_za64[_{d}]_vg4x4", "vm44", "s", MergeNone, "aarch64_sme_smla_za64_vg4x4", [IsStreaming, IsSharedZA], []>; - def SVMLAL_MULTI_VG4x4_U16 : Inst<"svmla_za64[_{d}]_vg4x4", "vm44", "Us", MergeNone, "aarch64_sme_umla_za64_vg4x4", [IsStreaming, IsSharedZA], []>; + def SVMLAL_MULTI_VG4x2_S16 : Inst<"svmla_za64[_{d}]_vg4x2", "vm22", "s", MergeNone, "aarch64_sme_smla_za64_vg4x2", [IsStreaming, IsInOutZA], []>; + def SVMLAL_MULTI_VG4x2_U16 : Inst<"svmla_za64[_{d}]_vg4x2", "vm22", "Us", MergeNone, "aarch64_sme_umla_za64_vg4x2", [IsStreaming, IsInOutZA], []>; + def SVMLAL_MULTI_VG4x4_S16 : Inst<"svmla_za64[_{d}]_vg4x4", "vm44", "s", MergeNone, "aarch64_sme_smla_za64_vg4x4", [IsStreaming, IsInOutZA], []>; + def SVMLAL_MULTI_VG4x4_U16 : Inst<"svmla_za64[_{d}]_vg4x4", "vm44", "Us", MergeNone, "aarch64_sme_umla_za64_vg4x4", [IsStreaming, IsInOutZA], []>; // MULTI MLSL - def SVMLSL_MULTI_VG4x2_S16 : Inst<"svmls_za64[_{d}]_vg4x2", "vm22", "s", MergeNone, "aarch64_sme_smls_za64_vg4x2", [IsStreaming, IsSharedZA], []>; - def SVMLSL_MULTI_VG4x2_U16 : Inst<"svmls_za64[_{d}]_vg4x2", "vm22", "Us", MergeNone, "aarch64_sme_umls_za64_vg4x2", [IsStreaming, IsSharedZA], []>; - def SVMLSL_MULTI_VG4x4_S16 : Inst<"svmls_za64[_{d}]_vg4x4", "vm44", "s", MergeNone, "aarch64_sme_smls_za64_vg4x4", [IsStreaming, IsSharedZA], []>; - def SVMLSL_MULTI_VG4x4_U16 : Inst<"svmls_za64[_{d}]_vg4x4", "vm44", "Us", MergeNone, "aarch64_sme_umls_za64_vg4x4", [IsStreaming, IsSharedZA], []>; + def SVMLSL_MULTI_VG4x2_S16 : Inst<"svmls_za64[_{d}]_vg4x2", "vm22", "s", MergeNone, "aarch64_sme_smls_za64_vg4x2", [IsStreaming, IsInOutZA], []>; + def SVMLSL_MULTI_VG4x2_U16 : Inst<"svmls_za64[_{d}]_vg4x2", "vm22", "Us", MergeNone, "aarch64_sme_umls_za64_vg4x2", [IsStreaming, IsInOutZA], []>; + def SVMLSL_MULTI_VG4x4_S16 : Inst<"svmls_za64[_{d}]_vg4x4", "vm44", "s", MergeNone, "aarch64_sme_smls_za64_vg4x4", [IsStreaming, IsInOutZA], []>; + def SVMLSL_MULTI_VG4x4_U16 : Inst<"svmls_za64[_{d}]_vg4x4", "vm44", "Us", MergeNone, "aarch64_sme_umls_za64_vg4x4", [IsStreaming, IsInOutZA], []>; // SINGLE MLAL - def SVMLAL_SINGLE_VG4x1_S16 : Inst<"svmla_za64[_{d}]_vg4x1", "vmdd", "s", MergeNone, "aarch64_sme_smla_za64_single_vg4x1", [IsStreaming, IsSharedZA], []>; - def SVMLAL_SINGLE_VG4x1_U16 : Inst<"svmla_za64[_{d}]_vg4x1", "vmdd", "Us", MergeNone, "aarch64_sme_umla_za64_single_vg4x1", [IsStreaming, IsSharedZA], []>; - def SVMLAL_SINGLE_VG4x2_S16 : Inst<"svmla[_single]_za64[_{d}]_vg4x2", "vm2d", "s", MergeNone, "aarch64_sme_smla_za64_single_vg4x2", [IsStreaming, IsSharedZA], []>; - def SVMLAL_SINGLE_VG4x2_U16 : Inst<"svmla[_single]_za64[_{d}]_vg4x2", "vm2d", "Us", MergeNone, "aarch64_sme_umla_za64_single_vg4x2", [IsStreaming, IsSharedZA], []>; - def SVMLAL_SINGLE_VG4x4_S16 : Inst<"svmla[_single]_za64[_{d}]_vg4x4", "vm4d", "s", MergeNone, "aarch64_sme_smla_za64_single_vg4x4", [IsStreaming, IsSharedZA], []>; - def SVMLAL_SINGLE_VG4x4_U16 : Inst<"svmla[_single]_za64[_{d}]_vg4x4", "vm4d", "Us", MergeNone, "aarch64_sme_umla_za64_single_vg4x4", [IsStreaming, IsSharedZA], []>; + def SVMLAL_SINGLE_VG4x1_S16 : Inst<"svmla_za64[_{d}]_vg4x1", "vmdd", "s", MergeNone, "aarch64_sme_smla_za64_single_vg4x1", [IsStreaming, IsInOutZA], []>; + def SVMLAL_SINGLE_VG4x1_U16 : Inst<"svmla_za64[_{d}]_vg4x1", "vmdd", "Us", MergeNone, "aarch64_sme_umla_za64_single_vg4x1", [IsStreaming, IsInOutZA], []>; + def SVMLAL_SINGLE_VG4x2_S16 : Inst<"svmla[_single]_za64[_{d}]_vg4x2", "vm2d", "s", MergeNone, "aarch64_sme_smla_za64_single_vg4x2", [IsStreaming, IsInOutZA], []>; + def SVMLAL_SINGLE_VG4x2_U16 : Inst<"svmla[_single]_za64[_{d}]_vg4x2", "vm2d", "Us", MergeNone, "aarch64_sme_umla_za64_single_vg4x2", [IsStreaming, IsInOutZA], []>; + def SVMLAL_SINGLE_VG4x4_S16 : Inst<"svmla[_single]_za64[_{d}]_vg4x4", "vm4d", "s", MergeNone, "aarch64_sme_smla_za64_single_vg4x4", [IsStreaming, IsInOutZA], []>; + def SVMLAL_SINGLE_VG4x4_U16 : Inst<"svmla[_single]_za64[_{d}]_vg4x4", "vm4d", "Us", MergeNone, "aarch64_sme_umla_za64_single_vg4x4", [IsStreaming, IsInOutZA], []>; // SINGLE MLSL - def SVMLSL_SINGLE_VG4x1_S16 : Inst<"svmls_za64[_{d}]_vg4x1", "vmdd", "s", MergeNone, "aarch64_sme_smls_za64_single_vg4x1", [IsStreaming, IsSharedZA], []>; - def SVMLSL_SINGLE_VG4x1_U16 : Inst<"svmls_za64[_{d}]_vg4x1", "vmdd", "Us", MergeNone, "aarch64_sme_umls_za64_single_vg4x1", [IsStreaming, IsSharedZA], []>; - def SVMLSL_SINGLE_VG4x2_S16 : Inst<"svmls[_single]_za64[_{d}]_vg4x2", "vm2d", "s", MergeNone, "aarch64_sme_smls_za64_single_vg4x2", [IsStreaming, IsSharedZA], []>; - def SVMLSL_SINGLE_VG4x2_U16 : Inst<"svmls[_single]_za64[_{d}]_vg4x2", "vm2d", "Us", MergeNone, "aarch64_sme_umls_za64_single_vg4x2", [IsStreaming, IsSharedZA], []>; - def SVMLSL_SINGLE_VG4x4_S16 : Inst<"svmls[_single]_za64[_{d}]_vg4x4", "vm4d", "s", MergeNone, "aarch64_sme_smls_za64_single_vg4x4", [IsStreaming, IsSharedZA], []>; - def SVMLSL_SINGLE_VG4x4_U16 : Inst<"svmls[_single]_za64[_{d}]_vg4x4", "vm4d", "Us", MergeNone, "aarch64_sme_umls_za64_single_vg4x4", [IsStreaming, IsSharedZA], []>; + def SVMLSL_SINGLE_VG4x1_S16 : Inst<"svmls_za64[_{d}]_vg4x1", "vmdd", "s", MergeNone, "aarch64_sme_smls_za64_single_vg4x1", [IsStreaming, IsInOutZA], []>; + def SVMLSL_SINGLE_VG4x1_U16 : Inst<"svmls_za64[_{d}]_vg4x1", "vmdd", "Us", MergeNone, "aarch64_sme_umls_za64_single_vg4x1", [IsStreaming, IsInOutZA], []>; + def SVMLSL_SINGLE_VG4x2_S16 : Inst<"svmls[_single]_za64[_{d}]_vg4x2", "vm2d", "s", MergeNone, "aarch64_sme_smls_za64_single_vg4x2", [IsStreaming, IsInOutZA], []>; + def SVMLSL_SINGLE_VG4x2_U16 : Inst<"svmls[_single]_za64[_{d}]_vg4x2", "vm2d", "Us", MergeNone, "aarch64_sme_umls_za64_single_vg4x2", [IsStreaming, IsInOutZA], []>; + def SVMLSL_SINGLE_VG4x4_S16 : Inst<"svmls[_single]_za64[_{d}]_vg4x4", "vm4d", "s", MergeNone, "aarch64_sme_smls_za64_single_vg4x4", [IsStreaming, IsInOutZA], []>; + def SVMLSL_SINGLE_VG4x4_U16 : Inst<"svmls[_single]_za64[_{d}]_vg4x4", "vm4d", "Us", MergeNone, "aarch64_sme_umls_za64_single_vg4x4", [IsStreaming, IsInOutZA], []>; // INDEXED MLAL - def SVMLAL_LANE_VG4x1_S16 : Inst<"svmla_lane_za64[_{d}]_vg4x1", "vmddi", "s", MergeNone, "aarch64_sme_smla_za64_lane_vg4x1", [IsStreaming, IsSharedZA], [ImmCheck<3, ImmCheck0_7>]>; - def SVMLAL_LANE_VG4x1_U16 : Inst<"svmla_lane_za64[_{d}]_vg4x1", "vmddi", "Us", MergeNone, "aarch64_sme_umla_za64_lane_vg4x1", [IsStreaming, IsSharedZA], [ImmCheck<3, ImmCheck0_7>]>; - def SVMLAL_LANE_VG4x2_S16 : Inst<"svmla_lane_za64[_{d}]_vg4x2", "vm2di", "s", MergeNone, "aarch64_sme_smla_za64_lane_vg4x2", [IsStreaming, IsSharedZA], [ImmCheck<3, ImmCheck0_7>]>; - def SVMLAL_LANE_VG4x2_U16 : Inst<"svmla_lane_za64[_{d}]_vg4x2", "vm2di", "Us", MergeNone, "aarch64_sme_umla_za64_lane_vg4x2", [IsStreaming, IsSharedZA], [ImmCheck<3, ImmCheck0_7>]>; - def SVMLAL_LANE_VG4x4_S16 : Inst<"svmla_lane_za64[_{d}]_vg4x4", "vm4di", "s", MergeNone, "aarch64_sme_smla_za64_lane_vg4x4", [IsStreaming, IsSharedZA], [ImmCheck<3, ImmCheck0_7>]>; - def SVMLAL_LANE_VG4x4_U16 : Inst<"svmla_lane_za64[_{d}]_vg4x4", "vm4di", "Us", MergeNone, "aarch64_sme_umla_za64_lane_vg4x4", [IsStreaming, IsSharedZA], [ImmCheck<3, ImmCheck0_7>]>; + def SVMLAL_LANE_VG4x1_S16 : Inst<"svmla_lane_za64[_{d}]_vg4x1", "vmddi", "s", MergeNone, "aarch64_sme_smla_za64_lane_vg4x1", [IsStreaming, IsInOutZA], [ImmCheck<3, ImmCheck0_7>]>; + def SVMLAL_LANE_VG4x1_U16 : Inst<"svmla_lane_za64[_{d}]_vg4x1", "vmddi", "Us", MergeNone, "aarch64_sme_umla_za64_lane_vg4x1", [IsStreaming, IsInOutZA], [ImmCheck<3, ImmCheck0_7>]>; + def SVMLAL_LANE_VG4x2_S16 : Inst<"svmla_lane_za64[_{d}]_vg4x2", "vm2di", "s", MergeNone, "aarch64_sme_smla_za64_lane_vg4x2", [IsStreaming, IsInOutZA], [ImmCheck<3, ImmCheck0_7>]>; + def SVMLAL_LANE_VG4x2_U16 : Inst<"svmla_lane_za64[_{d}]_vg4x2", "vm2di", "Us", MergeNone, "aarch64_sme_umla_za64_lane_vg4x2", [IsStreaming, IsInOutZA], [ImmCheck<3, ImmCheck0_7>]>; + def SVMLAL_LANE_VG4x4_S16 : Inst<"svmla_lane_za64[_{d}]_vg4x4", "vm4di", "s", MergeNone, "aarch64_sme_smla_za64_lane_vg4x4", [IsStreaming, IsInOutZA], [ImmCheck<3, ImmCheck0_7>]>; + def SVMLAL_LANE_VG4x4_U16 : Inst<"svmla_lane_za64[_{d}]_vg4x4", "vm4di", "Us", MergeNone, "aarch64_sme_umla_za64_lane_vg4x4", [IsStreaming, IsInOutZA], [ImmCheck<3, ImmCheck0_7>]>; // INDEXED MLSL - def SVMLSL_LANE_VG4x1_S16 : Inst<"svmls_lane_za64[_{d}]_vg4x1", "vmddi", "s", MergeNone, "aarch64_sme_smls_za64_lane_vg4x1", [IsStreaming, IsSharedZA], [ImmCheck<3, ImmCheck0_7>]>; - def SVMLSL_LANE_VG4x1_U16 : Inst<"svmls_lane_za64[_{d}]_vg4x1", "vmddi", "Us", MergeNone, "aarch64_sme_umls_za64_lane_vg4x1", [IsStreaming, IsSharedZA], [ImmCheck<3, ImmCheck0_7>]>; - def SVMLSL_LANE_VG4x2_S16 : Inst<"svmls_lane_za64[_{d}]_vg4x2", "vm2di", "s", MergeNone, "aarch64_sme_smls_za64_lane_vg4x2", [IsStreaming, IsSharedZA], [ImmCheck<3, ImmCheck0_7>]>; - def SVMLSL_LANE_VG4x2_U16 : Inst<"svmls_lane_za64[_{d}]_vg4x2", "vm2di", "Us", MergeNone, "aarch64_sme_umls_za64_lane_vg4x2", [IsStreaming, IsSharedZA], [ImmCheck<3, ImmCheck0_7>]>; - def SVMLSL_LANE_VG4x4_S16 : Inst<"svmls_lane_za64[_{d}]_vg4x4", "vm4di", "s", MergeNone, "aarch64_sme_smls_za64_lane_vg4x4", [IsStreaming, IsSharedZA], [ImmCheck<3, ImmCheck0_7>]>; - def SVMLSL_LANE_VG4x4_U16 : Inst<"svmls_lane_za64[_{d}]_vg4x4", "vm4di", "Us", MergeNone, "aarch64_sme_umls_za64_lane_vg4x4", [IsStreaming, IsSharedZA], [ImmCheck<3, ImmCheck0_7>]>; + def SVMLSL_LANE_VG4x1_S16 : Inst<"svmls_lane_za64[_{d}]_vg4x1", "vmddi", "s", MergeNone, "aarch64_sme_smls_za64_lane_vg4x1", [IsStreaming, IsInOutZA], [ImmCheck<3, ImmCheck0_7>]>; + def SVMLSL_LANE_VG4x1_U16 : Inst<"svmls_lane_za64[_{d}]_vg4x1", "vmddi", "Us", MergeNone, "aarch64_sme_umls_za64_lane_vg4x1", [IsStreaming, IsInOutZA], [ImmCheck<3, ImmCheck0_7>]>; + def SVMLSL_LANE_VG4x2_S16 : Inst<"svmls_lane_za64[_{d}]_vg4x2", "vm2di", "s", MergeNone, "aarch64_sme_smls_za64_lane_vg4x2", [IsStreaming, IsInOutZA], [ImmCheck<3, ImmCheck0_7>]>; + def SVMLSL_LANE_VG4x2_U16 : Inst<"svmls_lane_za64[_{d}]_vg4x2", "vm2di", "Us", MergeNone, "aarch64_sme_umls_za64_lane_vg4x2", [IsStreaming, IsInOutZA], [ImmCheck<3, ImmCheck0_7>]>; + def SVMLSL_LANE_VG4x4_S16 : Inst<"svmls_lane_za64[_{d}]_vg4x4", "vm4di", "s", MergeNone, "aarch64_sme_smls_za64_lane_vg4x4", [IsStreaming, IsInOutZA], [ImmCheck<3, ImmCheck0_7>]>; + def SVMLSL_LANE_VG4x4_U16 : Inst<"svmls_lane_za64[_{d}]_vg4x4", "vm4di", "Us", MergeNone, "aarch64_sme_umls_za64_lane_vg4x4", [IsStreaming, IsInOutZA], [ImmCheck<3, ImmCheck0_7>]>; } // // Spill and fill of ZT0 // let TargetGuard = "sme2" in { - def SVLDR_ZT : Inst<"svldr_zt", "viQ", "", MergeNone, "aarch64_sme_ldr_zt", [IsOverloadNone, IsStreamingCompatible, IsSharedZA], [ImmCheck<0, ImmCheck0_0>]>; - def SVSTR_ZT : Inst<"svstr_zt", "vi%", "", MergeNone, "aarch64_sme_str_zt", [IsOverloadNone, IsStreamingCompatible, IsSharedZA, IsPreservesZA], [ImmCheck<0, ImmCheck0_0>]>; + def SVLDR_ZT : Inst<"svldr_zt", "viQ", "", MergeNone, "aarch64_sme_ldr_zt", [IsOverloadNone, IsStreamingCompatible, IsInOutZT0], [ImmCheck<0, ImmCheck0_0>]>; + def SVSTR_ZT : Inst<"svstr_zt", "vi%", "", MergeNone, "aarch64_sme_str_zt", [IsOverloadNone, IsStreamingCompatible, IsInZT0], [ImmCheck<0, ImmCheck0_0>]>; } // // Zero ZT0 // let TargetGuard = "sme2" in { - def SVZERO_ZT : Inst<"svzero_zt", "vi", "", MergeNone, "aarch64_sme_zero_zt", [IsOverloadNone, IsStreamingCompatible, IsSharedZA], [ImmCheck<0, ImmCheck0_0>]>; + def SVZERO_ZT : Inst<"svzero_zt", "vi", "", MergeNone, "aarch64_sme_zero_zt", [IsOverloadNone, IsStreamingCompatible, IsOutZT0], [ImmCheck<0, ImmCheck0_0>]>; } // // lookup table expand four contiguous registers // let TargetGuard = "sme2" in { - def SVLUTI2_LANE_ZT_X4 : Inst<"svluti2_lane_zt_{d}_x4", "4.di[i", "cUcsUsiUibhf", MergeNone, "aarch64_sme_luti2_lane_zt_x4", [IsStreaming, IsSharedZA, IsPreservesZA], [ImmCheck<0, ImmCheck0_0>, ImmCheck<2, ImmCheck0_3>]>; - def SVLUTI4_LANE_ZT_X4 : Inst<"svluti4_lane_zt_{d}_x4", "4.di[i", "sUsiUibhf", MergeNone, "aarch64_sme_luti4_lane_zt_x4", [IsStreaming, IsSharedZA, IsPreservesZA], [ImmCheck<0, ImmCheck0_0>, ImmCheck<2, ImmCheck0_1>]>; + def SVLUTI2_LANE_ZT_X4 : Inst<"svluti2_lane_zt_{d}_x4", "4.di[i", "cUcsUsiUibhf", MergeNone, "aarch64_sme_luti2_lane_zt_x4", [IsStreaming, IsInZT0], [ImmCheck<0, ImmCheck0_0>, ImmCheck<2, ImmCheck0_3>]>; + def SVLUTI4_LANE_ZT_X4 : Inst<"svluti4_lane_zt_{d}_x4", "4.di[i", "sUsiUibhf", MergeNone, "aarch64_sme_luti4_lane_zt_x4", [IsStreaming, IsInZT0], [ImmCheck<0, ImmCheck0_0>, ImmCheck<2, ImmCheck0_1>]>; } // // lookup table expand one register // let TargetGuard = "sme2" in { - def SVLUTI2_LANE_ZT : Inst<"svluti2_lane_zt_{d}", "di[i", "cUcsUsiUibhf", MergeNone, "aarch64_sme_luti2_lane_zt", [IsStreaming, IsSharedZA, IsPreservesZA], [ImmCheck<0, ImmCheck0_0>, ImmCheck<2, ImmCheck0_15>]>; - def SVLUTI4_LANE_ZT : Inst<"svluti4_lane_zt_{d}", "di[i", "cUcsUsiUibhf", MergeNone, "aarch64_sme_luti4_lane_zt", [IsStreaming, IsSharedZA, IsPreservesZA], [ImmCheck<0, ImmCheck0_0>, ImmCheck<2, ImmCheck0_7>]>; + def SVLUTI2_LANE_ZT : Inst<"svluti2_lane_zt_{d}", "di[i", "cUcsUsiUibhf", MergeNone, "aarch64_sme_luti2_lane_zt", [IsStreaming, IsInZT0], [ImmCheck<0, ImmCheck0_0>, ImmCheck<2, ImmCheck0_15>]>; + def SVLUTI4_LANE_ZT : Inst<"svluti4_lane_zt_{d}", "di[i", "cUcsUsiUibhf", MergeNone, "aarch64_sme_luti4_lane_zt", [IsStreaming, IsInZT0], [ImmCheck<0, ImmCheck0_0>, ImmCheck<2, ImmCheck0_7>]>; } // // lookup table expand two contiguous registers // let TargetGuard = "sme2" in { - def SVLUTI2_LANE_ZT_X2 : Inst<"svluti2_lane_zt_{d}_x2", "2.di[i", "cUcsUsiUibhf", MergeNone, "aarch64_sme_luti2_lane_zt_x2", [IsStreaming, IsSharedZA, IsPreservesZA], [ImmCheck<0, ImmCheck0_0>, ImmCheck<2, ImmCheck0_7>]>; - def SVLUTI4_LANE_ZT_X2 : Inst<"svluti4_lane_zt_{d}_x2", "2.di[i", "cUcsUsiUibhf", MergeNone, "aarch64_sme_luti4_lane_zt_x2", [IsStreaming, IsSharedZA, IsPreservesZA], [ImmCheck<0, ImmCheck0_0>, ImmCheck<2, ImmCheck0_3>]>; + def SVLUTI2_LANE_ZT_X2 : Inst<"svluti2_lane_zt_{d}_x2", "2.di[i", "cUcsUsiUibhf", MergeNone, "aarch64_sme_luti2_lane_zt_x2", [IsStreaming, IsInZT0], [ImmCheck<0, ImmCheck0_0>, ImmCheck<2, ImmCheck0_7>]>; + def SVLUTI4_LANE_ZT_X2 : Inst<"svluti4_lane_zt_{d}_x2", "2.di[i", "cUcsUsiUibhf", MergeNone, "aarch64_sme_luti4_lane_zt_x2", [IsStreaming, IsInZT0], [ImmCheck<0, ImmCheck0_0>, ImmCheck<2, ImmCheck0_3>]>; } diff --git a/clang/include/clang/Basic/arm_sve.td b/clang/include/clang/Basic/arm_sve.td index 6f35e25617a..6da30e08e75 100644 --- a/clang/include/clang/Basic/arm_sve.td +++ b/clang/include/clang/Basic/arm_sve.td @@ -543,13 +543,13 @@ def SVADRD : SInst<"svadrd[_{0}base]_[{2}]index", "uud", "ilUiUl", MergeNone, " //////////////////////////////////////////////////////////////////////////////// // Scalar to vector -def SVDUPQ_8 : SInst<"svdupq[_n]_{d}", "dssssssssssssssss", "cUc", MergeNone>; -def SVDUPQ_16 : SInst<"svdupq[_n]_{d}", "dssssssss", "sUsh", MergeNone>; +def SVDUPQ_8 : SInst<"svdupq[_n]_{d}", "dssssssssssssssss", "cUc", MergeNone, "", [IsStreamingCompatible]>; +def SVDUPQ_16 : SInst<"svdupq[_n]_{d}", "dssssssss", "sUsh", MergeNone, "", [IsStreamingCompatible]>; let TargetGuard = "sve,bf16" in { - def SVDUPQ_BF16 : SInst<"svdupq[_n]_{d}", "dssssssss", "b", MergeNone>; + def SVDUPQ_BF16 : SInst<"svdupq[_n]_{d}", "dssssssss", "b", MergeNone, "", [IsStreamingCompatible]>; } -def SVDUPQ_32 : SInst<"svdupq[_n]_{d}", "dssss", "iUif", MergeNone>; -def SVDUPQ_64 : SInst<"svdupq[_n]_{d}", "dss", "lUld", MergeNone>; +def SVDUPQ_32 : SInst<"svdupq[_n]_{d}", "dssss", "iUif", MergeNone, "", [IsStreamingCompatible]>; +def SVDUPQ_64 : SInst<"svdupq[_n]_{d}", "dss", "lUld", MergeNone, "", [IsStreamingCompatible]>; multiclass svdup_base { def NAME : SInst; @@ -638,8 +638,8 @@ def SVQADD_N_U : SInst<"svqadd[_n_{d}]", "dda", "UcUsUiUl", MergeNone, "aarch64 def SVQSUB_N_S : SInst<"svqsub[_n_{d}]", "dda", "csil", MergeNone, "aarch64_sve_sqsub_x", [IsStreamingCompatible]>; def SVQSUB_N_U : SInst<"svqsub[_n_{d}]", "dda", "UcUsUiUl", MergeNone, "aarch64_sve_uqsub_x", [IsStreamingCompatible]>; -def SVDOT_LANE_S : SInst<"svdot_lane[_{d}]", "ddqqi", "il", MergeNone, "aarch64_sve_sdot_lane", [], [ImmCheck<3, ImmCheckLaneIndexDot, 2>]>; -def SVDOT_LANE_U : SInst<"svdot_lane[_{d}]", "ddqqi", "UiUl", MergeNone, "aarch64_sve_udot_lane", [], [ImmCheck<3, ImmCheckLaneIndexDot, 2>]>; +def SVDOT_LANE_S : SInst<"svdot_lane[_{d}]", "ddqqi", "il", MergeNone, "aarch64_sve_sdot_lane", [IsStreamingCompatible], [ImmCheck<3, ImmCheckLaneIndexDot, 2>]>; +def SVDOT_LANE_U : SInst<"svdot_lane[_{d}]", "ddqqi", "UiUl", MergeNone, "aarch64_sve_udot_lane", [IsStreamingCompatible], [ImmCheck<3, ImmCheckLaneIndexDot, 2>]>; //////////////////////////////////////////////////////////////////////////////// // Logical operations @@ -749,14 +749,14 @@ def SVCMPLS_WIDE_N : SInst<"svcmple_wide[_n_{d}]", "PPdj", "UcUsUi", MergeNone, //////////////////////////////////////////////////////////////////////////////// // While comparisons -def SVWHILELE_S32 : SInst<"svwhilele_{d}[_{1}]", "Pkk", "PcPsPiPl", MergeNone, "aarch64_sve_whilele", [IsOverloadWhile, IsStreamingCompatible]>; -def SVWHILELE_S64 : SInst<"svwhilele_{d}[_{1}]", "Pll", "PcPsPiPl", MergeNone, "aarch64_sve_whilele", [IsOverloadWhile, IsStreamingCompatible]>; -def SVWHILELO_U32 : SInst<"svwhilelt_{d}[_{1}]", "Pmm", "PUcPUsPUiPUl", MergeNone, "aarch64_sve_whilelo", [IsOverloadWhile, IsStreamingCompatible]>; -def SVWHILELO_U64 : SInst<"svwhilelt_{d}[_{1}]", "Pnn", "PUcPUsPUiPUl", MergeNone, "aarch64_sve_whilelo", [IsOverloadWhile, IsStreamingCompatible]>; -def SVWHILELS_U32 : SInst<"svwhilele_{d}[_{1}]", "Pmm", "PUcPUsPUiPUl", MergeNone, "aarch64_sve_whilels", [IsOverloadWhile, IsStreamingCompatible]>; -def SVWHILELS_U64 : SInst<"svwhilele_{d}[_{1}]", "Pnn", "PUcPUsPUiPUl", MergeNone, "aarch64_sve_whilels", [IsOverloadWhile, IsStreamingCompatible]>; -def SVWHILELT_S32 : SInst<"svwhilelt_{d}[_{1}]", "Pkk", "PcPsPiPl", MergeNone, "aarch64_sve_whilelt", [IsOverloadWhile, IsStreamingCompatible]>; -def SVWHILELT_S64 : SInst<"svwhilelt_{d}[_{1}]", "Pll", "PcPsPiPl", MergeNone, "aarch64_sve_whilelt", [IsOverloadWhile, IsStreamingCompatible]>; +def SVWHILELE_S32 : SInst<"svwhilele_{d}[_{1}]", "Pkk", "PcPsPiPl", MergeNone, "aarch64_sve_whilele", [IsOverloadWhileOrMultiVecCvt, IsStreamingCompatible]>; +def SVWHILELE_S64 : SInst<"svwhilele_{d}[_{1}]", "Pll", "PcPsPiPl", MergeNone, "aarch64_sve_whilele", [IsOverloadWhileOrMultiVecCvt, IsStreamingCompatible]>; +def SVWHILELO_U32 : SInst<"svwhilelt_{d}[_{1}]", "Pmm", "PUcPUsPUiPUl", MergeNone, "aarch64_sve_whilelo", [IsOverloadWhileOrMultiVecCvt, IsStreamingCompatible]>; +def SVWHILELO_U64 : SInst<"svwhilelt_{d}[_{1}]", "Pnn", "PUcPUsPUiPUl", MergeNone, "aarch64_sve_whilelo", [IsOverloadWhileOrMultiVecCvt, IsStreamingCompatible]>; +def SVWHILELS_U32 : SInst<"svwhilele_{d}[_{1}]", "Pmm", "PUcPUsPUiPUl", MergeNone, "aarch64_sve_whilels", [IsOverloadWhileOrMultiVecCvt, IsStreamingCompatible]>; +def SVWHILELS_U64 : SInst<"svwhilele_{d}[_{1}]", "Pnn", "PUcPUsPUiPUl", MergeNone, "aarch64_sve_whilels", [IsOverloadWhileOrMultiVecCvt, IsStreamingCompatible]>; +def SVWHILELT_S32 : SInst<"svwhilelt_{d}[_{1}]", "Pkk", "PcPsPiPl", MergeNone, "aarch64_sve_whilelt", [IsOverloadWhileOrMultiVecCvt, IsStreamingCompatible]>; +def SVWHILELT_S64 : SInst<"svwhilelt_{d}[_{1}]", "Pll", "PcPsPiPl", MergeNone, "aarch64_sve_whilelt", [IsOverloadWhileOrMultiVecCvt, IsStreamingCompatible]>; //////////////////////////////////////////////////////////////////////////////// // Counting bit @@ -835,14 +835,14 @@ def SVSCALE_N_M : SInst<"svscale[_n_{d}]", "dPdK", "hfd", MergeOp1, "aarch64_sv def SVSCALE_N_X : SInst<"svscale[_n_{d}]", "dPdK", "hfd", MergeAny, "aarch64_sve_fscale", [IsStreamingCompatible]>; def SVSCALE_N_Z : SInst<"svscale[_n_{d}]", "dPdK", "hfd", MergeZero, "aarch64_sve_fscale", [IsStreamingCompatible]>; -defm SVMAD_F : SInstZPZZZ<"svmad", "hfd", "aarch64_sve_fmad", "aarch64_sve_fmla_u", [ReverseMergeAnyAccOp]>; -defm SVMLA_F : SInstZPZZZ<"svmla", "hfd", "aarch64_sve_fmla", "aarch64_sve_fmla_u">; -defm SVMLS_F : SInstZPZZZ<"svmls", "hfd", "aarch64_sve_fmls", "aarch64_sve_fmls_u">; -defm SVMSB_F : SInstZPZZZ<"svmsb", "hfd", "aarch64_sve_fmsb", "aarch64_sve_fmls_u", [ReverseMergeAnyAccOp]>; -defm SVNMAD_F : SInstZPZZZ<"svnmad", "hfd", "aarch64_sve_fnmad", "aarch64_sve_fnmla_u", [ReverseMergeAnyAccOp]>; -defm SVNMLA_F : SInstZPZZZ<"svnmla", "hfd", "aarch64_sve_fnmla", "aarch64_sve_fnmla_u">; -defm SVNMLS_F : SInstZPZZZ<"svnmls", "hfd", "aarch64_sve_fnmls", "aarch64_sve_fnmls_u">; -defm SVNMSB_F : SInstZPZZZ<"svnmsb", "hfd", "aarch64_sve_fnmsb", "aarch64_sve_fnmls_u", [ReverseMergeAnyAccOp]>; +defm SVMAD_F : SInstZPZZZ<"svmad", "hfd", "aarch64_sve_fmad", "aarch64_sve_fmla_u", [IsStreamingCompatible, ReverseMergeAnyAccOp]>; +defm SVMLA_F : SInstZPZZZ<"svmla", "hfd", "aarch64_sve_fmla", "aarch64_sve_fmla_u", [IsStreamingCompatible]>; +defm SVMLS_F : SInstZPZZZ<"svmls", "hfd", "aarch64_sve_fmls", "aarch64_sve_fmls_u", [IsStreamingCompatible]>; +defm SVMSB_F : SInstZPZZZ<"svmsb", "hfd", "aarch64_sve_fmsb", "aarch64_sve_fmls_u", [IsStreamingCompatible, ReverseMergeAnyAccOp]>; +defm SVNMAD_F : SInstZPZZZ<"svnmad", "hfd", "aarch64_sve_fnmad", "aarch64_sve_fnmla_u", [IsStreamingCompatible, ReverseMergeAnyAccOp]>; +defm SVNMLA_F : SInstZPZZZ<"svnmla", "hfd", "aarch64_sve_fnmla", "aarch64_sve_fnmla_u", [IsStreamingCompatible]>; +defm SVNMLS_F : SInstZPZZZ<"svnmls", "hfd", "aarch64_sve_fnmls", "aarch64_sve_fnmls_u", [IsStreamingCompatible]>; +defm SVNMSB_F : SInstZPZZZ<"svnmsb", "hfd", "aarch64_sve_fnmsb", "aarch64_sve_fnmls_u", [IsStreamingCompatible, ReverseMergeAnyAccOp]>; def SVCADD_M : SInst<"svcadd[_{d}]", "dPddi", "hfd", MergeOp1, "aarch64_sve_fcadd", [IsStreamingCompatible], [ImmCheck<3, ImmCheckComplexRot90_270>]>; def SVCADD_X : SInst<"svcadd[_{d}]", "dPddi", "hfd", MergeAny, "aarch64_sve_fcadd", [IsStreamingCompatible], [ImmCheck<3, ImmCheckComplexRot90_270>]>; @@ -881,11 +881,11 @@ def SVACLE : SInst<"svacle[_{d}]", "PPdd", "hfd", MergeNone, "aarch64_sve_facg def SVACLT : SInst<"svaclt[_{d}]", "PPdd", "hfd", MergeNone, "aarch64_sve_facgt", [ReverseCompare, IsStreamingCompatible]>; def SVCMPUO : SInst<"svcmpuo[_{d}]", "PPdd", "hfd", MergeNone, "aarch64_sve_fcmpuo", [IsStreamingCompatible]>; -def SVACGE_N : SInst<"svacge[_n_{d}]", "PPda", "hfd", MergeNone, "aarch64_sve_facge">; -def SVACGT_N : SInst<"svacgt[_n_{d}]", "PPda", "hfd", MergeNone, "aarch64_sve_facgt">; -def SVACLE_N : SInst<"svacle[_n_{d}]", "PPda", "hfd", MergeNone, "aarch64_sve_facge", [ReverseCompare]>; -def SVACLT_N : SInst<"svaclt[_n_{d}]", "PPda", "hfd", MergeNone, "aarch64_sve_facgt", [ReverseCompare]>; -def SVCMPUO_N : SInst<"svcmpuo[_n_{d}]", "PPda", "hfd", MergeNone, "aarch64_sve_fcmpuo">; +def SVACGE_N : SInst<"svacge[_n_{d}]", "PPda", "hfd", MergeNone, "aarch64_sve_facge", [IsStreamingCompatible]>; +def SVACGT_N : SInst<"svacgt[_n_{d}]", "PPda", "hfd", MergeNone, "aarch64_sve_facgt", [IsStreamingCompatible]>; +def SVACLE_N : SInst<"svacle[_n_{d}]", "PPda", "hfd", MergeNone, "aarch64_sve_facge", [ReverseCompare, IsStreamingCompatible]>; +def SVACLT_N : SInst<"svaclt[_n_{d}]", "PPda", "hfd", MergeNone, "aarch64_sve_facgt", [ReverseCompare, IsStreamingCompatible]>; +def SVCMPUO_N : SInst<"svcmpuo[_n_{d}]", "PPda", "hfd", MergeNone, "aarch64_sve_fcmpuo", [IsStreamingCompatible]>; def SVCMPEQ_F : SInst<"svcmpeq[_{d}]", "PPdd", "hfd", MergeNone, "aarch64_sve_fcmpeq", [IsStreamingCompatible]>; def SVCMPNE_F : SInst<"svcmpne[_{d}]", "PPdd", "hfd", MergeNone, "aarch64_sve_fcmpne", [IsStreamingCompatible]>; @@ -1023,15 +1023,15 @@ def SVCOMPACT : SInst<"svcompact[_{d}]", "dPd", "ilUiUlfd", MergeNo // splat of any possible lane. It is upto LLVM to pick a more efficient // instruction such as DUP (indexed) if the lane index fits the range of the // instruction's immediate. -def SVDUP_LANE : SInst<"svdup_lane[_{d}]", "ddL", "csilUcUsUiUlhfd", MergeNone, "aarch64_sve_tbl">; +def SVDUP_LANE : SInst<"svdup_lane[_{d}]", "ddL", "csilUcUsUiUlhfd", MergeNone, "aarch64_sve_tbl", [IsStreamingCompatible]>; let TargetGuard = "sve,bf16" in { def SVDUP_LANE_BF16 : - SInst<"svdup_lane[_{d}]", "ddL", "b", MergeNone, "aarch64_sve_tbl">; + SInst<"svdup_lane[_{d}]", "ddL", "b", MergeNone, "aarch64_sve_tbl", [IsStreamingCompatible]>; } -def SVDUPQ_LANE : SInst<"svdupq_lane[_{d}]", "ddn", "csilUcUsUiUlhfd", MergeNone, "aarch64_sve_dupq_lane">; +def SVDUPQ_LANE : SInst<"svdupq_lane[_{d}]", "ddn", "csilUcUsUiUlhfd", MergeNone, "aarch64_sve_dupq_lane", [IsStreamingCompatible]>; let TargetGuard = "sve,bf16" in { - def SVDUPQ_LANE_BF16 : SInst<"svdupq_lane[_{d}]", "ddn", "b", MergeNone, "aarch64_sve_dupq_lane">; + def SVDUPQ_LANE_BF16 : SInst<"svdupq_lane[_{d}]", "ddn", "b", MergeNone, "aarch64_sve_dupq_lane", [IsStreamingCompatible]>; } def SVEXT : SInst<"svext[_{d}]", "dddi", "csilUcUsUiUlhfd", MergeNone, "aarch64_sve_ext", [IsStreamingCompatible], [ImmCheck<2, ImmCheckExtract, 1>]>; defm SVLASTA : SVEPerm<"svlasta[_{d}]", "sPd", "aarch64_sve_lasta">; @@ -1109,11 +1109,11 @@ def SVPFALSE : SInst<"svpfalse[_b]", "Pv", "", MergeNone, "", [IsOverloadNone, I def SVPTRUE_PAT : SInst<"svptrue_pat_{d}", "PI", "PcPsPiPl", MergeNone, "aarch64_sve_ptrue", [IsStreamingCompatible]>; def SVPTRUE : SInst<"svptrue_{d}", "Pv", "PcPsPiPl", MergeNone, "aarch64_sve_ptrue", [IsAppendSVALL, IsStreamingCompatible]>; -def SVDUPQ_B8 : SInst<"svdupq[_n]_{d}", "Pssssssssssssssss", "Pc", MergeNone>; -def SVDUPQ_B16 : SInst<"svdupq[_n]_{d}", "Pssssssss", "Ps", MergeNone>; -def SVDUPQ_B32 : SInst<"svdupq[_n]_{d}", "Pssss", "Pi", MergeNone>; -def SVDUPQ_B64 : SInst<"svdupq[_n]_{d}", "Pss", "Pl", MergeNone>; -def SVDUP_N_B : SInst<"svdup[_n]_{d}", "Ps", "PcPsPiPl", MergeNone>; +def SVDUPQ_B8 : SInst<"svdupq[_n]_{d}", "Pssssssssssssssss", "Pc", MergeNone, "", [IsStreamingCompatible]>; +def SVDUPQ_B16 : SInst<"svdupq[_n]_{d}", "Pssssssss", "Ps", MergeNone, "", [IsStreamingCompatible]>; +def SVDUPQ_B32 : SInst<"svdupq[_n]_{d}", "Pssss", "Pi", MergeNone, "", [IsStreamingCompatible]>; +def SVDUPQ_B64 : SInst<"svdupq[_n]_{d}", "Pss", "Pl", MergeNone, "", [IsStreamingCompatible]>; +def SVDUP_N_B : SInst<"svdup[_n]_{d}", "Ps", "PcPsPiPl", MergeNone, "", [IsStreamingCompatible]>; //////////////////////////////////////////////////////////////////////////////// @@ -1268,10 +1268,10 @@ def SVZIP2Q : SInst<"svzip2q[_{d}]", "ddd", "csilUcUsUiUlhfd", MergeNo let TargetGuard = "sve,bf16,f64mm" in { def SVTRN1Q_BF16 : SInst<"svtrn1q[_{d}]", "ddd", "b", MergeNone, "aarch64_sve_trn1q">; def SVTRN2Q_BF16 : SInst<"svtrn2q[_{d}]", "ddd", "b", MergeNone, "aarch64_sve_trn2q">; -def SVUZP1Q_BF16 : SInst<"svuzp1q[_{d}]", "ddd", "b", MergeNone, "aarch64_sve_uzp1q">; -def SVUZP2Q_BF16 : SInst<"svuzp2q[_{d}]", "ddd", "b", MergeNone, "aarch64_sve_uzp2q">; -def SVZIP1Q_BF16 : SInst<"svzip1q[_{d}]", "ddd", "b", MergeNone, "aarch64_sve_zip1q">; -def SVZIP2Q_BF16 : SInst<"svzip2q[_{d}]", "ddd", "b", MergeNone, "aarch64_sve_zip2q">; +def SVUZP1Q_BF16 : SInst<"svuzp1q[_{d}]", "ddd", "b", MergeNone, "aarch64_sve_uzp1q", [IsStreamingCompatible]>; +def SVUZP2Q_BF16 : SInst<"svuzp2q[_{d}]", "ddd", "b", MergeNone, "aarch64_sve_uzp2q", [IsStreamingCompatible]>; +def SVZIP1Q_BF16 : SInst<"svzip1q[_{d}]", "ddd", "b", MergeNone, "aarch64_sve_zip1q", [IsStreamingCompatible]>; +def SVZIP2Q_BF16 : SInst<"svzip2q[_{d}]", "ddd", "b", MergeNone, "aarch64_sve_zip2q", [IsStreamingCompatible]>; } //////////////////////////////////////////////////////////////////////////////// @@ -1281,9 +1281,9 @@ def SVUNDEF_2 : SInst<"svundef2_{d}", "2v", "csilUcUsUiUlhfd", MergeNone, "", [I def SVUNDEF_3 : SInst<"svundef3_{d}", "3v", "csilUcUsUiUlhfd", MergeNone, "", [IsUndef, IsStreamingCompatible]>; def SVUNDEF_4 : SInst<"svundef4_{d}", "4v", "csilUcUsUiUlhfd", MergeNone, "", [IsUndef, IsStreamingCompatible]>; -def SVCREATE_2 : SInst<"svcreate2[_{d}]", "2dd", "csilUcUsUiUlhfd", MergeNone, "", [IsTupleCreate]>; -def SVCREATE_3 : SInst<"svcreate3[_{d}]", "3ddd", "csilUcUsUiUlhfd", MergeNone, "", [IsTupleCreate]>; -def SVCREATE_4 : SInst<"svcreate4[_{d}]", "4dddd", "csilUcUsUiUlhfd", MergeNone, "", [IsTupleCreate]>; +def SVCREATE_2 : SInst<"svcreate2[_{d}]", "2dd", "csilUcUsUiUlhfd", MergeNone, "", [IsTupleCreate, IsStreamingCompatible]>; +def SVCREATE_3 : SInst<"svcreate3[_{d}]", "3ddd", "csilUcUsUiUlhfd", MergeNone, "", [IsTupleCreate, IsStreamingCompatible]>; +def SVCREATE_4 : SInst<"svcreate4[_{d}]", "4dddd", "csilUcUsUiUlhfd", MergeNone, "", [IsTupleCreate, IsStreamingCompatible]>; let TargetGuard = "sve,bf16" in { def SVUNDEF_1_BF16 : SInst<"svundef_{d}", "dv", "b", MergeNone, "", [IsUndef, IsStreamingCompatible]>; @@ -1291,65 +1291,70 @@ def SVUNDEF_2_BF16 : SInst<"svundef2_{d}", "2v", "b", MergeNone, "", [IsUndef, I def SVUNDEF_3_BF16 : SInst<"svundef3_{d}", "3v", "b", MergeNone, "", [IsUndef, IsStreamingCompatible]>; def SVUNDEF_4_BF16 : SInst<"svundef4_{d}", "4v", "b", MergeNone, "", [IsUndef, IsStreamingCompatible]>; -def SVCREATE_2_BF16 : SInst<"svcreate2[_{d}]", "2dd", "b", MergeNone, "", [IsTupleCreate]>; -def SVCREATE_3_BF16 : SInst<"svcreate3[_{d}]", "3ddd", "b", MergeNone, "", [IsTupleCreate]>; -def SVCREATE_4_BF16 : SInst<"svcreate4[_{d}]", "4dddd", "b", MergeNone, "", [IsTupleCreate]>; +def SVCREATE_2_BF16 : SInst<"svcreate2[_{d}]", "2dd", "b", MergeNone, "", [IsTupleCreate, IsStreamingCompatible]>; +def SVCREATE_3_BF16 : SInst<"svcreate3[_{d}]", "3ddd", "b", MergeNone, "", [IsTupleCreate, IsStreamingCompatible]>; +def SVCREATE_4_BF16 : SInst<"svcreate4[_{d}]", "4dddd", "b", MergeNone, "", [IsTupleCreate, IsStreamingCompatible]>; } -let TargetGuard = "sve2p1" in { - def SVCREATE_2_B : SInst<"svcreate2[_{d}]", "2dd", "Pc", MergeNone, "", [IsTupleCreate]>; - def SVCREATE_4_B : SInst<"svcreate4[_{d}]", "4dddd", "Pc", MergeNone, "", [IsTupleCreate]>; +let TargetGuard = "sve2p1|sme2" in { + def SVCREATE_2_B : SInst<"svcreate2[_b]", "2dd", "Pc", MergeNone, "", [IsTupleCreate, IsStreamingCompatible]>; + def SVCREATE_4_B : SInst<"svcreate4[_b]", "4dddd", "Pc", MergeNone, "", [IsTupleCreate, IsStreamingCompatible]>; } //////////////////////////////////////////////////////////////////////////////// // Vector insertion and extraction -def SVGET_2 : SInst<"svget2[_{d}]", "d2i", "csilUcUsUiUlhfd", MergeNone, "", [IsTupleGet], [ImmCheck<1, ImmCheck0_1>]>; -def SVGET_3 : SInst<"svget3[_{d}]", "d3i", "csilUcUsUiUlhfd", MergeNone, "", [IsTupleGet], [ImmCheck<1, ImmCheck0_2>]>; -def SVGET_4 : SInst<"svget4[_{d}]", "d4i", "csilUcUsUiUlhfd", MergeNone, "", [IsTupleGet], [ImmCheck<1, ImmCheck0_3>]>; +def SVGET_2 : SInst<"svget2[_{d}]", "d2i", "csilUcUsUiUlhfd", MergeNone, "", [IsTupleGet, IsStreamingCompatible], [ImmCheck<1, ImmCheck0_1>]>; +def SVGET_3 : SInst<"svget3[_{d}]", "d3i", "csilUcUsUiUlhfd", MergeNone, "", [IsTupleGet, IsStreamingCompatible], [ImmCheck<1, ImmCheck0_2>]>; +def SVGET_4 : SInst<"svget4[_{d}]", "d4i", "csilUcUsUiUlhfd", MergeNone, "", [IsTupleGet, IsStreamingCompatible], [ImmCheck<1, ImmCheck0_3>]>; -def SVSET_2 : SInst<"svset2[_{d}]", "22id", "csilUcUsUiUlhfd", MergeNone, "", [IsTupleSet], [ImmCheck<1, ImmCheck0_1>]>; -def SVSET_3 : SInst<"svset3[_{d}]", "33id", "csilUcUsUiUlhfd", MergeNone, "", [IsTupleSet], [ImmCheck<1, ImmCheck0_2>]>; -def SVSET_4 : SInst<"svset4[_{d}]", "44id", "csilUcUsUiUlhfd", MergeNone, "", [IsTupleSet], [ImmCheck<1, ImmCheck0_3>]>; +def SVSET_2 : SInst<"svset2[_{d}]", "22id", "csilUcUsUiUlhfd", MergeNone, "", [IsTupleSet, IsStreamingCompatible], [ImmCheck<1, ImmCheck0_1>]>; +def SVSET_3 : SInst<"svset3[_{d}]", "33id", "csilUcUsUiUlhfd", MergeNone, "", [IsTupleSet, IsStreamingCompatible], [ImmCheck<1, ImmCheck0_2>]>; +def SVSET_4 : SInst<"svset4[_{d}]", "44id", "csilUcUsUiUlhfd", MergeNone, "", [IsTupleSet, IsStreamingCompatible], [ImmCheck<1, ImmCheck0_3>]>; let TargetGuard = "sve,bf16" in { -def SVGET_2_BF16 : SInst<"svget2[_{d}]", "d2i", "b", MergeNone, "", [IsTupleGet], [ImmCheck<1, ImmCheck0_1>]>; -def SVGET_3_BF16 : SInst<"svget3[_{d}]", "d3i", "b", MergeNone, "", [IsTupleGet], [ImmCheck<1, ImmCheck0_2>]>; -def SVGET_4_BF16 : SInst<"svget4[_{d}]", "d4i", "b", MergeNone, "", [IsTupleGet], [ImmCheck<1, ImmCheck0_3>]>; +def SVGET_2_BF16 : SInst<"svget2[_{d}]", "d2i", "b", MergeNone, "", [IsTupleGet, IsStreamingCompatible], [ImmCheck<1, ImmCheck0_1>]>; +def SVGET_3_BF16 : SInst<"svget3[_{d}]", "d3i", "b", MergeNone, "", [IsTupleGet, IsStreamingCompatible], [ImmCheck<1, ImmCheck0_2>]>; +def SVGET_4_BF16 : SInst<"svget4[_{d}]", "d4i", "b", MergeNone, "", [IsTupleGet, IsStreamingCompatible], [ImmCheck<1, ImmCheck0_3>]>; -def SVSET_2_BF16 : SInst<"svset2[_{d}]", "22id", "b", MergeNone, "", [IsTupleSet], [ImmCheck<1, ImmCheck0_1>]>; -def SVSET_3_BF16 : SInst<"svset3[_{d}]", "33id", "b", MergeNone, "", [IsTupleSet], [ImmCheck<1, ImmCheck0_2>]>; -def SVSET_4_BF16 : SInst<"svset4[_{d}]", "44id", "b", MergeNone, "", [IsTupleSet], [ImmCheck<1, ImmCheck0_3>]>; +def SVSET_2_BF16 : SInst<"svset2[_{d}]", "22id", "b", MergeNone, "", [IsTupleSet, IsStreamingCompatible], [ImmCheck<1, ImmCheck0_1>]>; +def SVSET_3_BF16 : SInst<"svset3[_{d}]", "33id", "b", MergeNone, "", [IsTupleSet, IsStreamingCompatible], [ImmCheck<1, ImmCheck0_2>]>; +def SVSET_4_BF16 : SInst<"svset4[_{d}]", "44id", "b", MergeNone, "", [IsTupleSet, IsStreamingCompatible], [ImmCheck<1, ImmCheck0_3>]>; } -let TargetGuard = "sve2p1" in { - def SVGET_2_B : SInst<"svget2[_{d}]", "d2i", "Pc", MergeNone, "", [IsTupleGet], [ImmCheck<1, ImmCheck0_1>]>; - def SVGET_4_B : SInst<"svget4[_{d}]", "d4i", "Pc", MergeNone, "", [IsTupleGet], [ImmCheck<1, ImmCheck0_3>]>; +let TargetGuard = "sve2p1|sme2" in { + def SVGET_2_B : SInst<"svget2[_b]", "d2i", "Pc", MergeNone, "", [IsTupleGet, IsStreamingCompatible], [ImmCheck<1, ImmCheck0_1>]>; + def SVGET_4_B : SInst<"svget4[_b]", "d4i", "Pc", MergeNone, "", [IsTupleGet, IsStreamingCompatible], [ImmCheck<1, ImmCheck0_3>]>; - def SVSET_2_B : SInst<"svset2[_{d}]", "22id", "Pc", MergeNone, "", [IsTupleSet], [ImmCheck<1, ImmCheck0_1>]>; - def SVSET_4_B : SInst<"svset4[_{d}]", "44id", "Pc", MergeNone, "", [IsTupleSet], [ImmCheck<1, ImmCheck0_3>]>; + def SVSET_2_B : SInst<"svset2[_b]", "22id", "Pc", MergeNone, "", [IsTupleSet, IsStreamingCompatible], [ImmCheck<1, ImmCheck0_1>]>; + def SVSET_4_B : SInst<"svset4[_b]", "44id", "Pc", MergeNone, "", [IsTupleSet, IsStreamingCompatible], [ImmCheck<1, ImmCheck0_3>]>; +} + +let TargetGuard = "sve2p1|sme2" in { + def SVUNDEF_2_B: Inst<"svundef2_b", "2", "Pc", MergeNone, "", [IsUndef, IsStreamingCompatible], []>; + def SVUNDEF_4_B: Inst<"svundef4_b", "4", "Pc", MergeNone, "", [IsUndef, IsStreamingCompatible], []>; } //////////////////////////////////////////////////////////////////////////////// // SVE2 WhileGE/GT let TargetGuard = "sve2" in { -def SVWHILEGE_S32 : SInst<"svwhilege_{d}[_{1}]", "Pkk", "PcPsPiPl", MergeNone, "aarch64_sve_whilege", [IsOverloadWhile, IsStreamingCompatible]>; -def SVWHILEGE_S64 : SInst<"svwhilege_{d}[_{1}]", "Pll", "PcPsPiPl", MergeNone, "aarch64_sve_whilege", [IsOverloadWhile, IsStreamingCompatible]>; -def SVWHILEGT_S32 : SInst<"svwhilegt_{d}[_{1}]", "Pkk", "PcPsPiPl", MergeNone, "aarch64_sve_whilegt", [IsOverloadWhile, IsStreamingCompatible]>; -def SVWHILEGT_S64 : SInst<"svwhilegt_{d}[_{1}]", "Pll", "PcPsPiPl", MergeNone, "aarch64_sve_whilegt", [IsOverloadWhile, IsStreamingCompatible]>; -def SVWHILEHI_U32 : SInst<"svwhilegt_{d}[_{1}]", "Pmm", "PUcPUsPUiPUl", MergeNone, "aarch64_sve_whilehi", [IsOverloadWhile, IsStreamingCompatible]>; -def SVWHILEHI_U64 : SInst<"svwhilegt_{d}[_{1}]", "Pnn", "PUcPUsPUiPUl", MergeNone, "aarch64_sve_whilehi", [IsOverloadWhile, IsStreamingCompatible]>; -def SVWHILEHS_U32 : SInst<"svwhilege_{d}[_{1}]", "Pmm", "PUcPUsPUiPUl", MergeNone, "aarch64_sve_whilehs", [IsOverloadWhile, IsStreamingCompatible]>; -def SVWHILEHS_U64 : SInst<"svwhilege_{d}[_{1}]", "Pnn", "PUcPUsPUiPUl", MergeNone, "aarch64_sve_whilehs", [IsOverloadWhile, IsStreamingCompatible]>; +def SVWHILEGE_S32 : SInst<"svwhilege_{d}[_{1}]", "Pkk", "PcPsPiPl", MergeNone, "aarch64_sve_whilege", [IsOverloadWhileOrMultiVecCvt, IsStreamingCompatible]>; +def SVWHILEGE_S64 : SInst<"svwhilege_{d}[_{1}]", "Pll", "PcPsPiPl", MergeNone, "aarch64_sve_whilege", [IsOverloadWhileOrMultiVecCvt, IsStreamingCompatible]>; +def SVWHILEGT_S32 : SInst<"svwhilegt_{d}[_{1}]", "Pkk", "PcPsPiPl", MergeNone, "aarch64_sve_whilegt", [IsOverloadWhileOrMultiVecCvt, IsStreamingCompatible]>; +def SVWHILEGT_S64 : SInst<"svwhilegt_{d}[_{1}]", "Pll", "PcPsPiPl", MergeNone, "aarch64_sve_whilegt", [IsOverloadWhileOrMultiVecCvt, IsStreamingCompatible]>; +def SVWHILEHI_U32 : SInst<"svwhilegt_{d}[_{1}]", "Pmm", "PUcPUsPUiPUl", MergeNone, "aarch64_sve_whilehi", [IsOverloadWhileOrMultiVecCvt, IsStreamingCompatible]>; +def SVWHILEHI_U64 : SInst<"svwhilegt_{d}[_{1}]", "Pnn", "PUcPUsPUiPUl", MergeNone, "aarch64_sve_whilehi", [IsOverloadWhileOrMultiVecCvt, IsStreamingCompatible]>; +def SVWHILEHS_U32 : SInst<"svwhilege_{d}[_{1}]", "Pmm", "PUcPUsPUiPUl", MergeNone, "aarch64_sve_whilehs", [IsOverloadWhileOrMultiVecCvt, IsStreamingCompatible]>; +def SVWHILEHS_U64 : SInst<"svwhilege_{d}[_{1}]", "Pnn", "PUcPUsPUiPUl", MergeNone, "aarch64_sve_whilehs", [IsOverloadWhileOrMultiVecCvt, IsStreamingCompatible]>; } let TargetGuard = "sve2p1|sme2" in { - def SVWHILEGE_S64_X2 : SInst<"svwhilege_{d}[_{1}]_x2", "2ll", "PcPsPiPl", MergeNone, "aarch64_sve_whilege_x2">; - def SVWHILEGT_S64_X2 : SInst<"svwhilegt_{d}[_{1}]_x2", "2ll", "PcPsPiPl", MergeNone, "aarch64_sve_whilegt_x2">; - def SVWHILEHI_U64_X2 : SInst<"svwhilegt_{d}[_{1}]_x2", "2nn", "PcPsPiPl", MergeNone, "aarch64_sve_whilehi_x2">; - def SVWHILEHS_U64_X2 : SInst<"svwhilege_{d}[_{1}]_x2", "2nn", "PcPsPiPl", MergeNone, "aarch64_sve_whilehs_x2">; - def SVWHILELE_S64_X2 : SInst<"svwhilele_{d}[_{1}]_x2", "2ll", "PcPsPiPl", MergeNone, "aarch64_sve_whilele_x2">; - def SVWHILELT_S64_X2 : SInst<"svwhilelt_{d}[_{1}]_x2", "2ll", "PcPsPiPl", MergeNone, "aarch64_sve_whilelt_x2">; - def SVWHILELO_U64_X2 : SInst<"svwhilelt_{d}[_{1}]_x2", "2nn", "PcPsPiPl", MergeNone, "aarch64_sve_whilelo_x2">; - def SVWHILELS_U64_X2 : SInst<"svwhilele_{d}[_{1}]_x2", "2nn", "PcPsPiPl", MergeNone, "aarch64_sve_whilels_x2">; + def SVWHILEGE_S64_X2 : SInst<"svwhilege_{d}[_{1}]_x2", "2ll", "PcPsPiPl", MergeNone, "aarch64_sve_whilege_x2", [IsStreamingOrSVE2p1]>; + def SVWHILEGT_S64_X2 : SInst<"svwhilegt_{d}[_{1}]_x2", "2ll", "PcPsPiPl", MergeNone, "aarch64_sve_whilegt_x2", [IsStreamingOrSVE2p1]>; + def SVWHILEHI_U64_X2 : SInst<"svwhilegt_{d}[_{1}]_x2", "2nn", "PcPsPiPl", MergeNone, "aarch64_sve_whilehi_x2", [IsStreamingOrSVE2p1]>; + def SVWHILEHS_U64_X2 : SInst<"svwhilege_{d}[_{1}]_x2", "2nn", "PcPsPiPl", MergeNone, "aarch64_sve_whilehs_x2", [IsStreamingOrSVE2p1]>; + def SVWHILELE_S64_X2 : SInst<"svwhilele_{d}[_{1}]_x2", "2ll", "PcPsPiPl", MergeNone, "aarch64_sve_whilele_x2", [IsStreamingOrSVE2p1]>; + def SVWHILELT_S64_X2 : SInst<"svwhilelt_{d}[_{1}]_x2", "2ll", "PcPsPiPl", MergeNone, "aarch64_sve_whilelt_x2", [IsStreamingOrSVE2p1]>; + def SVWHILELO_U64_X2 : SInst<"svwhilelt_{d}[_{1}]_x2", "2nn", "PcPsPiPl", MergeNone, "aarch64_sve_whilelo_x2", [IsStreamingOrSVE2p1]>; + def SVWHILELS_U64_X2 : SInst<"svwhilele_{d}[_{1}]_x2", "2nn", "PcPsPiPl", MergeNone, "aarch64_sve_whilels_x2", [IsStreamingOrSVE2p1]>; } @@ -1826,8 +1831,8 @@ def SVPMULLB_PAIR : SInst<"svpmullb_pair[_{d}]", "ddd", "UcUi", Mer def SVPMULLB_PAIR_N : SInst<"svpmullb_pair[_n_{d}]", "dda", "UcUi", MergeNone, "aarch64_sve_pmullb_pair", [IsStreamingCompatible]>; def SVPMULLT : SInst<"svpmullt[_{d}]", "dhh", "UsUl", MergeNone, "", [IsStreamingCompatible]>; def SVPMULLT_N : SInst<"svpmullt[_n_{d}]", "dhR", "UsUl", MergeNone, "", [IsStreamingCompatible]>; -def SVPMULLT_PAIR : SInst<"svpmullt_pair[_{d}]", "ddd", "UcUi", MergeNone, "aarch64_sve_pmullt_pair">; -def SVPMULLT_PAIR_N : SInst<"svpmullt_pair[_n_{d}]", "dda", "UcUi", MergeNone, "aarch64_sve_pmullt_pair">; +def SVPMULLT_PAIR : SInst<"svpmullt_pair[_{d}]", "ddd", "UcUi", MergeNone, "aarch64_sve_pmullt_pair", [IsStreamingCompatible]>; +def SVPMULLT_PAIR_N : SInst<"svpmullt_pair[_n_{d}]", "dda", "UcUi", MergeNone, "aarch64_sve_pmullt_pair", [IsStreamingCompatible]>; } //////////////////////////////////////////////////////////////////////////////// @@ -1948,14 +1953,10 @@ def SVBGRP_N : SInst<"svbgrp[_n_{d}]", "dda", "UcUsUiUl", MergeNone, "aarch64_sv } let TargetGuard = "sve2p1|sme" in { -def SVPSEL_B : SInst<"svpsel_lane_b8", "PPPm", "Pc", MergeNone, "", [IsStreamingCompatible], []>; -def SVPSEL_H : SInst<"svpsel_lane_b16", "PPPm", "Ps", MergeNone, "", [IsStreamingCompatible], []>; -def SVPSEL_S : SInst<"svpsel_lane_b32", "PPPm", "Pi", MergeNone, "", [IsStreamingCompatible], []>; -def SVPSEL_D : SInst<"svpsel_lane_b64", "PPPm", "Pl", MergeNone, "", [IsStreamingCompatible], []>; -def SVPSEL_COUNT_ALIAS_B : SInst<"svpsel_lane_c8", "}}Pm", "Pc", MergeNone, "", [IsStreamingCompatible], []>; -def SVPSEL_COUNT_ALIAS_H : SInst<"svpsel_lane_c16", "}}Pm", "Ps", MergeNone, "", [IsStreamingCompatible], []>; -def SVPSEL_COUNT_ALIAS_S : SInst<"svpsel_lane_c32", "}}Pm", "Pi", MergeNone, "", [IsStreamingCompatible], []>; -def SVPSEL_COUNT_ALIAS_D : SInst<"svpsel_lane_c64", "}}Pm", "Pl", MergeNone, "", [IsStreamingCompatible], []>; +def SVPSEL_B : SInst<"svpsel_lane_b8", "PPPm", "Pc", MergeNone, "", [IsStreamingOrSVE2p1], []>; +def SVPSEL_H : SInst<"svpsel_lane_b16", "PPPm", "Ps", MergeNone, "", [IsStreamingOrSVE2p1], []>; +def SVPSEL_S : SInst<"svpsel_lane_b32", "PPPm", "Pi", MergeNone, "", [IsStreamingOrSVE2p1], []>; +def SVPSEL_D : SInst<"svpsel_lane_b64", "PPPm", "Pl", MergeNone, "", [IsStreamingOrSVE2p1], []>; } // Standalone sve2.1 builtins @@ -1979,6 +1980,11 @@ let TargetGuard = "sve2p1|sme2" in { def SVPEXT_SINGLE : SInst<"svpext_lane_{d}", "P}i", "QcQsQiQl", MergeNone, "aarch64_sve_pext", [IsStreamingOrSVE2p1], [ImmCheck<1, ImmCheck0_3>]>; def SVPEXT_X2 : SInst<"svpext_lane_{d}_x2", "2.P}i", "QcQsQiQl", MergeNone, "aarch64_sve_pext_x2", [IsStreamingOrSVE2p1], [ImmCheck<1, ImmCheck0_1>]>; +def SVPSEL_COUNT_ALIAS_B : SInst<"svpsel_lane_c8", "}}Pm", "Pc", MergeNone, "", [IsStreamingOrSVE2p1], []>; +def SVPSEL_COUNT_ALIAS_H : SInst<"svpsel_lane_c16", "}}Pm", "Ps", MergeNone, "", [IsStreamingOrSVE2p1], []>; +def SVPSEL_COUNT_ALIAS_S : SInst<"svpsel_lane_c32", "}}Pm", "Pi", MergeNone, "", [IsStreamingOrSVE2p1], []>; +def SVPSEL_COUNT_ALIAS_D : SInst<"svpsel_lane_c64", "}}Pm", "Pl", MergeNone, "", [IsStreamingOrSVE2p1], []>; + def SVWHILEGE_COUNT : SInst<"svwhilege_{d}[_{1}]", "}lli", "QcQsQiQl", MergeNone, "aarch64_sve_whilege_{d}", [IsOverloadNone, IsStreamingOrSVE2p1], [ImmCheck<2, ImmCheck2_4_Mul2>]>; def SVWHILEGT_COUNT : SInst<"svwhilegt_{d}[_{1}]", "}lli", "QcQsQiQl", MergeNone, "aarch64_sve_whilegt_{d}", [IsOverloadNone, IsStreamingOrSVE2p1], [ImmCheck<2, ImmCheck2_4_Mul2>]>; def SVWHILELE_COUNT : SInst<"svwhilele_{d}[_{1}]", "}lli", "QcQsQiQl", MergeNone, "aarch64_sve_whilele_{d}", [IsOverloadNone, IsStreamingOrSVE2p1], [ImmCheck<2, ImmCheck2_4_Mul2>]>; @@ -2039,13 +2045,13 @@ let TargetGuard = "sve2p1|sme2" in { defm STNT1 : MultiVecStore<"stnt1">; } -let TargetGuard = "sve2p1" in { -def SVDOT_X2_S : SInst<"svdot[_{d}_{2}]", "ddhh", "i", MergeNone, "aarch64_sve_sdot_x2", [], []>; -def SVDOT_X2_U : SInst<"svdot[_{d}_{2}]", "ddhh", "Ui", MergeNone, "aarch64_sve_udot_x2", [], []>; -def SVDOT_X2_F : SInst<"svdot[_{d}_{2}]", "ddhh", "f", MergeNone, "aarch64_sve_fdot_x2", [], []>; -def SVDOT_LANE_X2_S : SInst<"svdot_lane[_{d}_{2}]", "ddhhi", "i", MergeNone, "aarch64_sve_sdot_lane_x2", [], [ImmCheck<3, ImmCheck0_3>]>; -def SVDOT_LANE_X2_U : SInst<"svdot_lane[_{d}_{2}]", "ddhhi", "Ui", MergeNone, "aarch64_sve_udot_lane_x2", [], [ImmCheck<3, ImmCheck0_3>]>; -def SVDOT_LANE_X2_F : SInst<"svdot_lane[_{d}_{2}]", "ddhhi", "f", MergeNone, "aarch64_sve_fdot_lane_x2", [], [ImmCheck<3, ImmCheck0_3>]>; +let TargetGuard = "sve2p1|sme2" in { +def SVDOT_X2_S : SInst<"svdot[_{d}_{2}]", "ddhh", "i", MergeNone, "aarch64_sve_sdot_x2", [IsStreamingOrSVE2p1], []>; +def SVDOT_X2_U : SInst<"svdot[_{d}_{2}]", "ddhh", "Ui", MergeNone, "aarch64_sve_udot_x2", [IsStreamingOrSVE2p1], []>; +def SVDOT_X2_F : SInst<"svdot[_{d}_{2}]", "ddhh", "f", MergeNone, "aarch64_sve_fdot_x2", [IsStreamingOrSVE2p1], []>; +def SVDOT_LANE_X2_S : SInst<"svdot_lane[_{d}_{2}]", "ddhhi", "i", MergeNone, "aarch64_sve_sdot_lane_x2", [IsStreamingOrSVE2p1], [ImmCheck<3, ImmCheck0_3>]>; +def SVDOT_LANE_X2_U : SInst<"svdot_lane[_{d}_{2}]", "ddhhi", "Ui", MergeNone, "aarch64_sve_udot_lane_x2", [IsStreamingOrSVE2p1], [ImmCheck<3, ImmCheck0_3>]>; +def SVDOT_LANE_X2_F : SInst<"svdot_lane[_{d}_{2}]", "ddhhi", "f", MergeNone, "aarch64_sve_fdot_lane_x2", [IsStreamingOrSVE2p1], [ImmCheck<3, ImmCheck0_3>]>; } let TargetGuard = "sve2p1|sme2" in { @@ -2238,15 +2244,15 @@ let TargetGuard = "sme2" in { def SVCVT_F16_X2 : SInst<"svcvt_f16[_f32_x2]", "e2", "f", MergeNone, "aarch64_sve_fcvt_x2", [IsStreaming],[]>; def SVCVT_BF16_X2 : SInst<"svcvt_bf16[_f32_x2]", "$2", "f", MergeNone, "aarch64_sve_bfcvt_x2", [IsOverloadNone, IsStreaming],[]>; - def SVCVT_F32_U32_X2 : SInst<"svcvt_{d}[_u32_x2]", "2.d2.u", "f", MergeNone, "aarch64_sve_fcvtu_x2", [IsStreaming], []>; - def SVCVT_U32_F32_X2 : SInst<"svcvt_u32[_{d}_x2]", "2.u2.d", "f", MergeNone, "aarch64_sve_ucvtf_x2", [IsStreaming], []>; - def SVCVT_F32_S32_X2 : SInst<"svcvt_{d}[_s32_x2]", "2.d2.x", "f", MergeNone, "aarch64_sve_fcvts_x2", [IsStreaming], []>; - def SVCVT_S32_F32_X2 : SInst<"svcvt_s32[_{d}_x2]", "2.x2.d", "f", MergeNone, "aarch64_sve_scvtf_x2", [IsStreaming], []>; + def SVCVT_F32_U32_X2 : SInst<"svcvt_{d}[_u32_x2]", "2.d2.u", "f", MergeNone, "aarch64_sve_ucvtf_x2", [IsStreaming, IsOverloadWhileOrMultiVecCvt], []>; + def SVCVT_U32_F32_X2 : SInst<"svcvt_{d}[_f32_x2]", "2.d2.M", "Ui", MergeNone, "aarch64_sve_fcvtzu_x2", [IsStreaming, IsOverloadWhileOrMultiVecCvt], []>; + def SVCVT_F32_S32_X2 : SInst<"svcvt_{d}[_s32_x2]", "2.d2.x", "f", MergeNone, "aarch64_sve_scvtf_x2", [IsStreaming, IsOverloadWhileOrMultiVecCvt], []>; + def SVCVT_S32_F32_X2 : SInst<"svcvt_{d}[_f32_x2]", "2.d2.M", "i", MergeNone, "aarch64_sve_fcvtzs_x2", [IsStreaming, IsOverloadWhileOrMultiVecCvt], []>; - def SVCVT_F32_U32_X4 : SInst<"svcvt_{d}[_u32_x4]", "4.d4.u", "f", MergeNone, "aarch64_sve_fcvtu_x4", [IsStreaming], []>; - def SVCVT_U32_F32_X4 : SInst<"svcvt_u32[_{d}_x4]", "4.u4.d", "f", MergeNone, "aarch64_sve_ucvtf_x4", [IsStreaming], []>; - def SVCVT_F32_S32_X4 : SInst<"svcvt_{d}[_s32_x4]", "4.d4.x", "f", MergeNone, "aarch64_sve_fcvts_x4", [IsStreaming], []>; - def SVCVT_S32_F32_X4 : SInst<"svcvt_s32[_{d}_x4]", "4.x4.d", "f", MergeNone, "aarch64_sve_scvtf_x4", [IsStreaming], []>; + def SVCVT_F32_U32_X4 : SInst<"svcvt_{d}[_u32_x4]", "4.d4.u", "f", MergeNone, "aarch64_sve_ucvtf_x4", [IsStreaming, IsOverloadWhileOrMultiVecCvt], []>; + def SVCVT_U32_F32_X4 : SInst<"svcvt_{d}[_f32_x4]", "4.d4.M", "Ui", MergeNone, "aarch64_sve_fcvtzu_x4", [IsStreaming, IsOverloadWhileOrMultiVecCvt], []>; + def SVCVT_F32_S32_X4 : SInst<"svcvt_{d}[_s32_x4]", "4.d4.x", "f", MergeNone, "aarch64_sve_scvtf_x4", [IsStreaming, IsOverloadWhileOrMultiVecCvt], []>; + def SVCVT_S32_F32_X4 : SInst<"svcvt_{d}[_f32_x4]", "4.d4.M", "i", MergeNone, "aarch64_sve_fcvtzs_x4", [IsStreaming, IsOverloadWhileOrMultiVecCvt], []>; } // diff --git a/clang/include/clang/Basic/arm_sve_sme_incl.td b/clang/include/clang/Basic/arm_sve_sme_incl.td index ad29864440c..9a6ea9898ef 100644 --- a/clang/include/clang/Basic/arm_sve_sme_incl.td +++ b/clang/include/clang/Basic/arm_sve_sme_incl.td @@ -194,40 +194,44 @@ def FirstSplatOperand : FlagType<0x00000400>; // These flags are used to specify which scalar operand // needs to be duplicated/splatted into a vector. // : : -def SplatOperandMask : FlagType<0x00001C00>; -def IsLoad : FlagType<0x00002000>; -def IsStore : FlagType<0x00004000>; -def IsGatherLoad : FlagType<0x00008000>; -def IsScatterStore : FlagType<0x00010000>; -def IsStructLoad : FlagType<0x00020000>; -def IsStructStore : FlagType<0x00040000>; -def IsZExtReturn : FlagType<0x00080000>; // Return value is sign-extend by default -def IsOverloadNone : FlagType<0x00100000>; // Intrinsic does not take any overloaded types. -def IsOverloadWhile : FlagType<0x00200000>; // Use {default type, typeof(operand1)} as overloaded types. -def IsOverloadWhileRW : FlagType<0x00400000>; // Use {pred(default type), typeof(operand0)} as overloaded types. -def IsOverloadCvt : FlagType<0x00800000>; // Use {typeof(operand0), typeof(last operand)} as overloaded types. -def OverloadKindMask : FlagType<0x00E00000>; // When the masked values are all '0', the default type is used as overload type. -def IsByteIndexed : FlagType<0x01000000>; -def IsAppendSVALL : FlagType<0x02000000>; // Appends SV_ALL as the last operand. -def IsInsertOp1SVALL : FlagType<0x04000000>; // Inserts SV_ALL as the second operand. -def IsPrefetch : FlagType<0x08000000>; // Contiguous prefetches. -def IsGatherPrefetch : FlagType<0x10000000>; -def ReverseCompare : FlagType<0x20000000>; // Compare operands must be swapped. -def ReverseUSDOT : FlagType<0x40000000>; // Unsigned/signed operands must be swapped. -def IsUndef : FlagType<0x80000000>; // Codegen `undef` of given type. -def IsTupleCreate : FlagType<0x100000000>; -def IsTupleGet : FlagType<0x200000000>; -def IsTupleSet : FlagType<0x400000000>; -def ReverseMergeAnyBinOp : FlagType<0x800000000>; // e.g. Implement SUBR_X using SUB_X. -def ReverseMergeAnyAccOp : FlagType<0x1000000000>; // e.g. Implement MSB_X using MLS_X. -def IsStreaming : FlagType<0x2000000000>; -def IsStreamingCompatible : FlagType<0x4000000000>; -def IsSharedZA : FlagType<0x8000000000>; -def IsPreservesZA : FlagType<0x10000000000>; -def IsReadZA : FlagType<0x20000000000>; -def IsWriteZA : FlagType<0x40000000000>; -def IsReductionQV : FlagType<0x80000000000>; -def IsStreamingOrSVE2p1 : FlagType<0x80000000000>; // Use for intrinsics that are common between sme/sme2 and sve2p1. +def SplatOperandMask : FlagType<0x00001C00>; +def IsLoad : FlagType<0x00002000>; +def IsStore : FlagType<0x00004000>; +def IsGatherLoad : FlagType<0x00008000>; +def IsScatterStore : FlagType<0x00010000>; +def IsStructLoad : FlagType<0x00020000>; +def IsStructStore : FlagType<0x00040000>; +def IsZExtReturn : FlagType<0x00080000>; // Return value is sign-extend by default +def IsOverloadNone : FlagType<0x00100000>; // Intrinsic does not take any overloaded types. +def IsOverloadWhileOrMultiVecCvt : FlagType<0x00200000>; // Use {default type, typeof(operand1)} as overloaded types. +def IsOverloadWhileRW : FlagType<0x00400000>; // Use {pred(default type), typeof(operand0)} as overloaded types. +def IsOverloadCvt : FlagType<0x00800000>; // Use {typeof(operand0), typeof(last operand)} as overloaded types. +def OverloadKindMask : FlagType<0x00E00000>; // When the masked values are all '0', the default type is used as overload type. +def IsByteIndexed : FlagType<0x01000000>; +def IsAppendSVALL : FlagType<0x02000000>; // Appends SV_ALL as the last operand. +def IsInsertOp1SVALL : FlagType<0x04000000>; // Inserts SV_ALL as the second operand. +def IsPrefetch : FlagType<0x08000000>; // Contiguous prefetches. +def IsGatherPrefetch : FlagType<0x10000000>; +def ReverseCompare : FlagType<0x20000000>; // Compare operands must be swapped. +def ReverseUSDOT : FlagType<0x40000000>; // Unsigned/signed operands must be swapped. +def IsUndef : FlagType<0x80000000>; // Codegen `undef` of given type. +def IsTupleCreate : FlagType<0x100000000>; +def IsTupleGet : FlagType<0x200000000>; +def IsTupleSet : FlagType<0x400000000>; +def ReverseMergeAnyBinOp : FlagType<0x800000000>; // e.g. Implement SUBR_X using SUB_X. +def ReverseMergeAnyAccOp : FlagType<0x1000000000>; // e.g. Implement MSB_X using MLS_X. +def IsStreaming : FlagType<0x2000000000>; +def IsStreamingCompatible : FlagType<0x4000000000>; +def IsReadZA : FlagType<0x8000000000>; +def IsWriteZA : FlagType<0x10000000000>; +def IsReductionQV : FlagType<0x20000000000>; +def IsStreamingOrSVE2p1 : FlagType<0x40000000000>; // Use for intrinsics that are common between sme/sme2 and sve2p1. +def IsInZA : FlagType<0x80000000000>; +def IsOutZA : FlagType<0x100000000000>; +def IsInOutZA : FlagType<0x200000000000>; +def IsInZT0 : FlagType<0x400000000000>; +def IsOutZT0 : FlagType<0x800000000000>; +def IsInOutZT0 : FlagType<0x1000000000000>; // These must be kept in sync with the flags in include/clang/Basic/TargetBuiltins.h class ImmCheckType { diff --git a/clang/include/clang/Basic/riscv_vector.td b/clang/include/clang/Basic/riscv_vector.td index e7d78b03511..8bde0810525 100644 --- a/clang/include/clang/Basic/riscv_vector.td +++ b/clang/include/clang/Basic/riscv_vector.td @@ -117,7 +117,7 @@ multiclass RVVIndexedLoad { defvar eew = eew_list[0]; defvar eew_type = eew_list[1]; let Name = op # eew # "_v", IRName = op, MaskedIRName = op # "_mask", - RequiredFeatures = !if(!eq(type, "x"), ["ZvfhminOrZvfh"], + RequiredFeatures = !if(!eq(type, "x"), ["Zvfhmin"], []) in { def: RVVOutOp1Builtin<"v", "vPCe" # eew_type # "Uv", type>; if !not(IsFloat.val) then { @@ -128,7 +128,7 @@ multiclass RVVIndexedLoad { defvar eew64 = "64"; defvar eew64_type = "(Log2EEW:6)"; let Name = op # eew64 # "_v", IRName = op, MaskedIRName = op # "_mask", - RequiredFeatures = !if(!eq(type, "x"), ["ZvfhminOrZvfh", "RV64"], + RequiredFeatures = !if(!eq(type, "x"), ["Zvfhmin", "RV64"], ["RV64"]) in { def: RVVOutOp1Builtin<"v", "vPCe" # eew64_type # "Uv", type>; if !not(IsFloat.val) then { @@ -222,7 +222,7 @@ multiclass RVVIndexedStore { defvar eew = eew_list[0]; defvar eew_type = eew_list[1]; let Name = op # eew # "_v", IRName = op, MaskedIRName = op # "_mask", - RequiredFeatures = !if(!eq(type, "x"), ["ZvfhminOrZvfh"], + RequiredFeatures = !if(!eq(type, "x"), ["Zvfhmin"], []) in { def : RVVBuiltin<"v", "0Pe" # eew_type # "Uvv", type>; if !not(IsFloat.val) then { @@ -233,7 +233,7 @@ multiclass RVVIndexedStore { defvar eew64 = "64"; defvar eew64_type = "(Log2EEW:6)"; let Name = op # eew64 # "_v", IRName = op, MaskedIRName = op # "_mask", - RequiredFeatures = !if(!eq(type, "x"), ["ZvfhminOrZvfh", "RV64"], + RequiredFeatures = !if(!eq(type, "x"), ["Zvfhmin", "RV64"], ["RV64"]) in { def : RVVBuiltin<"v", "0Pe" # eew64_type # "Uvv", type>; if !not(IsFloat.val) then { @@ -681,7 +681,7 @@ let HasBuiltinAlias = false, def vlm: RVVVLEMaskBuiltin; defm vle8: RVVVLEBuiltin<["c"]>; defm vle16: RVVVLEBuiltin<["s"]>; -let Name = "vle16_v", RequiredFeatures = ["ZvfhminOrZvfh"] in +let Name = "vle16_v", RequiredFeatures = ["Zvfhmin"] in defm vle16_h: RVVVLEBuiltin<["x"]>; defm vle32: RVVVLEBuiltin<["i","f"]>; defm vle64: RVVVLEBuiltin<["l","d"]>; @@ -689,7 +689,7 @@ defm vle64: RVVVLEBuiltin<["l","d"]>; def vsm : RVVVSEMaskBuiltin; defm vse8 : RVVVSEBuiltin<["c"]>; defm vse16: RVVVSEBuiltin<["s"]>; -let Name = "vse16_v", RequiredFeatures = ["ZvfhminOrZvfh"] in +let Name = "vse16_v", RequiredFeatures = ["Zvfhmin"] in defm vse16_h: RVVVSEBuiltin<["x"]>; defm vse32: RVVVSEBuiltin<["i","f"]>; defm vse64: RVVVSEBuiltin<["l","d"]>; @@ -697,14 +697,14 @@ defm vse64: RVVVSEBuiltin<["l","d"]>; // 7.5. Vector Strided Instructions defm vlse8: RVVVLSEBuiltin<["c"]>; defm vlse16: RVVVLSEBuiltin<["s"]>; -let Name = "vlse16_v", RequiredFeatures = ["ZvfhminOrZvfh"] in +let Name = "vlse16_v", RequiredFeatures = ["Zvfhmin"] in defm vlse16_h: RVVVLSEBuiltin<["x"]>; defm vlse32: RVVVLSEBuiltin<["i","f"]>; defm vlse64: RVVVLSEBuiltin<["l","d"]>; defm vsse8 : RVVVSSEBuiltin<["c"]>; defm vsse16: RVVVSSEBuiltin<["s"]>; -let Name = "vsse16_v", RequiredFeatures = ["ZvfhminOrZvfh"] in +let Name = "vsse16_v", RequiredFeatures = ["Zvfhmin"] in defm vsse16_h: RVVVSSEBuiltin<["x"]>; defm vsse32: RVVVSSEBuiltin<["i","f"]>; defm vsse64: RVVVSSEBuiltin<["l","d"]>; @@ -719,7 +719,7 @@ defm : RVVIndexedStore<"vsoxei">; // 7.7. Unit-stride Fault-Only-First Loads defm vle8ff: RVVVLEFFBuiltin<["c"]>; defm vle16ff: RVVVLEFFBuiltin<["s"]>; -let Name = "vle16ff_v", RequiredFeatures = ["ZvfhminOrZvfh"] in +let Name = "vle16ff_v", RequiredFeatures = ["Zvfhmin"] in defm vle16ff: RVVVLEFFBuiltin<["x"]>; defm vle32ff: RVVVLEFFBuiltin<["i", "f"]>; defm vle64ff: RVVVLEFFBuiltin<["l", "d"]>; @@ -738,7 +738,7 @@ multiclass RVVUnitStridedSegLoadTuple { IRName = op # nf, MaskedIRName = op # nf # "_mask", NF = nf, - RequiredFeatures = !if(!eq(type, "x"), ["ZvfhminOrZvfh"], + RequiredFeatures = !if(!eq(type, "x"), ["Zvfhmin"], []), ManualCodegen = [{ { @@ -800,7 +800,7 @@ multiclass RVVUnitStridedSegStoreTuple { MaskedIRName = op # nf # "_mask", NF = nf, HasMaskedOffOperand = false, - RequiredFeatures = !if(!eq(type, "x"), ["ZvfhminOrZvfh"], + RequiredFeatures = !if(!eq(type, "x"), ["Zvfhmin"], []), ManualCodegen = [{ { @@ -852,7 +852,7 @@ multiclass RVVUnitStridedSegLoadFFTuple { IRName = op # nf # "ff", MaskedIRName = op # nf # "ff_mask", NF = nf, - RequiredFeatures = !if(!eq(type, "x"), ["ZvfhminOrZvfh"], + RequiredFeatures = !if(!eq(type, "x"), ["Zvfhmin"], []), ManualCodegen = [{ { @@ -927,7 +927,7 @@ multiclass RVVStridedSegLoadTuple { IRName = op # nf, MaskedIRName = op # nf # "_mask", NF = nf, - RequiredFeatures = !if(!eq(type, "x"), ["ZvfhminOrZvfh"], + RequiredFeatures = !if(!eq(type, "x"), ["Zvfhmin"], []), ManualCodegen = [{ { @@ -991,7 +991,7 @@ multiclass RVVStridedSegStoreTuple { NF = nf, HasMaskedOffOperand = false, MaskedPolicyScheme = NonePolicy, - RequiredFeatures = !if(!eq(type, "x"), ["ZvfhminOrZvfh"], + RequiredFeatures = !if(!eq(type, "x"), ["Zvfhmin"], []), ManualCodegen = [{ { @@ -1040,7 +1040,7 @@ multiclass RVVIndexedSegLoadTuple { IRName = op # nf, MaskedIRName = op # nf # "_mask", NF = nf, - RequiredFeatures = !if(!eq(type, "x"), ["ZvfhminOrZvfh"], + RequiredFeatures = !if(!eq(type, "x"), ["Zvfhmin"], []), ManualCodegen = [{ { @@ -1103,7 +1103,7 @@ multiclass RVVIndexedSegStoreTuple { NF = nf, HasMaskedOffOperand = false, MaskedPolicyScheme = NonePolicy, - RequiredFeatures = !if(!eq(type, "x"), ["ZvfhminOrZvfh"], + RequiredFeatures = !if(!eq(type, "x"), ["Zvfhmin"], []), ManualCodegen = [{ { @@ -1345,7 +1345,7 @@ let HasMasked = false, [["v", "Uv", "UvUv"]]>; defm vmv_v : RVVOutBuiltinSet<"vmv_v_v", "csilfd", [["v", "v", "vv"]]>; - let RequiredFeatures = ["ZvfhminOrZvfh"] in + let RequiredFeatures = ["Zvfhmin"] in defm vmv_v : RVVOutBuiltinSet<"vmv_v_v", "x", [["v", "v", "vv"]]>; let SupportOverloading = false in @@ -1841,7 +1841,7 @@ let HasMasked = false, }] in { defm vmerge : RVVOutOp1BuiltinSet<"vmerge", "fd", [["vvm", "v", "vvvm"]]>; - let RequiredFeatures = ["ZvfhminOrZvfh"] in + let RequiredFeatures = ["Zvfhmin"] in defm vmerge : RVVOutOp1BuiltinSet<"vmerge", "x", [["vvm", "v", "vvvm"]]>; defm vfmerge : RVVOutOp1BuiltinSet<"vfmerge", "xfd", @@ -1869,7 +1869,7 @@ let Log2LMUL = [-3, -2, -1, 0, 1, 2] in { def vfwcvt_f_xu_v : RVVConvBuiltin<"Fw", "FwUv", "csi", "vfwcvt_f">; def vfwcvt_f_x_v : RVVConvBuiltin<"Fw", "Fwv", "csi", "vfwcvt_f">; def vfwcvt_f_f_v : RVVConvBuiltin<"w", "wv", "f", "vfwcvt_f">; - let RequiredFeatures = ["ZvfhminOrZvfh"] in + let RequiredFeatures = ["Zvfhmin"] in def vfwcvt_f_f_v_fp16 : RVVConvBuiltin<"w", "wv", "x", "vfwcvt_f"> { let Name = "vfwcvt_f_f_v"; let IRName = "vfwcvt_f_f_v"; @@ -1966,7 +1966,7 @@ let ManualCodegen = [{ } let OverloadedName = "vfncvt_f" in { defm : RVVConvBuiltinSet<"vfncvt_f_f_w", "f", [["v", "vwu"]]>; - let RequiredFeatures = ["ZvfhminOrZvfh"] in + let RequiredFeatures = ["Zvfhmin"] in defm : RVVConvBuiltinSet<"vfncvt_f_f_w", "x", [["v", "vwu"]]>; } } @@ -2011,7 +2011,7 @@ let ManualCodegen = [{ } let OverloadedName = "vfncvt_f" in { defm : RVVConvBuiltinSet<"vfncvt_f_f_w", "f", [["v", "vw"]]>; - let RequiredFeatures = ["ZvfhminOrZvfh"] in + let RequiredFeatures = ["Zvfhmin"] in defm : RVVConvBuiltinSet<"vfncvt_f_f_w", "x", [["v", "vw"]]>; } } @@ -2271,7 +2271,7 @@ let HasMasked = false, HasVL = false, IRName = "" in { def vreinterpret_u_f : RVVBuiltin<"FvUv", "UvFv", "il", "Uv">; def vreinterpret_f_i : RVVBuiltin<"vFv", "Fvv", "il", "Fv">; def vreinterpret_f_u : RVVBuiltin<"UvFv", "FvUv", "il", "Fv">; - let RequiredFeatures = ["ZvfhminOrZvfh"] in { + let RequiredFeatures = ["Zvfhmin"] in { def vreinterpret_i_h : RVVBuiltin<"Fvv", "vFv", "s", "v">; def vreinterpret_u_h : RVVBuiltin<"FvUv", "UvFv", "s", "Uv">; def vreinterpret_h_i : RVVBuiltin<"vFv", "Fvv", "s", "Fv">; diff --git a/clang/include/clang/Driver/Options.td b/clang/include/clang/Driver/Options.td index 7f97d6b6faa..7f4fa33748f 100644 --- a/clang/include/clang/Driver/Options.td +++ b/clang/include/clang/Driver/Options.td @@ -3459,6 +3459,10 @@ def fopenmp_offload_mandatory : Flag<["-"], "fopenmp-offload-mandatory">, Group< Flags<[NoArgumentUnused]>, Visibility<[ClangOption, CC1Option]>, HelpText<"Do not create a host fallback if offloading to the device fails.">, MarshallingInfoFlag>; +def fopenmp_force_usm : Flag<["-"], "fopenmp-force-usm">, Group, + Flags<[NoArgumentUnused]>, Visibility<[ClangOption, CC1Option]>, + HelpText<"Force behvaior as if the user specified pragma omp requires unified_shared_memory.">, + MarshallingInfoFlag>; def fopenmp_target_jit : Flag<["-"], "fopenmp-target-jit">, Group, Flags<[NoArgumentUnused]>, Visibility<[ClangOption, CLOption]>, HelpText<"Emit code that can be JIT compiled for OpenMP offloading. Implies -foffload-lto=full">; @@ -3664,6 +3668,10 @@ def ftrivial_auto_var_init_stop_after : Joined<["-"], "ftrivial-auto-var-init-st Visibility<[ClangOption, CC1Option, CLOption, DXCOption]>, HelpText<"Stop initializing trivial automatic stack variables after the specified number of instances">, MarshallingInfoInt>; +def ftrivial_auto_var_init_max_size : Joined<["-"], "ftrivial-auto-var-init-max-size=">, Group, + Visibility<[ClangOption, CC1Option, CLOption, DXCOption]>, + HelpText<"Stop initializing trivial automatic stack variables if var size exceeds the specified number of instances (in bytes)">, + MarshallingInfoInt>; def fstandalone_debug : Flag<["-"], "fstandalone-debug">, Group, Visibility<[ClangOption, CLOption, DXCOption]>, HelpText<"Emit full debug info for all types used by the program">; @@ -3858,27 +3866,32 @@ def dA : Flag<["-"], "dA">, Alias; defm visibility_from_dllstorageclass : BoolFOption<"visibility-from-dllstorageclass", LangOpts<"VisibilityFromDLLStorageClass">, DefaultFalse, PosFlag, + "Override the visibility of globals based on their final DLL storage class.">, NegFlag>; +class MarshallingInfoVisibilityFromDLLStorage + : MarshallingInfoEnum, + Values<"keep,hidden,protected,default">, + NormalizedValuesScope<"LangOptions::VisibilityFromDLLStorageClassKinds">, + NormalizedValues<["Keep", "Hidden", "Protected", "Default"]> {} def fvisibility_dllexport_EQ : Joined<["-"], "fvisibility-dllexport=">, Group, Visibility<[ClangOption, CC1Option]>, - HelpText<"The visibility for dllexport definitions [-fvisibility-from-dllstorageclass]">, - MarshallingInfoVisibility, "DefaultVisibility">, + HelpText<"The visibility for dllexport definitions. If Keep is specified the visibility is not adjusted [-fvisibility-from-dllstorageclass]">, + MarshallingInfoVisibilityFromDLLStorage, "Default">, ShouldParseIf; def fvisibility_nodllstorageclass_EQ : Joined<["-"], "fvisibility-nodllstorageclass=">, Group, Visibility<[ClangOption, CC1Option]>, - HelpText<"The visibility for definitions without an explicit DLL export class [-fvisibility-from-dllstorageclass]">, - MarshallingInfoVisibility, "HiddenVisibility">, + HelpText<"The visibility for definitions without an explicit DLL storage class. If Keep is specified the visibility is not adjusted [-fvisibility-from-dllstorageclass]">, + MarshallingInfoVisibilityFromDLLStorage, "Hidden">, ShouldParseIf; def fvisibility_externs_dllimport_EQ : Joined<["-"], "fvisibility-externs-dllimport=">, Group, Visibility<[ClangOption, CC1Option]>, - HelpText<"The visibility for dllimport external declarations [-fvisibility-from-dllstorageclass]">, - MarshallingInfoVisibility, "DefaultVisibility">, + HelpText<"The visibility for dllimport external declarations. If Keep is specified the visibility is not adjusted [-fvisibility-from-dllstorageclass]">, + MarshallingInfoVisibilityFromDLLStorage, "Default">, ShouldParseIf; def fvisibility_externs_nodllstorageclass_EQ : Joined<["-"], "fvisibility-externs-nodllstorageclass=">, Group, Visibility<[ClangOption, CC1Option]>, - HelpText<"The visibility for external declarations without an explicit DLL dllstorageclass [-fvisibility-from-dllstorageclass]">, - MarshallingInfoVisibility, "HiddenVisibility">, + HelpText<"The visibility for external declarations without an explicit DLL storage class. If Keep is specified the visibility is not adjusted [-fvisibility-from-dllstorageclass]">, + MarshallingInfoVisibilityFromDLLStorage, "Hidden">, ShouldParseIf; def fvisibility_EQ : Joined<["-"], "fvisibility=">, Group, Visibility<[ClangOption, CC1Option]>, @@ -3901,9 +3914,16 @@ def fvisibility_ms_compat : Flag<["-"], "fvisibility-ms-compat">, Group HelpText<"Give global types 'default' visibility and global functions and " "variables 'hidden' visibility by default">; def fvisibility_global_new_delete_hidden : Flag<["-"], "fvisibility-global-new-delete-hidden">, Group, - HelpText<"Give global C++ operator new and delete declarations hidden visibility">, + HelpText<"Give global C++ operator new and delete declarations hidden visibility">; +class MarshallingInfoVisibilityGlobalNewDelete + : MarshallingInfoEnum, + Values<"force-default,force-protected,force-hidden,source">, + NormalizedValuesScope<"LangOptions::VisibilityForcedKinds">, + NormalizedValues<["ForceDefault", "ForceProtected", "ForceHidden", "Source"]> {} +def fvisibility_global_new_delete_EQ : Joined<["-"], "fvisibility-global-new-delete=">, Group, Visibility<[ClangOption, CC1Option]>, - MarshallingInfoFlag>; + HelpText<"The visibility for global C++ operator new and delete declarations. If 'source' is specified the visibility is not adjusted">, + MarshallingInfoVisibilityGlobalNewDelete, "ForceDefault">; def mdefault_visibility_export_mapping_EQ : Joined<["-"], "mdefault-visibility-export-mapping=">, Values<"none,explicit,all">, NormalizedValuesScope<"LangOptions::DefaultVisiblityExportMapping">, @@ -4392,8 +4412,8 @@ def mcmodel_EQ : Joined<["-"], "mcmodel=">, Group, Visibility<[ClangOption, CC1Option]>, MarshallingInfoString, [{"default"}]>; def mlarge_data_threshold_EQ : Joined<["-"], "mlarge-data-threshold=">, Group, - Visibility<[ClangOption, CC1Option]>, - MarshallingInfoInt, "65535">; + Flags<[TargetSpecific]>, Visibility<[ClangOption, CC1Option]>, + MarshallingInfoInt, "0">; def mtls_size_EQ : Joined<["-"], "mtls-size=">, Group, Visibility<[ClangOption, CC1Option]>, HelpText<"Specify bit size of immediate TLS offsets (AArch64 ELF only): " @@ -4761,12 +4781,12 @@ defm amdgpu_ieee : BoolOption<"m", "amdgpu-ieee", NegFlag>, Group; def mcode_object_version_EQ : Joined<["-"], "mcode-object-version=">, Group, - HelpText<"Specify code object ABI version. Defaults to 4. (AMDGPU only)">, + HelpText<"Specify code object ABI version. Defaults to 5. (AMDGPU only)">, Visibility<[ClangOption, FlangOption, CC1Option, FC1Option]>, Values<"none,4,5">, NormalizedValuesScope<"llvm::CodeObjectVersionKind">, NormalizedValues<["COV_None", "COV_4", "COV_5"]>, - MarshallingInfoEnum, "COV_4">; + MarshallingInfoEnum, "COV_5">; defm cumode : SimpleMFlag<"cumode", "Specify CU wavefront", "Specify WGP wavefront", @@ -5172,7 +5192,7 @@ def module_file_info : Flag<["-"], "module-file-info">, Flags<[]>, HelpText<"Provide information about a particular module file">; def mthumb : Flag<["-"], "mthumb">, Group; def mtune_EQ : Joined<["-"], "mtune=">, Group, - HelpText<"Only supported on AArch64, PowerPC, RISC-V, SystemZ, and X86">; + HelpText<"Only supported on AArch64, PowerPC, RISC-V, SPARC, SystemZ, and X86">; def multi__module : Flag<["-"], "multi_module">; def multiply__defined__unused : Separate<["-"], "multiply_defined_unused">; def multiply__defined : Separate<["-"], "multiply_defined">; @@ -5307,7 +5327,8 @@ def pthreads : Flag<["-"], "pthreads">; defm pthread : BoolOption<"", "pthread", LangOpts<"POSIXThreads">, DefaultFalse, PosFlag, - NegFlag, BothFlags<[], [ClangOption, CC1Option]>>; + NegFlag, + BothFlags<[], [ClangOption, CC1Option, FlangOption, FC1Option]>>; def pie : Flag<["-"], "pie">, Group; def static_pie : Flag<["-"], "static-pie">, Group; def read__only__relocs : Separate<["-"], "read_only_relocs">; @@ -6043,11 +6064,11 @@ def mapx_features_EQ : CommaJoined<["-"], "mapx-features=">, Group, Values<"egpr,push2pop2,ppx,ndd,ccmp,cf">; def mno_apx_features_EQ : CommaJoined<["-"], "mno-apx-features=">, Group, HelpText<"Disable features of APX">, Values<"egpr,push2pop2,ppx,ndd,ccmp,cf">; -// Features egpr, push2pop2 and ppx are validated with llvm-test-suite && cpu2017 on Intel SDE. +// Features egpr, push2pop2, ppx and ndd are validated with llvm-test-suite && cpu2017 on Intel SDE. // For stability, we turn on these features only for -mapxf. After a feature pass the validation, // we will add it to -mapxf. -def mapxf : Flag<["-"], "mapxf">, Alias, AliasArgs<["egpr","push2pop2","ppx"]>; -def mno_apxf : Flag<["-"], "mno-apxf">, Alias, AliasArgs<["egpr","push2pop2","ppx"]>; +def mapxf : Flag<["-"], "mapxf">, Alias, AliasArgs<["egpr","push2pop2","ppx", "ndd"]>; +def mno_apxf : Flag<["-"], "mno-apxf">, Alias, AliasArgs<["egpr","push2pop2","ppx","ndd"]>; } // let Flags = [TargetSpecific] // VE feature flags @@ -6297,6 +6318,11 @@ def fno_sycl : Flag<["-"], "fno-sycl">, Visibility<[ClangOption, CLOption]>, Group, HelpText<"Disables SYCL kernels compilation for device">; +// OS-specific options +let Flags = [TargetSpecific] in { +defm android_pad_segment : BooleanFFlag<"android-pad-segment">, Group; +} // let Flags = [TargetSpecific] + //===----------------------------------------------------------------------===// // FLangOption + NoXarchOption //===----------------------------------------------------------------------===// @@ -8457,3 +8483,6 @@ def : Option<["/", "-"], "Qembed_debug", KIND_FLAG>, Group, HelpText<"Embed PDB in shader container (ignored)">; def spirv : DXCFlag<"spirv">, HelpText<"Generate SPIR-V code">; +def fspv_target_env_EQ : Joined<["-"], "fspv-target-env=">, Group, + HelpText<"Specify the target environment">, + Values<"vulkan1.2, vulkan1.3">; diff --git a/clang/include/clang/Driver/Types.def b/clang/include/clang/Driver/Types.def index b889883125c..f72c27e1ee7 100644 --- a/clang/include/clang/Driver/Types.def +++ b/clang/include/clang/Driver/Types.def @@ -37,8 +37,10 @@ // C family source language (with and without preprocessing). TYPE("cpp-output", PP_C, INVALID, "i", phases::Compile, phases::Backend, phases::Assemble, phases::Link) TYPE("c", C, PP_C, "c", phases::Preprocess, phases::Compile, phases::Backend, phases::Assemble, phases::Link) -TYPE("cl", CL, PP_C, "cl", phases::Preprocess, phases::Compile, phases::Backend, phases::Assemble, phases::Link) -TYPE("clcpp", CLCXX, PP_CXX, "clcpp", phases::Preprocess, phases::Compile, phases::Backend, phases::Assemble, phases::Link) +TYPE("cl", CL, PP_CL, "cl", phases::Preprocess, phases::Compile, phases::Backend, phases::Assemble, phases::Link) +TYPE("cl-cpp-output", PP_CL, INVALID, "cli", phases::Compile, phases::Backend, phases::Assemble, phases::Link) +TYPE("clcpp", CLCXX, PP_CLCXX, "clcpp", phases::Preprocess, phases::Compile, phases::Backend, phases::Assemble, phases::Link) +TYPE("clcpp-cpp-output", PP_CLCXX, INVALID, "clii", phases::Compile, phases::Backend, phases::Assemble, phases::Link) TYPE("cuda-cpp-output", PP_CUDA, INVALID, "cui", phases::Compile, phases::Backend, phases::Assemble, phases::Link) TYPE("cuda", CUDA, PP_CUDA, "cu", phases::Preprocess, phases::Compile, phases::Backend, phases::Assemble, phases::Link) TYPE("cuda", CUDA_DEVICE, PP_CUDA, "cu", phases::Preprocess, phases::Compile, phases::Backend, phases::Assemble, phases::Link) diff --git a/clang/include/clang/ExtractAPI/API.h b/clang/include/clang/ExtractAPI/API.h index b4c0e0ad39c..0a0f1bd1e95 100644 --- a/clang/include/clang/ExtractAPI/API.h +++ b/clang/include/clang/ExtractAPI/API.h @@ -169,6 +169,7 @@ struct APIRecord { RK_Enum, RK_StructField, RK_Struct, + RK_UnionField, RK_Union, RK_StaticField, RK_CXXField, @@ -224,7 +225,7 @@ struct APIRecord { StringRef USR; StringRef Name; PresumedLoc Location; - AvailabilitySet Availabilities; + AvailabilityInfo Availability; LinkageInfo Linkage; /// Documentation comment lines attached to this symbol declaration. @@ -256,12 +257,12 @@ public: APIRecord() = delete; APIRecord(RecordKind Kind, StringRef USR, StringRef Name, - PresumedLoc Location, AvailabilitySet Availabilities, + PresumedLoc Location, AvailabilityInfo Availability, LinkageInfo Linkage, const DocComment &Comment, DeclarationFragments Declaration, DeclarationFragments SubHeading, bool IsFromSystemHeader) : USR(USR), Name(Name), Location(Location), - Availabilities(std::move(Availabilities)), Linkage(Linkage), + Availability(std::move(Availability)), Linkage(Linkage), Comment(Comment), Declaration(Declaration), SubHeading(SubHeading), IsFromSystemHeader(IsFromSystemHeader), Kind(Kind) {} @@ -274,10 +275,10 @@ public: struct NamespaceRecord : APIRecord { NamespaceRecord(StringRef USR, StringRef Name, PresumedLoc Loc, - AvailabilitySet Availabilities, LinkageInfo Linkage, + AvailabilityInfo Availability, LinkageInfo Linkage, const DocComment &Comment, DeclarationFragments Declaration, DeclarationFragments SubHeading, bool IsFromSystemHeader) - : APIRecord(RK_Namespace, USR, Name, Loc, std::move(Availabilities), + : APIRecord(RK_Namespace, USR, Name, Loc, std::move(Availability), Linkage, Comment, Declaration, SubHeading, IsFromSystemHeader) {} @@ -291,23 +292,23 @@ struct GlobalFunctionRecord : APIRecord { FunctionSignature Signature; GlobalFunctionRecord(StringRef USR, StringRef Name, PresumedLoc Loc, - AvailabilitySet Availabilities, LinkageInfo Linkage, + AvailabilityInfo Availability, LinkageInfo Linkage, const DocComment &Comment, DeclarationFragments Declaration, DeclarationFragments SubHeading, FunctionSignature Signature, bool IsFromSystemHeader) - : APIRecord(RK_GlobalFunction, USR, Name, Loc, std::move(Availabilities), + : APIRecord(RK_GlobalFunction, USR, Name, Loc, std::move(Availability), Linkage, Comment, Declaration, SubHeading, IsFromSystemHeader), Signature(Signature) {} GlobalFunctionRecord(RecordKind Kind, StringRef USR, StringRef Name, - PresumedLoc Loc, AvailabilitySet Availabilities, + PresumedLoc Loc, AvailabilityInfo Availability, LinkageInfo Linkage, const DocComment &Comment, DeclarationFragments Declaration, DeclarationFragments SubHeading, FunctionSignature Signature, bool IsFromSystemHeader) - : APIRecord(Kind, USR, Name, Loc, std::move(Availabilities), Linkage, + : APIRecord(Kind, USR, Name, Loc, std::move(Availability), Linkage, Comment, Declaration, SubHeading, IsFromSystemHeader), Signature(Signature) {} @@ -323,14 +324,14 @@ struct GlobalFunctionTemplateRecord : GlobalFunctionRecord { Template Templ; GlobalFunctionTemplateRecord(StringRef USR, StringRef Name, PresumedLoc Loc, - AvailabilitySet Availabilities, + AvailabilityInfo Availability, LinkageInfo Linkage, const DocComment &Comment, DeclarationFragments Declaration, DeclarationFragments SubHeading, FunctionSignature Signature, Template Template, bool IsFromSystemHeader) : GlobalFunctionRecord(RK_GlobalFunctionTemplate, USR, Name, Loc, - std::move(Availabilities), Linkage, Comment, + std::move(Availability), Linkage, Comment, Declaration, SubHeading, Signature, IsFromSystemHeader), Templ(Template) {} @@ -343,12 +344,12 @@ struct GlobalFunctionTemplateRecord : GlobalFunctionRecord { struct GlobalFunctionTemplateSpecializationRecord : GlobalFunctionRecord { GlobalFunctionTemplateSpecializationRecord( StringRef USR, StringRef Name, PresumedLoc Loc, - AvailabilitySet Availabilities, LinkageInfo Linkage, + AvailabilityInfo Availability, LinkageInfo Linkage, const DocComment &Comment, DeclarationFragments Declaration, DeclarationFragments SubHeading, FunctionSignature Signature, bool IsFromSystemHeader) : GlobalFunctionRecord(RK_GlobalFunctionTemplateSpecialization, USR, Name, - Loc, std::move(Availabilities), Linkage, Comment, + Loc, std::move(Availability), Linkage, Comment, Declaration, SubHeading, Signature, IsFromSystemHeader) {} @@ -360,20 +361,20 @@ struct GlobalFunctionTemplateSpecializationRecord : GlobalFunctionRecord { /// This holds information associated with global functions. struct GlobalVariableRecord : APIRecord { GlobalVariableRecord(StringRef USR, StringRef Name, PresumedLoc Loc, - AvailabilitySet Availabilities, LinkageInfo Linkage, + AvailabilityInfo Availability, LinkageInfo Linkage, const DocComment &Comment, DeclarationFragments Declaration, DeclarationFragments SubHeading, bool IsFromSystemHeader) - : APIRecord(RK_GlobalVariable, USR, Name, Loc, std::move(Availabilities), + : APIRecord(RK_GlobalVariable, USR, Name, Loc, std::move(Availability), Linkage, Comment, Declaration, SubHeading, IsFromSystemHeader) {} GlobalVariableRecord(RecordKind Kind, StringRef USR, StringRef Name, - PresumedLoc Loc, AvailabilitySet Availabilities, + PresumedLoc Loc, AvailabilityInfo Availability, LinkageInfo Linkage, const DocComment &Comment, DeclarationFragments Declaration, DeclarationFragments SubHeading, bool IsFromSystemHeader) - : APIRecord(Kind, USR, Name, Loc, std::move(Availabilities), Linkage, + : APIRecord(Kind, USR, Name, Loc, std::move(Availability), Linkage, Comment, Declaration, SubHeading, IsFromSystemHeader) {} static bool classof(const APIRecord *Record) { @@ -388,13 +389,13 @@ struct GlobalVariableTemplateRecord : GlobalVariableRecord { Template Templ; GlobalVariableTemplateRecord(StringRef USR, StringRef Name, PresumedLoc Loc, - AvailabilitySet Availabilities, + AvailabilityInfo Availability, LinkageInfo Linkage, const DocComment &Comment, DeclarationFragments Declaration, DeclarationFragments SubHeading, class Template Template, bool IsFromSystemHeader) : GlobalVariableRecord(RK_GlobalVariableTemplate, USR, Name, Loc, - std::move(Availabilities), Linkage, Comment, + std::move(Availability), Linkage, Comment, Declaration, SubHeading, IsFromSystemHeader), Templ(Template) {} @@ -406,11 +407,11 @@ struct GlobalVariableTemplateRecord : GlobalVariableRecord { struct GlobalVariableTemplateSpecializationRecord : GlobalVariableRecord { GlobalVariableTemplateSpecializationRecord( StringRef USR, StringRef Name, PresumedLoc Loc, - AvailabilitySet Availabilities, LinkageInfo Linkage, + AvailabilityInfo Availability, LinkageInfo Linkage, const DocComment &Comment, DeclarationFragments Declaration, DeclarationFragments SubHeading, bool IsFromSystemHeader) : GlobalVariableRecord(RK_GlobalVariableTemplateSpecialization, USR, Name, - Loc, std::move(Availabilities), Linkage, Comment, + Loc, std::move(Availability), Linkage, Comment, Declaration, SubHeading, IsFromSystemHeader) {} static bool classof(const APIRecord *Record) { @@ -424,12 +425,12 @@ struct GlobalVariableTemplatePartialSpecializationRecord GlobalVariableTemplatePartialSpecializationRecord( StringRef USR, StringRef Name, PresumedLoc Loc, - AvailabilitySet Availabilities, LinkageInfo Linkage, + AvailabilityInfo Availability, LinkageInfo Linkage, const DocComment &Comment, DeclarationFragments Declaration, DeclarationFragments SubHeading, class Template Template, bool IsFromSystemHeader) : GlobalVariableRecord(RK_GlobalVariableTemplatePartialSpecialization, - USR, Name, Loc, std::move(Availabilities), Linkage, + USR, Name, Loc, std::move(Availability), Linkage, Comment, Declaration, SubHeading, IsFromSystemHeader), Templ(Template) {} @@ -442,10 +443,10 @@ struct GlobalVariableTemplatePartialSpecializationRecord /// This holds information associated with enum constants. struct EnumConstantRecord : APIRecord { EnumConstantRecord(StringRef USR, StringRef Name, PresumedLoc Loc, - AvailabilitySet Availabilities, const DocComment &Comment, + AvailabilityInfo Availability, const DocComment &Comment, DeclarationFragments Declaration, DeclarationFragments SubHeading, bool IsFromSystemHeader) - : APIRecord(RK_EnumConstant, USR, Name, Loc, std::move(Availabilities), + : APIRecord(RK_EnumConstant, USR, Name, Loc, std::move(Availability), LinkageInfo::none(), Comment, Declaration, SubHeading, IsFromSystemHeader) {} @@ -462,10 +463,10 @@ struct EnumRecord : APIRecord { SmallVector> Constants; EnumRecord(StringRef USR, StringRef Name, PresumedLoc Loc, - AvailabilitySet Availabilities, const DocComment &Comment, + AvailabilityInfo Availability, const DocComment &Comment, DeclarationFragments Declaration, DeclarationFragments SubHeading, bool IsFromSystemHeader) - : APIRecord(RK_Enum, USR, Name, Loc, std::move(Availabilities), + : APIRecord(RK_Enum, USR, Name, Loc, std::move(Availability), LinkageInfo::none(), Comment, Declaration, SubHeading, IsFromSystemHeader) {} @@ -478,17 +479,19 @@ private: }; /// This holds information associated with struct fields. -struct StructFieldRecord : APIRecord { - StructFieldRecord(StringRef USR, StringRef Name, PresumedLoc Loc, - AvailabilitySet Availabilities, const DocComment &Comment, +struct RecordFieldRecord : APIRecord { + RecordFieldRecord(StringRef USR, StringRef Name, PresumedLoc Loc, + AvailabilityInfo Availability, const DocComment &Comment, DeclarationFragments Declaration, - DeclarationFragments SubHeading, bool IsFromSystemHeader) - : APIRecord(RK_StructField, USR, Name, Loc, std::move(Availabilities), + DeclarationFragments SubHeading, RecordKind Kind, + bool IsFromSystemHeader) + : APIRecord(Kind, USR, Name, Loc, std::move(Availability), LinkageInfo::none(), Comment, Declaration, SubHeading, IsFromSystemHeader) {} static bool classof(const APIRecord *Record) { - return Record->getKind() == RK_StructField; + return Record->getKind() == RK_StructField || + Record->getKind() == RK_UnionField; } private: @@ -496,19 +499,20 @@ private: }; /// This holds information associated with structs. -struct StructRecord : APIRecord { - SmallVector> Fields; +struct RecordRecord : APIRecord { + SmallVector> Fields; - StructRecord(StringRef USR, StringRef Name, PresumedLoc Loc, - AvailabilitySet Availabilities, const DocComment &Comment, + RecordRecord(StringRef USR, StringRef Name, PresumedLoc Loc, + AvailabilityInfo Availability, const DocComment &Comment, DeclarationFragments Declaration, - DeclarationFragments SubHeading, bool IsFromSystemHeader) - : APIRecord(RK_Struct, USR, Name, Loc, std::move(Availabilities), + DeclarationFragments SubHeading, RecordKind Kind, + bool IsFromSystemHeader) + : APIRecord(Kind, USR, Name, Loc, std::move(Availability), LinkageInfo::none(), Comment, Declaration, SubHeading, IsFromSystemHeader) {} static bool classof(const APIRecord *Record) { - return Record->getKind() == RK_Struct; + return Record->getKind() == RK_Struct || Record->getKind() == RK_Union; } private: @@ -519,21 +523,21 @@ struct CXXFieldRecord : APIRecord { AccessControl Access; CXXFieldRecord(StringRef USR, StringRef Name, PresumedLoc Loc, - AvailabilitySet Availabilities, const DocComment &Comment, + AvailabilityInfo Availability, const DocComment &Comment, DeclarationFragments Declaration, DeclarationFragments SubHeading, AccessControl Access, bool IsFromSystemHeader) - : APIRecord(RK_CXXField, USR, Name, Loc, std::move(Availabilities), + : APIRecord(RK_CXXField, USR, Name, Loc, std::move(Availability), LinkageInfo::none(), Comment, Declaration, SubHeading, IsFromSystemHeader), Access(Access) {} CXXFieldRecord(RecordKind Kind, StringRef USR, StringRef Name, - PresumedLoc Loc, AvailabilitySet Availabilities, + PresumedLoc Loc, AvailabilityInfo Availability, const DocComment &Comment, DeclarationFragments Declaration, DeclarationFragments SubHeading, AccessControl Access, bool IsFromSystemHeader) - : APIRecord(Kind, USR, Name, Loc, std::move(Availabilities), + : APIRecord(Kind, USR, Name, Loc, std::move(Availability), LinkageInfo::none(), Comment, Declaration, SubHeading, IsFromSystemHeader), Access(Access) {} @@ -550,13 +554,13 @@ struct CXXFieldTemplateRecord : CXXFieldRecord { Template Templ; CXXFieldTemplateRecord(StringRef USR, StringRef Name, PresumedLoc Loc, - AvailabilitySet Availabilities, + AvailabilityInfo Availability, const DocComment &Comment, DeclarationFragments Declaration, DeclarationFragments SubHeading, AccessControl Access, Template Template, bool IsFromSystemHeader) : CXXFieldRecord(RK_CXXFieldTemplate, USR, Name, Loc, - std::move(Availabilities), Comment, Declaration, + std::move(Availability), Comment, Declaration, SubHeading, Access, IsFromSystemHeader), Templ(Template) {} @@ -572,11 +576,11 @@ struct CXXMethodRecord : APIRecord { CXXMethodRecord() = delete; CXXMethodRecord(RecordKind Kind, StringRef USR, StringRef Name, - PresumedLoc Loc, AvailabilitySet Availabilities, + PresumedLoc Loc, AvailabilityInfo Availability, const DocComment &Comment, DeclarationFragments Declaration, DeclarationFragments SubHeading, FunctionSignature Signature, AccessControl Access, bool IsFromSystemHeader) - : APIRecord(Kind, USR, Name, Loc, std::move(Availabilities), + : APIRecord(Kind, USR, Name, Loc, std::move(Availability), LinkageInfo::none(), Comment, Declaration, SubHeading, IsFromSystemHeader), Signature(Signature), Access(Access) {} @@ -586,14 +590,13 @@ struct CXXMethodRecord : APIRecord { struct CXXConstructorRecord : CXXMethodRecord { CXXConstructorRecord(StringRef USR, StringRef Name, PresumedLoc Loc, - AvailabilitySet Availabilities, - const DocComment &Comment, + AvailabilityInfo Availability, const DocComment &Comment, DeclarationFragments Declaration, DeclarationFragments SubHeading, FunctionSignature Signature, AccessControl Access, bool IsFromSystemHeader) : CXXMethodRecord(RK_CXXConstructorMethod, USR, Name, Loc, - std::move(Availabilities), Comment, Declaration, + std::move(Availability), Comment, Declaration, SubHeading, Signature, Access, IsFromSystemHeader) {} static bool classof(const APIRecord *Record) { return Record->getKind() == RK_CXXConstructorMethod; @@ -605,13 +608,13 @@ private: struct CXXDestructorRecord : CXXMethodRecord { CXXDestructorRecord(StringRef USR, StringRef Name, PresumedLoc Loc, - AvailabilitySet Availabilities, const DocComment &Comment, + AvailabilityInfo Availability, const DocComment &Comment, DeclarationFragments Declaration, DeclarationFragments SubHeading, FunctionSignature Signature, AccessControl Access, bool IsFromSystemHeader) : CXXMethodRecord(RK_CXXDestructorMethod, USR, Name, Loc, - std::move(Availabilities), Comment, Declaration, + std::move(Availability), Comment, Declaration, SubHeading, Signature, Access, IsFromSystemHeader) {} static bool classof(const APIRecord *Record) { return Record->getKind() == RK_CXXDestructorMethod; @@ -623,14 +626,14 @@ private: struct CXXStaticMethodRecord : CXXMethodRecord { CXXStaticMethodRecord(StringRef USR, StringRef Name, PresumedLoc Loc, - AvailabilitySet Availabilities, + AvailabilityInfo Availability, const DocComment &Comment, DeclarationFragments Declaration, DeclarationFragments SubHeading, FunctionSignature Signature, AccessControl Access, bool IsFromSystemHeader) : CXXMethodRecord(RK_CXXStaticMethod, USR, Name, Loc, - std::move(Availabilities), Comment, Declaration, + std::move(Availability), Comment, Declaration, SubHeading, Signature, Access, IsFromSystemHeader) {} static bool classof(const APIRecord *Record) { return Record->getKind() == RK_CXXStaticMethod; @@ -642,14 +645,14 @@ private: struct CXXInstanceMethodRecord : CXXMethodRecord { CXXInstanceMethodRecord(StringRef USR, StringRef Name, PresumedLoc Loc, - AvailabilitySet Availabilities, + AvailabilityInfo Availability, const DocComment &Comment, DeclarationFragments Declaration, DeclarationFragments SubHeading, FunctionSignature Signature, AccessControl Access, bool IsFromSystemHeader) : CXXMethodRecord(RK_CXXInstanceMethod, USR, Name, Loc, - std::move(Availabilities), Comment, Declaration, + std::move(Availability), Comment, Declaration, SubHeading, Signature, Access, IsFromSystemHeader) {} static bool classof(const APIRecord *Record) { @@ -664,14 +667,14 @@ struct CXXMethodTemplateRecord : CXXMethodRecord { Template Templ; CXXMethodTemplateRecord(StringRef USR, StringRef Name, PresumedLoc Loc, - AvailabilitySet Availabilities, + AvailabilityInfo Availability, const DocComment &Comment, DeclarationFragments Declaration, DeclarationFragments SubHeading, FunctionSignature Signature, AccessControl Access, Template Template, bool IsFromSystemHeader) : CXXMethodRecord(RK_CXXMethodTemplate, USR, Name, Loc, - std::move(Availabilities), Comment, Declaration, + std::move(Availability), Comment, Declaration, SubHeading, Signature, Access, IsFromSystemHeader), Templ(Template) {} @@ -683,12 +686,12 @@ struct CXXMethodTemplateRecord : CXXMethodRecord { struct CXXMethodTemplateSpecializationRecord : CXXMethodRecord { CXXMethodTemplateSpecializationRecord( StringRef USR, StringRef Name, PresumedLoc Loc, - AvailabilitySet Availabilities, const DocComment &Comment, + AvailabilityInfo Availability, const DocComment &Comment, DeclarationFragments Declaration, DeclarationFragments SubHeading, FunctionSignature Signature, AccessControl Access, bool IsFromSystemHeader) : CXXMethodRecord(RK_CXXMethodTemplateSpecialization, USR, Name, Loc, - std::move(Availabilities), Comment, Declaration, + std::move(Availability), Comment, Declaration, SubHeading, Signature, Access, IsFromSystemHeader) {} static bool classof(const APIRecord *Record) { @@ -711,13 +714,13 @@ struct ObjCPropertyRecord : APIRecord { bool IsOptional; ObjCPropertyRecord(RecordKind Kind, StringRef USR, StringRef Name, - PresumedLoc Loc, AvailabilitySet Availabilities, + PresumedLoc Loc, AvailabilityInfo Availability, const DocComment &Comment, DeclarationFragments Declaration, DeclarationFragments SubHeading, AttributeKind Attributes, StringRef GetterName, StringRef SetterName, bool IsOptional, bool IsFromSystemHeader) - : APIRecord(Kind, USR, Name, Loc, std::move(Availabilities), + : APIRecord(Kind, USR, Name, Loc, std::move(Availability), LinkageInfo::none(), Comment, Declaration, SubHeading, IsFromSystemHeader), Attributes(Attributes), GetterName(GetterName), SetterName(SetterName), @@ -731,7 +734,7 @@ struct ObjCPropertyRecord : APIRecord { struct ObjCInstancePropertyRecord : ObjCPropertyRecord { ObjCInstancePropertyRecord(StringRef USR, StringRef Name, PresumedLoc Loc, - AvailabilitySet Availabilities, + AvailabilityInfo Availability, const DocComment &Comment, DeclarationFragments Declaration, DeclarationFragments SubHeading, @@ -739,7 +742,7 @@ struct ObjCInstancePropertyRecord : ObjCPropertyRecord { StringRef SetterName, bool IsOptional, bool IsFromSystemHeader) : ObjCPropertyRecord(RK_ObjCInstanceProperty, USR, Name, Loc, - std::move(Availabilities), Comment, Declaration, + std::move(Availability), Comment, Declaration, SubHeading, Attributes, GetterName, SetterName, IsOptional, IsFromSystemHeader) {} @@ -753,7 +756,7 @@ private: struct ObjCClassPropertyRecord : ObjCPropertyRecord { ObjCClassPropertyRecord(StringRef USR, StringRef Name, PresumedLoc Loc, - AvailabilitySet Availabilities, + AvailabilityInfo Availability, const DocComment &Comment, DeclarationFragments Declaration, DeclarationFragments SubHeading, @@ -761,7 +764,7 @@ struct ObjCClassPropertyRecord : ObjCPropertyRecord { StringRef SetterName, bool IsOptional, bool IsFromSystemHeader) : ObjCPropertyRecord(RK_ObjCClassProperty, USR, Name, Loc, - std::move(Availabilities), Comment, Declaration, + std::move(Availability), Comment, Declaration, SubHeading, Attributes, GetterName, SetterName, IsOptional, IsFromSystemHeader) {} @@ -779,12 +782,12 @@ struct ObjCInstanceVariableRecord : APIRecord { AccessControl Access; ObjCInstanceVariableRecord(StringRef USR, StringRef Name, PresumedLoc Loc, - AvailabilitySet Availabilities, + AvailabilityInfo Availability, const DocComment &Comment, DeclarationFragments Declaration, DeclarationFragments SubHeading, AccessControl Access, bool IsFromSystemHeader) - : APIRecord(RK_ObjCIvar, USR, Name, Loc, std::move(Availabilities), + : APIRecord(RK_ObjCIvar, USR, Name, Loc, std::move(Availability), LinkageInfo::none(), Comment, Declaration, SubHeading, IsFromSystemHeader), Access(Access) {} @@ -804,11 +807,11 @@ struct ObjCMethodRecord : APIRecord { ObjCMethodRecord() = delete; ObjCMethodRecord(RecordKind Kind, StringRef USR, StringRef Name, - PresumedLoc Loc, AvailabilitySet Availabilities, + PresumedLoc Loc, AvailabilityInfo Availability, const DocComment &Comment, DeclarationFragments Declaration, DeclarationFragments SubHeading, FunctionSignature Signature, bool IsFromSystemHeader) - : APIRecord(Kind, USR, Name, Loc, std::move(Availabilities), + : APIRecord(Kind, USR, Name, Loc, std::move(Availability), LinkageInfo::none(), Comment, Declaration, SubHeading, IsFromSystemHeader), Signature(Signature) {} @@ -818,13 +821,13 @@ struct ObjCMethodRecord : APIRecord { struct ObjCInstanceMethodRecord : ObjCMethodRecord { ObjCInstanceMethodRecord(StringRef USR, StringRef Name, PresumedLoc Loc, - AvailabilitySet Availabilities, + AvailabilityInfo Availability, const DocComment &Comment, DeclarationFragments Declaration, DeclarationFragments SubHeading, FunctionSignature Signature, bool IsFromSystemHeader) : ObjCMethodRecord(RK_ObjCInstanceMethod, USR, Name, Loc, - std::move(Availabilities), Comment, Declaration, + std::move(Availability), Comment, Declaration, SubHeading, Signature, IsFromSystemHeader) {} static bool classof(const APIRecord *Record) { return Record->getKind() == RK_ObjCInstanceMethod; @@ -836,13 +839,13 @@ private: struct ObjCClassMethodRecord : ObjCMethodRecord { ObjCClassMethodRecord(StringRef USR, StringRef Name, PresumedLoc Loc, - AvailabilitySet Availabilities, + AvailabilityInfo Availability, const DocComment &Comment, DeclarationFragments Declaration, DeclarationFragments SubHeading, FunctionSignature Signature, bool IsFromSystemHeader) : ObjCMethodRecord(RK_ObjCClassMethod, USR, Name, Loc, - std::move(Availabilities), Comment, Declaration, + std::move(Availability), Comment, Declaration, SubHeading, Signature, IsFromSystemHeader) {} static bool classof(const APIRecord *Record) { @@ -880,13 +883,13 @@ struct StaticFieldRecord : CXXFieldRecord { SymbolReference Context; StaticFieldRecord(StringRef USR, StringRef Name, PresumedLoc Loc, - AvailabilitySet Availabilities, LinkageInfo Linkage, + AvailabilityInfo Availability, LinkageInfo Linkage, const DocComment &Comment, DeclarationFragments Declaration, DeclarationFragments SubHeading, SymbolReference Context, AccessControl Access, bool IsFromSystemHeader) - : CXXFieldRecord(RK_StaticField, USR, Name, Loc, - std::move(Availabilities), Comment, Declaration, - SubHeading, Access, IsFromSystemHeader), + : CXXFieldRecord(RK_StaticField, USR, Name, Loc, std::move(Availability), + Comment, Declaration, SubHeading, Access, + IsFromSystemHeader), Context(Context) {} static bool classof(const APIRecord *Record) { @@ -905,11 +908,11 @@ struct ObjCContainerRecord : APIRecord { ObjCContainerRecord() = delete; ObjCContainerRecord(RecordKind Kind, StringRef USR, StringRef Name, - PresumedLoc Loc, AvailabilitySet Availabilities, + PresumedLoc Loc, AvailabilityInfo Availability, LinkageInfo Linkage, const DocComment &Comment, DeclarationFragments Declaration, DeclarationFragments SubHeading, bool IsFromSystemHeader) - : APIRecord(Kind, USR, Name, Loc, std::move(Availabilities), Linkage, + : APIRecord(Kind, USR, Name, Loc, std::move(Availability), Linkage, Comment, Declaration, SubHeading, IsFromSystemHeader) {} virtual ~ObjCContainerRecord() = 0; @@ -922,11 +925,11 @@ struct CXXClassRecord : APIRecord { AccessControl Access; CXXClassRecord(StringRef USR, StringRef Name, PresumedLoc Loc, - AvailabilitySet Availabilities, const DocComment &Comment, + AvailabilityInfo Availability, const DocComment &Comment, DeclarationFragments Declaration, DeclarationFragments SubHeading, RecordKind Kind, AccessControl Access, bool IsFromSystemHeader) - : APIRecord(Kind, USR, Name, Loc, std::move(Availabilities), + : APIRecord(Kind, USR, Name, Loc, std::move(Availability), LinkageInfo::none(), Comment, Declaration, SubHeading, IsFromSystemHeader), Access(Access) {} @@ -943,11 +946,11 @@ struct ClassTemplateRecord : CXXClassRecord { Template Templ; ClassTemplateRecord(StringRef USR, StringRef Name, PresumedLoc Loc, - AvailabilitySet Availabilities, const DocComment &Comment, + AvailabilityInfo Availability, const DocComment &Comment, DeclarationFragments Declaration, DeclarationFragments SubHeading, Template Template, AccessControl Access, bool IsFromSystemHeader) - : CXXClassRecord(USR, Name, Loc, std::move(Availabilities), Comment, + : CXXClassRecord(USR, Name, Loc, std::move(Availability), Comment, Declaration, SubHeading, RK_ClassTemplate, Access, IsFromSystemHeader), Templ(Template) {} @@ -960,10 +963,10 @@ struct ClassTemplateRecord : CXXClassRecord { struct ClassTemplateSpecializationRecord : CXXClassRecord { ClassTemplateSpecializationRecord( StringRef USR, StringRef Name, PresumedLoc Loc, - AvailabilitySet Availabilities, const DocComment &Comment, + AvailabilityInfo Availability, const DocComment &Comment, DeclarationFragments Declaration, DeclarationFragments SubHeading, AccessControl Access, bool IsFromSystemHeader) - : CXXClassRecord(USR, Name, Loc, std::move(Availabilities), Comment, + : CXXClassRecord(USR, Name, Loc, std::move(Availability), Comment, Declaration, SubHeading, RK_ClassTemplateSpecialization, Access, IsFromSystemHeader) {} @@ -976,10 +979,10 @@ struct ClassTemplatePartialSpecializationRecord : CXXClassRecord { Template Templ; ClassTemplatePartialSpecializationRecord( StringRef USR, StringRef Name, PresumedLoc Loc, - AvailabilitySet Availabilities, const DocComment &Comment, + AvailabilityInfo Availability, const DocComment &Comment, DeclarationFragments Declaration, DeclarationFragments SubHeading, Template Template, AccessControl Access, bool IsFromSystemHeader) - : CXXClassRecord(USR, Name, Loc, std::move(Availabilities), Comment, + : CXXClassRecord(USR, Name, Loc, std::move(Availability), Comment, Declaration, SubHeading, RK_ClassTemplateSpecialization, Access, IsFromSystemHeader), Templ(Template) {} @@ -993,11 +996,11 @@ struct ConceptRecord : APIRecord { Template Templ; ConceptRecord(StringRef USR, StringRef Name, PresumedLoc Loc, - AvailabilitySet Availabilities, const DocComment &Comment, + AvailabilityInfo Availability, const DocComment &Comment, DeclarationFragments Declaration, DeclarationFragments SubHeading, Template Template, bool IsFromSystemHeader) - : APIRecord(RK_Concept, USR, Name, Loc, std::move(Availabilities), + : APIRecord(RK_Concept, USR, Name, Loc, std::move(Availability), LinkageInfo::none(), Comment, Declaration, SubHeading, IsFromSystemHeader), Templ(Template) {} @@ -1010,12 +1013,12 @@ struct ObjCCategoryRecord : ObjCContainerRecord { bool IsFromExternalModule = false; ObjCCategoryRecord(StringRef USR, StringRef Name, PresumedLoc Loc, - AvailabilitySet Availabilities, const DocComment &Comment, + AvailabilityInfo Availability, const DocComment &Comment, DeclarationFragments Declaration, DeclarationFragments SubHeading, SymbolReference Interface, bool IsFromSystemHeader) : ObjCContainerRecord(RK_ObjCCategory, USR, Name, Loc, - std::move(Availabilities), LinkageInfo::none(), + std::move(Availability), LinkageInfo::none(), Comment, Declaration, SubHeading, IsFromSystemHeader), Interface(Interface) {} @@ -1035,13 +1038,13 @@ struct ObjCInterfaceRecord : ObjCContainerRecord { SmallVector Categories; ObjCInterfaceRecord(StringRef USR, StringRef Name, PresumedLoc Loc, - AvailabilitySet Availabilities, LinkageInfo Linkage, + AvailabilityInfo Availability, LinkageInfo Linkage, const DocComment &Comment, DeclarationFragments Declaration, DeclarationFragments SubHeading, SymbolReference SuperClass, bool IsFromSystemHeader) : ObjCContainerRecord(RK_ObjCInterface, USR, Name, Loc, - std::move(Availabilities), Linkage, Comment, + std::move(Availability), Linkage, Comment, Declaration, SubHeading, IsFromSystemHeader), SuperClass(SuperClass) {} @@ -1056,11 +1059,11 @@ private: /// This holds information associated with Objective-C protocols. struct ObjCProtocolRecord : ObjCContainerRecord { ObjCProtocolRecord(StringRef USR, StringRef Name, PresumedLoc Loc, - AvailabilitySet Availabilities, const DocComment &Comment, + AvailabilityInfo Availability, const DocComment &Comment, DeclarationFragments Declaration, DeclarationFragments SubHeading, bool IsFromSystemHeader) : ObjCContainerRecord(RK_ObjCProtocol, USR, Name, Loc, - std::move(Availabilities), LinkageInfo::none(), + std::move(Availability), LinkageInfo::none(), Comment, Declaration, SubHeading, IsFromSystemHeader) {} @@ -1078,7 +1081,7 @@ struct MacroDefinitionRecord : APIRecord { DeclarationFragments Declaration, DeclarationFragments SubHeading, bool IsFromSystemHeader) - : APIRecord(RK_MacroDefinition, USR, Name, Loc, AvailabilitySet(), + : APIRecord(RK_MacroDefinition, USR, Name, Loc, AvailabilityInfo(), LinkageInfo(), {}, Declaration, SubHeading, IsFromSystemHeader) {} @@ -1099,11 +1102,11 @@ struct TypedefRecord : APIRecord { SymbolReference UnderlyingType; TypedefRecord(StringRef USR, StringRef Name, PresumedLoc Loc, - AvailabilitySet Availabilities, const DocComment &Comment, + AvailabilityInfo Availability, const DocComment &Comment, DeclarationFragments Declaration, DeclarationFragments SubHeading, SymbolReference UnderlyingType, bool IsFromSystemHeader) - : APIRecord(RK_Typedef, USR, Name, Loc, std::move(Availabilities), + : APIRecord(RK_Typedef, USR, Name, Loc, std::move(Availability), LinkageInfo(), Comment, Declaration, SubHeading, IsFromSystemHeader), UnderlyingType(UnderlyingType) {} @@ -1191,7 +1194,7 @@ class APISet { public: NamespaceRecord *addNamespace(APIRecord *Parent, StringRef Name, StringRef USR, PresumedLoc Loc, - AvailabilitySet Availability, + AvailabilityInfo Availability, LinkageInfo Linkage, const DocComment &Comment, DeclarationFragments Declaration, DeclarationFragments SubHeading, @@ -1204,13 +1207,13 @@ public: /// to generate the USR for \c D and keep it alive in APISet. GlobalVariableRecord * addGlobalVar(StringRef Name, StringRef USR, PresumedLoc Loc, - AvailabilitySet Availability, LinkageInfo Linkage, + AvailabilityInfo Availability, LinkageInfo Linkage, const DocComment &Comment, DeclarationFragments Declaration, DeclarationFragments SubHeadin, bool IsFromSystemHeaderg); GlobalVariableTemplateRecord * addGlobalVariableTemplate(StringRef Name, StringRef USR, PresumedLoc Loc, - AvailabilitySet Availability, LinkageInfo Linkage, + AvailabilityInfo Availability, LinkageInfo Linkage, const DocComment &Comment, DeclarationFragments Declaration, DeclarationFragments SubHeading, Template Template, @@ -1224,14 +1227,14 @@ public: /// to generate the USR for \c D and keep it alive in APISet. GlobalFunctionRecord * addGlobalFunction(StringRef Name, StringRef USR, PresumedLoc Loc, - AvailabilitySet Availability, LinkageInfo Linkage, + AvailabilityInfo Availability, LinkageInfo Linkage, const DocComment &Comment, DeclarationFragments Declaration, DeclarationFragments SubHeading, FunctionSignature Signature, bool IsFromSystemHeader); GlobalFunctionTemplateRecord *addGlobalFunctionTemplate( StringRef Name, StringRef USR, PresumedLoc Loc, - AvailabilitySet Availability, LinkageInfo Linkage, + AvailabilityInfo Availability, LinkageInfo Linkage, const DocComment &Comment, DeclarationFragments Declaration, DeclarationFragments SubHeading, FunctionSignature Signature, Template Template, bool IsFromSystemHeader); @@ -1239,7 +1242,7 @@ public: GlobalFunctionTemplateSpecializationRecord * addGlobalFunctionTemplateSpecialization( StringRef Name, StringRef USR, PresumedLoc Loc, - AvailabilitySet Availability, LinkageInfo Linkage, + AvailabilityInfo Availability, LinkageInfo Linkage, const DocComment &Comment, DeclarationFragments Declaration, DeclarationFragments SubHeading, FunctionSignature Signature, bool IsFromSystemHeader); @@ -1252,7 +1255,7 @@ public: /// to generate the USR for \c D and keep it alive in APISet. EnumConstantRecord * addEnumConstant(EnumRecord *Enum, StringRef Name, StringRef USR, - PresumedLoc Loc, AvailabilitySet Availability, + PresumedLoc Loc, AvailabilityInfo Availability, const DocComment &Comment, DeclarationFragments Declaration, DeclarationFragments SubHeading, bool IsFromSystemHeader); @@ -1263,45 +1266,46 @@ public: /// APISet itself, and APISet::recordUSR(const Decl *D) is a helper method /// to generate the USR for \c D and keep it alive in APISet. EnumRecord *addEnum(StringRef Name, StringRef USR, PresumedLoc Loc, - AvailabilitySet Availability, const DocComment &Comment, + AvailabilityInfo Availability, const DocComment &Comment, DeclarationFragments Declaration, DeclarationFragments SubHeading, bool IsFromSystemHeader); - /// Create and add a struct field record into the API set. + /// Create and add a record field record into the API set. /// /// Note: the caller is responsible for keeping the StringRef \p Name and /// \p USR alive. APISet::copyString provides a way to copy strings into /// APISet itself, and APISet::recordUSR(const Decl *D) is a helper method /// to generate the USR for \c D and keep it alive in APISet. - StructFieldRecord * - addStructField(StructRecord *Struct, StringRef Name, StringRef USR, - PresumedLoc Loc, AvailabilitySet Availability, + RecordFieldRecord * + addRecordField(RecordRecord *Record, StringRef Name, StringRef USR, + PresumedLoc Loc, AvailabilityInfo Availability, const DocComment &Comment, DeclarationFragments Declaration, - DeclarationFragments SubHeading, bool IsFromSystemHeader); + DeclarationFragments SubHeading, APIRecord::RecordKind Kind, + bool IsFromSystemHeader); - /// Create and add a struct record into the API set. + /// Create and add a record record into the API set. /// /// Note: the caller is responsible for keeping the StringRef \p Name and /// \p USR alive. APISet::copyString provides a way to copy strings into /// APISet itself, and APISet::recordUSR(const Decl *D) is a helper method /// to generate the USR for \c D and keep it alive in APISet. - StructRecord *addStruct(StringRef Name, StringRef USR, PresumedLoc Loc, - AvailabilitySet Availability, + RecordRecord *addRecord(StringRef Name, StringRef USR, PresumedLoc Loc, + AvailabilityInfo Availability, const DocComment &Comment, DeclarationFragments Declaration, DeclarationFragments SubHeading, - bool IsFromSystemHeader); + APIRecord::RecordKind Kind, bool IsFromSystemHeader); StaticFieldRecord * addStaticField(StringRef Name, StringRef USR, PresumedLoc Loc, - AvailabilitySet Availabilities, LinkageInfo Linkage, + AvailabilityInfo Availability, LinkageInfo Linkage, const DocComment &Comment, DeclarationFragments Declaration, DeclarationFragments SubHeading, SymbolReference Context, AccessControl Access, bool IsFromSystemHeaderg); CXXFieldRecord *addCXXField(APIRecord *CXXClass, StringRef Name, StringRef USR, PresumedLoc Loc, - AvailabilitySet Availabilities, + AvailabilityInfo Availability, const DocComment &Comment, DeclarationFragments Declaration, DeclarationFragments SubHeading, @@ -1309,12 +1313,12 @@ public: CXXFieldTemplateRecord *addCXXFieldTemplate( APIRecord *Parent, StringRef Name, StringRef USR, PresumedLoc Loc, - AvailabilitySet Availability, const DocComment &Comment, + AvailabilityInfo Availability, const DocComment &Comment, DeclarationFragments Declaration, DeclarationFragments SubHeading, AccessControl Access, Template Template, bool IsFromSystemHeader); CXXClassRecord *addCXXClass(APIRecord *Parent, StringRef Name, StringRef USR, - PresumedLoc Loc, AvailabilitySet Availability, + PresumedLoc Loc, AvailabilityInfo Availability, const DocComment &Comment, DeclarationFragments Declaration, DeclarationFragments SubHeading, @@ -1323,76 +1327,76 @@ public: ClassTemplateRecord * addClassTemplate(APIRecord *Parent, StringRef Name, StringRef USR, - PresumedLoc Loc, AvailabilitySet Availability, + PresumedLoc Loc, AvailabilityInfo Availability, const DocComment &Comment, DeclarationFragments Declaration, DeclarationFragments SubHeading, Template Template, AccessControl Access, bool IsFromSystemHeader); ClassTemplateSpecializationRecord *addClassTemplateSpecialization( APIRecord *Parent, StringRef Name, StringRef USR, PresumedLoc Loc, - AvailabilitySet Availability, const DocComment &Comment, + AvailabilityInfo Availability, const DocComment &Comment, DeclarationFragments Declaration, DeclarationFragments SubHeading, AccessControl Access, bool IsFromSystemHeader); ClassTemplatePartialSpecializationRecord * addClassTemplatePartialSpecialization( APIRecord *Parent, StringRef Name, StringRef USR, PresumedLoc Loc, - AvailabilitySet Availability, const DocComment &Comment, + AvailabilityInfo Availability, const DocComment &Comment, DeclarationFragments Declaration, DeclarationFragments SubHeading, Template Template, AccessControl Access, bool IsFromSystemHeader); GlobalVariableTemplateSpecializationRecord * addGlobalVariableTemplateSpecialization( StringRef Name, StringRef USR, PresumedLoc Loc, - AvailabilitySet Availability, LinkageInfo Linkage, + AvailabilityInfo Availability, LinkageInfo Linkage, const DocComment &Comment, DeclarationFragments Declaration, DeclarationFragments SubHeading, bool IsFromSystemHeader); GlobalVariableTemplatePartialSpecializationRecord * addGlobalVariableTemplatePartialSpecialization( StringRef Name, StringRef USR, PresumedLoc Loc, - AvailabilitySet Availability, LinkageInfo Linkage, + AvailabilityInfo Availability, LinkageInfo Linkage, const DocComment &Comment, DeclarationFragments Declaration, DeclarationFragments SubHeading, Template Template, bool IsFromSystemHeader); CXXMethodRecord *addCXXInstanceMethod( APIRecord *Parent, StringRef Name, StringRef USR, PresumedLoc Loc, - AvailabilitySet Availability, const DocComment &Comment, + AvailabilityInfo Availability, const DocComment &Comment, DeclarationFragments Declaration, DeclarationFragments SubHeading, FunctionSignature Signature, AccessControl Access, bool IsFromSystemHeader); CXXMethodRecord *addCXXStaticMethod( APIRecord *Parent, StringRef Name, StringRef USR, PresumedLoc Loc, - AvailabilitySet Availability, const DocComment &Comment, + AvailabilityInfo Availability, const DocComment &Comment, DeclarationFragments Declaration, DeclarationFragments SubHeading, FunctionSignature Signature, AccessControl Access, bool IsFromSystemHeader); CXXMethodRecord *addCXXSpecialMethod( APIRecord *Parent, StringRef Name, StringRef USR, PresumedLoc Loc, - AvailabilitySet Availability, const DocComment &Comment, + AvailabilityInfo Availability, const DocComment &Comment, DeclarationFragments Declaration, DeclarationFragments SubHeading, FunctionSignature Signature, AccessControl Access, bool IsFromSystemHeader); CXXMethodTemplateRecord *addCXXMethodTemplate( APIRecord *Parent, StringRef Name, StringRef USR, PresumedLoc Loc, - AvailabilitySet Availability, const DocComment &Comment, + AvailabilityInfo Availability, const DocComment &Comment, DeclarationFragments Declaration, DeclarationFragments SubHeading, FunctionSignature Signature, AccessControl Access, Template Template, bool IsFromSystemHeader); CXXMethodTemplateSpecializationRecord *addCXXMethodTemplateSpec( APIRecord *Parent, StringRef Name, StringRef USR, PresumedLoc Loc, - AvailabilitySet Availability, const DocComment &Comment, + AvailabilityInfo Availability, const DocComment &Comment, DeclarationFragments Declaration, DeclarationFragments SubHeading, FunctionSignature Signature, AccessControl Access, bool IsFromSystemHeader); ConceptRecord *addConcept(StringRef Name, StringRef USR, PresumedLoc Loc, - AvailabilitySet Availability, + AvailabilityInfo Availability, const DocComment &Comment, DeclarationFragments Declaration, DeclarationFragments SubHeading, Template Template, @@ -1406,7 +1410,7 @@ public: /// to generate the USR for \c D and keep it alive in APISet. ObjCCategoryRecord * addObjCCategory(StringRef Name, StringRef USR, PresumedLoc Loc, - AvailabilitySet Availability, const DocComment &Comment, + AvailabilityInfo Availability, const DocComment &Comment, DeclarationFragments Declaration, DeclarationFragments SubHeading, SymbolReference Interface, bool IsFromSystemHeader, bool IsFromExternalModule); @@ -1419,7 +1423,7 @@ public: /// to generate the USR for \c D and keep it alive in APISet. ObjCInterfaceRecord * addObjCInterface(StringRef Name, StringRef USR, PresumedLoc Loc, - AvailabilitySet Availability, LinkageInfo Linkage, + AvailabilityInfo Availability, LinkageInfo Linkage, const DocComment &Comment, DeclarationFragments Declaration, DeclarationFragments SubHeading, SymbolReference SuperClass, bool IsFromSystemHeader); @@ -1432,7 +1436,7 @@ public: /// to generate the USR for \c D and keep it alive in APISet. ObjCMethodRecord * addObjCMethod(ObjCContainerRecord *Container, StringRef Name, StringRef USR, - PresumedLoc Loc, AvailabilitySet Availability, + PresumedLoc Loc, AvailabilityInfo Availability, const DocComment &Comment, DeclarationFragments Declaration, DeclarationFragments SubHeading, FunctionSignature Signature, bool IsInstanceMethod, bool IsFromSystemHeader); @@ -1445,7 +1449,7 @@ public: /// to generate the USR for \c D and keep it alive in APISet. ObjCPropertyRecord * addObjCProperty(ObjCContainerRecord *Container, StringRef Name, StringRef USR, - PresumedLoc Loc, AvailabilitySet Availability, + PresumedLoc Loc, AvailabilityInfo Availability, const DocComment &Comment, DeclarationFragments Declaration, DeclarationFragments SubHeading, ObjCPropertyRecord::AttributeKind Attributes, @@ -1460,7 +1464,7 @@ public: /// to generate the USR for \c D and keep it alive in APISet. ObjCInstanceVariableRecord *addObjCInstanceVariable( ObjCContainerRecord *Container, StringRef Name, StringRef USR, - PresumedLoc Loc, AvailabilitySet Availability, const DocComment &Comment, + PresumedLoc Loc, AvailabilityInfo Availability, const DocComment &Comment, DeclarationFragments Declaration, DeclarationFragments SubHeading, ObjCInstanceVariableRecord::AccessControl Access, bool IsFromSystemHeader); @@ -1473,7 +1477,7 @@ public: /// to generate the USR for \c D and keep it alive in APISet. ObjCProtocolRecord * addObjCProtocol(StringRef Name, StringRef USR, PresumedLoc Loc, - AvailabilitySet Availability, const DocComment &Comment, + AvailabilityInfo Availability, const DocComment &Comment, DeclarationFragments Declaration, DeclarationFragments SubHeading, bool IsFromSystemHeader); @@ -1498,7 +1502,7 @@ public: /// to generate the USR for \c D and keep it alive in APISet. TypedefRecord * addTypedef(StringRef Name, StringRef USR, PresumedLoc Loc, - AvailabilitySet Availability, const DocComment &Comment, + AvailabilityInfo Availability, const DocComment &Comment, DeclarationFragments Declaration, DeclarationFragments SubHeading, SymbolReference UnderlyingType, bool IsFromSystemHeader); @@ -1545,7 +1549,7 @@ public: return GlobalVariableTemplatePartialSpecializations; } const RecordMap &getEnums() const { return Enums; } - const RecordMap &getStructs() const { return Structs; } + const RecordMap &getRecords() const { return Records; } const RecordMap &getCXXClasses() const { return CXXClasses; } const RecordMap &getCXXMethodTemplates() const { return CXXMethodTemplates; @@ -1564,7 +1568,6 @@ public: const RecordMap &getCXXFieldTemplates() const { return CXXFieldTemplates; } - const RecordMap &getConcepts() const { return Concepts; } const RecordMap &getClassTemplates() const { return ClassTemplates; } @@ -1576,7 +1579,7 @@ public: getClassTemplatePartialSpecializations() const { return ClassTemplatePartialSpecializations; } - const RecordMap &getRecords() const { return Concepts; } + const RecordMap &getConcepts() const { return Concepts; } const RecordMap &getObjCCategories() const { return ObjCCategories; } @@ -1642,7 +1645,7 @@ private: RecordMap Concepts; RecordMap StaticFields; RecordMap Enums; - RecordMap Structs; + RecordMap Records; RecordMap CXXClasses; RecordMap CXXFields; RecordMap CXXMethods; diff --git a/clang/include/clang/ExtractAPI/AvailabilityInfo.h b/clang/include/clang/ExtractAPI/AvailabilityInfo.h index 0af373135b6..3b8d6f46ed5 100644 --- a/clang/include/clang/ExtractAPI/AvailabilityInfo.h +++ b/clang/include/clang/ExtractAPI/AvailabilityInfo.h @@ -16,56 +16,31 @@ #define LLVM_CLANG_EXTRACTAPI_AVAILABILITY_INFO_H #include "clang/AST/Decl.h" -#include "llvm/ADT/SmallVector.h" #include "llvm/Support/Error.h" #include "llvm/Support/VersionTuple.h" #include "llvm/Support/raw_ostream.h" -using llvm::VersionTuple; - namespace clang { namespace extractapi { -/// Stores availability attributes of a symbol in a given domain. +/// Stores availability attributes of a symbol. struct AvailabilityInfo { /// The domain for which this availability info item applies std::string Domain; VersionTuple Introduced; VersionTuple Deprecated; VersionTuple Obsoleted; - bool Unavailable; - - AvailabilityInfo() = default; - - AvailabilityInfo(StringRef Domain, VersionTuple I, VersionTuple D, - VersionTuple O, bool U) - : Domain(Domain), Introduced(I), Deprecated(D), Obsoleted(O), - Unavailable(U) {} -}; - -class AvailabilitySet { -private: - using AvailabilityList = llvm::SmallVector; - AvailabilityList Availabilities; - bool UnconditionallyDeprecated = false; bool UnconditionallyUnavailable = false; -public: - AvailabilitySet(const Decl *Decl); - AvailabilitySet() = default; - - AvailabilityList::const_iterator begin() const { - return Availabilities.begin(); - } - - AvailabilityList::const_iterator end() const { return Availabilities.end(); } + AvailabilityInfo() = default; + /// Determine if this AvailabilityInfo represents the default availability. + bool isDefault() const { return *this == AvailabilityInfo(); } /// Check if the symbol is unconditionally deprecated. /// /// i.e. \code __attribute__((deprecated)) \endcode bool isUnconditionallyDeprecated() const { return UnconditionallyDeprecated; } - /// Check if the symbol is unconditionally unavailable. /// /// i.e. \code __attribute__((unavailable)) \endcode @@ -73,10 +48,28 @@ public: return UnconditionallyUnavailable; } - /// Determine if this AvailabilitySet represents default availability. - bool isDefault() const { return Availabilities.empty(); } + AvailabilityInfo(StringRef Domain, VersionTuple I, VersionTuple D, + VersionTuple O, bool UD, bool UU) + : Domain(Domain), Introduced(I), Deprecated(D), Obsoleted(O), + UnconditionallyDeprecated(UD), UnconditionallyUnavailable(UU) {} + + friend bool operator==(const AvailabilityInfo &Lhs, + const AvailabilityInfo &Rhs); + +public: + static AvailabilityInfo createFromDecl(const Decl *Decl); }; +inline bool operator==(const AvailabilityInfo &Lhs, + const AvailabilityInfo &Rhs) { + return std::tie(Lhs.Introduced, Lhs.Deprecated, Lhs.Obsoleted, + Lhs.UnconditionallyDeprecated, + Lhs.UnconditionallyUnavailable) == + std::tie(Rhs.Introduced, Rhs.Deprecated, Rhs.Obsoleted, + Rhs.UnconditionallyDeprecated, + Rhs.UnconditionallyUnavailable); +} + } // namespace extractapi } // namespace clang diff --git a/clang/include/clang/ExtractAPI/DeclarationFragments.h b/clang/include/clang/ExtractAPI/DeclarationFragments.h index d719196b9a4..1b78c8b5931 100644 --- a/clang/include/clang/ExtractAPI/DeclarationFragments.h +++ b/clang/include/clang/ExtractAPI/DeclarationFragments.h @@ -295,8 +295,9 @@ public: /// Build DeclarationFragments for a field declaration FieldDecl. static DeclarationFragments getFragmentsForField(const FieldDecl *); - /// Build DeclarationFragments for a struct record declaration RecordDecl. - static DeclarationFragments getFragmentsForStruct(const RecordDecl *); + /// Build DeclarationFragments for a struct/union record declaration + /// RecordDecl. + static DeclarationFragments getFragmentsForRecordDecl(const RecordDecl *); static DeclarationFragments getFragmentsForCXXClass(const CXXRecordDecl *); diff --git a/clang/include/clang/ExtractAPI/ExtractAPIVisitor.h b/clang/include/clang/ExtractAPI/ExtractAPIVisitor.h index a344fa7d5d8..ac6f4e31354 100644 --- a/clang/include/clang/ExtractAPI/ExtractAPIVisitor.h +++ b/clang/include/clang/ExtractAPI/ExtractAPIVisitor.h @@ -14,10 +14,12 @@ #ifndef LLVM_CLANG_EXTRACTAPI_EXTRACT_API_VISITOR_H #define LLVM_CLANG_EXTRACTAPI_EXTRACT_API_VISITOR_H +#include "clang/AST/Decl.h" #include "clang/AST/DeclCXX.h" #include "clang/AST/DeclTemplate.h" #include "clang/Basic/OperatorKinds.h" #include "clang/Basic/Specifiers.h" +#include "clang/ExtractAPI/AvailabilityInfo.h" #include "clang/ExtractAPI/DeclarationFragments.h" #include "llvm/ADT/FunctionExtras.h" @@ -128,9 +130,10 @@ protected: void recordEnumConstants(EnumRecord *EnumRecord, const EnumDecl::enumerator_range Constants); - /// Collect API information for the struct fields and associate with the + /// Collect API information for the record fields and associate with the /// parent struct. - void recordStructFields(StructRecord *StructRecord, + void recordRecordFields(RecordRecord *RecordRecord, + APIRecord::RecordKind FieldKind, const RecordDecl::field_range Fields); /// Collect API information for the Objective-C methods and associate with the @@ -263,7 +266,6 @@ bool ExtractAPIVisitorBase::VisitVarDecl(const VarDecl *Decl) { DeclarationFragmentsBuilder::getFragmentsForVar(Decl); DeclarationFragments SubHeading = DeclarationFragmentsBuilder::getSubHeading(Decl); - if (Decl->isStaticDataMember()) { SymbolReference Context; // getDeclContext() should return a RecordDecl since we @@ -272,13 +274,14 @@ bool ExtractAPIVisitorBase::VisitVarDecl(const VarDecl *Decl) { Context.Name = Record->getName(); Context.USR = API.recordUSR(Record); auto Access = DeclarationFragmentsBuilder::getAccessControl(Decl); - API.addStaticField(Name, USR, Loc, AvailabilitySet(Decl), Linkage, Comment, - Declaration, SubHeading, Context, Access, - isInSystemHeader(Decl)); + API.addStaticField(Name, USR, Loc, AvailabilityInfo::createFromDecl(Decl), + Linkage, Comment, Declaration, SubHeading, Context, + Access, isInSystemHeader(Decl)); } else // Add the global variable record to the API set. - API.addGlobalVar(Name, USR, Loc, AvailabilitySet(Decl), Linkage, Comment, - Declaration, SubHeading, isInSystemHeader(Decl)); + API.addGlobalVar(Name, USR, Loc, AvailabilityInfo::createFromDecl(Decl), + Linkage, Comment, Declaration, SubHeading, + isInSystemHeader(Decl)); return true; } @@ -333,19 +336,19 @@ bool ExtractAPIVisitorBase::VisitFunctionDecl( DeclarationFragmentsBuilder::getSubHeading(Decl); FunctionSignature Signature = DeclarationFragmentsBuilder::getFunctionSignature(Decl); - if (Decl->getTemplateSpecializationInfo()) API.addGlobalFunctionTemplateSpecialization( - Name, USR, Loc, AvailabilitySet(Decl), Linkage, Comment, + Name, USR, Loc, AvailabilityInfo::createFromDecl(Decl), Linkage, + Comment, DeclarationFragmentsBuilder:: getFragmentsForFunctionTemplateSpecialization(Decl), SubHeading, Signature, isInSystemHeader(Decl)); else // Add the function record to the API set. API.addGlobalFunction( - Name, USR, Loc, AvailabilitySet(Decl), Linkage, Comment, - DeclarationFragmentsBuilder::getFragmentsForFunction(Decl), SubHeading, - Signature, isInSystemHeader(Decl)); + Name, USR, Loc, AvailabilityInfo::createFromDecl(Decl), Linkage, + Comment, DeclarationFragmentsBuilder::getFragmentsForFunction(Decl), + SubHeading, Signature, isInSystemHeader(Decl)); return true; } @@ -379,10 +382,9 @@ bool ExtractAPIVisitorBase::VisitEnumDecl(const EnumDecl *Decl) { DeclarationFragmentsBuilder::getFragmentsForEnum(Decl); DeclarationFragments SubHeading = DeclarationFragmentsBuilder::getSubHeading(Decl); - - EnumRecord *EnumRecord = - API.addEnum(API.copyString(Name), USR, Loc, AvailabilitySet(Decl), - Comment, Declaration, SubHeading, isInSystemHeader(Decl)); + EnumRecord *EnumRecord = API.addEnum( + API.copyString(Name), USR, Loc, AvailabilityInfo::createFromDecl(Decl), + Comment, Declaration, SubHeading, isInSystemHeader(Decl)); // Now collect information about the enumerators in this enum. getDerivedExtractAPIVisitor().recordEnumConstants(EnumRecord, @@ -496,8 +498,9 @@ bool ExtractAPIVisitorBase::VisitNamespaceDecl( DeclarationFragments SubHeading = DeclarationFragmentsBuilder::getSubHeading(Decl); APIRecord *Parent = determineParentRecord(Decl->getDeclContext()); - API.addNamespace(Parent, Name, USR, Loc, AvailabilitySet(Decl), Linkage, - Comment, Declaration, SubHeading, isInSystemHeader(Decl)); + API.addNamespace(Parent, Name, USR, Loc, + AvailabilityInfo::createFromDecl(Decl), Linkage, Comment, + Declaration, SubHeading, isInSystemHeader(Decl)); return true; } @@ -524,17 +527,25 @@ bool ExtractAPIVisitorBase::VisitRecordDecl(const RecordDecl *Decl) { // Build declaration fragments and sub-heading for the struct. DeclarationFragments Declaration = - DeclarationFragmentsBuilder::getFragmentsForStruct(Decl); + DeclarationFragmentsBuilder::getFragmentsForRecordDecl(Decl); DeclarationFragments SubHeading = DeclarationFragmentsBuilder::getSubHeading(Decl); - StructRecord *StructRecord = - API.addStruct(Name, USR, Loc, AvailabilitySet(Decl), Comment, Declaration, - SubHeading, isInSystemHeader(Decl)); + auto RecordKind = APIRecord::RK_Struct; + auto FieldRecordKind = APIRecord::RK_StructField; + + if (Decl->isUnion()) { + RecordKind = APIRecord::RK_Union; + FieldRecordKind = APIRecord::RK_UnionField; + } + + RecordRecord *RecordRecord = API.addRecord( + Name, USR, Loc, AvailabilityInfo::createFromDecl(Decl), Comment, + Declaration, SubHeading, RecordKind, isInSystemHeader(Decl)); // Now collect information about the fields in this struct. - getDerivedExtractAPIVisitor().recordStructFields(StructRecord, - Decl->fields()); + getDerivedExtractAPIVisitor().recordRecordFields( + RecordRecord, FieldRecordKind, Decl->fields()); return true; } @@ -578,13 +589,13 @@ bool ExtractAPIVisitorBase::VisitCXXRecordDecl( DeclarationFragmentsBuilder::getFragmentsForRedeclarableTemplate( Decl->getDescribedClassTemplate())); CXXClassRecord = API.addClassTemplate( - Parent, Name, USR, Loc, AvailabilitySet(Decl), Comment, Declaration, - SubHeading, Template(Decl->getDescribedClassTemplate()), Access, - isInSystemHeader(Decl)); + Parent, Name, USR, Loc, AvailabilityInfo::createFromDecl(Decl), Comment, + Declaration, SubHeading, Template(Decl->getDescribedClassTemplate()), + Access, isInSystemHeader(Decl)); } else CXXClassRecord = API.addCXXClass( - Parent, Name, USR, Loc, AvailabilitySet(Decl), Comment, Declaration, - SubHeading, Kind, Access, isInSystemHeader(Decl)); + Parent, Name, USR, Loc, AvailabilityInfo::createFromDecl(Decl), Comment, + Declaration, SubHeading, Kind, Access, isInSystemHeader(Decl)); CXXClassRecord->Bases = getBases(Decl); @@ -624,7 +635,7 @@ bool ExtractAPIVisitorBase::VisitCXXMethodDecl( FunctionTemplateDecl *TemplateDecl = Decl->getDescribedFunctionTemplate(); API.addCXXMethodTemplate( API.findRecordForUSR(ParentUSR), Decl->getName(), USR, Loc, - AvailabilitySet(Decl), Comment, + AvailabilityInfo::createFromDecl(Decl), Comment, DeclarationFragmentsBuilder::getFragmentsForFunctionTemplate( TemplateDecl), SubHeading, DeclarationFragmentsBuilder::getFunctionSignature(Decl), @@ -632,24 +643,27 @@ bool ExtractAPIVisitorBase::VisitCXXMethodDecl( Template(TemplateDecl), isInSystemHeader(Decl)); } else if (Decl->getTemplateSpecializationInfo()) API.addCXXMethodTemplateSpec( - Parent, Decl->getName(), USR, Loc, AvailabilitySet(Decl), Comment, + Parent, Decl->getName(), USR, Loc, + AvailabilityInfo::createFromDecl(Decl), Comment, DeclarationFragmentsBuilder:: getFragmentsForFunctionTemplateSpecialization(Decl), SubHeading, Signature, Access, isInSystemHeader(Decl)); else if (Decl->isOverloadedOperator()) API.addCXXInstanceMethod( Parent, API.copyString(Decl->getNameAsString()), USR, Loc, - AvailabilitySet(Decl), Comment, + AvailabilityInfo::createFromDecl(Decl), Comment, DeclarationFragmentsBuilder::getFragmentsForOverloadedOperator(Decl), SubHeading, Signature, Access, isInSystemHeader(Decl)); else if (Decl->isStatic()) API.addCXXStaticMethod( - Parent, Decl->getName(), USR, Loc, AvailabilitySet(Decl), Comment, + Parent, Decl->getName(), USR, Loc, + AvailabilityInfo::createFromDecl(Decl), Comment, DeclarationFragmentsBuilder::getFragmentsForCXXMethod(Decl), SubHeading, Signature, Access, isInSystemHeader(Decl)); else API.addCXXInstanceMethod( - Parent, Decl->getName(), USR, Loc, AvailabilitySet(Decl), Comment, + Parent, Decl->getName(), USR, Loc, + AvailabilityInfo::createFromDecl(Decl), Comment, DeclarationFragmentsBuilder::getFragmentsForCXXMethod(Decl), SubHeading, Signature, Access, isInSystemHeader(Decl)); @@ -678,13 +692,12 @@ bool ExtractAPIVisitorBase::VisitCXXConstructorDecl( FunctionSignature Signature = DeclarationFragmentsBuilder::getFunctionSignature(Decl); AccessControl Access = DeclarationFragmentsBuilder::getAccessControl(Decl); - SmallString<128> ParentUSR; index::generateUSRForDecl(dyn_cast(Decl->getDeclContext()), ParentUSR); API.addCXXInstanceMethod(API.findRecordForUSR(ParentUSR), Name, USR, Loc, - AvailabilitySet(Decl), Comment, Declaration, - SubHeading, Signature, Access, + AvailabilityInfo::createFromDecl(Decl), Comment, + Declaration, SubHeading, Signature, Access, isInSystemHeader(Decl)); return true; } @@ -711,13 +724,12 @@ bool ExtractAPIVisitorBase::VisitCXXDestructorDecl( FunctionSignature Signature = DeclarationFragmentsBuilder::getFunctionSignature(Decl); AccessControl Access = DeclarationFragmentsBuilder::getAccessControl(Decl); - SmallString<128> ParentUSR; index::generateUSRForDecl(dyn_cast(Decl->getDeclContext()), ParentUSR); API.addCXXInstanceMethod(API.findRecordForUSR(ParentUSR), Name, USR, Loc, - AvailabilitySet(Decl), Comment, Declaration, - SubHeading, Signature, Access, + AvailabilityInfo::createFromDecl(Decl), Comment, + Declaration, SubHeading, Signature, Access, isInSystemHeader(Decl)); return true; } @@ -740,8 +752,9 @@ bool ExtractAPIVisitorBase::VisitConceptDecl(const ConceptDecl *Decl) { DeclarationFragmentsBuilder::getFragmentsForConcept(Decl); DeclarationFragments SubHeading = DeclarationFragmentsBuilder::getSubHeading(Decl); - API.addConcept(Name, USR, Loc, AvailabilitySet(Decl), Comment, Declaration, - SubHeading, Template(Decl), isInSystemHeader(Decl)); + API.addConcept(Name, USR, Loc, AvailabilityInfo::createFromDecl(Decl), + Comment, Declaration, SubHeading, Template(Decl), + isInSystemHeader(Decl)); return true; } @@ -768,8 +781,9 @@ bool ExtractAPIVisitorBase::VisitClassTemplateSpecializationDecl( APIRecord *Parent = determineParentRecord(Decl->getDeclContext()); auto *ClassTemplateSpecializationRecord = API.addClassTemplateSpecialization( - Parent, Name, USR, Loc, AvailabilitySet(Decl), Comment, Declaration, - SubHeading, DeclarationFragmentsBuilder::getAccessControl(Decl), + Parent, Name, USR, Loc, AvailabilityInfo::createFromDecl(Decl), Comment, + Declaration, SubHeading, + DeclarationFragmentsBuilder::getAccessControl(Decl), isInSystemHeader(Decl)); ClassTemplateSpecializationRecord->Bases = getBases(Decl); @@ -797,12 +811,11 @@ bool ExtractAPIVisitorBase:: getFragmentsForClassTemplatePartialSpecialization(Decl); DeclarationFragments SubHeading = DeclarationFragmentsBuilder::getSubHeading(Decl); - APIRecord *Parent = determineParentRecord(Decl->getDeclContext()); auto *ClassTemplatePartialSpecRecord = API.addClassTemplatePartialSpecialization( - Parent, Name, USR, Loc, AvailabilitySet(Decl), Comment, Declaration, - SubHeading, Template(Decl), + Parent, Name, USR, Loc, AvailabilityInfo::createFromDecl(Decl), + Comment, Declaration, SubHeading, Template(Decl), DeclarationFragmentsBuilder::getAccessControl(Decl), isInSystemHeader(Decl)); @@ -845,12 +858,13 @@ bool ExtractAPIVisitorBase::VisitVarTemplateDecl( ParentUSR); if (Decl->getDeclContext()->getDeclKind() == Decl::CXXRecord) API.addCXXFieldTemplate(API.findRecordForUSR(ParentUSR), Name, USR, Loc, - AvailabilitySet(Decl), Comment, Declaration, - SubHeading, + AvailabilityInfo::createFromDecl(Decl), Comment, + Declaration, SubHeading, DeclarationFragmentsBuilder::getAccessControl(Decl), Template(Decl), isInSystemHeader(Decl)); else - API.addGlobalVariableTemplate(Name, USR, Loc, AvailabilitySet(Decl), + API.addGlobalVariableTemplate(Name, USR, Loc, + AvailabilityInfo::createFromDecl(Decl), Linkage, Comment, Declaration, SubHeading, Template(Decl), isInSystemHeader(Decl)); return true; @@ -880,10 +894,9 @@ bool ExtractAPIVisitorBase::VisitVarTemplateSpecializationDecl( Decl); DeclarationFragments SubHeading = DeclarationFragmentsBuilder::getSubHeading(Decl); - API.addGlobalVariableTemplateSpecialization( - Name, USR, Loc, AvailabilitySet(Decl), Linkage, Comment, Declaration, - SubHeading, isInSystemHeader(Decl)); + Name, USR, Loc, AvailabilityInfo::createFromDecl(Decl), Linkage, Comment, + Declaration, SubHeading, isInSystemHeader(Decl)); return true; } @@ -910,10 +923,9 @@ bool ExtractAPIVisitorBase::VisitVarTemplatePartialSpecializationDecl( getFragmentsForVarTemplatePartialSpecialization(Decl); DeclarationFragments SubHeading = DeclarationFragmentsBuilder::getSubHeading(Decl); - API.addGlobalVariableTemplatePartialSpecialization( - Name, USR, Loc, AvailabilitySet(Decl), Linkage, Comment, Declaration, - SubHeading, Template(Decl), isInSystemHeader(Decl)); + Name, USR, Loc, AvailabilityInfo::createFromDecl(Decl), Linkage, Comment, + Declaration, SubHeading, Template(Decl), isInSystemHeader(Decl)); return true; } @@ -942,9 +954,8 @@ bool ExtractAPIVisitorBase::VisitFunctionTemplateDecl( FunctionSignature Signature = DeclarationFragmentsBuilder::getFunctionSignature( Decl->getTemplatedDecl()); - API.addGlobalFunctionTemplate( - Name, USR, Loc, AvailabilitySet(Decl), Linkage, Comment, + Name, USR, Loc, AvailabilityInfo::createFromDecl(Decl), Linkage, Comment, DeclarationFragmentsBuilder::getFragmentsForFunctionTemplate(Decl), SubHeading, Signature, Template(Decl), isInSystemHeader(Decl)); @@ -983,8 +994,8 @@ bool ExtractAPIVisitorBase::VisitObjCInterfaceDecl( } ObjCInterfaceRecord *ObjCInterfaceRecord = API.addObjCInterface( - Name, USR, Loc, AvailabilitySet(Decl), Linkage, Comment, Declaration, - SubHeading, SuperClass, isInSystemHeader(Decl)); + Name, USR, Loc, AvailabilityInfo::createFromDecl(Decl), Linkage, Comment, + Declaration, SubHeading, SuperClass, isInSystemHeader(Decl)); // Record all methods (selectors). This doesn't include automatically // synthesized property methods. @@ -1023,9 +1034,9 @@ bool ExtractAPIVisitorBase::VisitObjCProtocolDecl( DeclarationFragments SubHeading = DeclarationFragmentsBuilder::getSubHeading(Decl); - ObjCProtocolRecord *ObjCProtocolRecord = - API.addObjCProtocol(Name, USR, Loc, AvailabilitySet(Decl), Comment, - Declaration, SubHeading, isInSystemHeader(Decl)); + ObjCProtocolRecord *ObjCProtocolRecord = API.addObjCProtocol( + Name, USR, Loc, AvailabilityInfo::createFromDecl(Decl), Comment, + Declaration, SubHeading, isInSystemHeader(Decl)); getDerivedExtractAPIVisitor().recordObjCMethods(ObjCProtocolRecord, Decl->methods()); @@ -1055,8 +1066,8 @@ bool ExtractAPIVisitorBase::VisitTypedefNameDecl( dyn_cast(Decl->getUnderlyingType())) { if (const TagType *TagTy = dyn_cast(ET->desugar())) { if (Decl->getName() == TagTy->getDecl()->getName()) { - if (TagTy->getDecl()->isStruct()) { - modifyRecords(API.getStructs(), Decl->getName()); + if (isa(TagTy->getDecl())) { + modifyRecords(API.getRecords(), Decl->getName()); } if (TagTy->getDecl()->isEnum()) { modifyRecords(API.getEnums(), Decl->getName()); @@ -1080,7 +1091,8 @@ bool ExtractAPIVisitorBase::VisitTypedefNameDecl( TypedefUnderlyingTypeResolver(Context).getSymbolReferenceForType(Type, API); - API.addTypedef(Name, USR, Loc, AvailabilitySet(Decl), Comment, + API.addTypedef(Name, USR, Loc, AvailabilityInfo::createFromDecl(Decl), + Comment, DeclarationFragmentsBuilder::getFragmentsForTypedef(Decl), DeclarationFragmentsBuilder::getSubHeading(Decl), SymRef, isInSystemHeader(Decl)); @@ -1122,8 +1134,9 @@ bool ExtractAPIVisitorBase::VisitObjCCategoryDecl( } ObjCCategoryRecord *ObjCCategoryRecord = API.addObjCCategory( - Name, USR, Loc, AvailabilitySet(Decl), Comment, Declaration, SubHeading, - Interface, isInSystemHeader(Decl), IsFromExternalModule); + Name, USR, Loc, AvailabilityInfo::createFromDecl(Decl), Comment, + Declaration, SubHeading, Interface, isInSystemHeader(Decl), + IsFromExternalModule); getDerivedExtractAPIVisitor().recordObjCMethods(ObjCCategoryRecord, Decl->methods()); @@ -1160,17 +1173,18 @@ void ExtractAPIVisitorBase::recordEnumConstants( DeclarationFragments SubHeading = DeclarationFragmentsBuilder::getSubHeading(Constant); - API.addEnumConstant(EnumRecord, Name, USR, Loc, AvailabilitySet(Constant), - Comment, Declaration, SubHeading, - isInSystemHeader(Constant)); + API.addEnumConstant(EnumRecord, Name, USR, Loc, + AvailabilityInfo::createFromDecl(Constant), Comment, + Declaration, SubHeading, isInSystemHeader(Constant)); } } /// Collect API information for the struct fields and associate with the /// parent struct. template -void ExtractAPIVisitorBase::recordStructFields( - StructRecord *StructRecord, const RecordDecl::field_range Fields) { +void ExtractAPIVisitorBase::recordRecordFields( + RecordRecord *RecordRecord, APIRecord::RecordKind FieldKind, + const RecordDecl::field_range Fields) { for (const auto *Field : Fields) { // Collect symbol information. StringRef Name = Field->getName(); @@ -1189,9 +1203,9 @@ void ExtractAPIVisitorBase::recordStructFields( DeclarationFragments SubHeading = DeclarationFragmentsBuilder::getSubHeading(Field); - API.addStructField(StructRecord, Name, USR, Loc, AvailabilitySet(Field), - Comment, Declaration, SubHeading, - isInSystemHeader(Field)); + API.addRecordField( + RecordRecord, Name, USR, Loc, AvailabilityInfo::createFromDecl(Field), + Comment, Declaration, SubHeading, FieldKind, isInSystemHeader(Field)); } } @@ -1223,8 +1237,8 @@ bool ExtractAPIVisitorBase::VisitFieldDecl(const FieldDecl *Decl) { index::generateUSRForDecl(dyn_cast(Decl->getDeclContext()), ParentUSR); API.addCXXField(API.findRecordForUSR(ParentUSR), Name, USR, Loc, - AvailabilitySet(Decl), Comment, Declaration, SubHeading, - Access, isInSystemHeader(Decl)); + AvailabilityInfo::createFromDecl(Decl), Comment, Declaration, + SubHeading, Access, isInSystemHeader(Decl)); return true; } @@ -1255,13 +1269,13 @@ bool ExtractAPIVisitorBase::VisitCXXConversionDecl( ParentUSR); if (Decl->isStatic()) API.addCXXStaticMethod(API.findRecordForUSR(ParentUSR), Name, USR, Loc, - AvailabilitySet(Decl), Comment, Declaration, - SubHeading, Signature, Access, + AvailabilityInfo::createFromDecl(Decl), Comment, + Declaration, SubHeading, Signature, Access, isInSystemHeader(Decl)); else API.addCXXInstanceMethod(API.findRecordForUSR(ParentUSR), Name, USR, Loc, - AvailabilitySet(Decl), Comment, Declaration, - SubHeading, Signature, Access, + AvailabilityInfo::createFromDecl(Decl), Comment, + Declaration, SubHeading, Signature, Access, isInSystemHeader(Decl)); return true; } @@ -1295,8 +1309,9 @@ void ExtractAPIVisitorBase::recordObjCMethods( FunctionSignature Signature = DeclarationFragmentsBuilder::getFunctionSignature(Method); - API.addObjCMethod(Container, Name, USR, Loc, AvailabilitySet(Method), - Comment, Declaration, SubHeading, Signature, + API.addObjCMethod(Container, Name, USR, Loc, + AvailabilityInfo::createFromDecl(Method), Comment, + Declaration, SubHeading, Signature, Method->isInstanceMethod(), isInSystemHeader(Method)); } } @@ -1334,8 +1349,8 @@ void ExtractAPIVisitorBase::recordObjCProperties( Attributes |= ObjCPropertyRecord::ReadOnly; API.addObjCProperty( - Container, Name, USR, Loc, AvailabilitySet(Property), Comment, - Declaration, SubHeading, + Container, Name, USR, Loc, AvailabilityInfo::createFromDecl(Property), + Comment, Declaration, SubHeading, static_cast(Attributes), GetterName, SetterName, Property->isOptional(), !(Property->getPropertyAttributes() & @@ -1370,9 +1385,9 @@ void ExtractAPIVisitorBase::recordObjCInstanceVariables( ObjCInstanceVariableRecord::AccessControl Access = Ivar->getCanonicalAccessControl(); - API.addObjCInstanceVariable(Container, Name, USR, Loc, - AvailabilitySet(Ivar), Comment, Declaration, - SubHeading, Access, isInSystemHeader(Ivar)); + API.addObjCInstanceVariable( + Container, Name, USR, Loc, AvailabilityInfo::createFromDecl(Ivar), + Comment, Declaration, SubHeading, Access, isInSystemHeader(Ivar)); } } diff --git a/clang/include/clang/ExtractAPI/Serialization/SerializerBase.h b/clang/include/clang/ExtractAPI/Serialization/SerializerBase.h index a188400a74d..f0629a9ad56 100644 --- a/clang/include/clang/ExtractAPI/Serialization/SerializerBase.h +++ b/clang/include/clang/ExtractAPI/Serialization/SerializerBase.h @@ -65,7 +65,7 @@ public: getDerived()->traverseGlobalFunctionTemplateSpecializationRecords(); - getDerived()->traverseStructRecords(); + getDerived()->traverseRecordRecords(); getDerived()->traverseObjCInterfaces(); @@ -98,9 +98,9 @@ public: getDerived()->visitEnumRecord(*Enum.second); } - void traverseStructRecords() { - for (const auto &Struct : API.getStructs()) - getDerived()->visitStructRecord(*Struct.second); + void traverseRecordRecords() { + for (const auto &Record : API.getRecords()) + getDerived()->visitRecordRecord(*Record.second); } void traverseStaticFieldRecords() { @@ -238,8 +238,8 @@ public: /// Visit an enum record. void visitEnumRecord(const EnumRecord &Record){}; - /// Visit a struct record. - void visitStructRecord(const StructRecord &Record){}; + /// Visit a record record. + void visitRecordRecord(const RecordRecord &Record){}; void visitStaticFieldRecord(const StaticFieldRecord &Record){}; diff --git a/clang/include/clang/ExtractAPI/Serialization/SymbolGraphSerializer.h b/clang/include/clang/ExtractAPI/Serialization/SymbolGraphSerializer.h index a9b714dc484..4249ac405fd 100644 --- a/clang/include/clang/ExtractAPI/Serialization/SymbolGraphSerializer.h +++ b/clang/include/clang/ExtractAPI/Serialization/SymbolGraphSerializer.h @@ -170,8 +170,8 @@ public: /// Visit an enum record. void visitEnumRecord(const EnumRecord &Record); - /// Visit a struct record. - void visitStructRecord(const StructRecord &Record); + /// Visit a record record. + void visitRecordRecord(const RecordRecord &Record); void visitStaticFieldRecord(const StaticFieldRecord &Record); diff --git a/clang/include/clang/Format/Format.h b/clang/include/clang/Format/Format.h index 59b645ecab7..bc9eecd42f9 100644 --- a/clang/include/clang/Format/Format.h +++ b/clang/include/clang/Format/Format.h @@ -3055,6 +3055,7 @@ struct FormatStyle { bool isProto() const { return Language == LK_Proto || Language == LK_TextProto; } + bool isTableGen() const { return Language == LK_TableGen; } /// Language, this format style is targeted at. /// \version 3.5 @@ -3397,6 +3398,10 @@ struct FormatStyle { /// \version 14 unsigned PenaltyBreakOpenParenthesis; + /// The penalty for breaking after ``::``. + /// \version 18 + unsigned PenaltyBreakScopeResolution; + /// The penalty for each line break introduced inside a string literal. /// \version 3.7 unsigned PenaltyBreakString; @@ -3927,6 +3932,10 @@ struct FormatStyle { /// \version 13 unsigned ShortNamespaceLines; + /// Do not format macro definition body. + /// \version 18 + bool SkipMacroDefinitionBody; + /// Include sorting options. enum SortIncludesOptions : int8_t { /// Includes are never sorted. @@ -4872,6 +4881,7 @@ struct FormatStyle { PenaltyBreakComment == R.PenaltyBreakComment && PenaltyBreakFirstLessLess == R.PenaltyBreakFirstLessLess && PenaltyBreakOpenParenthesis == R.PenaltyBreakOpenParenthesis && + PenaltyBreakScopeResolution == R.PenaltyBreakScopeResolution && PenaltyBreakString == R.PenaltyBreakString && PenaltyBreakTemplateDeclaration == R.PenaltyBreakTemplateDeclaration && @@ -4889,6 +4899,7 @@ struct FormatStyle { RequiresExpressionIndentation == R.RequiresExpressionIndentation && SeparateDefinitionBlocks == R.SeparateDefinitionBlocks && ShortNamespaceLines == R.ShortNamespaceLines && + SkipMacroDefinitionBody == R.SkipMacroDefinitionBody && SortIncludes == R.SortIncludes && SortJavaStaticImport == R.SortJavaStaticImport && SpaceAfterCStyleCast == R.SpaceAfterCStyleCast && diff --git a/clang/include/clang/Frontend/ASTUnit.h b/clang/include/clang/Frontend/ASTUnit.h index fe99b3d5adb..6af712afdcb 100644 --- a/clang/include/clang/Frontend/ASTUnit.h +++ b/clang/include/clang/Frontend/ASTUnit.h @@ -902,7 +902,7 @@ public: SourceManager &SourceMgr, FileManager &FileMgr, SmallVectorImpl &StoredDiagnostics, SmallVectorImpl &OwnedBuffers, - std::unique_ptr Act = nullptr); + std::unique_ptr Act); /// Save this translation unit to a file with the given name. /// diff --git a/clang/include/clang/Frontend/Utils.h b/clang/include/clang/Frontend/Utils.h index 143cf4359f0..604e42067a3 100644 --- a/clang/include/clang/Frontend/Utils.h +++ b/clang/include/clang/Frontend/Utils.h @@ -43,12 +43,14 @@ class PCHContainerReader; class Preprocessor; class PreprocessorOptions; class PreprocessorOutputOptions; +class CodeGenOptions; /// InitializePreprocessor - Initialize the preprocessor getting it and the /// environment ready to process a single file. void InitializePreprocessor(Preprocessor &PP, const PreprocessorOptions &PPOpts, const PCHContainerReader &PCHContainerRdr, - const FrontendOptions &FEOpts); + const FrontendOptions &FEOpts, + const CodeGenOptions &CodeGenOpts); /// DoPrintPreprocessedInput - Implement -E mode. void DoPrintPreprocessedInput(Preprocessor &PP, raw_ostream *OS, diff --git a/clang/include/clang/Interpreter/Interpreter.h b/clang/include/clang/Interpreter/Interpreter.h index 01858dfcc90..292fa566ae7 100644 --- a/clang/include/clang/Interpreter/Interpreter.h +++ b/clang/include/clang/Interpreter/Interpreter.h @@ -129,7 +129,7 @@ public: llvm::Expected getSymbolAddressFromLinkerName(llvm::StringRef LinkerName) const; - enum InterfaceKind { NoAlloc, WithAlloc, CopyArray }; + enum InterfaceKind { NoAlloc, WithAlloc, CopyArray, NewTag }; const llvm::SmallVectorImpl &getValuePrintingInfo() const { return ValuePrintingInfo; @@ -144,7 +144,7 @@ private: llvm::DenseMap Dtors; - llvm::SmallVector ValuePrintingInfo; + llvm::SmallVector ValuePrintingInfo; }; } // namespace clang diff --git a/clang/include/clang/Lex/Lexer.h b/clang/include/clang/Lex/Lexer.h index 899e665e745..b6ecc7e5ded 100644 --- a/clang/include/clang/Lex/Lexer.h +++ b/clang/include/clang/Lex/Lexer.h @@ -198,11 +198,11 @@ public: /// from. Currently this is only used by _Pragma handling. SourceLocation getFileLoc() const { return FileLoc; } -private: /// Lex - Return the next token in the file. If this is the end of file, it /// return the tok::eof token. This implicitly involves the preprocessor. bool Lex(Token &Result); +private: /// Called when the preprocessor is in 'dependency scanning lexing mode'. bool LexDependencyDirectiveToken(Token &Result); diff --git a/clang/include/clang/Lex/Preprocessor.h b/clang/include/clang/Lex/Preprocessor.h index 4ec21a8b6be..2d9c53cdf5b 100644 --- a/clang/include/clang/Lex/Preprocessor.h +++ b/clang/include/clang/Lex/Preprocessor.h @@ -2829,12 +2829,20 @@ public: } void emitMacroExpansionWarnings(const Token &Identifier) const { - if (Identifier.getIdentifierInfo()->isDeprecatedMacro()) + IdentifierInfo *Info = Identifier.getIdentifierInfo(); + if (Info->isDeprecatedMacro()) emitMacroDeprecationWarning(Identifier); - if (Identifier.getIdentifierInfo()->isRestrictExpansion() && + if (Info->isRestrictExpansion() && !SourceMgr.isInMainFile(Identifier.getLocation())) emitRestrictExpansionWarning(Identifier); + + if (Info->getName() == "INFINITY") + if (getLangOpts().NoHonorInfs) + emitRestrictInfNaNWarning(Identifier, 0); + if (Info->getName() == "NAN") + if (getLangOpts().NoHonorNaNs) + emitRestrictInfNaNWarning(Identifier, 1); } static void processPathForFileMacro(SmallVectorImpl &Path, @@ -2850,6 +2858,8 @@ private: void emitMacroDeprecationWarning(const Token &Identifier) const; void emitRestrictExpansionWarning(const Token &Identifier) const; void emitFinalMacroWarning(const Token &Identifier, bool IsUndef) const; + void emitRestrictInfNaNWarning(const Token &Identifier, + unsigned DiagSelection) const; /// This boolean state keeps track if the current scanned token (by this PP) /// is in an "-Wunsafe-buffer-usage" opt-out region. Assuming PP scans a diff --git a/clang/include/clang/Parse/Parser.h b/clang/include/clang/Parse/Parser.h index 186dbb77085..ffbde370e8f 100644 --- a/clang/include/clang/Parse/Parser.h +++ b/clang/include/clang/Parse/Parser.h @@ -13,6 +13,7 @@ #ifndef LLVM_CLANG_PARSE_PARSER_H #define LLVM_CLANG_PARSE_PARSER_H +#include "clang/Basic/OpenACCKinds.h" #include "clang/Basic/OperatorPrecedence.h" #include "clang/Lex/CodeCompletionHandler.h" #include "clang/Lex/Preprocessor.h" @@ -3568,7 +3569,26 @@ private: void ParseOpenACCCacheVarList(); /// Parses a single variable in a variable list for OpenACC. bool ParseOpenACCVar(); + /// Parses the variable list for the variety of clauses that take a var-list, + /// including the optional Special Token listed for some,based on clause type. + bool ParseOpenACCClauseVarList(OpenACCClauseKind Kind); + /// Parses any parameters for an OpenACC Clause, including required/optional + /// parens. + bool ParseOpenACCClauseParams(OpenACCDirectiveKind DirKind, + OpenACCClauseKind Kind); + /// Parses a single clause in a clause-list for OpenACC. + bool ParseOpenACCClause(OpenACCDirectiveKind DirKind); + /// Parses the clause-list for an OpenACC directive. + void ParseOpenACCClauseList(OpenACCDirectiveKind DirKind); bool ParseOpenACCWaitArgument(); + /// Parses the clause of the 'bind' argument, which can be a string literal or + /// an ID expression. + ExprResult ParseOpenACCBindClauseArgument(); + /// Parses the clause kind of 'int-expr', which can be any integral + /// expression. + ExprResult ParseOpenACCIntExpr(); + /// Parses the 'device-type-list', which is a list of identifiers. + bool ParseOpenACCDeviceTypeList(); private: //===--------------------------------------------------------------------===// @@ -3644,6 +3664,18 @@ private: ParseConceptDefinition(const ParsedTemplateInfo &TemplateInfo, SourceLocation &DeclEnd); + /// Parse the given string as a type. + /// + /// This is a dangerous utility function currently employed only by API notes. + /// It is not a general entry-point for safely parsing types from strings. + /// + /// \param TypeStr The string to be parsed as a type. + /// \param Context The name of the context in which this string is being + /// parsed, which will be used in diagnostics. + /// \param IncludeLoc The location at which this parse was triggered. + TypeResult ParseTypeFromString(StringRef TypeStr, StringRef Context, + SourceLocation IncludeLoc); + //===--------------------------------------------------------------------===// // Modules DeclGroupPtrTy ParseModuleDecl(Sema::ModuleImportState &ImportState); diff --git a/clang/include/clang/Sema/ScopeInfo.h b/clang/include/clang/Sema/ScopeInfo.h index b2f6e3289f4..6eaa7438268 100644 --- a/clang/include/clang/Sema/ScopeInfo.h +++ b/clang/include/clang/Sema/ScopeInfo.h @@ -66,7 +66,7 @@ namespace sema { /// parsed. class CompoundScopeInfo { public: - /// Whether this compound stamement contains `for' or `while' loops + /// Whether this compound statement contains `for' or `while' loops /// with empty bodies. bool HasEmptyLoopBodies = false; @@ -168,7 +168,7 @@ public: /// to build, the initial and final coroutine suspend points bool NeedsCoroutineSuspends : 1; - /// An enumeration represeting the kind of the first coroutine statement + /// An enumeration representing the kind of the first coroutine statement /// in the function. One of co_return, co_await, or co_yield. unsigned char FirstCoroutineStmtKind : 2; @@ -220,7 +220,7 @@ public: /// The initial and final coroutine suspend points. std::pair CoroutineSuspends; - /// The stack of currently active compound stamement scopes in the + /// The stack of currently active compound statement scopes in the /// function. SmallVector CompoundScopes; diff --git a/clang/include/clang/Sema/Sema.h b/clang/include/clang/Sema/Sema.h index cf2d4fbe6d3..1f1cbd11ff7 100644 --- a/clang/include/clang/Sema/Sema.h +++ b/clang/include/clang/Sema/Sema.h @@ -955,6 +955,10 @@ public: OpaqueParser = P; } + /// Callback to the parser to parse a type expressed as a string. + std::function + ParseTypeFromStringCallback; + class DelayedDiagnostics; class DelayedDiagnosticsState { @@ -2108,6 +2112,10 @@ public: bool CheckFunctionReturnType(QualType T, SourceLocation Loc); + /// Check an argument list for placeholders that we won't try to + /// handle later. + bool CheckArgsForPlaceholders(MultiExprArg args); + /// Build a function type. /// /// This routine checks the function type according to C++ rules and @@ -2153,7 +2161,7 @@ public: SourceLocation Loc); QualType BuildBitIntType(bool IsUnsigned, Expr *BitWidth, SourceLocation Loc); - TypeSourceInfo *GetTypeForDeclarator(Declarator &D, Scope *S); + TypeSourceInfo *GetTypeForDeclarator(Declarator &D); TypeSourceInfo *GetTypeForDeclaratorCast(Declarator &D, QualType FromTy); /// Package the given type and TSI into a ParsedType. @@ -2194,7 +2202,7 @@ public: SourceLocation TargetLoc, const FunctionProtoType *Source, bool SkipSourceFirstParameter, SourceLocation SourceLoc); - TypeResult ActOnTypeName(Scope *S, Declarator &D); + TypeResult ActOnTypeName(Declarator &D); /// The parser has parsed the context-sensitive type 'instancetype' /// in an Objective-C message declaration. Return the appropriate type. @@ -3017,6 +3025,9 @@ public: ParmVarDecl *BuildParmVarDeclForTypedef(DeclContext *DC, SourceLocation Loc, QualType T); + QualType AdjustParameterTypeForObjCAutoRefCount(QualType T, + SourceLocation NameLoc, + TypeSourceInfo *TSInfo); ParmVarDecl *CheckParameter(DeclContext *DC, SourceLocation StartLoc, SourceLocation NameLoc, IdentifierInfo *Name, QualType T, TypeSourceInfo *TSInfo, @@ -4816,6 +4827,29 @@ public: /// Valid types should not have multiple attributes with different CCs. const AttributedType *getCallingConvAttributedType(QualType T) const; + /// Check whether a nullability type specifier can be added to the given + /// type through some means not written in source (e.g. API notes). + /// + /// \param Type The type to which the nullability specifier will be + /// added. On success, this type will be updated appropriately. + /// + /// \param Nullability The nullability specifier to add. + /// + /// \param DiagLoc The location to use for diagnostics. + /// + /// \param AllowArrayTypes Whether to accept nullability specifiers on an + /// array type (e.g., because it will decay to a pointer). + /// + /// \param OverrideExisting Whether to override an existing, locally-specified + /// nullability specifier rather than complaining about the conflict. + /// + /// \returns true if nullability cannot be applied, false otherwise. + bool CheckImplicitNullabilityTypeSpecifier(QualType &Type, + NullabilityKind Nullability, + SourceLocation DiagLoc, + bool AllowArrayTypes, + bool OverrideExisting); + /// Process the attributes before creating an attributed statement. Returns /// the semantic attributes that have been processed. void ProcessStmtAttributes(Stmt *Stmt, const ParsedAttributes &InAttrs, @@ -7110,15 +7144,7 @@ public: NestedNameSpecInfo &IdInfo, bool EnteringContext); - /// The kind of conversion to check for. Either all attributes must match exactly, - /// or the converted type may add/drop '__arm_preserves_za'. - enum class AArch64SMECallConversionKind { - MatchExactly, - MayAddPreservesZA, - MayDropPreservesZA, - }; - bool IsInvalidSMECallConversion(QualType FromType, QualType ToType, - AArch64SMECallConversionKind C); + bool IsInvalidSMECallConversion(QualType FromType, QualType ToType); /// The parser has parsed a nested-name-specifier /// 'template[opt] template-name < template-args >::'. @@ -8569,8 +8595,8 @@ public: QualType ParamType, SourceLocation Loc); ExprResult - BuildExpressionFromIntegralTemplateArgument(const TemplateArgument &Arg, - SourceLocation Loc); + BuildExpressionFromNonTypeTemplateArgument(const TemplateArgument &Arg, + SourceLocation Loc); /// Enumeration describing how template parameter lists are compared /// for equality. @@ -11223,6 +11249,11 @@ public: VarDecl *buildCoroutinePromise(SourceLocation Loc); void CheckCompletedCoroutineBody(FunctionDecl *FD, Stmt *&Body); + // Heuristically tells if the function is `get_return_object` member of a + // coroutine promise_type by matching the function name. + static bool CanBeGetReturnObject(const FunctionDecl *FD); + static bool CanBeGetReturnTypeOnAllocFailure(const FunctionDecl *FD); + // As a clang extension, enforces that a non-coroutine function must be marked // with [[clang::coro_wrapper]] if it returns a type marked with // [[clang::coro_return_type]]. @@ -13901,8 +13932,9 @@ private: bool SemaBuiltinVAStart(unsigned BuiltinID, CallExpr *TheCall); bool SemaBuiltinVAStartARMMicrosoft(CallExpr *Call); - bool SemaBuiltinUnorderedCompare(CallExpr *TheCall); - bool SemaBuiltinFPClassification(CallExpr *TheCall, unsigned NumArgs); + bool SemaBuiltinUnorderedCompare(CallExpr *TheCall, unsigned BuiltinID); + bool SemaBuiltinFPClassification(CallExpr *TheCall, unsigned NumArgs, + unsigned BuiltinID); bool SemaBuiltinComplex(CallExpr *TheCall); bool SemaBuiltinVSX(CallExpr *TheCall); bool SemaBuiltinOSLogFormat(CallExpr *TheCall); @@ -14006,6 +14038,8 @@ private: SourceRange range, llvm::SmallBitVector &CheckedVarArgs); + void CheckInfNaNFunction(const CallExpr *Call, const FunctionDecl *FDecl); + void CheckAbsoluteValueFunction(const CallExpr *Call, const FunctionDecl *FDecl); diff --git a/clang/include/clang/Serialization/ASTReader.h b/clang/include/clang/Serialization/ASTReader.h index 21d791f5cd8..dd1451bbf2d 100644 --- a/clang/include/clang/Serialization/ASTReader.h +++ b/clang/include/clang/Serialization/ASTReader.h @@ -550,6 +550,10 @@ private: /// declaration and the value is the deduced return type. llvm::SmallMapVector PendingDeducedTypeUpdates; + /// Functions has undededuced return type and we wish we can find the deduced + /// return type by iterating the redecls in other modules. + llvm::SmallVector PendingUndeducedFunctionDecls; + /// Declarations that have been imported and have typedef names for /// linkage purposes. llvm::DenseMap, NamedDecl *> diff --git a/clang/include/clang/Support/RISCVVIntrinsicUtils.h b/clang/include/clang/Support/RISCVVIntrinsicUtils.h index c525d344333..05a5e02e139 100644 --- a/clang/include/clang/Support/RISCVVIntrinsicUtils.h +++ b/clang/include/clang/Support/RISCVVIntrinsicUtils.h @@ -488,7 +488,7 @@ public: enum RVVRequire : uint32_t { RVV_REQ_None = 0, RVV_REQ_RV64 = 1 << 0, - RVV_REQ_ZvfhminOrZvfh = 1 << 1, + RVV_REQ_Zvfhmin = 1 << 1, RVV_REQ_Xsfvcp = 1 << 2, RVV_REQ_Xsfvfnrclipxfqf = 1 << 3, RVV_REQ_Xsfvfwmaccqqq = 1 << 4, diff --git a/clang/lib/ARCMigrate/FileRemapper.cpp b/clang/lib/ARCMigrate/FileRemapper.cpp index 7abc862ceec..84024c3bafd 100644 --- a/clang/lib/ARCMigrate/FileRemapper.cpp +++ b/clang/lib/ARCMigrate/FileRemapper.cpp @@ -43,7 +43,7 @@ std::string FileRemapper::getRemapInfoFile(StringRef outputDir) { assert(!outputDir.empty()); SmallString<128> InfoFile = outputDir; llvm::sys::path::append(InfoFile, "remap"); - return std::string(InfoFile.str()); + return std::string(InfoFile); } bool FileRemapper::initFromDisk(StringRef outputDir, DiagnosticsEngine &Diag, diff --git a/clang/lib/ARCMigrate/ObjCMT.cpp b/clang/lib/ARCMigrate/ObjCMT.cpp index ed363a46a20..0786c81516b 100644 --- a/clang/lib/ARCMigrate/ObjCMT.cpp +++ b/clang/lib/ARCMigrate/ObjCMT.cpp @@ -2201,7 +2201,7 @@ static std::string applyEditsToTemp(FileEntryRef FE, TmpOut.write(NewText.data(), NewText.size()); TmpOut.close(); - return std::string(TempPath.str()); + return std::string(TempPath); } bool arcmt::getFileRemappingsFromFileList( diff --git a/clang/lib/AST/ASTContext.cpp b/clang/lib/AST/ASTContext.cpp index d9cefcaa84d..5eb7aa36645 100644 --- a/clang/lib/AST/ASTContext.cpp +++ b/clang/lib/AST/ASTContext.cpp @@ -4484,10 +4484,11 @@ QualType ASTContext::getFunctionTypeInternal( EPI.ExceptionSpec.Type, EPI.ExceptionSpec.Exceptions.size()); size_t Size = FunctionProtoType::totalSizeToAlloc< QualType, SourceLocation, FunctionType::FunctionTypeExtraBitfields, - FunctionType::ExceptionType, Expr *, FunctionDecl *, - FunctionProtoType::ExtParameterInfo, Qualifiers>( + FunctionType::FunctionTypeArmAttributes, FunctionType::ExceptionType, + Expr *, FunctionDecl *, FunctionProtoType::ExtParameterInfo, Qualifiers>( NumArgs, EPI.Variadic, EPI.requiresFunctionProtoTypeExtraBitfields(), - ESH.NumExceptionType, ESH.NumExprPtr, ESH.NumFunctionDeclPtr, + EPI.requiresFunctionProtoTypeArmAttributes(), ESH.NumExceptionType, + ESH.NumExprPtr, ESH.NumFunctionDeclPtr, EPI.ExtParameterInfos ? NumArgs : 0, EPI.TypeQuals.hasNonFastQualifiers() ? 1 : 0); @@ -6753,6 +6754,11 @@ ASTContext::getCanonicalTemplateArgument(const TemplateArgument &Arg) const { case TemplateArgument::Integral: return TemplateArgument(Arg, getCanonicalType(Arg.getIntegralType())); + case TemplateArgument::StructuralValue: + return TemplateArgument(*this, + getCanonicalType(Arg.getStructuralValueType()), + Arg.getAsStructuralValue()); + case TemplateArgument::Type: return TemplateArgument(getCanonicalType(Arg.getAsType()), /*isNullPtr*/ false, Arg.getIsDefaulted()); diff --git a/clang/lib/AST/ASTImporter.cpp b/clang/lib/AST/ASTImporter.cpp index b762d6a4cd3..12734d62ed9 100644 --- a/clang/lib/AST/ASTImporter.cpp +++ b/clang/lib/AST/ASTImporter.cpp @@ -823,6 +823,17 @@ ASTNodeImporter::import(const TemplateArgument &From) { From.getIsDefaulted()); } + case TemplateArgument::StructuralValue: { + ExpectedType ToTypeOrErr = import(From.getStructuralValueType()); + if (!ToTypeOrErr) + return ToTypeOrErr.takeError(); + Expected ToValueOrErr = import(From.getAsStructuralValue()); + if (!ToValueOrErr) + return ToValueOrErr.takeError(); + return TemplateArgument(Importer.getToContext(), *ToTypeOrErr, + *ToValueOrErr); + } + case TemplateArgument::Template: { Expected ToTemplateOrErr = import(From.getAsTemplate()); if (!ToTemplateOrErr) @@ -3572,6 +3583,8 @@ private: case TemplateArgument::NullPtr: // FIXME: The type is not allowed to be in the function? return CheckType(Arg.getNullPtrType()); + case TemplateArgument::StructuralValue: + return CheckType(Arg.getStructuralValueType()); case TemplateArgument::Pack: for (const auto &PackArg : Arg.getPackAsArray()) if (checkTemplateArgument(PackArg)) @@ -3896,7 +3909,7 @@ ExpectedDecl ASTNodeImporter::VisitFunctionDecl(FunctionDecl *D) { ToFunction->setLexicalDeclContext(LexicalDC); ToFunction->setVirtualAsWritten(D->isVirtualAsWritten()); ToFunction->setTrivial(D->isTrivial()); - ToFunction->setPure(D->isPure()); + ToFunction->setIsPureVirtual(D->isPureVirtual()); ToFunction->setDefaulted(D->isDefaulted()); ToFunction->setExplicitlyDefaulted(D->isExplicitlyDefaulted()); ToFunction->setDeletedAsWritten(D->isDeletedAsWritten()); @@ -6280,17 +6293,21 @@ ExpectedDecl ASTNodeImporter::VisitVarTemplateDecl(VarTemplateDecl *D) { D->getTemplatedDecl())) continue; if (IsStructuralMatch(D, FoundTemplate)) { - // The Decl in the "From" context has a definition, but in the - // "To" context we already have a definition. + // FIXME Check for ODR error if the two definitions have + // different initializers? VarTemplateDecl *FoundDef = getTemplateDefinition(FoundTemplate); - if (D->isThisDeclarationADefinition() && FoundDef) - // FIXME Check for ODR error if the two definitions have - // different initializers? - return Importer.MapImported(D, FoundDef); - if (FoundTemplate->getDeclContext()->isRecord() && - D->getDeclContext()->isRecord()) - return Importer.MapImported(D, FoundTemplate); - + if (D->getDeclContext()->isRecord()) { + assert(FoundTemplate->getDeclContext()->isRecord() && + "Member variable template imported as non-member, " + "inconsistent imported AST?"); + if (FoundDef) + return Importer.MapImported(D, FoundDef); + if (!D->isThisDeclarationADefinition()) + return Importer.MapImported(D, FoundTemplate); + } else { + if (FoundDef && D->isThisDeclarationADefinition()) + return Importer.MapImported(D, FoundDef); + } FoundByLookup = FoundTemplate; break; } diff --git a/clang/lib/AST/ASTStructuralEquivalence.cpp b/clang/lib/AST/ASTStructuralEquivalence.cpp index a9e0d1698a9..be7a850a298 100644 --- a/clang/lib/AST/ASTStructuralEquivalence.cpp +++ b/clang/lib/AST/ASTStructuralEquivalence.cpp @@ -98,6 +98,8 @@ static bool IsStructurallyEquivalent(StructuralEquivalenceContext &Context, QualType T1, QualType T2); static bool IsStructurallyEquivalent(StructuralEquivalenceContext &Context, Decl *D1, Decl *D2); +static bool IsStructurallyEquivalent(StructuralEquivalenceContext &Context, + const Stmt *S1, const Stmt *S2); static bool IsStructurallyEquivalent(StructuralEquivalenceContext &Context, const TemplateArgument &Arg1, const TemplateArgument &Arg2); @@ -437,12 +439,67 @@ public: }; } // namespace +static bool IsStructurallyEquivalent(StructuralEquivalenceContext &Context, + const UnaryOperator *E1, + const CXXOperatorCallExpr *E2) { + return UnaryOperator::getOverloadedOperator(E1->getOpcode()) == + E2->getOperator() && + IsStructurallyEquivalent(Context, E1->getSubExpr(), E2->getArg(0)); +} + +static bool IsStructurallyEquivalent(StructuralEquivalenceContext &Context, + const CXXOperatorCallExpr *E1, + const UnaryOperator *E2) { + return E1->getOperator() == + UnaryOperator::getOverloadedOperator(E2->getOpcode()) && + IsStructurallyEquivalent(Context, E1->getArg(0), E2->getSubExpr()); +} + +static bool IsStructurallyEquivalent(StructuralEquivalenceContext &Context, + const BinaryOperator *E1, + const CXXOperatorCallExpr *E2) { + return BinaryOperator::getOverloadedOperator(E1->getOpcode()) == + E2->getOperator() && + IsStructurallyEquivalent(Context, E1->getLHS(), E2->getArg(0)) && + IsStructurallyEquivalent(Context, E1->getRHS(), E2->getArg(1)); +} + +static bool IsStructurallyEquivalent(StructuralEquivalenceContext &Context, + const CXXOperatorCallExpr *E1, + const BinaryOperator *E2) { + return E1->getOperator() == + BinaryOperator::getOverloadedOperator(E2->getOpcode()) && + IsStructurallyEquivalent(Context, E1->getArg(0), E2->getLHS()) && + IsStructurallyEquivalent(Context, E1->getArg(1), E2->getRHS()); +} + /// Determine structural equivalence of two statements. static bool IsStructurallyEquivalent(StructuralEquivalenceContext &Context, const Stmt *S1, const Stmt *S2) { if (!S1 || !S2) return S1 == S2; + // Check for statements with similar syntax but different AST. + // A UnaryOperator node is more lightweight than a CXXOperatorCallExpr node. + // The more heavyweight node is only created if the definition-time name + // lookup had any results. The lookup results are stored CXXOperatorCallExpr + // only. The lookup results can be different in a "From" and "To" AST even if + // the compared structure is otherwise equivalent. For this reason we must + // treat a similar unary/binary operator node and CXXOperatorCall node as + // equivalent. + if (const auto *E2CXXOperatorCall = dyn_cast(S2)) { + if (const auto *E1Unary = dyn_cast(S1)) + return IsStructurallyEquivalent(Context, E1Unary, E2CXXOperatorCall); + if (const auto *E1Binary = dyn_cast(S1)) + return IsStructurallyEquivalent(Context, E1Binary, E2CXXOperatorCall); + } + if (const auto *E1CXXOperatorCall = dyn_cast(S1)) { + if (const auto *E2Unary = dyn_cast(S2)) + return IsStructurallyEquivalent(Context, E1CXXOperatorCall, E2Unary); + if (const auto *E2Binary = dyn_cast(S2)) + return IsStructurallyEquivalent(Context, E1CXXOperatorCall, E2Binary); + } + // Compare the statements itself. StmtComparer Comparer(Context); if (!Comparer.IsEquivalent(S1, S2)) @@ -628,6 +685,9 @@ static bool IsStructurallyEquivalent(StructuralEquivalenceContext &Context, return IsStructurallyEquivalent(Context, Arg1.getAsExpr(), Arg2.getAsExpr()); + case TemplateArgument::StructuralValue: + return Arg1.structurallyEquals(Arg2); + case TemplateArgument::Pack: return IsStructurallyEquivalent(Context, Arg1.pack_elements(), Arg2.pack_elements()); @@ -1410,7 +1470,7 @@ static bool IsStructurallyEquivalent(StructuralEquivalenceContext &Context, Method1->isConst() == Method2->isConst() && Method1->isVolatile() == Method2->isVolatile() && Method1->isVirtual() == Method2->isVirtual() && - Method1->isPure() == Method2->isPure() && + Method1->isPureVirtual() == Method2->isPureVirtual() && Method1->isDefaulted() == Method2->isDefaulted() && Method1->isDeleted() == Method2->isDeleted(); if (!PropertiesEqual) diff --git a/clang/lib/AST/Decl.cpp b/clang/lib/AST/Decl.cpp index e1440e5183a..26fdfa04079 100644 --- a/clang/lib/AST/Decl.cpp +++ b/clang/lib/AST/Decl.cpp @@ -343,6 +343,10 @@ LinkageComputer::getLVForTemplateArgumentList(ArrayRef Args, LV.merge(getTypeLinkageAndVisibility(Arg.getNullPtrType())); continue; + case TemplateArgument::StructuralValue: + LV.merge(getLVForValue(Arg.getAsStructuralValue(), computation)); + continue; + case TemplateArgument::Template: case TemplateArgument::TemplateExpansion: if (TemplateDecl *Template = @@ -3036,7 +3040,7 @@ FunctionDecl::FunctionDecl(Kind DK, ASTContext &C, DeclContext *DC, FunctionDeclBits.IsInline = isInlineSpecified; FunctionDeclBits.IsInlineSpecified = isInlineSpecified; FunctionDeclBits.IsVirtualAsWritten = false; - FunctionDeclBits.IsPure = false; + FunctionDeclBits.IsPureVirtual = false; FunctionDeclBits.HasInheritedPrototype = false; FunctionDeclBits.HasWrittenPrototype = true; FunctionDeclBits.IsDeleted = false; @@ -3203,8 +3207,8 @@ void FunctionDecl::setBody(Stmt *B) { EndRangeLoc = B->getEndLoc(); } -void FunctionDecl::setPure(bool P) { - FunctionDeclBits.IsPure = P; +void FunctionDecl::setIsPureVirtual(bool P) { + FunctionDeclBits.IsPureVirtual = P; if (P) if (auto *Parent = dyn_cast(getDeclContext())) Parent->markedVirtualFunctionPure(); @@ -5369,16 +5373,23 @@ void CapturedDecl::setBody(Stmt *B) { BodyAndNothrow.setPointer(B); } bool CapturedDecl::isNothrow() const { return BodyAndNothrow.getInt(); } void CapturedDecl::setNothrow(bool Nothrow) { BodyAndNothrow.setInt(Nothrow); } +EnumConstantDecl::EnumConstantDecl(const ASTContext &C, DeclContext *DC, + SourceLocation L, IdentifierInfo *Id, + QualType T, Expr *E, const llvm::APSInt &V) + : ValueDecl(EnumConstant, DC, L, Id, T), Init((Stmt *)E) { + setInitVal(C, V); +} + EnumConstantDecl *EnumConstantDecl::Create(ASTContext &C, EnumDecl *CD, SourceLocation L, IdentifierInfo *Id, QualType T, Expr *E, const llvm::APSInt &V) { - return new (C, CD) EnumConstantDecl(CD, L, Id, T, E, V); + return new (C, CD) EnumConstantDecl(C, CD, L, Id, T, E, V); } EnumConstantDecl * EnumConstantDecl::CreateDeserialized(ASTContext &C, unsigned ID) { - return new (C, ID) EnumConstantDecl(nullptr, SourceLocation(), nullptr, + return new (C, ID) EnumConstantDecl(C, nullptr, SourceLocation(), nullptr, QualType(), nullptr, llvm::APSInt()); } diff --git a/clang/lib/AST/DeclCXX.cpp b/clang/lib/AST/DeclCXX.cpp index 98b0a6dc28e..117e802dae2 100644 --- a/clang/lib/AST/DeclCXX.cpp +++ b/clang/lib/AST/DeclCXX.cpp @@ -1383,6 +1383,31 @@ void CXXRecordDecl::addedMember(Decl *D) { } } +bool CXXRecordDecl::isLiteral() const { + const LangOptions &LangOpts = getLangOpts(); + if (!(LangOpts.CPlusPlus20 ? hasConstexprDestructor() + : hasTrivialDestructor())) + return false; + + if (hasNonLiteralTypeFieldsOrBases()) { + // CWG2598 + // is an aggregate union type that has either no variant + // members or at least one variant member of non-volatile literal type, + if (!isUnion()) + return false; + bool HasAtLeastOneLiteralMember = + fields().empty() || any_of(fields(), [this](const FieldDecl *D) { + return !D->getType().isVolatileQualified() && + D->getType()->isLiteralType(getASTContext()); + }); + if (!HasAtLeastOneLiteralMember) + return false; + } + + return isAggregate() || (isLambda() && LangOpts.CPlusPlus17) || + hasConstexprNonCopyMoveConstructor() || hasTrivialDefaultConstructor(); +} + void CXXRecordDecl::addedSelectedDestructor(CXXDestructorDecl *DD) { DD->setIneligibleOrNotSelected(false); addedEligibleSpecialMemberFunction(DD, SMF_Destructor); @@ -2054,7 +2079,7 @@ void CXXRecordDecl::completeDefinition(CXXFinalOverriderMap *FinalOverriders) { // A class is abstract if it contains or inherits at least one // pure virtual function for which the final overrider is pure // virtual. - if (SO->second.front().Method->isPure()) { + if (SO->second.front().Method->isPureVirtual()) { data().Abstract = true; Done = true; break; @@ -2273,7 +2298,7 @@ CXXMethodDecl *CXXMethodDecl::getDevirtualizedMethod(const Expr *Base, // If the member function is marked 'final', we know that it can't be // overridden and can therefore devirtualize it unless it's pure virtual. if (hasAttr()) - return isPure() ? nullptr : this; + return isPureVirtual() ? nullptr : this; // If Base is unknown, we cannot devirtualize. if (!Base) @@ -2302,7 +2327,7 @@ CXXMethodDecl *CXXMethodDecl::getDevirtualizedMethod(const Expr *Base, // If that method is pure virtual, we can't devirtualize. If this code is // reached, the result would be UB, not a direct call to the derived class // function, and we can't assume the derived class function is defined. - if (DevirtualizedMethod->isPure()) + if (DevirtualizedMethod->isPureVirtual()) return nullptr; // If that method is marked final, we can devirtualize it. diff --git a/clang/lib/AST/DeclPrinter.cpp b/clang/lib/AST/DeclPrinter.cpp index 24da6f2ef32..822ac12c4c7 100644 --- a/clang/lib/AST/DeclPrinter.cpp +++ b/clang/lib/AST/DeclPrinter.cpp @@ -871,7 +871,7 @@ void DeclPrinter::VisitFunctionDecl(FunctionDecl *D) { prettyPrintAttributes(D, Out, AttrPrintLoc::Right); - if (D->isPure()) + if (D->isPureVirtual()) Out << " = 0"; else if (D->isDeletedAsWritten()) Out << " = delete"; diff --git a/clang/lib/AST/Expr.cpp b/clang/lib/AST/Expr.cpp index b125fc676da..f1efa98e175 100644 --- a/clang/lib/AST/Expr.cpp +++ b/clang/lib/AST/Expr.cpp @@ -690,7 +690,7 @@ std::string PredefinedExpr::ComputeName(PredefinedIdentKind IK, if (!Buffer.empty() && Buffer.front() == '\01') return std::string(Buffer.substr(1)); - return std::string(Buffer.str()); + return std::string(Buffer); } return std::string(ND->getIdentifier()->getName()); } @@ -986,7 +986,7 @@ std::string FixedPointLiteral::getValueAsString(unsigned Radix) const { SmallString<64> S; FixedPointValueToString( S, llvm::APSInt::getUnsigned(getValue().getZExtValue()), Scale); - return std::string(S.str()); + return std::string(S); } void CharacterLiteral::print(unsigned Val, CharacterLiteralKind Kind, @@ -2219,7 +2219,10 @@ SourceLocExpr::SourceLocExpr(const ASTContext &Ctx, SourceLocIdentKind Kind, : Expr(SourceLocExprClass, ResultTy, VK_PRValue, OK_Ordinary), BuiltinLoc(BLoc), RParenLoc(RParenLoc), ParentContext(ParentContext) { SourceLocExprBits.Kind = llvm::to_underlying(Kind); - setDependence(ExprDependence::None); + // In dependent contexts, function names may change. + setDependence(MayBeDependent(Kind) && ParentContext->isDependentContext() + ? ExprDependence::Value + : ExprDependence::None); } StringRef SourceLocExpr::getBuiltinStr() const { diff --git a/clang/lib/AST/ExprCXX.cpp b/clang/lib/AST/ExprCXX.cpp index 83af7998f68..e61c11dffd8 100644 --- a/clang/lib/AST/ExprCXX.cpp +++ b/clang/lib/AST/ExprCXX.cpp @@ -194,14 +194,14 @@ CXXNewExpr::CXXNewExpr(bool IsGlobalNew, FunctionDecl *OperatorNew, DirectInitRange(DirectInitRange) { assert((Initializer != nullptr || - InitializationStyle == CXXNewInitializationStyle::None || - InitializationStyle == CXXNewInitializationStyle::Implicit) && - "Only NoInit can have no initializer!"); + InitializationStyle == CXXNewInitializationStyle::None) && + "Only CXXNewInitializationStyle::None can have no initializer!"); CXXNewExprBits.IsGlobalNew = IsGlobalNew; CXXNewExprBits.IsArray = ArraySize.has_value(); CXXNewExprBits.ShouldPassAlignment = ShouldPassAlignment; CXXNewExprBits.UsualArrayDeleteWantsSize = UsualArrayDeleteWantsSize; + CXXNewExprBits.HasInitializer = Initializer != nullptr; CXXNewExprBits.StoredInitializationStyle = llvm::to_underlying(InitializationStyle); bool IsParenTypeId = TypeIdParens.isValid(); @@ -219,10 +219,10 @@ CXXNewExpr::CXXNewExpr(bool IsGlobalNew, FunctionDecl *OperatorNew, getTrailingObjects()[0] = TypeIdParens; switch (getInitializationStyle()) { - case CXXNewInitializationStyle::Call: + case CXXNewInitializationStyle::Parens: this->Range.setEnd(DirectInitRange.getEnd()); break; - case CXXNewInitializationStyle::List: + case CXXNewInitializationStyle::Braces: this->Range.setEnd(getInitializer()->getSourceRange().getEnd()); break; default: diff --git a/clang/lib/AST/ExprConstant.cpp b/clang/lib/AST/ExprConstant.cpp index f6aeee1a4e9..f1d07d022b2 100644 --- a/clang/lib/AST/ExprConstant.cpp +++ b/clang/lib/AST/ExprConstant.cpp @@ -5839,7 +5839,7 @@ static const CXXMethodDecl *HandleVirtualDispatch( // C++2a [class.abstract]p6: // the effect of making a virtual call to a pure virtual function [...] is // undefined - if (Callee->isPure()) { + if (Callee->isPureVirtual()) { Info.FFDiag(E, diag::note_constexpr_pure_virtual_call, 1) << Callee; Info.Note(Callee->getLocation(), diag::note_declared_at); return nullptr; @@ -15439,11 +15439,13 @@ static bool EvaluateAsRValue(EvalInfo &Info, const Expr *E, APValue &Result) { if (Info.EnableNewConstInterp) { if (!Info.Ctx.getInterpContext().evaluateAsRValue(Info, E, Result)) return false; - } else { - if (!::Evaluate(Result, Info, E)) - return false; + return CheckConstantExpression(Info, E->getExprLoc(), E->getType(), Result, + ConstantExprKind::Normal); } + if (!::Evaluate(Result, Info, E)) + return false; + // Implicit lvalue-to-rvalue cast. if (E->isGLValue()) { LValue LV; @@ -15671,6 +15673,13 @@ bool Expr::EvaluateAsConstantExpr(EvalResult &Result, const ASTContext &Ctx, EvalInfo Info(Ctx, Result, EM); Info.InConstantContext = true; + if (Info.EnableNewConstInterp) { + if (!Info.Ctx.getInterpContext().evaluate(Info, this, Result.Val)) + return false; + return CheckConstantExpression(Info, getExprLoc(), + getStorageType(Ctx, this), Result.Val, Kind); + } + // The type of the object we're initializing is 'const T' for a class NTTP. QualType T = getType(); if (Kind == ConstantExprKind::ClassTemplateArgument) @@ -15746,18 +15755,36 @@ bool Expr::EvaluateAsInitializer(APValue &Value, const ASTContext &Ctx, Info.setEvaluatingDecl(VD, Value); Info.InConstantContext = IsConstantInitialization; + SourceLocation DeclLoc = VD->getLocation(); + QualType DeclTy = VD->getType(); + if (Info.EnableNewConstInterp) { auto &InterpCtx = const_cast(Ctx).getInterpContext(); if (!InterpCtx.evaluateAsInitializer(Info, VD, Value)) return false; + + return CheckConstantExpression(Info, DeclLoc, DeclTy, Value, + ConstantExprKind::Normal); } else { LValue LVal; LVal.set(VD); - if (!EvaluateInPlace(Value, Info, LVal, this, - /*AllowNonLiteralTypes=*/true) || - EStatus.HasSideEffects) - return false; + { + // C++23 [intro.execution]/p5 + // A full-expression is ... an init-declarator ([dcl.decl]) or a + // mem-initializer. + // So we need to make sure temporary objects are destroyed after having + // evaluated the expression (per C++23 [class.temporary]/p4). + // + // FIXME: Otherwise this may break test/Modules/pr68702.cpp because the + // serialization code calls ParmVarDecl::getDefaultArg() which strips the + // outermost FullExpr, such as ExprWithCleanups. + FullExpressionRAII Scope(Info); + if (!EvaluateInPlace(Value, Info, LVal, this, + /*AllowNonLiteralTypes=*/true) || + EStatus.HasSideEffects) + return false; + } // At this point, any lifetime-extended temporaries are completely // initialized. @@ -15767,8 +15794,6 @@ bool Expr::EvaluateAsInitializer(APValue &Value, const ASTContext &Ctx, llvm_unreachable("Unhandled cleanup; missing full expression marker?"); } - SourceLocation DeclLoc = VD->getLocation(); - QualType DeclTy = VD->getType(); return CheckConstantExpression(Info, DeclLoc, DeclTy, Value, ConstantExprKind::Normal) && CheckMemoryLeaks(Info); diff --git a/clang/lib/AST/Interp/ByteCodeEmitter.cpp b/clang/lib/AST/Interp/ByteCodeEmitter.cpp index 045263447cb..fd2a92d9d3f 100644 --- a/clang/lib/AST/Interp/ByteCodeEmitter.cpp +++ b/clang/lib/AST/Interp/ByteCodeEmitter.cpp @@ -20,8 +20,7 @@ using namespace clang; using namespace clang::interp; -Expected -ByteCodeEmitter::compileFunc(const FunctionDecl *FuncDecl) { +Function *ByteCodeEmitter::compileFunc(const FunctionDecl *FuncDecl) { // Set up argument indices. unsigned ParamOffset = 0; SmallVector ParamTypes; @@ -120,10 +119,6 @@ ByteCodeEmitter::compileFunc(const FunctionDecl *FuncDecl) { // Compile the function body. if (!IsEligibleForCompilation || !visitFunc(FuncDecl)) { - // Return a dummy function if compilation failed. - if (BailLocation) - return llvm::make_error(*BailLocation); - Func->setIsFullyCompiled(true); return Func; } @@ -183,12 +178,6 @@ int32_t ByteCodeEmitter::getOffset(LabelTy Label) { return 0ull; } -bool ByteCodeEmitter::bail(const SourceLocation &Loc) { - if (!BailLocation) - BailLocation = Loc; - return false; -} - /// Helper to write bytecode and bail out if 32-bit offsets become invalid. /// Pointers will be automatically marshalled as 32-bit IDs. template diff --git a/clang/lib/AST/Interp/ByteCodeEmitter.h b/clang/lib/AST/Interp/ByteCodeEmitter.h index 5520f8c3006..03de286582c 100644 --- a/clang/lib/AST/Interp/ByteCodeEmitter.h +++ b/clang/lib/AST/Interp/ByteCodeEmitter.h @@ -17,7 +17,6 @@ #include "PrimType.h" #include "Program.h" #include "Source.h" -#include "llvm/Support/Error.h" namespace clang { namespace interp { @@ -32,7 +31,7 @@ protected: public: /// Compiles the function into the module. - llvm::Expected compileFunc(const FunctionDecl *FuncDecl); + Function *compileFunc(const FunctionDecl *FuncDecl); protected: ByteCodeEmitter(Context &Ctx, Program &P) : Ctx(Ctx), P(P) {} @@ -49,11 +48,6 @@ protected: virtual bool visitExpr(const Expr *E) = 0; virtual bool visitDecl(const VarDecl *E) = 0; - /// Bails out if a given node cannot be compiled. - bool bail(const Stmt *S) { return bail(S->getBeginLoc()); } - bool bail(const Decl *D) { return bail(D->getBeginLoc()); } - bool bail(const SourceLocation &Loc); - /// Emits jumps. bool jumpTrue(const LabelTy &Label); bool jumpFalse(const LabelTy &Label); @@ -81,8 +75,6 @@ private: LabelTy NextLabel = 0; /// Offset of the next local variable. unsigned NextLocalOffset = 0; - /// Location of a failure. - std::optional BailLocation; /// Label information for linker. llvm::DenseMap LabelOffsets; /// Location of label relocations. diff --git a/clang/lib/AST/Interp/ByteCodeExprGen.cpp b/clang/lib/AST/Interp/ByteCodeExprGen.cpp index 7f8bbe78732..cfcef067b92 100644 --- a/clang/lib/AST/Interp/ByteCodeExprGen.cpp +++ b/clang/lib/AST/Interp/ByteCodeExprGen.cpp @@ -287,6 +287,33 @@ bool ByteCodeExprGen::VisitCastExpr(const CastExpr *CE) { return true; } + case CK_IntegralComplexToReal: + case CK_FloatingComplexToReal: + return this->emitComplexReal(SubExpr); + + case CK_IntegralRealToComplex: + case CK_FloatingRealToComplex: { + // We're creating a complex value here, so we need to + // allocate storage for it. + if (!Initializing) { + std::optional LocalIndex = + allocateLocal(CE, /*IsExtended=*/true); + if (!LocalIndex) + return false; + if (!this->emitGetPtrLocal(*LocalIndex, CE)) + return false; + } + + // Init the complex value to {SubExpr, 0}. + if (!this->visitArrayElemInit(0, SubExpr)) + return false; + // Zero-init the second element. + PrimType T = classifyPrim(SubExpr->getType()); + if (!this->visitZeroInitializer(T, SubExpr->getType(), SubExpr)) + return false; + return this->emitInitElem(T, 1, SubExpr); + } + case CK_ToVoid: return discard(SubExpr); @@ -371,7 +398,7 @@ bool ByteCodeExprGen::VisitBinaryOperator(const BinaryOperator *BO) { } if (!LT || !RT || !T) - return this->bail(BO); + return false; // Pointer arithmetic special case. if (BO->getOpcode() == BO_Add || BO->getOpcode() == BO_Sub) { @@ -451,7 +478,7 @@ bool ByteCodeExprGen::VisitBinaryOperator(const BinaryOperator *BO) { case BO_LAnd: llvm_unreachable("Already handled earlier"); default: - return this->bail(BO); + return false; } llvm_unreachable("Unhandled binary op"); @@ -504,7 +531,7 @@ bool ByteCodeExprGen::VisitPointerArithBinOp(const BinaryOperator *E) { else if (Op == BO_Sub) return this->emitSubOffset(OffsetType, E); - return this->bail(E); + return false; } template @@ -842,6 +869,10 @@ bool ByteCodeExprGen::VisitInitListExpr(const InitListExpr *E) { if (T->isAnyComplexType()) { unsigned NumInits = E->getNumInits(); + + if (NumInits == 1) + return this->delegate(E->inits()[0]); + QualType ElemQT = E->getType()->getAs()->getElementType(); PrimType ElemT = classifyPrim(ElemQT); if (NumInits == 0) { @@ -2030,7 +2061,7 @@ bool ByteCodeExprGen::dereference( } if (LV->getType()->isAnyComplexType()) - return visit(LV); + return this->delegate(LV); return false; } @@ -2337,7 +2368,7 @@ bool ByteCodeExprGen::visitDecl(const VarDecl *VD) { auto GlobalIndex = P.getGlobal(VD); assert(GlobalIndex); // visitVarDecl() didn't return false. if (VarT) { - if (!this->emitGetGlobal(*VarT, *GlobalIndex, VD)) + if (!this->emitGetGlobalUnchecked(*VarT, *GlobalIndex, VD)) return false; } else { if (!this->emitGetPtrGlobal(*GlobalIndex, VD)) @@ -2358,7 +2389,9 @@ bool ByteCodeExprGen::visitDecl(const VarDecl *VD) { // Return the value if (VarT) return this->emitRet(*VarT, VD); - return this->emitRetValue(VD); + + // Return non-primitive values as pointers here. + return this->emitRet(PT_Ptr, VD); } template @@ -2378,7 +2411,7 @@ bool ByteCodeExprGen::visitVarDecl(const VarDecl *VD) { std::optional GlobalIndex = P.createGlobal(VD, Init); if (!GlobalIndex) - return this->bail(VD); + return false; assert(Init); { @@ -2767,23 +2800,16 @@ bool ByteCodeExprGen::VisitUnaryOperator(const UnaryOperator *E) { if (!this->visit(SubExpr)) return false; return DiscardResult ? this->emitPop(*T, E) : this->emitComp(*T, E); - case UO_Real: { // __real x - assert(!T); - if (!this->visit(SubExpr)) - return false; - if (!this->emitConstUint8(0, E)) - return false; - if (!this->emitArrayElemPtrPopUint8(E)) - return false; - - // Since our _Complex implementation does not map to a primitive type, - // we sometimes have to do the lvalue-to-rvalue conversion here manually. - if (!SubExpr->isLValue()) - return this->emitLoadPop(classifyPrim(E->getType()), E); - return true; - } + case UO_Real: // __real x + if (T) + return this->delegate(SubExpr); + return this->emitComplexReal(SubExpr); case UO_Imag: { // __imag x - assert(!T); + if (T) { + if (!this->discard(SubExpr)) + return false; + return this->visitZeroInitializer(*T, SubExpr->getType(), SubExpr); + } if (!this->visit(SubExpr)) return false; if (!this->emitConstUint8(1, E)) @@ -2948,10 +2974,32 @@ bool ByteCodeExprGen::emitPrimCast(PrimType FromT, PrimType ToT, return false; } +/// Emits __real(SubExpr) +template +bool ByteCodeExprGen::emitComplexReal(const Expr *SubExpr) { + assert(SubExpr->getType()->isAnyComplexType()); + + if (DiscardResult) + return this->discard(SubExpr); + + if (!this->visit(SubExpr)) + return false; + if (!this->emitConstUint8(0, SubExpr)) + return false; + if (!this->emitArrayElemPtrPopUint8(SubExpr)) + return false; + + // Since our _Complex implementation does not map to a primitive type, + // we sometimes have to do the lvalue-to-rvalue conversion here manually. + if (!SubExpr->isLValue()) + return this->emitLoadPop(*classifyComplexElementType(SubExpr->getType()), + SubExpr); + return true; +} + /// When calling this, we have a pointer of the local-to-destroy /// on the stack. /// Emit destruction of record types (or arrays of record types). -/// FIXME: Handle virtual destructors. template bool ByteCodeExprGen::emitRecordDestruction(const Descriptor *Desc) { assert(Desc); diff --git a/clang/lib/AST/Interp/ByteCodeExprGen.h b/clang/lib/AST/Interp/ByteCodeExprGen.h index bbb13e97e72..df4cb736299 100644 --- a/clang/lib/AST/Interp/ByteCodeExprGen.h +++ b/clang/lib/AST/Interp/ByteCodeExprGen.h @@ -191,10 +191,6 @@ protected: if (!visitInitializer(Init)) return false; - if ((Init->getType()->isArrayType() || Init->getType()->isRecordType()) && - !this->emitCheckGlobalCtor(Init)) - return false; - return this->emitPopPtr(Init); } @@ -294,6 +290,8 @@ private: return this->classify(ElemType); } + bool emitComplexReal(const Expr *SubExpr); + bool emitRecordDestruction(const Descriptor *Desc); unsigned collectBaseOffset(const RecordType *BaseType, const RecordType *DerivedType); diff --git a/clang/lib/AST/Interp/ByteCodeStmtGen.cpp b/clang/lib/AST/Interp/ByteCodeStmtGen.cpp index b1ab5fcf9cb..a2d8c4e1301 100644 --- a/clang/lib/AST/Interp/ByteCodeStmtGen.cpp +++ b/clang/lib/AST/Interp/ByteCodeStmtGen.cpp @@ -142,6 +142,27 @@ bool ByteCodeStmtGen::visitFunc(const FunctionDecl *F) { // Classify the return type. ReturnType = this->classify(F->getReturnType()); + auto emitFieldInitializer = [&](const Record::Field *F, unsigned FieldOffset, + const Expr *InitExpr) -> bool { + if (std::optional T = this->classify(InitExpr)) { + if (!this->visit(InitExpr)) + return false; + + if (F->isBitField()) + return this->emitInitThisBitField(*T, F, FieldOffset, InitExpr); + return this->emitInitThisField(*T, FieldOffset, InitExpr); + } + // Non-primitive case. Get a pointer to the field-to-initialize + // on the stack and call visitInitialzer() for it. + if (!this->emitGetPtrThisField(FieldOffset, InitExpr)) + return false; + + if (!this->visitInitializer(InitExpr)) + return false; + + return this->emitPopPtr(InitExpr); + }; + // Emit custom code if this is a lambda static invoker. if (const auto *MD = dyn_cast(F); MD && MD->isLambdaStaticInvoker()) @@ -162,29 +183,8 @@ bool ByteCodeStmtGen::visitFunc(const FunctionDecl *F) { if (const FieldDecl *Member = Init->getMember()) { const Record::Field *F = R->getField(Member); - if (std::optional T = this->classify(InitExpr)) { - if (!this->visit(InitExpr)) - return false; - - if (F->isBitField()) { - if (!this->emitInitThisBitField(*T, F, InitExpr)) - return false; - } else { - if (!this->emitInitThisField(*T, F->Offset, InitExpr)) - return false; - } - } else { - // Non-primitive case. Get a pointer to the field-to-initialize - // on the stack and call visitInitialzer() for it. - if (!this->emitGetPtrThisField(F->Offset, InitExpr)) - return false; - - if (!this->visitInitializer(InitExpr)) - return false; - - if (!this->emitPopPtr(InitExpr)) - return false; - } + if (!emitFieldInitializer(F, F->Offset, InitExpr)) + return false; } else if (const Type *Base = Init->getBaseClass()) { // Base class initializer. // Get This Base and call initializer on it. @@ -198,6 +198,26 @@ bool ByteCodeStmtGen::visitFunc(const FunctionDecl *F) { return false; if (!this->emitInitPtrPop(InitExpr)) return false; + } else if (const IndirectFieldDecl *IFD = Init->getIndirectMember()) { + assert(IFD->getChainingSize() >= 2); + + unsigned NestedFieldOffset = 0; + const Record::Field *NestedField = nullptr; + for (const NamedDecl *ND : IFD->chain()) { + const auto *FD = cast(ND); + const Record *FieldRecord = + this->P.getOrCreateRecord(FD->getParent()); + assert(FieldRecord); + + NestedField = FieldRecord->getField(FD); + assert(NestedField); + + NestedFieldOffset += NestedField->Offset; + } + assert(NestedField); + + if (!emitFieldInitializer(NestedField, NestedFieldOffset, InitExpr)) + return false; } else { assert(Init->isDelegatingInitializer()); if (!this->emitThis(InitExpr)) @@ -262,7 +282,7 @@ bool ByteCodeStmtGen::visitStmt(const Stmt *S) { default: { if (auto *Exp = dyn_cast(S)) return this->discard(Exp); - return this->bail(S); + return false; } } } diff --git a/clang/lib/AST/Interp/Context.cpp b/clang/lib/AST/Interp/Context.cpp index 17abb716358..75a300bcbac 100644 --- a/clang/lib/AST/Interp/Context.cpp +++ b/clang/lib/AST/Interp/Context.cpp @@ -30,18 +30,8 @@ Context::~Context() {} bool Context::isPotentialConstantExpr(State &Parent, const FunctionDecl *FD) { assert(Stk.empty()); Function *Func = P->getFunction(FD); - if (!Func || !Func->hasBody()) { - if (auto R = ByteCodeStmtGen(*this, *P).compileFunc(FD)) { - Func = *R; - } else { - handleAllErrors(R.takeError(), [&Parent](ByteCodeGenError &Err) { - Parent.FFDiag(Err.getRange().getBegin(), - diag::err_experimental_clang_interp_failed) - << Err.getRange(); - }); - return false; - } - } + if (!Func || !Func->hasBody()) + Func = ByteCodeStmtGen(*this, *P).compileFunc(FD); APValue DummyResult; if (!Run(Parent, Func, DummyResult)) { @@ -54,36 +44,90 @@ bool Context::isPotentialConstantExpr(State &Parent, const FunctionDecl *FD) { bool Context::evaluateAsRValue(State &Parent, const Expr *E, APValue &Result) { assert(Stk.empty()); ByteCodeExprGen C(*this, *P, Parent, Stk, Result); - if (Check(Parent, C.interpretExpr(E))) { - assert(Stk.empty()); -#ifndef NDEBUG - // Make sure we don't rely on some value being still alive in - // InterpStack memory. + + auto Res = C.interpretExpr(E); + + if (Res.isInvalid()) { Stk.clear(); -#endif - return true; + return false; } + assert(Stk.empty()); +#ifndef NDEBUG + // Make sure we don't rely on some value being still alive in + // InterpStack memory. Stk.clear(); - return false; +#endif + + // Implicit lvalue-to-rvalue conversion. + if (E->isGLValue()) { + std::optional RValueResult = Res.toRValue(); + if (!RValueResult) { + return false; + } + Result = *RValueResult; + } else { + Result = Res.toAPValue(); + } + + return true; +} + +bool Context::evaluate(State &Parent, const Expr *E, APValue &Result) { + assert(Stk.empty()); + ByteCodeExprGen C(*this, *P, Parent, Stk, Result); + + auto Res = C.interpretExpr(E); + if (Res.isInvalid()) { + Stk.clear(); + return false; + } + + assert(Stk.empty()); +#ifndef NDEBUG + // Make sure we don't rely on some value being still alive in + // InterpStack memory. + Stk.clear(); +#endif + Result = Res.toAPValue(); + return true; } bool Context::evaluateAsInitializer(State &Parent, const VarDecl *VD, APValue &Result) { assert(Stk.empty()); ByteCodeExprGen C(*this, *P, Parent, Stk, Result); - if (Check(Parent, C.interpretDecl(VD))) { - assert(Stk.empty()); -#ifndef NDEBUG - // Make sure we don't rely on some value being still alive in - // InterpStack memory. + + auto Res = C.interpretDecl(VD); + if (Res.isInvalid()) { Stk.clear(); -#endif - return true; + return false; } + assert(Stk.empty()); +#ifndef NDEBUG + // Make sure we don't rely on some value being still alive in + // InterpStack memory. Stk.clear(); - return false; +#endif + + // Ensure global variables are fully initialized. + if (shouldBeGloballyIndexed(VD) && !Res.isInvalid() && + (VD->getType()->isRecordType() || VD->getType()->isArrayType())) { + assert(Res.isLValue()); + + if (!Res.checkFullyInitialized(C.getState())) + return false; + + // lvalue-to-rvalue conversion. + std::optional RValueResult = Res.toRValue(); + if (!RValueResult) + return false; + Result = *RValueResult; + + } else + Result = Res.toAPValue(); + return true; } const LangOptions &Context::getLangOpts() const { return Ctx.getLangOpts(); } @@ -234,12 +278,8 @@ const Function *Context::getOrCreateFunction(const FunctionDecl *FD) { return Func; if (!Func || WasNotDefined) { - if (auto R = ByteCodeStmtGen(*this, *P).compileFunc(FD)) - Func = *R; - else { - llvm::consumeError(R.takeError()); - return nullptr; - } + if (auto F = ByteCodeStmtGen(*this, *P).compileFunc(FD)) + Func = F; } return Func; diff --git a/clang/lib/AST/Interp/Context.h b/clang/lib/AST/Interp/Context.h index 7649caef224..ab83a8d1322 100644 --- a/clang/lib/AST/Interp/Context.h +++ b/clang/lib/AST/Interp/Context.h @@ -51,6 +51,9 @@ public: /// Evaluates a toplevel expression as an rvalue. bool evaluateAsRValue(State &Parent, const Expr *E, APValue &Result); + /// Like evaluateAsRvalue(), but does no implicit lvalue-to-rvalue conversion. + bool evaluate(State &Parent, const Expr *E, APValue &Result); + /// Evaluates a toplevel initializer. bool evaluateAsInitializer(State &Parent, const VarDecl *VD, APValue &Result); diff --git a/clang/lib/AST/Interp/EvalEmitter.cpp b/clang/lib/AST/Interp/EvalEmitter.cpp index 0ff0bde8fd1..a60f893de8b 100644 --- a/clang/lib/AST/Interp/EvalEmitter.cpp +++ b/clang/lib/AST/Interp/EvalEmitter.cpp @@ -19,7 +19,7 @@ using namespace clang::interp; EvalEmitter::EvalEmitter(Context &Ctx, Program &P, State &Parent, InterpStack &Stk, APValue &Result) - : Ctx(Ctx), P(P), S(Parent, P, Stk, Ctx, this), Result(Result) { + : Ctx(Ctx), P(P), S(Parent, P, Stk, Ctx, this), EvalResult(&Ctx) { // Create a dummy frame for the interpreter which does not have locals. S.Current = new InterpFrame(S, /*Func=*/nullptr, /*Caller=*/nullptr, CodePtr()); @@ -33,20 +33,22 @@ EvalEmitter::~EvalEmitter() { } } -llvm::Expected EvalEmitter::interpretExpr(const Expr *E) { - if (this->visitExpr(E)) - return true; - if (BailLocation) - return llvm::make_error(*BailLocation); - return false; +EvaluationResult EvalEmitter::interpretExpr(const Expr *E) { + EvalResult.setSource(E); + + if (!this->visitExpr(E)) + EvalResult.setInvalid(); + + return std::move(this->EvalResult); } -llvm::Expected EvalEmitter::interpretDecl(const VarDecl *VD) { - if (this->visitDecl(VD)) - return true; - if (BailLocation) - return llvm::make_error(*BailLocation); - return false; +EvaluationResult EvalEmitter::interpretDecl(const VarDecl *VD) { + EvalResult.setSource(VD); + + if (!this->visitDecl(VD)) + EvalResult.setInvalid(); + + return std::move(this->EvalResult); } void EvalEmitter::emitLabel(LabelTy Label) { @@ -77,12 +79,6 @@ Scope::Local EvalEmitter::createLocal(Descriptor *D) { return {Off, D}; } -bool EvalEmitter::bail(const SourceLocation &Loc) { - if (!BailLocation) - BailLocation = Loc; - return false; -} - bool EvalEmitter::jumpTrue(const LabelTy &Label) { if (isActive()) { if (S.Stk.pop()) @@ -116,125 +112,37 @@ template bool EvalEmitter::emitRet(const SourceInfo &Info) { if (!isActive()) return true; using T = typename PrimConv::T; - return ReturnValue(S.Stk.pop(), Result); + EvalResult.setValue(S.Stk.pop().toAPValue()); + return true; } -bool EvalEmitter::emitRetVoid(const SourceInfo &Info) { return true; } +template <> bool EvalEmitter::emitRet(const SourceInfo &Info) { + if (!isActive()) + return true; + EvalResult.setPointer(S.Stk.pop()); + return true; +} +template <> bool EvalEmitter::emitRet(const SourceInfo &Info) { + if (!isActive()) + return true; + EvalResult.setFunctionPointer(S.Stk.pop()); + return true; +} + +bool EvalEmitter::emitRetVoid(const SourceInfo &Info) { + EvalResult.setValid(); + return true; +} bool EvalEmitter::emitRetValue(const SourceInfo &Info) { - // Method to recursively traverse composites. - std::function Composite; - Composite = [this, &Composite](QualType Ty, const Pointer &Ptr, APValue &R) { - if (const auto *AT = Ty->getAs()) - Ty = AT->getValueType(); - - if (const auto *RT = Ty->getAs()) { - const auto *Record = Ptr.getRecord(); - assert(Record && "Missing record descriptor"); - - bool Ok = true; - if (RT->getDecl()->isUnion()) { - const FieldDecl *ActiveField = nullptr; - APValue Value; - for (const auto &F : Record->fields()) { - const Pointer &FP = Ptr.atField(F.Offset); - QualType FieldTy = F.Decl->getType(); - if (FP.isActive()) { - if (std::optional T = Ctx.classify(FieldTy)) { - TYPE_SWITCH(*T, Ok &= ReturnValue(FP.deref(), Value)); - } else { - Ok &= Composite(FieldTy, FP, Value); - } - break; - } - } - R = APValue(ActiveField, Value); - } else { - unsigned NF = Record->getNumFields(); - unsigned NB = Record->getNumBases(); - unsigned NV = Ptr.isBaseClass() ? 0 : Record->getNumVirtualBases(); - - R = APValue(APValue::UninitStruct(), NB, NF); - - for (unsigned I = 0; I < NF; ++I) { - const Record::Field *FD = Record->getField(I); - QualType FieldTy = FD->Decl->getType(); - const Pointer &FP = Ptr.atField(FD->Offset); - APValue &Value = R.getStructField(I); - - if (std::optional T = Ctx.classify(FieldTy)) { - TYPE_SWITCH(*T, Ok &= ReturnValue(FP.deref(), Value)); - } else { - Ok &= Composite(FieldTy, FP, Value); - } - } - - for (unsigned I = 0; I < NB; ++I) { - const Record::Base *BD = Record->getBase(I); - QualType BaseTy = Ctx.getASTContext().getRecordType(BD->Decl); - const Pointer &BP = Ptr.atField(BD->Offset); - Ok &= Composite(BaseTy, BP, R.getStructBase(I)); - } - - for (unsigned I = 0; I < NV; ++I) { - const Record::Base *VD = Record->getVirtualBase(I); - QualType VirtBaseTy = Ctx.getASTContext().getRecordType(VD->Decl); - const Pointer &VP = Ptr.atField(VD->Offset); - Ok &= Composite(VirtBaseTy, VP, R.getStructBase(NB + I)); - } - } - return Ok; - } - - if (Ty->isIncompleteArrayType()) { - R = APValue(APValue::UninitArray(), 0, 0); - return true; - } - - if (const auto *AT = Ty->getAsArrayTypeUnsafe()) { - const size_t NumElems = Ptr.getNumElems(); - QualType ElemTy = AT->getElementType(); - R = APValue(APValue::UninitArray{}, NumElems, NumElems); - - bool Ok = true; - for (unsigned I = 0; I < NumElems; ++I) { - APValue &Slot = R.getArrayInitializedElt(I); - const Pointer &EP = Ptr.atIndex(I); - if (std::optional T = Ctx.classify(ElemTy)) { - TYPE_SWITCH(*T, Ok &= ReturnValue(EP.deref(), Slot)); - } else { - Ok &= Composite(ElemTy, EP.narrow(), Slot); - } - } - return Ok; - } - - // Complex types. - if (const auto *CT = Ty->getAs()) { - QualType ElemTy = CT->getElementType(); - std::optional ElemT = Ctx.classify(ElemTy); - assert(ElemT); - - if (ElemTy->isIntegerType()) { - INT_TYPE_SWITCH(*ElemT, { - auto V1 = Ptr.atIndex(0).deref(); - auto V2 = Ptr.atIndex(1).deref(); - Result = APValue(V1.toAPSInt(), V2.toAPSInt()); - return true; - }); - } else if (ElemTy->isFloatingType()) { - Result = APValue(Ptr.atIndex(0).deref().getAPFloat(), - Ptr.atIndex(1).deref().getAPFloat()); - return true; - } - return false; - } - llvm_unreachable("invalid value to return"); - }; - - // Return the composite type. const auto &Ptr = S.Stk.pop(); - return Composite(Ptr.getType(), Ptr, Result); + if (std::optional APV = Ptr.toRValue(S.getCtx())) { + EvalResult.setValue(*APV); + return true; + } + + EvalResult.setInvalid(); + return false; } bool EvalEmitter::emitGetPtrLocal(uint32_t I, const SourceInfo &Info) { diff --git a/clang/lib/AST/Interp/EvalEmitter.h b/clang/lib/AST/Interp/EvalEmitter.h index 5a9be18c34a..deb2ebc4e61 100644 --- a/clang/lib/AST/Interp/EvalEmitter.h +++ b/clang/lib/AST/Interp/EvalEmitter.h @@ -13,6 +13,7 @@ #ifndef LLVM_CLANG_AST_INTERP_EVALEMITTER_H #define LLVM_CLANG_AST_INTERP_EVALEMITTER_H +#include "EvaluationResult.h" #include "InterpState.h" #include "PrimType.h" #include "Source.h" @@ -33,8 +34,10 @@ public: using AddrTy = uintptr_t; using Local = Scope::Local; - llvm::Expected interpretExpr(const Expr *E); - llvm::Expected interpretDecl(const VarDecl *VD); + EvaluationResult interpretExpr(const Expr *E); + EvaluationResult interpretDecl(const VarDecl *VD); + + InterpState &getState() { return S; } protected: EvalEmitter(Context &Ctx, Program &P, State &Parent, InterpStack &Stk, @@ -51,10 +54,6 @@ protected: virtual bool visitExpr(const Expr *E) = 0; virtual bool visitDecl(const VarDecl *VD) = 0; - bool bail(const Stmt *S) { return bail(S->getBeginLoc()); } - bool bail(const Decl *D) { return bail(D->getBeginLoc()); } - bool bail(const SourceLocation &Loc); - /// Emits jumps. bool jumpTrue(const LabelTy &Label); bool jumpFalse(const LabelTy &Label); @@ -86,7 +85,7 @@ private: /// Callee evaluation state. InterpState S; /// Location to write the result to. - APValue &Result; + EvaluationResult EvalResult; /// Temporaries which require storage. llvm::DenseMap> Locals; @@ -100,8 +99,6 @@ private: // The emitter always tracks the current instruction and sets OpPC to a token // value which is mapped to the location of the opcode being evaluated. CodePtr OpPC; - /// Location of a failure. - std::optional BailLocation; /// Location of the current instruction. SourceInfo CurrentSource; diff --git a/clang/lib/AST/Interp/EvaluationResult.cpp b/clang/lib/AST/Interp/EvaluationResult.cpp new file mode 100644 index 00000000000..a14dc87f1df --- /dev/null +++ b/clang/lib/AST/Interp/EvaluationResult.cpp @@ -0,0 +1,196 @@ +//===----- EvaluationResult.cpp - Result class for the VM ------*- C++ -*-===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +#include "EvaluationResult.h" +#include "Context.h" +#include "InterpState.h" +#include "Record.h" +#include "clang/AST/ExprCXX.h" + +namespace clang { +namespace interp { + +APValue EvaluationResult::toAPValue() const { + assert(!empty()); + switch (Kind) { + case LValue: + // Either a pointer or a function pointer. + if (const auto *P = std::get_if(&Value)) + return P->toAPValue(); + else if (const auto *FP = std::get_if(&Value)) + return FP->toAPValue(); + else + llvm_unreachable("Unhandled LValue type"); + break; + case RValue: + return std::get(Value); + case Valid: + return APValue(); + default: + llvm_unreachable("Unhandled result kind?"); + } +} + +std::optional EvaluationResult::toRValue() const { + if (Kind == RValue) + return toAPValue(); + + assert(Kind == LValue); + + // We have a pointer and want an RValue. + if (const auto *P = std::get_if(&Value)) + return P->toRValue(*Ctx); + else if (const auto *FP = std::get_if(&Value)) // Nope + return FP->toAPValue(); + llvm_unreachable("Unhandled lvalue kind"); +} + +static void DiagnoseUninitializedSubobject(InterpState &S, SourceLocation Loc, + const FieldDecl *SubObjDecl) { + assert(SubObjDecl && "Subobject declaration does not exist"); + S.FFDiag(Loc, diag::note_constexpr_uninitialized) + << /*(name)*/ 1 << SubObjDecl; + S.Note(SubObjDecl->getLocation(), + diag::note_constexpr_subobject_declared_here); +} + +static bool CheckFieldsInitialized(InterpState &S, SourceLocation Loc, + const Pointer &BasePtr, const Record *R); + +static bool CheckArrayInitialized(InterpState &S, SourceLocation Loc, + const Pointer &BasePtr, + const ConstantArrayType *CAT) { + bool Result = true; + size_t NumElems = CAT->getSize().getZExtValue(); + QualType ElemType = CAT->getElementType(); + + if (ElemType->isRecordType()) { + const Record *R = BasePtr.getElemRecord(); + for (size_t I = 0; I != NumElems; ++I) { + Pointer ElemPtr = BasePtr.atIndex(I).narrow(); + Result &= CheckFieldsInitialized(S, Loc, ElemPtr, R); + } + } else if (const auto *ElemCAT = dyn_cast(ElemType)) { + for (size_t I = 0; I != NumElems; ++I) { + Pointer ElemPtr = BasePtr.atIndex(I).narrow(); + Result &= CheckArrayInitialized(S, Loc, ElemPtr, ElemCAT); + } + } else { + for (size_t I = 0; I != NumElems; ++I) { + if (!BasePtr.atIndex(I).isInitialized()) { + DiagnoseUninitializedSubobject(S, Loc, BasePtr.getField()); + Result = false; + } + } + } + + return Result; +} + +static bool CheckFieldsInitialized(InterpState &S, SourceLocation Loc, + const Pointer &BasePtr, const Record *R) { + assert(R); + bool Result = true; + // Check all fields of this record are initialized. + for (const Record::Field &F : R->fields()) { + Pointer FieldPtr = BasePtr.atField(F.Offset); + QualType FieldType = F.Decl->getType(); + + if (FieldType->isRecordType()) { + Result &= CheckFieldsInitialized(S, Loc, FieldPtr, FieldPtr.getRecord()); + } else if (FieldType->isIncompleteArrayType()) { + // Nothing to do here. + } else if (FieldType->isArrayType()) { + const auto *CAT = + cast(FieldType->getAsArrayTypeUnsafe()); + Result &= CheckArrayInitialized(S, Loc, FieldPtr, CAT); + } else if (!FieldPtr.isInitialized()) { + DiagnoseUninitializedSubobject(S, Loc, F.Decl); + Result = false; + } + } + + // Check Fields in all bases + for (const Record::Base &B : R->bases()) { + Pointer P = BasePtr.atField(B.Offset); + if (!P.isInitialized()) { + S.FFDiag(BasePtr.getDeclDesc()->asDecl()->getLocation(), + diag::note_constexpr_uninitialized_base) + << B.Desc->getType(); + return false; + } + Result &= CheckFieldsInitialized(S, Loc, P, B.R); + } + + // TODO: Virtual bases + + return Result; +} + +bool EvaluationResult::checkFullyInitialized(InterpState &S) const { + assert(Source); + assert(isLValue()); + + // Our Source must be a VarDecl. + const Decl *SourceDecl = Source.dyn_cast(); + assert(SourceDecl); + const auto *VD = cast(SourceDecl); + assert(VD->getType()->isRecordType() || VD->getType()->isArrayType()); + SourceLocation InitLoc = VD->getAnyInitializer()->getExprLoc(); + + const Pointer &Ptr = *std::get_if(&Value); + assert(!Ptr.isZero()); + + if (const Record *R = Ptr.getRecord()) + return CheckFieldsInitialized(S, InitLoc, Ptr, R); + const auto *CAT = + cast(Ptr.getType()->getAsArrayTypeUnsafe()); + return CheckArrayInitialized(S, InitLoc, Ptr, CAT); + + return true; +} + +void EvaluationResult::dump() const { + assert(Ctx); + auto &OS = llvm::errs(); + const ASTContext &ASTCtx = Ctx->getASTContext(); + + switch (Kind) { + case Empty: + OS << "Empty\n"; + break; + case RValue: + OS << "RValue: "; + std::get(Value).dump(OS, ASTCtx); + break; + case LValue: { + assert(Source); + QualType SourceType; + if (const auto *D = Source.dyn_cast()) { + if (const auto *VD = dyn_cast(D)) + SourceType = VD->getType(); + } else if (const auto *E = Source.dyn_cast()) { + SourceType = E->getType(); + } + + OS << "LValue: "; + if (const auto *P = std::get_if(&Value)) + P->toAPValue().printPretty(OS, ASTCtx, SourceType); + else if (const auto *FP = std::get_if(&Value)) // Nope + FP->toAPValue().printPretty(OS, ASTCtx, SourceType); + OS << "\n"; + break; + } + + default: + llvm_unreachable("Can't print that."); + } +} + +} // namespace interp +} // namespace clang diff --git a/clang/lib/AST/Interp/EvaluationResult.h b/clang/lib/AST/Interp/EvaluationResult.h new file mode 100644 index 00000000000..2b9fc16f1a0 --- /dev/null +++ b/clang/lib/AST/Interp/EvaluationResult.h @@ -0,0 +1,111 @@ +//===------ EvaluationResult.h - Result class for the VM -------*- C++ -*-===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +#ifndef LLVM_CLANG_AST_INTERP_EVALUATION_RESULT_H +#define LLVM_CLANG_AST_INTERP_EVALUATION_RESULT_H + +#include "FunctionPointer.h" +#include "Pointer.h" +#include "clang/AST/APValue.h" +#include "clang/AST/Decl.h" +#include "clang/AST/Expr.h" +#include +#include + +namespace clang { +namespace interp { +class EvalEmitter; +class Context; + +/// Defines the result of an evaluation. +/// +/// The result might be in different forms--one of the pointer types, +/// an APValue, or nothing. +/// +/// We use this class to inspect and diagnose the result, as well as +/// convert it to the requested form. +class EvaluationResult final { +public: + enum ResultKind { + Empty, // Initial state. + LValue, // Result is an lvalue/pointer. + RValue, // Result is an rvalue. + Invalid, // Result is invalid. + Valid, // Result is valid and empty. + }; + + using DeclTy = llvm::PointerUnion; + +private: + const Context *Ctx = nullptr; + std::variant Value; + ResultKind Kind = Empty; + DeclTy Source = nullptr; // Currently only needed for dump(). + + EvaluationResult(ResultKind Kind) : Kind(Kind) { + // Leave everything empty. Can be used as an + // error marker or for void return values. + assert(Kind == Valid || Kind == Invalid); + } + + void setSource(DeclTy D) { Source = D; } + + void setValue(const APValue &V) { + assert(empty()); + assert(!V.isLValue()); + Value = std::move(V); + Kind = RValue; + } + void setPointer(const Pointer P) { + assert(empty()); + Value = P; + Kind = LValue; + } + void setFunctionPointer(const FunctionPointer &P) { + assert(empty()); + Value = P; + Kind = LValue; + } + void setInvalid() { + assert(empty()); + Kind = Invalid; + } + void setValid() { + assert(empty()); + Kind = Valid; + } + +public: + EvaluationResult(const Context *Ctx) : Ctx(Ctx) {} + + bool empty() const { return Kind == Empty; } + bool isInvalid() const { return Kind == Invalid; } + bool isLValue() const { return Kind == LValue; } + bool isRValue() const { return Kind == RValue; } + + /// Returns an APValue for the evaluation result. The returned + /// APValue might be an LValue or RValue. + APValue toAPValue() const; + + /// If the result is an LValue, convert that to an RValue + /// and return it. This may fail, e.g. if the result is an + /// LValue and we can't read from it. + std::optional toRValue() const; + + bool checkFullyInitialized(InterpState &S) const; + + /// Dump to stderr. + void dump() const; + + friend class EvalEmitter; +}; + +} // namespace interp +} // namespace clang + +#endif diff --git a/clang/lib/AST/Interp/IntegralAP.h b/clang/lib/AST/Interp/IntegralAP.h index d5f46409d23..55e29caa1cd 100644 --- a/clang/lib/AST/Interp/IntegralAP.h +++ b/clang/lib/AST/Interp/IntegralAP.h @@ -204,14 +204,18 @@ public: } static bool rem(IntegralAP A, IntegralAP B, unsigned OpBits, IntegralAP *R) { - // FIXME: Implement. - assert(false); + if constexpr (Signed) + *R = IntegralAP(A.V.srem(B.V)); + else + *R = IntegralAP(A.V.urem(B.V)); return false; } static bool div(IntegralAP A, IntegralAP B, unsigned OpBits, IntegralAP *R) { - // FIXME: Implement. - assert(false); + if constexpr (Signed) + *R = IntegralAP(A.V.sdiv(B.V)); + else + *R = IntegralAP(A.V.udiv(B.V)); return false; } diff --git a/clang/lib/AST/Interp/Interp.cpp b/clang/lib/AST/Interp/Interp.cpp index 9de0926b9db..807b860f356 100644 --- a/clang/lib/AST/Interp/Interp.cpp +++ b/clang/lib/AST/Interp/Interp.cpp @@ -53,6 +53,25 @@ static bool Jf(InterpState &S, CodePtr &PC, int32_t Offset) { return true; } +static void diagnoseNonConstVariable(InterpState &S, CodePtr OpPC, + const ValueDecl *VD) { + if (!S.getLangOpts().CPlusPlus) + return; + + const SourceInfo &Loc = S.Current->getSource(OpPC); + + if (VD->getType()->isIntegralOrEnumerationType()) + S.FFDiag(Loc, diag::note_constexpr_ltor_non_const_int, 1) << VD; + else + S.FFDiag(Loc, + S.getLangOpts().CPlusPlus11 + ? diag::note_constexpr_ltor_non_constexpr + : diag::note_constexpr_ltor_non_integral, + 1) + << VD << VD->getType(); + S.Note(VD->getLocation(), diag::note_declared_at); +} + static bool CheckActive(InterpState &S, CodePtr OpPC, const Pointer &Ptr, AccessKinds AK) { if (Ptr.isActive()) @@ -171,9 +190,7 @@ bool CheckExtern(InterpState &S, CodePtr OpPC, const Pointer &Ptr) { if (!S.checkingPotentialConstantExpression() && S.getLangOpts().CPlusPlus) { const auto *VD = Ptr.getDeclDesc()->asValueDecl(); - const SourceInfo &Loc = S.Current->getSource(OpPC); - S.FFDiag(Loc, diag::note_constexpr_ltor_non_constexpr, 1) << VD; - S.Note(VD->getLocation(), diag::note_declared_at); + diagnoseNonConstVariable(S, OpPC, VD); } return false; } @@ -216,6 +233,44 @@ bool CheckLive(InterpState &S, CodePtr OpPC, const Pointer &Ptr, return true; } +bool CheckConstant(InterpState &S, CodePtr OpPC, const Descriptor *Desc) { + assert(Desc); + + auto IsConstType = [&S](const VarDecl *VD) -> bool { + if (VD->isConstexpr()) + return true; + + if (S.getLangOpts().CPlusPlus && !S.getLangOpts().CPlusPlus11) + return false; + + QualType T = VD->getType(); + if (T.isConstQualified()) + return true; + + if (const auto *RT = T->getAs()) + return RT->getPointeeType().isConstQualified(); + + if (const auto *PT = T->getAs()) + return PT->getPointeeType().isConstQualified(); + + return false; + }; + + if (const auto *D = Desc->asValueDecl()) { + if (const auto *VD = dyn_cast(D); + VD && VD->hasGlobalStorage() && !IsConstType(VD)) { + diagnoseNonConstVariable(S, OpPC, VD); + return S.inConstantContext(); + } + } + + return true; +} + +static bool CheckConstant(InterpState &S, CodePtr OpPC, const Pointer &Ptr) { + return CheckConstant(S, OpPC, Ptr.getDeclDesc()); +} + bool CheckDummy(InterpState &S, CodePtr OpPC, const Pointer &Ptr) { return !Ptr.isZero() && !Ptr.isDummy(); } @@ -304,6 +359,9 @@ bool CheckInitialized(InterpState &S, CodePtr OpPC, const Pointer &Ptr, bool CheckLoad(InterpState &S, CodePtr OpPC, const Pointer &Ptr) { if (!CheckLive(S, OpPC, Ptr, AK_Read)) return false; + if (!CheckConstant(S, OpPC, Ptr)) + return false; + if (!CheckDummy(S, OpPC, Ptr)) return false; if (!CheckExtern(S, OpPC, Ptr)) @@ -432,7 +490,7 @@ bool CheckThis(InterpState &S, CodePtr OpPC, const Pointer &This) { } bool CheckPure(InterpState &S, CodePtr OpPC, const CXXMethodDecl *MD) { - if (!MD->isPure()) + if (!MD->isPureVirtual()) return true; const SourceInfo &E = S.Current->getSource(OpPC); S.FFDiag(E, diag::note_constexpr_pure_virtual_call, 1) << MD; @@ -440,98 +498,6 @@ bool CheckPure(InterpState &S, CodePtr OpPC, const CXXMethodDecl *MD) { return false; } -static void DiagnoseUninitializedSubobject(InterpState &S, const SourceInfo &SI, - const FieldDecl *SubObjDecl) { - assert(SubObjDecl && "Subobject declaration does not exist"); - S.FFDiag(SI, diag::note_constexpr_uninitialized) - << /*(name)*/ 1 << SubObjDecl; - S.Note(SubObjDecl->getLocation(), - diag::note_constexpr_subobject_declared_here); -} - -static bool CheckFieldsInitialized(InterpState &S, CodePtr OpPC, - const Pointer &BasePtr, const Record *R); - -static bool CheckArrayInitialized(InterpState &S, CodePtr OpPC, - const Pointer &BasePtr, - const ConstantArrayType *CAT) { - bool Result = true; - size_t NumElems = CAT->getSize().getZExtValue(); - QualType ElemType = CAT->getElementType(); - - if (ElemType->isRecordType()) { - const Record *R = BasePtr.getElemRecord(); - for (size_t I = 0; I != NumElems; ++I) { - Pointer ElemPtr = BasePtr.atIndex(I).narrow(); - Result &= CheckFieldsInitialized(S, OpPC, ElemPtr, R); - } - } else if (const auto *ElemCAT = dyn_cast(ElemType)) { - for (size_t I = 0; I != NumElems; ++I) { - Pointer ElemPtr = BasePtr.atIndex(I).narrow(); - Result &= CheckArrayInitialized(S, OpPC, ElemPtr, ElemCAT); - } - } else { - for (size_t I = 0; I != NumElems; ++I) { - if (!BasePtr.atIndex(I).isInitialized()) { - DiagnoseUninitializedSubobject(S, S.Current->getSource(OpPC), - BasePtr.getField()); - Result = false; - } - } - } - - return Result; -} - -static bool CheckFieldsInitialized(InterpState &S, CodePtr OpPC, - const Pointer &BasePtr, const Record *R) { - assert(R); - bool Result = true; - // Check all fields of this record are initialized. - for (const Record::Field &F : R->fields()) { - Pointer FieldPtr = BasePtr.atField(F.Offset); - QualType FieldType = F.Decl->getType(); - - if (FieldType->isRecordType()) { - Result &= CheckFieldsInitialized(S, OpPC, FieldPtr, FieldPtr.getRecord()); - } else if (FieldType->isIncompleteArrayType()) { - // Nothing to do here. - } else if (FieldType->isArrayType()) { - const auto *CAT = - cast(FieldType->getAsArrayTypeUnsafe()); - Result &= CheckArrayInitialized(S, OpPC, FieldPtr, CAT); - } else if (!FieldPtr.isInitialized()) { - DiagnoseUninitializedSubobject(S, S.Current->getSource(OpPC), F.Decl); - Result = false; - } - } - - // Check Fields in all bases - for (const Record::Base &B : R->bases()) { - Pointer P = BasePtr.atField(B.Offset); - if (!P.isInitialized()) { - S.FFDiag(BasePtr.getDeclDesc()->asDecl()->getLocation(), - diag::note_constexpr_uninitialized_base) - << B.Desc->getType(); - return false; - } - Result &= CheckFieldsInitialized(S, OpPC, P, B.R); - } - - // TODO: Virtual bases - - return Result; -} - -bool CheckCtorCall(InterpState &S, CodePtr OpPC, const Pointer &This) { - assert(!This.isZero()); - if (const Record *R = This.getRecord()) - return CheckFieldsInitialized(S, OpPC, This, R); - const auto *CAT = - cast(This.getType()->getAsArrayTypeUnsafe()); - return CheckArrayInitialized(S, OpPC, This, CAT); -} - bool CheckPotentialReinterpretCast(InterpState &S, CodePtr OpPC, const Pointer &Ptr) { if (!S.inConstantContext()) @@ -605,13 +571,7 @@ bool CheckDeclRef(InterpState &S, CodePtr OpPC, const DeclRefExpr *DR) { } } else if (const auto *VD = dyn_cast(D)) { if (!VD->getType().isConstQualified()) { - S.FFDiag(E, - VD->getType()->isIntegralOrEnumerationType() - ? diag::note_constexpr_ltor_non_const_int - : diag::note_constexpr_ltor_non_constexpr, - 1) - << VD; - S.Note(VD->getLocation(), diag::note_declared_at) << VD->getSourceRange(); + diagnoseNonConstVariable(S, OpPC, VD); return false; } diff --git a/clang/lib/AST/Interp/Interp.h b/clang/lib/AST/Interp/Interp.h index c05dea0cc55..65c54ed9c89 100644 --- a/clang/lib/AST/Interp/Interp.h +++ b/clang/lib/AST/Interp/Interp.h @@ -77,6 +77,9 @@ bool CheckSubobject(InterpState &S, CodePtr OpPC, const Pointer &Ptr, /// Checks if a pointer points to const storage. bool CheckConst(InterpState &S, CodePtr OpPC, const Pointer &Ptr); +/// Checks if the Descriptor is of a constexpr or const global variable. +bool CheckConstant(InterpState &S, CodePtr OpPC, const Descriptor *Desc); + /// Checks if a pointer points to a mutable field. bool CheckMutable(InterpState &S, CodePtr OpPC, const Pointer &Ptr); @@ -108,9 +111,6 @@ bool CheckThis(InterpState &S, CodePtr OpPC, const Pointer &This); /// Checks if a method is pure virtual. bool CheckPure(InterpState &S, CodePtr OpPC, const CXXMethodDecl *MD); -/// Checks that all fields are initialized after a constructor call. -bool CheckCtorCall(InterpState &S, CodePtr OpPC, const Pointer &This); - /// Checks if reinterpret casts are legal in the current context. bool CheckPotentialReinterpretCast(InterpState &S, CodePtr OpPC, const Pointer &Ptr); @@ -1004,12 +1004,23 @@ bool SetThisField(InterpState &S, CodePtr OpPC, uint32_t I) { template ::T> bool GetGlobal(InterpState &S, CodePtr OpPC, uint32_t I) { const Block *B = S.P.getGlobal(I); + + if (!CheckConstant(S, OpPC, B->getDescriptor())) + return false; if (B->isExtern()) return false; S.Stk.push(B->deref()); return true; } +/// Same as GetGlobal, but without the checks. +template ::T> +bool GetGlobalUnchecked(InterpState &S, CodePtr OpPC, uint32_t I) { + auto *B = S.P.getGlobal(I); + S.Stk.push(B->deref()); + return true; +} + template ::T> bool SetGlobal(InterpState &S, CodePtr OpPC, uint32_t I) { // TODO: emit warning. @@ -1047,8 +1058,12 @@ inline bool InitGlobalTempComp(InterpState &S, CodePtr OpPC, const Pointer &P = S.Stk.peek(); APValue *Cached = Temp->getOrCreateValue(true); - *Cached = P.toRValue(S.getCtx()); - return true; + if (std::optional APV = P.toRValue(S.getCtx())) { + *Cached = *APV; + return true; + } + + return false; } template ::T> @@ -1064,15 +1079,18 @@ bool InitThisField(InterpState &S, CodePtr OpPC, uint32_t I) { return true; } +// FIXME: The Field pointer here is too much IMO and we could instead just +// pass an Offset + BitWidth pair. template ::T> -bool InitThisBitField(InterpState &S, CodePtr OpPC, const Record::Field *F) { +bool InitThisBitField(InterpState &S, CodePtr OpPC, const Record::Field *F, + uint32_t FieldOffset) { assert(F->isBitField()); if (S.checkingPotentialConstantExpression()) return false; const Pointer &This = S.Current->getThis(); if (!CheckThis(S, OpPC, This)) return false; - const Pointer &Field = This.atField(F->Offset); + const Pointer &Field = This.atField(FieldOffset); const auto &Value = S.Stk.pop(); Field.deref() = Value.truncate(F->Decl->getBitWidthValue(S.getCtx())); Field.initialize(); @@ -1846,11 +1864,6 @@ inline bool ArrayElemPtrPop(InterpState &S, CodePtr OpPC) { return NarrowPtr(S, OpPC); } -inline bool CheckGlobalCtor(InterpState &S, CodePtr OpPC) { - const Pointer &Obj = S.Stk.peek(); - return CheckCtorCall(S, OpPC, Obj); -} - inline bool Call(InterpState &S, CodePtr OpPC, const Function *Func) { if (Func->hasThisPointer()) { size_t ThisOffset = diff --git a/clang/lib/AST/Interp/Opcodes.td b/clang/lib/AST/Interp/Opcodes.td index 69068e87d57..24747b6b98c 100644 --- a/clang/lib/AST/Interp/Opcodes.td +++ b/clang/lib/AST/Interp/Opcodes.td @@ -375,10 +375,9 @@ def GetLocal : AccessOpcode { let HasCustomEval = 1; } // [] -> [Pointer] def SetLocal : AccessOpcode { let HasCustomEval = 1; } -def CheckGlobalCtor : Opcode {} - // [] -> [Value] def GetGlobal : AccessOpcode; +def GetGlobalUnchecked : AccessOpcode; // [Value] -> [] def InitGlobal : AccessOpcode; // [Value] -> [] @@ -416,7 +415,11 @@ def InitThisField : AccessOpcode; // [Value] -> [] def InitThisFieldActive : AccessOpcode; // [Value] -> [] -def InitThisBitField : BitFieldOpcode; +def InitThisBitField : Opcode { + let Types = [AluTypeClass]; + let Args = [ArgRecordField, ArgUint32]; + let HasGroup = 1; +} // [Pointer, Value] -> [] def InitField : AccessOpcode; // [Pointer, Value] -> [] diff --git a/clang/lib/AST/Interp/Pointer.cpp b/clang/lib/AST/Interp/Pointer.cpp index e979b99b0fd..5af1d6d52e9 100644 --- a/clang/lib/AST/Interp/Pointer.cpp +++ b/clang/lib/AST/Interp/Pointer.cpp @@ -231,33 +231,143 @@ bool Pointer::hasSameArray(const Pointer &A, const Pointer &B) { return hasSameBase(A, B) && A.Base == B.Base && A.getFieldDesc()->IsArray; } -APValue Pointer::toRValue(const Context &Ctx) const { - // Primitives. - if (getFieldDesc()->isPrimitive()) { - PrimType PT = *Ctx.classify(getType()); - TYPE_SWITCH(PT, return deref().toAPValue()); - llvm_unreachable("Unhandled PrimType?"); - } +std::optional Pointer::toRValue(const Context &Ctx) const { + // Method to recursively traverse composites. + std::function Composite; + Composite = [&Composite, &Ctx](QualType Ty, const Pointer &Ptr, APValue &R) { + if (const auto *AT = Ty->getAs()) + Ty = AT->getValueType(); + // Invalid pointers. + if (Ptr.isDummy() || !Ptr.isLive() || + (!Ptr.isUnknownSizeArray() && Ptr.isOnePastEnd())) + return false; + + // Primitive values. + if (std::optional T = Ctx.classify(Ty)) { + if (T == PT_Ptr || T == PT_FnPtr) { + R = Ptr.toAPValue(); + } else { + TYPE_SWITCH(*T, R = Ptr.deref().toAPValue()); + } + return true; + } + + if (const auto *RT = Ty->getAs()) { + const auto *Record = Ptr.getRecord(); + assert(Record && "Missing record descriptor"); + + bool Ok = true; + if (RT->getDecl()->isUnion()) { + const FieldDecl *ActiveField = nullptr; + APValue Value; + for (const auto &F : Record->fields()) { + const Pointer &FP = Ptr.atField(F.Offset); + QualType FieldTy = F.Decl->getType(); + if (FP.isActive()) { + if (std::optional T = Ctx.classify(FieldTy)) { + TYPE_SWITCH(*T, Value = FP.deref().toAPValue()); + } else { + Ok &= Composite(FieldTy, FP, Value); + } + break; + } + } + R = APValue(ActiveField, Value); + } else { + unsigned NF = Record->getNumFields(); + unsigned NB = Record->getNumBases(); + unsigned NV = Ptr.isBaseClass() ? 0 : Record->getNumVirtualBases(); + + R = APValue(APValue::UninitStruct(), NB, NF); + + for (unsigned I = 0; I < NF; ++I) { + const Record::Field *FD = Record->getField(I); + QualType FieldTy = FD->Decl->getType(); + const Pointer &FP = Ptr.atField(FD->Offset); + APValue &Value = R.getStructField(I); + + if (std::optional T = Ctx.classify(FieldTy)) { + TYPE_SWITCH(*T, Value = FP.deref().toAPValue()); + } else { + Ok &= Composite(FieldTy, FP, Value); + } + } + + for (unsigned I = 0; I < NB; ++I) { + const Record::Base *BD = Record->getBase(I); + QualType BaseTy = Ctx.getASTContext().getRecordType(BD->Decl); + const Pointer &BP = Ptr.atField(BD->Offset); + Ok &= Composite(BaseTy, BP, R.getStructBase(I)); + } + + for (unsigned I = 0; I < NV; ++I) { + const Record::Base *VD = Record->getVirtualBase(I); + QualType VirtBaseTy = Ctx.getASTContext().getRecordType(VD->Decl); + const Pointer &VP = Ptr.atField(VD->Offset); + Ok &= Composite(VirtBaseTy, VP, R.getStructBase(NB + I)); + } + } + return Ok; + } + + if (Ty->isIncompleteArrayType()) { + R = APValue(APValue::UninitArray(), 0, 0); + return true; + } + + if (const auto *AT = Ty->getAsArrayTypeUnsafe()) { + const size_t NumElems = Ptr.getNumElems(); + QualType ElemTy = AT->getElementType(); + R = APValue(APValue::UninitArray{}, NumElems, NumElems); + + bool Ok = true; + for (unsigned I = 0; I < NumElems; ++I) { + APValue &Slot = R.getArrayInitializedElt(I); + const Pointer &EP = Ptr.atIndex(I); + if (std::optional T = Ctx.classify(ElemTy)) { + TYPE_SWITCH(*T, Slot = EP.deref().toAPValue()); + } else { + Ok &= Composite(ElemTy, EP.narrow(), Slot); + } + } + return Ok; + } + + // Complex types. + if (const auto *CT = Ty->getAs()) { + QualType ElemTy = CT->getElementType(); + std::optional ElemT = Ctx.classify(ElemTy); + assert(ElemT); + + if (ElemTy->isIntegerType()) { + INT_TYPE_SWITCH(*ElemT, { + auto V1 = Ptr.atIndex(0).deref(); + auto V2 = Ptr.atIndex(1).deref(); + R = APValue(V1.toAPSInt(), V2.toAPSInt()); + return true; + }); + } else if (ElemTy->isFloatingType()) { + R = APValue(Ptr.atIndex(0).deref().getAPFloat(), + Ptr.atIndex(1).deref().getAPFloat()); + return true; + } + return false; + } + + llvm_unreachable("invalid value to return"); + }; + + if (isZero()) + return APValue(static_cast(nullptr), CharUnits::Zero(), {}, false, + true); + + if (isDummy() || !isLive()) + return std::nullopt; + + // Return the composite type. APValue Result; - // Records. - if (getFieldDesc()->isRecord()) { - const Record *R = getRecord(); - Result = - APValue(APValue::UninitStruct(), R->getNumBases(), R->getNumFields()); - - for (unsigned I = 0; I != R->getNumFields(); ++I) { - const Pointer &FieldPtr = this->atField(R->getField(I)->Offset); - Result.getStructField(I) = FieldPtr.toRValue(Ctx); - } - - for (unsigned I = 0; I != R->getNumBases(); ++I) { - const Pointer &BasePtr = this->atField(R->getBase(I)->Offset); - Result.getStructBase(I) = BasePtr.toRValue(Ctx); - } - } - - // TODO: Arrays - + if (!Composite(getType(), *this, Result)) + return std::nullopt; return Result; } diff --git a/clang/lib/AST/Interp/Pointer.h b/clang/lib/AST/Interp/Pointer.h index a8f6e62fa76..8ccaff41ded 100644 --- a/clang/lib/AST/Interp/Pointer.h +++ b/clang/lib/AST/Interp/Pointer.h @@ -98,7 +98,7 @@ public: } /// Converts the pointer to an APValue that is an rvalue. - APValue toRValue(const Context &Ctx) const; + std::optional toRValue(const Context &Ctx) const; /// Offsets a pointer inside an array. [[nodiscard]] Pointer atIndex(unsigned Idx) const { @@ -379,6 +379,7 @@ public: return *reinterpret_cast(Pointee->rawData() + Base + sizeof(InitMapPtr)); + assert(Offset + sizeof(T) <= Pointee->getDescriptor()->getAllocSize()); return *reinterpret_cast(Pointee->rawData() + Offset); } diff --git a/clang/lib/AST/ItaniumMangle.cpp b/clang/lib/AST/ItaniumMangle.cpp index b1678479888..40b1e086ddd 100644 --- a/clang/lib/AST/ItaniumMangle.cpp +++ b/clang/lib/AST/ItaniumMangle.cpp @@ -4833,9 +4833,23 @@ recurse: E = cast(E)->getSubExpr(); goto recurse; - case Expr::SubstNonTypeTemplateParmExprClass: + case Expr::SubstNonTypeTemplateParmExprClass: { + // Mangle a substituted parameter the same way we mangle the template + // argument. + auto *SNTTPE = cast(E); + if (auto *CE = dyn_cast(SNTTPE->getReplacement())) { + // Pull out the constant value and mangle it as a template argument. + QualType ParamType = SNTTPE->getParameterType(Context.getASTContext()); + assert(CE->hasAPValueResult() && "expected the NTTP to have an APValue"); + mangleValueInTemplateArg(ParamType, CE->getAPValueResult(), false, + /*NeedExactType=*/true); + break; + } + // The remaining cases all happen to be substituted with expressions that + // mangle the same as a corresponding template argument anyway. E = cast(E)->getReplacement(); goto recurse; + } case Expr::UserDefinedLiteralClass: // We follow g++'s approach of mangling a UDL as a call to the literal @@ -4883,7 +4897,7 @@ recurse: Out << '_'; mangleType(New->getAllocatedType()); if (New->hasInitializer()) { - if (New->getInitializationStyle() == CXXNewInitializationStyle::List) + if (New->getInitializationStyle() == CXXNewInitializationStyle::Braces) Out << "il"; else Out << "pi"; @@ -4898,7 +4912,7 @@ recurse: for (unsigned i = 0, e = PLE->getNumExprs(); i != e; ++i) mangleExpression(PLE->getExpr(i)); } else if (New->getInitializationStyle() == - CXXNewInitializationStyle::List && + CXXNewInitializationStyle::Braces && isa(Init)) { // Only take InitListExprs apart for list-initialization. mangleInitListElements(cast(Init)); @@ -6064,6 +6078,11 @@ void CXXNameMangler::mangleTemplateArg(TemplateArgument A, bool NeedExactType) { mangleNullPointer(A.getNullPtrType()); break; } + case TemplateArgument::StructuralValue: + mangleValueInTemplateArg(A.getStructuralValueType(), + A.getAsStructuralValue(), + /*TopLevel=*/true, NeedExactType); + break; case TemplateArgument::Pack: { // ::= J * E Out << 'J'; @@ -6472,7 +6491,20 @@ void CXXNameMangler::mangleValueInTemplateArg(QualType T, const APValue &V, Out << "plcvPcad"; Kind = Offset; } else { - if (!V.getLValuePath().empty() || V.isLValueOnePastTheEnd()) { + // Clang 11 and before mangled an array subject to array-to-pointer decay + // as if it were the declaration itself. + bool IsArrayToPointerDecayMangledAsDecl = false; + if (TopLevel && Ctx.getLangOpts().getClangABICompat() <= + LangOptions::ClangABI::Ver11) { + QualType BType = B.getType(); + IsArrayToPointerDecayMangledAsDecl = + BType->isArrayType() && V.getLValuePath().size() == 1 && + V.getLValuePath()[0].getAsArrayIndex() == 0 && + Ctx.hasSimilarType(T, Ctx.getDecayedType(BType)); + } + + if ((!V.getLValuePath().empty() || V.isLValueOnePastTheEnd()) && + !IsArrayToPointerDecayMangledAsDecl) { NotPrimaryExpr(); // A final conversion to the template parameter's type is usually // folded into the 'so' mangling, but we can't do that for 'void*' diff --git a/clang/lib/AST/JSONNodeDumper.cpp b/clang/lib/AST/JSONNodeDumper.cpp index 637d06cee78..3daba13d0fc 100644 --- a/clang/lib/AST/JSONNodeDumper.cpp +++ b/clang/lib/AST/JSONNodeDumper.cpp @@ -930,7 +930,7 @@ void JSONNodeDumper::VisitFunctionDecl(const FunctionDecl *FD) { JOS.attribute("storageClass", VarDecl::getStorageClassSpecifierString(SC)); attributeOnlyIfTrue("inline", FD->isInlineSpecified()); attributeOnlyIfTrue("virtual", FD->isVirtualAsWritten()); - attributeOnlyIfTrue("pure", FD->isPure()); + attributeOnlyIfTrue("pure", FD->isPureVirtual()); attributeOnlyIfTrue("explicitlyDeleted", FD->isDeletedAsWritten()); attributeOnlyIfTrue("constexpr", FD->isConstexpr()); attributeOnlyIfTrue("variadic", FD->isVariadic()); @@ -1356,12 +1356,11 @@ void JSONNodeDumper::VisitCXXNewExpr(const CXXNewExpr *NE) { attributeOnlyIfTrue("isPlacement", NE->getNumPlacementArgs() != 0); switch (NE->getInitializationStyle()) { case CXXNewInitializationStyle::None: - case CXXNewInitializationStyle::Implicit: break; - case CXXNewInitializationStyle::Call: + case CXXNewInitializationStyle::Parens: JOS.attribute("initStyle", "call"); break; - case CXXNewInitializationStyle::List: + case CXXNewInitializationStyle::Braces: JOS.attribute("initStyle", "list"); break; } diff --git a/clang/lib/AST/Mangle.cpp b/clang/lib/AST/Mangle.cpp index d3a6b61fd2b..30cff1ba2e6 100644 --- a/clang/lib/AST/Mangle.cpp +++ b/clang/lib/AST/Mangle.cpp @@ -464,7 +464,7 @@ public: SmallString<40> Mangled; auto Prefix = getClassSymbolPrefix(Kind, OCD->getASTContext()); llvm::Mangler::getNameWithPrefix(Mangled, Prefix + ClassName, DL); - return std::string(Mangled.str()); + return std::string(Mangled); }; return { diff --git a/clang/lib/AST/MicrosoftMangle.cpp b/clang/lib/AST/MicrosoftMangle.cpp index 8346ad87b40..36b5bf64f67 100644 --- a/clang/lib/AST/MicrosoftMangle.cpp +++ b/clang/lib/AST/MicrosoftMangle.cpp @@ -337,6 +337,7 @@ class MicrosoftCXXNameMangler { public: enum QualifierMangleMode { QMM_Drop, QMM_Mangle, QMM_Escape, QMM_Result }; + enum class TplArgKind { ClassNTTP, StructuralValue }; MicrosoftCXXNameMangler(MicrosoftMangleContextImpl &C, raw_ostream &Out_) : Context(C), Out(Out_), Structor(nullptr), StructorType(-1), @@ -453,7 +454,7 @@ private: const TemplateArgumentList &TemplateArgs); void mangleTemplateArg(const TemplateDecl *TD, const TemplateArgument &TA, const NamedDecl *Parm); - void mangleTemplateArgValue(QualType T, const APValue &V, + void mangleTemplateArgValue(QualType T, const APValue &V, TplArgKind, bool WithScalarType = false); void mangleObjCProtocol(const ObjCProtocolDecl *PD); @@ -1088,7 +1089,7 @@ void MicrosoftCXXNameMangler::mangleUnqualifiedName(GlobalDecl GD, if (const auto *TPO = dyn_cast(ND)) { Out << "?__N"; mangleTemplateArgValue(TPO->getType().getUnqualifiedType(), - TPO->getValue()); + TPO->getValue(), TplArgKind::ClassNTTP); break; } @@ -1604,6 +1605,22 @@ void MicrosoftCXXNameMangler::mangleTemplateArgs( } } +/// If value V (with type T) represents a decayed pointer to the first element +/// of an array, return that array. +static ValueDecl *getAsArrayToPointerDecayedDecl(QualType T, const APValue &V) { + // Must be a pointer... + if (!T->isPointerType() || !V.isLValue() || !V.hasLValuePath() || + !V.getLValueBase()) + return nullptr; + // ... to element 0 of an array. + QualType BaseT = V.getLValueBase().getType(); + if (!BaseT->isArrayType() || V.getLValuePath().size() != 1 || + V.getLValuePath()[0].getAsArrayIndex() != 0) + return nullptr; + return const_cast( + V.getLValueBase().dyn_cast()); +} + void MicrosoftCXXNameMangler::mangleTemplateArg(const TemplateDecl *TD, const TemplateArgument &TA, const NamedDecl *Parm) { @@ -1669,7 +1686,7 @@ void MicrosoftCXXNameMangler::mangleTemplateArg(const TemplateDecl *TD, Out << "$"; auto *TPO = cast(ND); mangleTemplateArgValue(TPO->getType().getUnqualifiedType(), - TPO->getValue()); + TPO->getValue(), TplArgKind::ClassNTTP); } else { mangle(ND, "$1?"); } @@ -1712,6 +1729,27 @@ void MicrosoftCXXNameMangler::mangleTemplateArg(const TemplateDecl *TD, cast(Parm), T); break; } + case TemplateArgument::StructuralValue: + if (ValueDecl *D = getAsArrayToPointerDecayedDecl( + TA.getStructuralValueType(), TA.getAsStructuralValue())) { + // Mangle the result of array-to-pointer decay as if it were a reference + // to the original declaration, to match MSVC's behavior. This can result + // in mangling collisions in some cases! + return mangleTemplateArg( + TD, TemplateArgument(D, TA.getStructuralValueType()), Parm); + } + Out << "$"; + if (cast(Parm) + ->getType() + ->getContainedDeducedType()) { + Out << "M"; + mangleType(TA.getNonTypeTemplateArgumentType(), SourceRange(), QMM_Drop); + } + mangleTemplateArgValue(TA.getStructuralValueType(), + TA.getAsStructuralValue(), + TplArgKind::StructuralValue, + /*WithScalarType=*/false); + break; case TemplateArgument::Expression: mangleExpression(TA.getAsExpr(), cast(Parm)); break; @@ -1754,6 +1792,7 @@ void MicrosoftCXXNameMangler::mangleTemplateArg(const TemplateDecl *TD, void MicrosoftCXXNameMangler::mangleTemplateArgValue(QualType T, const APValue &V, + TplArgKind TAK, bool WithScalarType) { switch (V.getKind()) { case APValue::None: @@ -1806,7 +1845,7 @@ void MicrosoftCXXNameMangler::mangleTemplateArgValue(QualType T, break; } } else { - if (T->isPointerType()) + if (TAK == TplArgKind::ClassNTTP && T->isPointerType()) Out << "5"; SmallVector EntryTypes; @@ -1850,12 +1889,12 @@ void MicrosoftCXXNameMangler::mangleTemplateArgValue(QualType T, auto *VD = Base.dyn_cast(); if (!VD) break; - Out << "E"; + Out << (TAK == TplArgKind::ClassNTTP ? 'E' : '1'); mangle(VD); for (const std::function &Mangler : EntryManglers) Mangler(); - if (T->isPointerType()) + if (TAK == TplArgKind::ClassNTTP && T->isPointerType()) Out << '@'; } @@ -1869,11 +1908,18 @@ void MicrosoftCXXNameMangler::mangleTemplateArgValue(QualType T, const CXXRecordDecl *RD = T->castAs()->getMostRecentCXXRecordDecl(); const ValueDecl *D = V.getMemberPointerDecl(); - if (T->isMemberDataPointerType()) - mangleMemberDataPointerInClassNTTP(RD, D); - else - mangleMemberFunctionPointerInClassNTTP(RD, - cast_or_null(D)); + if (TAK == TplArgKind::ClassNTTP) { + if (T->isMemberDataPointerType()) + mangleMemberDataPointerInClassNTTP(RD, D); + else + mangleMemberFunctionPointerInClassNTTP(RD, + cast_or_null(D)); + } else { + if (T->isMemberDataPointerType()) + mangleMemberDataPointer(RD, D, ""); + else + mangleMemberFunctionPointer(RD, cast_or_null(D), ""); + } return; } @@ -1885,11 +1931,11 @@ void MicrosoftCXXNameMangler::mangleTemplateArgValue(QualType T, unsigned BaseIndex = 0; for (const CXXBaseSpecifier &B : RD->bases()) - mangleTemplateArgValue(B.getType(), V.getStructBase(BaseIndex++)); + mangleTemplateArgValue(B.getType(), V.getStructBase(BaseIndex++), TAK); for (const FieldDecl *FD : RD->fields()) if (!FD->isUnnamedBitfield()) mangleTemplateArgValue(FD->getType(), - V.getStructField(FD->getFieldIndex()), + V.getStructField(FD->getFieldIndex()), TAK, /*WithScalarType*/ true); Out << '@'; return; @@ -1900,7 +1946,7 @@ void MicrosoftCXXNameMangler::mangleTemplateArgValue(QualType T, mangleType(T, SourceRange(), QMM_Escape); if (const FieldDecl *FD = V.getUnionField()) { mangleUnqualifiedName(FD); - mangleTemplateArgValue(FD->getType(), V.getUnionValue()); + mangleTemplateArgValue(FD->getType(), V.getUnionValue(), TAK); } Out << '@'; return; @@ -1932,7 +1978,7 @@ void MicrosoftCXXNameMangler::mangleTemplateArgValue(QualType T, const APValue &ElemV = I < V.getArrayInitializedElts() ? V.getArrayInitializedElt(I) : V.getArrayFiller(); - mangleTemplateArgValue(ElemT, ElemV); + mangleTemplateArgValue(ElemT, ElemV, TAK); Out << '@'; } Out << '@'; @@ -1949,7 +1995,7 @@ void MicrosoftCXXNameMangler::mangleTemplateArgValue(QualType T, mangleType(ElemT, SourceRange(), QMM_Escape); for (unsigned I = 0, N = V.getVectorLength(); I != N; ++I) { const APValue &ElemV = V.getVectorElt(I); - mangleTemplateArgValue(ElemT, ElemV); + mangleTemplateArgValue(ElemT, ElemV, TAK); Out << '@'; } Out << "@@"; diff --git a/clang/lib/AST/ODRDiagsEmitter.cpp b/clang/lib/AST/ODRDiagsEmitter.cpp index 9dcd2ed04f6..5b1cdc16e2e 100644 --- a/clang/lib/AST/ODRDiagsEmitter.cpp +++ b/clang/lib/AST/ODRDiagsEmitter.cpp @@ -1102,8 +1102,8 @@ bool ODRDiagsEmitter::diagnoseMismatch( const bool FirstVirtual = FirstMethod->isVirtualAsWritten(); const bool SecondVirtual = SecondMethod->isVirtualAsWritten(); - const bool FirstPure = FirstMethod->isPure(); - const bool SecondPure = SecondMethod->isPure(); + const bool FirstPure = FirstMethod->isPureVirtual(); + const bool SecondPure = SecondMethod->isPureVirtual(); if ((FirstVirtual || SecondVirtual) && (FirstVirtual != SecondVirtual || FirstPure != SecondPure)) { DiagMethodError(MethodVirtual) << FirstPure << FirstVirtual; diff --git a/clang/lib/AST/ODRHash.cpp b/clang/lib/AST/ODRHash.cpp index aea1a93ae1f..5b98646a1e8 100644 --- a/clang/lib/AST/ODRHash.cpp +++ b/clang/lib/AST/ODRHash.cpp @@ -180,6 +180,10 @@ void ODRHash::AddTemplateArgument(TemplateArgument TA) { TA.getAsIntegral().Profile(ID); break; } + case TemplateArgument::StructuralValue: + AddQualType(TA.getStructuralValueType()); + AddStructuralValue(TA.getAsStructuralValue()); + break; case TemplateArgument::Template: case TemplateArgument::TemplateExpansion: AddTemplateName(TA.getAsTemplateOrTemplatePattern()); @@ -688,7 +692,7 @@ void ODRHash::AddFunctionDecl(const FunctionDecl *Function, ID.AddInteger(Function->getStorageClass()); AddBoolean(Function->isInlineSpecified()); AddBoolean(Function->isVirtualAsWritten()); - AddBoolean(Function->isPure()); + AddBoolean(Function->isPureVirtual()); AddBoolean(Function->isDeletedAsWritten()); AddBoolean(Function->isExplicitlyDefaulted()); @@ -741,8 +745,55 @@ void ODRHash::AddEnumDecl(const EnumDecl *Enum) { if (Enum->isScoped()) AddBoolean(Enum->isScopedUsingClassTag()); - if (Enum->getIntegerTypeSourceInfo()) - AddQualType(Enum->getIntegerType()); + if (Enum->getIntegerTypeSourceInfo()) { + // FIMXE: This allows two enums with different spellings to have the same + // hash. + // + // // mod1.cppm + // module; + // extern "C" { + // typedef unsigned __int64 size_t; + // } + // namespace std { + // using :: size_t; + // } + // + // extern "C++" { + // namespace std { + // enum class align_val_t : std::size_t {}; + // } + // } + // + // export module mod1; + // export using std::align_val_t; + // + // // mod2.cppm + // module; + // extern "C" { + // typedef unsigned __int64 size_t; + // } + // + // extern "C++" { + // namespace std { + // enum class align_val_t : size_t {}; + // } + // } + // + // export module mod2; + // import mod1; + // export using std::align_val_t; + // + // The above example should be disallowed since it violates + // [basic.def.odr]p14: + // + // Each such definition shall consist of the same sequence of tokens + // + // The definitions of `std::align_val_t` in two module units have different + // spellings but we failed to give an error here. + // + // See https://github.com/llvm/llvm-project/issues/76638 for details. + AddQualType(Enum->getIntegerType().getCanonicalType()); + } // Filter out sub-Decls which will not be processed in order to get an // accurate count of Decl's. @@ -1249,3 +1300,66 @@ void ODRHash::AddQualType(QualType T) { void ODRHash::AddBoolean(bool Value) { Bools.push_back(Value); } + +void ODRHash::AddStructuralValue(const APValue &Value) { + ID.AddInteger(Value.getKind()); + + // 'APValue::Profile' uses pointer values to make hash for LValue and + // MemberPointer, but they differ from one compiler invocation to another. + // So, handle them explicitly here. + + switch (Value.getKind()) { + case APValue::LValue: { + const APValue::LValueBase &Base = Value.getLValueBase(); + if (!Base) { + ID.AddInteger(Value.getLValueOffset().getQuantity()); + break; + } + + assert(Base.is()); + AddDecl(Base.get()); + ID.AddInteger(Value.getLValueOffset().getQuantity()); + + bool OnePastTheEnd = Value.isLValueOnePastTheEnd(); + if (Value.hasLValuePath()) { + QualType TypeSoFar = Base.getType(); + for (APValue::LValuePathEntry E : Value.getLValuePath()) { + if (const auto *AT = TypeSoFar->getAsArrayTypeUnsafe()) { + if (const auto *CAT = dyn_cast(AT)) + OnePastTheEnd |= CAT->getSize() == E.getAsArrayIndex(); + TypeSoFar = AT->getElementType(); + } else { + const Decl *D = E.getAsBaseOrMember().getPointer(); + if (const auto *FD = dyn_cast(D)) { + if (FD->getParent()->isUnion()) + ID.AddInteger(FD->getFieldIndex()); + TypeSoFar = FD->getType(); + } else { + TypeSoFar = + D->getASTContext().getRecordType(cast(D)); + } + } + } + } + unsigned Val = 0; + if (Value.isNullPointer()) + Val |= 1 << 0; + if (OnePastTheEnd) + Val |= 1 << 1; + if (Value.hasLValuePath()) + Val |= 1 << 2; + ID.AddInteger(Val); + break; + } + case APValue::MemberPointer: { + const ValueDecl *D = Value.getMemberPointerDecl(); + assert(D); + AddDecl(D); + ID.AddInteger( + D->getASTContext().getMemberPointerPathAdjustment(Value).getQuantity()); + break; + } + default: + Value.Profile(ID); + } +} diff --git a/clang/lib/AST/RecordLayoutBuilder.cpp b/clang/lib/AST/RecordLayoutBuilder.cpp index 706991f4fb5..6dfaadd92e7 100644 --- a/clang/lib/AST/RecordLayoutBuilder.cpp +++ b/clang/lib/AST/RecordLayoutBuilder.cpp @@ -2349,7 +2349,7 @@ static const CXXMethodDecl *computeKeyFunction(ASTContext &Context, if (!MD->isVirtual()) continue; - if (MD->isPure()) + if (MD->isPureVirtual()) continue; // Ignore implicit member functions, they are always marked as inline, but @@ -3293,7 +3293,7 @@ void MicrosoftRecordLayoutBuilder::computeVtorDispSet( // Seed the working set with our non-destructor, non-pure virtual methods. for (const CXXMethodDecl *MD : RD->methods()) if (MicrosoftVTableContext::hasVtableSlot(MD) && - !isa(MD) && !MD->isPure()) + !isa(MD) && !MD->isPureVirtual()) Work.insert(MD); while (!Work.empty()) { const CXXMethodDecl *MD = *Work.begin(); diff --git a/clang/lib/AST/StmtPrinter.cpp b/clang/lib/AST/StmtPrinter.cpp index c04cb313c33..9d4aa07ec4d 100644 --- a/clang/lib/AST/StmtPrinter.cpp +++ b/clang/lib/AST/StmtPrinter.cpp @@ -2300,9 +2300,8 @@ void StmtPrinter::VisitCXXNewExpr(CXXNewExpr *E) { OS << ")"; CXXNewInitializationStyle InitStyle = E->getInitializationStyle(); - if (InitStyle != CXXNewInitializationStyle::None && - InitStyle != CXXNewInitializationStyle::Implicit) { - bool Bare = InitStyle == CXXNewInitializationStyle::Call && + if (InitStyle != CXXNewInitializationStyle::None) { + bool Bare = InitStyle == CXXNewInitializationStyle::Parens && !isa(E->getInitializer()); if (Bare) OS << "("; diff --git a/clang/lib/AST/StmtProfile.cpp b/clang/lib/AST/StmtProfile.cpp index d7b980a5857..dd0838edab7 100644 --- a/clang/lib/AST/StmtProfile.cpp +++ b/clang/lib/AST/StmtProfile.cpp @@ -2416,6 +2416,12 @@ void StmtProfiler::VisitTemplateArgument(const TemplateArgument &Arg) { Arg.getAsIntegral().Profile(ID); break; + case TemplateArgument::StructuralValue: + VisitType(Arg.getStructuralValueType()); + // FIXME: Do we need to recursively decompose this ourselves? + Arg.getAsStructuralValue().Profile(ID); + break; + case TemplateArgument::Expression: Visit(Arg.getAsExpr()); break; diff --git a/clang/lib/AST/TemplateBase.cpp b/clang/lib/AST/TemplateBase.cpp index 2ec0b2cce08..2bdbeb08ef2 100644 --- a/clang/lib/AST/TemplateBase.cpp +++ b/clang/lib/AST/TemplateBase.cpp @@ -161,8 +161,25 @@ static bool needsAmpersandOnTemplateArg(QualType paramType, QualType argType) { // TemplateArgument Implementation //===----------------------------------------------------------------------===// -TemplateArgument::TemplateArgument(ASTContext &Ctx, const llvm::APSInt &Value, - QualType Type, bool IsDefaulted) { +void TemplateArgument::initFromType(QualType T, bool IsNullPtr, + bool IsDefaulted) { + TypeOrValue.Kind = IsNullPtr ? NullPtr : Type; + TypeOrValue.IsDefaulted = IsDefaulted; + TypeOrValue.V = reinterpret_cast(T.getAsOpaquePtr()); +} + +void TemplateArgument::initFromDeclaration(ValueDecl *D, QualType QT, + bool IsDefaulted) { + assert(D && "Expected decl"); + DeclArg.Kind = Declaration; + DeclArg.IsDefaulted = IsDefaulted; + DeclArg.QT = QT.getAsOpaquePtr(); + DeclArg.D = D; +} + +void TemplateArgument::initFromIntegral(const ASTContext &Ctx, + const llvm::APSInt &Value, + QualType Type, bool IsDefaulted) { Integer.Kind = Integral; Integer.IsDefaulted = IsDefaulted; // Copy the APSInt value into our decomposed form. @@ -181,6 +198,56 @@ TemplateArgument::TemplateArgument(ASTContext &Ctx, const llvm::APSInt &Value, Integer.Type = Type.getAsOpaquePtr(); } +void TemplateArgument::initFromStructural(const ASTContext &Ctx, QualType Type, + const APValue &V, bool IsDefaulted) { + Value.Kind = StructuralValue; + Value.IsDefaulted = IsDefaulted; + Value.Value = new (Ctx) APValue(V); + Ctx.addDestruction(Value.Value); + Value.Type = Type.getAsOpaquePtr(); +} + +TemplateArgument::TemplateArgument(const ASTContext &Ctx, + const llvm::APSInt &Value, QualType Type, + bool IsDefaulted) { + initFromIntegral(Ctx, Value, Type, IsDefaulted); +} + +static const ValueDecl *getAsSimpleValueDeclRef(const ASTContext &Ctx, + QualType T, const APValue &V) { + // Pointers to members are relatively easy. + if (V.isMemberPointer() && V.getMemberPointerPath().empty()) + return V.getMemberPointerDecl(); + + // We model class non-type template parameters as their template parameter + // object declaration. + if (V.isStruct() || V.isUnion()) + return Ctx.getTemplateParamObjectDecl(T, V); + + // Pointers and references with an empty path use the special 'Declaration' + // representation. + if (V.isLValue() && V.hasLValuePath() && V.getLValuePath().empty() && + !V.isLValueOnePastTheEnd()) + return V.getLValueBase().dyn_cast(); + + // Everything else uses the 'structural' representation. + return nullptr; +} + +TemplateArgument::TemplateArgument(const ASTContext &Ctx, QualType Type, + const APValue &V, bool IsDefaulted) { + if (Type->isIntegralOrEnumerationType() && V.isInt()) + initFromIntegral(Ctx, V.getInt(), Type, IsDefaulted); + else if ((V.isLValue() && V.isNullPointer()) || + (V.isMemberPointer() && !V.getMemberPointerDecl())) + initFromType(Type, /*isNullPtr=*/true, IsDefaulted); + else if (const ValueDecl *VD = getAsSimpleValueDeclRef(Ctx, Type, V)) + // FIXME: The Declaration form should expose a const ValueDecl*. + initFromDeclaration(const_cast(VD), Type, IsDefaulted); + else + initFromStructural(Ctx, Type, V, IsDefaulted); +} + TemplateArgument TemplateArgument::CreatePackCopy(ASTContext &Context, ArrayRef Args) { @@ -221,6 +288,7 @@ TemplateArgumentDependence TemplateArgument::getDependence() const { case NullPtr: case Integral: + case StructuralValue: return TemplateArgumentDependence::None; case Expression: @@ -251,6 +319,7 @@ bool TemplateArgument::isPackExpansion() const { case Null: case Declaration: case Integral: + case StructuralValue: case Pack: case Template: case NullPtr: @@ -301,6 +370,9 @@ QualType TemplateArgument::getNonTypeTemplateArgumentType() const { case TemplateArgument::NullPtr: return getNullPtrType(); + + case TemplateArgument::StructuralValue: + return getStructuralValueType(); } llvm_unreachable("Invalid TemplateArgument Kind!"); @@ -334,8 +406,13 @@ void TemplateArgument::Profile(llvm::FoldingSetNodeID &ID, break; case Integral: - getAsIntegral().Profile(ID); getIntegralType().Profile(ID); + getAsIntegral().Profile(ID); + break; + + case StructuralValue: + getStructuralValueType().Profile(ID); + getAsStructuralValue().Profile(ID); break; case Expression: @@ -372,6 +449,16 @@ bool TemplateArgument::structurallyEquals(const TemplateArgument &Other) const { return getIntegralType() == Other.getIntegralType() && getAsIntegral() == Other.getAsIntegral(); + case StructuralValue: { + if (getStructuralValueType() != Other.getStructuralValueType()) + return false; + + llvm::FoldingSetNodeID A, B; + getAsStructuralValue().Profile(A); + Other.getAsStructuralValue().Profile(B); + return A == B; + } + case Pack: if (Args.NumArgs != Other.Args.NumArgs) return false; for (unsigned I = 0, E = Args.NumArgs; I != E; ++I) @@ -398,6 +485,7 @@ TemplateArgument TemplateArgument::getPackExpansionPattern() const { case Declaration: case Integral: + case StructuralValue: case Pack: case Null: case Template: @@ -440,6 +528,10 @@ void TemplateArgument::print(const PrintingPolicy &Policy, raw_ostream &Out, break; } + case StructuralValue: + getAsStructuralValue().printPretty(Out, Policy, getStructuralValueType()); + break; + case NullPtr: // FIXME: Include the type if it's not obvious from the context. Out << "nullptr"; @@ -523,6 +615,9 @@ SourceRange TemplateArgumentLoc::getSourceRange() const { case TemplateArgument::Integral: return getSourceIntegralExpression()->getSourceRange(); + case TemplateArgument::StructuralValue: + return getSourceStructuralValueExpression()->getSourceRange(); + case TemplateArgument::Pack: case TemplateArgument::Null: return SourceRange(); @@ -551,6 +646,18 @@ static const T &DiagTemplateArg(const T &DB, const TemplateArgument &Arg) { case TemplateArgument::Integral: return DB << toString(Arg.getAsIntegral(), 10); + case TemplateArgument::StructuralValue: { + // FIXME: We're guessing at LangOptions! + SmallString<32> Str; + llvm::raw_svector_ostream OS(Str); + LangOptions LangOpts; + LangOpts.CPlusPlus = true; + PrintingPolicy Policy(LangOpts); + Arg.getAsStructuralValue().printPretty(OS, Policy, + Arg.getStructuralValueType()); + return DB << OS.str(); + } + case TemplateArgument::Template: return DB << Arg.getAsTemplate(); diff --git a/clang/lib/AST/TextNodeDumper.cpp b/clang/lib/AST/TextNodeDumper.cpp index 369ff66ac4d..48c6729a673 100644 --- a/clang/lib/AST/TextNodeDumper.cpp +++ b/clang/lib/AST/TextNodeDumper.cpp @@ -1875,7 +1875,7 @@ void TextNodeDumper::VisitFunctionDecl(const FunctionDecl *D) { if (D->isModulePrivate()) OS << " __module_private__"; - if (D->isPure()) + if (D->isPureVirtual()) OS << " pure"; if (D->isDefaulted()) { OS << " default"; diff --git a/clang/lib/AST/Type.cpp b/clang/lib/AST/Type.cpp index b419fc8836b..3db5ae182f3 100644 --- a/clang/lib/AST/Type.cpp +++ b/clang/lib/AST/Type.cpp @@ -3459,6 +3459,14 @@ FunctionProtoType::FunctionProtoType(QualType result, ArrayRef params, FunctionTypeBits.HasExtraBitfields = false; } + if (epi.requiresFunctionProtoTypeArmAttributes()) { + auto &ArmTypeAttrs = *getTrailingObjects(); + ArmTypeAttrs = FunctionTypeArmAttributes(); + + // Also set the bit in FunctionTypeExtraBitfields + auto &ExtraBits = *getTrailingObjects(); + ExtraBits.HasArmTypeAttributes = true; + } // Fill in the trailing argument array. auto *argSlot = getTrailingObjects(); @@ -3470,10 +3478,10 @@ FunctionProtoType::FunctionProtoType(QualType result, ArrayRef params, // Propagate the SME ACLE attributes. if (epi.AArch64SMEAttributes != SME_NormalFunction) { - auto &ExtraBits = *getTrailingObjects(); + auto &ArmTypeAttrs = *getTrailingObjects(); assert(epi.AArch64SMEAttributes <= SME_AttributeMask && "Not enough bits to encode SME attributes"); - ExtraBits.AArch64SMEAttributes = epi.AArch64SMEAttributes; + ArmTypeAttrs.AArch64SMEAttributes = epi.AArch64SMEAttributes; } // Fill in the exception type array if present. diff --git a/clang/lib/AST/TypeLoc.cpp b/clang/lib/AST/TypeLoc.cpp index e12b9b50f6e..66732bba18e 100644 --- a/clang/lib/AST/TypeLoc.cpp +++ b/clang/lib/AST/TypeLoc.cpp @@ -586,6 +586,7 @@ void TemplateSpecializationTypeLoc::initializeArgLocs( case TemplateArgument::Integral: case TemplateArgument::Declaration: case TemplateArgument::NullPtr: + case TemplateArgument::StructuralValue: ArgInfos[i] = TemplateArgumentLocInfo(); break; diff --git a/clang/lib/AST/TypePrinter.cpp b/clang/lib/AST/TypePrinter.cpp index f6941242927..80b42c8f84a 100644 --- a/clang/lib/AST/TypePrinter.cpp +++ b/clang/lib/AST/TypePrinter.cpp @@ -937,15 +937,28 @@ void TypePrinter::printFunctionProtoAfter(const FunctionProtoType *T, OS << ')'; FunctionType::ExtInfo Info = T->getExtInfo(); + unsigned SMEBits = T->getAArch64SMEAttributes(); - if ((T->getAArch64SMEAttributes() & FunctionType::SME_PStateSMCompatibleMask)) + if (SMEBits & FunctionType::SME_PStateSMCompatibleMask) OS << " __arm_streaming_compatible"; - if ((T->getAArch64SMEAttributes() & FunctionType::SME_PStateSMEnabledMask)) + if (SMEBits & FunctionType::SME_PStateSMEnabledMask) OS << " __arm_streaming"; - if ((T->getAArch64SMEAttributes() & FunctionType::SME_PStateZASharedMask)) - OS << " __arm_shared_za"; - if ((T->getAArch64SMEAttributes() & FunctionType::SME_PStateZAPreservedMask)) - OS << " __arm_preserves_za"; + if (FunctionType::getArmZAState(SMEBits) == FunctionType::ARM_Preserves) + OS << " __arm_preserves(\"za\")"; + if (FunctionType::getArmZAState(SMEBits) == FunctionType::ARM_In) + OS << " __arm_in(\"za\")"; + if (FunctionType::getArmZAState(SMEBits) == FunctionType::ARM_Out) + OS << " __arm_out(\"za\")"; + if (FunctionType::getArmZAState(SMEBits) == FunctionType::ARM_InOut) + OS << " __arm_inout(\"za\")"; + if (FunctionType::getArmZT0State(SMEBits) == FunctionType::ARM_Preserves) + OS << " __arm_preserves(\"zt0\")"; + if (FunctionType::getArmZT0State(SMEBits) == FunctionType::ARM_In) + OS << " __arm_in(\"zt0\")"; + if (FunctionType::getArmZT0State(SMEBits) == FunctionType::ARM_Out) + OS << " __arm_out(\"zt0\")"; + if (FunctionType::getArmZT0State(SMEBits) == FunctionType::ARM_InOut) + OS << " __arm_inout(\"zt0\")"; printFunctionAfter(Info, OS); @@ -1788,14 +1801,6 @@ void TypePrinter::printAttributedAfter(const AttributedType *T, OS << "__arm_streaming_compatible"; return; } - if (T->getAttrKind() == attr::ArmSharedZA) { - OS << "__arm_shared_za"; - return; - } - if (T->getAttrKind() == attr::ArmPreservesZA) { - OS << "__arm_preserves_za"; - return; - } OS << " __attribute__(("; switch (T->getAttrKind()) { @@ -1839,8 +1844,10 @@ void TypePrinter::printAttributedAfter(const AttributedType *T, case attr::WebAssemblyFuncref: case attr::ArmStreaming: case attr::ArmStreamingCompatible: - case attr::ArmSharedZA: - case attr::ArmPreservesZA: + case attr::ArmIn: + case attr::ArmOut: + case attr::ArmInOut: + case attr::ArmPreserves: llvm_unreachable("This attribute should have been handled already"); case attr::NSReturnsRetained: diff --git a/clang/lib/AST/VTableBuilder.cpp b/clang/lib/AST/VTableBuilder.cpp index 69861c65f6e..a956ca5b37a 100644 --- a/clang/lib/AST/VTableBuilder.cpp +++ b/clang/lib/AST/VTableBuilder.cpp @@ -422,7 +422,7 @@ void FinalOverriders::dump(raw_ostream &Out, BaseSubobject Base, Out << ", " << Overrider.Offset.getQuantity() << ')'; BaseOffset Offset; - if (!Overrider.Method->isPure()) + if (!Overrider.Method->isPureVirtual()) Offset = ComputeReturnAdjustmentBaseOffset(Context, Overrider.Method, MD); if (!Offset.isEmpty()) { @@ -1261,7 +1261,7 @@ ThisAdjustment ItaniumVTableBuilder::ComputeThisAdjustment( const CXXMethodDecl *MD, CharUnits BaseOffsetInLayoutClass, FinalOverriders::OverriderInfo Overrider) { // Ignore adjustments for pure virtual member functions. - if (Overrider.Method->isPure()) + if (Overrider.Method->isPureVirtual()) return ThisAdjustment(); BaseSubobject OverriddenBaseSubobject(MD->getParent(), @@ -1607,7 +1607,7 @@ void ItaniumVTableBuilder::AddMethods( // Check if this overrider needs a return adjustment. // We don't want to do this for pure virtual member functions. BaseOffset ReturnAdjustmentOffset; - if (!OverriderMD->isPure()) { + if (!OverriderMD->isPureVirtual()) { ReturnAdjustmentOffset = ComputeReturnAdjustmentBaseOffset(Context, OverriderMD, MD); } @@ -1959,7 +1959,7 @@ void ItaniumVTableBuilder::dumpLayout(raw_ostream &Out) { std::string Str = PredefinedExpr::ComputeName( PredefinedIdentKind::PrettyFunctionNoVirtual, MD); Out << Str; - if (MD->isPure()) + if (MD->isPureVirtual()) Out << " [pure]"; if (MD->isDeleted()) @@ -2010,7 +2010,7 @@ void ItaniumVTableBuilder::dumpLayout(raw_ostream &Out) { else Out << "() [deleting]"; - if (DD->isPure()) + if (DD->isPureVirtual()) Out << " [pure]"; ThunkInfo Thunk = VTableThunks.lookup(I); @@ -2038,7 +2038,7 @@ void ItaniumVTableBuilder::dumpLayout(raw_ostream &Out) { std::string Str = PredefinedExpr::ComputeName( PredefinedIdentKind::PrettyFunctionNoVirtual, MD); Out << "[unused] " << Str; - if (MD->isPure()) + if (MD->isPureVirtual()) Out << " [pure]"; } @@ -3076,7 +3076,7 @@ void VFTableBuilder::AddMethods(BaseSubobject Base, unsigned BaseDepth, // We don't want to do this for pure virtual member functions. BaseOffset ReturnAdjustmentOffset; ReturnAdjustment ReturnAdjustment; - if (!FinalOverriderMD->isPure()) { + if (!FinalOverriderMD->isPureVirtual()) { ReturnAdjustmentOffset = ComputeReturnAdjustmentBaseOffset(Context, FinalOverriderMD, MD); } @@ -3175,7 +3175,7 @@ void VFTableBuilder::dumpLayout(raw_ostream &Out) { std::string Str = PredefinedExpr::ComputeName( PredefinedIdentKind::PrettyFunctionNoVirtual, MD); Out << Str; - if (MD->isPure()) + if (MD->isPureVirtual()) Out << " [pure]"; if (MD->isDeleted()) @@ -3194,7 +3194,7 @@ void VFTableBuilder::dumpLayout(raw_ostream &Out) { DD->printQualifiedName(Out); Out << "() [scalar deleting]"; - if (DD->isPure()) + if (DD->isPureVirtual()) Out << " [pure]"; ThunkInfo Thunk = VTableThunks.lookup(I); diff --git a/clang/lib/ASTMatchers/ASTMatchersInternal.cpp b/clang/lib/ASTMatchers/ASTMatchersInternal.cpp index 8ed213ca2ce..bf87b1aa099 100644 --- a/clang/lib/ASTMatchers/ASTMatchersInternal.cpp +++ b/clang/lib/ASTMatchers/ASTMatchersInternal.cpp @@ -893,6 +893,7 @@ const internal::VariadicDynCastAllOfMatcher cxxOperatorCallExpr; const internal::VariadicDynCastAllOfMatcher cxxRewrittenBinaryOperator; +const internal::VariadicDynCastAllOfMatcher cxxFoldExpr; const internal::VariadicDynCastAllOfMatcher expr; const internal::VariadicDynCastAllOfMatcher declRefExpr; const internal::VariadicDynCastAllOfMatcher objcIvarRefExpr; diff --git a/clang/lib/ASTMatchers/Dynamic/Registry.cpp b/clang/lib/ASTMatchers/Dynamic/Registry.cpp index 2e43dec331b..15dad022df5 100644 --- a/clang/lib/ASTMatchers/Dynamic/Registry.cpp +++ b/clang/lib/ASTMatchers/Dynamic/Registry.cpp @@ -198,6 +198,7 @@ RegistryMaps::RegistryMaps() { REGISTER_MATCHER(cxxDependentScopeMemberExpr); REGISTER_MATCHER(cxxDestructorDecl); REGISTER_MATCHER(cxxDynamicCastExpr); + REGISTER_MATCHER(cxxFoldExpr); REGISTER_MATCHER(cxxForRangeStmt); REGISTER_MATCHER(cxxFunctionalCastExpr); REGISTER_MATCHER(cxxMemberCallExpr); @@ -319,6 +320,7 @@ RegistryMaps::RegistryMaps() { REGISTER_MATCHER(hasExplicitSpecifier); REGISTER_MATCHER(hasExternalFormalLinkage); REGISTER_MATCHER(hasFalseExpression); + REGISTER_MATCHER(hasFoldInit); REGISTER_MATCHER(hasGlobalStorage); REGISTER_MATCHER(hasImplicitDestinationType); REGISTER_MATCHER(hasInClassInitializer); @@ -344,6 +346,7 @@ RegistryMaps::RegistryMaps() { REGISTER_MATCHER(hasOverloadedOperatorName); REGISTER_MATCHER(hasParameter); REGISTER_MATCHER(hasParent); + REGISTER_MATCHER(hasPattern); REGISTER_MATCHER(hasPointeeLoc); REGISTER_MATCHER(hasQualifier); REGISTER_MATCHER(hasRHS); @@ -404,6 +407,7 @@ RegistryMaps::RegistryMaps() { REGISTER_MATCHER(isAssignmentOperator); REGISTER_MATCHER(isAtPosition); REGISTER_MATCHER(isBaseInitializer); + REGISTER_MATCHER(isBinaryFold); REGISTER_MATCHER(isBitField); REGISTER_MATCHER(isCatchAll); REGISTER_MATCHER(isClass); @@ -447,6 +451,7 @@ RegistryMaps::RegistryMaps() { REGISTER_MATCHER(isInteger); REGISTER_MATCHER(isIntegral); REGISTER_MATCHER(isLambda); + REGISTER_MATCHER(isLeftFold); REGISTER_MATCHER(isListInitialization); REGISTER_MATCHER(isMain); REGISTER_MATCHER(isMemberInitializer); @@ -460,6 +465,7 @@ RegistryMaps::RegistryMaps() { REGISTER_MATCHER(isProtected); REGISTER_MATCHER(isPublic); REGISTER_MATCHER(isPure); + REGISTER_MATCHER(isRightFold); REGISTER_MATCHER(isScoped); REGISTER_MATCHER(isSharedKind); REGISTER_MATCHER(isSignedInteger); @@ -469,6 +475,7 @@ RegistryMaps::RegistryMaps() { REGISTER_MATCHER(isStruct); REGISTER_MATCHER(isTemplateInstantiation); REGISTER_MATCHER(isTypeDependent); + REGISTER_MATCHER(isUnaryFold); REGISTER_MATCHER(isUnion); REGISTER_MATCHER(isUnsignedInteger); REGISTER_MATCHER(isUserProvided); diff --git a/clang/lib/Analysis/ExprMutationAnalyzer.cpp b/clang/lib/Analysis/ExprMutationAnalyzer.cpp index c0de9277ff8..bb042760d29 100644 --- a/clang/lib/Analysis/ExprMutationAnalyzer.cpp +++ b/clang/lib/Analysis/ExprMutationAnalyzer.cpp @@ -243,9 +243,16 @@ const Stmt *ExprMutationAnalyzer::findMutationMemoized( const Stmt *ExprMutationAnalyzer::tryEachDeclRef(const Decl *Dec, MutationFinder Finder) { - const auto Refs = - match(findAll(declRefExpr(to(equalsNode(Dec))).bind(NodeID::value)), - Stm, Context); + const auto Refs = match( + findAll( + declRefExpr(to( + // `Dec` or a binding if `Dec` is a decomposition. + anyOf(equalsNode(Dec), + bindingDecl(forDecomposition(equalsNode(Dec)))) + // + )) + .bind(NodeID::value)), + Stm, Context); for (const auto &RefNodes : Refs) { const auto *E = RefNodes.getNodeAs(NodeID::value); if ((this->*Finder)(E)) @@ -336,6 +343,10 @@ const Stmt *ExprMutationAnalyzer::findDirectMutation(const Expr *Exp) { // in different instantiations of the template. binaryOperator(isTypeDependent(), hasEitherOperand(ignoringImpCasts(canResolveToExpr(Exp)))), + // A fold expression may contain `Exp` as it's initializer. + // We don't know if the operator modifies `Exp` because the + // operator is type dependent due to the parameter pack. + cxxFoldExpr(hasFoldInit(ignoringImpCasts(canResolveToExpr(Exp)))), // Within class templates and member functions the member expression might // not be resolved. In that case, the `callExpr` is considered to be a // modification. diff --git a/clang/lib/Analysis/FlowSensitive/ControlFlowContext.cpp b/clang/lib/Analysis/FlowSensitive/ControlFlowContext.cpp index 56246066e4a..c9ebffe6f37 100644 --- a/clang/lib/Analysis/FlowSensitive/ControlFlowContext.cpp +++ b/clang/lib/Analysis/FlowSensitive/ControlFlowContext.cpp @@ -69,7 +69,7 @@ static llvm::BitVector findReachableBlocks(const CFG &Cfg) { llvm::Expected ControlFlowContext::build(const FunctionDecl &Func) { - if (!Func.hasBody()) + if (!Func.doesThisDeclarationHaveABody()) return llvm::createStringError( std::make_error_code(std::errc::invalid_argument), "Cannot analyze function without a body"); diff --git a/clang/lib/Analysis/FlowSensitive/DataflowAnalysisContext.cpp b/clang/lib/Analysis/FlowSensitive/DataflowAnalysisContext.cpp index fa114979c8e..f4c4af022f5 100644 --- a/clang/lib/Analysis/FlowSensitive/DataflowAnalysisContext.cpp +++ b/clang/lib/Analysis/FlowSensitive/DataflowAnalysisContext.cpp @@ -174,6 +174,9 @@ Solver::Result DataflowAnalysisContext::querySolver( bool DataflowAnalysisContext::flowConditionImplies(Atom Token, const Formula &F) { + if (F.isLiteral(true)) + return true; + // Returns true if and only if truth assignment of the flow condition implies // that `F` is also true. We prove whether or not this property holds by // reducing the problem to satisfiability checking. In other words, we attempt @@ -188,6 +191,9 @@ bool DataflowAnalysisContext::flowConditionImplies(Atom Token, bool DataflowAnalysisContext::flowConditionAllows(Atom Token, const Formula &F) { + if (F.isLiteral(false)) + return false; + llvm::SetVector Constraints; Constraints.insert(&arena().makeAtomRef(Token)); Constraints.insert(&F); @@ -292,7 +298,7 @@ DataflowAnalysisContext::getControlFlowContext(const FunctionDecl *F) { if (It != FunctionContexts.end()) return &It->second; - if (F->hasBody()) { + if (F->doesThisDeclarationHaveABody()) { auto CFCtx = ControlFlowContext::build(*F); // FIXME: Handle errors. assert(CFCtx); diff --git a/clang/lib/Analysis/FlowSensitive/DataflowEnvironment.cpp b/clang/lib/Analysis/FlowSensitive/DataflowEnvironment.cpp index 96fe6df88db..196a1360a77 100644 --- a/clang/lib/Analysis/FlowSensitive/DataflowEnvironment.cpp +++ b/clang/lib/Analysis/FlowSensitive/DataflowEnvironment.cpp @@ -386,7 +386,7 @@ void Environment::initialize() { return; if (const auto *FuncDecl = dyn_cast(DeclCtx)) { - assert(FuncDecl->getBody() != nullptr); + assert(FuncDecl->doesThisDeclarationHaveABody()); initFieldsGlobalsAndFuncs(FuncDecl); @@ -426,7 +426,7 @@ void Environment::initialize() { // FIXME: Add support for resetting globals after function calls to enable // the implementation of sound analyses. void Environment::initFieldsGlobalsAndFuncs(const FunctionDecl *FuncDecl) { - assert(FuncDecl->getBody() != nullptr); + assert(FuncDecl->doesThisDeclarationHaveABody()); FieldSet Fields; llvm::DenseSet Vars; @@ -747,6 +747,7 @@ static bool isOriginalRecordConstructor(const Expr &RecordPRValue) { return !Init->isSemanticForm() || !Init->isTransparent(); return isa(RecordPRValue) || isa(RecordPRValue) || isa(RecordPRValue) || + isa(RecordPRValue) || // The framework currently does not propagate the objects created in // the two branches of a `ConditionalOperator` because there is no way // to reconcile their storage locations, which are different. We @@ -781,8 +782,13 @@ Environment::getResultObjectLocation(const Expr &RecordPRValue) const { return Val->getLoc(); } - // Expression nodes that propagate a record prvalue should have exactly one - // child. + if (auto *Op = dyn_cast(&RecordPRValue); + Op && Op->isCommaOp()) { + return getResultObjectLocation(*Op->getRHS()); + } + + // All other expression nodes that propagate a record prvalue should have + // exactly one child. llvm::SmallVector children(RecordPRValue.child_begin(), RecordPRValue.child_end()); assert(children.size() == 1); @@ -803,13 +809,15 @@ void Environment::setValue(const StorageLocation &Loc, Value &Val) { } void Environment::setValue(const Expr &E, Value &Val) { + const Expr &CanonE = ignoreCFGOmittedNodes(E); + if (auto *RecordVal = dyn_cast(&Val)) { - assert(isOriginalRecordConstructor(E) || - &RecordVal->getLoc() == &getResultObjectLocation(E)); + assert(isOriginalRecordConstructor(CanonE) || + &RecordVal->getLoc() == &getResultObjectLocation(CanonE)); } - assert(E.isPRValue()); - ExprToVal[&E] = &Val; + assert(CanonE.isPRValue()); + ExprToVal[&CanonE] = &Val; } Value *Environment::getValue(const StorageLocation &Loc) const { diff --git a/clang/lib/Analysis/FlowSensitive/SimplifyConstraints.cpp b/clang/lib/Analysis/FlowSensitive/SimplifyConstraints.cpp index 00a3104a57b..cc20202768b 100644 --- a/clang/lib/Analysis/FlowSensitive/SimplifyConstraints.cpp +++ b/clang/lib/Analysis/FlowSensitive/SimplifyConstraints.cpp @@ -131,9 +131,9 @@ void simplifyConstraints(llvm::SetVector &Constraints, for (const auto *Constraint : Constraints) { const Formula &NewConstraint = substitute(*Constraint, Substitutions, arena); - if (&NewConstraint == &arena.makeLiteral(true)) + if (NewConstraint.isLiteral(true)) continue; - if (&NewConstraint == &arena.makeLiteral(false)) { + if (NewConstraint.isLiteral(false)) { contradiction(); return; } diff --git a/clang/lib/Analysis/FlowSensitive/Transfer.cpp b/clang/lib/Analysis/FlowSensitive/Transfer.cpp index 55093c2e2cd..2271a75fbca 100644 --- a/clang/lib/Analysis/FlowSensitive/Transfer.cpp +++ b/clang/lib/Analysis/FlowSensitive/Transfer.cpp @@ -42,6 +42,8 @@ const Environment *StmtToEnvMap::getEnvironment(const Stmt &S) const { assert(BlockIt != CFCtx.getStmtToBlock().end()); if (!CFCtx.isBlockReachable(*BlockIt->getSecond())) return nullptr; + if (BlockIt->getSecond()->getBlockID() == CurBlockID) + return &CurState.Env; const auto &State = BlockToState[BlockIt->getSecond()->getBlockID()]; if (!(State)) return nullptr; diff --git a/clang/lib/Analysis/FlowSensitive/TypeErasedDataflowAnalysis.cpp b/clang/lib/Analysis/FlowSensitive/TypeErasedDataflowAnalysis.cpp index faf83a8920d..49e425bde66 100644 --- a/clang/lib/Analysis/FlowSensitive/TypeErasedDataflowAnalysis.cpp +++ b/clang/lib/Analysis/FlowSensitive/TypeErasedDataflowAnalysis.cpp @@ -75,9 +75,8 @@ using TerminatorVisitorRetTy = std::pair; class TerminatorVisitor : public ConstStmtVisitor { public: - TerminatorVisitor(const StmtToEnvMap &StmtToEnv, Environment &Env, - int BlockSuccIdx) - : StmtToEnv(StmtToEnv), Env(Env), BlockSuccIdx(BlockSuccIdx) {} + TerminatorVisitor(Environment &Env, int BlockSuccIdx) + : Env(Env), BlockSuccIdx(BlockSuccIdx) {} TerminatorVisitorRetTy VisitIfStmt(const IfStmt *S) { auto *Cond = S->getCond(); @@ -126,19 +125,12 @@ public: private: TerminatorVisitorRetTy extendFlowCondition(const Expr &Cond) { - // The terminator sub-expression might not be evaluated. - if (Env.getValue(Cond) == nullptr) - transfer(StmtToEnv, Cond, Env); - auto *Val = Env.get(Cond); - // Value merging depends on flow conditions from different environments - // being mutually exclusive -- that is, they cannot both be true in their - // entirety (even if they may share some clauses). So, we need *some* value - // for the condition expression, even if just an atom. - if (Val == nullptr) { - Val = &Env.makeAtomicBoolValue(); - Env.setValue(Cond, *Val); - } + // In transferCFGBlock(), we ensure that we always have a `Value` for the + // terminator condition, so assert this. + // We consciously assert ourselves instead of asserting via `cast()` so + // that we get a more meaningful line number if the assertion fails. + assert(Val != nullptr); bool ConditionValue = true; // The condition must be inverted for the successor that encompasses the @@ -152,7 +144,6 @@ private: return {&Cond, ConditionValue}; } - const StmtToEnvMap &StmtToEnv; Environment &Env; int BlockSuccIdx; }; @@ -335,10 +326,8 @@ computeBlockInputState(const CFGBlock &Block, AnalysisContext &AC) { // when the terminator is taken. Copy now. TypeErasedDataflowAnalysisState Copy = MaybePredState->fork(); - const StmtToEnvMap StmtToEnv(AC.CFCtx, AC.BlockStates); auto [Cond, CondValue] = - TerminatorVisitor(StmtToEnv, Copy.Env, - blockIndexInPredecessor(*Pred, Block)) + TerminatorVisitor(Copy.Env, blockIndexInPredecessor(*Pred, Block)) .Visit(PredTerminatorStmt); if (Cond != nullptr) // FIXME: Call transferBranchTypeErased even if BuiltinTransferOpts @@ -356,12 +345,13 @@ computeBlockInputState(const CFGBlock &Block, AnalysisContext &AC) { /// Built-in transfer function for `CFGStmt`. static void -builtinTransferStatement(const CFGStmt &Elt, +builtinTransferStatement(unsigned CurBlockID, const CFGStmt &Elt, TypeErasedDataflowAnalysisState &InputState, AnalysisContext &AC) { const Stmt *S = Elt.getStmt(); assert(S != nullptr); - transfer(StmtToEnvMap(AC.CFCtx, AC.BlockStates), *S, InputState.Env); + transfer(StmtToEnvMap(AC.CFCtx, AC.BlockStates, CurBlockID, InputState), *S, + InputState.Env); } /// Built-in transfer function for `CFGInitializer`. @@ -428,12 +418,12 @@ builtinTransferInitializer(const CFGInitializer &Elt, } } -static void builtinTransfer(const CFGElement &Elt, +static void builtinTransfer(unsigned CurBlockID, const CFGElement &Elt, TypeErasedDataflowAnalysisState &State, AnalysisContext &AC) { switch (Elt.getKind()) { case CFGElement::Statement: - builtinTransferStatement(Elt.castAs(), State, AC); + builtinTransferStatement(CurBlockID, Elt.castAs(), State, AC); break; case CFGElement::Initializer: builtinTransferInitializer(Elt.castAs(), State); @@ -477,7 +467,7 @@ transferCFGBlock(const CFGBlock &Block, AnalysisContext &AC, AC.Log.enterElement(Element); // Built-in analysis if (AC.Analysis.builtinOptions()) { - builtinTransfer(Element, State, AC); + builtinTransfer(Block.getBlockID(), Element, State, AC); } // User-provided analysis @@ -489,6 +479,32 @@ transferCFGBlock(const CFGBlock &Block, AnalysisContext &AC, } AC.Log.recordState(State); } + + // If we have a terminator, evaluate its condition. + // This `Expr` may not appear as a `CFGElement` anywhere else, and it's + // important that we evaluate it here (rather than while processing the + // terminator) so that we put the corresponding value in the right + // environment. + if (const Expr *TerminatorCond = + dyn_cast_or_null(Block.getTerminatorCondition())) { + if (State.Env.getValue(*TerminatorCond) == nullptr) + // FIXME: This only runs the builtin transfer, not the analysis-specific + // transfer. Fixing this isn't trivial, as the analysis-specific transfer + // takes a `CFGElement` as input, but some expressions only show up as a + // terminator condition, but not as a `CFGElement`. The condition of an if + // statement is one such example. + transfer( + StmtToEnvMap(AC.CFCtx, AC.BlockStates, Block.getBlockID(), State), + *TerminatorCond, State.Env); + + // If the transfer function didn't produce a value, create an atom so that + // we have *some* value for the condition expression. This ensures that + // when we extend the flow condition, it actually changes. + if (State.Env.getValue(*TerminatorCond) == nullptr) + State.Env.setValue(*TerminatorCond, State.Env.makeAtomicBoolValue()); + AC.Log.recordState(State); + } + return State; } @@ -498,7 +514,8 @@ runTypeErasedDataflowAnalysis( const Environment &InitEnv, std::function - PostVisitCFG) { + PostVisitCFG, + std::int32_t MaxBlockVisits) { PrettyStackTraceAnalysis CrashInfo(CFCtx, "runTypeErasedDataflowAnalysis"); std::optional MaybeStartingEnv; @@ -524,27 +541,20 @@ runTypeErasedDataflowAnalysis( AnalysisContext AC(CFCtx, Analysis, StartingEnv, BlockStates); - // Bugs in lattices and transfer functions can prevent the analysis from - // converging. To limit the damage (infinite loops) that these bugs can cause, - // limit the number of iterations. - // FIXME: Consider making the maximum number of iterations configurable. - // FIXME: Consider restricting the number of backedges followed, rather than - // iterations. - // FIXME: Set up statistics (see llvm/ADT/Statistic.h) to count average number - // of iterations, number of functions that time out, etc. - static constexpr uint32_t MaxAverageVisitsPerBlock = 4; - static constexpr uint32_t AbsoluteMaxIterations = 1 << 16; - const uint32_t RelativeMaxIterations = + // FIXME: remove relative cap. There isn't really any good setting for + // `MaxAverageVisitsPerBlock`, so it has no clear value over using + // `MaxBlockVisits` directly. + static constexpr std::int32_t MaxAverageVisitsPerBlock = 4; + const std::int32_t RelativeMaxBlockVisits = MaxAverageVisitsPerBlock * BlockStates.size(); - const uint32_t MaxIterations = - std::min(RelativeMaxIterations, AbsoluteMaxIterations); - uint32_t Iterations = 0; + MaxBlockVisits = std::min(RelativeMaxBlockVisits, MaxBlockVisits); + std::int32_t BlockVisits = 0; while (const CFGBlock *Block = Worklist.dequeue()) { LLVM_DEBUG(llvm::dbgs() << "Processing Block " << Block->getBlockID() << "\n"); - if (++Iterations > MaxIterations) { + if (++BlockVisits > MaxBlockVisits) { return llvm::createStringError(std::errc::timed_out, - "maximum number of iterations reached"); + "maximum number of blocks processed"); } const std::optional &OldBlockState = diff --git a/clang/lib/Analysis/FlowSensitive/Value.cpp b/clang/lib/Analysis/FlowSensitive/Value.cpp index 349f873f1e6..7fad6deb0e9 100644 --- a/clang/lib/Analysis/FlowSensitive/Value.cpp +++ b/clang/lib/Analysis/FlowSensitive/Value.cpp @@ -27,9 +27,17 @@ static bool areEquivalentIndirectionValues(const Value &Val1, } bool areEquivalentValues(const Value &Val1, const Value &Val2) { - return &Val1 == &Val2 || (Val1.getKind() == Val2.getKind() && - (isa(&Val1) || - areEquivalentIndirectionValues(Val1, Val2))); + if (&Val1 == &Val2) + return true; + if (Val1.getKind() != Val2.getKind()) + return false; + // If values are distinct and have properties, we don't consider them equal, + // leaving equality up to the user model. + if (!Val1.properties().empty() || !Val2.properties().empty()) + return false; + if (isa(&Val1)) + return true; + return areEquivalentIndirectionValues(Val1, Val2); } raw_ostream &operator<<(raw_ostream &OS, const Value &Val) { diff --git a/clang/lib/Analysis/RetainSummaryManager.cpp b/clang/lib/Analysis/RetainSummaryManager.cpp index 6f50d95b179..8d279d969b6 100644 --- a/clang/lib/Analysis/RetainSummaryManager.cpp +++ b/clang/lib/Analysis/RetainSummaryManager.cpp @@ -1098,7 +1098,7 @@ RetainSummaryManager::getStandardMethodSummary(const ObjCMethodDecl *MD, if (S.isKeywordSelector()) { for (unsigned i = 0, e = S.getNumArgs(); i != e; ++i) { StringRef Slot = S.getNameForSlot(i); - if (Slot.substr(Slot.size() - 8).equals_insensitive("delegate")) { + if (Slot.ends_with_insensitive("delegate")) { if (ResultEff == ObjCInitRetE) ResultEff = RetEffect::MakeNoRetHard(); else diff --git a/clang/lib/Analysis/UnsafeBufferUsage.cpp b/clang/lib/Analysis/UnsafeBufferUsage.cpp index 724c4304a07..7df706beb22 100644 --- a/clang/lib/Analysis/UnsafeBufferUsage.cpp +++ b/clang/lib/Analysis/UnsafeBufferUsage.cpp @@ -739,9 +739,10 @@ public: } static Matcher matcher() { + Matcher callExpr = cxxMemberCallExpr( + callee(cxxMethodDecl(hasName("data"), ofClass(hasName("std::span"))))); return stmt( - explicitCastExpr(has(cxxMemberCallExpr(callee(cxxMethodDecl( - hasName("data"), ofClass(hasName("std::span"))))))) + explicitCastExpr(anyOf(has(callExpr), has(parenExpr(has(callExpr))))) .bind(OpTag)); } const Stmt *getBaseStmt() const override { return Op; } diff --git a/clang/lib/Basic/CodeGenOptions.cpp b/clang/lib/Basic/CodeGenOptions.cpp index 182d0a2fa4d..79d715305ef 100644 --- a/clang/lib/Basic/CodeGenOptions.cpp +++ b/clang/lib/Basic/CodeGenOptions.cpp @@ -27,6 +27,8 @@ void CodeGenOptions::resetNonModularOptions(StringRef ModuleFormat) { #define ENUM_DEBUGOPT(Name, Type, Bits, Default) #define CODEGENOPT(Name, Bits, Default) Name = Default; #define ENUM_CODEGENOPT(Name, Type, Bits, Default) set##Name(Default); +// Do not reset AST affecting code generation options. +#define AFFECTING_VALUE_CODEGENOPT(Name, Bits, Default) #include "clang/Basic/CodeGenOptions.def" // Next reset all debug options that can always be reset, because they never diff --git a/clang/lib/Basic/FileManager.cpp b/clang/lib/Basic/FileManager.cpp index d16626b1065..974c8c22598 100644 --- a/clang/lib/Basic/FileManager.cpp +++ b/clang/lib/Basic/FileManager.cpp @@ -532,7 +532,7 @@ void FileManager::fillRealPathName(FileEntry *UFE, llvm::StringRef FileName) { // misleading. We need to clean up the interface here. makeAbsolutePath(AbsPath); llvm::sys::path::remove_dots(AbsPath, /*remove_dot_dot=*/true); - UFE->RealPathName = std::string(AbsPath.str()); + UFE->RealPathName = std::string(AbsPath); } llvm::ErrorOr> diff --git a/clang/lib/Basic/Targets.cpp b/clang/lib/Basic/Targets.cpp index ea002bb464f..e3283510c6a 100644 --- a/clang/lib/Basic/Targets.cpp +++ b/clang/lib/Basic/Targets.cpp @@ -644,6 +644,8 @@ std::unique_ptr AllocateTarget(const llvm::Triple &Triple, return std::make_unique>(Triple, Opts); case llvm::Triple::PS5: return std::make_unique>(Triple, Opts); + case llvm::Triple::Hurd: + return std::make_unique>(Triple, Opts); default: return std::make_unique(Triple, Opts); } diff --git a/clang/lib/Basic/Targets/AArch64.cpp b/clang/lib/Basic/Targets/AArch64.cpp index 9ebaf4d40cd..d47181bfca4 100644 --- a/clang/lib/Basic/Targets/AArch64.cpp +++ b/clang/lib/Basic/Targets/AArch64.cpp @@ -622,9 +622,8 @@ AArch64TargetInfo::getVScaleRange(const LangOptions &LangOpts) const { unsigned AArch64TargetInfo::multiVersionSortPriority(StringRef Name) const { if (Name == "default") return 0; - for (const auto &E : llvm::AArch64::Extensions) - if (Name == E.Name) - return E.FmvPriority; + if (auto Ext = llvm::AArch64::parseArchExtension(Name)) + return Ext->FmvPriority; return 0; } @@ -634,24 +633,19 @@ unsigned AArch64TargetInfo::multiVersionFeatureCost() const { } bool AArch64TargetInfo::doesFeatureAffectCodeGen(StringRef Name) const { - auto F = llvm::find_if(llvm::AArch64::Extensions, [&](const auto &E) { - return Name == E.Name && !E.DependentFeatures.empty(); - }); - return F != std::end(llvm::AArch64::Extensions); + if (auto Ext = llvm::AArch64::parseArchExtension(Name)) + return !Ext->DependentFeatures.empty(); + return false; } StringRef AArch64TargetInfo::getFeatureDependencies(StringRef Name) const { - auto F = llvm::find_if(llvm::AArch64::Extensions, - [&](const auto &E) { return Name == E.Name; }); - return F != std::end(llvm::AArch64::Extensions) ? F->DependentFeatures - : StringRef(); + if (auto Ext = llvm::AArch64::parseArchExtension(Name)) + return Ext->DependentFeatures; + return StringRef(); } bool AArch64TargetInfo::validateCpuSupports(StringRef FeatureStr) const { - for (const auto &E : llvm::AArch64::Extensions) - if (FeatureStr == E.Name) - return true; - return false; + return llvm::AArch64::parseArchExtension(FeatureStr).has_value(); } bool AArch64TargetInfo::hasFeature(StringRef Feature) const { @@ -1093,8 +1087,7 @@ ParsedTargetAttr AArch64TargetInfo::parseTargetAttr(StringRef Features) const { FoundArch = true; std::pair Split = Feature.split("=").second.trim().split("+"); - const std::optional AI = - llvm::AArch64::parseArch(Split.first); + const llvm::AArch64::ArchInfo *AI = llvm::AArch64::parseArch(Split.first); // Parse the architecture version, adding the required features to // Ret.Features. diff --git a/clang/lib/Basic/Targets/AMDGPU.h b/clang/lib/Basic/Targets/AMDGPU.h index 1819ba544cc..90a1516ecdd 100644 --- a/clang/lib/Basic/Targets/AMDGPU.h +++ b/clang/lib/Basic/Targets/AMDGPU.h @@ -169,10 +169,8 @@ public: } bool HasLeftParen = false; - if (S.front() == '{') { + if (S.consume_front("{")) HasLeftParen = true; - S = S.drop_front(); - } if (S.empty()) return false; if (S.front() != 'v' && S.front() != 's' && S.front() != 'a') { @@ -199,29 +197,24 @@ public: return true; } bool HasLeftBracket = false; - if (!S.empty() && S.front() == '[') { + if (S.consume_front("[")) HasLeftBracket = true; - S = S.drop_front(); - } unsigned long long N; if (S.empty() || consumeUnsignedInteger(S, 10, N)) return false; - if (!S.empty() && S.front() == ':') { + if (S.consume_front(":")) { if (!HasLeftBracket) return false; - S = S.drop_front(); unsigned long long M; if (consumeUnsignedInteger(S, 10, M) || N >= M) return false; } if (HasLeftBracket) { - if (S.empty() || S.front() != ']') + if (!S.consume_front("]")) return false; - S = S.drop_front(); } - if (S.empty() || S.front() != '}') + if (!S.consume_front("}")) return false; - S = S.drop_front(); if (!S.empty()) return false; // Found {vn}, {sn}, {an}, {v[n]}, {s[n]}, {a[n]}, {v[n:m]}, {s[n:m]} diff --git a/clang/lib/Basic/Targets/ARM.cpp b/clang/lib/Basic/Targets/ARM.cpp index a72bd42bad4..55b71557452 100644 --- a/clang/lib/Basic/Targets/ARM.cpp +++ b/clang/lib/Basic/Targets/ARM.cpp @@ -227,6 +227,8 @@ StringRef ARMTargetInfo::getCPUAttr() const { return "9_3A"; case llvm::ARM::ArchKind::ARMV9_4A: return "9_4A"; + case llvm::ARM::ArchKind::ARMV9_5A: + return "9_5A"; case llvm::ARM::ArchKind::ARMV8MBaseline: return "8M_BASE"; case llvm::ARM::ArchKind::ARMV8MMainline: @@ -889,6 +891,7 @@ void ARMTargetInfo::getTargetDefines(const LangOptions &Opts, case llvm::ARM::ArchKind::ARMV9_2A: case llvm::ARM::ArchKind::ARMV9_3A: case llvm::ARM::ArchKind::ARMV9_4A: + case llvm::ARM::ArchKind::ARMV9_5A: // Filter __arm_cdp, __arm_ldcl, __arm_stcl in arm_acle.h FeatureCoprocBF = FEATURE_COPROC_B1 | FEATURE_COPROC_B3; break; @@ -1057,6 +1060,7 @@ void ARMTargetInfo::getTargetDefines(const LangOptions &Opts, case llvm::ARM::ArchKind::ARMV9_2A: case llvm::ARM::ArchKind::ARMV9_3A: case llvm::ARM::ArchKind::ARMV9_4A: + case llvm::ARM::ArchKind::ARMV9_5A: getTargetDefinesARMV83A(Opts, Builder); break; } diff --git a/clang/lib/Basic/Targets/OSTargets.h b/clang/lib/Basic/Targets/OSTargets.h index 342af4bbc42..4366c1149e4 100644 --- a/clang/lib/Basic/Targets/OSTargets.h +++ b/clang/lib/Basic/Targets/OSTargets.h @@ -74,7 +74,8 @@ public: this->TLSSupported = !Triple.isOSVersionLT(3); } else if (Triple.isDriverKit()) { // No TLS on DriverKit. - } + } else if (Triple.isXROS()) + this->TLSSupported = true; this->MCountName = "\01mcount"; } @@ -109,6 +110,9 @@ public: case llvm::Triple::WatchOS: // Earliest supporting version is 5.0.0. MinVersion = llvm::VersionTuple(5U); break; + case llvm::Triple::XROS: + MinVersion = llvm::VersionTuple(0); + break; default: // Conservatively return 8 bytes if OS is unknown. return 64; diff --git a/clang/lib/Basic/Targets/PPC.cpp b/clang/lib/Basic/Targets/PPC.cpp index 045c273f03c..41935abfb65 100644 --- a/clang/lib/Basic/Targets/PPC.cpp +++ b/clang/lib/Basic/Targets/PPC.cpp @@ -212,6 +212,7 @@ static void defineXLCompatMacros(MacroBuilder &Builder) { Builder.defineMacro("__darn_32", "__builtin_darn_32"); Builder.defineMacro("__darn_raw", "__builtin_darn_raw"); Builder.defineMacro("__dcbf", "__builtin_dcbf"); + Builder.defineMacro("__fence", "__builtin_ppc_fence"); Builder.defineMacro("__fmadd", "__builtin_fma"); Builder.defineMacro("__fmadds", "__builtin_fmaf"); Builder.defineMacro("__abs", "__builtin_abs"); diff --git a/clang/lib/Basic/Targets/RISCV.cpp b/clang/lib/Basic/Targets/RISCV.cpp index fb312b6cf26..c71b2e9eeb6 100644 --- a/clang/lib/Basic/Targets/RISCV.cpp +++ b/clang/lib/Basic/Targets/RISCV.cpp @@ -154,7 +154,7 @@ void RISCVTargetInfo::getTargetDefines(const LangOptions &Opts, else Builder.defineMacro("__riscv_float_abi_soft"); - if (ABIName == "ilp32e") + if (ABIName == "ilp32e" || ABIName == "lp64e") Builder.defineMacro("__riscv_abi_rve"); Builder.defineMacro("__riscv_arch_test"); @@ -214,6 +214,13 @@ void RISCVTargetInfo::getTargetDefines(const LangOptions &Opts, Builder.defineMacro("__riscv_misaligned_fast"); else Builder.defineMacro("__riscv_misaligned_avoid"); + + if (ISAInfo->hasExtension("e")) { + if (Is64Bit) + Builder.defineMacro("__riscv_64e"); + else + Builder.defineMacro("__riscv_32e"); + } } static constexpr Builtin::Info BuiltinInfo[] = { @@ -234,39 +241,6 @@ ArrayRef RISCVTargetInfo::getTargetBuiltins() const { clang::RISCV::LastTSBuiltin - Builtin::FirstTSBuiltin); } -static std::vector -collectNonISAExtFeature(ArrayRef FeaturesNeedOverride, int XLen) { - std::vector NonISAExtFeatureVec; - - auto IsNonISAExtFeature = [](const std::string &Feature) { - assert(Feature.size() > 1 && (Feature[0] == '+' || Feature[0] == '-')); - StringRef Ext = StringRef(Feature).drop_front(); // drop the +/- - return !llvm::RISCVISAInfo::isSupportedExtensionFeature(Ext); - }; - llvm::copy_if(FeaturesNeedOverride, std::back_inserter(NonISAExtFeatureVec), - IsNonISAExtFeature); - - return NonISAExtFeatureVec; -} - -static std::vector -resolveTargetAttrOverride(const std::vector &FeaturesVec, - int XLen) { - auto I = llvm::find(FeaturesVec, "__RISCV_TargetAttrNeedOverride"); - if (I == FeaturesVec.end()) - return FeaturesVec; - - ArrayRef FeaturesNeedOverride(&*FeaturesVec.begin(), &*I); - std::vector NonISAExtFeature = - collectNonISAExtFeature(FeaturesNeedOverride, XLen); - - std::vector ResolvedFeature(++I, FeaturesVec.end()); - ResolvedFeature.insert(ResolvedFeature.end(), NonISAExtFeature.begin(), - NonISAExtFeature.end()); - - return ResolvedFeature; -} - bool RISCVTargetInfo::initFeatureMap( llvm::StringMap &Features, DiagnosticsEngine &Diags, StringRef CPU, const std::vector &FeaturesVec) const { @@ -280,10 +254,27 @@ bool RISCVTargetInfo::initFeatureMap( Features["32bit"] = true; } - std::vector NewFeaturesVec = - resolveTargetAttrOverride(FeaturesVec, XLen); + // If a target attribute specified a full arch string, override all the ISA + // extension target features. + const auto I = llvm::find(FeaturesVec, "__RISCV_TargetAttrNeedOverride"); + if (I != FeaturesVec.end()) { + std::vector OverrideFeatures(std::next(I), FeaturesVec.end()); - auto ParseResult = llvm::RISCVISAInfo::parseFeatures(XLen, NewFeaturesVec); + // Add back any non ISA extension features, e.g. +relax. + auto IsNonISAExtFeature = [](StringRef Feature) { + assert(Feature.size() > 1 && (Feature[0] == '+' || Feature[0] == '-')); + StringRef Ext = Feature.substr(1); // drop the +/- + return !llvm::RISCVISAInfo::isSupportedExtensionFeature(Ext); + }; + llvm::copy_if(llvm::make_range(FeaturesVec.begin(), I), + std::back_inserter(OverrideFeatures), IsNonISAExtFeature); + + return TargetInfo::initFeatureMap(Features, Diags, CPU, OverrideFeatures); + } + + // Otherwise, parse the features and add any implied extensions. + std::vector AllFeatures = FeaturesVec; + auto ParseResult = llvm::RISCVISAInfo::parseFeatures(XLen, FeaturesVec); if (!ParseResult) { std::string Buffer; llvm::raw_string_ostream OutputErrMsg(Buffer); @@ -294,21 +285,9 @@ bool RISCVTargetInfo::initFeatureMap( return false; } - // RISCVISAInfo makes implications for ISA features - std::vector ImpliedFeatures = (*ParseResult)->toFeatures(); - - // parseFeatures normalizes the feature set by dropping any explicit - // negatives, and non-extension features. We need to preserve the later - // for correctness and want to preserve the former for consistency. - for (auto &Feature : NewFeaturesVec) { - StringRef ExtName = Feature; - assert(ExtName.size() > 1 && (ExtName[0] == '+' || ExtName[0] == '-')); - ExtName = ExtName.drop_front(1); // Drop '+' or '-' - if (!llvm::is_contained(ImpliedFeatures, ("+" + ExtName).str()) && - !llvm::is_contained(ImpliedFeatures, ("-" + ExtName).str())) - ImpliedFeatures.push_back(Feature); - } - return TargetInfo::initFeatureMap(Features, Diags, CPU, ImpliedFeatures); + // Append all features, not just new ones, so we override any negatives. + llvm::append_range(AllFeatures, (*ParseResult)->toFeatures()); + return TargetInfo::initFeatureMap(Features, Diags, CPU, AllFeatures); } std::optional> @@ -378,6 +357,11 @@ bool RISCVTargetInfo::handleTargetFeatures(std::vector &Features, if (llvm::is_contained(Features, "+experimental")) HasExperimental = true; + if (ABI == "ilp32e" && ISAInfo->hasExtension("d")) { + Diags.Report(diag::err_invalid_feature_combination) + << "ILP32E cannot be used with the D ISA extension"; + return false; + } return true; } @@ -412,7 +396,10 @@ static void handleFullArchString(StringRef FullArchStr, // Forward the invalid FullArchStr. Features.push_back("+" + FullArchStr.str()); } else { - std::vector FeatStrings = (*RII)->toFeatures(); + // Append a full list of features, including any negative extensions so that + // we override the CPU's features. + std::vector FeatStrings = + (*RII)->toFeatures(/* AddAllExtensions */ true); Features.insert(Features.end(), FeatStrings.begin(), FeatStrings.end()); } } diff --git a/clang/lib/Basic/Targets/RISCV.h b/clang/lib/Basic/Targets/RISCV.h index f98c88cd45f..bfbdafb682c 100644 --- a/clang/lib/Basic/Targets/RISCV.h +++ b/clang/lib/Basic/Targets/RISCV.h @@ -132,6 +132,12 @@ public: } bool setABI(const std::string &Name) override { + if (Name == "ilp32e") { + ABI = Name; + resetDataLayout("e-m:e-p:32:32-i64:64-n32-S32"); + return true; + } + if (Name == "ilp32" || Name == "ilp32f" || Name == "ilp32d") { ABI = Name; return true; @@ -156,6 +162,12 @@ public: } bool setABI(const std::string &Name) override { + if (Name == "lp64e") { + ABI = Name; + resetDataLayout("e-m:e-p:64:64-i64:64-i128:128-n32:64-S64"); + return true; + } + if (Name == "lp64" || Name == "lp64f" || Name == "lp64d") { ABI = Name; return true; diff --git a/clang/lib/Basic/Targets/SPIR.h b/clang/lib/Basic/Targets/SPIR.h index 9ab2b7c6093..fa4a3bb1c82 100644 --- a/clang/lib/Basic/Targets/SPIR.h +++ b/clang/lib/Basic/Targets/SPIR.h @@ -17,6 +17,7 @@ #include "clang/Basic/TargetInfo.h" #include "clang/Basic/TargetOptions.h" #include "llvm/Support/Compiler.h" +#include "llvm/Support/VersionTuple.h" #include "llvm/TargetParser/Triple.h" #include @@ -301,8 +302,9 @@ public: : BaseSPIRVTargetInfo(Triple, Opts) { assert(Triple.getArch() == llvm::Triple::spirv && "Invalid architecture for Logical SPIR-V."); - assert(Triple.getOS() == llvm::Triple::ShaderModel && - "Logical SPIR-V requires a valid ShaderModel."); + assert(Triple.getOS() == llvm::Triple::Vulkan && + Triple.getVulkanVersion() != llvm::VersionTuple(0) && + "Logical SPIR-V requires a valid Vulkan environment."); assert(Triple.getEnvironment() >= llvm::Triple::Pixel && Triple.getEnvironment() <= llvm::Triple::Amplification && "Logical SPIR-V environment must be a valid shader stage."); diff --git a/clang/lib/Basic/Targets/X86.cpp b/clang/lib/Basic/Targets/X86.cpp index 64e281b888a..a68b662d940 100644 --- a/clang/lib/Basic/Targets/X86.cpp +++ b/clang/lib/Basic/Targets/X86.cpp @@ -1418,6 +1418,14 @@ bool X86TargetInfo::validateAsmConstraint( case 'O': Info.setRequiresImmediate(0, 127); return true; + case 'W': + switch (*++Name) { + default: + return false; + case 's': + Info.setAllowsRegister(); + return true; + } // Register constraints. case 'Y': // 'Y' is the first character for several 2-character constraints. // Shift the pointer to the second character of the constraint. @@ -1715,6 +1723,9 @@ std::string X86TargetInfo::convertConstraint(const char *&Constraint) const { return std::string("{st}"); case 'u': // second from top of floating point stack. return std::string("{st(1)}"); // second from top of floating point stack. + case 'W': + assert(Constraint[1] == 's'); + return '^' + std::string(Constraint++, 2); case 'Y': switch (Constraint[1]) { default: diff --git a/clang/lib/Basic/Warnings.cpp b/clang/lib/Basic/Warnings.cpp index 92954cab6fb..5a5ac555633 100644 --- a/clang/lib/Basic/Warnings.cpp +++ b/clang/lib/Basic/Warnings.cpp @@ -199,8 +199,7 @@ void clang::ProcessWarningOptions(DiagnosticsEngine &Diags, // Check to see if this warning starts with "no-", if so, this is a // negative form of the option. - bool IsPositive = !Opt.starts_with("no-"); - if (!IsPositive) Opt = Opt.substr(3); + bool IsPositive = !Opt.consume_front("no-"); auto Severity = IsPositive ? diag::Severity::Remark : diag::Severity::Ignored; diff --git a/clang/lib/CodeGen/BackendUtil.cpp b/clang/lib/CodeGen/BackendUtil.cpp index a6142d99f3b..ec203f6f28b 100644 --- a/clang/lib/CodeGen/BackendUtil.cpp +++ b/clang/lib/CodeGen/BackendUtil.cpp @@ -1001,8 +1001,9 @@ void EmitAssemblyHelper::RunOptimizationPipeline( } if (CodeGenOpts.FatLTO) { - assert(CodeGenOpts.UnifiedLTO && "FatLTO requires UnifiedLTO"); - MPM.addPass(PB.buildFatLTODefaultPipeline(Level)); + MPM.addPass(PB.buildFatLTODefaultPipeline( + Level, PrepareForThinLTO, + PrepareForThinLTO || shouldEmitRegularLTOSummary())); } else if (PrepareForThinLTO) { MPM.addPass(PB.buildThinLTOPreLinkDefaultPipeline(Level)); } else if (PrepareForLTO) { @@ -1073,8 +1074,7 @@ void EmitAssemblyHelper::RunOptimizationPipeline( if (!TheModule->getModuleFlag("EnableSplitLTOUnit")) TheModule->addModuleFlag(llvm::Module::Error, "EnableSplitLTOUnit", uint32_t(CodeGenOpts.EnableSplitLTOUnit)); - // FatLTO always means UnifiedLTO - if (!TheModule->getModuleFlag("UnifiedLTO")) + if (CodeGenOpts.UnifiedLTO && !TheModule->getModuleFlag("UnifiedLTO")) TheModule->addModuleFlag(llvm::Module::Error, "UnifiedLTO", uint32_t(1)); } diff --git a/clang/lib/CodeGen/CGBuiltin.cpp b/clang/lib/CodeGen/CGBuiltin.cpp index 998fcc3af58..7ef764b8e1a 100644 --- a/clang/lib/CodeGen/CGBuiltin.cpp +++ b/clang/lib/CodeGen/CGBuiltin.cpp @@ -1019,7 +1019,7 @@ CodeGenFunction::emitFlexibleArrayMemberSize(const Expr *E, unsigned Type, FAMSize = Builder.CreateIntCast(FAMSize, ResType, IsSigned); Value *Res = FAMSize; - if (const auto *DRE = dyn_cast(Base)) { + if (isa(Base)) { // The whole struct is specificed in the __bdos. const ASTRecordLayout &Layout = Ctx.getASTRecordLayout(OuterRD); @@ -10056,7 +10056,7 @@ CodeGenFunction::getSVEOverloadTypes(const SVETypeFlags &TypeFlags, llvm::Type *DefaultType = getSVEType(TypeFlags); - if (TypeFlags.isOverloadWhile()) + if (TypeFlags.isOverloadWhileOrMultiVecCvt()) return {DefaultType, Ops[1]->getType()}; if (TypeFlags.isOverloadWhileRW()) @@ -13287,7 +13287,7 @@ Value *CodeGenFunction::EmitBPFBuiltinExpr(unsigned BuiltinID, const auto *DR = cast(CE->getSubExpr()); const auto *Enumerator = cast(DR->getDecl()); - auto &InitVal = Enumerator->getInitVal(); + auto InitVal = Enumerator->getInitVal(); std::string InitValStr; if (InitVal.isNegative() || InitVal > uint64_t(INT64_MAX)) InitValStr = std::to_string(InitVal.getSExtValue()); @@ -18178,6 +18178,45 @@ Value *CodeGenFunction::EmitAMDGPUBuiltinExpr(unsigned BuiltinID, llvm::Function *F = CGM.getIntrinsic(IID, {ArgTy}); return Builder.CreateCall(F, {Addr, Val, ZeroI32, ZeroI32, ZeroI1}); } + case AMDGPU::BI__builtin_amdgcn_global_load_tr_i32: + case AMDGPU::BI__builtin_amdgcn_global_load_tr_v2i32: + case AMDGPU::BI__builtin_amdgcn_global_load_tr_v4f16: + case AMDGPU::BI__builtin_amdgcn_global_load_tr_v4i16: + case AMDGPU::BI__builtin_amdgcn_global_load_tr_v8f16: + case AMDGPU::BI__builtin_amdgcn_global_load_tr_v8i16: { + + llvm::Type *ArgTy; + switch (BuiltinID) { + case AMDGPU::BI__builtin_amdgcn_global_load_tr_i32: + ArgTy = llvm::Type::getInt32Ty(getLLVMContext()); + break; + case AMDGPU::BI__builtin_amdgcn_global_load_tr_v2i32: + ArgTy = llvm::FixedVectorType::get( + llvm::Type::getInt32Ty(getLLVMContext()), 2); + break; + case AMDGPU::BI__builtin_amdgcn_global_load_tr_v4f16: + ArgTy = llvm::FixedVectorType::get( + llvm::Type::getHalfTy(getLLVMContext()), 4); + break; + case AMDGPU::BI__builtin_amdgcn_global_load_tr_v4i16: + ArgTy = llvm::FixedVectorType::get( + llvm::Type::getInt16Ty(getLLVMContext()), 4); + break; + case AMDGPU::BI__builtin_amdgcn_global_load_tr_v8f16: + ArgTy = llvm::FixedVectorType::get( + llvm::Type::getHalfTy(getLLVMContext()), 8); + break; + case AMDGPU::BI__builtin_amdgcn_global_load_tr_v8i16: + ArgTy = llvm::FixedVectorType::get( + llvm::Type::getInt16Ty(getLLVMContext()), 8); + break; + } + + llvm::Value *Addr = EmitScalarExpr(E->getArg(0)); + llvm::Function *F = + CGM.getIntrinsic(Intrinsic::amdgcn_global_load_tr, {ArgTy}); + return Builder.CreateCall(F, {Addr}); + } case AMDGPU::BI__builtin_amdgcn_read_exec: return EmitAMDGCNBallotForExec(*this, E, Int64Ty, Int64Ty, false); case AMDGPU::BI__builtin_amdgcn_read_exec_lo: diff --git a/clang/lib/CodeGen/CGCUDANV.cpp b/clang/lib/CodeGen/CGCUDANV.cpp index 353370f1d76..5b43272bfa6 100644 --- a/clang/lib/CodeGen/CGCUDANV.cpp +++ b/clang/lib/CodeGen/CGCUDANV.cpp @@ -893,7 +893,7 @@ llvm::Function *CGNVCUDARuntime::makeModuleCtorFunction() { llvm::raw_svector_ostream OS(ModuleID); OS << ModuleIDPrefix << llvm::format("%" PRIx64, FatbinWrapper->getGUID()); llvm::Constant *ModuleIDConstant = makeConstantArray( - std::string(ModuleID.str()), "", ModuleIDSectionName, 32, /*AddNull=*/true); + std::string(ModuleID), "", ModuleIDSectionName, 32, /*AddNull=*/true); // Create an alias for the FatbinWrapper that nvcc will look for. llvm::GlobalAlias::create(llvm::GlobalValue::ExternalLinkage, diff --git a/clang/lib/CodeGen/CGCXX.cpp b/clang/lib/CodeGen/CGCXX.cpp index 110e21f7cb6..e95a735f92f 100644 --- a/clang/lib/CodeGen/CGCXX.cpp +++ b/clang/lib/CodeGen/CGCXX.cpp @@ -40,6 +40,11 @@ bool CodeGenModule::TryEmitBaseDestructorAsAlias(const CXXDestructorDecl *D) { if (getCodeGenOpts().OptimizationLevel == 0) return true; + // Disable this optimization for ARM64EC. FIXME: This probably should work, + // but getting the symbol table correct is complicated. + if (getTarget().getTriple().isWindowsArm64EC()) + return true; + // If sanitizing memory to check for use-after-dtor, do not emit as // an alias, unless this class owns no members. if (getCodeGenOpts().SanitizeMemoryUseAfterDtor && diff --git a/clang/lib/CodeGen/CGCall.cpp b/clang/lib/CodeGen/CGCall.cpp index 13677cf150a..28c211aa631 100644 --- a/clang/lib/CodeGen/CGCall.cpp +++ b/clang/lib/CodeGen/CGCall.cpp @@ -1767,14 +1767,31 @@ static void AddAttributesFromFunctionProtoType(ASTContext &Ctx, FPT->isNothrow()) FuncAttrs.addAttribute(llvm::Attribute::NoUnwind); - if (FPT->getAArch64SMEAttributes() & FunctionType::SME_PStateSMEnabledMask) + unsigned SMEBits = FPT->getAArch64SMEAttributes(); + if (SMEBits & FunctionType::SME_PStateSMEnabledMask) FuncAttrs.addAttribute("aarch64_pstate_sm_enabled"); - if (FPT->getAArch64SMEAttributes() & FunctionType::SME_PStateSMCompatibleMask) + if (SMEBits & FunctionType::SME_PStateSMCompatibleMask) FuncAttrs.addAttribute("aarch64_pstate_sm_compatible"); - if (FPT->getAArch64SMEAttributes() & FunctionType::SME_PStateZASharedMask) + + // ZA + if (FunctionType::getArmZAState(SMEBits) == FunctionType::ARM_Out || + FunctionType::getArmZAState(SMEBits) == FunctionType::ARM_InOut) + FuncAttrs.addAttribute("aarch64_pstate_za_shared"); + if (FunctionType::getArmZAState(SMEBits) == FunctionType::ARM_Preserves || + FunctionType::getArmZAState(SMEBits) == FunctionType::ARM_In) { FuncAttrs.addAttribute("aarch64_pstate_za_shared"); - if (FPT->getAArch64SMEAttributes() & FunctionType::SME_PStateZAPreservedMask) FuncAttrs.addAttribute("aarch64_pstate_za_preserved"); + } + + // ZT0 + if (FunctionType::getArmZT0State(SMEBits) == FunctionType::ARM_Preserves) + FuncAttrs.addAttribute("aarch64_preserves_zt0"); + if (FunctionType::getArmZT0State(SMEBits) == FunctionType::ARM_In) + FuncAttrs.addAttribute("aarch64_in_zt0"); + if (FunctionType::getArmZT0State(SMEBits) == FunctionType::ARM_Out) + FuncAttrs.addAttribute("aarch64_out_zt0"); + if (FunctionType::getArmZT0State(SMEBits) == FunctionType::ARM_InOut) + FuncAttrs.addAttribute("aarch64_inout_zt0"); } static void AddAttributesFromAssumes(llvm::AttrBuilder &FuncAttrs, @@ -2446,9 +2463,6 @@ void CodeGenModule::ConstructAttributeList(StringRef Name, if (TargetDecl->hasAttr()) FuncAttrs.addAttribute("aarch64_pstate_sm_body"); - - if (TargetDecl->hasAttr()) - FuncAttrs.addAttribute("aarch64_pstate_za_new"); } // Attach "no-builtins" attributes to: diff --git a/clang/lib/CodeGen/CGCleanup.h b/clang/lib/CodeGen/CGCleanup.h index 079a3e25d6d..fcfbf41b0ea 100644 --- a/clang/lib/CodeGen/CGCleanup.h +++ b/clang/lib/CodeGen/CGCleanup.h @@ -613,6 +613,7 @@ struct EHPersonality { static const EHPersonality MSVC_CxxFrameHandler3; static const EHPersonality GNU_Wasm_CPlusPlus; static const EHPersonality XL_CPlusPlus; + static const EHPersonality ZOS_CPlusPlus; /// Does this personality use landingpads or the family of pad instructions /// designed to form funclets? diff --git a/clang/lib/CodeGen/CGDebugInfo.cpp b/clang/lib/CodeGen/CGDebugInfo.cpp index 236d53bee4e..0f3f684d61d 100644 --- a/clang/lib/CodeGen/CGDebugInfo.cpp +++ b/clang/lib/CodeGen/CGDebugInfo.cpp @@ -1926,7 +1926,7 @@ llvm::DISubprogram *CGDebugInfo::CreateCXXMemberFunction( int ThisAdjustment = 0; if (VTableContextBase::hasVtableSlot(Method)) { - if (Method->isPure()) + if (Method->isPureVirtual()) SPFlags |= llvm::DISubprogram::SPFlagPureVirtual; else SPFlags |= llvm::DISubprogram::SPFlagVirtual; @@ -2201,6 +2201,14 @@ CGDebugInfo::CollectTemplateParams(std::optional OArgs, TemplateParams.push_back(DBuilder.createTemplateValueParameter( TheCU, Name, TTy, defaultParameter, V)); } break; + case TemplateArgument::StructuralValue: { + QualType T = TA.getStructuralValueType(); + llvm::DIType *TTy = getOrCreateType(T, Unit); + llvm::Constant *V = ConstantEmitter(CGM).emitAbstract( + SourceLocation(), TA.getAsStructuralValue(), T); + TemplateParams.push_back(DBuilder.createTemplateValueParameter( + TheCU, Name, TTy, defaultParameter, V)); + } break; case TemplateArgument::Template: { std::string QualName; llvm::raw_string_ostream OS(QualName); @@ -5401,6 +5409,8 @@ std::string CGDebugInfo::GetName(const Decl *D, bool Qualified) const { // feasible some day. return TA.getAsIntegral().getBitWidth() <= 64 && IsReconstitutableType(TA.getIntegralType()); + case TemplateArgument::StructuralValue: + return false; case TemplateArgument::Type: return IsReconstitutableType(TA.getAsType()); default: diff --git a/clang/lib/CodeGen/CGDecl.cpp b/clang/lib/CodeGen/CGDecl.cpp index a5da0aa2965..bbe14ef4c17 100644 --- a/clang/lib/CodeGen/CGDecl.cpp +++ b/clang/lib/CodeGen/CGDecl.cpp @@ -1759,20 +1759,34 @@ void CodeGenFunction::emitZeroOrPatternForAutoVarInit(QualType type, const VarDecl &D, Address Loc) { auto trivialAutoVarInit = getContext().getLangOpts().getTrivialAutoVarInit(); + auto trivialAutoVarInitMaxSize = + getContext().getLangOpts().TrivialAutoVarInitMaxSize; CharUnits Size = getContext().getTypeSizeInChars(type); bool isVolatile = type.isVolatileQualified(); if (!Size.isZero()) { + // We skip auto-init variables by their alloc size. Take this as an example: + // "struct Foo {int x; char buff[1024];}" Assume the max-size flag is 1023. + // All Foo type variables will be skipped. Ideally, we only skip the buff + // array and still auto-init X in this example. + // TODO: Improve the size filtering to by member size. + auto allocSize = CGM.getDataLayout().getTypeAllocSize(Loc.getElementType()); switch (trivialAutoVarInit) { case LangOptions::TrivialAutoVarInitKind::Uninitialized: llvm_unreachable("Uninitialized handled by caller"); case LangOptions::TrivialAutoVarInitKind::Zero: if (CGM.stopAutoInit()) return; + if (trivialAutoVarInitMaxSize > 0 && + allocSize > trivialAutoVarInitMaxSize) + return; emitStoresForZeroInit(CGM, D, Loc, isVolatile, Builder); break; case LangOptions::TrivialAutoVarInitKind::Pattern: if (CGM.stopAutoInit()) return; + if (trivialAutoVarInitMaxSize > 0 && + allocSize > trivialAutoVarInitMaxSize) + return; emitStoresForPatternInit(CGM, D, Loc, isVolatile, Builder); break; } diff --git a/clang/lib/CodeGen/CGException.cpp b/clang/lib/CodeGen/CGException.cpp index 56a246eb65e..5a9d06da12d 100644 --- a/clang/lib/CodeGen/CGException.cpp +++ b/clang/lib/CodeGen/CGException.cpp @@ -127,6 +127,8 @@ const EHPersonality EHPersonality::GNU_Wasm_CPlusPlus = { "__gxx_wasm_personality_v0", nullptr }; const EHPersonality EHPersonality::XL_CPlusPlus = {"__xlcxx_personality_v1", nullptr}; +const EHPersonality EHPersonality::ZOS_CPlusPlus = {"__zos_cxx_personality_v2", + nullptr}; static const EHPersonality &getCPersonality(const TargetInfo &Target, const LangOptions &L) { @@ -187,6 +189,8 @@ static const EHPersonality &getCXXPersonality(const TargetInfo &Target, return EHPersonality::GNU_CPlusPlus_SEH; if (L.hasWasmExceptions()) return EHPersonality::GNU_Wasm_CPlusPlus; + if (T.isOSzOS()) + return EHPersonality::ZOS_CPlusPlus; return EHPersonality::GNU_CPlusPlus; } diff --git a/clang/lib/CodeGen/CGExpr.cpp b/clang/lib/CodeGen/CGExpr.cpp index d12e85b48d0..c5f6b6d3a99 100644 --- a/clang/lib/CodeGen/CGExpr.cpp +++ b/clang/lib/CodeGen/CGExpr.cpp @@ -1516,6 +1516,14 @@ LValue CodeGenFunction::EmitLValue(const Expr *E, return LV; } +static QualType getConstantExprReferredType(const FullExpr *E, + const ASTContext &Ctx) { + const Expr *SE = E->getSubExpr()->IgnoreImplicit(); + if (isa(SE)) + return SE->getType(); + return cast(SE)->getCallReturnType(Ctx)->getPointeeType(); +} + LValue CodeGenFunction::EmitLValueHelper(const Expr *E, KnownNonNull_t IsKnownNonNull) { ApplyDebugLocation DL(*this, E); @@ -1554,9 +1562,7 @@ LValue CodeGenFunction::EmitLValueHelper(const Expr *E, case Expr::ConstantExprClass: { const ConstantExpr *CE = cast(E); if (llvm::Value *Result = ConstantEmitter(*this).tryEmitConstantExpr(CE)) { - QualType RetType = cast(CE->getSubExpr()->IgnoreImplicit()) - ->getCallReturnType(getContext()) - ->getPointeeType(); + QualType RetType = getConstantExprReferredType(CE, getContext()); return MakeNaturalAlignAddrLValue(Result, RetType); } return EmitLValue(cast(E)->getSubExpr(), IsKnownNonNull); diff --git a/clang/lib/CodeGen/CGExprCXX.cpp b/clang/lib/CodeGen/CGExprCXX.cpp index 98ae56e2df8..d136bfc3727 100644 --- a/clang/lib/CodeGen/CGExprCXX.cpp +++ b/clang/lib/CodeGen/CGExprCXX.cpp @@ -1038,11 +1038,25 @@ void CodeGenFunction::EmitNewArrayInitializer( return true; }; + const InitListExpr *ILE = dyn_cast(Init); + const CXXParenListInitExpr *CPLIE = nullptr; + const StringLiteral *SL = nullptr; + const ObjCEncodeExpr *OCEE = nullptr; + const Expr *IgnoreParen = nullptr; + if (!ILE) { + IgnoreParen = Init->IgnoreParenImpCasts(); + CPLIE = dyn_cast(IgnoreParen); + SL = dyn_cast(IgnoreParen); + OCEE = dyn_cast(IgnoreParen); + } + // If the initializer is an initializer list, first do the explicit elements. - if (const InitListExpr *ILE = dyn_cast(Init)) { + if (ILE || CPLIE || SL || OCEE) { // Initializing from a (braced) string literal is a special case; the init // list element does not initialize a (single) array element. - if (ILE->isStringLiteralInit()) { + if ((ILE && ILE->isStringLiteralInit()) || SL || OCEE) { + if (!ILE) + Init = IgnoreParen; // Initialize the initial portion of length equal to that of the string // literal. The allocation must be for at least this much; we emitted a // check for that earlier. @@ -1054,12 +1068,13 @@ void CodeGenFunction::EmitNewArrayInitializer( AggValueSlot::DoesNotOverlap, AggValueSlot::IsNotZeroed, AggValueSlot::IsSanitizerChecked); - EmitAggExpr(ILE->getInit(0), Slot); + EmitAggExpr(ILE ? ILE->getInit(0) : Init, Slot); // Move past these elements. InitListElements = - cast(ILE->getType()->getAsArrayTypeUnsafe()) - ->getSize().getZExtValue(); + cast(Init->getType()->getAsArrayTypeUnsafe()) + ->getSize() + .getZExtValue(); CurPtr = Builder.CreateConstInBoundsGEP( CurPtr, InitListElements, "string.init.end"); @@ -1073,7 +1088,9 @@ void CodeGenFunction::EmitNewArrayInitializer( return; } - InitListElements = ILE->getNumInits(); + ArrayRef InitExprs = + ILE ? ILE->inits() : CPLIE->getInitExprs(); + InitListElements = InitExprs.size(); // If this is a multi-dimensional array new, we will initialize multiple // elements with each init list element. @@ -1101,7 +1118,8 @@ void CodeGenFunction::EmitNewArrayInitializer( } CharUnits StartAlign = CurPtr.getAlignment(); - for (unsigned i = 0, e = ILE->getNumInits(); i != e; ++i) { + unsigned i = 0; + for (const Expr *IE : InitExprs) { // Tell the cleanup that it needs to destroy up to this // element. TODO: some of these stores can be trivially // observed to be unnecessary. @@ -1111,18 +1129,17 @@ void CodeGenFunction::EmitNewArrayInitializer( // FIXME: If the last initializer is an incomplete initializer list for // an array, and we have an array filler, we can fold together the two // initialization loops. - StoreAnyExprIntoOneUnit(*this, ILE->getInit(i), - ILE->getInit(i)->getType(), CurPtr, + StoreAnyExprIntoOneUnit(*this, IE, IE->getType(), CurPtr, AggValueSlot::DoesNotOverlap); CurPtr = Address(Builder.CreateInBoundsGEP( CurPtr.getElementType(), CurPtr.getPointer(), Builder.getSize(1), "array.exp.next"), CurPtr.getElementType(), - StartAlign.alignmentAtOffset((i + 1) * ElementSize)); + StartAlign.alignmentAtOffset((++i) * ElementSize)); } // The remaining elements are filled with the array filler expression. - Init = ILE->getArrayFiller(); + Init = ILE ? ILE->getArrayFiller() : CPLIE->getArrayFiller(); // Extract the initializer for the individual array elements by pulling // out the array filler from all the nested initializer lists. This avoids @@ -1561,16 +1578,23 @@ llvm::Value *CodeGenFunction::EmitCXXNewExpr(const CXXNewExpr *E) { // 1. Build a call to the allocation function. FunctionDecl *allocator = E->getOperatorNew(); - // If there is a brace-initializer, cannot allocate fewer elements than inits. + // If there is a brace-initializer or C++20 parenthesized initializer, cannot + // allocate fewer elements than inits. unsigned minElements = 0; if (E->isArray() && E->hasInitializer()) { - const InitListExpr *ILE = dyn_cast(E->getInitializer()); - if (ILE && ILE->isStringLiteralInit()) + const Expr *Init = E->getInitializer(); + const InitListExpr *ILE = dyn_cast(Init); + const CXXParenListInitExpr *CPLIE = dyn_cast(Init); + const Expr *IgnoreParen = Init->IgnoreParenImpCasts(); + if ((ILE && ILE->isStringLiteralInit()) || + isa(IgnoreParen) || isa(IgnoreParen)) { minElements = - cast(ILE->getType()->getAsArrayTypeUnsafe()) - ->getSize().getZExtValue(); - else if (ILE) - minElements = ILE->getNumInits(); + cast(Init->getType()->getAsArrayTypeUnsafe()) + ->getSize() + .getZExtValue(); + } else if (ILE || CPLIE) { + minElements = ILE ? ILE->getNumInits() : CPLIE->getInitExprs().size(); + } } llvm::Value *numElements = nullptr; diff --git a/clang/lib/CodeGen/CGExprComplex.cpp b/clang/lib/CodeGen/CGExprComplex.cpp index e532794b71b..839fe16cd77 100644 --- a/clang/lib/CodeGen/CGExprComplex.cpp +++ b/clang/lib/CodeGen/CGExprComplex.cpp @@ -892,6 +892,9 @@ ComplexPairTy ComplexExprEmitter::EmitRangeReductionDiv(llvm::Value *LHSr, llvm::Value *LHSi, llvm::Value *RHSr, llvm::Value *RHSi) { + // FIXME: This could eventually be replaced by an LLVM intrinsic to + // avoid this long IR sequence. + // (a + ib) / (c + id) = (e + if) llvm::Value *FAbsRHSr = EmitllvmFAbs(CGF, RHSr); // |c| llvm::Value *FAbsRHSi = EmitllvmFAbs(CGF, RHSi); // |d| @@ -936,7 +939,7 @@ ComplexPairTy ComplexExprEmitter::EmitRangeReductionDiv(llvm::Value *LHSr, llvm::Value *RC = Builder.CreateFMul(CdD, RHSr); // rc llvm::Value *DpRC = Builder.CreateFAdd(RHSi, RC); // tmp=d+rc - llvm::Value *T7 = Builder.CreateFMul(LHSr, RC); // ar + llvm::Value *T7 = Builder.CreateFMul(LHSr, CdD); // ar llvm::Value *T8 = Builder.CreateFAdd(T7, LHSi); // ar+b llvm::Value *DSTFr = Builder.CreateFDiv(T8, DpRC); // (ar+b)/tmp @@ -978,7 +981,10 @@ ComplexPairTy ComplexExprEmitter::EmitBinDiv(const BinOpInfo &Op) { return EmitRangeReductionDiv(LHSr, LHSi, RHSr, RHSi); else if (Op.FPFeatures.getComplexRange() == LangOptions::CX_Limited) return EmitAlgebraicDiv(LHSr, LHSi, RHSr, RHSi); - else if (!CGF.getLangOpts().FastMath) { + else if (!CGF.getLangOpts().FastMath || + // '-ffast-math' is used in the command line but followed by an + // '-fno-cx-limited-range'. + Op.FPFeatures.getComplexRange() == LangOptions::CX_Full) { LHSi = OrigLHSi; // If we have a complex operand on the RHS and FastMath is not allowed, we // delegate to a libcall to handle all of the complexities and minimize diff --git a/clang/lib/CodeGen/CGExprScalar.cpp b/clang/lib/CodeGen/CGExprScalar.cpp index 9ec185153d1..181b15e9c7d 100644 --- a/clang/lib/CodeGen/CGExprScalar.cpp +++ b/clang/lib/CodeGen/CGExprScalar.cpp @@ -4960,6 +4960,13 @@ VisitAbstractConditionalOperator(const AbstractConditionalOperator *E) { CGF.getProfileCount(lhsExpr)); CGF.EmitBlock(LHSBlock); + + // If the top of the logical operator nest, update the MCDC bitmap for the + // ConditionalOperator prior to visiting its LHS and RHS blocks, since they + // may also contain a boolean expression. + if (CGF.MCDCLogOpStack.empty()) + CGF.maybeUpdateMCDCTestVectorBitmap(condExpr); + CGF.incrementProfileCounter(E); eval.begin(CGF); Value *LHS = Visit(lhsExpr); @@ -4969,6 +4976,13 @@ VisitAbstractConditionalOperator(const AbstractConditionalOperator *E) { Builder.CreateBr(ContBlock); CGF.EmitBlock(RHSBlock); + + // If the top of the logical operator nest, update the MCDC bitmap for the + // ConditionalOperator prior to visiting its LHS and RHS blocks, since they + // may also contain a boolean expression. + if (CGF.MCDCLogOpStack.empty()) + CGF.maybeUpdateMCDCTestVectorBitmap(condExpr); + eval.begin(CGF); Value *RHS = Visit(rhsExpr); eval.end(CGF); @@ -4987,10 +5001,6 @@ VisitAbstractConditionalOperator(const AbstractConditionalOperator *E) { PN->addIncoming(LHS, LHSBlock); PN->addIncoming(RHS, RHSBlock); - // If the top of the logical operator nest, update the MCDC bitmap. - if (CGF.MCDCLogOpStack.empty()) - CGF.maybeUpdateMCDCTestVectorBitmap(condExpr); - return PN; } diff --git a/clang/lib/CodeGen/CGObjC.cpp b/clang/lib/CodeGen/CGObjC.cpp index acc85165a47..03fc0ec7ff5 100644 --- a/clang/lib/CodeGen/CGObjC.cpp +++ b/clang/lib/CodeGen/CGObjC.cpp @@ -3941,6 +3941,8 @@ static unsigned getBaseMachOPlatformID(const llvm::Triple &TT) { return llvm::MachO::PLATFORM_TVOS; case llvm::Triple::WatchOS: return llvm::MachO::PLATFORM_WATCHOS; + case llvm::Triple::XROS: + return llvm::MachO::PLATFORM_XROS; case llvm::Triple::DriverKit: return llvm::MachO::PLATFORM_DRIVERKIT; default: @@ -4024,6 +4026,9 @@ static bool isFoundationNeededForDarwinAvailabilityCheck( case llvm::Triple::MacOSX: FoundationDroppedInVersion = VersionTuple(/*Major=*/10, /*Minor=*/15); break; + case llvm::Triple::XROS: + // XROS doesn't need Foundation. + return false; case llvm::Triple::DriverKit: // DriverKit doesn't need Foundation. return false; diff --git a/clang/lib/CodeGen/CGObjCGNU.cpp b/clang/lib/CodeGen/CGObjCGNU.cpp index cd1a0b6a130..a36b0cdddaf 100644 --- a/clang/lib/CodeGen/CGObjCGNU.cpp +++ b/clang/lib/CodeGen/CGObjCGNU.cpp @@ -18,6 +18,8 @@ #include "CGObjCRuntime.h" #include "CodeGenFunction.h" #include "CodeGenModule.h" +#include "CodeGenTypes.h" +#include "SanitizerMetadata.h" #include "clang/AST/ASTContext.h" #include "clang/AST/Attr.h" #include "clang/AST/Decl.h" @@ -597,6 +599,10 @@ public: llvm::Function *GenerateMethod(const ObjCMethodDecl *OMD, const ObjCContainerDecl *CD) override; + + // Map to unify direct method definitions. + llvm::DenseMap + DirectMethodDefinitions; void GenerateDirectMethodPrologue(CodeGenFunction &CGF, llvm::Function *Fn, const ObjCMethodDecl *OMD, const ObjCContainerDecl *CD) override; @@ -917,6 +923,14 @@ class CGObjCGNUstep2 : public CGObjCGNUstep { ClassAliasSection, ConstantStringSection }; + /// The subset of `objc_class_flags` used at compile time. + enum ClassFlags { + /// This is a metaclass + ClassFlagMeta = (1 << 0), + /// This class has been initialised by the runtime (+initialize has been + /// sent if necessary). + ClassFlagInitialized = (1 << 8), + }; static const char *const SectionsBaseNames[8]; static const char *const PECOFFSectionsBaseNames[8]; template @@ -932,6 +946,8 @@ class CGObjCGNUstep2 : public CGObjCGNUstep { /// structure describing the receiver and the class, and a selector as /// arguments. Returns the IMP for the corresponding method. LazyRuntimeFunction MsgLookupSuperFn; + /// Function to ensure that +initialize is sent to a class. + LazyRuntimeFunction SentInitializeFn; /// A flag indicating if we've emitted at least one protocol. /// If we haven't, then we need to emit an empty protocol, to ensure that the /// __start__objc_protocols and __stop__objc_protocols sections exist. @@ -1431,12 +1447,24 @@ class CGObjCGNUstep2 : public CGObjCGNUstep { const std::string &TypeEncoding) override { return GetConstantSelector(Sel, TypeEncoding); } + std::string GetSymbolNameForTypeEncoding(const std::string &TypeEncoding) { + std::string MangledTypes = std::string(TypeEncoding); + // @ is used as a special character in ELF symbol names (used for symbol + // versioning), so mangle the name to not include it. Replace it with a + // character that is not a valid type encoding character (and, being + // non-printable, never will be!) + if (CGM.getTriple().isOSBinFormatELF()) + std::replace(MangledTypes.begin(), MangledTypes.end(), '@', '\1'); + // = in dll exported names causes lld to fail when linking on Windows. + if (CGM.getTriple().isOSWindows()) + std::replace(MangledTypes.begin(), MangledTypes.end(), '=', '\2'); + return MangledTypes; + } llvm::Constant *GetTypeString(llvm::StringRef TypeEncoding) { if (TypeEncoding.empty()) return NULLPtr; - std::string MangledTypes = std::string(TypeEncoding); - std::replace(MangledTypes.begin(), MangledTypes.end(), - '@', '\1'); + std::string MangledTypes = + GetSymbolNameForTypeEncoding(std::string(TypeEncoding)); std::string TypesVarName = ".objc_sel_types_" + MangledTypes; auto *TypesGlobal = TheModule.getGlobalVariable(TypesVarName); if (!TypesGlobal) { @@ -1453,13 +1481,7 @@ class CGObjCGNUstep2 : public CGObjCGNUstep { } llvm::Constant *GetConstantSelector(Selector Sel, const std::string &TypeEncoding) override { - // @ is used as a special character in symbol names (used for symbol - // versioning), so mangle the name to not include it. Replace it with a - // character that is not a valid type encoding character (and, being - // non-printable, never will be!) - std::string MangledTypes = TypeEncoding; - std::replace(MangledTypes.begin(), MangledTypes.end(), - '@', '\1'); + std::string MangledTypes = GetSymbolNameForTypeEncoding(TypeEncoding); auto SelVarName = (StringRef(".objc_selector_") + Sel.getAsString() + "_" + MangledTypes).str(); if (auto *GV = TheModule.getNamedGlobal(SelVarName)) @@ -1671,9 +1693,7 @@ class CGObjCGNUstep2 : public CGObjCGNUstep { const ObjCIvarDecl *Ivar) override { std::string TypeEncoding; CGM.getContext().getObjCEncodingForType(Ivar->getType(), TypeEncoding); - // Prevent the @ from being interpreted as a symbol version. - std::replace(TypeEncoding.begin(), TypeEncoding.end(), - '@', '\1'); + TypeEncoding = GetSymbolNameForTypeEncoding(TypeEncoding); const std::string Name = "__objc_ivar_offset_" + ID->getNameAsString() + '.' + Ivar->getNameAsString() + '.' + TypeEncoding; return Name; @@ -1715,7 +1735,7 @@ class CGObjCGNUstep2 : public CGObjCGNUstep { metaclassFields.addInt(LongTy, 0); // unsigned long info; // objc_class_flag_meta - metaclassFields.addInt(LongTy, 1); + metaclassFields.addInt(LongTy, ClassFlags::ClassFlagMeta); // long instance_size; // Setting this to zero is consistent with the older ABI, but it might be // more sensible to set this to sizeof(struct objc_class) @@ -1989,6 +2009,8 @@ class CGObjCGNUstep2 : public CGObjCGNUstep { CGObjCGNUstep2(CodeGenModule &Mod) : CGObjCGNUstep(Mod, 10, 4, 2) { MsgLookupSuperFn.init(&CGM, "objc_msg_lookup_super", IMPTy, PtrToObjCSuperTy, SelectorTy); + SentInitializeFn.init(&CGM, "objc_send_initialize", + llvm::Type::getVoidTy(VMContext), IdTy); // struct objc_property // { // const char *name; @@ -2002,6 +2024,106 @@ class CGObjCGNUstep2 : public CGObjCGNUstep { { PtrToInt8Ty, PtrToInt8Ty, PtrToInt8Ty, PtrToInt8Ty, PtrToInt8Ty }); } + void GenerateDirectMethodPrologue(CodeGenFunction &CGF, llvm::Function *Fn, + const ObjCMethodDecl *OMD, + const ObjCContainerDecl *CD) override { + auto &Builder = CGF.Builder; + bool ReceiverCanBeNull = true; + auto selfAddr = CGF.GetAddrOfLocalVar(OMD->getSelfDecl()); + auto selfValue = Builder.CreateLoad(selfAddr); + + // Generate: + // + // /* unless the receiver is never NULL */ + // if (self == nil) { + // return (ReturnType){ }; + // } + // + // /* for class methods only to force class lazy initialization */ + // if (!__objc_{class}_initialized) + // { + // objc_send_initialize(class); + // __objc_{class}_initialized = 1; + // } + // + // _cmd = @selector(...) + // ... + + if (OMD->isClassMethod()) { + const ObjCInterfaceDecl *OID = cast(CD); + + // Nullable `Class` expressions cannot be messaged with a direct method + // so the only reason why the receive can be null would be because + // of weak linking. + ReceiverCanBeNull = isWeakLinkedClass(OID); + } + + llvm::MDBuilder MDHelper(CGM.getLLVMContext()); + if (ReceiverCanBeNull) { + llvm::BasicBlock *SelfIsNilBlock = + CGF.createBasicBlock("objc_direct_method.self_is_nil"); + llvm::BasicBlock *ContBlock = + CGF.createBasicBlock("objc_direct_method.cont"); + + // if (self == nil) { + auto selfTy = cast(selfValue->getType()); + auto Zero = llvm::ConstantPointerNull::get(selfTy); + + Builder.CreateCondBr(Builder.CreateICmpEQ(selfValue, Zero), + SelfIsNilBlock, ContBlock, + MDHelper.createBranchWeights(1, 1 << 20)); + + CGF.EmitBlock(SelfIsNilBlock); + + // return (ReturnType){ }; + auto retTy = OMD->getReturnType(); + Builder.SetInsertPoint(SelfIsNilBlock); + if (!retTy->isVoidType()) { + CGF.EmitNullInitialization(CGF.ReturnValue, retTy); + } + CGF.EmitBranchThroughCleanup(CGF.ReturnBlock); + // } + + // rest of the body + CGF.EmitBlock(ContBlock); + Builder.SetInsertPoint(ContBlock); + } + + if (OMD->isClassMethod()) { + // Prefix of the class type. + auto *classStart = + llvm::StructType::get(PtrTy, PtrTy, PtrTy, LongTy, LongTy); + auto &astContext = CGM.getContext(); + auto flags = Builder.CreateLoad( + Address{Builder.CreateStructGEP(classStart, selfValue, 4), LongTy, + CharUnits::fromQuantity( + astContext.getTypeAlign(astContext.UnsignedLongTy))}); + auto isInitialized = + Builder.CreateAnd(flags, ClassFlags::ClassFlagInitialized); + llvm::BasicBlock *notInitializedBlock = + CGF.createBasicBlock("objc_direct_method.class_uninitialized"); + llvm::BasicBlock *initializedBlock = + CGF.createBasicBlock("objc_direct_method.class_initialized"); + Builder.CreateCondBr(Builder.CreateICmpEQ(isInitialized, Zeros[0]), + notInitializedBlock, initializedBlock, + MDHelper.createBranchWeights(1, 1 << 20)); + CGF.EmitBlock(notInitializedBlock); + Builder.SetInsertPoint(notInitializedBlock); + CGF.EmitRuntimeCall(SentInitializeFn, selfValue); + Builder.CreateBr(initializedBlock); + CGF.EmitBlock(initializedBlock); + Builder.SetInsertPoint(initializedBlock); + } + + // only synthesize _cmd if it's referenced + if (OMD->getCmdDecl()->isUsed()) { + // `_cmd` is not a parameter to direct methods, so storage must be + // explicitly declared for it. + CGF.EmitVarDecl(*OMD->getCmdDecl()); + Builder.CreateStore(GetSelector(CGF, OMD), + CGF.GetAddrOfLocalVar(OMD->getCmdDecl())); + } + } }; const char *const CGObjCGNUstep2::SectionsBaseNames[8] = @@ -2645,13 +2767,18 @@ CGObjCGNU::GenerateMessageSend(CodeGenFunction &CGF, } } + bool isDirect = Method && Method->isDirectMethod(); + IdTy = cast(CGM.getTypes().ConvertType(ASTIdTy)); llvm::Value *cmd; - if (Method) - cmd = GetSelector(CGF, Method); - else - cmd = GetSelector(CGF, Sel); - cmd = EnforceType(Builder, cmd, SelectorTy); + if (!isDirect) { + if (Method) + cmd = GetSelector(CGF, Method); + else + cmd = GetSelector(CGF, Sel); + cmd = EnforceType(Builder, cmd, SelectorTy); + } + Receiver = EnforceType(Builder, Receiver, IdTy); llvm::Metadata *impMD[] = { @@ -2663,7 +2790,8 @@ CGObjCGNU::GenerateMessageSend(CodeGenFunction &CGF, CallArgList ActualArgs; ActualArgs.add(RValue::get(Receiver), ASTIdTy); - ActualArgs.add(RValue::get(cmd), CGF.getContext().getObjCSelType()); + if (!isDirect) + ActualArgs.add(RValue::get(cmd), CGF.getContext().getObjCSelType()); ActualArgs.addFrom(CallArgs); MessageSendInfo MSI = getMessageSendInfo(Method, ResultType, ActualArgs); @@ -2682,7 +2810,7 @@ CGObjCGNU::GenerateMessageSend(CodeGenFunction &CGF, // Rather than doing a whole target-specific analysis, we assume it // only works for void, integer, and pointer types, and in all // other cases we do an explicit nil check is emitted code. In - // addition to ensuring we produe a zero value for other types, this + // addition to ensuring we produce a zero value for other types, this // sidesteps the few outright CC incompatibilities we know about that // could otherwise lead to crashes, like when a method is expected to // return on the x87 floating point stack or adjust the stack pointer @@ -2716,8 +2844,9 @@ CGObjCGNU::GenerateMessageSend(CodeGenFunction &CGF, // FIXME: we probably need a size limit here, but we've // never imposed one before } else { - // Otherwise, use an explicit check just to be sure. - requiresExplicitZeroResult = true; + // Otherwise, use an explicit check just to be sure, unless we're + // calling a direct method, where the implementation does this for us. + requiresExplicitZeroResult = !isDirect; } } @@ -2761,10 +2890,14 @@ CGObjCGNU::GenerateMessageSend(CodeGenFunction &CGF, // Get the IMP to call llvm::Value *imp; - // If we have non-legacy dispatch specified, we try using the objc_msgSend() - // functions. These are not supported on all platforms (or all runtimes on a - // given platform), so we - switch (CGM.getCodeGenOpts().getObjCDispatchMethod()) { + // If this is a direct method, just emit it here. + if (isDirect) + imp = GenerateMethod(Method, Method->getClassInterface()); + else + // If we have non-legacy dispatch specified, we try using the + // objc_msgSend() functions. These are not supported on all platforms + // (or all runtimes on a given platform), so we + switch (CGM.getCodeGenOpts().getObjCDispatchMethod()) { case CodeGenOptions::Legacy: imp = LookupIMP(CGF, Receiver, cmd, node, MSI); break; @@ -2787,7 +2920,7 @@ CGObjCGNU::GenerateMessageSend(CodeGenFunction &CGF, llvm::FunctionType::get(IdTy, IdTy, true), "objc_msgSend") .getCallee(); } - } + } // Reset the receiver in case the lookup modified it ActualArgs[0] = CallArg(RValue::get(Receiver), ASTIdTy); @@ -2797,7 +2930,8 @@ CGObjCGNU::GenerateMessageSend(CodeGenFunction &CGF, llvm::CallBase *call; CGCallee callee(CGCalleeInfo(), imp); RValue msgRet = CGF.EmitCall(MSI.CallInfo, callee, Return, ActualArgs, &call); - call->setMetadata(msgSendMDKind, node); + if (!isDirect) + call->setMetadata(msgSendMDKind, node); if (requiresNilReceiverCheck) { llvm::BasicBlock *nonNilPathBB = CGF.Builder.GetInsertBlock(); @@ -3920,14 +4054,50 @@ llvm::Function *CGObjCGNU::GenerateMethod(const ObjCMethodDecl *OMD, CodeGenTypes &Types = CGM.getTypes(); llvm::FunctionType *MethodTy = Types.GetFunctionType(Types.arrangeObjCMethodDeclaration(OMD)); - std::string FunctionName = getSymbolNameForMethod(OMD); - llvm::Function *Method - = llvm::Function::Create(MethodTy, - llvm::GlobalValue::InternalLinkage, - FunctionName, - &TheModule); - return Method; + bool isDirect = OMD->isDirectMethod(); + std::string FunctionName = + getSymbolNameForMethod(OMD, /*include category*/ !isDirect); + + if (!isDirect) + return llvm::Function::Create(MethodTy, + llvm::GlobalVariable::InternalLinkage, + FunctionName, &TheModule); + + auto *COMD = OMD->getCanonicalDecl(); + auto I = DirectMethodDefinitions.find(COMD); + llvm::Function *OldFn = nullptr, *Fn = nullptr; + + if (I == DirectMethodDefinitions.end()) { + auto *F = + llvm::Function::Create(MethodTy, llvm::GlobalVariable::ExternalLinkage, + FunctionName, &TheModule); + DirectMethodDefinitions.insert(std::make_pair(COMD, F)); + return F; + } + + // Objective-C allows for the declaration and implementation types + // to differ slightly. + // + // If we're being asked for the Function associated for a method + // implementation, a previous value might have been cached + // based on the type of the canonical declaration. + // + // If these do not match, then we'll replace this function with + // a new one that has the proper type below. + if (!OMD->getBody() || COMD->getReturnType() == OMD->getReturnType()) + return I->second; + + OldFn = I->second; + Fn = llvm::Function::Create(MethodTy, llvm::GlobalValue::ExternalLinkage, "", + &CGM.getModule()); + Fn->takeName(OldFn); + OldFn->replaceAllUsesWith(Fn); + OldFn->eraseFromParent(); + + // Replace the cached function in the map. + I->second = Fn; + return Fn; } void CGObjCGNU::GenerateDirectMethodPrologue(CodeGenFunction &CGF, diff --git a/clang/lib/CodeGen/CGOpenMPRuntime.cpp b/clang/lib/CodeGen/CGOpenMPRuntime.cpp index ea6645a39e8..4855e7410a0 100644 --- a/clang/lib/CodeGen/CGOpenMPRuntime.cpp +++ b/clang/lib/CodeGen/CGOpenMPRuntime.cpp @@ -1044,6 +1044,13 @@ CGOpenMPRuntime::CGOpenMPRuntime(CodeGenModule &CGM) ? CGM.getLangOpts().OMPHostIRFile : StringRef{}); OMPBuilder.setConfig(Config); + + // The user forces the compiler to behave as if omp requires + // unified_shared_memory was given. + if (CGM.getLangOpts().OpenMPForceUSM) { + HasRequiresUnifiedSharedMemory = true; + OMPBuilder.Config.setHasRequiresUnifiedSharedMemory(true); + } } void CGOpenMPRuntime::clear() { diff --git a/clang/lib/CodeGen/CGStmt.cpp b/clang/lib/CodeGen/CGStmt.cpp index b89017de0bc..beff0ad9da2 100644 --- a/clang/lib/CodeGen/CGStmt.cpp +++ b/clang/lib/CodeGen/CGStmt.cpp @@ -2399,9 +2399,9 @@ EmitAsmStores(CodeGenFunction &CGF, const AsmStmt &S, Tmp = Builder.CreatePtrToInt( Tmp, llvm::IntegerType::get(CTX, (unsigned)TmpSize)); Tmp = Builder.CreateTrunc(Tmp, TruncTy); - } else if (TruncTy->isIntegerTy()) { + } else if (Tmp->getType()->isIntegerTy() && TruncTy->isIntegerTy()) { Tmp = Builder.CreateZExtOrTrunc(Tmp, TruncTy); - } else if (TruncTy->isVectorTy()) { + } else if (Tmp->getType()->isVectorTy() || TruncTy->isVectorTy()) { Tmp = Builder.CreateBitCast(Tmp, TruncTy); } } diff --git a/clang/lib/CodeGen/CGVTables.cpp b/clang/lib/CodeGen/CGVTables.cpp index 27a2cab4f75..8dee3f74b44 100644 --- a/clang/lib/CodeGen/CGVTables.cpp +++ b/clang/lib/CodeGen/CGVTables.cpp @@ -793,7 +793,7 @@ void CodeGenVTables::addVTableComponent(ConstantArrayBuilder &builder, llvm::Constant *fnPtr; // Pure virtual member functions. - if (cast(GD.getDecl())->isPure()) { + if (cast(GD.getDecl())->isPureVirtual()) { if (!PureVirtualFn) PureVirtualFn = getSpecialVirtualFn(CGM.getCXXABI().GetPureVirtualCallName()); diff --git a/clang/lib/CodeGen/CodeGenModule.cpp b/clang/lib/CodeGen/CodeGenModule.cpp index ad6fc71c1e5..1280bcd36de 100644 --- a/clang/lib/CodeGen/CodeGenModule.cpp +++ b/clang/lib/CodeGen/CodeGenModule.cpp @@ -229,7 +229,8 @@ createTargetCodeGenInfo(CodeGenModule &CGM) { ABIFLen = 32; else if (ABIStr.ends_with("d")) ABIFLen = 64; - return createRISCVTargetCodeGenInfo(CGM, XLen, ABIFLen); + bool EABI = ABIStr.ends_with("e"); + return createRISCVTargetCodeGenInfo(CGM, XLen, ABIFLen, EABI); } case llvm::Triple::systemz: { @@ -721,43 +722,70 @@ void InstrProfStats::reportDiagnostics(DiagnosticsEngine &Diags, } } +static std::optional +getLLVMVisibility(clang::LangOptions::VisibilityFromDLLStorageClassKinds K) { + // Map to LLVM visibility. + switch (K) { + case clang::LangOptions::VisibilityFromDLLStorageClassKinds::Keep: + return std::nullopt; + case clang::LangOptions::VisibilityFromDLLStorageClassKinds::Default: + return llvm::GlobalValue::DefaultVisibility; + case clang::LangOptions::VisibilityFromDLLStorageClassKinds::Hidden: + return llvm::GlobalValue::HiddenVisibility; + case clang::LangOptions::VisibilityFromDLLStorageClassKinds::Protected: + return llvm::GlobalValue::ProtectedVisibility; + } + llvm_unreachable("unknown option value!"); +} + +void setLLVMVisibility(llvm::GlobalValue &GV, + std::optional V) { + if (!V) + return; + + // Reset DSO locality before setting the visibility. This removes + // any effects that visibility options and annotations may have + // had on the DSO locality. Setting the visibility will implicitly set + // appropriate globals to DSO Local; however, this will be pessimistic + // w.r.t. to the normal compiler IRGen. + GV.setDSOLocal(false); + GV.setVisibility(*V); +} + static void setVisibilityFromDLLStorageClass(const clang::LangOptions &LO, llvm::Module &M) { if (!LO.VisibilityFromDLLStorageClass) return; - llvm::GlobalValue::VisibilityTypes DLLExportVisibility = - CodeGenModule::GetLLVMVisibility(LO.getDLLExportVisibility()); - llvm::GlobalValue::VisibilityTypes NoDLLStorageClassVisibility = - CodeGenModule::GetLLVMVisibility(LO.getNoDLLStorageClassVisibility()); - llvm::GlobalValue::VisibilityTypes ExternDeclDLLImportVisibility = - CodeGenModule::GetLLVMVisibility(LO.getExternDeclDLLImportVisibility()); - llvm::GlobalValue::VisibilityTypes ExternDeclNoDLLStorageClassVisibility = - CodeGenModule::GetLLVMVisibility( - LO.getExternDeclNoDLLStorageClassVisibility()); + std::optional DLLExportVisibility = + getLLVMVisibility(LO.getDLLExportVisibility()); + + std::optional + NoDLLStorageClassVisibility = + getLLVMVisibility(LO.getNoDLLStorageClassVisibility()); + + std::optional + ExternDeclDLLImportVisibility = + getLLVMVisibility(LO.getExternDeclDLLImportVisibility()); + + std::optional + ExternDeclNoDLLStorageClassVisibility = + getLLVMVisibility(LO.getExternDeclNoDLLStorageClassVisibility()); for (llvm::GlobalValue &GV : M.global_values()) { if (GV.hasAppendingLinkage() || GV.hasLocalLinkage()) continue; - // Reset DSO locality before setting the visibility. This removes - // any effects that visibility options and annotations may have - // had on the DSO locality. Setting the visibility will implicitly set - // appropriate globals to DSO Local; however, this will be pessimistic - // w.r.t. to the normal compiler IRGen. - GV.setDSOLocal(false); - - if (GV.isDeclarationForLinker()) { - GV.setVisibility(GV.getDLLStorageClass() == - llvm::GlobalValue::DLLImportStorageClass - ? ExternDeclDLLImportVisibility - : ExternDeclNoDLLStorageClassVisibility); - } else { - GV.setVisibility(GV.getDLLStorageClass() == - llvm::GlobalValue::DLLExportStorageClass - ? DLLExportVisibility - : NoDLLStorageClassVisibility); - } + if (GV.isDeclarationForLinker()) + setLLVMVisibility(GV, GV.getDLLStorageClass() == + llvm::GlobalValue::DLLImportStorageClass + ? ExternDeclDLLImportVisibility + : ExternDeclNoDLLStorageClassVisibility); + else + setLLVMVisibility(GV, GV.getDLLStorageClass() == + llvm::GlobalValue::DLLExportStorageClass + ? DLLExportVisibility + : NoDLLStorageClassVisibility); GV.setDLLStorageClass(llvm::GlobalValue::DefaultStorageClass); } @@ -1201,7 +1229,7 @@ void CodeGenModule::Release() { llvm::CodeModel::Model codeModel = static_cast(CM); getModule().setCodeModel(codeModel); - if (CM == llvm::CodeModel::Medium && + if ((CM == llvm::CodeModel::Medium || CM == llvm::CodeModel::Large) && Context.getTargetInfo().getTriple().getArch() == llvm::Triple::x86_64) { getModule().setLargeDataThreshold(getCodeGenOpts().LargeDataThreshold); @@ -1688,8 +1716,10 @@ static void AppendCPUSpecificCPUDispatchMangling(const CodeGenModule &CGM, static void AppendTargetVersionMangling(const CodeGenModule &CGM, const TargetVersionAttr *Attr, raw_ostream &Out) { - if (Attr->isDefaultVersion()) + if (Attr->isDefaultVersion()) { + Out << ".default"; return; + } Out << "._"; const TargetInfo &TI = CGM.getTarget(); llvm::SmallVector Feats; @@ -1752,8 +1782,10 @@ static void AppendTargetClonesMangling(const CodeGenModule &CGM, const TargetInfo &TI = CGM.getTarget(); if (TI.getTriple().isAArch64()) { StringRef FeatureStr = Attr->getFeatureStr(VersionIndex); - if (FeatureStr == "default") + if (FeatureStr == "default") { + Out << ".default"; return; + } Out << "._"; SmallVector Features; FeatureStr.split(Features, "+"); @@ -2380,8 +2412,12 @@ void CodeGenModule::SetLLVMFunctionAttributesForDefinition(const Decl *D, if (D->hasAttr()) B.addAttribute("aarch64_pstate_sm_body"); - if (D->hasAttr()) - B.addAttribute("aarch64_pstate_za_new"); + if (auto *Attr = D->getAttr()) { + if (Attr->isNewZA()) + B.addAttribute("aarch64_pstate_za_new"); + if (Attr->isNewZT0()) + B.addAttribute("aarch64_new_zt0"); + } // Track whether we need to add the optnone LLVM attribute, // starting with the default for this optimization level. @@ -3999,6 +4035,8 @@ void CodeGenModule::EmitMultiVersionFunctionDefinition(GlobalDecl GD, EmitGlobalFunctionDefinition(GD.getWithMultiVersionIndex(I), nullptr); // Ensure that the resolver function is also emitted. GetOrCreateMultiVersionResolver(GD); + } else if (FD->hasAttr()) { + GetOrCreateMultiVersionResolver(GD); } else EmitGlobalFunctionDefinition(GD, GV); } @@ -4180,14 +4218,7 @@ void CodeGenModule::emitMultiVersionFunctions() { llvm::Constant *ResolverConstant = GetOrCreateMultiVersionResolver(GD); if (auto *IFunc = dyn_cast(ResolverConstant)) { ResolverConstant = IFunc->getResolver(); - // In Aarch64, default versions of multiversioned functions are mangled to - // their 'normal' assembly name. This deviates from other targets which - // append a '.default' string. As a result we need to continue appending - // .ifunc in Aarch64. - // FIXME: Should Aarch64 mangling for 'default' multiversion function and - // in turn ifunc function match that of other targets? - if (FD->isTargetClonesMultiVersion() && - !getTarget().getTriple().isAArch64()) { + if (FD->isTargetClonesMultiVersion()) { const CGFunctionInfo &FI = getTypes().arrangeGlobalDeclaration(GD); llvm::FunctionType *DeclTy = getTypes().GetFunctionType(FI); std::string MangledName = getMangledNameImpl( @@ -4368,14 +4399,7 @@ llvm::Constant *CodeGenModule::GetOrCreateMultiVersionResolver(GlobalDecl GD) { // a separate resolver). std::string ResolverName = MangledName; if (getTarget().supportsIFunc()) { - // In Aarch64, default versions of multiversioned functions are mangled to - // their 'normal' assembly name. This deviates from other targets which - // append a '.default' string. As a result we need to continue appending - // .ifunc in Aarch64. - // FIXME: Should Aarch64 mangling for 'default' multiversion function and - // in turn ifunc function match that of other targets? - if (!FD->isTargetClonesMultiVersion() || - getTarget().getTriple().isAArch64()) + if (!FD->isTargetClonesMultiVersion()) ResolverName += ".ifunc"; } else if (FD->isTargetMultiVersion()) { ResolverName += ".resolver"; diff --git a/clang/lib/CodeGen/CodeGenPGO.cpp b/clang/lib/CodeGen/CodeGenPGO.cpp index d68844d476e..5d7c3847745 100644 --- a/clang/lib/CodeGen/CodeGenPGO.cpp +++ b/clang/lib/CodeGen/CodeGenPGO.cpp @@ -28,6 +28,8 @@ static llvm::cl::opt llvm::cl::desc("Enable value profiling"), llvm::cl::Hidden, llvm::cl::init(false)); +extern llvm::cl::opt SystemHeadersCoverage; + using namespace clang; using namespace CodeGen; @@ -1022,7 +1024,7 @@ bool CodeGenPGO::skipRegionMappingForDecl(const Decl *D) { // Don't map the functions in system headers. const auto &SM = CGM.getContext().getSourceManager(); auto Loc = D->getBody()->getBeginLoc(); - return SM.isInSystemHeader(Loc); + return !SystemHeadersCoverage && SM.isInSystemHeader(Loc); } void CodeGenPGO::emitCounterRegionMapping(const Decl *D) { diff --git a/clang/lib/CodeGen/CoverageMappingGen.cpp b/clang/lib/CodeGen/CoverageMappingGen.cpp index b245abd16c3..5eca00f22bb 100644 --- a/clang/lib/CodeGen/CoverageMappingGen.cpp +++ b/clang/lib/CodeGen/CoverageMappingGen.cpp @@ -37,7 +37,7 @@ static llvm::cl::opt EmptyLineCommentCoverage( "disable it on test)"), llvm::cl::init(true), llvm::cl::Hidden); -static llvm::cl::opt SystemHeadersCoverage( +llvm::cl::opt SystemHeadersCoverage( "system-headers-coverage", llvm::cl::desc("Enable collecting coverage from system headers"), llvm::cl::init(false), llvm::cl::Hidden); @@ -119,12 +119,16 @@ class SourceMappingRegion { /// as the line execution count if there are no other regions on the line. bool GapRegion; + /// Whetever this region is skipped ('if constexpr' or 'if consteval' untaken + /// branch, or anything skipped but not empty line / comments) + bool SkippedRegion; + public: SourceMappingRegion(Counter Count, std::optional LocStart, std::optional LocEnd, bool GapRegion = false) - : Count(Count), LocStart(LocStart), LocEnd(LocEnd), GapRegion(GapRegion) { - } + : Count(Count), LocStart(LocStart), LocEnd(LocEnd), GapRegion(GapRegion), + SkippedRegion(false) {} SourceMappingRegion(Counter Count, std::optional FalseCount, MCDCParameters MCDCParams, @@ -132,13 +136,14 @@ public: std::optional LocEnd, bool GapRegion = false) : Count(Count), FalseCount(FalseCount), MCDCParams(MCDCParams), - LocStart(LocStart), LocEnd(LocEnd), GapRegion(GapRegion) {} + LocStart(LocStart), LocEnd(LocEnd), GapRegion(GapRegion), + SkippedRegion(false) {} SourceMappingRegion(MCDCParameters MCDCParams, std::optional LocStart, std::optional LocEnd) : MCDCParams(MCDCParams), LocStart(LocStart), LocEnd(LocEnd), - GapRegion(false) {} + GapRegion(false), SkippedRegion(false) {} const Counter &getCounter() const { return Count; } @@ -174,6 +179,10 @@ public: void setGap(bool Gap) { GapRegion = Gap; } + bool isSkipped() const { return SkippedRegion; } + + void setSkipped(bool Skipped) { SkippedRegion = Skipped; } + bool isBranch() const { return FalseCount.has_value(); } bool isMCDCDecision() const { return MCDCParams.NumConditions != 0; } @@ -468,6 +477,10 @@ public: MappingRegions.push_back(CounterMappingRegion::makeGapRegion( Region.getCounter(), *CovFileID, SR.LineStart, SR.ColumnStart, SR.LineEnd, SR.ColumnEnd)); + } else if (Region.isSkipped()) { + MappingRegions.push_back(CounterMappingRegion::makeSkipped( + *CovFileID, SR.LineStart, SR.ColumnStart, SR.LineEnd, + SR.ColumnEnd)); } else if (Region.isBranch()) { MappingRegions.push_back(CounterMappingRegion::makeBranchRegion( Region.getCounter(), Region.getFalseCounter(), @@ -573,6 +586,11 @@ struct EmptyCoverageMappingBuilder : public CoverageMappingBuilder { /// creation. struct MCDCCoverageBuilder { + struct DecisionIDPair { + MCDCConditionID TrueID = 0; + MCDCConditionID FalseID = 0; + }; + /// The AST walk recursively visits nested logical-AND or logical-OR binary /// operator nodes and then visits their LHS and RHS children nodes. As this /// happens, the algorithm will assign IDs to each operator's LHS and RHS side @@ -616,14 +634,14 @@ struct MCDCCoverageBuilder { /// /// A node ID of '0' always means MC/DC isn't being tracked. /// - /// As the AST walk proceeds recursively, the algorithm will also use stacks + /// As the AST walk proceeds recursively, the algorithm will also use a stack /// to track the IDs of logical-AND and logical-OR operations on the RHS so /// that it can be determined which nodes are executed next, depending on how /// a LHS or RHS of a logical-AND or logical-OR is evaluated. This /// information relies on the assigned IDs and are embedded within the /// coverage region IDs of each branch region associated with a leaf-level /// condition. This information helps the visualization tool reconstruct all - /// possible test vectors for the purposes of MC/DC analysis. if a "next" node + /// possible test vectors for the purposes of MC/DC analysis. If a "next" node /// ID is '0', it means it's the end of the test vector. The following rules /// are used: /// @@ -663,54 +681,40 @@ struct MCDCCoverageBuilder { private: CodeGenModule &CGM; - llvm::SmallVector AndRHS; - llvm::SmallVector OrRHS; - llvm::SmallVector NestLevel; + llvm::SmallVector DecisionStack; llvm::DenseMap &CondIDs; llvm::DenseMap &MCDCBitmapMap; MCDCConditionID NextID = 1; bool NotMapped = false; + /// Represent a sentinel value of [0,0] for the bottom of DecisionStack. + static constexpr DecisionIDPair DecisionStackSentinel{0, 0}; + /// Is this a logical-AND operation? bool isLAnd(const BinaryOperator *E) const { return E->getOpcode() == BO_LAnd; } - /// Push an ID onto the corresponding RHS stack. - void pushRHS(const BinaryOperator *E) { - llvm::SmallVector &rhs = isLAnd(E) ? AndRHS : OrRHS; - rhs.push_back(CondIDs[CodeGenFunction::stripCond(E->getRHS())]); - } - - /// Pop an ID from the corresponding RHS stack. - void popRHS(const BinaryOperator *E) { - llvm::SmallVector &rhs = isLAnd(E) ? AndRHS : OrRHS; - if (!rhs.empty()) - rhs.pop_back(); - } - - /// If the expected ID is on top, pop it off the corresponding RHS stack. - void popRHSifTop(const BinaryOperator *E) { - if (!OrRHS.empty() && CondIDs[E] == OrRHS.back()) - OrRHS.pop_back(); - else if (!AndRHS.empty() && CondIDs[E] == AndRHS.back()) - AndRHS.pop_back(); - } - public: MCDCCoverageBuilder(CodeGenModule &CGM, llvm::DenseMap &CondIDMap, llvm::DenseMap &MCDCBitmapMap) - : CGM(CGM), CondIDs(CondIDMap), MCDCBitmapMap(MCDCBitmapMap) {} + : CGM(CGM), DecisionStack(1, DecisionStackSentinel), CondIDs(CondIDMap), + MCDCBitmapMap(MCDCBitmapMap) {} - /// Return the ID of the RHS of the next, upper nest-level logical-OR. - MCDCConditionID getNextLOrCondID() const { - return OrRHS.empty() ? 0 : OrRHS.back(); - } + /// Return whether the build of the control flow map is at the top-level + /// (root) of a logical operator nest in a boolean expression prior to the + /// assignment of condition IDs. + bool isIdle() const { return (NextID == 1 && !NotMapped); } - /// Return the ID of the RHS of the next, upper nest-level logical-AND. - MCDCConditionID getNextLAndCondID() const { - return AndRHS.empty() ? 0 : AndRHS.back(); + /// Return whether any IDs have been assigned in the build of the control + /// flow map, indicating that the map is being generated for this boolean + /// expression. + bool isBuilding() const { return (NextID > 1); } + + /// Set the given condition's ID. + void setCondID(const Expr *Cond, MCDCConditionID ID) { + CondIDs[CodeGenFunction::stripCond(Cond)] = ID; } /// Return the ID of a given condition. @@ -722,6 +726,9 @@ public: return I->second; } + /// Return the LHS Decision ([0,0] if not set). + const DecisionIDPair &back() const { return DecisionStack.back(); } + /// Push the binary operator statement to track the nest level and assign IDs /// to the operator's LHS and RHS. The RHS may be a larger subtree that is /// broken up on successive levels. @@ -730,68 +737,67 @@ public: return; // If binary expression is disqualified, don't do mapping. - if (NestLevel.empty() && MCDCBitmapMap.find(CodeGenFunction::stripCond( - E)) == MCDCBitmapMap.end()) + if (!isBuilding() && !MCDCBitmapMap.contains(CodeGenFunction::stripCond(E))) NotMapped = true; - // Push Stmt on 'NestLevel' stack to keep track of nest location. - NestLevel.push_back(E); - // Don't go any further if we don't need to map condition IDs. if (NotMapped) return; + const DecisionIDPair &ParentDecision = DecisionStack.back(); + // If the operator itself has an assigned ID, this means it represents a - // larger subtree. In this case, pop its ID out of the RHS stack and - // assign that ID to its LHS node. Its RHS will receive a new ID. - if (CondIDs.find(CodeGenFunction::stripCond(E)) != CondIDs.end()) { - // If Stmt has an ID, assign its ID to LHS - CondIDs[CodeGenFunction::stripCond(E->getLHS())] = CondIDs[E]; + // larger subtree. In this case, assign that ID to its LHS node. Its RHS + // will receive a new ID below. Otherwise, assign ID+1 to LHS. + if (CondIDs.contains(CodeGenFunction::stripCond(E))) + setCondID(E->getLHS(), getCondID(E)); + else + setCondID(E->getLHS(), NextID++); - // Since the operator's LHS assumes the operator's same ID, pop the - // operator from the RHS stack so that if LHS short-circuits, it won't be - // incorrectly re-used as the node executed next. - popRHSifTop(E); - } else { - // Otherwise, assign ID+1 to LHS. - CondIDs[CodeGenFunction::stripCond(E->getLHS())] = NextID++; - } + // Assign a ID+1 for the RHS. + MCDCConditionID RHSid = NextID++; + setCondID(E->getRHS(), RHSid); - // Assign ID+1 to RHS. - CondIDs[CodeGenFunction::stripCond(E->getRHS())] = NextID++; - - // Push ID of Stmt's RHS so that LHS nodes know about it - pushRHS(E); + // Push the LHS decision IDs onto the DecisionStack. + if (isLAnd(E)) + DecisionStack.push_back({RHSid, ParentDecision.FalseID}); + else + DecisionStack.push_back({ParentDecision.TrueID, RHSid}); } - /// Pop the binary operator from the next level. If the walk is at the top of - /// the next, assign the total number of conditions. - unsigned popAndReturnCondCount(const BinaryOperator *E) { + /// Pop and return the LHS Decision ([0,0] if not set). + DecisionIDPair pop() { + if (!CGM.getCodeGenOpts().MCDCCoverage || NotMapped) + return DecisionStack.front(); + + assert(DecisionStack.size() > 1); + DecisionIDPair D = DecisionStack.back(); + DecisionStack.pop_back(); + return D; + } + + /// Return the total number of conditions and reset the state. The number of + /// conditions is zero if the expression isn't mapped. + unsigned getTotalConditionsAndReset(const BinaryOperator *E) { if (!CGM.getCodeGenOpts().MCDCCoverage) return 0; - unsigned TotalConds = 0; - - // Pop Stmt from 'NestLevel' stack. - assert(NestLevel.back() == E); - NestLevel.pop_back(); + assert(!isIdle()); + assert(DecisionStack.size() == 1); // Reset state if not doing mapping. - if (NestLevel.empty() && NotMapped) { + if (NotMapped) { NotMapped = false; + assert(NextID == 1); return 0; } - // Pop RHS ID. - popRHS(E); + // Set number of conditions and reset. + unsigned TotalConds = NextID - 1; - // If at the parent (NestLevel=0), set conds and reset. - if (NestLevel.empty()) { - TotalConds = NextID - 1; + // Reset ID back to beginning. + NextID = 1; - // Reset ID back to beginning. - NextID = 1; - } return TotalConds; } }; @@ -1018,13 +1024,15 @@ struct CounterCoverageMappingBuilder return (Cond->EvaluateAsInt(Result, CVM.getCodeGenModule().getContext())); } + using MCDCDecisionIDPair = MCDCCoverageBuilder::DecisionIDPair; + /// Create a Branch Region around an instrumentable condition for coverage /// and add it to the function's SourceRegions. A branch region tracks a /// "True" counter and a "False" counter for boolean expressions that /// result in the generation of a branch. - void createBranchRegion(const Expr *C, Counter TrueCnt, Counter FalseCnt, - MCDCConditionID ID = 0, MCDCConditionID TrueID = 0, - MCDCConditionID FalseID = 0) { + void + createBranchRegion(const Expr *C, Counter TrueCnt, Counter FalseCnt, + const MCDCDecisionIDPair &IDPair = MCDCDecisionIDPair()) { // Check for NULL conditions. if (!C) return; @@ -1034,6 +1042,10 @@ struct CounterCoverageMappingBuilder // function's SourceRegions) because it doesn't apply to any other source // code other than the Condition. if (CodeGenFunction::isInstrumentedCondition(C)) { + MCDCConditionID ID = MCDCBuilder.getCondID(C); + MCDCConditionID TrueID = IDPair.TrueID; + MCDCConditionID FalseID = IDPair.FalseID; + // If a condition can fold to true or false, the corresponding branch // will be removed. Create a region with both counters hard-coded to // zero. This allows us to visualize them in a special way. @@ -1252,6 +1264,69 @@ struct CounterCoverageMappingBuilder popRegions(Index); } + /// Find a valid range starting with \p StartingLoc and ending before \p + /// BeforeLoc. + std::optional findAreaStartingFromTo(SourceLocation StartingLoc, + SourceLocation BeforeLoc) { + // If StartingLoc is in function-like macro, use its start location. + if (StartingLoc.isMacroID()) { + FileID FID = SM.getFileID(StartingLoc); + const SrcMgr::ExpansionInfo *EI = &SM.getSLocEntry(FID).getExpansion(); + if (EI->isFunctionMacroExpansion()) + StartingLoc = EI->getExpansionLocStart(); + } + + size_t StartDepth = locationDepth(StartingLoc); + size_t EndDepth = locationDepth(BeforeLoc); + while (!SM.isWrittenInSameFile(StartingLoc, BeforeLoc)) { + bool UnnestStart = StartDepth >= EndDepth; + bool UnnestEnd = EndDepth >= StartDepth; + if (UnnestEnd) { + assert(SM.isWrittenInSameFile(getStartOfFileOrMacro(BeforeLoc), + BeforeLoc)); + + BeforeLoc = getIncludeOrExpansionLoc(BeforeLoc); + assert(BeforeLoc.isValid()); + EndDepth--; + } + if (UnnestStart) { + assert(SM.isWrittenInSameFile(StartingLoc, + getStartOfFileOrMacro(StartingLoc))); + + StartingLoc = getIncludeOrExpansionLoc(StartingLoc); + assert(StartingLoc.isValid()); + StartDepth--; + } + } + // If the start and end locations of the gap are both within the same macro + // file, the range may not be in source order. + if (StartingLoc.isMacroID() || BeforeLoc.isMacroID()) + return std::nullopt; + if (!SM.isWrittenInSameFile(StartingLoc, BeforeLoc) || + !SpellingRegion(SM, StartingLoc, BeforeLoc).isInSourceOrder()) + return std::nullopt; + return {{StartingLoc, BeforeLoc}}; + } + + void markSkipped(SourceLocation StartLoc, SourceLocation BeforeLoc) { + const auto Skipped = findAreaStartingFromTo(StartLoc, BeforeLoc); + + if (!Skipped) + return; + + const auto NewStartLoc = Skipped->getBegin(); + const auto EndLoc = Skipped->getEnd(); + + if (NewStartLoc == EndLoc) + return; + assert(SpellingRegion(SM, NewStartLoc, EndLoc).isInSourceOrder()); + handleFileExit(NewStartLoc); + size_t Index = pushRegion({}, NewStartLoc, EndLoc); + getRegion().setSkipped(true); + handleFileExit(EndLoc); + popRegions(Index); + } + /// Keep counts of breaks and continues inside loops. struct BreakContinue { Counter BreakCount; @@ -1701,43 +1776,119 @@ struct CounterCoverageMappingBuilder Visit(S->getSubStmt()); } + void coverIfConsteval(const IfStmt *S) { + assert(S->isConsteval()); + + const auto *Then = S->getThen(); + const auto *Else = S->getElse(); + + // It's better for llvm-cov to create a new region with same counter + // so line-coverage can be properly calculated for lines containing + // a skipped region (without it the line is marked uncovered) + const Counter ParentCount = getRegion().getCounter(); + + extendRegion(S); + + if (S->isNegatedConsteval()) { + // ignore 'if consteval' + markSkipped(S->getIfLoc(), getStart(Then)); + propagateCounts(ParentCount, Then); + + if (Else) { + // ignore 'else ' + markSkipped(getEnd(Then), getEnd(Else)); + } + } else { + assert(S->isNonNegatedConsteval()); + // ignore 'if consteval [else]' + markSkipped(S->getIfLoc(), Else ? getStart(Else) : getEnd(Then)); + + if (Else) + propagateCounts(ParentCount, Else); + } + } + + void coverIfConstexpr(const IfStmt *S) { + assert(S->isConstexpr()); + + // evaluate constant condition... + const auto *E = cast(S->getCond()); + const bool isTrue = E->getResultAsAPSInt().getExtValue(); + + extendRegion(S); + + // I'm using 'propagateCounts' later as new region is better and allows me + // to properly calculate line coverage in llvm-cov utility + const Counter ParentCount = getRegion().getCounter(); + + // ignore 'if constexpr (' + SourceLocation startOfSkipped = S->getIfLoc(); + + if (const auto *Init = S->getInit()) { + const auto start = getStart(Init); + const auto end = getEnd(Init); + + // this check is to make sure typedef here which doesn't have valid source + // location won't crash it + if (start.isValid() && end.isValid()) { + markSkipped(startOfSkipped, start); + propagateCounts(ParentCount, Init); + startOfSkipped = getEnd(Init); + } + } + + const auto *Then = S->getThen(); + const auto *Else = S->getElse(); + + if (isTrue) { + // ignore ')' + markSkipped(startOfSkipped, getStart(Then)); + propagateCounts(ParentCount, Then); + + if (Else) + // ignore 'else ' + markSkipped(getEnd(Then), getEnd(Else)); + } else { + // ignore ') [else]' + markSkipped(startOfSkipped, Else ? getStart(Else) : getEnd(Then)); + + if (Else) + propagateCounts(ParentCount, Else); + } + } + void VisitIfStmt(const IfStmt *S) { + // "if constexpr" and "if consteval" are not normal conditional statements, + // their discarded statement should be skipped + if (S->isConsteval()) + return coverIfConsteval(S); + else if (S->isConstexpr()) + return coverIfConstexpr(S); + extendRegion(S); if (S->getInit()) Visit(S->getInit()); // Extend into the condition before we propagate through it below - this is // needed to handle macros that generate the "if" but not the condition. - if (!S->isConsteval()) - extendRegion(S->getCond()); + extendRegion(S->getCond()); Counter ParentCount = getRegion().getCounter(); + Counter ThenCount = getRegionCounter(S); - // If this is "if !consteval" the then-branch will never be taken, we don't - // need to change counter - Counter ThenCount = - S->isNegatedConsteval() ? ParentCount : getRegionCounter(S); + // Emitting a counter for the condition makes it easier to interpret the + // counter for the body when looking at the coverage. + propagateCounts(ParentCount, S->getCond()); - if (!S->isConsteval()) { - // Emitting a counter for the condition makes it easier to interpret the - // counter for the body when looking at the coverage. - propagateCounts(ParentCount, S->getCond()); - - // The 'then' count applies to the area immediately after the condition. - std::optional Gap = - findGapAreaBetween(S->getRParenLoc(), getStart(S->getThen())); - if (Gap) - fillGapAreaWithCount(Gap->getBegin(), Gap->getEnd(), ThenCount); - } + // The 'then' count applies to the area immediately after the condition. + std::optional Gap = + findGapAreaBetween(S->getRParenLoc(), getStart(S->getThen())); + if (Gap) + fillGapAreaWithCount(Gap->getBegin(), Gap->getEnd(), ThenCount); extendRegion(S->getThen()); Counter OutCount = propagateCounts(ThenCount, S->getThen()); - - // If this is "if consteval" the else-branch will never be taken, we don't - // need to change counter - Counter ElseCount = S->isNonNegatedConsteval() - ? ParentCount - : subtractCounters(ParentCount, ThenCount); + Counter ElseCount = subtractCounters(ParentCount, ThenCount); if (const Stmt *Else = S->getElse()) { bool ThenHasTerminateStmt = HasTerminateStmt; @@ -1760,11 +1911,9 @@ struct CounterCoverageMappingBuilder GapRegionCounter = OutCount; } - if (!S->isConsteval()) { - // Create Branch Region around condition. - createBranchRegion(S->getCond(), ThenCount, - subtractCounters(ParentCount, ThenCount)); - } + // Create Branch Region around condition. + createBranchRegion(S->getCond(), ThenCount, + subtractCounters(ParentCount, ThenCount)); } void VisitCXXTryStmt(const CXXTryStmt *S) { @@ -1822,20 +1971,28 @@ struct CounterCoverageMappingBuilder } void VisitBinLAnd(const BinaryOperator *E) { - // Keep track of Binary Operator and assign MCDC condition IDs + bool IsRootNode = MCDCBuilder.isIdle(); + + // Keep track of Binary Operator and assign MCDC condition IDs. MCDCBuilder.pushAndAssignIDs(E); extendRegion(E->getLHS()); propagateCounts(getRegion().getCounter(), E->getLHS()); handleFileExit(getEnd(E->getLHS())); + // Track LHS True/False Decision. + const auto DecisionLHS = MCDCBuilder.pop(); + // Counter tracks the right hand side of a logical and operator. extendRegion(E->getRHS()); propagateCounts(getRegionCounter(E), E->getRHS()); - // Process Binary Operator and create MCDC Decision Region if top-level + // Track RHS True/False Decision. + const auto DecisionRHS = MCDCBuilder.back(); + + // Create MCDC Decision Region if at top-level (root). unsigned NumConds = 0; - if ((NumConds = MCDCBuilder.popAndReturnCondCount(E))) + if (IsRootNode && (NumConds = MCDCBuilder.getTotalConditionsAndReset(E))) createDecisionRegion(E, getRegionBitmap(E), NumConds); // Extract the RHS's Execution Counter. @@ -1847,30 +2004,13 @@ struct CounterCoverageMappingBuilder // Extract the Parent Region Counter. Counter ParentCnt = getRegion().getCounter(); - // Extract the MCDC condition IDs (returns 0 if not needed). - MCDCConditionID NextOrID = MCDCBuilder.getNextLOrCondID(); - MCDCConditionID NextAndID = MCDCBuilder.getNextLAndCondID(); - MCDCConditionID LHSid = MCDCBuilder.getCondID(E->getLHS()); - MCDCConditionID RHSid = MCDCBuilder.getCondID(E->getRHS()); - // Create Branch Region around LHS condition. - // MC/DC: For "LHS && RHS" - // - If LHS is TRUE, execution goes to the RHS. - // - If LHS is FALSE, execution goes to the LHS of the next logical-OR. - // If that does not exist, execution exits (ID == 0). createBranchRegion(E->getLHS(), RHSExecCnt, - subtractCounters(ParentCnt, RHSExecCnt), LHSid, RHSid, - NextOrID); + subtractCounters(ParentCnt, RHSExecCnt), DecisionLHS); // Create Branch Region around RHS condition. - // MC/DC: For "LHS && RHS" - // - If RHS is TRUE, execution goes to LHS of the next logical-AND. - // If that does not exist, execution exits (ID == 0). - // - If RHS is FALSE, execution goes to the LHS of the next logical-OR. - // If that does not exist, execution exits (ID == 0). createBranchRegion(E->getRHS(), RHSTrueCnt, - subtractCounters(RHSExecCnt, RHSTrueCnt), RHSid, - NextAndID, NextOrID); + subtractCounters(RHSExecCnt, RHSTrueCnt), DecisionRHS); } // Determine whether the right side of OR operation need to be visited. @@ -1884,20 +2024,28 @@ struct CounterCoverageMappingBuilder } void VisitBinLOr(const BinaryOperator *E) { - // Keep track of Binary Operator and assign MCDC condition IDs + bool IsRootNode = MCDCBuilder.isIdle(); + + // Keep track of Binary Operator and assign MCDC condition IDs. MCDCBuilder.pushAndAssignIDs(E); extendRegion(E->getLHS()); Counter OutCount = propagateCounts(getRegion().getCounter(), E->getLHS()); handleFileExit(getEnd(E->getLHS())); + // Track LHS True/False Decision. + const auto DecisionLHS = MCDCBuilder.pop(); + // Counter tracks the right hand side of a logical or operator. extendRegion(E->getRHS()); propagateCounts(getRegionCounter(E), E->getRHS()); - // Process Binary Operator and create MCDC Decision Region if top-level + // Track RHS True/False Decision. + const auto DecisionRHS = MCDCBuilder.back(); + + // Create MCDC Decision Region if at top-level (root). unsigned NumConds = 0; - if ((NumConds = MCDCBuilder.popAndReturnCondCount(E))) + if (IsRootNode && (NumConds = MCDCBuilder.getTotalConditionsAndReset(E))) createDecisionRegion(E, getRegionBitmap(E), NumConds); // Extract the RHS's Execution Counter. @@ -1913,28 +2061,13 @@ struct CounterCoverageMappingBuilder // Extract the Parent Region Counter. Counter ParentCnt = getRegion().getCounter(); - // Extract the MCDC condition IDs (returns 0 if not needed). - MCDCConditionID NextOrID = MCDCBuilder.getNextLOrCondID(); - MCDCConditionID NextAndID = MCDCBuilder.getNextLAndCondID(); - MCDCConditionID LHSid = MCDCBuilder.getCondID(E->getLHS()); - MCDCConditionID RHSid = MCDCBuilder.getCondID(E->getRHS()); - // Create Branch Region around LHS condition. - // MC/DC: For "LHS || RHS" - // - If LHS is TRUE, execution goes to the LHS of the next logical-AND. - // If that does not exist, execution exits (ID == 0). - // - If LHS is FALSE, execution goes to the RHS. createBranchRegion(E->getLHS(), subtractCounters(ParentCnt, RHSExecCnt), - RHSExecCnt, LHSid, NextAndID, RHSid); + RHSExecCnt, DecisionLHS); // Create Branch Region around RHS condition. - // MC/DC: For "LHS || RHS" - // - If RHS is TRUE, execution goes to LHS of the next logical-AND. - // If that does not exist, execution exits (ID == 0). - // - If RHS is FALSE, execution goes to the LHS of the next logical-OR. - // If that does not exist, execution exits (ID == 0). createBranchRegion(E->getRHS(), subtractCounters(RHSExecCnt, RHSFalseCnt), - RHSFalseCnt, RHSid, NextAndID, NextOrID); + RHSFalseCnt, DecisionRHS); } void VisitLambdaExpr(const LambdaExpr *LE) { diff --git a/clang/lib/CodeGen/TargetInfo.h b/clang/lib/CodeGen/TargetInfo.h index 0c0781a2d5a..7682f197041 100644 --- a/clang/lib/CodeGen/TargetInfo.h +++ b/clang/lib/CodeGen/TargetInfo.h @@ -496,7 +496,8 @@ createPPC64_SVR4_TargetCodeGenInfo(CodeGenModule &CGM, PPC64_SVR4_ABIKind Kind, bool SoftFloatABI); std::unique_ptr -createRISCVTargetCodeGenInfo(CodeGenModule &CGM, unsigned XLen, unsigned FLen); +createRISCVTargetCodeGenInfo(CodeGenModule &CGM, unsigned XLen, unsigned FLen, + bool EABI); std::unique_ptr createCommonSPIRTargetCodeGenInfo(CodeGenModule &CGM); diff --git a/clang/lib/CodeGen/Targets/RISCV.cpp b/clang/lib/CodeGen/Targets/RISCV.cpp index 1e1d249b37a..0851d1993d0 100644 --- a/clang/lib/CodeGen/Targets/RISCV.cpp +++ b/clang/lib/CodeGen/Targets/RISCV.cpp @@ -25,8 +25,9 @@ private: // ISA might have a wider FLen than the selected ABI (e.g. an RV32IF target // with soft float ABI has FLen==0). unsigned FLen; - static const int NumArgGPRs = 8; - static const int NumArgFPRs = 8; + const int NumArgGPRs; + const int NumArgFPRs; + const bool EABI; bool detectFPCCEligibleStructHelper(QualType Ty, CharUnits CurOff, llvm::Type *&Field1Ty, CharUnits &Field1Off, @@ -34,8 +35,10 @@ private: CharUnits &Field2Off) const; public: - RISCVABIInfo(CodeGen::CodeGenTypes &CGT, unsigned XLen, unsigned FLen) - : DefaultABIInfo(CGT), XLen(XLen), FLen(FLen) {} + RISCVABIInfo(CodeGen::CodeGenTypes &CGT, unsigned XLen, unsigned FLen, + bool EABI) + : DefaultABIInfo(CGT), XLen(XLen), FLen(FLen), NumArgGPRs(EABI ? 6 : 8), + NumArgFPRs(FLen != 0 ? 8 : 0), EABI(EABI) {} // DefaultABIInfo's classifyReturnType and classifyArgumentType are // non-virtual, but computeInfo is virtual, so we overload it. @@ -86,7 +89,7 @@ void RISCVABIInfo::computeInfo(CGFunctionInfo &FI) const { } int ArgGPRsLeft = IsRetIndirect ? NumArgGPRs - 1 : NumArgGPRs; - int ArgFPRsLeft = FLen ? NumArgFPRs : 0; + int ArgFPRsLeft = NumArgFPRs; int NumFixedArgs = FI.getNumRequiredArgs(); int ArgNum = 0; @@ -396,9 +399,12 @@ ABIArgInfo RISCVABIInfo::classifyArgumentType(QualType Ty, bool IsFixed, // Determine the number of GPRs needed to pass the current argument // according to the ABI. 2*XLen-aligned varargs are passed in "aligned" // register pairs, so may consume 3 registers. + // TODO: To be compatible with GCC's behaviors, we don't align registers + // currently if we are using ILP32E calling convention. This behavior may be + // changed when RV32E/ILP32E is ratified. int NeededArgGPRs = 1; if (!IsFixed && NeededAlign == 2 * XLen) - NeededArgGPRs = 2 + (ArgGPRsLeft % 2); + NeededArgGPRs = 2 + (EABI && XLen == 32 ? 0 : (ArgGPRsLeft % 2)); else if (Size > XLen && Size <= 2 * XLen) NeededArgGPRs = 2; @@ -480,6 +486,13 @@ Address RISCVABIInfo::EmitVAArg(CodeGenFunction &CGF, Address VAListAddr, auto TInfo = getContext().getTypeInfoInChars(Ty); + // TODO: To be compatible with GCC's behaviors, we force arguments with + // 2×XLEN-bit alignment and size at most 2×XLEN bits like `long long`, + // `unsigned long long` and `double` to have 4-byte alignment. This + // behavior may be changed when RV32E/ILP32E is ratified. + if (EABI && XLen == 32) + TInfo.Align = std::min(TInfo.Align, CharUnits::fromQuantity(4)); + // Arguments bigger than 2*Xlen bytes are passed indirectly. bool IsIndirect = TInfo.Width > 2 * SlotSize; @@ -499,8 +512,9 @@ namespace { class RISCVTargetCodeGenInfo : public TargetCodeGenInfo { public: RISCVTargetCodeGenInfo(CodeGen::CodeGenTypes &CGT, unsigned XLen, - unsigned FLen) - : TargetCodeGenInfo(std::make_unique(CGT, XLen, FLen)) {} + unsigned FLen, bool EABI) + : TargetCodeGenInfo( + std::make_unique(CGT, XLen, FLen, EABI)) {} void setTargetAttributes(const Decl *D, llvm::GlobalValue *GV, CodeGen::CodeGenModule &CGM) const override { @@ -526,6 +540,7 @@ public: std::unique_ptr CodeGen::createRISCVTargetCodeGenInfo(CodeGenModule &CGM, unsigned XLen, - unsigned FLen) { - return std::make_unique(CGM.getTypes(), XLen, FLen); + unsigned FLen, bool EABI) { + return std::make_unique(CGM.getTypes(), XLen, FLen, + EABI); } diff --git a/clang/lib/CodeGen/Targets/X86.cpp b/clang/lib/CodeGen/Targets/X86.cpp index d053f41ab16..2291c991fb1 100644 --- a/clang/lib/CodeGen/Targets/X86.cpp +++ b/clang/lib/CodeGen/Targets/X86.cpp @@ -40,6 +40,11 @@ static llvm::Type* X86AdjustInlineAsmType(CodeGen::CodeGenFunction &CGF, return llvm::Type::getX86_MMXTy(CGF.getLLVMContext()); } + if (Constraint == "k") { + llvm::Type *Int1Ty = llvm::Type::getInt1Ty(CGF.getLLVMContext()); + return llvm::FixedVectorType::get(Int1Ty, Ty->getScalarSizeInBits()); + } + // No operation needed return Ty; } diff --git a/clang/lib/CrossTU/CrossTranslationUnit.cpp b/clang/lib/CrossTU/CrossTranslationUnit.cpp index 94c10e50d7d..986470042bd 100644 --- a/clang/lib/CrossTU/CrossTranslationUnit.cpp +++ b/clang/lib/CrossTU/CrossTranslationUnit.cpp @@ -247,7 +247,7 @@ CrossTranslationUnitContext::getLookupName(const NamedDecl *ND) { bool Ret = index::generateUSRForDecl(ND, DeclUSR); if (Ret) return {}; - return std::string(DeclUSR.str()); + return std::string(DeclUSR); } /// Recursively visits the decls of a DeclContext, and returns one with the diff --git a/clang/lib/Driver/Driver.cpp b/clang/lib/Driver/Driver.cpp index 1889ea28079..7109faa1072 100644 --- a/clang/lib/Driver/Driver.cpp +++ b/clang/lib/Driver/Driver.cpp @@ -186,7 +186,7 @@ std::string Driver::GetResourcesPath(StringRef BinaryPath, CLANG_VERSION_MAJOR_STRING); } - return std::string(P.str()); + return std::string(P); } Driver::Driver(StringRef ClangExecutable, StringRef TargetTriple, @@ -1310,10 +1310,23 @@ Compilation *Driver::BuildCompilation(ArrayRef ArgList) { A->claim(); - // TODO: Specify Vulkan target environment somewhere in the triple. if (Args.hasArg(options::OPT_spirv)) { llvm::Triple T(TargetTriple); T.setArch(llvm::Triple::spirv); + T.setOS(llvm::Triple::Vulkan); + + // Set specific Vulkan version if applicable. + if (const Arg *A = Args.getLastArg(options::OPT_fspv_target_env_EQ)) { + const llvm::StringSet<> ValidValues = {"vulkan1.2", "vulkan1.3"}; + if (ValidValues.contains(A->getValue())) { + T.setOSName(A->getValue()); + } else { + Diag(diag::err_drv_invalid_value) + << A->getAsString(Args) << A->getValue(); + } + A->claim(); + } + TargetTriple = T.str(); } } else { @@ -1831,7 +1844,7 @@ void Driver::generateCompilationDiagnostics( ScriptOS << "\n# Additional information: " << AdditionalInformation << "\n"; if (Report) - Report->TemporaryFiles.push_back(std::string(Script.str())); + Report->TemporaryFiles.push_back(std::string(Script)); Diag(clang::diag::note_drv_command_failed_diag_msg) << Script; } @@ -4751,10 +4764,11 @@ Action *Driver::ConstructPhaseAction( case phases::Backend: { if (isUsingLTO() && TargetDeviceOffloadKind == Action::OFK_None) { types::ID Output; - if (Args.hasArg(options::OPT_S)) + if (Args.hasArg(options::OPT_ffat_lto_objects)) + Output = Args.hasArg(options::OPT_emit_llvm) ? types::TY_LTO_IR + : types::TY_PP_Asm; + else if (Args.hasArg(options::OPT_S)) Output = types::TY_LTO_IR; - else if (Args.hasArg(options::OPT_ffat_lto_objects)) - Output = types::TY_PP_Asm; else Output = types::TY_LTO_BC; return C.MakeAction(Input, Output); @@ -6073,17 +6087,17 @@ std::string Driver::GetFilePath(StringRef Name, const ToolChain &TC) const { SmallString<128> R(ResourceDir); llvm::sys::path::append(R, Name); if (llvm::sys::fs::exists(Twine(R))) - return std::string(R.str()); + return std::string(R); SmallString<128> P(TC.getCompilerRTPath()); llvm::sys::path::append(P, Name); if (llvm::sys::fs::exists(Twine(P))) - return std::string(P.str()); + return std::string(P); SmallString<128> D(Dir); llvm::sys::path::append(D, "..", Name); if (llvm::sys::fs::exists(Twine(D))) - return std::string(D.str()); + return std::string(D); if (auto P = SearchPaths(TC.getLibraryPaths())) return *P; @@ -6120,11 +6134,11 @@ std::string Driver::GetProgramPath(StringRef Name, const ToolChain &TC) const { if (llvm::sys::fs::is_directory(PrefixDir)) { SmallString<128> P(PrefixDir); if (ScanDirForExecutable(P, Name)) - return std::string(P.str()); + return std::string(P); } else { SmallString<128> P((PrefixDir + Name).str()); if (llvm::sys::fs::can_execute(Twine(P))) - return std::string(P.str()); + return std::string(P); } } @@ -6140,7 +6154,7 @@ std::string Driver::GetProgramPath(StringRef Name, const ToolChain &TC) const { for (const auto &Path : List) { SmallString<128> P(Path); if (ScanDirForExecutable(P, TargetSpecificExecutable)) - return std::string(P.str()); + return std::string(P); } // Fall back to the path @@ -6160,7 +6174,7 @@ std::string Driver::GetTemporaryPath(StringRef Prefix, StringRef Suffix) const { return ""; } - return std::string(Path.str()); + return std::string(Path); } std::string Driver::GetTemporaryDirectory(StringRef Prefix) const { @@ -6171,7 +6185,7 @@ std::string Driver::GetTemporaryDirectory(StringRef Prefix) const { return ""; } - return std::string(Path.str()); + return std::string(Path); } std::string Driver::GetClPchPath(Compilation &C, StringRef BaseName) const { @@ -6193,7 +6207,7 @@ std::string Driver::GetClPchPath(Compilation &C, StringRef BaseName) const { Output = BaseName; llvm::sys::path::replace_extension(Output, ".pch"); } - return std::string(Output.str()); + return std::string(Output); } const ToolChain &Driver::getToolChain(const ArgList &Args, @@ -6213,6 +6227,7 @@ const ToolChain &Driver::getToolChain(const ArgList &Args, case llvm::Triple::IOS: case llvm::Triple::TvOS: case llvm::Triple::WatchOS: + case llvm::Triple::XROS: case llvm::Triple::DriverKit: TC = std::make_unique(*this, Target, Args); break; diff --git a/clang/lib/Driver/SanitizerArgs.cpp b/clang/lib/Driver/SanitizerArgs.cpp index ad68c086b71..56d497eb4c3 100644 --- a/clang/lib/Driver/SanitizerArgs.cpp +++ b/clang/lib/Driver/SanitizerArgs.cpp @@ -39,8 +39,6 @@ static const SanitizerMask NotAllowedWithTrap = SanitizerKind::Vptr; static const SanitizerMask NotAllowedWithMinimalRuntime = SanitizerKind::Vptr; static const SanitizerMask NotAllowedWithExecuteOnly = SanitizerKind::Function | SanitizerKind::KCFI; -static const SanitizerMask RequiresPIE = - SanitizerKind::DataFlow | SanitizerKind::Scudo; static const SanitizerMask NeedsUnwindTables = SanitizerKind::Address | SanitizerKind::HWAddress | SanitizerKind::Thread | SanitizerKind::Memory | SanitizerKind::DataFlow; @@ -192,7 +190,7 @@ static void addDefaultIgnorelists(const Driver &D, SanitizerMask Kinds, clang::SmallString<64> Path(D.ResourceDir); llvm::sys::path::append(Path, "share", BL.File); if (D.getVFS().exists(Path)) - IgnorelistFiles.push_back(std::string(Path.str())); + IgnorelistFiles.push_back(std::string(Path)); else if (BL.Mask == SanitizerKind::CFI && DiagnoseErrors) // If cfi_ignorelist.txt cannot be found in the resource dir, driver // should fail. @@ -303,9 +301,7 @@ bool SanitizerArgs::needsCfiDiagRt() const { CfiCrossDso && !ImplicitCfiRuntime; } -bool SanitizerArgs::requiresPIE() const { - return NeedPIE || (Sanitizers.Mask & RequiresPIE); -} +bool SanitizerArgs::requiresPIE() const { return NeedPIE; } bool SanitizerArgs::needsUnwindTables() const { return static_cast(Sanitizers.Mask & NeedsUnwindTables); @@ -699,8 +695,6 @@ SanitizerArgs::SanitizerArgs(const ToolChain &TC, MsanParamRetval = Args.hasFlag( options::OPT_fsanitize_memory_param_retval, options::OPT_fno_sanitize_memory_param_retval, MsanParamRetval); - NeedPIE |= !(TC.getTriple().isOSLinux() && - TC.getTriple().getArch() == llvm::Triple::x86_64); } else if (AllAddedKinds & SanitizerKind::KernelMemory) { MsanUseAfterDtor = false; MsanParamRetval = Args.hasFlag( diff --git a/clang/lib/Driver/ToolChain.cpp b/clang/lib/Driver/ToolChain.cpp index 96a57927339..388030592b4 100644 --- a/clang/lib/Driver/ToolChain.cpp +++ b/clang/lib/Driver/ToolChain.cpp @@ -606,7 +606,7 @@ std::string ToolChain::getCompilerRTPath() const { } else { llvm::sys::path::append(Path, "lib", getOSLibName()); } - return std::string(Path.str()); + return std::string(Path); } std::string ToolChain::getCompilerRTBasename(const ArgList &Args, @@ -659,7 +659,7 @@ std::string ToolChain::getCompilerRT(const ArgList &Args, StringRef Component, SmallString<128> P(LibPath); llvm::sys::path::append(P, CRTBasename); if (getVFS().exists(P)) - return std::string(P.str()); + return std::string(P); } // Fall back to the old expected compiler-rt name if the new one does not @@ -668,7 +668,7 @@ std::string ToolChain::getCompilerRT(const ArgList &Args, StringRef Component, buildCompilerRTBasename(Args, Component, Type, /*AddArch=*/true); SmallString<128> Path(getCompilerRTPath()); llvm::sys::path::append(Path, CRTBasename); - return std::string(Path.str()); + return std::string(Path); } const char *ToolChain::getCompilerRTArgString(const llvm::opt::ArgList &Args, @@ -783,7 +783,7 @@ ToolChain::path_list ToolChain::getArchSpecificLibPaths() const { llvm::sys::path::append(Path, "lib"); for (auto &S : SS) llvm::sys::path::append(Path, S); - Paths.push_back(std::string(Path.str())); + Paths.push_back(std::string(Path)); }; AddPath({getTriple().str()}); diff --git a/clang/lib/Driver/ToolChains/AMDGPU.cpp b/clang/lib/Driver/ToolChains/AMDGPU.cpp index 56f06fc5fcc..b3c9d590865 100644 --- a/clang/lib/Driver/ToolChains/AMDGPU.cpp +++ b/clang/lib/Driver/ToolChains/AMDGPU.cpp @@ -545,26 +545,35 @@ void RocmInstallationDetector::AddHIPIncludeArgs(const ArgList &DriverArgs, } const auto HandleHipStdPar = [=, &DriverArgs, &CC1Args]() { - if (!hasHIPStdParLibrary()) { - D.Diag(diag::err_drv_no_hipstdpar_lib); - return; - } - if (!HasRocThrustLibrary && - !D.getVFS().exists(getIncludePath() + "/thrust")) { + StringRef Inc = getIncludePath(); + auto &FS = D.getVFS(); + + if (!hasHIPStdParLibrary()) + if (!HIPStdParPathArg.empty() || + !FS.exists(Inc + "/thrust/system/hip/hipstdpar/hipstdpar_lib.hpp")) { + D.Diag(diag::err_drv_no_hipstdpar_lib); + return; + } + if (!HasRocThrustLibrary && !FS.exists(Inc + "/thrust")) { D.Diag(diag::err_drv_no_hipstdpar_thrust_lib); return; } - if (!HasRocPrimLibrary && - !D.getVFS().exists(getIncludePath() + "/rocprim")) { + if (!HasRocPrimLibrary && !FS.exists(Inc + "/rocprim")) { D.Diag(diag::err_drv_no_hipstdpar_prim_lib); return; } - const char *ThrustPath; if (HasRocThrustLibrary) ThrustPath = DriverArgs.MakeArgString(HIPRocThrustPathArg); else - ThrustPath = DriverArgs.MakeArgString(getIncludePath() + "/thrust"); + ThrustPath = DriverArgs.MakeArgString(Inc + "/thrust"); + + const char *HIPStdParPath; + if (hasHIPStdParLibrary()) + HIPStdParPath = DriverArgs.MakeArgString(HIPStdParPathArg); + else + HIPStdParPath = DriverArgs.MakeArgString(StringRef(ThrustPath) + + "/system/hip/hipstdpar"); const char *PrimPath; if (HasRocPrimLibrary) @@ -573,8 +582,8 @@ void RocmInstallationDetector::AddHIPIncludeArgs(const ArgList &DriverArgs, PrimPath = DriverArgs.MakeArgString(getIncludePath() + "/rocprim"); CC1Args.append({"-idirafter", ThrustPath, "-idirafter", PrimPath, - "-idirafter", DriverArgs.MakeArgString(HIPStdParPathArg), - "-include", "hipstdpar_lib.hpp"}); + "-idirafter", HIPStdParPath, "-include", + "hipstdpar_lib.hpp"}); }; if (DriverArgs.hasArg(options::OPT_nogpuinc)) { diff --git a/clang/lib/Driver/ToolChains/AVR.cpp b/clang/lib/Driver/ToolChains/AVR.cpp index a4ce2258c3d..bb5c0e6db99 100644 --- a/clang/lib/Driver/ToolChains/AVR.cpp +++ b/clang/lib/Driver/ToolChains/AVR.cpp @@ -430,7 +430,7 @@ AVRToolChain::getCompilerRT(const llvm::opt::ArgList &Args, StringRef Component, SmallString<256> Path(ToolChain::getCompilerRTPath()); llvm::sys::path::append(Path, "avr"); llvm::sys::path::append(Path, File.str()); - return std::string(Path.str()); + return std::string(Path); } void AVR::Linker::ConstructJob(Compilation &C, const JobAction &JA, diff --git a/clang/lib/Driver/ToolChains/Arch/AArch64.cpp b/clang/lib/Driver/ToolChains/Arch/AArch64.cpp index 912df79417a..0cf96bb5c9c 100644 --- a/clang/lib/Driver/ToolChains/Arch/AArch64.cpp +++ b/clang/lib/Driver/ToolChains/Arch/AArch64.cpp @@ -53,6 +53,11 @@ std::string aarch64::getAArch64TargetCPU(const ArgList &Args, return "apple-m1"; } + if (Triple.isXROS()) { + // The xrOS simulator runs on M1 as well, it should have been covered above. + assert(!Triple.isSimulatorEnvironment() && "xrossim should be mac-like"); + return "apple-a12"; + } // arm64e requires v8.3a and only runs on apple-a12 and later CPUs. if (Triple.isArm64e()) return "apple-a12"; @@ -67,103 +72,45 @@ std::string aarch64::getAArch64TargetCPU(const ArgList &Args, // Decode AArch64 features from string like +[no]featureA+[no]featureB+... static bool DecodeAArch64Features(const Driver &D, StringRef text, - std::vector &Features, - const llvm::AArch64::ArchInfo &ArchInfo) { + llvm::AArch64::ExtensionSet &Extensions) { SmallVector Split; text.split(Split, StringRef("+"), -1, false); for (StringRef Feature : Split) { - StringRef FeatureName = llvm::AArch64::getArchExtFeature(Feature); - if (!FeatureName.empty()) - Features.push_back(FeatureName); - else if (Feature == "neon" || Feature == "noneon") + if (Feature == "neon" || Feature == "noneon") { D.Diag(clang::diag::err_drv_no_neon_modifier); - else + continue; + } + if (!Extensions.parseModifier(Feature)) return false; - - // +sme implies +bf16. - // +sme-f64f64 and +sme-i16i64 both imply +sme. - if (Feature == "sme") { - Features.push_back("+bf16"); - } else if (Feature == "nosme") { - Features.push_back("-sme-f64f64"); - Features.push_back("-sme-i16i64"); - } else if (Feature == "sme-f64f64") { - Features.push_back("+sme"); - Features.push_back("+bf16"); - } else if (Feature == "sme-i16i64") { - Features.push_back("+sme"); - Features.push_back("+bf16"); - } else if (Feature == "nobf16") { - Features.push_back("-sme"); - Features.push_back("-sme-f64f64"); - Features.push_back("-sme-i16i64"); - } - - if (Feature == "sve2") - Features.push_back("+sve"); - else if (Feature == "sve2-bitperm" || Feature == "sve2-sha3" || - Feature == "sve2-aes" || Feature == "sve2-sm4") { - Features.push_back("+sve"); - Features.push_back("+sve2"); - } else if (Feature == "nosve") { - Features.push_back("-sve2"); - Features.push_back("-sve2-bitperm"); - Features.push_back("-sve2-sha3"); - Features.push_back("-sve2-aes"); - Features.push_back("-sve2-sm4"); - } else if (Feature == "nosve2") { - Features.push_back("-sve2-bitperm"); - Features.push_back("-sve2-sha3"); - Features.push_back("-sve2-aes"); - Features.push_back("-sve2-sm4"); - } - - // +sve implies +f32mm if the base architecture is >= v8.6A (except v9A) - // It isn't the case in general that sve implies both f64mm and f32mm - if ((ArchInfo == llvm::AArch64::ARMV8_6A || - ArchInfo == llvm::AArch64::ARMV8_7A || - ArchInfo == llvm::AArch64::ARMV8_8A || - ArchInfo == llvm::AArch64::ARMV8_9A || - ArchInfo == llvm::AArch64::ARMV9_1A || - ArchInfo == llvm::AArch64::ARMV9_2A || - ArchInfo == llvm::AArch64::ARMV9_3A || - ArchInfo == llvm::AArch64::ARMV9_4A) && - Feature == "sve") - Features.push_back("+f32mm"); } + return true; } // Check if the CPU name and feature modifiers in -mcpu are legal. If yes, // decode CPU and feature. static bool DecodeAArch64Mcpu(const Driver &D, StringRef Mcpu, StringRef &CPU, - std::vector &Features) { + llvm::AArch64::ExtensionSet &Extensions) { std::pair Split = Mcpu.split("+"); CPU = Split.first; - const llvm::AArch64::ArchInfo *ArchInfo = &llvm::AArch64::ARMV8A; if (CPU == "native") CPU = llvm::sys::getHostCPUName(); if (CPU == "generic") { - Features.push_back("+neon"); + Extensions.enable(llvm::AArch64::AEK_SIMD); } else { const std::optional CpuInfo = llvm::AArch64::parseCpu(CPU); if (!CpuInfo) return false; - ArchInfo = &CpuInfo->Arch; - Features.push_back(ArchInfo->ArchFeature); - - auto Extension = CpuInfo->getImpliedExtensions(); - if (!llvm::AArch64::getExtensionFeatures(Extension, Features)) - return false; + Extensions.addCPUDefaults(*CpuInfo); } if (Split.second.size() && - !DecodeAArch64Features(D, Split.second, Features, *ArchInfo)) + !DecodeAArch64Features(D, Split.second, Extensions)) return false; return true; @@ -172,30 +119,21 @@ static bool DecodeAArch64Mcpu(const Driver &D, StringRef Mcpu, StringRef &CPU, static bool getAArch64ArchFeaturesFromMarch(const Driver &D, StringRef March, const ArgList &Args, - std::vector &Features) { + llvm::AArch64::ExtensionSet &Extensions) { std::string MarchLowerCase = March.lower(); std::pair Split = StringRef(MarchLowerCase).split("+"); - std::optional ArchInfo = + const llvm::AArch64::ArchInfo *ArchInfo = llvm::AArch64::parseArch(Split.first); if (Split.first == "native") ArchInfo = llvm::AArch64::getArchForCpu(llvm::sys::getHostCPUName().str()); if (!ArchInfo) return false; - Features.push_back(ArchInfo->ArchFeature); - // Enable SVE2 by default on Armv9-A. - // It can still be disabled if +nosve2 is present. - // We must do this early so that DecodeAArch64Features has the correct state - if ((*ArchInfo == llvm::AArch64::ARMV9A || - *ArchInfo == llvm::AArch64::ARMV9_1A || - *ArchInfo == llvm::AArch64::ARMV9_2A)) { - Features.push_back("+sve"); - Features.push_back("+sve2"); - } + Extensions.addArchDefaults(*ArchInfo); if ((Split.second.size() && - !DecodeAArch64Features(D, Split.second, Features, *ArchInfo))) + !DecodeAArch64Features(D, Split.second, Extensions))) return false; return true; @@ -204,10 +142,10 @@ getAArch64ArchFeaturesFromMarch(const Driver &D, StringRef March, static bool getAArch64ArchFeaturesFromMcpu(const Driver &D, StringRef Mcpu, const ArgList &Args, - std::vector &Features) { + llvm::AArch64::ExtensionSet &Extensions) { StringRef CPU; std::string McpuLowerCase = Mcpu.lower(); - if (!DecodeAArch64Mcpu(D, McpuLowerCase, CPU, Features)) + if (!DecodeAArch64Mcpu(D, McpuLowerCase, CPU, Extensions)) return false; return true; @@ -218,10 +156,10 @@ getAArch64MicroArchFeaturesFromMtune(const Driver &D, StringRef Mtune, const ArgList &Args, std::vector &Features) { std::string MtuneLowerCase = Mtune.lower(); - // Check CPU name is valid - std::vector MtuneFeatures; + // Check CPU name is valid, but ignore any extensions on it. + llvm::AArch64::ExtensionSet Extensions; StringRef Tune; - if (!DecodeAArch64Mcpu(D, MtuneLowerCase, Tune, MtuneFeatures)) + if (!DecodeAArch64Mcpu(D, MtuneLowerCase, Tune, Extensions)) return false; // Handle CPU name is 'native'. @@ -240,7 +178,8 @@ getAArch64MicroArchFeaturesFromMcpu(const Driver &D, StringRef Mcpu, const ArgList &Args, std::vector &Features) { StringRef CPU; - std::vector DecodedFeature; + // Check CPU name is valid, but ignore any extensions on it. + llvm::AArch64::ExtensionSet DecodedFeature; std::string McpuLowerCase = Mcpu.lower(); if (!DecodeAArch64Mcpu(D, McpuLowerCase, CPU, DecodedFeature)) return false; @@ -255,9 +194,8 @@ void aarch64::getAArch64TargetFeatures(const Driver &D, bool ForAS) { Arg *A; bool success = true; - // Enable NEON by default. - Features.push_back("+neon"); llvm::StringRef WaMArch; + llvm::AArch64::ExtensionSet Extensions; if (ForAS) for (const auto *A : Args.filtered(options::OPT_Wa_COMMA, options::OPT_Xassembler)) @@ -268,17 +206,19 @@ void aarch64::getAArch64TargetFeatures(const Driver &D, // "-Xassembler -march" is detected. Otherwise it may return false // and causes Clang to error out. if (!WaMArch.empty()) - success = getAArch64ArchFeaturesFromMarch(D, WaMArch, Args, Features); + success = getAArch64ArchFeaturesFromMarch(D, WaMArch, Args, Extensions); else if ((A = Args.getLastArg(options::OPT_march_EQ))) - success = getAArch64ArchFeaturesFromMarch(D, A->getValue(), Args, Features); + success = + getAArch64ArchFeaturesFromMarch(D, A->getValue(), Args, Extensions); else if ((A = Args.getLastArg(options::OPT_mcpu_EQ))) - success = getAArch64ArchFeaturesFromMcpu(D, A->getValue(), Args, Features); + success = + getAArch64ArchFeaturesFromMcpu(D, A->getValue(), Args, Extensions); else if (isCPUDeterminedByTriple(Triple)) success = getAArch64ArchFeaturesFromMcpu( - D, getAArch64TargetCPU(Args, Triple, A), Args, Features); + D, getAArch64TargetCPU(Args, Triple, A), Args, Extensions); else // Default to 'A' profile if the architecture is not specified. - success = getAArch64ArchFeaturesFromMarch(D, "armv8-a", Args, Features); + success = getAArch64ArchFeaturesFromMarch(D, "armv8-a", Args, Extensions); if (success && (A = Args.getLastArg(clang::driver::options::OPT_mtune_EQ))) success = @@ -300,12 +240,23 @@ void aarch64::getAArch64TargetFeatures(const Driver &D, Diag << A->getSpelling() << A->getValue(); } + // -mgeneral-regs-only disables all floating-point features. if (Args.getLastArg(options::OPT_mgeneral_regs_only)) { - Features.push_back("-fp-armv8"); - Features.push_back("-crypto"); - Features.push_back("-neon"); + Extensions.disable(llvm::AArch64::AEK_FP); } + // En/disable crc + if (Arg *A = Args.getLastArg(options::OPT_mcrc, options::OPT_mnocrc)) { + if (A->getOption().matches(options::OPT_mcrc)) + Extensions.enable(llvm::AArch64::AEK_CRC); + else + Extensions.disable(llvm::AArch64::AEK_CRC); + } + + // At this point all hardware features are decided, so convert the extensions + // set to a feature list. + Extensions.toLLVMFeatureList(Features); + if (Arg *A = Args.getLastArg(options::OPT_mtp_mode_EQ)) { StringRef Mtp = A->getValue(); if (Mtp == "el3" || Mtp == "tpidr_el3") @@ -367,147 +318,6 @@ void aarch64::getAArch64TargetFeatures(const Driver &D, } } - // En/disable crc - if (Arg *A = Args.getLastArg(options::OPT_mcrc, options::OPT_mnocrc)) { - if (A->getOption().matches(options::OPT_mcrc)) - Features.push_back("+crc"); - else - Features.push_back("-crc"); - } - - int V8Version = -1; - int V9Version = -1; - bool HasNoSM4 = false; - bool HasNoSHA3 = false; - bool HasNoSHA2 = false; - bool HasNoAES = false; - bool HasSM4 = false; - bool HasSHA3 = false; - bool HasSHA2 = false; - bool HasAES = false; - bool HasCrypto = false; - bool HasNoCrypto = false; - int FullFP16Pos = -1; - int NoFullFP16Pos = -1; - int FP16FMLPos = -1; - int NoFP16FMLPos = -1; - int ArchFeatPos = -1; - - for (auto I = Features.begin(), E = Features.end(); I != E; I++) { - if (*I == "+v8a") V8Version = 0; - else if (*I == "+v8.1a") V8Version = 1; - else if (*I == "+v8.2a") V8Version = 2; - else if (*I == "+v8.3a") V8Version = 3; - else if (*I == "+v8.4a") V8Version = 4; - else if (*I == "+v8.5a") V8Version = 5; - else if (*I == "+v8.6a") V8Version = 6; - else if (*I == "+v8.7a") V8Version = 7; - else if (*I == "+v8.8a") V8Version = 8; - else if (*I == "+v8.9a") V8Version = 9; - else if (*I == "+v9a") V9Version = 0; - else if (*I == "+v9.1a") V9Version = 1; - else if (*I == "+v9.2a") V9Version = 2; - else if (*I == "+v9.3a") V9Version = 3; - else if (*I == "+v9.4a") V9Version = 4; - else if (*I == "+v9.5a") V9Version = 5; - else if (*I == "+sm4") HasSM4 = true; - else if (*I == "+sha3") HasSHA3 = true; - else if (*I == "+sha2") HasSHA2 = true; - else if (*I == "+aes") HasAES = true; - else if (*I == "-sm4") HasNoSM4 = true; - else if (*I == "-sha3") HasNoSHA3 = true; - else if (*I == "-sha2") HasNoSHA2 = true; - else if (*I == "-aes") HasNoAES = true; - else if (*I == "+fp16fml") FP16FMLPos = I - Features.begin(); - else if (*I == "-fp16fml") NoFP16FMLPos = I - Features.begin(); - else if (*I == "-fullfp16") NoFullFP16Pos = I - Features.begin(); - else if (*I == "+fullfp16") FullFP16Pos = I - Features.begin(); - // Whichever option comes after (right-most option) will win - else if (*I == "+crypto") { - HasCrypto = true; - HasNoCrypto = false; - } else if (*I == "-crypto" || *I == "-neon") { - HasCrypto = false; - HasNoCrypto = true; - HasSM4 = HasSHA2 = HasSHA3 = HasAES = false; - } - // Register the iterator position if this is an architecture feature - if (ArchFeatPos == -1 && (V8Version != -1 || V9Version != -1)) - ArchFeatPos = I - Features.begin(); - } - - // Handle (arch-dependent) fp16fml/fullfp16 relationship. - // FIXME: this fp16fml option handling will be reimplemented after the - // TargetParser rewrite. - if (V8Version >= 4) { - // "-fullfp16" "+fullfp16" && "+fp16fml" "+fullfp16" && no "+fullfp16" "-fp16fml" = "+fp16fml" - if (FullFP16Pos > NoFullFP16Pos && FullFP16Pos > FP16FMLPos && FullFP16Pos > NoFP16FMLPos) - // Only entangled feature that can be to the right of this +fullfp16 is -fp16fml. - // Only append the +fp16fml if there is no -fp16fml after the +fullfp16. - Features.push_back("+fp16fml"); - else - goto fp16_fml_fallthrough; - } else { -fp16_fml_fallthrough: - // In both of these cases, putting the 'other' feature on the end of the vector will - // result in the same effect as placing it immediately after the current feature. - // "+fp16fml" "-fullfp16" = "-fp16fml" - if (NoFullFP16Pos > FP16FMLPos) - Features.push_back("-fp16fml"); - // "-fullfp16" "+fp16fml" = "+fullfp16" - else if (NoFullFP16Pos < FP16FMLPos) - Features.push_back("+fullfp16"); - } - - // FIXME: this needs reimplementation too after the TargetParser rewrite - // - // Context sensitive meaning of Crypto: - // 1) For Arch >= ARMv8.4a: crypto = sm4 + sha3 + sha2 + aes - // 2) For Arch <= ARMv8.3a: crypto = sha2 + aes - if (V8Version >= 4 || V9Version >= 0) { - if (HasCrypto && !HasNoCrypto) { - // Check if we have NOT disabled an algorithm with something like: - // +crypto, -algorithm - // And if "-algorithm" does not occur, we enable that crypto algorithm. - if (!HasNoSM4) - Features.push_back("+sm4"); - if (!HasNoSHA3) - Features.push_back("+sha3"); - if (!HasNoSHA2) - Features.push_back("+sha2"); - if (!HasNoAES) - Features.push_back("+aes"); - } else if (HasNoCrypto) { - // Check if we have NOT enabled a crypto algorithm with something like: - // -crypto, +algorithm - // And if "+algorithm" does not occur, we disable that crypto algorithm. - if (!HasSM4) - Features.push_back("-sm4"); - if (!HasSHA3) - Features.push_back("-sha3"); - if (!HasSHA2) - Features.push_back("-sha2"); - if (!HasAES) - Features.push_back("-aes"); - } - } else { - if (HasCrypto && !HasNoCrypto) { - if (!HasNoSHA2) - Features.push_back("+sha2"); - if (!HasNoAES) - Features.push_back("+aes"); - } else if (HasNoCrypto) { - if (!HasSHA2) - Features.push_back("-sha2"); - if (!HasAES) - Features.push_back("-aes"); - if (V8Version == 2 || V8Version == 3) { - Features.push_back("-sm4"); - Features.push_back("-sha3"); - } - } - } - if (Arg *A = Args.getLastArg(options::OPT_mno_unaligned_access, options::OPT_munaligned_access)) { if (A->getOption().matches(options::OPT_mno_unaligned_access)) diff --git a/clang/lib/Driver/ToolChains/Arch/ARM.cpp b/clang/lib/Driver/ToolChains/Arch/ARM.cpp index 25470db2b6c..e6ee2f88a84 100644 --- a/clang/lib/Driver/ToolChains/Arch/ARM.cpp +++ b/clang/lib/Driver/ToolChains/Arch/ARM.cpp @@ -367,6 +367,7 @@ arm::FloatABI arm::getDefaultFloatABI(const llvm::Triple &Triple) { case llvm::Triple::IOS: case llvm::Triple::TvOS: case llvm::Triple::DriverKit: + case llvm::Triple::XROS: // Darwin defaults to "softfp" for v6 and v7. if (Triple.isWatchABI()) return FloatABI::Hard; @@ -836,8 +837,8 @@ fp16_fml_fallthrough: if (A->getOption().matches(options::OPT_mlong_calls)) Features.push_back("+long-calls"); } else if (KernelOrKext && (!Triple.isiOS() || Triple.isOSVersionLT(6)) && - !Triple.isWatchOS()) { - Features.push_back("+long-calls"); + !Triple.isWatchOS() && !Triple.isXROS()) { + Features.push_back("+long-calls"); } // Generate execute-only output (no data access to code sections). diff --git a/clang/lib/Driver/ToolChains/Arch/RISCV.cpp b/clang/lib/Driver/ToolChains/Arch/RISCV.cpp index 16a8b3cc42b..a46b44f9ad2 100644 --- a/clang/lib/Driver/ToolChains/Arch/RISCV.cpp +++ b/clang/lib/Driver/ToolChains/Arch/RISCV.cpp @@ -210,6 +210,7 @@ StringRef riscv::getRISCVABI(const ArgList &Args, const llvm::Triple &Triple) { // rv32e -> ilp32e // rv32* -> ilp32 // rv64g | rv64*d -> lp64d + // rv64e -> lp64e // rv64* -> lp64 StringRef Arch = getRISCVArch(Args, Triple); @@ -285,6 +286,7 @@ StringRef riscv::getRISCVArch(const llvm::opt::ArgList &Args, // 3. Choose a default based on `-mabi=` // // ilp32e -> rv32e + // lp64e -> rv64e // ilp32 | ilp32f | ilp32d -> rv32imafdc // lp64 | lp64f | lp64d -> rv64imafdc if (const Arg *A = Args.getLastArg(options::OPT_mabi_EQ)) { @@ -292,6 +294,8 @@ StringRef riscv::getRISCVArch(const llvm::opt::ArgList &Args, if (MABI.equals_insensitive("ilp32e")) return "rv32e"; + else if (MABI.equals_insensitive("lp64e")) + return "rv64e"; else if (MABI.starts_with_insensitive("ilp32")) return "rv32imafdc"; else if (MABI.starts_with_insensitive("lp64")) { diff --git a/clang/lib/Driver/ToolChains/CSKYToolChain.cpp b/clang/lib/Driver/ToolChains/CSKYToolChain.cpp index 0c280347b2a..feb3bc92292 100644 --- a/clang/lib/Driver/ToolChains/CSKYToolChain.cpp +++ b/clang/lib/Driver/ToolChains/CSKYToolChain.cpp @@ -125,7 +125,7 @@ std::string CSKYToolChain::computeSysRoot() const { if (!llvm::sys::fs::exists(SysRootDir)) return std::string(); - return std::string(SysRootDir.str()); + return std::string(SysRootDir); } void CSKY::Linker::ConstructJob(Compilation &C, const JobAction &JA, diff --git a/clang/lib/Driver/ToolChains/Clang.cpp b/clang/lib/Driver/ToolChains/Clang.cpp index 1ee7ae602f3..5dc614e11aa 100644 --- a/clang/lib/Driver/ToolChains/Clang.cpp +++ b/clang/lib/Driver/ToolChains/Clang.cpp @@ -43,7 +43,9 @@ #include "clang/Driver/XRayArgs.h" #include "llvm/ADT/SmallSet.h" #include "llvm/ADT/StringExtras.h" +#include "llvm/BinaryFormat/Magic.h" #include "llvm/Config/llvm-config.h" +#include "llvm/Object/ObjectFile.h" #include "llvm/Option/ArgList.h" #include "llvm/Support/CodeGen.h" #include "llvm/Support/Compiler.h" @@ -948,11 +950,21 @@ static void handleAMDGPUCodeObjectVersionOptions(const Driver &D, } } -static bool hasClangPchSignature(const Driver &D, StringRef Path) { - if (llvm::ErrorOr> MemBuf = - D.getVFS().getBufferForFile(Path)) - return (*MemBuf)->getBuffer().starts_with("CPCH"); - return false; +static bool maybeHasClangPchSignature(const Driver &D, StringRef Path) { + llvm::ErrorOr> MemBuf = + D.getVFS().getBufferForFile(Path); + if (!MemBuf) + return false; + llvm::file_magic Magic = llvm::identify_magic((*MemBuf)->getBuffer()); + if (Magic == llvm::file_magic::unknown) + return false; + // Return true for both raw Clang AST files and object files which may + // contain a __clangast section. + if (Magic == llvm::file_magic::clang_ast) + return true; + Expected> Obj = + llvm::object::ObjectFile::createObjectFile(**MemBuf, Magic); + return !Obj.takeError(); } static bool gchProbe(const Driver &D, StringRef Path) { @@ -964,14 +976,14 @@ static bool gchProbe(const Driver &D, StringRef Path) { std::error_code EC; for (llvm::vfs::directory_iterator DI = D.getVFS().dir_begin(Path, EC), DE; !EC && DI != DE; DI = DI.increment(EC)) { - if (hasClangPchSignature(D, DI->path())) + if (maybeHasClangPchSignature(D, DI->path())) return true; } D.Diag(diag::warn_drv_pch_ignoring_gch_dir) << Path; return false; } - if (hasClangPchSignature(D, Path)) + if (maybeHasClangPchSignature(D, Path)) return true; D.Diag(diag::warn_drv_pch_ignoring_gch_file) << Path; return false; @@ -2700,9 +2712,22 @@ static void EmitComplexRangeDiag(const Driver &D, << EnumComplexRangeToStr(Range1) << EnumComplexRangeToStr(Range2); } -static std::string RenderComplexRangeOption(std::string Range) { +static std::string +RenderComplexRangeOption(LangOptions::ComplexRangeKind Range) { std::string ComplexRangeStr = "-complex-range="; - ComplexRangeStr += Range; + switch (Range) { + case LangOptions::ComplexRangeKind::CX_Full: + ComplexRangeStr += "full"; + break; + case LangOptions::ComplexRangeKind::CX_Limited: + ComplexRangeStr += "limited"; + break; + case LangOptions::ComplexRangeKind::CX_Fortran: + ComplexRangeStr += "fortran"; + break; + default: + assert(0 && "Unexpected range option"); + } return ComplexRangeStr; } @@ -2752,7 +2777,8 @@ static void RenderFloatingPointOptions(const ToolChain &TC, const Driver &D, bool StrictFPModel = false; StringRef Float16ExcessPrecision = ""; StringRef BFloat16ExcessPrecision = ""; - LangOptions::ComplexRangeKind Range = LangOptions::ComplexRangeKind::CX_Full; + LangOptions::ComplexRangeKind Range = LangOptions::ComplexRangeKind::CX_None; + std::string ComplexRangeStr = ""; if (const Arg *A = Args.getLastArg(options::OPT_flimited_precision_EQ)) { CmdArgs.push_back("-mlimit-float-precision"); @@ -2768,23 +2794,19 @@ static void RenderFloatingPointOptions(const ToolChain &TC, const Driver &D, case options::OPT_fcx_limited_range: { EmitComplexRangeDiag(D, Range, LangOptions::ComplexRangeKind::CX_Limited); Range = LangOptions::ComplexRangeKind::CX_Limited; - std::string ComplexRangeStr = RenderComplexRangeOption("limited"); - if (!ComplexRangeStr.empty()) - CmdArgs.push_back(Args.MakeArgString(ComplexRangeStr)); break; } case options::OPT_fno_cx_limited_range: + EmitComplexRangeDiag(D, Range, LangOptions::ComplexRangeKind::CX_Full); Range = LangOptions::ComplexRangeKind::CX_Full; break; case options::OPT_fcx_fortran_rules: { EmitComplexRangeDiag(D, Range, LangOptions::ComplexRangeKind::CX_Fortran); Range = LangOptions::ComplexRangeKind::CX_Fortran; - std::string ComplexRangeStr = RenderComplexRangeOption("fortran"); - if (!ComplexRangeStr.empty()) - CmdArgs.push_back(Args.MakeArgString(ComplexRangeStr)); break; } case options::OPT_fno_cx_fortran_rules: + EmitComplexRangeDiag(D, Range, LangOptions::ComplexRangeKind::CX_Full); Range = LangOptions::ComplexRangeKind::CX_Full; break; case options::OPT_ffp_model_EQ: { @@ -3056,9 +3078,7 @@ static void RenderFloatingPointOptions(const ToolChain &TC, const Driver &D, SeenUnsafeMathModeOption = true; // ffast-math enables fortran rules for complex multiplication and // division. - std::string ComplexRangeStr = RenderComplexRangeOption("limited"); - if (!ComplexRangeStr.empty()) - CmdArgs.push_back(Args.MakeArgString(ComplexRangeStr)); + Range = LangOptions::ComplexRangeKind::CX_Limited; break; } case options::OPT_fno_fast_math: @@ -3215,6 +3235,10 @@ static void RenderFloatingPointOptions(const ToolChain &TC, const Driver &D, options::OPT_fstrict_float_cast_overflow, false)) CmdArgs.push_back("-fno-strict-float-cast-overflow"); + if (Range != LangOptions::ComplexRangeKind::CX_None) + ComplexRangeStr = RenderComplexRangeOption(Range); + if (!ComplexRangeStr.empty()) + CmdArgs.push_back(Args.MakeArgString(ComplexRangeStr)); if (Args.hasArg(options::OPT_fcx_limited_range)) CmdArgs.push_back("-fcx-limited-range"); if (Args.hasArg(options::OPT_fcx_fortran_rules)) @@ -3523,6 +3547,20 @@ static void RenderTrivialAutoVarInitOptions(const Driver &D, CmdArgs.push_back( Args.MakeArgString("-ftrivial-auto-var-init-stop-after=" + Val)); } + + if (Arg *A = Args.getLastArg(options::OPT_ftrivial_auto_var_init_max_size)) { + if (!Args.hasArg(options::OPT_ftrivial_auto_var_init) || + StringRef( + Args.getLastArg(options::OPT_ftrivial_auto_var_init)->getValue()) == + "uninitialized") + D.Diag(diag::err_drv_trivial_auto_var_init_max_size_missing_dependency); + A->claim(); + StringRef Val = A->getValue(); + if (std::stoi(Val.str()) <= 0) + D.Diag(diag::err_drv_trivial_auto_var_init_max_size_invalid_value); + CmdArgs.push_back( + Args.MakeArgString("-ftrivial-auto-var-init-max-size=" + Val)); + } } static void RenderOpenCLOptions(const ArgList &Args, ArgStringList &CmdArgs, @@ -4816,9 +4854,7 @@ void Clang::ConstructJob(Compilation &C, const JobAction &JA, bool UnifiedLTO = false; if (IsUsingLTO) { UnifiedLTO = Args.hasFlag(options::OPT_funified_lto, - options::OPT_fno_unified_lto, Triple.isPS()) || - Args.hasFlag(options::OPT_ffat_lto_objects, - options::OPT_fno_fat_lto_objects, false); + options::OPT_fno_unified_lto, Triple.isPS()); if (UnifiedLTO) CmdArgs.push_back("-funified-lto"); } @@ -5752,20 +5788,24 @@ void Clang::ConstructJob(Compilation &C, const JobAction &JA, } } - if (Arg *A = Args.getLastArg(options::OPT_mlarge_data_threshold_EQ)) { - if (!Triple.isX86()) { - D.Diag(diag::err_drv_unsupported_opt_for_target) - << A->getOption().getName() << TripleStr; - } else { - bool IsMediumCM = false; - if (Arg *A = Args.getLastArg(options::OPT_mcmodel_EQ)) - IsMediumCM = StringRef(A->getValue()) == "medium"; - if (!IsMediumCM) { + if (Triple.getArch() == llvm::Triple::x86_64) { + bool IsMediumCM = false; + bool IsLargeCM = false; + if (Arg *A = Args.getLastArg(options::OPT_mcmodel_EQ)) { + IsMediumCM = StringRef(A->getValue()) == "medium"; + IsLargeCM = StringRef(A->getValue()) == "large"; + } + if (Arg *A = Args.getLastArg(options::OPT_mlarge_data_threshold_EQ)) { + if (!IsMediumCM && !IsLargeCM) { D.Diag(diag::warn_drv_large_data_threshold_invalid_code_model) << A->getOption().getRenderName(); } else { A->render(Args, CmdArgs); } + } else if (IsMediumCM) { + CmdArgs.push_back("-mlarge-data-threshold=65536"); + } else if (IsLargeCM) { + CmdArgs.push_back("-mlarge-data-threshold=0"); } } @@ -6295,7 +6335,28 @@ void Clang::ConstructJob(Compilation &C, const JobAction &JA, Args.AddLastArg(CmdArgs, options::OPT_fvisibility_inlines_hidden_static_local_var, options::OPT_fno_visibility_inlines_hidden_static_local_var); - Args.AddLastArg(CmdArgs, options::OPT_fvisibility_global_new_delete_hidden); + + // -fvisibility-global-new-delete-hidden is a deprecated spelling of + // -fvisibility-global-new-delete=force-hidden. + if (const Arg *A = + Args.getLastArg(options::OPT_fvisibility_global_new_delete_hidden)) { + D.Diag(diag::warn_drv_deprecated_arg) + << A->getAsString(Args) + << "-fvisibility-global-new-delete=force-hidden"; + } + + if (const Arg *A = + Args.getLastArg(options::OPT_fvisibility_global_new_delete_EQ, + options::OPT_fvisibility_global_new_delete_hidden)) { + if (A->getOption().matches(options::OPT_fvisibility_global_new_delete_EQ)) { + A->render(Args, CmdArgs); + } else { + assert(A->getOption().matches( + options::OPT_fvisibility_global_new_delete_hidden)); + CmdArgs.push_back("-fvisibility-global-new-delete=force-hidden"); + } + } + Args.AddLastArg(CmdArgs, options::OPT_ftlsmodel_EQ); if (Args.hasFlag(options::OPT_fnew_infallible, @@ -6397,6 +6458,8 @@ void Clang::ConstructJob(Compilation &C, const JobAction &JA, CmdArgs.push_back("-fopenmp-assume-no-nested-parallelism"); if (Args.hasArg(options::OPT_fopenmp_offload_mandatory)) CmdArgs.push_back("-fopenmp-offload-mandatory"); + if (Args.hasArg(options::OPT_fopenmp_force_usm)) + CmdArgs.push_back("-fopenmp-force-usm"); break; default: // By default, if Clang doesn't know how to generate useful OpenMP code @@ -8684,7 +8747,7 @@ void OffloadPackager::ConstructJob(Compilation &C, const JobAction &JA, SmallVector Parts{ "file=" + File.str(), "triple=" + TC->getTripleString(), - "arch=" + getProcessorFromTargetID(TC->getTriple(), Arch).str(), + "arch=" + Arch.str(), "kind=" + Kind.str(), }; diff --git a/clang/lib/Driver/ToolChains/CommonArgs.cpp b/clang/lib/Driver/ToolChains/CommonArgs.cpp index 2340191ca97..fadaf3e60c6 100644 --- a/clang/lib/Driver/ToolChains/CommonArgs.cpp +++ b/clang/lib/Driver/ToolChains/CommonArgs.cpp @@ -736,6 +736,8 @@ void tools::addLTOOptions(const ToolChain &ToolChain, const ArgList &Args, const bool IsAMDGCN = ToolChain.getTriple().isAMDGCN(); const char *Linker = Args.MakeArgString(ToolChain.GetLinkerPath()); const Driver &D = ToolChain.getDriver(); + const bool IsFatLTO = Args.hasArg(options::OPT_ffat_lto_objects); + const bool IsUnifiedLTO = Args.hasArg(options::OPT_funified_lto); if (llvm::sys::path::filename(Linker) != "ld.lld" && llvm::sys::path::stem(Linker) != "ld.lld" && !ToolChain.getTriple().isOSOpenBSD()) { @@ -765,7 +767,7 @@ void tools::addLTOOptions(const ToolChain &ToolChain, const ArgList &Args, } else { // Tell LLD to find and use .llvm.lto section in regular relocatable object // files - if (Args.hasArg(options::OPT_ffat_lto_objects)) + if (IsFatLTO) CmdArgs.push_back("--fat-lto-objects"); } @@ -825,7 +827,8 @@ void tools::addLTOOptions(const ToolChain &ToolChain, const ArgList &Args, // Matrix intrinsic lowering happens at link time with ThinLTO. Enable // LowerMatrixIntrinsicsPass, which is transitively called by // buildThinLTODefaultPipeline under EnableMatrix. - if (IsThinLTO && Args.hasArg(options::OPT_fenable_matrix)) + if ((IsThinLTO || IsFatLTO || IsUnifiedLTO) && + Args.hasArg(options::OPT_fenable_matrix)) CmdArgs.push_back( Args.MakeArgString(Twine(PluginOptPrefix) + "-enable-matrix")); @@ -1191,6 +1194,18 @@ static void addFortranMain(const ToolChain &TC, const ArgList &Args, } // 2. GNU and similar + const Driver &D = TC.getDriver(); + const char *FortranMainLinkFlag = "-lFortran_main"; + + // Warn if the user added `-lFortran_main` - this library is an implementation + // detail of Flang and should be handled automaticaly by the driver. + for (const char *arg : CmdArgs) { + if (strncmp(arg, FortranMainLinkFlag, strlen(FortranMainLinkFlag)) == 0) + D.Diag(diag::warn_drv_deprecated_custom) + << FortranMainLinkFlag + << "see the Flang driver documentation for correct usage"; + } + // The --whole-archive option needs to be part of the link line to make // sure that the main() function from Fortran_main.a is pulled in by the // linker. However, it shouldn't be used if it's already active. @@ -1198,12 +1213,12 @@ static void addFortranMain(const ToolChain &TC, const ArgList &Args, if (!isWholeArchivePresent(Args) && !TC.getTriple().isMacOSX() && !TC.getTriple().isOSAIX()) { CmdArgs.push_back("--whole-archive"); - CmdArgs.push_back("-lFortran_main"); + CmdArgs.push_back(FortranMainLinkFlag); CmdArgs.push_back("--no-whole-archive"); return; } - CmdArgs.push_back("-lFortran_main"); + CmdArgs.push_back(FortranMainLinkFlag); } /// Add Fortran runtime libs diff --git a/clang/lib/Driver/ToolChains/Cuda.cpp b/clang/lib/Driver/ToolChains/Cuda.cpp index f7a208575cb..1462576ca87 100644 --- a/clang/lib/Driver/ToolChains/Cuda.cpp +++ b/clang/lib/Driver/ToolChains/Cuda.cpp @@ -894,7 +894,7 @@ std::string CudaToolChain::getInputFilename(const InputInfo &Input) const { // these particular file names. SmallString<256> Filename(ToolChain::getInputFilename(Input)); llvm::sys::path::replace_extension(Filename, "cubin"); - return std::string(Filename.str()); + return std::string(Filename); } llvm::opt::DerivedArgList * diff --git a/clang/lib/Driver/ToolChains/Darwin.cpp b/clang/lib/Driver/ToolChains/Darwin.cpp index 65846cace46..fae8ad1a958 100644 --- a/clang/lib/Driver/ToolChains/Darwin.cpp +++ b/clang/lib/Driver/ToolChains/Darwin.cpp @@ -219,7 +219,8 @@ static bool shouldLinkerNotDedup(bool IsLinkerOnlyAction, const ArgList &Args) { void darwin::Linker::AddLinkArgs(Compilation &C, const ArgList &Args, ArgStringList &CmdArgs, const InputInfoList &Inputs, - VersionTuple Version, bool LinkerIsLLD) const { + VersionTuple Version, bool LinkerIsLLD, + bool UsePlatformVersion) const { const Driver &D = getToolChain().getDriver(); const toolchains::MachO &MachOTC = getMachOToolChain(); @@ -355,7 +356,7 @@ void darwin::Linker::AddLinkArgs(Compilation &C, const ArgList &Args, Args.AddAllArgs(CmdArgs, options::OPT_init); // Add the deployment target. - if (Version >= VersionTuple(520) || LinkerIsLLD) + if (Version >= VersionTuple(520) || LinkerIsLLD || UsePlatformVersion) MachOTC.addPlatformVersionArgs(Args, CmdArgs); else MachOTC.addMinVersionArgs(Args, CmdArgs); @@ -596,9 +597,13 @@ void darwin::Linker::ConstructJob(Compilation &C, const JobAction &JA, const char *Exec = Args.MakeArgString(getToolChain().GetLinkerPath(&LinkerIsLLD)); + // xrOS always uses -platform-version. + bool UsePlatformVersion = getToolChain().getTriple().isXROS(); + // I'm not sure why this particular decomposition exists in gcc, but // we follow suite for ease of comparison. - AddLinkArgs(C, Args, CmdArgs, Inputs, Version, LinkerIsLLD); + AddLinkArgs(C, Args, CmdArgs, Inputs, Version, LinkerIsLLD, + UsePlatformVersion); if (willEmitRemarks(Args) && checkRemarksOptions(getToolChain().getDriver(), Args, @@ -954,6 +959,13 @@ ObjCRuntime Darwin::getDefaultObjCRuntime(bool isNonFragile) const { return ObjCRuntime(ObjCRuntime::WatchOS, TargetVersion); if (isTargetIOSBased()) return ObjCRuntime(ObjCRuntime::iOS, TargetVersion); + if (isTargetXROS()) { + // XROS uses the iOS runtime. + auto T = llvm::Triple(Twine("arm64-apple-") + + llvm::Triple::getOSTypeName(llvm::Triple::XROS) + + TargetVersion.getAsString()); + return ObjCRuntime(ObjCRuntime::iOS, T.getiOSVersion()); + } if (isNonFragile) return ObjCRuntime(ObjCRuntime::MacOSX, TargetVersion); return ObjCRuntime(ObjCRuntime::FragileMacOSX, TargetVersion); @@ -961,7 +973,7 @@ ObjCRuntime Darwin::getDefaultObjCRuntime(bool isNonFragile) const { /// Darwin provides a blocks runtime starting in MacOS X 10.6 and iOS 3.2. bool Darwin::hasBlocksRuntime() const { - if (isTargetWatchOSBased() || isTargetDriverKit()) + if (isTargetWatchOSBased() || isTargetDriverKit() || isTargetXROS()) return true; else if (isTargetIOSBased()) return !isIPhoneOSVersionLT(3, 2); @@ -973,12 +985,12 @@ bool Darwin::hasBlocksRuntime() const { void Darwin::AddCudaIncludeArgs(const ArgList &DriverArgs, ArgStringList &CC1Args) const { - CudaInstallation.AddCudaIncludeArgs(DriverArgs, CC1Args); + CudaInstallation->AddCudaIncludeArgs(DriverArgs, CC1Args); } void Darwin::AddHIPIncludeArgs(const ArgList &DriverArgs, ArgStringList &CC1Args) const { - RocmInstallation.AddHIPIncludeArgs(DriverArgs, CC1Args); + RocmInstallation->AddHIPIncludeArgs(DriverArgs, CC1Args); } // This is just a MachO name translation routine and there's no @@ -1092,6 +1104,8 @@ std::string Darwin::ComputeEffectiveClangTriple(const ArgList &Args, Str += "driverkit"; else if (isTargetIOSBased() || isTargetMacCatalyst()) Str += "ios"; + else if (isTargetXROS()) + Str += llvm::Triple::getOSTypeName(llvm::Triple::XROS); else Str += "macosx"; Str += getTripleTargetVersion().getAsString(); @@ -1174,6 +1188,8 @@ void DarwinClang::AddLinkARCArgs(const ArgList &Args, // ARC runtime is supported everywhere on arm64e. if (getTriple().isArm64e()) return; + if (isTargetXROS()) + return; ObjCRuntime runtime = getDefaultObjCRuntime(/*nonfragile*/ true); @@ -1309,6 +1325,8 @@ StringRef Darwin::getPlatformFamily() const { return "Watch"; case DarwinPlatformKind::DriverKit: return "DriverKit"; + case DarwinPlatformKind::XROS: + return "XR"; } llvm_unreachable("Unsupported platform"); } @@ -1340,6 +1358,9 @@ StringRef Darwin::getOSLibraryNameSuffix(bool IgnoreSim) const { case DarwinPlatformKind::WatchOS: return TargetEnvironment == NativeEnvironment || IgnoreSim ? "watchos" : "watchossim"; + case DarwinPlatformKind::XROS: + return TargetEnvironment == NativeEnvironment || IgnoreSim ? "xros" + : "xrossim"; case DarwinPlatformKind::DriverKit: return "driverkit"; } @@ -1649,6 +1670,9 @@ struct DarwinPlatform { case DarwinPlatformKind::WatchOS: Opt = options::OPT_mwatchos_version_min_EQ; break; + case DarwinPlatformKind::XROS: + // xrOS always explicitly provides a version in the triple. + return; case DarwinPlatformKind::DriverKit: // DriverKit always explicitly provides a version in the triple. return; @@ -1794,6 +1818,8 @@ private: return DarwinPlatformKind::TvOS; case llvm::Triple::WatchOS: return DarwinPlatformKind::WatchOS; + case llvm::Triple::XROS: + return DarwinPlatformKind::XROS; case llvm::Triple::DriverKit: return DarwinPlatformKind::DriverKit; default: @@ -1975,6 +2001,10 @@ inferDeploymentTargetFromSDK(DerivedArgList &Args, return DarwinPlatform::createFromSDK( Darwin::TvOS, Version, /*IsSimulator=*/SDK.starts_with("AppleTVSimulator")); + else if (SDK.starts_with("XR")) + return DarwinPlatform::createFromSDK( + Darwin::XROS, Version, + /*IsSimulator=*/SDK.contains("Simulator")); else if (SDK.starts_with("DriverKit")) return DarwinPlatform::createFromSDK(Darwin::DriverKit, Version); return std::nullopt; @@ -2013,6 +2043,11 @@ std::string getOSVersion(llvm::Triple::OSType OS, const llvm::Triple &Triple, case llvm::Triple::WatchOS: OsVersion = Triple.getWatchOSVersion(); break; + case llvm::Triple::XROS: + OsVersion = Triple.getOSVersion(); + if (!OsVersion.getMajor()) + OsVersion = OsVersion.withMajorReplaced(1); + break; case llvm::Triple::DriverKit: OsVersion = Triple.getDriverKitVersion(); break; @@ -2104,6 +2139,7 @@ std::optional getDeploymentTargetFromMTargetOSArg( case llvm::Triple::IOS: case llvm::Triple::TvOS: case llvm::Triple::WatchOS: + case llvm::Triple::XROS: break; default: TheDriver.Diag(diag::err_drv_invalid_os_in_arg) @@ -2319,6 +2355,13 @@ void Darwin::AddDeploymentTarget(DerivedArgList &Args) const { Micro >= 100) getDriver().Diag(diag::err_drv_invalid_version_number) << OSTarget->getAsString(Args, Opts); + } else if (Platform == XROS) { + if (!Driver::GetReleaseVersion(OSTarget->getOSVersion(), Major, Minor, + Micro, HadExtra) || + HadExtra || Major < 1 || Major >= MajorVersionLimit || Minor >= 100 || + Micro >= 100) + getDriver().Diag(diag::err_drv_invalid_version_number) + << OSTarget->getAsString(Args, Opts); } else llvm_unreachable("unknown kind of Darwin platform"); @@ -2641,6 +2684,10 @@ void DarwinClang::AddCCKextLibArgs(const ArgList &Args, llvm::sys::path::append(P, "libclang_rt.cc_kext_ios.a"); } else if (isTargetDriverKit()) { // DriverKit doesn't want extra runtime support. + } else if (isTargetXROSDevice()) { + llvm::sys::path::append( + P, llvm::Twine("libclang_rt.cc_kext_") + + llvm::Triple::getOSTypeName(llvm::Triple::XROS) + ".a"); } else { llvm::sys::path::append(P, "libclang_rt.cc_kext.a"); } @@ -2855,6 +2902,8 @@ bool Darwin::isAlignedAllocationUnavailable() const { case WatchOS: // Earlier than 4.0. OS = llvm::Triple::WatchOS; break; + case XROS: // Always available. + return false; case DriverKit: // Always available. return false; } @@ -2876,6 +2925,8 @@ static bool sdkSupportsBuiltinModules(const Darwin::DarwinPlatformKind &TargetPl return SDKVersion >= VersionTuple(99U); case Darwin::WatchOS: return SDKVersion >= VersionTuple(99U); + case Darwin::XROS: + return SDKVersion >= VersionTuple(99U); default: return true; } @@ -2917,6 +2968,10 @@ void Darwin::addClangTargetOptions(const llvm::opt::ArgList &DriverArgs, // to fix the same problem with C++ headers, and is generally fragile. if (!sdkSupportsBuiltinModules(TargetPlatform, SDKInfo)) CC1Args.push_back("-fbuiltin-headers-in-system-modules"); + + if (!DriverArgs.hasArgNoClaim(options::OPT_fdefine_target_os_macros, + options::OPT_fno_define_target_os_macros)) + CC1Args.push_back("-fdefine-target-os-macros"); } void Darwin::addClangCC1ASTargetOptions( @@ -2994,7 +3049,7 @@ Darwin::TranslateArgs(const DerivedArgList &Args, StringRef BoundArch, // FIXME: It would be far better to avoid inserting those -static arguments, // but we can't check the deployment target in the translation code until // it is set here. - if (isTargetWatchOSBased() || isTargetDriverKit() || + if (isTargetWatchOSBased() || isTargetDriverKit() || isTargetXROS() || (isTargetIOSBased() && !isIPhoneOSVersionLT(6, 0))) { for (ArgList::iterator it = DAL->begin(), ie = DAL->end(); it != ie; ) { Arg *A = *it; @@ -3088,6 +3143,8 @@ void Darwin::addMinVersionArgs(const ArgList &Args, ArgStringList &CmdArgs) const { VersionTuple TargetVersion = getTripleTargetVersion(); + assert(!isTargetXROS() && "xrOS always uses -platform-version"); + if (isTargetWatchOS()) CmdArgs.push_back("-watchos_version_min"); else if (isTargetWatchOSSimulator()) @@ -3147,6 +3204,8 @@ static const char *getPlatformName(Darwin::DarwinPlatformKind Platform, return "tvos"; case Darwin::WatchOS: return "watchos"; + case Darwin::XROS: + return "xros"; case Darwin::DriverKit: return "driverkit"; } @@ -3343,7 +3402,7 @@ void Darwin::addStartObjectFileArgs(const ArgList &Args, } void Darwin::CheckObjCARC() const { - if (isTargetIOSBased() || isTargetWatchOSBased() || + if (isTargetIOSBased() || isTargetWatchOSBased() || isTargetXROS() || (isTargetMacOSBased() && !isMacosxVersionLT(10, 6))) return; getDriver().Diag(diag::err_arc_unsupported_on_toolchain); @@ -3377,6 +3436,6 @@ SanitizerMask Darwin::getSupportedSanitizers() const { } void Darwin::printVerboseInfo(raw_ostream &OS) const { - CudaInstallation.print(OS); - RocmInstallation.print(OS); + CudaInstallation->print(OS); + RocmInstallation->print(OS); } diff --git a/clang/lib/Driver/ToolChains/Darwin.h b/clang/lib/Driver/ToolChains/Darwin.h index 815449ae8f3..5e60b0841d6 100644 --- a/clang/lib/Driver/ToolChains/Darwin.h +++ b/clang/lib/Driver/ToolChains/Darwin.h @@ -10,6 +10,7 @@ #define LLVM_CLANG_LIB_DRIVER_TOOLCHAINS_DARWIN_H #include "Cuda.h" +#include "LazyDetector.h" #include "ROCm.h" #include "clang/Basic/DarwinSDKInfo.h" #include "clang/Basic/LangOptions.h" @@ -65,7 +66,7 @@ class LLVM_LIBRARY_VISIBILITY Linker : public MachOTool { void AddLinkArgs(Compilation &C, const llvm::opt::ArgList &Args, llvm::opt::ArgStringList &CmdArgs, const InputInfoList &Inputs, VersionTuple Version, - bool LinkerIsLLD) const; + bool LinkerIsLLD, bool UsePlatformVersion) const; public: Linker(const ToolChain &TC) : MachOTool("darwin::Linker", "linker", TC) {} @@ -298,6 +299,7 @@ public: TvOS, WatchOS, DriverKit, + XROS, LastDarwinPlatform = DriverKit }; enum DarwinEnvironmentKind { @@ -320,8 +322,8 @@ public: /// The target variant triple that was specified (if any). mutable std::optional TargetVariantTriple; - CudaInstallationDetector CudaInstallation; - RocmInstallationDetector RocmInstallation; + LazyDetector CudaInstallation; + LazyDetector RocmInstallation; private: void AddDeploymentTarget(llvm::opt::DerivedArgList &Args) const; @@ -404,6 +406,16 @@ public: return isTargetIPhoneOS() || isTargetIOSSimulator(); } + bool isTargetXROSDevice() const { + return TargetPlatform == XROS && TargetEnvironment == NativeEnvironment; + } + + bool isTargetXROSSimulator() const { + return TargetPlatform == XROS && TargetEnvironment == Simulator; + } + + bool isTargetXROS() const { return TargetPlatform == XROS; } + bool isTargetTvOS() const { assert(TargetInitialized && "Target not initialized!"); return TargetPlatform == TvOS && TargetEnvironment == NativeEnvironment; @@ -546,7 +558,8 @@ public: GetDefaultStackProtectorLevel(bool KernelOrKext) const override { // Stack protectors default to on for user code on 10.5, // and for everything in 10.6 and beyond - if (isTargetIOSBased() || isTargetWatchOSBased() || isTargetDriverKit()) + if (isTargetIOSBased() || isTargetWatchOSBased() || isTargetDriverKit() || + isTargetXROS()) return LangOptions::SSPOn; else if (isTargetMacOSBased() && !isMacosxVersionLT(10, 6)) return LangOptions::SSPOn; diff --git a/clang/lib/Driver/ToolChains/Fuchsia.cpp b/clang/lib/Driver/ToolChains/Fuchsia.cpp index 6525cf8356d..14b838500be 100644 --- a/clang/lib/Driver/ToolChains/Fuchsia.cpp +++ b/clang/lib/Driver/ToolChains/Fuchsia.cpp @@ -258,7 +258,7 @@ Fuchsia::Fuchsia(const Driver &D, const llvm::Triple &Triple, if (!D.SysRoot.empty()) { SmallString<128> P(D.SysRoot); llvm::sys::path::append(P, "lib"); - getFilePaths().push_back(std::string(P.str())); + getFilePaths().push_back(std::string(P)); } auto FilePaths = [&](const Multilib &M) -> std::vector { @@ -266,7 +266,7 @@ Fuchsia::Fuchsia(const Driver &D, const llvm::Triple &Triple, if (std::optional Path = getStdlibPath()) { SmallString<128> P(*Path); llvm::sys::path::append(P, M.gccSuffix()); - FP.push_back(std::string(P.str())); + FP.push_back(std::string(P)); } return FP; }; diff --git a/clang/lib/Driver/ToolChains/Gnu.cpp b/clang/lib/Driver/ToolChains/Gnu.cpp index 771240dac7a..e5e1b1d7726 100644 --- a/clang/lib/Driver/ToolChains/Gnu.cpp +++ b/clang/lib/Driver/ToolChains/Gnu.cpp @@ -508,6 +508,11 @@ void tools::gnutools::Linker::ConstructJob(Compilation &C, const JobAction &JA, // Add crtfastmath.o if available and fast math is enabled. ToolChain.addFastMathRuntimeIfAvailable(Args, CmdArgs); + + if (isAndroid && Args.hasFlag(options::OPT_fandroid_pad_segment, + options::OPT_fno_android_pad_segment, false)) + CmdArgs.push_back( + Args.MakeArgString(ToolChain.GetFilePath("crt_pad_segment.o"))); } Args.addAllArgs(CmdArgs, {options::OPT_L, options::OPT_u}); @@ -2485,7 +2490,7 @@ void Generic_GCC::GCCInstallationDetector::AddDefaultGCCPrefixes( static const char *const X86Triples[] = { "i586-linux-gnu", "i686-linux-gnu", "i686-pc-linux-gnu", "i386-redhat-linux6E", "i686-redhat-linux", "i386-redhat-linux", - "i586-suse-linux", "i686-montavista-linux", "i686-gnu", + "i586-suse-linux", "i686-montavista-linux", }; static const char *const LoongArch64LibDirs[] = {"/lib64", "/lib"}; @@ -2652,6 +2657,23 @@ void Generic_GCC::GCCInstallationDetector::AddDefaultGCCPrefixes( return; } + if (TargetTriple.isOSHurd()) { + switch (TargetTriple.getArch()) { + case llvm::Triple::x86_64: + LibDirs.append(begin(X86_64LibDirs), end(X86_64LibDirs)); + TripleAliases.push_back("x86_64-gnu"); + break; + case llvm::Triple::x86: + LibDirs.append(begin(X86LibDirs), end(X86LibDirs)); + TripleAliases.push_back("i686-gnu"); + break; + default: + break; + } + + return; + } + switch (TargetTriple.getArch()) { case llvm::Triple::aarch64: LibDirs.append(begin(AArch64LibDirs), end(AArch64LibDirs)); diff --git a/clang/lib/Driver/ToolChains/Hexagon.cpp b/clang/lib/Driver/ToolChains/Hexagon.cpp index 6a2a105bee3..d1eed931be5 100644 --- a/clang/lib/Driver/ToolChains/Hexagon.cpp +++ b/clang/lib/Driver/ToolChains/Hexagon.cpp @@ -550,7 +550,7 @@ std::string HexagonToolChain::getCompilerRTPath() const { if (!SelectedMultilibs.empty()) { Dir += SelectedMultilibs.back().gccSuffix(); } - return std::string(Dir.str()); + return std::string(Dir); } void HexagonToolChain::getHexagonLibraryPaths(const ArgList &Args, diff --git a/clang/lib/Driver/ToolChains/Hurd.cpp b/clang/lib/Driver/ToolChains/Hurd.cpp index 7a4c2bb7ede..0bc114b90ff 100644 --- a/clang/lib/Driver/ToolChains/Hurd.cpp +++ b/clang/lib/Driver/ToolChains/Hurd.cpp @@ -30,13 +30,21 @@ using tools::addPathIfExists; std::string Hurd::getMultiarchTriple(const Driver &D, const llvm::Triple &TargetTriple, StringRef SysRoot) const { - if (TargetTriple.getArch() == llvm::Triple::x86) { + switch (TargetTriple.getArch()) { + default: + break; + + case llvm::Triple::x86: // We use the existence of '/lib/' as a directory to detect some // common hurd triples that don't quite match the Clang triple for both // 32-bit and 64-bit targets. Multiarch fixes its install triples to these // regardless of what the actual target triple is. if (D.getVFS().exists(SysRoot + "/lib/i386-gnu")) return "i386-gnu"; + break; + + case llvm::Triple::x86_64: + return "x86_64-gnu"; } // For most architectures, just use whatever we have rather than trying to be @@ -126,8 +134,14 @@ Tool *Hurd::buildAssembler() const { } std::string Hurd::getDynamicLinker(const ArgList &Args) const { - if (getArch() == llvm::Triple::x86) + switch (getArch()) { + case llvm::Triple::x86: return "/lib/ld.so"; + case llvm::Triple::x86_64: + return "/lib/ld-x86-64.so.1"; + default: + break; + } llvm_unreachable("unsupported architecture"); } diff --git a/clang/lib/Driver/ToolChains/MSP430.cpp b/clang/lib/Driver/ToolChains/MSP430.cpp index 8dc23521f40..07e875c6496 100644 --- a/clang/lib/Driver/ToolChains/MSP430.cpp +++ b/clang/lib/Driver/ToolChains/MSP430.cpp @@ -142,7 +142,7 @@ std::string MSP430ToolChain::computeSysRoot() const { else llvm::sys::path::append(Dir, getDriver().Dir, ".."); - return std::string(Dir.str()); + return std::string(Dir); } void MSP430ToolChain::AddClangSystemIncludeArgs(const ArgList &DriverArgs, diff --git a/clang/lib/Driver/ToolChains/MSVC.cpp b/clang/lib/Driver/ToolChains/MSVC.cpp index 8e1e9517383..39652222515 100644 --- a/clang/lib/Driver/ToolChains/MSVC.cpp +++ b/clang/lib/Driver/ToolChains/MSVC.cpp @@ -495,24 +495,24 @@ bool MSVCToolChain::isPICDefaultForced() const { void MSVCToolChain::AddCudaIncludeArgs(const ArgList &DriverArgs, ArgStringList &CC1Args) const { - CudaInstallation.AddCudaIncludeArgs(DriverArgs, CC1Args); + CudaInstallation->AddCudaIncludeArgs(DriverArgs, CC1Args); } void MSVCToolChain::AddHIPIncludeArgs(const ArgList &DriverArgs, ArgStringList &CC1Args) const { - RocmInstallation.AddHIPIncludeArgs(DriverArgs, CC1Args); + RocmInstallation->AddHIPIncludeArgs(DriverArgs, CC1Args); } void MSVCToolChain::AddHIPRuntimeLibArgs(const ArgList &Args, ArgStringList &CmdArgs) const { CmdArgs.append({Args.MakeArgString(StringRef("-libpath:") + - RocmInstallation.getLibPath()), + RocmInstallation->getLibPath()), "amdhip64.lib"}); } void MSVCToolChain::printVerboseInfo(raw_ostream &OS) const { - CudaInstallation.print(OS); - RocmInstallation.print(OS); + CudaInstallation->print(OS); + RocmInstallation->print(OS); } std::string @@ -585,7 +585,7 @@ bool MSVCToolChain::getUniversalCRTLibraryPath(const ArgList &Args, llvm::SmallString<128> LibPath(UniversalCRTSdkPath); llvm::sys::path::append(LibPath, "Lib", UCRTVersion, "ucrt", ArchName); - Path = std::string(LibPath.str()); + Path = std::string(LibPath); return true; } diff --git a/clang/lib/Driver/ToolChains/MSVC.h b/clang/lib/Driver/ToolChains/MSVC.h index fb27c621f2d..48369e030aa 100644 --- a/clang/lib/Driver/ToolChains/MSVC.h +++ b/clang/lib/Driver/ToolChains/MSVC.h @@ -11,6 +11,7 @@ #include "AMDGPU.h" #include "Cuda.h" +#include "LazyDetector.h" #include "clang/Driver/Compilation.h" #include "clang/Driver/Tool.h" #include "clang/Driver/ToolChain.h" @@ -136,8 +137,8 @@ private: std::optional WinSdkDir, WinSdkVersion, WinSysRoot; std::string VCToolChainPath; llvm::ToolsetLayout VSLayout = llvm::ToolsetLayout::OlderVS; - CudaInstallationDetector CudaInstallation; - RocmInstallationDetector RocmInstallation; + LazyDetector CudaInstallation; + LazyDetector RocmInstallation; }; } // end namespace toolchains diff --git a/clang/lib/Driver/ToolChains/MinGW.cpp b/clang/lib/Driver/ToolChains/MinGW.cpp index 18fc9d4b680..067758c05e9 100644 --- a/clang/lib/Driver/ToolChains/MinGW.cpp +++ b/clang/lib/Driver/ToolChains/MinGW.cpp @@ -614,17 +614,17 @@ SanitizerMask toolchains::MinGW::getSupportedSanitizers() const { void toolchains::MinGW::AddCudaIncludeArgs(const ArgList &DriverArgs, ArgStringList &CC1Args) const { - CudaInstallation.AddCudaIncludeArgs(DriverArgs, CC1Args); + CudaInstallation->AddCudaIncludeArgs(DriverArgs, CC1Args); } void toolchains::MinGW::AddHIPIncludeArgs(const ArgList &DriverArgs, ArgStringList &CC1Args) const { - RocmInstallation.AddHIPIncludeArgs(DriverArgs, CC1Args); + RocmInstallation->AddHIPIncludeArgs(DriverArgs, CC1Args); } void toolchains::MinGW::printVerboseInfo(raw_ostream &OS) const { - CudaInstallation.print(OS); - RocmInstallation.print(OS); + CudaInstallation->print(OS); + RocmInstallation->print(OS); } // Include directories for various hosts: diff --git a/clang/lib/Driver/ToolChains/MinGW.h b/clang/lib/Driver/ToolChains/MinGW.h index 75d629d5d1c..a9963d8d06c 100644 --- a/clang/lib/Driver/ToolChains/MinGW.h +++ b/clang/lib/Driver/ToolChains/MinGW.h @@ -11,6 +11,7 @@ #include "Cuda.h" #include "Gnu.h" +#include "LazyDetector.h" #include "ROCm.h" #include "clang/Driver/Tool.h" #include "clang/Driver/ToolChain.h" @@ -102,8 +103,8 @@ protected: Tool *buildAssembler() const override; private: - CudaInstallationDetector CudaInstallation; - RocmInstallationDetector RocmInstallation; + LazyDetector CudaInstallation; + LazyDetector RocmInstallation; std::string Base; std::string GccLibDir; diff --git a/clang/lib/Driver/ToolChains/MipsLinux.cpp b/clang/lib/Driver/ToolChains/MipsLinux.cpp index eacdcbf730b..4183eccceed 100644 --- a/clang/lib/Driver/ToolChains/MipsLinux.cpp +++ b/clang/lib/Driver/ToolChains/MipsLinux.cpp @@ -138,5 +138,5 @@ std::string MipsLLVMToolChain::getCompilerRT(const ArgList &Args, } llvm::sys::path::append( Path, Twine("libclang_rt." + Component + "-" + "mips" + Suffix)); - return std::string(Path.str()); + return std::string(Path); } diff --git a/clang/lib/Driver/ToolChains/OpenBSD.cpp b/clang/lib/Driver/ToolChains/OpenBSD.cpp index 21b9004ef2d..fd6aa4d7e68 100644 --- a/clang/lib/Driver/ToolChains/OpenBSD.cpp +++ b/clang/lib/Driver/ToolChains/OpenBSD.cpp @@ -371,7 +371,7 @@ std::string OpenBSD::getCompilerRT(const ArgList &Args, StringRef Component, if (Component == "builtins") { SmallString<128> Path(getDriver().SysRoot); llvm::sys::path::append(Path, "/usr/lib/libcompiler_rt.a"); - return std::string(Path.str()); + return std::string(Path); } SmallString<128> P(getDriver().ResourceDir); std::string CRTBasename = @@ -379,7 +379,7 @@ std::string OpenBSD::getCompilerRT(const ArgList &Args, StringRef Component, llvm::sys::path::append(P, "lib", CRTBasename); // Checks if this is the base system case which uses a different location. if (getVFS().exists(P)) - return std::string(P.str()); + return std::string(P); return ToolChain::getCompilerRT(Args, Component, Type); } diff --git a/clang/lib/Driver/ToolChains/PS4CPU.cpp b/clang/lib/Driver/ToolChains/PS4CPU.cpp index 5fd82d1da19..8ba8b80cfec 100644 --- a/clang/lib/Driver/ToolChains/PS4CPU.cpp +++ b/clang/lib/Driver/ToolChains/PS4CPU.cpp @@ -292,7 +292,7 @@ toolchains::PS4PS5Base::PS4PS5Base(const Driver &D, const llvm::Triple &Triple, << Twine(Platform, " system libraries").str() << SDKLibDir << Whence; return; } - getFilePaths().push_back(std::string(SDKLibDir.str())); + getFilePaths().push_back(std::string(SDKLibDir)); } void toolchains::PS4PS5Base::AddClangSystemIncludeArgs( @@ -359,6 +359,12 @@ void toolchains::PS4PS5Base::addClangTargetOptions( CC1Args.push_back("-fno-use-init-array"); + // Default to -fvisibility-global-new-delete=source for PS5. + if (getTriple().isPS5() && + !DriverArgs.hasArg(options::OPT_fvisibility_global_new_delete_EQ, + options::OPT_fvisibility_global_new_delete_hidden)) + CC1Args.push_back("-fvisibility-global-new-delete=source"); + const Arg *A = DriverArgs.getLastArg(options::OPT_fvisibility_from_dllstorageclass, options::OPT_fno_visibility_from_dllstorageclass); diff --git a/clang/lib/Driver/ToolChains/RISCVToolchain.cpp b/clang/lib/Driver/ToolChains/RISCVToolchain.cpp index 7e6abd14442..5e4fa4d5331 100644 --- a/clang/lib/Driver/ToolChains/RISCVToolchain.cpp +++ b/clang/lib/Driver/ToolChains/RISCVToolchain.cpp @@ -141,7 +141,7 @@ std::string RISCVToolChain::computeSysRoot() const { if (!llvm::sys::fs::exists(SysRootDir)) return std::string(); - return std::string(SysRootDir.str()); + return std::string(SysRootDir); } void RISCV::Linker::ConstructJob(Compilation &C, const JobAction &JA, diff --git a/clang/lib/Driver/Types.cpp b/clang/lib/Driver/Types.cpp index 08df34ade7b..a7b6b9000e1 100644 --- a/clang/lib/Driver/Types.cpp +++ b/clang/lib/Driver/Types.cpp @@ -133,7 +133,7 @@ bool types::isAcceptedByClang(ID Id) { case TY_Asm: case TY_C: case TY_PP_C: - case TY_CL: case TY_CLCXX: + case TY_CL: case TY_PP_CL: case TY_CLCXX: case TY_PP_CLCXX: case TY_CUDA: case TY_PP_CUDA: case TY_CUDA_DEVICE: case TY_HIP: @@ -181,7 +181,9 @@ bool types::isDerivedFromC(ID Id) { case TY_PP_C: case TY_C: case TY_CL: + case TY_PP_CL: case TY_CLCXX: + case TY_PP_CLCXX: case TY_PP_CUDA: case TY_CUDA: case TY_CUDA_DEVICE: @@ -241,6 +243,7 @@ bool types::isCXX(ID Id) { case TY_PP_CXXHeaderUnit: case TY_ObjCXXHeader: case TY_PP_ObjCXXHeader: case TY_CXXModule: case TY_PP_CXXModule: + case TY_PP_CLCXX: case TY_CUDA: case TY_PP_CUDA: case TY_CUDA_DEVICE: case TY_HIP: case TY_PP_HIP: @@ -310,7 +313,9 @@ types::ID types::lookupTypeForExtension(llvm::StringRef Ext) { .Case("cc", TY_CXX) .Case("CC", TY_CXX) .Case("cl", TY_CL) + .Case("cli", TY_PP_CL) .Case("clcpp", TY_CLCXX) + .Case("clii", TY_PP_CLCXX) .Case("cp", TY_CXX) .Case("cu", TY_CUDA) .Case("hh", TY_CXXHeader) diff --git a/clang/lib/ExtractAPI/API.cpp b/clang/lib/ExtractAPI/API.cpp index 71c655ba5b5..aa7a1e9360f 100644 --- a/clang/lib/ExtractAPI/API.cpp +++ b/clang/lib/ExtractAPI/API.cpp @@ -45,7 +45,7 @@ RecordTy *addTopLevelRecord(DenseMap &USRLookupTable, NamespaceRecord * APISet::addNamespace(APIRecord *Parent, StringRef Name, StringRef USR, - PresumedLoc Loc, AvailabilitySet Availability, + PresumedLoc Loc, AvailabilityInfo Availability, LinkageInfo Linkage, const DocComment &Comment, DeclarationFragments Declaration, DeclarationFragments SubHeading, bool IsFromSystemHeader) { @@ -61,17 +61,17 @@ APISet::addNamespace(APIRecord *Parent, StringRef Name, StringRef USR, GlobalVariableRecord * APISet::addGlobalVar(StringRef Name, StringRef USR, PresumedLoc Loc, - AvailabilitySet Availabilities, LinkageInfo Linkage, + AvailabilityInfo Availability, LinkageInfo Linkage, const DocComment &Comment, DeclarationFragments Fragments, DeclarationFragments SubHeading, bool IsFromSystemHeader) { return addTopLevelRecord(USRBasedLookupTable, GlobalVariables, USR, Name, Loc, - std::move(Availabilities), Linkage, Comment, - Fragments, SubHeading, IsFromSystemHeader); + std::move(Availability), Linkage, Comment, Fragments, + SubHeading, IsFromSystemHeader); } GlobalVariableTemplateRecord *APISet::addGlobalVariableTemplate( StringRef Name, StringRef USR, PresumedLoc Loc, - AvailabilitySet Availability, LinkageInfo Linkage, + AvailabilityInfo Availability, LinkageInfo Linkage, const DocComment &Comment, DeclarationFragments Declaration, DeclarationFragments SubHeading, Template Template, bool IsFromSystemHeader) { @@ -83,19 +83,18 @@ GlobalVariableTemplateRecord *APISet::addGlobalVariableTemplate( GlobalFunctionRecord *APISet::addGlobalFunction( StringRef Name, StringRef USR, PresumedLoc Loc, - AvailabilitySet Availabilities, LinkageInfo Linkage, + AvailabilityInfo Availability, LinkageInfo Linkage, const DocComment &Comment, DeclarationFragments Fragments, DeclarationFragments SubHeading, FunctionSignature Signature, bool IsFromSystemHeader) { return addTopLevelRecord(USRBasedLookupTable, GlobalFunctions, USR, Name, Loc, - std::move(Availabilities), Linkage, Comment, - Fragments, SubHeading, Signature, - IsFromSystemHeader); + std::move(Availability), Linkage, Comment, Fragments, + SubHeading, Signature, IsFromSystemHeader); } GlobalFunctionTemplateRecord *APISet::addGlobalFunctionTemplate( StringRef Name, StringRef USR, PresumedLoc Loc, - AvailabilitySet Availability, LinkageInfo Linkage, + AvailabilityInfo Availability, LinkageInfo Linkage, const DocComment &Comment, DeclarationFragments Declaration, DeclarationFragments SubHeading, FunctionSignature Signature, Template Template, bool IsFromSystemHeader) { @@ -108,7 +107,7 @@ GlobalFunctionTemplateRecord *APISet::addGlobalFunctionTemplate( GlobalFunctionTemplateSpecializationRecord * APISet::addGlobalFunctionTemplateSpecialization( StringRef Name, StringRef USR, PresumedLoc Loc, - AvailabilitySet Availability, LinkageInfo Linkage, + AvailabilityInfo Availability, LinkageInfo Linkage, const DocComment &Comment, DeclarationFragments Declaration, DeclarationFragments SubHeading, FunctionSignature Signature, bool IsFromSystemHeader) { @@ -120,14 +119,14 @@ APISet::addGlobalFunctionTemplateSpecialization( EnumConstantRecord *APISet::addEnumConstant(EnumRecord *Enum, StringRef Name, StringRef USR, PresumedLoc Loc, - AvailabilitySet Availabilities, + AvailabilityInfo Availability, const DocComment &Comment, DeclarationFragments Declaration, DeclarationFragments SubHeading, bool IsFromSystemHeader) { auto Record = std::make_unique( - USR, Name, Loc, std::move(Availabilities), Comment, Declaration, - SubHeading, IsFromSystemHeader); + USR, Name, Loc, std::move(Availability), Comment, Declaration, SubHeading, + IsFromSystemHeader); Record->ParentInformation = APIRecord::HierarchyInformation( Enum->USR, Enum->Name, Enum->getKind(), Enum); USRBasedLookupTable.insert({USR, Record.get()}); @@ -135,64 +134,63 @@ EnumConstantRecord *APISet::addEnumConstant(EnumRecord *Enum, StringRef Name, } EnumRecord *APISet::addEnum(StringRef Name, StringRef USR, PresumedLoc Loc, - AvailabilitySet Availabilities, + AvailabilityInfo Availability, const DocComment &Comment, DeclarationFragments Declaration, DeclarationFragments SubHeading, bool IsFromSystemHeader) { return addTopLevelRecord(USRBasedLookupTable, Enums, USR, Name, Loc, - std::move(Availabilities), Comment, Declaration, + std::move(Availability), Comment, Declaration, SubHeading, IsFromSystemHeader); } -StructFieldRecord *APISet::addStructField(StructRecord *Struct, StringRef Name, - StringRef USR, PresumedLoc Loc, - AvailabilitySet Availabilities, - const DocComment &Comment, - DeclarationFragments Declaration, - DeclarationFragments SubHeading, - bool IsFromSystemHeader) { - auto Record = std::make_unique( - USR, Name, Loc, std::move(Availabilities), Comment, Declaration, - SubHeading, IsFromSystemHeader); - Record->ParentInformation = APIRecord::HierarchyInformation( - Struct->USR, Struct->Name, Struct->getKind(), Struct); - USRBasedLookupTable.insert({USR, Record.get()}); - return Struct->Fields.emplace_back(std::move(Record)).get(); +RecordFieldRecord *APISet::addRecordField( + RecordRecord *Record, StringRef Name, StringRef USR, PresumedLoc Loc, + AvailabilityInfo Availability, const DocComment &Comment, + DeclarationFragments Declaration, DeclarationFragments SubHeading, + APIRecord::RecordKind Kind, bool IsFromSystemHeader) { + auto RecordField = std::make_unique( + USR, Name, Loc, std::move(Availability), Comment, Declaration, SubHeading, + Kind, IsFromSystemHeader); + RecordField->ParentInformation = APIRecord::HierarchyInformation( + Record->USR, Record->Name, Record->getKind(), Record); + USRBasedLookupTable.insert({USR, RecordField.get()}); + return Record->Fields.emplace_back(std::move(RecordField)).get(); } -StructRecord *APISet::addStruct(StringRef Name, StringRef USR, PresumedLoc Loc, - AvailabilitySet Availabilities, +RecordRecord *APISet::addRecord(StringRef Name, StringRef USR, PresumedLoc Loc, + AvailabilityInfo Availability, const DocComment &Comment, DeclarationFragments Declaration, DeclarationFragments SubHeading, + APIRecord::RecordKind Kind, bool IsFromSystemHeader) { - return addTopLevelRecord(USRBasedLookupTable, Structs, USR, Name, Loc, - std::move(Availabilities), Comment, Declaration, - SubHeading, IsFromSystemHeader); + return addTopLevelRecord(USRBasedLookupTable, Records, USR, Name, Loc, + std::move(Availability), Comment, Declaration, + SubHeading, Kind, IsFromSystemHeader); } StaticFieldRecord * APISet::addStaticField(StringRef Name, StringRef USR, PresumedLoc Loc, - AvailabilitySet Availabilities, LinkageInfo Linkage, + AvailabilityInfo Availability, LinkageInfo Linkage, const DocComment &Comment, DeclarationFragments Declaration, DeclarationFragments SubHeading, SymbolReference Context, AccessControl Access, bool IsFromSystemHeader) { return addTopLevelRecord(USRBasedLookupTable, StaticFields, USR, Name, Loc, - std::move(Availabilities), Linkage, Comment, + std::move(Availability), Linkage, Comment, Declaration, SubHeading, Context, Access, IsFromSystemHeader); } CXXFieldRecord * APISet::addCXXField(APIRecord *CXXClass, StringRef Name, StringRef USR, - PresumedLoc Loc, AvailabilitySet Availabilities, + PresumedLoc Loc, AvailabilityInfo Availability, const DocComment &Comment, DeclarationFragments Declaration, DeclarationFragments SubHeading, AccessControl Access, bool IsFromSystemHeader) { auto *Record = addTopLevelRecord( - USRBasedLookupTable, CXXFields, USR, Name, Loc, std::move(Availabilities), + USRBasedLookupTable, CXXFields, USR, Name, Loc, std::move(Availability), Comment, Declaration, SubHeading, Access, IsFromSystemHeader); Record->ParentInformation = APIRecord::HierarchyInformation( CXXClass->USR, CXXClass->Name, CXXClass->getKind(), CXXClass); @@ -201,7 +199,7 @@ APISet::addCXXField(APIRecord *CXXClass, StringRef Name, StringRef USR, CXXFieldTemplateRecord *APISet::addCXXFieldTemplate( APIRecord *Parent, StringRef Name, StringRef USR, PresumedLoc Loc, - AvailabilitySet Availability, const DocComment &Comment, + AvailabilityInfo Availability, const DocComment &Comment, DeclarationFragments Declaration, DeclarationFragments SubHeading, AccessControl Access, Template Template, bool IsFromSystemHeader) { auto *Record = @@ -216,14 +214,13 @@ CXXFieldTemplateRecord *APISet::addCXXFieldTemplate( CXXClassRecord * APISet::addCXXClass(APIRecord *Parent, StringRef Name, StringRef USR, - PresumedLoc Loc, AvailabilitySet Availabilities, + PresumedLoc Loc, AvailabilityInfo Availability, const DocComment &Comment, DeclarationFragments Declaration, DeclarationFragments SubHeading, APIRecord::RecordKind Kind, AccessControl Access, bool IsFromSystemHeader) { - auto *Record = - addTopLevelRecord(USRBasedLookupTable, CXXClasses, USR, Name, Loc, - std::move(Availabilities), Comment, Declaration, - SubHeading, Kind, Access, IsFromSystemHeader); + auto *Record = addTopLevelRecord( + USRBasedLookupTable, CXXClasses, USR, Name, Loc, std::move(Availability), + Comment, Declaration, SubHeading, Kind, Access, IsFromSystemHeader); if (Parent) Record->ParentInformation = APIRecord::HierarchyInformation( Parent->USR, Parent->Name, Parent->getKind(), Parent); @@ -232,7 +229,7 @@ APISet::addCXXClass(APIRecord *Parent, StringRef Name, StringRef USR, ClassTemplateRecord *APISet::addClassTemplate( APIRecord *Parent, StringRef Name, StringRef USR, PresumedLoc Loc, - AvailabilitySet Availability, const DocComment &Comment, + AvailabilityInfo Availability, const DocComment &Comment, DeclarationFragments Declaration, DeclarationFragments SubHeading, Template Template, AccessControl Access, bool IsFromSystemHeader) { auto *Record = @@ -247,7 +244,7 @@ ClassTemplateRecord *APISet::addClassTemplate( ClassTemplateSpecializationRecord *APISet::addClassTemplateSpecialization( APIRecord *Parent, StringRef Name, StringRef USR, PresumedLoc Loc, - AvailabilitySet Availability, const DocComment &Comment, + AvailabilityInfo Availability, const DocComment &Comment, DeclarationFragments Declaration, DeclarationFragments SubHeading, AccessControl Access, bool IsFromSystemHeader) { auto *Record = @@ -263,7 +260,7 @@ ClassTemplateSpecializationRecord *APISet::addClassTemplateSpecialization( ClassTemplatePartialSpecializationRecord * APISet::addClassTemplatePartialSpecialization( APIRecord *Parent, StringRef Name, StringRef USR, PresumedLoc Loc, - AvailabilitySet Availability, const DocComment &Comment, + AvailabilityInfo Availability, const DocComment &Comment, DeclarationFragments Declaration, DeclarationFragments SubHeading, Template Template, AccessControl Access, bool IsFromSystemHeader) { auto *Record = addTopLevelRecord( @@ -279,7 +276,7 @@ APISet::addClassTemplatePartialSpecialization( GlobalVariableTemplateSpecializationRecord * APISet::addGlobalVariableTemplateSpecialization( StringRef Name, StringRef USR, PresumedLoc Loc, - AvailabilitySet Availability, LinkageInfo Linkage, + AvailabilityInfo Availability, LinkageInfo Linkage, const DocComment &Comment, DeclarationFragments Declaration, DeclarationFragments SubHeading, bool IsFromSystemHeader) { return addTopLevelRecord(USRBasedLookupTable, @@ -291,7 +288,7 @@ APISet::addGlobalVariableTemplateSpecialization( GlobalVariableTemplatePartialSpecializationRecord * APISet::addGlobalVariableTemplatePartialSpecialization( StringRef Name, StringRef USR, PresumedLoc Loc, - AvailabilitySet Availability, LinkageInfo Linkage, + AvailabilityInfo Availability, LinkageInfo Linkage, const DocComment &Comment, DeclarationFragments Declaration, DeclarationFragments SubHeading, Template Template, bool IsFromSystemHeader) { @@ -302,7 +299,8 @@ APISet::addGlobalVariableTemplatePartialSpecialization( } ConceptRecord *APISet::addConcept(StringRef Name, StringRef USR, - PresumedLoc Loc, AvailabilitySet Availability, + PresumedLoc Loc, + AvailabilityInfo Availability, const DocComment &Comment, DeclarationFragments Declaration, DeclarationFragments SubHeading, @@ -314,7 +312,7 @@ ConceptRecord *APISet::addConcept(StringRef Name, StringRef USR, CXXMethodRecord *APISet::addCXXInstanceMethod( APIRecord *CXXClassRecord, StringRef Name, StringRef USR, PresumedLoc Loc, - AvailabilitySet Availability, const DocComment &Comment, + AvailabilityInfo Availability, const DocComment &Comment, DeclarationFragments Declaration, DeclarationFragments SubHeading, FunctionSignature Signature, AccessControl Access, bool IsFromSystemHeader) { @@ -331,7 +329,7 @@ CXXMethodRecord *APISet::addCXXInstanceMethod( CXXMethodRecord *APISet::addCXXStaticMethod( APIRecord *CXXClassRecord, StringRef Name, StringRef USR, PresumedLoc Loc, - AvailabilitySet Availability, const DocComment &Comment, + AvailabilityInfo Availability, const DocComment &Comment, DeclarationFragments Declaration, DeclarationFragments SubHeading, FunctionSignature Signature, AccessControl Access, bool IsFromSystemHeader) { @@ -348,7 +346,7 @@ CXXMethodRecord *APISet::addCXXStaticMethod( CXXMethodTemplateRecord *APISet::addCXXMethodTemplate( APIRecord *Parent, StringRef Name, StringRef USR, PresumedLoc Loc, - AvailabilitySet Availability, const DocComment &Comment, + AvailabilityInfo Availability, const DocComment &Comment, DeclarationFragments Declaration, DeclarationFragments SubHeading, FunctionSignature Signature, AccessControl Access, Template Template, bool IsFromSystemHeader) { @@ -364,7 +362,7 @@ CXXMethodTemplateRecord *APISet::addCXXMethodTemplate( CXXMethodTemplateSpecializationRecord *APISet::addCXXMethodTemplateSpec( APIRecord *Parent, StringRef Name, StringRef USR, PresumedLoc Loc, - AvailabilitySet Availability, const DocComment &Comment, + AvailabilityInfo Availability, const DocComment &Comment, DeclarationFragments Declaration, DeclarationFragments SubHeading, FunctionSignature Signature, AccessControl Access, bool IsFromSystemHeader) { @@ -381,14 +379,14 @@ CXXMethodTemplateSpecializationRecord *APISet::addCXXMethodTemplateSpec( ObjCCategoryRecord *APISet::addObjCCategory( StringRef Name, StringRef USR, PresumedLoc Loc, - AvailabilitySet Availabilities, const DocComment &Comment, + AvailabilityInfo Availability, const DocComment &Comment, DeclarationFragments Declaration, DeclarationFragments SubHeading, SymbolReference Interface, bool IsFromSystemHeader, bool IsFromExternalModule) { // Create the category record. auto *Record = addTopLevelRecord(USRBasedLookupTable, ObjCCategories, USR, Name, Loc, - std::move(Availabilities), Comment, Declaration, + std::move(Availability), Comment, Declaration, SubHeading, Interface, IsFromSystemHeader); Record->IsFromExternalModule = IsFromExternalModule; @@ -402,31 +400,31 @@ ObjCCategoryRecord *APISet::addObjCCategory( ObjCInterfaceRecord * APISet::addObjCInterface(StringRef Name, StringRef USR, PresumedLoc Loc, - AvailabilitySet Availabilities, LinkageInfo Linkage, + AvailabilityInfo Availability, LinkageInfo Linkage, const DocComment &Comment, DeclarationFragments Declaration, DeclarationFragments SubHeading, SymbolReference SuperClass, bool IsFromSystemHeader) { return addTopLevelRecord(USRBasedLookupTable, ObjCInterfaces, USR, Name, Loc, - std::move(Availabilities), Linkage, Comment, + std::move(Availability), Linkage, Comment, Declaration, SubHeading, SuperClass, IsFromSystemHeader); } ObjCMethodRecord *APISet::addObjCMethod( ObjCContainerRecord *Container, StringRef Name, StringRef USR, - PresumedLoc Loc, AvailabilitySet Availabilities, const DocComment &Comment, + PresumedLoc Loc, AvailabilityInfo Availability, const DocComment &Comment, DeclarationFragments Declaration, DeclarationFragments SubHeading, FunctionSignature Signature, bool IsInstanceMethod, bool IsFromSystemHeader) { std::unique_ptr Record; if (IsInstanceMethod) Record = std::make_unique( - USR, Name, Loc, std::move(Availabilities), Comment, Declaration, + USR, Name, Loc, std::move(Availability), Comment, Declaration, SubHeading, Signature, IsFromSystemHeader); else Record = std::make_unique( - USR, Name, Loc, std::move(Availabilities), Comment, Declaration, + USR, Name, Loc, std::move(Availability), Comment, Declaration, SubHeading, Signature, IsFromSystemHeader); Record->ParentInformation = APIRecord::HierarchyInformation( @@ -437,7 +435,7 @@ ObjCMethodRecord *APISet::addObjCMethod( ObjCPropertyRecord *APISet::addObjCProperty( ObjCContainerRecord *Container, StringRef Name, StringRef USR, - PresumedLoc Loc, AvailabilitySet Availabilities, const DocComment &Comment, + PresumedLoc Loc, AvailabilityInfo Availability, const DocComment &Comment, DeclarationFragments Declaration, DeclarationFragments SubHeading, ObjCPropertyRecord::AttributeKind Attributes, StringRef GetterName, StringRef SetterName, bool IsOptional, bool IsInstanceProperty, @@ -445,12 +443,12 @@ ObjCPropertyRecord *APISet::addObjCProperty( std::unique_ptr Record; if (IsInstanceProperty) Record = std::make_unique( - USR, Name, Loc, std::move(Availabilities), Comment, Declaration, + USR, Name, Loc, std::move(Availability), Comment, Declaration, SubHeading, Attributes, GetterName, SetterName, IsOptional, IsFromSystemHeader); else Record = std::make_unique( - USR, Name, Loc, std::move(Availabilities), Comment, Declaration, + USR, Name, Loc, std::move(Availability), Comment, Declaration, SubHeading, Attributes, GetterName, SetterName, IsOptional, IsFromSystemHeader); Record->ParentInformation = APIRecord::HierarchyInformation( @@ -461,12 +459,12 @@ ObjCPropertyRecord *APISet::addObjCProperty( ObjCInstanceVariableRecord *APISet::addObjCInstanceVariable( ObjCContainerRecord *Container, StringRef Name, StringRef USR, - PresumedLoc Loc, AvailabilitySet Availabilities, const DocComment &Comment, + PresumedLoc Loc, AvailabilityInfo Availability, const DocComment &Comment, DeclarationFragments Declaration, DeclarationFragments SubHeading, ObjCInstanceVariableRecord::AccessControl Access, bool IsFromSystemHeader) { auto Record = std::make_unique( - USR, Name, Loc, std::move(Availabilities), Comment, Declaration, - SubHeading, Access, IsFromSystemHeader); + USR, Name, Loc, std::move(Availability), Comment, Declaration, SubHeading, + Access, IsFromSystemHeader); Record->ParentInformation = APIRecord::HierarchyInformation( Container->USR, Container->Name, Container->getKind(), Container); USRBasedLookupTable.insert({USR, Record.get()}); @@ -475,13 +473,13 @@ ObjCInstanceVariableRecord *APISet::addObjCInstanceVariable( ObjCProtocolRecord *APISet::addObjCProtocol(StringRef Name, StringRef USR, PresumedLoc Loc, - AvailabilitySet Availabilities, + AvailabilityInfo Availability, const DocComment &Comment, DeclarationFragments Declaration, DeclarationFragments SubHeading, bool IsFromSystemHeader) { return addTopLevelRecord(USRBasedLookupTable, ObjCProtocols, USR, Name, Loc, - std::move(Availabilities), Comment, Declaration, + std::move(Availability), Comment, Declaration, SubHeading, IsFromSystemHeader); } @@ -496,12 +494,12 @@ APISet::addMacroDefinition(StringRef Name, StringRef USR, PresumedLoc Loc, TypedefRecord * APISet::addTypedef(StringRef Name, StringRef USR, PresumedLoc Loc, - AvailabilitySet Availabilities, const DocComment &Comment, + AvailabilityInfo Availability, const DocComment &Comment, DeclarationFragments Declaration, DeclarationFragments SubHeading, SymbolReference UnderlyingType, bool IsFromSystemHeader) { return addTopLevelRecord(USRBasedLookupTable, Typedefs, USR, Name, Loc, - std::move(Availabilities), Comment, Declaration, + std::move(Availability), Comment, Declaration, SubHeading, UnderlyingType, IsFromSystemHeader); } @@ -548,8 +546,8 @@ void GlobalFunctionRecord::anchor() {} void GlobalVariableRecord::anchor() {} void EnumConstantRecord::anchor() {} void EnumRecord::anchor() {} -void StructFieldRecord::anchor() {} -void StructRecord::anchor() {} +void RecordFieldRecord::anchor() {} +void RecordRecord::anchor() {} void CXXFieldRecord::anchor() {} void CXXClassRecord::anchor() {} void CXXConstructorRecord::anchor() {} diff --git a/clang/lib/ExtractAPI/AvailabilityInfo.cpp b/clang/lib/ExtractAPI/AvailabilityInfo.cpp index 1df852fdbf9..18e4d16b45b 100644 --- a/clang/lib/ExtractAPI/AvailabilityInfo.cpp +++ b/clang/lib/ExtractAPI/AvailabilityInfo.cpp @@ -1,50 +1,35 @@ #include "clang/ExtractAPI/AvailabilityInfo.h" +#include "clang/AST/ASTContext.h" #include "clang/AST/Attr.h" +#include "clang/Basic/TargetInfo.h" #include "llvm/ADT/STLExtras.h" -using namespace clang; -using namespace extractapi; +using namespace clang::extractapi; +using namespace llvm; -AvailabilitySet::AvailabilitySet(const Decl *Decl) { - // Collect availability attributes from all redeclrations. +AvailabilityInfo AvailabilityInfo::createFromDecl(const Decl *Decl) { + ASTContext &Context = Decl->getASTContext(); + StringRef PlatformName = Context.getTargetInfo().getPlatformName(); + AvailabilityInfo Availability; + + // Collect availability attributes from all redeclarations. for (const auto *RD : Decl->redecls()) { - if (const auto *A = RD->getAttr()) { - if (!A->isImplicit()) { - this->Availabilities.clear(); - UnconditionallyUnavailable = true; - } + for (const auto *A : RD->specific_attrs()) { + if (A->getPlatform()->getName() != PlatformName) + continue; + Availability = + AvailabilityInfo(A->getPlatform()->getName(), A->getIntroduced(), + A->getDeprecated(), A->getObsoleted(), false, false); + break; } - if (const auto *A = RD->getAttr()) { - if (!A->isImplicit()) { - this->Availabilities.clear(); - UnconditionallyDeprecated = true; - } - } + if (const auto *A = RD->getAttr()) + if (!A->isImplicit()) + Availability.UnconditionallyUnavailable = true; - for (const auto *Attr : RD->specific_attrs()) { - StringRef Domain = Attr->getPlatform()->getName(); - auto *Availability = - llvm::find_if(Availabilities, [Domain](const AvailabilityInfo &Info) { - return Domain.equals(Info.Domain); - }); - if (Availability != Availabilities.end()) { - // Get the highest introduced version for all redeclarations. - if (Availability->Introduced < Attr->getIntroduced()) - Availability->Introduced = Attr->getIntroduced(); - - // Get the lowest deprecated version for all redeclarations. - if (Availability->Deprecated > Attr->getDeprecated()) - Availability->Deprecated = Attr->getDeprecated(); - - // Get the lowest obsoleted version for all redeclarations. - if (Availability->Obsoleted > Attr->getObsoleted()) - Availability->Obsoleted = Attr->getObsoleted(); - } else { - Availabilities.emplace_back(Domain, Attr->getIntroduced(), - Attr->getDeprecated(), Attr->getObsoleted(), - Attr->getUnavailable()); - } - } + if (const auto *A = RD->getAttr()) + if (!A->isImplicit()) + Availability.UnconditionallyDeprecated = true; } + return Availability; } diff --git a/clang/lib/ExtractAPI/DeclarationFragments.cpp b/clang/lib/ExtractAPI/DeclarationFragments.cpp index eb6eea0aaf5..56c1f5bf5ea 100644 --- a/clang/lib/ExtractAPI/DeclarationFragments.cpp +++ b/clang/lib/ExtractAPI/DeclarationFragments.cpp @@ -252,6 +252,46 @@ DeclarationFragments DeclarationFragmentsBuilder::getFragmentsForType( DeclarationFragments Fragments; + // An ElaboratedType is a sugar for types that are referred to using an + // elaborated keyword, e.g., `struct S`, `enum E`, or (in C++) via a + // qualified name, e.g., `N::M::type`, or both. + if (const ElaboratedType *ET = dyn_cast(T)) { + ElaboratedTypeKeyword Keyword = ET->getKeyword(); + if (Keyword != ElaboratedTypeKeyword::None) { + Fragments + .append(ElaboratedType::getKeywordName(Keyword), + DeclarationFragments::FragmentKind::Keyword) + .appendSpace(); + } + + if (const NestedNameSpecifier *NNS = ET->getQualifier()) + Fragments.append(getFragmentsForNNS(NNS, Context, After)); + + // After handling the elaborated keyword or qualified name, build + // declaration fragments for the desugared underlying type. + return Fragments.append(getFragmentsForType(ET->desugar(), Context, After)); + } + + // If the type is a typedefed type, get the underlying TypedefNameDecl for a + // direct reference to the typedef instead of the wrapped type. + + // 'id' type is a typedef for an ObjCObjectPointerType + // we treat it as a typedef + if (const TypedefType *TypedefTy = dyn_cast(T)) { + const TypedefNameDecl *Decl = TypedefTy->getDecl(); + TypedefUnderlyingTypeResolver TypedefResolver(Context); + std::string USR = TypedefResolver.getUSRForType(QualType(T, 0)); + + if (T->isObjCIdType()) { + return Fragments.append(Decl->getName(), + DeclarationFragments::FragmentKind::Keyword); + } + + return Fragments.append( + Decl->getName(), DeclarationFragments::FragmentKind::TypeIdentifier, + USR, TypedefResolver.getUnderlyingTypeDecl(QualType(T, 0))); + } + // Declaration fragments of a pointer type is the declaration fragments of // the pointee type followed by a `*`, if (T->isPointerType() && !T->isFunctionPointerType()) @@ -328,46 +368,6 @@ DeclarationFragments DeclarationFragmentsBuilder::getFragmentsForType( getFragmentsForType(AT->getElementType(), Context, After)); } - // An ElaboratedType is a sugar for types that are referred to using an - // elaborated keyword, e.g., `struct S`, `enum E`, or (in C++) via a - // qualified name, e.g., `N::M::type`, or both. - if (const ElaboratedType *ET = dyn_cast(T)) { - ElaboratedTypeKeyword Keyword = ET->getKeyword(); - if (Keyword != ElaboratedTypeKeyword::None) { - Fragments - .append(ElaboratedType::getKeywordName(Keyword), - DeclarationFragments::FragmentKind::Keyword) - .appendSpace(); - } - - if (const NestedNameSpecifier *NNS = ET->getQualifier()) - Fragments.append(getFragmentsForNNS(NNS, Context, After)); - - // After handling the elaborated keyword or qualified name, build - // declaration fragments for the desugared underlying type. - return Fragments.append(getFragmentsForType(ET->desugar(), Context, After)); - } - - // If the type is a typedefed type, get the underlying TypedefNameDecl for a - // direct reference to the typedef instead of the wrapped type. - - // 'id' type is a typedef for an ObjCObjectPointerType - // we treat it as a typedef - if (const TypedefType *TypedefTy = dyn_cast(T)) { - const TypedefNameDecl *Decl = TypedefTy->getDecl(); - TypedefUnderlyingTypeResolver TypedefResolver(Context); - std::string USR = TypedefResolver.getUSRForType(QualType(T, 0)); - - if (T->isObjCIdType()) { - return Fragments.append(Decl->getName(), - DeclarationFragments::FragmentKind::Keyword); - } - - return Fragments.append( - Decl->getName(), DeclarationFragments::FragmentKind::TypeIdentifier, - USR, TypedefResolver.getUnderlyingTypeDecl(QualType(T, 0))); - } - // Everything we care about has been handled now, reduce to the canonical // unqualified base type. QualType Base = T->getCanonicalTypeUnqualified(); @@ -760,13 +760,16 @@ DeclarationFragmentsBuilder::getFragmentsForField(const FieldDecl *Field) { .append(";", DeclarationFragments::FragmentKind::Text); } -DeclarationFragments -DeclarationFragmentsBuilder::getFragmentsForStruct(const RecordDecl *Record) { +DeclarationFragments DeclarationFragmentsBuilder::getFragmentsForRecordDecl( + const RecordDecl *Record) { if (const auto *TypedefNameDecl = Record->getTypedefNameForAnonDecl()) return getFragmentsForTypedef(TypedefNameDecl); DeclarationFragments Fragments; - Fragments.append("struct", DeclarationFragments::FragmentKind::Keyword); + if (Record->isUnion()) + Fragments.append("union", DeclarationFragments::FragmentKind::Keyword); + else + Fragments.append("struct", DeclarationFragments::FragmentKind::Keyword); if (!Record->getName().empty()) Fragments.appendSpace().append( diff --git a/clang/lib/ExtractAPI/Serialization/SymbolGraphSerializer.cpp b/clang/lib/ExtractAPI/Serialization/SymbolGraphSerializer.cpp index 53b22297ee0..349b93e2a23 100644 --- a/clang/lib/ExtractAPI/Serialization/SymbolGraphSerializer.cpp +++ b/clang/lib/ExtractAPI/Serialization/SymbolGraphSerializer.cpp @@ -147,46 +147,40 @@ Object serializeSourceRange(const PresumedLoc &BeginLoc, /// Serialize the availability attributes of a symbol. /// /// Availability information contains the introduced, deprecated, and obsoleted -/// versions of the symbol for a given domain (roughly corresponds to a -/// platform) as semantic versions, if not default. Availability information -/// also contains flags to indicate if the symbol is unconditionally unavailable -/// or deprecated, i.e. \c __attribute__((unavailable)) and \c -/// __attribute__((deprecated)). +/// versions of the symbol as semantic versions, if not default. +/// Availability information also contains flags to indicate if the symbol is +/// unconditionally unavailable or deprecated, +/// i.e. \c __attribute__((unavailable)) and \c __attribute__((deprecated)). /// /// \returns \c std::nullopt if the symbol has default availability attributes, -/// or an \c Array containing the formatted availability information. -std::optional -serializeAvailability(const AvailabilitySet &Availabilities) { - if (Availabilities.isDefault()) +/// or an \c Array containing an object with the formatted availability +/// information. +std::optional serializeAvailability(const AvailabilityInfo &Avail) { + if (Avail.isDefault()) return std::nullopt; + Object Availability; Array AvailabilityArray; - - if (Availabilities.isUnconditionallyDeprecated()) { + Availability["domain"] = Avail.Domain; + serializeObject(Availability, "introduced", + serializeSemanticVersion(Avail.Introduced)); + serializeObject(Availability, "deprecated", + serializeSemanticVersion(Avail.Deprecated)); + serializeObject(Availability, "obsoleted", + serializeSemanticVersion(Avail.Obsoleted)); + if (Avail.isUnconditionallyDeprecated()) { Object UnconditionallyDeprecated; UnconditionallyDeprecated["domain"] = "*"; UnconditionallyDeprecated["isUnconditionallyDeprecated"] = true; AvailabilityArray.emplace_back(std::move(UnconditionallyDeprecated)); } - - // Note unconditionally unavailable records are skipped. - - for (const auto &AvailInfo : Availabilities) { - Object Availability; - Availability["domain"] = AvailInfo.Domain; - if (AvailInfo.Unavailable) - Availability["isUnconditionallyUnavailable"] = true; - else { - serializeObject(Availability, "introduced", - serializeSemanticVersion(AvailInfo.Introduced)); - serializeObject(Availability, "deprecated", - serializeSemanticVersion(AvailInfo.Deprecated)); - serializeObject(Availability, "obsoleted", - serializeSemanticVersion(AvailInfo.Obsoleted)); - } - AvailabilityArray.emplace_back(std::move(Availability)); + if (Avail.isUnconditionallyUnavailable()) { + Object UnconditionallyUnavailable; + UnconditionallyUnavailable["domain"] = "*"; + UnconditionallyUnavailable["isUnconditionallyUnavailable"] = true; + AvailabilityArray.emplace_back(std::move(UnconditionallyUnavailable)); } - + AvailabilityArray.emplace_back(std::move(Availability)); return AvailabilityArray; } @@ -406,7 +400,7 @@ Object serializeSymbolKind(APIRecord::RecordKind RK, Language Lang) { Kind["identifier"] = AddLangPrefix("struct"); Kind["displayName"] = "Structure"; break; - case APIRecord::RK_CXXField: + case APIRecord::RK_UnionField: Kind["identifier"] = AddLangPrefix("property"); Kind["displayName"] = "Instance Property"; break; @@ -414,6 +408,10 @@ Object serializeSymbolKind(APIRecord::RecordKind RK, Language Lang) { Kind["identifier"] = AddLangPrefix("union"); Kind["displayName"] = "Union"; break; + case APIRecord::RK_CXXField: + Kind["identifier"] = AddLangPrefix("property"); + Kind["displayName"] = "Instance Property"; + break; case APIRecord::RK_StaticField: Kind["identifier"] = AddLangPrefix("type.property"); Kind["displayName"] = "Type Property"; @@ -738,7 +736,7 @@ bool SymbolGraphSerializer::shouldSkip(const APIRecord &Record) const { return true; // Skip unconditionally unavailable symbols - if (Record.Availabilities.isUnconditionallyUnavailable()) + if (Record.Availability.isUnconditionallyUnavailable()) return true; // Filter out symbols prefixed with an underscored as they are understood to @@ -764,7 +762,7 @@ SymbolGraphSerializer::serializeAPIRecord(const RecordTy &Record) const { Obj, "location", serializeSourceLocation(Record.Location, /*IncludeFileURI=*/true)); serializeArray(Obj, "availability", - serializeAvailability(Record.Availabilities)); + serializeAvailability(Record.Availability)); serializeObject(Obj, "docComment", serializeDocComment(Record.Comment)); serializeArray(Obj, "declarationFragments", serializeDeclarationFragments(Record.Declaration)); @@ -877,12 +875,12 @@ void SymbolGraphSerializer::visitEnumRecord(const EnumRecord &Record) { serializeMembers(Record, Record.Constants); } -void SymbolGraphSerializer::visitStructRecord(const StructRecord &Record) { - auto Struct = serializeAPIRecord(Record); - if (!Struct) +void SymbolGraphSerializer::visitRecordRecord(const RecordRecord &Record) { + auto SerializedRecord = serializeAPIRecord(Record); + if (!SerializedRecord) return; - Symbols.emplace_back(std::move(*Struct)); + Symbols.emplace_back(std::move(*SerializedRecord)); serializeMembers(Record, Record.Fields); } @@ -1173,7 +1171,9 @@ void SymbolGraphSerializer::serializeSingleRecord(const APIRecord *Record) { visitEnumRecord(*cast(Record)); break; case APIRecord::RK_Struct: - visitStructRecord(*cast(Record)); + LLVM_FALLTHROUGH; + case APIRecord::RK_Union: + visitRecordRecord(*cast(Record)); break; case APIRecord::RK_StaticField: visitStaticFieldRecord(*cast(Record)); diff --git a/clang/lib/Format/ContinuationIndenter.cpp b/clang/lib/Format/ContinuationIndenter.cpp index 102504182c4..a3eb9138b21 100644 --- a/clang/lib/Format/ContinuationIndenter.cpp +++ b/clang/lib/Format/ContinuationIndenter.cpp @@ -703,7 +703,9 @@ void ContinuationIndenter::addTokenOnCurrentLine(LineState &State, bool DryRun, if (Current.is(tok::equal) && (State.Line->First->is(tok::kw_for) || Current.NestingLevel == 0) && - CurrentState.VariablePos == 0) { + CurrentState.VariablePos == 0 && + (!Previous.Previous || + Previous.Previous->isNot(TT_DesignatedInitializerPeriod))) { CurrentState.VariablePos = State.Column; // Move over * and & if they are bound to the variable name. const FormatToken *Tok = &Previous; @@ -738,7 +740,8 @@ void ContinuationIndenter::addTokenOnCurrentLine(LineState &State, bool DryRun, if (!DryRun) { Whitespaces.replaceWhitespace(Current, /*Newlines=*/0, Spaces, - State.Column + Spaces + PPColumnCorrection); + State.Column + Spaces + PPColumnCorrection, + /*IsAligned=*/false, State.Line->InMacroBody); } // If "BreakBeforeInheritanceComma" mode, don't break within the inheritance @@ -768,15 +771,25 @@ void ContinuationIndenter::addTokenOnCurrentLine(LineState &State, bool DryRun, // parenthesis by disallowing any further line breaks if there is no line // break after the opening parenthesis. Don't break if it doesn't conserve // columns. + auto IsOpeningBracket = [&](const FormatToken &Tok) { + auto IsStartOfBracedList = [&]() { + return Tok.is(tok::l_brace) && Tok.isNot(BK_Block) && + Style.Cpp11BracedListStyle; + }; + if (!Tok.isOneOf(tok::l_paren, TT_TemplateOpener, tok::l_square) && + !IsStartOfBracedList()) { + return false; + } + if (!Tok.Previous) + return true; + if (Tok.Previous->isIf()) + return Style.AlignAfterOpenBracket == FormatStyle::BAS_AlwaysBreak; + return !Tok.Previous->isOneOf(TT_CastRParen, tok::kw_for, tok::kw_while, + tok::kw_switch); + }; if ((Style.AlignAfterOpenBracket == FormatStyle::BAS_AlwaysBreak || Style.AlignAfterOpenBracket == FormatStyle::BAS_BlockIndent) && - (Previous.isOneOf(tok::l_paren, TT_TemplateOpener, tok::l_square) || - (Previous.is(tok::l_brace) && Previous.isNot(BK_Block) && - Style.Cpp11BracedListStyle)) && - State.Column > getNewLineColumn(State) && - (!Previous.Previous || - !Previous.Previous->isOneOf(TT_CastRParen, tok::kw_for, tok::kw_while, - tok::kw_switch)) && + IsOpeningBracket(Previous) && State.Column > getNewLineColumn(State) && // Don't do this for simple (no expressions) one-argument function calls // as that feels like needlessly wasting whitespace, e.g.: // @@ -1591,6 +1604,9 @@ unsigned ContinuationIndenter::moveStateToNextToken(LineState &State, State.StartOfStringLiteral = State.Column + 1; if (Current.is(TT_CSharpStringLiteral) && State.StartOfStringLiteral == 0) { State.StartOfStringLiteral = State.Column + 1; + } else if (Current.is(TT_TableGenMultiLineString) && + State.StartOfStringLiteral == 0) { + State.StartOfStringLiteral = State.Column + 1; } else if (Current.isStringLiteral() && State.StartOfStringLiteral == 0) { State.StartOfStringLiteral = State.Column; } else if (!Current.isOneOf(tok::comment, tok::identifier, tok::hash) && diff --git a/clang/lib/Format/Format.cpp b/clang/lib/Format/Format.cpp index ff5ed6c306f..ff326dc7847 100644 --- a/clang/lib/Format/Format.cpp +++ b/clang/lib/Format/Format.cpp @@ -1054,6 +1054,8 @@ template <> struct MappingTraits { Style.PenaltyBreakFirstLessLess); IO.mapOptional("PenaltyBreakOpenParenthesis", Style.PenaltyBreakOpenParenthesis); + IO.mapOptional("PenaltyBreakScopeResolution", + Style.PenaltyBreakScopeResolution); IO.mapOptional("PenaltyBreakString", Style.PenaltyBreakString); IO.mapOptional("PenaltyBreakTemplateDeclaration", Style.PenaltyBreakTemplateDeclaration); @@ -1083,6 +1085,7 @@ template <> struct MappingTraits { Style.RequiresExpressionIndentation); IO.mapOptional("SeparateDefinitionBlocks", Style.SeparateDefinitionBlocks); IO.mapOptional("ShortNamespaceLines", Style.ShortNamespaceLines); + IO.mapOptional("SkipMacroDefinitionBody", Style.SkipMacroDefinitionBody); IO.mapOptional("SortIncludes", Style.SortIncludes); IO.mapOptional("SortJavaStaticImport", Style.SortJavaStaticImport); IO.mapOptional("SortUsingDeclarations", Style.SortUsingDeclarations); @@ -1554,6 +1557,7 @@ FormatStyle getLLVMStyle(FormatStyle::LanguageKind Language) { LLVMStyle.RequiresExpressionIndentation = FormatStyle::REI_OuterScope; LLVMStyle.SeparateDefinitionBlocks = FormatStyle::SDS_Leave; LLVMStyle.ShortNamespaceLines = 1; + LLVMStyle.SkipMacroDefinitionBody = false; LLVMStyle.SortIncludes = FormatStyle::SI_CaseSensitive; LLVMStyle.SortJavaStaticImport = FormatStyle::SJSIO_Before; LLVMStyle.SortUsingDeclarations = FormatStyle::SUD_LexicographicNumeric; @@ -1602,6 +1606,7 @@ FormatStyle getLLVMStyle(FormatStyle::LanguageKind Language) { LLVMStyle.PenaltyReturnTypeOnItsOwnLine = 60; LLVMStyle.PenaltyBreakBeforeFirstCallParameter = 19; LLVMStyle.PenaltyBreakOpenParenthesis = 0; + LLVMStyle.PenaltyBreakScopeResolution = 500; LLVMStyle.PenaltyBreakTemplateDeclaration = prec::Relational; LLVMStyle.PenaltyIndentedWhitespace = 0; @@ -1698,8 +1703,6 @@ FormatStyle getGoogleStyle(FormatStyle::LanguageKind Language) { /*BasedOnStyle=*/"google", }, }; - GoogleStyle.AttributeMacros.push_back("GUARDED_BY"); - GoogleStyle.AttributeMacros.push_back("ABSL_GUARDED_BY"); GoogleStyle.SpacesBeforeTrailingComments = 2; GoogleStyle.Standard = FormatStyle::LS_Auto; diff --git a/clang/lib/Format/FormatToken.h b/clang/lib/Format/FormatToken.h index 981592aa094..dede89f2600 100644 --- a/clang/lib/Format/FormatToken.h +++ b/clang/lib/Format/FormatToken.h @@ -148,6 +148,7 @@ namespace format { TYPE(StructLBrace) \ TYPE(StructRBrace) \ TYPE(StructuredBindingLSquare) \ + TYPE(TableGenMultiLineString) \ TYPE(TemplateCloser) \ TYPE(TemplateOpener) \ TYPE(TemplateString) \ @@ -1211,6 +1212,21 @@ struct AdditionalKeywords { kw_verilogHashHash = &IdentTable.get("##"); kw_apostrophe = &IdentTable.get("\'"); + // TableGen keywords + kw_bit = &IdentTable.get("bit"); + kw_bits = &IdentTable.get("bits"); + kw_code = &IdentTable.get("code"); + kw_dag = &IdentTable.get("dag"); + kw_def = &IdentTable.get("def"); + kw_defm = &IdentTable.get("defm"); + kw_defset = &IdentTable.get("defset"); + kw_defvar = &IdentTable.get("defvar"); + kw_dump = &IdentTable.get("dump"); + kw_include = &IdentTable.get("include"); + kw_list = &IdentTable.get("list"); + kw_multiclass = &IdentTable.get("multiclass"); + kw_then = &IdentTable.get("then"); + // Keep this at the end of the constructor to make sure everything here // is // already initialized. @@ -1303,6 +1319,27 @@ struct AdditionalKeywords { kw_wildcard, kw_wire, kw_with, kw_wor, kw_verilogHash, kw_verilogHashHash}); + + TableGenExtraKeywords = std::unordered_set({ + kw_assert, + kw_bit, + kw_bits, + kw_code, + kw_dag, + kw_def, + kw_defm, + kw_defset, + kw_defvar, + kw_dump, + kw_foreach, + kw_in, + kw_include, + kw_let, + kw_list, + kw_multiclass, + kw_string, + kw_then, + }); } // Context sensitive keywords. @@ -1548,6 +1585,21 @@ struct AdditionalKeywords { // Symbols in Verilog that don't exist in C++. IdentifierInfo *kw_apostrophe; + // TableGen keywords + IdentifierInfo *kw_bit; + IdentifierInfo *kw_bits; + IdentifierInfo *kw_code; + IdentifierInfo *kw_dag; + IdentifierInfo *kw_def; + IdentifierInfo *kw_defm; + IdentifierInfo *kw_defset; + IdentifierInfo *kw_defvar; + IdentifierInfo *kw_dump; + IdentifierInfo *kw_include; + IdentifierInfo *kw_list; + IdentifierInfo *kw_multiclass; + IdentifierInfo *kw_then; + /// Returns \c true if \p Tok is a keyword or an identifier. bool isWordLike(const FormatToken &Tok) const { // getIdentifierinfo returns non-null for keywords as well as identifiers. @@ -1820,6 +1872,27 @@ struct AdditionalKeywords { } } + bool isTableGenDefinition(const FormatToken &Tok) const { + return Tok.isOneOf(kw_def, kw_defm, kw_defset, kw_defvar, kw_multiclass, + kw_let, tok::kw_class); + } + + bool isTableGenKeyword(const FormatToken &Tok) const { + switch (Tok.Tok.getKind()) { + case tok::kw_class: + case tok::kw_else: + case tok::kw_false: + case tok::kw_if: + case tok::kw_int: + case tok::kw_true: + return true; + default: + return Tok.is(tok::identifier) && + TableGenExtraKeywords.find(Tok.Tok.getIdentifierInfo()) != + TableGenExtraKeywords.end(); + } + } + private: /// The JavaScript keywords beyond the C++ keyword set. std::unordered_set JsExtraKeywords; @@ -1829,6 +1902,9 @@ private: /// The Verilog keywords beyond the C++ keyword set. std::unordered_set VerilogExtraKeywords; + + /// The TableGen keywords beyond the C++ keyword set. + std::unordered_set TableGenExtraKeywords; }; inline bool isLineComment(const FormatToken &FormatTok) { diff --git a/clang/lib/Format/FormatTokenLexer.cpp b/clang/lib/Format/FormatTokenLexer.cpp index 61430282c6f..52a55ea23b5 100644 --- a/clang/lib/Format/FormatTokenLexer.cpp +++ b/clang/lib/Format/FormatTokenLexer.cpp @@ -93,6 +93,10 @@ ArrayRef FormatTokenLexer::lex() { // string literals are correctly identified. handleCSharpVerbatimAndInterpolatedStrings(); } + if (Style.isTableGen()) { + handleTableGenMultilineString(); + handleTableGenNumericLikeIdentifier(); + } if (Tokens.back()->NewlinesBefore > 0 || Tokens.back()->IsMultiline) FirstInLineIndex = Tokens.size() - 1; } while (Tokens.back()->isNot(tok::eof)); @@ -272,6 +276,14 @@ void FormatTokenLexer::tryMergePreviousTokens() { return; } } + // TableGen's Multi line string starts with [{ + if (Style.isTableGen() && tryMergeTokens({tok::l_square, tok::l_brace}, + TT_TableGenMultiLineString)) { + // Set again with finalizing. This must never be annotated as other types. + Tokens.back()->setFinalizedType(TT_TableGenMultiLineString); + Tokens.back()->Tok.setKind(tok::string_literal); + return; + } } bool FormatTokenLexer::tryMergeNSStringLiteral() { @@ -763,6 +775,75 @@ void FormatTokenLexer::handleCSharpVerbatimAndInterpolatedStrings() { resetLexer(SourceMgr.getFileOffset(Lex->getSourceLocation(Offset + 1))); } +void FormatTokenLexer::handleTableGenMultilineString() { + FormatToken *MultiLineString = Tokens.back(); + if (MultiLineString->isNot(TT_TableGenMultiLineString)) + return; + + auto OpenOffset = Lex->getCurrentBufferOffset() - 2 /* "[{" */; + // "}]" is the end of multi line string. + auto CloseOffset = Lex->getBuffer().find("}]", OpenOffset); + if (CloseOffset == StringRef::npos) + return; + auto Text = Lex->getBuffer().substr(OpenOffset, CloseOffset + 2); + MultiLineString->TokenText = Text; + resetLexer(SourceMgr.getFileOffset( + Lex->getSourceLocation(Lex->getBufferLocation() - 2 + Text.size()))); + auto FirstLineText = Text; + auto FirstBreak = Text.find('\n'); + // Set ColumnWidth and LastLineColumnWidth when it has multiple lines. + if (FirstBreak != StringRef::npos) { + MultiLineString->IsMultiline = true; + FirstLineText = Text.substr(0, FirstBreak + 1); + // LastLineColumnWidth holds the width of the last line. + auto LastBreak = Text.rfind('\n'); + MultiLineString->LastLineColumnWidth = encoding::columnWidthWithTabs( + Text.substr(LastBreak + 1), MultiLineString->OriginalColumn, + Style.TabWidth, Encoding); + } + // ColumnWidth holds only the width of the first line. + MultiLineString->ColumnWidth = encoding::columnWidthWithTabs( + FirstLineText, MultiLineString->OriginalColumn, Style.TabWidth, Encoding); +} + +void FormatTokenLexer::handleTableGenNumericLikeIdentifier() { + FormatToken *Tok = Tokens.back(); + // TableGen identifiers can begin with digits. Such tokens are lexed as + // numeric_constant now. + if (Tok->isNot(tok::numeric_constant)) + return; + StringRef Text = Tok->TokenText; + // The following check is based on llvm::TGLexer::LexToken. + // That lexes the token as a number if any of the following holds: + // 1. It starts with '+', '-'. + // 2. All the characters are digits. + // 3. The first non-digit character is 'b', and the next is '0' or '1'. + // 4. The first non-digit character is 'x', and the next is a hex digit. + // Note that in the case 3 and 4, if the next character does not exists in + // this token, the token is an identifier. + if (Text.size() < 1 || Text[0] == '+' || Text[0] == '-') + return; + const auto NonDigitPos = Text.find_if([](char C) { return !isdigit(C); }); + // All the characters are digits + if (NonDigitPos == StringRef::npos) + return; + char FirstNonDigit = Text[NonDigitPos]; + if (NonDigitPos < Text.size() - 1) { + char TheNext = Text[NonDigitPos + 1]; + // Regarded as a binary number. + if (FirstNonDigit == 'b' && (TheNext == '0' || TheNext == '1')) + return; + // Regarded as hex number. + if (FirstNonDigit == 'x' && isxdigit(TheNext)) + return; + } + if (isalpha(FirstNonDigit) || FirstNonDigit == '_') { + // This is actually an identifier in TableGen. + Tok->Tok.setKind(tok::identifier); + Tok->Tok.setIdentifierInfo(nullptr); + } +} + void FormatTokenLexer::handleTemplateStrings() { FormatToken *BacktickToken = Tokens.back(); @@ -1182,6 +1263,9 @@ FormatToken *FormatTokenLexer::getNextToken() { tok::kw_operator)) { FormatTok->Tok.setKind(tok::identifier); FormatTok->Tok.setIdentifierInfo(nullptr); + } else if (Style.isTableGen() && !Keywords.isTableGenKeyword(*FormatTok)) { + FormatTok->Tok.setKind(tok::identifier); + FormatTok->Tok.setIdentifierInfo(nullptr); } } else if (FormatTok->is(tok::greatergreater)) { FormatTok->Tok.setKind(tok::greater); diff --git a/clang/lib/Format/FormatTokenLexer.h b/clang/lib/Format/FormatTokenLexer.h index bb6a8ab69c1..65dd733bd53 100644 --- a/clang/lib/Format/FormatTokenLexer.h +++ b/clang/lib/Format/FormatTokenLexer.h @@ -95,6 +95,13 @@ private: void handleCSharpVerbatimAndInterpolatedStrings(); + // Handles TableGen multiline strings. It has the form [{ ... }]. + void handleTableGenMultilineString(); + // Handles TableGen numeric like identifiers. + // They have a forms of [0-9]*[_a-zA-Z]([_a-zA-Z0-9]*). But limited to the + // case it is not lexed as an integer. + void handleTableGenNumericLikeIdentifier(); + void tryParsePythonComment(); bool tryMerge_TMacro(); diff --git a/clang/lib/Format/TokenAnnotator.cpp b/clang/lib/Format/TokenAnnotator.cpp index 227aa0b97af..25fcceb8786 100644 --- a/clang/lib/Format/TokenAnnotator.cpp +++ b/clang/lib/Format/TokenAnnotator.cpp @@ -2209,7 +2209,8 @@ private: (!NextNonComment && !Line.InMacroBody) || (NextNonComment && (NextNonComment->isPointerOrReference() || - NextNonComment->isOneOf(tok::identifier, tok::string_literal)))) { + NextNonComment->is(tok::string_literal) || + (Line.InPragmaDirective && NextNonComment->is(tok::identifier))))) { return false; } @@ -2234,6 +2235,12 @@ private: if (PreviousNotConst->ClosesRequiresClause) return false; + if (Style.isTableGen()) { + // keywords such as let and def* defines names. + if (Keywords.isTableGenDefinition(*PreviousNotConst)) + return true; + } + bool IsPPKeyword = PreviousNotConst->is(tok::identifier) && PreviousNotConst->Previous && PreviousNotConst->Previous->is(tok::hash); @@ -2369,7 +2376,7 @@ private: } } - if (Tok.Next->is(tok::question)) + if (Tok.Next->isOneOf(tok::question, tok::ampamp)) return false; // `foreach((A a, B b) in someList)` should not be seen as a cast. @@ -3759,7 +3766,7 @@ unsigned TokenAnnotator::splitPenalty(const AnnotatedLine &Line, } if (Left.is(tok::coloncolon)) - return 500; + return Style.PenaltyBreakScopeResolution; if (Right.isOneOf(TT_StartOfName, TT_FunctionDeclarationName) || Right.is(tok::kw_operator)) { if (Line.startsWith(tok::kw_for) && Right.PartOfMultiVariableDeclStmt) @@ -4668,6 +4675,10 @@ bool TokenAnnotator::spaceRequiredBefore(const AnnotatedLine &Line, } else if (Style.Language == FormatStyle::LK_Java) { if (Left.is(tok::r_square) && Right.is(tok::l_brace)) return true; + // spaces inside square brackets. + if (Left.is(tok::l_square) || Right.is(tok::r_square)) + return Style.SpacesInSquareBrackets; + if (Left.is(Keywords.kw_synchronized) && Right.is(tok::l_paren)) { return Style.SpaceBeforeParensOptions.AfterControlStatements || spaceRequiredBeforeParens(Right); diff --git a/clang/lib/Format/UnwrappedLineFormatter.cpp b/clang/lib/Format/UnwrappedLineFormatter.cpp index 27983a330ac..adeb0724348 100644 --- a/clang/lib/Format/UnwrappedLineFormatter.cpp +++ b/clang/lib/Format/UnwrappedLineFormatter.cpp @@ -95,7 +95,7 @@ public: /// level to the same indent. /// Note that \c nextLine must have been called before this method. void adjustToUnmodifiedLine(const AnnotatedLine &Line) { - if (Line.InPPDirective) + if (Line.InPPDirective || Line.IsContinuation) return; assert(Line.Level < IndentForLevel.size()); if (Line.First->is(tok::comment) && IndentForLevel[Line.Level] != -1) diff --git a/clang/lib/Format/UnwrappedLineParser.cpp b/clang/lib/Format/UnwrappedLineParser.cpp index 50d41c9f57a..b904e0e56d9 100644 --- a/clang/lib/Format/UnwrappedLineParser.cpp +++ b/clang/lib/Format/UnwrappedLineParser.cpp @@ -1170,6 +1170,15 @@ void UnwrappedLineParser::parsePPDefine() { assert((int)Line->PPLevel >= 0); Line->InMacroBody = true; + if (Style.SkipMacroDefinitionBody) { + do { + FormatTok->Finalized = true; + nextToken(); + } while (!eof()); + addUnwrappedLine(); + return; + } + if (FormatTok->is(tok::identifier) && Tokens->peekNextToken()->is(tok::colon)) { nextToken(); @@ -1652,7 +1661,8 @@ void UnwrappedLineParser::parseStructuralElement( // In Verilog labels can be any expression, so we don't do them here. // JS doesn't have macros, and within classes colons indicate fields, not // labels. - if (!Style.isJavaScript() && !Style.isVerilog() && + // TableGen doesn't have labels. + if (!Style.isJavaScript() && !Style.isVerilog() && !Style.isTableGen() && Tokens->peekNextToken()->is(tok::colon) && !Line->MustBeDeclaration) { nextToken(); Line->Tokens.begin()->Tok->MustBreakBefore = true; @@ -1781,6 +1791,12 @@ void UnwrappedLineParser::parseStructuralElement( addUnwrappedLine(); return; } + if (Style.isTableGen()) { + // Do nothing special. In this case the l_brace becomes FunctionLBrace. + // This is same as def and so on. + nextToken(); + break; + } [[fallthrough]]; case tok::kw_struct: case tok::kw_union: @@ -2019,6 +2035,16 @@ void UnwrappedLineParser::parseStructuralElement( // initialisers are indented the same way. if (Style.isCSharp()) FormatTok->setBlockKind(BK_BracedInit); + // TableGen's defset statement has syntax of the form, + // `defset = { ... }` + if (Style.isTableGen() && + Line->Tokens.begin()->Tok->is(Keywords.kw_defset)) { + FormatTok->setFinalizedType(TT_FunctionLBrace); + parseBlock(/*MustBeDeclaration=*/false, /*AddLevels=*/1u, + /*MunchSemi=*/false); + addUnwrappedLine(); + break; + } nextToken(); parseBracedList(); } else if (Style.Language == FormatStyle::LK_Proto && @@ -2734,6 +2760,14 @@ FormatToken *UnwrappedLineParser::parseIfThenElse(IfStmtKind *IfKind, } } + // TableGen's if statement has the form of `if then { ... }`. + if (Style.isTableGen()) { + while (!eof() && FormatTok->isNot(Keywords.kw_then)) { + // Simply skip until then. This range only contains a value. + nextToken(); + } + } + // Handle `if !consteval`. if (FormatTok->is(tok::exclaim)) nextToken(); @@ -3873,6 +3907,9 @@ void UnwrappedLineParser::parseRecord(bool ParseAsExpr) { const FormatToken &InitialToken = *FormatTok; nextToken(); + auto IsNonMacroIdentifier = [](const FormatToken *Tok) { + return Tok->is(tok::identifier) && Tok->TokenText != Tok->TokenText.upper(); + }; // The actual identifier can be a nested name specifier, and in macros // it is often token-pasted. // An [[attribute]] can be before the identifier. @@ -3894,27 +3931,26 @@ void UnwrappedLineParser::parseRecord(bool ParseAsExpr) { } if (FormatTok->is(tok::l_square) && handleCppAttributes()) continue; - bool IsNonMacroIdentifier = - FormatTok->is(tok::identifier) && - FormatTok->TokenText != FormatTok->TokenText.upper(); nextToken(); // We can have macros in between 'class' and the class name. - if (!IsNonMacroIdentifier && FormatTok->is(tok::l_paren)) + if (!IsNonMacroIdentifier(FormatTok->Previous) && + FormatTok->is(tok::l_paren)) { parseParens(); + } } - // Note that parsing away template declarations here leads to incorrectly - // accepting function declarations as record declarations. - // In general, we cannot solve this problem. Consider: - // class A B() {} - // which can be a function definition or a class definition when B() is a - // macro. If we find enough real-world cases where this is a problem, we - // can parse for the 'template' keyword in the beginning of the statement, - // and thus rule out the record production in case there is no template - // (this would still leave us with an ambiguity between template function - // and class declarations). if (FormatTok->isOneOf(tok::colon, tok::less)) { + int AngleNestingLevel = 0; do { + if (FormatTok->is(tok::less)) + ++AngleNestingLevel; + else if (FormatTok->is(tok::greater)) + --AngleNestingLevel; + + if (AngleNestingLevel == 0 && FormatTok->is(tok::l_paren) && + IsNonMacroIdentifier(FormatTok->Previous)) { + break; + } if (FormatTok->is(tok::l_brace)) { calculateBraceTypes(/*ExpectClassBody=*/true); if (!tryToParseBracedList()) diff --git a/clang/lib/Format/WhitespaceManager.cpp b/clang/lib/Format/WhitespaceManager.cpp index f1d176f182f..df84f97a8e8 100644 --- a/clang/lib/Format/WhitespaceManager.cpp +++ b/clang/lib/Format/WhitespaceManager.cpp @@ -1366,11 +1366,12 @@ void WhitespaceManager::alignArrayInitializersLeftJustified( auto &Cells = CellDescs.Cells; // Now go through and fixup the spaces. auto *CellIter = Cells.begin(); - // The first cell needs to be against the left brace. - if (Changes[CellIter->Index].NewlinesBefore == 0) - Changes[CellIter->Index].Spaces = BracePadding; - else - Changes[CellIter->Index].Spaces = CellDescs.InitialSpaces; + // The first cell of every row needs to be against the left brace. + for (const auto *Next = CellIter; Next; Next = Next->NextColumnElement) { + auto &Change = Changes[Next->Index]; + Change.Spaces = + Change.NewlinesBefore == 0 ? BracePadding : CellDescs.InitialSpaces; + } ++CellIter; for (auto i = 1U; i < CellDescs.CellCounts[0]; i++, ++CellIter) { auto MaxNetWidth = getMaximumNetWidth( @@ -1451,8 +1452,10 @@ WhitespaceManager::CellDescriptions WhitespaceManager::getCells(unsigned Start, } else if (C.Tok->is(tok::comma)) { if (!Cells.empty()) Cells.back().EndIndex = i; - if (C.Tok->getNextNonComment()->isNot(tok::r_brace)) // dangling comma + if (const auto *Next = C.Tok->getNextNonComment(); + Next && Next->isNot(tok::r_brace)) { // dangling comma ++Cell; + } } } else if (Depth == 1) { if (C.Tok == MatchingParen) { diff --git a/clang/lib/Format/WhitespaceManager.h b/clang/lib/Format/WhitespaceManager.h index dc6f60e5dee..8ac73305871 100644 --- a/clang/lib/Format/WhitespaceManager.h +++ b/clang/lib/Format/WhitespaceManager.h @@ -55,7 +55,7 @@ public: /// this replacement. It is needed for determining how \p Spaces is turned /// into tabs and spaces for some format styles. void replaceWhitespace(FormatToken &Tok, unsigned Newlines, unsigned Spaces, - unsigned StartOfTokenColumn, bool isAligned = false, + unsigned StartOfTokenColumn, bool IsAligned = false, bool InPPDirective = false); /// Adds information about an unchangeable token's whitespace. diff --git a/clang/lib/Frontend/CompilerInstance.cpp b/clang/lib/Frontend/CompilerInstance.cpp index 56bbef9697b..a25aa88bd85 100644 --- a/clang/lib/Frontend/CompilerInstance.cpp +++ b/clang/lib/Frontend/CompilerInstance.cpp @@ -470,7 +470,7 @@ void CompilerInstance::createPreprocessor(TranslationUnitKind TUKind) { // Predefine macros and configure the preprocessor. InitializePreprocessor(*PP, PPOpts, getPCHContainerReader(), - getFrontendOpts()); + getFrontendOpts(), getCodeGenOpts()); // Initialize the header search object. In CUDA compilations, we use the aux // triple (the host triple) to initialize our header search, since we need to @@ -543,7 +543,7 @@ std::string CompilerInstance::getSpecificModuleCachePath(StringRef ModuleHash) { SmallString<256> SpecificModuleCache(getHeaderSearchOpts().ModuleCachePath); if (!SpecificModuleCache.empty() && !getHeaderSearchOpts().DisableModuleHash) llvm::sys::path::append(SpecificModuleCache, ModuleHash); - return std::string(SpecificModuleCache.str()); + return std::string(SpecificModuleCache); } // ASTContext @@ -2204,7 +2204,7 @@ void CompilerInstance::createModuleFromSource(SourceLocation ImportLoc, // Build the module, inheriting any modules that we've built locally. if (compileModuleImpl(*this, ImportLoc, ModuleName, Input, StringRef(), ModuleFileName, PreBuildStep, PostBuildStep)) { - BuiltModules[std::string(ModuleName)] = std::string(ModuleFileName.str()); + BuiltModules[std::string(ModuleName)] = std::string(ModuleFileName); llvm::sys::RemoveFileOnSignal(ModuleFileName); } } diff --git a/clang/lib/Frontend/CompilerInvocation.cpp b/clang/lib/Frontend/CompilerInvocation.cpp index 11f3f2c2d64..feb4de2084b 100644 --- a/clang/lib/Frontend/CompilerInvocation.cpp +++ b/clang/lib/Frontend/CompilerInvocation.cpp @@ -1861,20 +1861,6 @@ bool CompilerInvocation::ParseCodeGenArgs(CodeGenOptions &Opts, ArgList &Args, if (Args.hasArg(OPT_funified_lto)) Opts.PrepareForThinLTO = true; } - if (Arg *A = Args.getLastArg(options::OPT_ffat_lto_objects, - options::OPT_fno_fat_lto_objects)) { - if (A->getOption().matches(options::OPT_ffat_lto_objects)) { - if (Arg *Uni = Args.getLastArg(options::OPT_funified_lto, - options::OPT_fno_unified_lto)) { - if (Uni->getOption().matches(options::OPT_fno_unified_lto)) - Diags.Report(diag::err_drv_incompatible_options) - << A->getAsString(Args) << "-fno-unified-lto"; - } else - Diags.Report(diag::err_drv_argument_only_allowed_with) - << A->getAsString(Args) << "-funified-lto"; - } - } - if (Arg *A = Args.getLastArg(OPT_fthinlto_index_EQ)) { if (IK.getLanguage() != Language::LLVM_IR) Diags.Report(diag::err_drv_argument_only_allowed_with) @@ -3176,7 +3162,7 @@ static bool ParseHeaderSearchArgs(HeaderSearchOptions &Opts, ArgList &Args, llvm::sys::fs::make_absolute(WorkingDir, P); } llvm::sys::path::remove_dots(P); - Opts.ModuleCachePath = std::string(P.str()); + Opts.ModuleCachePath = std::string(P); // Only the -fmodule-file== form. for (const auto *A : Args.filtered(OPT_fmodule_file)) { @@ -3217,7 +3203,7 @@ static bool ParseHeaderSearchArgs(HeaderSearchOptions &Opts, ArgList &Args, SmallString<32> Buffer; llvm::sys::path::append(Buffer, Opts.Sysroot, llvm::StringRef(A->getValue()).substr(1)); - Path = std::string(Buffer.str()); + Path = std::string(Buffer); } Opts.AddPath(Path, Group, IsFramework, @@ -3480,7 +3466,8 @@ void CompilerInvocationBase::GenerateLangArgs(const LangOptions &Opts, Twine(Major) + "." + Twine(Minor) + "." + Twine(Subminor)); } - if ((!Opts.GNUMode && !Opts.MSVCCompat && !Opts.CPlusPlus17) || T.isOSzOS()) { + if ((!Opts.GNUMode && !Opts.MSVCCompat && !Opts.CPlusPlus17 && !Opts.C23) || + T.isOSzOS()) { if (!Opts.Trigraphs) GenerateArg(Consumer, OPT_fno_trigraphs); } else { @@ -3876,10 +3863,11 @@ bool CompilerInvocation::ParseLangArgs(LangOptions &Opts, ArgList &Args, // Mimicking gcc's behavior, trigraphs are only enabled if -trigraphs // is specified, or -std is set to a conforming mode. - // Trigraphs are disabled by default in c++1z onwards. + // Trigraphs are disabled by default in C++17 and C23 onwards. // For z/OS, trigraphs are enabled by default (without regard to the above). Opts.Trigraphs = - (!Opts.GNUMode && !Opts.MSVCCompat && !Opts.CPlusPlus17) || T.isOSzOS(); + (!Opts.GNUMode && !Opts.MSVCCompat && !Opts.CPlusPlus17 && !Opts.C23) || + T.isOSzOS(); Opts.Trigraphs = Args.hasFlag(OPT_ftrigraphs, OPT_fno_trigraphs, Opts.Trigraphs); @@ -4236,20 +4224,35 @@ bool CompilerInvocation::ParseLangArgs(LangOptions &Opts, ArgList &Args, // TODO: Revisit restricting SPIR-V to logical once we've figured out how to // handle PhysicalStorageBuffer64 memory model if (T.isDXIL() || T.isSPIRVLogical()) { - enum { ShaderModel, ShaderStage }; + enum { ShaderModel, VulkanEnv, ShaderStage }; + enum { OS, Environment }; + + int ExpectedOS = T.isSPIRVLogical() ? VulkanEnv : ShaderModel; + if (T.getOSName().empty()) { Diags.Report(diag::err_drv_hlsl_bad_shader_required_in_target) - << ShaderModel << T.str(); - } else if (!T.isShaderModelOS() || T.getOSVersion() == VersionTuple(0)) { - Diags.Report(diag::err_drv_hlsl_bad_shader_unsupported) - << ShaderModel << T.getOSName() << T.str(); + << ExpectedOS << OS << T.str(); } else if (T.getEnvironmentName().empty()) { Diags.Report(diag::err_drv_hlsl_bad_shader_required_in_target) - << ShaderStage << T.str(); + << ShaderStage << Environment << T.str(); } else if (!T.isShaderStageEnvironment()) { Diags.Report(diag::err_drv_hlsl_bad_shader_unsupported) << ShaderStage << T.getEnvironmentName() << T.str(); } + + if (T.isDXIL()) { + if (!T.isShaderModelOS() || T.getOSVersion() == VersionTuple(0)) { + Diags.Report(diag::err_drv_hlsl_bad_shader_unsupported) + << ShaderModel << T.getOSName() << T.str(); + } + } else if (T.isSPIRVLogical()) { + if (!T.isVulkanOS() || T.getVulkanVersion() == VersionTuple(0)) { + Diags.Report(diag::err_drv_hlsl_bad_shader_unsupported) + << VulkanEnv << T.getOSName() << T.str(); + } + } else { + llvm_unreachable("expected DXIL or SPIR-V target"); + } } else Diags.Report(diag::err_drv_hlsl_unsupported_target) << T.str(); } diff --git a/clang/lib/Frontend/InitPreprocessor.cpp b/clang/lib/Frontend/InitPreprocessor.cpp index d83128adb51..1b91c86f913 100644 --- a/clang/lib/Frontend/InitPreprocessor.cpp +++ b/clang/lib/Frontend/InitPreprocessor.cpp @@ -728,6 +728,7 @@ static void InitializeCPlusPlusFeatureTestMacros(const LangOptions &LangOpts, Builder.defineMacro("__cpp_size_t_suffix", "202011L"); Builder.defineMacro("__cpp_if_consteval", "202106L"); Builder.defineMacro("__cpp_multidimensional_subscript", "202211L"); + Builder.defineMacro("__cpp_auto_cast", "202110L"); } // We provide those C++23 features as extensions in earlier language modes, so @@ -1364,12 +1365,22 @@ static void InitializePredefinedMacros(const TargetInfo &TI, TI.getTargetDefines(LangOpts, Builder); } +static void InitializePGOProfileMacros(const CodeGenOptions &CodeGenOpts, + MacroBuilder &Builder) { + if (CodeGenOpts.hasProfileInstr()) + Builder.defineMacro("__LLVM_INSTR_PROFILE_GENERATE"); + + if (CodeGenOpts.hasProfileIRUse() || CodeGenOpts.hasProfileClangUse()) + Builder.defineMacro("__LLVM_INSTR_PROFILE_USE"); +} + /// InitializePreprocessor - Initialize the preprocessor getting it and the /// environment ready to process a single file. -void clang::InitializePreprocessor( - Preprocessor &PP, const PreprocessorOptions &InitOpts, - const PCHContainerReader &PCHContainerRdr, - const FrontendOptions &FEOpts) { +void clang::InitializePreprocessor(Preprocessor &PP, + const PreprocessorOptions &InitOpts, + const PCHContainerReader &PCHContainerRdr, + const FrontendOptions &FEOpts, + const CodeGenOptions &CodeGenOpts) { const LangOptions &LangOpts = PP.getLangOpts(); std::string PredefineBuffer; PredefineBuffer.reserve(4080); @@ -1416,6 +1427,11 @@ void clang::InitializePreprocessor( InitializeStandardPredefinedMacros(PP.getTargetInfo(), PP.getLangOpts(), FEOpts, Builder); + // The PGO instrumentation profile macros are driven by options + // -fprofile[-instr]-generate/-fcs-profile-generate/-fprofile[-instr]-use, + // hence they are not guarded by InitOpts.UsePredefines. + InitializePGOProfileMacros(CodeGenOpts, Builder); + // Add on the predefines from the driver. Wrap in a #line directive to report // that they come from the command line. Builder.append("# 1 \"\" 1"); diff --git a/clang/lib/Frontend/LogDiagnosticPrinter.cpp b/clang/lib/Frontend/LogDiagnosticPrinter.cpp index 32fc6cb2acd..469d1c22633 100644 --- a/clang/lib/Frontend/LogDiagnosticPrinter.cpp +++ b/clang/lib/Frontend/LogDiagnosticPrinter.cpp @@ -134,7 +134,7 @@ void LogDiagnosticPrinter::HandleDiagnostic(DiagnosticsEngine::Level Level, // Format the message. SmallString<100> MessageStr; Info.FormatDiagnostic(MessageStr); - DE.Message = std::string(MessageStr.str()); + DE.Message = std::string(MessageStr); // Set the location information. DE.Filename = ""; diff --git a/clang/lib/Frontend/Rewrite/FrontendActions.cpp b/clang/lib/Frontend/Rewrite/FrontendActions.cpp index 14569013b92..cf5a9437e89 100644 --- a/clang/lib/Frontend/Rewrite/FrontendActions.cpp +++ b/clang/lib/Frontend/Rewrite/FrontendActions.cpp @@ -77,7 +77,7 @@ public: SmallString<128> Path(Filename); llvm::sys::path::replace_extension(Path, NewSuffix + llvm::sys::path::extension(Path)); - return std::string(Path.str()); + return std::string(Path); } }; @@ -88,7 +88,7 @@ public: llvm::sys::fs::createTemporaryFile(llvm::sys::path::filename(Filename), llvm::sys::path::extension(Filename).drop_front(), fd, Path); - return std::string(Path.str()); + return std::string(Path); } }; } // end anonymous namespace diff --git a/clang/lib/Frontend/TextDiagnosticBuffer.cpp b/clang/lib/Frontend/TextDiagnosticBuffer.cpp index 90f273e65f8..681bc25f46b 100644 --- a/clang/lib/Frontend/TextDiagnosticBuffer.cpp +++ b/clang/lib/Frontend/TextDiagnosticBuffer.cpp @@ -32,20 +32,20 @@ void TextDiagnosticBuffer::HandleDiagnostic(DiagnosticsEngine::Level Level, "Diagnostic not handled during diagnostic buffering!"); case DiagnosticsEngine::Note: All.emplace_back(Level, Notes.size()); - Notes.emplace_back(Info.getLocation(), std::string(Buf.str())); + Notes.emplace_back(Info.getLocation(), std::string(Buf)); break; case DiagnosticsEngine::Warning: All.emplace_back(Level, Warnings.size()); - Warnings.emplace_back(Info.getLocation(), std::string(Buf.str())); + Warnings.emplace_back(Info.getLocation(), std::string(Buf)); break; case DiagnosticsEngine::Remark: All.emplace_back(Level, Remarks.size()); - Remarks.emplace_back(Info.getLocation(), std::string(Buf.str())); + Remarks.emplace_back(Info.getLocation(), std::string(Buf)); break; case DiagnosticsEngine::Error: case DiagnosticsEngine::Fatal: All.emplace_back(Level, Errors.size()); - Errors.emplace_back(Info.getLocation(), std::string(Buf.str())); + Errors.emplace_back(Info.getLocation(), std::string(Buf)); break; } } diff --git a/clang/lib/Headers/arm_acle.h b/clang/lib/Headers/arm_acle.h index 9aae2285aeb..9cd34948e3c 100644 --- a/clang/lib/Headers/arm_acle.h +++ b/clang/lib/Headers/arm_acle.h @@ -4,6 +4,13 @@ * See https://llvm.org/LICENSE.txt for license information. * SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception * + * The Arm C Language Extensions specifications can be found in the following + * link: https://github.com/ARM-software/acle/releases + * + * The ACLE section numbers are subject to change. When consulting the + * specifications, it is recommended to search using section titles if + * the section numbers look outdated. + * *===-----------------------------------------------------------------------=== */ @@ -20,8 +27,8 @@ extern "C" { #endif -/* 8 SYNCHRONIZATION, BARRIER AND HINT INTRINSICS */ -/* 8.3 Memory barriers */ +/* 7 SYNCHRONIZATION, BARRIER AND HINT INTRINSICS */ +/* 7.3 Memory barriers */ #if !__has_builtin(__dmb) #define __dmb(i) __builtin_arm_dmb(i) #endif @@ -32,7 +39,7 @@ extern "C" { #define __isb(i) __builtin_arm_isb(i) #endif -/* 8.4 Hints */ +/* 7.4 Hints */ #if !__has_builtin(__wfi) static __inline__ void __attribute__((__always_inline__, __nodebug__)) __wfi(void) { @@ -68,7 +75,7 @@ static __inline__ void __attribute__((__always_inline__, __nodebug__)) __yield(v #define __dbg(t) __builtin_arm_dbg(t) #endif -/* 8.5 Swap */ +/* 7.5 Swap */ static __inline__ uint32_t __attribute__((__always_inline__, __nodebug__)) __swp(uint32_t __x, volatile uint32_t *__p) { uint32_t v; @@ -78,8 +85,8 @@ __swp(uint32_t __x, volatile uint32_t *__p) { return v; } -/* 8.6 Memory prefetch intrinsics */ -/* 8.6.1 Data prefetch */ +/* 7.6 Memory prefetch intrinsics */ +/* 7.6.1 Data prefetch */ #define __pld(addr) __pldx(0, 0, 0, addr) #if defined(__ARM_32BIT_STATE) && __ARM_32BIT_STATE @@ -90,7 +97,7 @@ __swp(uint32_t __x, volatile uint32_t *__p) { __builtin_arm_prefetch(addr, access_kind, cache_level, retention_policy, 1) #endif -/* 8.6.2 Instruction prefetch */ +/* 7.6.2 Instruction prefetch */ #define __pli(addr) __plix(0, 0, addr) #if defined(__ARM_32BIT_STATE) && __ARM_32BIT_STATE @@ -101,15 +108,15 @@ __swp(uint32_t __x, volatile uint32_t *__p) { __builtin_arm_prefetch(addr, 0, cache_level, retention_policy, 0) #endif -/* 8.7 NOP */ +/* 7.7 NOP */ #if !defined(_MSC_VER) || !defined(__aarch64__) static __inline__ void __attribute__((__always_inline__, __nodebug__)) __nop(void) { __builtin_arm_nop(); } #endif -/* 9 DATA-PROCESSING INTRINSICS */ -/* 9.2 Miscellaneous data-processing intrinsics */ +/* 8 DATA-PROCESSING INTRINSICS */ +/* 8.2 Miscellaneous data-processing intrinsics */ /* ROR */ static __inline__ uint32_t __attribute__((__always_inline__, __nodebug__)) __ror(uint32_t __x, uint32_t __y) { @@ -248,9 +255,7 @@ __rbitl(unsigned long __t) { #endif } -/* - * 9.3 16-bit multiplications - */ +/* 8.3 16-bit multiplications */ #if defined(__ARM_FEATURE_DSP) && __ARM_FEATURE_DSP static __inline__ int32_t __attribute__((__always_inline__,__nodebug__)) __smulbb(int32_t __a, int32_t __b) { @@ -279,18 +284,18 @@ __smulwt(int32_t __a, int32_t __b) { #endif /* - * 9.4 Saturating intrinsics + * 8.4 Saturating intrinsics * * FIXME: Change guard to their corresponding __ARM_FEATURE flag when Q flag * intrinsics are implemented and the flag is enabled. */ -/* 9.4.1 Width-specified saturation intrinsics */ +/* 8.4.1 Width-specified saturation intrinsics */ #if defined(__ARM_FEATURE_SAT) && __ARM_FEATURE_SAT #define __ssat(x, y) __builtin_arm_ssat(x, y) #define __usat(x, y) __builtin_arm_usat(x, y) #endif -/* 9.4.2 Saturating addition and subtraction intrinsics */ +/* 8.4.2 Saturating addition and subtraction intrinsics */ #if defined(__ARM_FEATURE_DSP) && __ARM_FEATURE_DSP static __inline__ int32_t __attribute__((__always_inline__, __nodebug__)) __qadd(int32_t __t, int32_t __v) { @@ -308,7 +313,7 @@ __qdbl(int32_t __t) { } #endif -/* 9.4.3 Accumultating multiplications */ +/* 8.4.3 Accumultating multiplications */ #if defined(__ARM_FEATURE_DSP) && __ARM_FEATURE_DSP static __inline__ int32_t __attribute__((__always_inline__, __nodebug__)) __smlabb(int32_t __a, int32_t __b, int32_t __c) { @@ -337,13 +342,13 @@ __smlawt(int32_t __a, int32_t __b, int32_t __c) { #endif -/* 9.5.4 Parallel 16-bit saturation */ +/* 8.5.4 Parallel 16-bit saturation */ #if defined(__ARM_FEATURE_SIMD32) && __ARM_FEATURE_SIMD32 #define __ssat16(x, y) __builtin_arm_ssat16(x, y) #define __usat16(x, y) __builtin_arm_usat16(x, y) #endif -/* 9.5.5 Packing and unpacking */ +/* 8.5.5 Packing and unpacking */ #if defined(__ARM_FEATURE_SIMD32) && __ARM_FEATURE_SIMD32 typedef int32_t int8x4_t; typedef int32_t int16x2_t; @@ -368,7 +373,7 @@ __uxtb16(int8x4_t __a) { } #endif -/* 9.5.6 Parallel selection */ +/* 8.5.6 Parallel selection */ #if defined(__ARM_FEATURE_SIMD32) && __ARM_FEATURE_SIMD32 static __inline__ uint8x4_t __attribute__((__always_inline__, __nodebug__)) __sel(uint8x4_t __a, uint8x4_t __b) { @@ -376,7 +381,7 @@ __sel(uint8x4_t __a, uint8x4_t __b) { } #endif -/* 9.5.7 Parallel 8-bit addition and subtraction */ +/* 8.5.7 Parallel 8-bit addition and subtraction */ #if defined(__ARM_FEATURE_SIMD32) && __ARM_FEATURE_SIMD32 static __inline__ int8x4_t __attribute__((__always_inline__, __nodebug__)) __qadd8(int8x4_t __a, int8x4_t __b) { @@ -428,7 +433,7 @@ __usub8(uint8x4_t __a, uint8x4_t __b) { } #endif -/* 9.5.8 Sum of 8-bit absolute differences */ +/* 8.5.8 Sum of 8-bit absolute differences */ #if defined(__ARM_FEATURE_SIMD32) && __ARM_FEATURE_SIMD32 static __inline__ uint32_t __attribute__((__always_inline__, __nodebug__)) __usad8(uint8x4_t __a, uint8x4_t __b) { @@ -440,7 +445,7 @@ __usada8(uint8x4_t __a, uint8x4_t __b, uint32_t __c) { } #endif -/* 9.5.9 Parallel 16-bit addition and subtraction */ +/* 8.5.9 Parallel 16-bit addition and subtraction */ #if defined(__ARM_FEATURE_SIMD32) && __ARM_FEATURE_SIMD32 static __inline__ int16x2_t __attribute__((__always_inline__, __nodebug__)) __qadd16(int16x2_t __a, int16x2_t __b) { @@ -540,7 +545,7 @@ __usub16(uint16x2_t __a, uint16x2_t __b) { } #endif -/* 9.5.10 Parallel 16-bit multiplications */ +/* 8.5.10 Parallel 16-bit multiplications */ #if defined(__ARM_FEATURE_SIMD32) && __ARM_FEATURE_SIMD32 static __inline__ int32_t __attribute__((__always_inline__, __nodebug__)) __smlad(int16x2_t __a, int16x2_t __b, int32_t __c) { @@ -607,7 +612,7 @@ __rintnf(float __a) { } #endif -/* 9.7 CRC32 intrinsics */ +/* 8.8 CRC32 intrinsics */ #if (defined(__ARM_FEATURE_CRC32) && __ARM_FEATURE_CRC32) || \ (defined(__ARM_64BIT_STATE) && __ARM_64BIT_STATE) static __inline__ uint32_t __attribute__((__always_inline__, __nodebug__, target("crc"))) @@ -651,6 +656,7 @@ __crc32cd(uint32_t __a, uint64_t __b) { } #endif +/* 8.6 Floating-point data-processing intrinsics */ /* Armv8.3-A Javascript conversion intrinsic */ #if defined(__ARM_64BIT_STATE) && __ARM_64BIT_STATE static __inline__ int32_t __attribute__((__always_inline__, __nodebug__, target("v8.3a"))) @@ -702,7 +708,7 @@ __rint64x(double __a) { } #endif -/* Armv8.7-A load/store 64-byte intrinsics */ +/* 8.9 Armv8.7-A load/store 64-byte intrinsics */ #if defined(__ARM_64BIT_STATE) && __ARM_64BIT_STATE typedef struct { uint64_t val[8]; @@ -728,7 +734,7 @@ __arm_st64bv0(void *__addr, data512_t __value) { } #endif -/* 10.1 Special register intrinsics */ +/* 11.1 Special register intrinsics */ #define __arm_rsr(sysreg) __builtin_arm_rsr(sysreg) #define __arm_rsr64(sysreg) __builtin_arm_rsr64(sysreg) #define __arm_rsr128(sysreg) __builtin_arm_rsr128(sysreg) @@ -742,7 +748,7 @@ __arm_st64bv0(void *__addr, data512_t __value) { #define __arm_wsrf(sysreg, v) __arm_wsr(sysreg, __builtin_bit_cast(uint32_t, v)) #define __arm_wsrf64(sysreg, v) __arm_wsr64(sysreg, __builtin_bit_cast(uint64_t, v)) -/* Memory Tagging Extensions (MTE) Intrinsics */ +/* 10.3 Memory Tagging Extensions (MTE) Intrinsics */ #if defined(__ARM_64BIT_STATE) && __ARM_64BIT_STATE #define __arm_mte_create_random_tag(__ptr, __mask) __builtin_arm_irg(__ptr, __mask) #define __arm_mte_increment_tag(__ptr, __tag_offset) __builtin_arm_addg(__ptr, __tag_offset) @@ -751,12 +757,12 @@ __arm_st64bv0(void *__addr, data512_t __value) { #define __arm_mte_set_tag(__ptr) __builtin_arm_stg(__ptr) #define __arm_mte_ptrdiff(__ptra, __ptrb) __builtin_arm_subp(__ptra, __ptrb) -/* Memory Operations Intrinsics */ +/* 18 Memory Operations Intrinsics */ #define __arm_mops_memset_tag(__tagged_address, __value, __size) \ __builtin_arm_mops_memset_tag(__tagged_address, __value, __size) #endif -/* Coprocessor Intrinsics */ +/* 11.3 Coprocessor Intrinsics */ #if defined(__ARM_FEATURE_COPROC) #if (__ARM_FEATURE_COPROC & 0x1) @@ -815,7 +821,7 @@ __arm_st64bv0(void *__addr, data512_t __value) { #endif // __ARM_FEATURE_COPROC -/* Transactional Memory Extension (TME) Intrinsics */ +/* 17 Transactional Memory Extension (TME) Intrinsics */ #if defined(__ARM_FEATURE_TME) && __ARM_FEATURE_TME #define _TMFAILURE_REASON 0x00007fffu @@ -837,7 +843,7 @@ __arm_st64bv0(void *__addr, data512_t __value) { #endif /* __ARM_FEATURE_TME */ -/* Armv8.5-A Random number generation intrinsics */ +/* 8.7 Armv8.5-A Random number generation intrinsics */ #if defined(__ARM_64BIT_STATE) && __ARM_64BIT_STATE static __inline__ int __attribute__((__always_inline__, __nodebug__, target("rand"))) __rndr(uint64_t *__p) { diff --git a/clang/lib/Headers/bmiintrin.h b/clang/lib/Headers/bmiintrin.h index bc7c8a03c5e..d8e57c0cb49 100644 --- a/clang/lib/Headers/bmiintrin.h +++ b/clang/lib/Headers/bmiintrin.h @@ -19,18 +19,17 @@ to use it as a potentially faster version of BSF. */ #define __RELAXED_FN_ATTRS __attribute__((__always_inline__, __nodebug__)) -#define _tzcnt_u16 __tzcnt_u16 - /// Counts the number of trailing zero bits in the operand. /// /// \headerfile /// -/// This intrinsic corresponds to the TZCNT instruction. +/// This intrinsic corresponds to the \c TZCNT instruction. /// /// \param __X /// An unsigned 16-bit integer whose trailing zeros are to be counted. /// \returns An unsigned 16-bit integer containing the number of trailing zero /// bits in the operand. +/// \see _tzcnt_u16 static __inline__ unsigned short __RELAXED_FN_ATTRS __tzcnt_u16(unsigned short __X) { @@ -41,13 +40,30 @@ __tzcnt_u16(unsigned short __X) /// /// \headerfile /// -/// This intrinsic corresponds to the TZCNT instruction. +/// \code +/// unsigned short _tzcnt_u16(unsigned short __X); +/// \endcode +/// +/// This intrinsic corresponds to the \c TZCNT instruction. +/// +/// \param __X +/// An unsigned 16-bit integer whose trailing zeros are to be counted. +/// \returns An unsigned 16-bit integer containing the number of trailing zero +/// bits in the operand. +/// \see __tzcnt_u16 +#define _tzcnt_u16 __tzcnt_u16 + +/// Counts the number of trailing zero bits in the operand. +/// +/// \headerfile +/// +/// This intrinsic corresponds to the \c TZCNT instruction. /// /// \param __X /// An unsigned 32-bit integer whose trailing zeros are to be counted. /// \returns An unsigned 32-bit integer containing the number of trailing zero /// bits in the operand. -/// \see _mm_tzcnt_32 +/// \see { _mm_tzcnt_32 _tzcnt_u32 } static __inline__ unsigned int __RELAXED_FN_ATTRS __tzcnt_u32(unsigned int __X) { @@ -58,19 +74,34 @@ __tzcnt_u32(unsigned int __X) /// /// \headerfile /// -/// This intrinsic corresponds to the TZCNT instruction. +/// This intrinsic corresponds to the \c TZCNT instruction. /// /// \param __X /// An unsigned 32-bit integer whose trailing zeros are to be counted. -/// \returns An 32-bit integer containing the number of trailing zero bits in +/// \returns A 32-bit integer containing the number of trailing zero bits in /// the operand. -/// \see __tzcnt_u32 +/// \see { __tzcnt_u32 _tzcnt_u32 } static __inline__ int __RELAXED_FN_ATTRS _mm_tzcnt_32(unsigned int __X) { return (int)__builtin_ia32_tzcnt_u32(__X); } +/// Counts the number of trailing zero bits in the operand. +/// +/// \headerfile +/// +/// \code +/// unsigned int _tzcnt_u32(unsigned int __X); +/// \endcode +/// +/// This intrinsic corresponds to the \c TZCNT instruction. +/// +/// \param __X +/// An unsigned 32-bit integer whose trailing zeros are to be counted. +/// \returns An unsigned 32-bit integer containing the number of trailing zero +/// bits in the operand. +/// \see { _mm_tzcnt_32 __tzcnt_u32 } #define _tzcnt_u32 __tzcnt_u32 #ifdef __x86_64__ @@ -79,13 +110,13 @@ _mm_tzcnt_32(unsigned int __X) /// /// \headerfile /// -/// This intrinsic corresponds to the TZCNT instruction. +/// This intrinsic corresponds to the \c TZCNT instruction. /// /// \param __X /// An unsigned 64-bit integer whose trailing zeros are to be counted. /// \returns An unsigned 64-bit integer containing the number of trailing zero /// bits in the operand. -/// \see _mm_tzcnt_64 +/// \see { _mm_tzcnt_64 _tzcnt_u64 } static __inline__ unsigned long long __RELAXED_FN_ATTRS __tzcnt_u64(unsigned long long __X) { @@ -96,19 +127,34 @@ __tzcnt_u64(unsigned long long __X) /// /// \headerfile /// -/// This intrinsic corresponds to the TZCNT instruction. +/// This intrinsic corresponds to the \c TZCNT instruction. /// /// \param __X /// An unsigned 64-bit integer whose trailing zeros are to be counted. /// \returns An 64-bit integer containing the number of trailing zero bits in /// the operand. -/// \see __tzcnt_u64 +/// \see { __tzcnt_u64 _tzcnt_u64 } static __inline__ long long __RELAXED_FN_ATTRS _mm_tzcnt_64(unsigned long long __X) { return (long long)__builtin_ia32_tzcnt_u64(__X); } +/// Counts the number of trailing zero bits in the operand. +/// +/// \headerfile +/// +/// \code +/// unsigned long long _tzcnt_u64(unsigned long long __X); +/// \endcode +/// +/// This intrinsic corresponds to the \c TZCNT instruction. +/// +/// \param __X +/// An unsigned 64-bit integer whose trailing zeros are to be counted. +/// \returns An unsigned 64-bit integer containing the number of trailing zero +/// bits in the operand. +/// \see { _mm_tzcnt_64 __tzcnt_u64 #define _tzcnt_u64 __tzcnt_u64 #endif /* __x86_64__ */ @@ -121,21 +167,12 @@ _mm_tzcnt_64(unsigned long long __X) /* Define the default attributes for the functions in this file. */ #define __DEFAULT_FN_ATTRS __attribute__((__always_inline__, __nodebug__, __target__("bmi"))) -#define _andn_u32 __andn_u32 - -/* _bextr_u32 != __bextr_u32 */ -#define _blsi_u32 __blsi_u32 - -#define _blsmsk_u32 __blsmsk_u32 - -#define _blsr_u32 __blsr_u32 - /// Performs a bitwise AND of the second operand with the one's /// complement of the first operand. /// /// \headerfile /// -/// This intrinsic corresponds to the ANDN instruction. +/// This intrinsic corresponds to the \c ANDN instruction. /// /// \param __X /// An unsigned integer containing one of the operands. @@ -143,19 +180,40 @@ _mm_tzcnt_64(unsigned long long __X) /// An unsigned integer containing one of the operands. /// \returns An unsigned integer containing the bitwise AND of the second /// operand with the one's complement of the first operand. +/// \see _andn_u32 static __inline__ unsigned int __DEFAULT_FN_ATTRS __andn_u32(unsigned int __X, unsigned int __Y) { return ~__X & __Y; } +/// Performs a bitwise AND of the second operand with the one's +/// complement of the first operand. +/// +/// \headerfile +/// +/// \code +/// unsigned int _andn_u32(unsigned int __X, unsigned int __Y); +/// \endcode +/// +/// This intrinsic corresponds to the \c ANDN instruction. +/// +/// \param __X +/// An unsigned integer containing one of the operands. +/// \param __Y +/// An unsigned integer containing one of the operands. +/// \returns An unsigned integer containing the bitwise AND of the second +/// operand with the one's complement of the first operand. +/// \see __andn_u32 +#define _andn_u32 __andn_u32 + /* AMD-specified, double-leading-underscore version of BEXTR */ /// Extracts the specified bits from the first operand and returns them /// in the least significant bits of the result. /// /// \headerfile /// -/// This intrinsic corresponds to the BEXTR instruction. +/// This intrinsic corresponds to the \c BEXTR instruction. /// /// \param __X /// An unsigned integer whose bits are to be extracted. @@ -178,7 +236,7 @@ __bextr_u32(unsigned int __X, unsigned int __Y) /// /// \headerfile /// -/// This intrinsic corresponds to the BEXTR instruction. +/// This intrinsic corresponds to the \c BEXTR instruction. /// /// \param __X /// An unsigned integer whose bits are to be extracted. @@ -203,7 +261,7 @@ _bextr_u32(unsigned int __X, unsigned int __Y, unsigned int __Z) /// /// \headerfile /// -/// This intrinsic corresponds to the BEXTR instruction. +/// This intrinsic corresponds to the \c BEXTR instruction. /// /// \param __X /// An unsigned integer whose bits are to be extracted. @@ -224,33 +282,89 @@ _bextr2_u32(unsigned int __X, unsigned int __Y) { /// /// \headerfile /// -/// This intrinsic corresponds to the BLSI instruction. +/// This intrinsic corresponds to the \c BLSI instruction. /// /// \param __X /// An unsigned integer whose bits are to be cleared. /// \returns An unsigned integer containing the result of clearing the bits from /// the source operand. +/// \see _blsi_u32 static __inline__ unsigned int __DEFAULT_FN_ATTRS __blsi_u32(unsigned int __X) { return __X & -__X; } +/// Clears all bits in the source except for the least significant bit +/// containing a value of 1 and returns the result. +/// +/// \headerfile +/// +/// \code +/// unsigned int _blsi_u32(unsigned int __X); +/// \endcode +/// +/// This intrinsic corresponds to the \c BLSI instruction. +/// +/// \param __X +/// An unsigned integer whose bits are to be cleared. +/// \returns An unsigned integer containing the result of clearing the bits from +/// the source operand. +/// \see __blsi_u32 +#define _blsi_u32 __blsi_u32 + +/// Creates a mask whose bits are set to 1, using bit 0 up to and +/// including the least significant bit that is set to 1 in the source +/// operand and returns the result. +/// +/// \headerfile +/// +/// This intrinsic corresponds to the \c BLSMSK instruction. +/// +/// \param __X +/// An unsigned integer used to create the mask. +/// \returns An unsigned integer containing the newly created mask. +/// \see _blsmsk_u32 +static __inline__ unsigned int __DEFAULT_FN_ATTRS +__blsmsk_u32(unsigned int __X) +{ + return __X ^ (__X - 1); +} + /// Creates a mask whose bits are set to 1, using bit 0 up to and /// including the least significant bit that is set to 1 in the source /// operand and returns the result. /// /// \headerfile /// -/// This intrinsic corresponds to the BLSMSK instruction. +/// \code +/// unsigned int _blsmsk_u32(unsigned int __X); +/// \endcode +/// +/// This intrinsic corresponds to the \c BLSMSK instruction. /// /// \param __X /// An unsigned integer used to create the mask. /// \returns An unsigned integer containing the newly created mask. +/// \see __blsmsk_u32 +#define _blsmsk_u32 __blsmsk_u32 + +/// Clears the least significant bit that is set to 1 in the source +/// operand and returns the result. +/// +/// \headerfile +/// +/// This intrinsic corresponds to the \c BLSR instruction. +/// +/// \param __X +/// An unsigned integer containing the operand to be cleared. +/// \returns An unsigned integer containing the result of clearing the source +/// operand. +/// \see _blsr_u32 static __inline__ unsigned int __DEFAULT_FN_ATTRS -__blsmsk_u32(unsigned int __X) +__blsr_u32(unsigned int __X) { - return __X ^ (__X - 1); + return __X & (__X - 1); } /// Clears the least significant bit that is set to 1 in the source @@ -258,35 +372,27 @@ __blsmsk_u32(unsigned int __X) /// /// \headerfile /// -/// This intrinsic corresponds to the BLSR instruction. +/// \code +/// unsigned int _bls4_u32(unsigned int __X); +/// \endcode +/// +/// This intrinsic corresponds to the \c BLSR instruction. /// /// \param __X /// An unsigned integer containing the operand to be cleared. /// \returns An unsigned integer containing the result of clearing the source /// operand. -static __inline__ unsigned int __DEFAULT_FN_ATTRS -__blsr_u32(unsigned int __X) -{ - return __X & (__X - 1); -} +/// \see __blsr_u32 +#define _blsr_u32 __blsr_u32 #ifdef __x86_64__ -#define _andn_u64 __andn_u64 - -/* _bextr_u64 != __bextr_u64 */ -#define _blsi_u64 __blsi_u64 - -#define _blsmsk_u64 __blsmsk_u64 - -#define _blsr_u64 __blsr_u64 - /// Performs a bitwise AND of the second operand with the one's /// complement of the first operand. /// /// \headerfile /// -/// This intrinsic corresponds to the ANDN instruction. +/// This intrinsic corresponds to the \c ANDN instruction. /// /// \param __X /// An unsigned 64-bit integer containing one of the operands. @@ -294,19 +400,41 @@ __blsr_u32(unsigned int __X) /// An unsigned 64-bit integer containing one of the operands. /// \returns An unsigned 64-bit integer containing the bitwise AND of the second /// operand with the one's complement of the first operand. +/// \see _andn_u64 static __inline__ unsigned long long __DEFAULT_FN_ATTRS __andn_u64 (unsigned long long __X, unsigned long long __Y) { return ~__X & __Y; } +/// Performs a bitwise AND of the second operand with the one's +/// complement of the first operand. +/// +/// \headerfile +/// +/// \code +/// unsigned long long _andn_u64(unsigned long long __X, +/// unsigned long long __Y); +/// \endcode +/// +/// This intrinsic corresponds to the \c ANDN instruction. +/// +/// \param __X +/// An unsigned 64-bit integer containing one of the operands. +/// \param __Y +/// An unsigned 64-bit integer containing one of the operands. +/// \returns An unsigned 64-bit integer containing the bitwise AND of the second +/// operand with the one's complement of the first operand. +/// \see __andn_u64 +#define _andn_u64 __andn_u64 + /* AMD-specified, double-leading-underscore version of BEXTR */ /// Extracts the specified bits from the first operand and returns them /// in the least significant bits of the result. /// /// \headerfile /// -/// This intrinsic corresponds to the BEXTR instruction. +/// This intrinsic corresponds to the \c BEXTR instruction. /// /// \param __X /// An unsigned 64-bit integer whose bits are to be extracted. @@ -329,7 +457,7 @@ __bextr_u64(unsigned long long __X, unsigned long long __Y) /// /// \headerfile /// -/// This intrinsic corresponds to the BEXTR instruction. +/// This intrinsic corresponds to the \c BEXTR instruction. /// /// \param __X /// An unsigned 64-bit integer whose bits are to be extracted. @@ -354,7 +482,7 @@ _bextr_u64(unsigned long long __X, unsigned int __Y, unsigned int __Z) /// /// \headerfile /// -/// This intrinsic corresponds to the BEXTR instruction. +/// This intrinsic corresponds to the \c BEXTR instruction. /// /// \param __X /// An unsigned 64-bit integer whose bits are to be extracted. @@ -375,33 +503,89 @@ _bextr2_u64(unsigned long long __X, unsigned long long __Y) { /// /// \headerfile /// -/// This intrinsic corresponds to the BLSI instruction. +/// This intrinsic corresponds to the \c BLSI instruction. /// /// \param __X /// An unsigned 64-bit integer whose bits are to be cleared. /// \returns An unsigned 64-bit integer containing the result of clearing the /// bits from the source operand. +/// \see _blsi_u64 static __inline__ unsigned long long __DEFAULT_FN_ATTRS __blsi_u64(unsigned long long __X) { return __X & -__X; } +/// Clears all bits in the source except for the least significant bit +/// containing a value of 1 and returns the result. +/// +/// \headerfile +/// +/// \code +/// unsigned long long _blsi_u64(unsigned long long __X); +/// \endcode +/// +/// This intrinsic corresponds to the \c BLSI instruction. +/// +/// \param __X +/// An unsigned 64-bit integer whose bits are to be cleared. +/// \returns An unsigned 64-bit integer containing the result of clearing the +/// bits from the source operand. +/// \see __blsi_u64 +#define _blsi_u64 __blsi_u64 + +/// Creates a mask whose bits are set to 1, using bit 0 up to and +/// including the least significant bit that is set to 1 in the source +/// operand and returns the result. +/// +/// \headerfile +/// +/// This intrinsic corresponds to the \c BLSMSK instruction. +/// +/// \param __X +/// An unsigned 64-bit integer used to create the mask. +/// \returns An unsigned 64-bit integer containing the newly created mask. +/// \see _blsmsk_u64 +static __inline__ unsigned long long __DEFAULT_FN_ATTRS +__blsmsk_u64(unsigned long long __X) +{ + return __X ^ (__X - 1); +} + /// Creates a mask whose bits are set to 1, using bit 0 up to and /// including the least significant bit that is set to 1 in the source /// operand and returns the result. /// /// \headerfile /// -/// This intrinsic corresponds to the BLSMSK instruction. +/// \code +/// unsigned long long _blsmsk_u64(unsigned long long __X); +/// \endcode +/// +/// This intrinsic corresponds to the \c BLSMSK instruction. /// /// \param __X /// An unsigned 64-bit integer used to create the mask. /// \returns An unsigned 64-bit integer containing the newly created mask. +/// \see __blsmsk_u64 +#define _blsmsk_u64 __blsmsk_u64 + +/// Clears the least significant bit that is set to 1 in the source +/// operand and returns the result. +/// +/// \headerfile +/// +/// This intrinsic corresponds to the \c BLSR instruction. +/// +/// \param __X +/// An unsigned 64-bit integer containing the operand to be cleared. +/// \returns An unsigned 64-bit integer containing the result of clearing the +/// source operand. +/// \see _blsr_u64 static __inline__ unsigned long long __DEFAULT_FN_ATTRS -__blsmsk_u64(unsigned long long __X) +__blsr_u64(unsigned long long __X) { - return __X ^ (__X - 1); + return __X & (__X - 1); } /// Clears the least significant bit that is set to 1 in the source @@ -409,17 +593,18 @@ __blsmsk_u64(unsigned long long __X) /// /// \headerfile /// -/// This intrinsic corresponds to the BLSR instruction. +/// \code +/// unsigned long long _blsr_u64(unsigned long long __X); +/// \endcode +/// +/// This intrinsic corresponds to the \c BLSR instruction. /// /// \param __X /// An unsigned 64-bit integer containing the operand to be cleared. /// \returns An unsigned 64-bit integer containing the result of clearing the /// source operand. -static __inline__ unsigned long long __DEFAULT_FN_ATTRS -__blsr_u64(unsigned long long __X) -{ - return __X & (__X - 1); -} +/// \see __blsr_u64 +#define _blsr_u64 __blsr_u64 #endif /* __x86_64__ */ diff --git a/clang/lib/Headers/ia32intrin.h b/clang/lib/Headers/ia32intrin.h index a8b59dfaad8..1b979770e19 100644 --- a/clang/lib/Headers/ia32intrin.h +++ b/clang/lib/Headers/ia32intrin.h @@ -37,6 +37,7 @@ /// \param __A /// A 32-bit integer operand. /// \returns A 32-bit integer containing the bit number. +/// \see _bit_scan_forward static __inline__ int __DEFAULT_FN_ATTRS_CONSTEXPR __bsfd(int __A) { return __builtin_ctz((unsigned int)__A); @@ -53,12 +54,13 @@ __bsfd(int __A) { /// \param __A /// A 32-bit integer operand. /// \returns A 32-bit integer containing the bit number. +/// \see _bit_scan_reverse static __inline__ int __DEFAULT_FN_ATTRS_CONSTEXPR __bsrd(int __A) { return 31 - __builtin_clz((unsigned int)__A); } -/// Swaps the bytes in the input. Converting little endian to big endian or +/// Swaps the bytes in the input, converting little endian to big endian or /// vice versa. /// /// \headerfile @@ -73,12 +75,55 @@ __bswapd(int __A) { return (int)__builtin_bswap32((unsigned int)__A); } +/// Swaps the bytes in the input, converting little endian to big endian or +/// vice versa. +/// +/// \headerfile +/// +/// This intrinsic corresponds to the \c BSWAP instruction. +/// +/// \param __A +/// A 32-bit integer operand. +/// \returns A 32-bit integer containing the swapped bytes. static __inline__ int __DEFAULT_FN_ATTRS_CONSTEXPR _bswap(int __A) { return (int)__builtin_bswap32((unsigned int)__A); } +/// Find the first set bit starting from the lsb. Result is undefined if +/// input is 0. +/// +/// \headerfile +/// +/// \code +/// int _bit_scan_forward(int A); +/// \endcode +/// +/// This intrinsic corresponds to the \c BSF instruction or the +/// \c TZCNT instruction. +/// +/// \param A +/// A 32-bit integer operand. +/// \returns A 32-bit integer containing the bit number. +/// \see __bsfd #define _bit_scan_forward(A) __bsfd((A)) + +/// Find the first set bit starting from the msb. Result is undefined if +/// input is 0. +/// +/// \headerfile +/// +/// \code +/// int _bit_scan_reverse(int A); +/// \endcode +/// +/// This intrinsic corresponds to the \c BSR instruction or the +/// \c LZCNT instruction and an \c XOR. +/// +/// \param A +/// A 32-bit integer operand. +/// \returns A 32-bit integer containing the bit number. +/// \see __bsrd #define _bit_scan_reverse(A) __bsrd((A)) #ifdef __x86_64__ @@ -124,13 +169,29 @@ __bsrq(long long __A) { /// \param __A /// A 64-bit integer operand. /// \returns A 64-bit integer containing the swapped bytes. +/// \see _bswap64 static __inline__ long long __DEFAULT_FN_ATTRS_CONSTEXPR __bswapq(long long __A) { return (long long)__builtin_bswap64((unsigned long long)__A); } +/// Swaps the bytes in the input. Converting little endian to big endian or +/// vice versa. +/// +/// \headerfile +/// +/// \code +/// long long _bswap64(long long A); +/// \endcode +/// +/// This intrinsic corresponds to the \c BSWAP instruction. +/// +/// \param A +/// A 64-bit integer operand. +/// \returns A 64-bit integer containing the swapped bytes. +/// \see __bswapq #define _bswap64(A) __bswapq((A)) -#endif +#endif /* __x86_64__ */ /// Counts the number of bits in the source operand having a value of 1. /// @@ -143,12 +204,29 @@ __bswapq(long long __A) { /// An unsigned 32-bit integer operand. /// \returns A 32-bit integer containing the number of bits with value 1 in the /// source operand. +/// \see _popcnt32 static __inline__ int __DEFAULT_FN_ATTRS_CONSTEXPR __popcntd(unsigned int __A) { return __builtin_popcount(__A); } +/// Counts the number of bits in the source operand having a value of 1. +/// +/// \headerfile +/// +/// \code +/// int _popcnt32(int A); +/// \endcode +/// +/// This intrinsic corresponds to the \c POPCNT instruction or a +/// a sequence of arithmetic and logic ops to calculate it. +/// +/// \param A +/// An unsigned 32-bit integer operand. +/// \returns A 32-bit integer containing the number of bits with value 1 in the +/// source operand. +/// \see __popcntd #define _popcnt32(A) __popcntd((A)) #ifdef __x86_64__ @@ -163,22 +241,56 @@ __popcntd(unsigned int __A) /// An unsigned 64-bit integer operand. /// \returns A 64-bit integer containing the number of bits with value 1 in the /// source operand. +/// \see _popcnt64 static __inline__ long long __DEFAULT_FN_ATTRS_CONSTEXPR __popcntq(unsigned long long __A) { return __builtin_popcountll(__A); } +/// Counts the number of bits in the source operand having a value of 1. +/// +/// \headerfile +/// +/// \code +/// long long _popcnt64(unsigned long long A); +/// \endcode +/// +/// This intrinsic corresponds to the \c POPCNT instruction or a +/// a sequence of arithmetic and logic ops to calculate it. +/// +/// \param A +/// An unsigned 64-bit integer operand. +/// \returns A 64-bit integer containing the number of bits with value 1 in the +/// source operand. +/// \see __popcntq #define _popcnt64(A) __popcntq((A)) #endif /* __x86_64__ */ #ifdef __x86_64__ +/// Returns the program status and control \c RFLAGS register with the \c VM +/// and \c RF flags cleared. +/// +/// \headerfile +/// +/// This intrinsic corresponds to the \c PUSHFQ + \c POP instruction sequence. +/// +/// \returns The 64-bit value of the RFLAGS register. static __inline__ unsigned long long __DEFAULT_FN_ATTRS __readeflags(void) { return __builtin_ia32_readeflags_u64(); } +/// Writes the specified value to the program status and control \c RFLAGS +/// register. Reserved bits are not affected. +/// +/// \headerfile +/// +/// This intrinsic corresponds to the \c PUSH + \c POPFQ instruction sequence. +/// +/// \param __f +/// The 64-bit value to write to \c RFLAGS. static __inline__ void __DEFAULT_FN_ATTRS __writeeflags(unsigned long long __f) { @@ -186,12 +298,29 @@ __writeeflags(unsigned long long __f) } #else /* !__x86_64__ */ +/// Returns the program status and control \c EFLAGS register with the \c VM +/// and \c RF flags cleared. +/// +/// \headerfile +/// +/// This intrinsic corresponds to the \c PUSHFD + \c POP instruction sequence. +/// +/// \returns The 32-bit value of the EFLAGS register. static __inline__ unsigned int __DEFAULT_FN_ATTRS __readeflags(void) { return __builtin_ia32_readeflags_u32(); } +/// Writes the specified value to the program status and control \c EFLAGS +/// register. Reserved bits are not affected. +/// +/// \headerfile +/// +/// This intrinsic corresponds to the \c PUSH + \c POPFD instruction sequence. +/// +/// \param __f +/// The 32-bit value to write to \c EFLAGS. static __inline__ void __DEFAULT_FN_ATTRS __writeeflags(unsigned int __f) { @@ -341,19 +470,67 @@ __crc32q(unsigned long long __C, unsigned long long __D) } #endif /* __x86_64__ */ +/// Reads the specified performance monitoring counter. Refer to your +/// processor's documentation to determine which performance counters are +/// supported. +/// +/// \headerfile +/// +/// This intrinsic corresponds to the \c RDPMC instruction. +/// +/// \param __A +/// The performance counter to read. +/// \returns The 64-bit value read from the performance counter. +/// \see _rdpmc static __inline__ unsigned long long __DEFAULT_FN_ATTRS __rdpmc(int __A) { return __builtin_ia32_rdpmc(__A); } -/* __rdtscp */ +/// Reads the processor's time stamp counter and the \c IA32_TSC_AUX MSR +/// \c (0xc0000103). +/// +/// \headerfile +/// +/// This intrinsic corresponds to the \c RDTSCP instruction. +/// +/// \param __A +/// Address of where to store the 32-bit \c IA32_TSC_AUX value. +/// \returns The 64-bit value of the time stamp counter. static __inline__ unsigned long long __DEFAULT_FN_ATTRS __rdtscp(unsigned int *__A) { return __builtin_ia32_rdtscp(__A); } +/// Reads the processor's time stamp counter. +/// +/// \headerfile +/// +/// \code +/// unsigned long long _rdtsc(); +/// \endcode +/// +/// This intrinsic corresponds to the \c RDTSC instruction. +/// +/// \returns The 64-bit value of the time stamp counter. #define _rdtsc() __rdtsc() +/// Reads the specified performance monitoring counter. Refer to your +/// processor's documentation to determine which performance counters are +/// supported. +/// +/// \headerfile +/// +/// \code +/// unsigned long long _rdpmc(int A); +/// \endcode +/// +/// This intrinsic corresponds to the \c RDPMC instruction. +/// +/// \param A +/// The performance counter to read. +/// \returns The 64-bit value read from the performance counter. +/// \see __rdpmc #define _rdpmc(A) __rdpmc(A) static __inline__ void __DEFAULT_FN_ATTRS @@ -361,42 +538,150 @@ _wbinvd(void) { __builtin_ia32_wbinvd(); } +/// Rotates an 8-bit value to the left by the specified number of bits. +/// This operation is undefined if the number of bits exceeds the size of +/// the value. +/// +/// \headerfile +/// +/// This intrinsic corresponds to the \c ROL instruction. +/// +/// \param __X +/// The unsigned 8-bit value to be rotated. +/// \param __C +/// The number of bits to rotate the value. +/// \returns The rotated value. static __inline__ unsigned char __DEFAULT_FN_ATTRS_CONSTEXPR __rolb(unsigned char __X, int __C) { return __builtin_rotateleft8(__X, __C); } +/// Rotates an 8-bit value to the right by the specified number of bits. +/// This operation is undefined if the number of bits exceeds the size of +/// the value. +/// +/// \headerfile +/// +/// This intrinsic corresponds to the \c ROR instruction. +/// +/// \param __X +/// The unsigned 8-bit value to be rotated. +/// \param __C +/// The number of bits to rotate the value. +/// \returns The rotated value. static __inline__ unsigned char __DEFAULT_FN_ATTRS_CONSTEXPR __rorb(unsigned char __X, int __C) { return __builtin_rotateright8(__X, __C); } +/// Rotates a 16-bit value to the left by the specified number of bits. +/// This operation is undefined if the number of bits exceeds the size of +/// the value. +/// +/// \headerfile +/// +/// This intrinsic corresponds to the \c ROL instruction. +/// +/// \param __X +/// The unsigned 16-bit value to be rotated. +/// \param __C +/// The number of bits to rotate the value. +/// \returns The rotated value. +/// \see _rotwl static __inline__ unsigned short __DEFAULT_FN_ATTRS_CONSTEXPR __rolw(unsigned short __X, int __C) { return __builtin_rotateleft16(__X, __C); } +/// Rotates a 16-bit value to the right by the specified number of bits. +/// This operation is undefined if the number of bits exceeds the size of +/// the value. +/// +/// \headerfile +/// +/// This intrinsic corresponds to the \c ROR instruction. +/// +/// \param __X +/// The unsigned 16-bit value to be rotated. +/// \param __C +/// The number of bits to rotate the value. +/// \returns The rotated value. +/// \see _rotwr static __inline__ unsigned short __DEFAULT_FN_ATTRS_CONSTEXPR __rorw(unsigned short __X, int __C) { return __builtin_rotateright16(__X, __C); } +/// Rotates a 32-bit value to the left by the specified number of bits. +/// This operation is undefined if the number of bits exceeds the size of +/// the value. +/// +/// \headerfile +/// +/// This intrinsic corresponds to the \c ROL instruction. +/// +/// \param __X +/// The unsigned 32-bit value to be rotated. +/// \param __C +/// The number of bits to rotate the value. +/// \returns The rotated value. +/// \see _rotl static __inline__ unsigned int __DEFAULT_FN_ATTRS_CONSTEXPR __rold(unsigned int __X, int __C) { return __builtin_rotateleft32(__X, (unsigned int)__C); } +/// Rotates a 32-bit value to the right by the specified number of bits. +/// This operation is undefined if the number of bits exceeds the size of +/// the value. +/// +/// \headerfile +/// +/// This intrinsic corresponds to the \c ROR instruction. +/// +/// \param __X +/// The unsigned 32-bit value to be rotated. +/// \param __C +/// The number of bits to rotate the value. +/// \returns The rotated value. +/// \see _rotr static __inline__ unsigned int __DEFAULT_FN_ATTRS_CONSTEXPR __rord(unsigned int __X, int __C) { return __builtin_rotateright32(__X, (unsigned int)__C); } #ifdef __x86_64__ +/// Rotates a 64-bit value to the left by the specified number of bits. +/// This operation is undefined if the number of bits exceeds the size of +/// the value. +/// +/// \headerfile +/// +/// This intrinsic corresponds to the \c ROL instruction. +/// +/// \param __X +/// The unsigned 64-bit value to be rotated. +/// \param __C +/// The number of bits to rotate the value. +/// \returns The rotated value. static __inline__ unsigned long long __DEFAULT_FN_ATTRS_CONSTEXPR __rolq(unsigned long long __X, int __C) { return __builtin_rotateleft64(__X, (unsigned long long)__C); } +/// Rotates a 64-bit value to the right by the specified number of bits. +/// This operation is undefined if the number of bits exceeds the size of +/// the value. +/// +/// \headerfile +/// +/// This intrinsic corresponds to the \c ROR instruction. +/// +/// \param __X +/// The unsigned 64-bit value to be rotated. +/// \param __C +/// The number of bits to rotate the value. +/// \returns The rotated value. static __inline__ unsigned long long __DEFAULT_FN_ATTRS_CONSTEXPR __rorq(unsigned long long __X, int __C) { return __builtin_rotateright64(__X, (unsigned long long)__C); @@ -407,18 +692,167 @@ __rorq(unsigned long long __X, int __C) { /* These are already provided as builtins for MSVC. */ /* Select the correct function based on the size of long. */ #ifdef __LP64__ +/// Rotates a 64-bit value to the left by the specified number of bits. +/// This operation is undefined if the number of bits exceeds the size of +/// the value. +/// +/// \headerfile +/// +/// \code +/// unsigned long long _lrotl(unsigned long long a, int b); +/// \endcode +/// +/// This intrinsic corresponds to the \c ROL instruction. +/// +/// \param a +/// The unsigned 64-bit value to be rotated. +/// \param b +/// The number of bits to rotate the value. +/// \returns The rotated value. +/// \see __rolq #define _lrotl(a,b) __rolq((a), (b)) + +/// Rotates a 64-bit value to the right by the specified number of bits. +/// This operation is undefined if the number of bits exceeds the size of +/// the value. +/// +/// \headerfile +/// +/// \code +/// unsigned long long _lrotr(unsigned long long a, int b); +/// \endcode +/// +/// This intrinsic corresponds to the \c ROR instruction. +/// +/// \param a +/// The unsigned 64-bit value to be rotated. +/// \param b +/// The number of bits to rotate the value. +/// \returns The rotated value. +/// \see __rorq #define _lrotr(a,b) __rorq((a), (b)) -#else +#else // __LP64__ +/// Rotates a 32-bit value to the left by the specified number of bits. +/// This operation is undefined if the number of bits exceeds the size of +/// the value. +/// +/// \headerfile +/// +/// \code +/// unsigned int _lrotl(unsigned int a, int b); +/// \endcode +/// +/// This intrinsic corresponds to the \c ROL instruction. +/// +/// \param a +/// The unsigned 32-bit value to be rotated. +/// \param b +/// The number of bits to rotate the value. +/// \returns The rotated value. +/// \see __rold #define _lrotl(a,b) __rold((a), (b)) + +/// Rotates a 32-bit value to the right by the specified number of bits. +/// This operation is undefined if the number of bits exceeds the size of +/// the value. +/// +/// \headerfile +/// +/// \code +/// unsigned int _lrotr(unsigned int a, int b); +/// \endcode +/// +/// This intrinsic corresponds to the \c ROR instruction. +/// +/// \param a +/// The unsigned 32-bit value to be rotated. +/// \param b +/// The number of bits to rotate the value. +/// \returns The rotated value. +/// \see __rord #define _lrotr(a,b) __rord((a), (b)) -#endif +#endif // __LP64__ + +/// Rotates a 32-bit value to the left by the specified number of bits. +/// This operation is undefined if the number of bits exceeds the size of +/// the value. +/// +/// \headerfile +/// +/// \code +/// unsigned int _rotl(unsigned int a, int b); +/// \endcode +/// +/// This intrinsic corresponds to the \c ROL instruction. +/// +/// \param a +/// The unsigned 32-bit value to be rotated. +/// \param b +/// The number of bits to rotate the value. +/// \returns The rotated value. +/// \see __rold #define _rotl(a,b) __rold((a), (b)) + +/// Rotates a 32-bit value to the right by the specified number of bits. +/// This operation is undefined if the number of bits exceeds the size of +/// the value. +/// +/// \headerfile +/// +/// \code +/// unsigned int _rotr(unsigned int a, int b); +/// \endcode +/// +/// This intrinsic corresponds to the \c ROR instruction. +/// +/// \param a +/// The unsigned 32-bit value to be rotated. +/// \param b +/// The number of bits to rotate the value. +/// \returns The rotated value. +/// \see __rord #define _rotr(a,b) __rord((a), (b)) #endif // _MSC_VER /* These are not builtins so need to be provided in all modes. */ +/// Rotates a 16-bit value to the left by the specified number of bits. +/// This operation is undefined if the number of bits exceeds the size of +/// the value. +/// +/// \headerfile +/// +/// \code +/// unsigned short _rotwl(unsigned short a, int b); +/// \endcode +/// +/// This intrinsic corresponds to the \c ROL instruction. +/// +/// \param a +/// The unsigned 16-bit value to be rotated. +/// \param b +/// The number of bits to rotate the value. +/// \returns The rotated value. +/// \see __rolw #define _rotwl(a,b) __rolw((a), (b)) + +/// Rotates a 16-bit value to the right by the specified number of bits. +/// This operation is undefined if the number of bits exceeds the size of +/// the value. +/// +/// \headerfile +/// +/// \code +/// unsigned short _rotwr(unsigned short a, int b); +/// \endcode +/// +/// This intrinsic corresponds to the \c ROR instruction. +/// +/// \param a +/// The unsigned 16-bit value to be rotated. +/// \param b +/// The number of bits to rotate the value. +/// \returns The rotated value. +/// \see __rorw #define _rotwr(a,b) __rorw((a), (b)) #undef __DEFAULT_FN_ATTRS diff --git a/clang/lib/Headers/immintrin.h b/clang/lib/Headers/immintrin.h index 0149a1cdea6..27800f7a820 100644 --- a/clang/lib/Headers/immintrin.h +++ b/clang/lib/Headers/immintrin.h @@ -490,6 +490,15 @@ _writegsbase_u64(unsigned long long __V) * field inside of it. */ +/// Load a 16-bit value from memory and swap its bytes. +/// +/// \headerfile +/// +/// This intrinsic corresponds to the MOVBE instruction. +/// +/// \param __P +/// A pointer to the 16-bit value to load. +/// \returns The byte-swapped value. static __inline__ short __attribute__((__always_inline__, __nodebug__, __target__("movbe"))) _loadbe_i16(void const * __P) { struct __loadu_i16 { @@ -498,6 +507,16 @@ _loadbe_i16(void const * __P) { return (short)__builtin_bswap16(((const struct __loadu_i16*)__P)->__v); } +/// Swap the bytes of a 16-bit value and store it to memory. +/// +/// \headerfile +/// +/// This intrinsic corresponds to the MOVBE instruction. +/// +/// \param __P +/// A pointer to the memory for storing the swapped value. +/// \param __D +/// The 16-bit value to be byte-swapped. static __inline__ void __attribute__((__always_inline__, __nodebug__, __target__("movbe"))) _storebe_i16(void * __P, short __D) { struct __storeu_i16 { @@ -506,6 +525,15 @@ _storebe_i16(void * __P, short __D) { ((struct __storeu_i16*)__P)->__v = __builtin_bswap16((unsigned short)__D); } +/// Load a 32-bit value from memory and swap its bytes. +/// +/// \headerfile +/// +/// This intrinsic corresponds to the MOVBE instruction. +/// +/// \param __P +/// A pointer to the 32-bit value to load. +/// \returns The byte-swapped value. static __inline__ int __attribute__((__always_inline__, __nodebug__, __target__("movbe"))) _loadbe_i32(void const * __P) { struct __loadu_i32 { @@ -514,6 +542,16 @@ _loadbe_i32(void const * __P) { return (int)__builtin_bswap32(((const struct __loadu_i32*)__P)->__v); } +/// Swap the bytes of a 32-bit value and store it to memory. +/// +/// \headerfile +/// +/// This intrinsic corresponds to the MOVBE instruction. +/// +/// \param __P +/// A pointer to the memory for storing the swapped value. +/// \param __D +/// The 32-bit value to be byte-swapped. static __inline__ void __attribute__((__always_inline__, __nodebug__, __target__("movbe"))) _storebe_i32(void * __P, int __D) { struct __storeu_i32 { @@ -523,6 +561,15 @@ _storebe_i32(void * __P, int __D) { } #ifdef __x86_64__ +/// Load a 64-bit value from memory and swap its bytes. +/// +/// \headerfile +/// +/// This intrinsic corresponds to the MOVBE instruction. +/// +/// \param __P +/// A pointer to the 64-bit value to load. +/// \returns The byte-swapped value. static __inline__ long long __attribute__((__always_inline__, __nodebug__, __target__("movbe"))) _loadbe_i64(void const * __P) { struct __loadu_i64 { @@ -531,6 +578,16 @@ _loadbe_i64(void const * __P) { return (long long)__builtin_bswap64(((const struct __loadu_i64*)__P)->__v); } +/// Swap the bytes of a 64-bit value and store it to memory. +/// +/// \headerfile +/// +/// This intrinsic corresponds to the MOVBE instruction. +/// +/// \param __P +/// A pointer to the memory for storing the swapped value. +/// \param __D +/// The 64-bit value to be byte-swapped. static __inline__ void __attribute__((__always_inline__, __nodebug__, __target__("movbe"))) _storebe_i64(void * __P, long long __D) { struct __storeu_i64 { diff --git a/clang/lib/Headers/larchintrin.h b/clang/lib/Headers/larchintrin.h index c5c533ee0b8..a613e5ca0e5 100644 --- a/clang/lib/Headers/larchintrin.h +++ b/clang/lib/Headers/larchintrin.h @@ -228,6 +228,18 @@ extern __inline void ((void)__builtin_loongarch_ldpte_d((long int)(_1), (_2))) #endif +#define __frecipe_s(/*float*/ _1) \ + (float)__builtin_loongarch_frecipe_s((float)_1) + +#define __frecipe_d(/*double*/ _1) \ + (double)__builtin_loongarch_frecipe_d((double)_1) + +#define __frsqrte_s(/*float*/ _1) \ + (float)__builtin_loongarch_frsqrte_s((float)_1) + +#define __frsqrte_d(/*double*/ _1) \ + (double)__builtin_loongarch_frsqrte_d((double)_1) + #ifdef __cplusplus } #endif diff --git a/clang/lib/Headers/lasxintrin.h b/clang/lib/Headers/lasxintrin.h index 6b4d5012a24..dafc2a2f3e6 100644 --- a/clang/lib/Headers/lasxintrin.h +++ b/clang/lib/Headers/lasxintrin.h @@ -1726,6 +1726,18 @@ extern __inline return (__m256d)__builtin_lasx_xvfrecip_d((v4f64)_1); } +extern __inline + __attribute__((__gnu_inline__, __always_inline__, __artificial__)) __m256 + __lasx_xvfrecipe_s(__m256 _1) { + return (__m256)__builtin_lasx_xvfrecipe_s((v8f32)_1); +} + +extern __inline + __attribute__((__gnu_inline__, __always_inline__, __artificial__)) __m256d + __lasx_xvfrecipe_d(__m256d _1) { + return (__m256d)__builtin_lasx_xvfrecipe_d((v4f64)_1); +} + extern __inline __attribute__((__gnu_inline__, __always_inline__, __artificial__)) __m256 __lasx_xvfrint_s(__m256 _1) { @@ -1750,6 +1762,18 @@ extern __inline return (__m256d)__builtin_lasx_xvfrsqrt_d((v4f64)_1); } +extern __inline + __attribute__((__gnu_inline__, __always_inline__, __artificial__)) __m256 + __lasx_xvfrsqrte_s(__m256 _1) { + return (__m256)__builtin_lasx_xvfrsqrte_s((v8f32)_1); +} + +extern __inline + __attribute__((__gnu_inline__, __always_inline__, __artificial__)) __m256d + __lasx_xvfrsqrte_d(__m256d _1) { + return (__m256d)__builtin_lasx_xvfrsqrte_d((v4f64)_1); +} + extern __inline __attribute__((__gnu_inline__, __always_inline__, __artificial__)) __m256 __lasx_xvflogb_s(__m256 _1) { diff --git a/clang/lib/Headers/llvm_libc_wrappers/string.h b/clang/lib/Headers/llvm_libc_wrappers/string.h index b4fbf17c7e4..0ea49cb1376 100644 --- a/clang/lib/Headers/llvm_libc_wrappers/string.h +++ b/clang/lib/Headers/llvm_libc_wrappers/string.h @@ -51,13 +51,13 @@ char *strcpy(char *__restrict, const char *__restrict) __LIBC_ATTRS; size_t strcspn(const char *, const char *) __LIBC_ATTRS; char *strdup(const char *) __LIBC_ATTRS; size_t strlen(const char *) __LIBC_ATTRS; -char *strncat(char *, const char *, size_t) __LIBC_ATTRS; +char *strncat(char *__restrict, const char *__restrict, size_t) __LIBC_ATTRS; int strncmp(const char *, const char *, size_t) __LIBC_ATTRS; char *strncpy(char *__restrict, const char *__restrict, size_t) __LIBC_ATTRS; char *strndup(const char *, size_t) __LIBC_ATTRS; size_t strnlen(const char *, size_t) __LIBC_ATTRS; size_t strspn(const char *, const char *) __LIBC_ATTRS; -char *strtok(char *__restrict, const char *) __LIBC_ATTRS; +char *strtok(char *__restrict, const char *__restrict) __LIBC_ATTRS; char *strtok_r(char *__restrict, const char *__restrict, char **__restrict) __LIBC_ATTRS; size_t strxfrm(char *__restrict, const char *__restrict, size_t) __LIBC_ATTRS; diff --git a/clang/lib/Headers/lsxintrin.h b/clang/lib/Headers/lsxintrin.h index a29bc7757ab..f347955ce6f 100644 --- a/clang/lib/Headers/lsxintrin.h +++ b/clang/lib/Headers/lsxintrin.h @@ -1776,6 +1776,18 @@ extern __inline return (__m128d)__builtin_lsx_vfrecip_d((v2f64)_1); } +extern __inline + __attribute__((__gnu_inline__, __always_inline__, __artificial__)) __m128 + __lsx_vfrecipe_s(__m128 _1) { + return (__m128)__builtin_lsx_vfrecipe_s((v4f32)_1); +} + +extern __inline + __attribute__((__gnu_inline__, __always_inline__, __artificial__)) __m128d + __lsx_vfrecipe_d(__m128d _1) { + return (__m128d)__builtin_lsx_vfrecipe_d((v2f64)_1); +} + extern __inline __attribute__((__gnu_inline__, __always_inline__, __artificial__)) __m128 __lsx_vfrint_s(__m128 _1) { @@ -1800,6 +1812,18 @@ extern __inline return (__m128d)__builtin_lsx_vfrsqrt_d((v2f64)_1); } +extern __inline + __attribute__((__gnu_inline__, __always_inline__, __artificial__)) __m128 + __lsx_vfrsqrte_s(__m128 _1) { + return (__m128)__builtin_lsx_vfrsqrte_s((v4f32)_1); +} + +extern __inline + __attribute__((__gnu_inline__, __always_inline__, __artificial__)) __m128d + __lsx_vfrsqrte_d(__m128d _1) { + return (__m128d)__builtin_lsx_vfrsqrte_d((v2f64)_1); +} + extern __inline __attribute__((__gnu_inline__, __always_inline__, __artificial__)) __m128 __lsx_vflogb_s(__m128 _1) { diff --git a/clang/lib/Index/USRGeneration.cpp b/clang/lib/Index/USRGeneration.cpp index fb936d9fbf8..5acc86191f8 100644 --- a/clang/lib/Index/USRGeneration.cpp +++ b/clang/lib/Index/USRGeneration.cpp @@ -12,6 +12,7 @@ #include "clang/AST/DeclCXX.h" #include "clang/AST/DeclTemplate.h" #include "clang/AST/DeclVisitor.h" +#include "clang/AST/ODRHash.h" #include "clang/Basic/FileManager.h" #include "clang/Lex/PreprocessingRecord.h" #include "llvm/Support/Path.h" @@ -1051,6 +1052,15 @@ void USRGenerator::VisitTemplateArgument(const TemplateArgument &Arg) { VisitType(Arg.getIntegralType()); Out << Arg.getAsIntegral(); break; + + case TemplateArgument::StructuralValue: { + Out << 'S'; + VisitType(Arg.getStructuralValueType()); + ODRHash Hash{}; + Hash.AddStructuralValue(Arg.getAsStructuralValue()); + Out << Hash.CalculateHash(); + break; + } } } diff --git a/clang/lib/Interpreter/Interpreter.cpp b/clang/lib/Interpreter/Interpreter.cpp index 734fe90d0d8..9f97a3c6b0b 100644 --- a/clang/lib/Interpreter/Interpreter.cpp +++ b/clang/lib/Interpreter/Interpreter.cpp @@ -148,7 +148,6 @@ IncrementalCompilerBuilder::create(std::vector &ClangArgv) { // We do C++ by default; append right after argv[0] if no "-x" given ClangArgv.insert(ClangArgv.end(), "-Xclang"); ClangArgv.insert(ClangArgv.end(), "-fincremental-extensions"); - ClangArgv.insert(ClangArgv.end(), "-mcpu=native"); ClangArgv.insert(ClangArgv.end(), "-c"); // Put a dummy C++ file on to ensure there's at least one compile job for the @@ -249,7 +248,7 @@ Interpreter::~Interpreter() { // can't find the precise resource directory in unittests so we have to hard // code them. const char *const Runtimes = R"( - void* operator new(__SIZE_TYPE__, void* __p) noexcept; +#ifdef __cplusplus void *__clang_Interpreter_SetValueWithAlloc(void*, void*, void*); void __clang_Interpreter_SetValueNoAlloc(void*, void*, void*); void __clang_Interpreter_SetValueNoAlloc(void*, void*, void*, void*); @@ -257,15 +256,18 @@ const char *const Runtimes = R"( void __clang_Interpreter_SetValueNoAlloc(void*, void*, void*, double); void __clang_Interpreter_SetValueNoAlloc(void*, void*, void*, long double); void __clang_Interpreter_SetValueNoAlloc(void*,void*,void*,unsigned long long); + struct __clang_Interpreter_NewTag{} __ci_newtag; + void* operator new(__SIZE_TYPE__, void* __p, __clang_Interpreter_NewTag) noexcept; template void __clang_Interpreter_SetValueCopyArr(T* Src, void* Placement, unsigned long Size) { for (auto Idx = 0; Idx < Size; ++Idx) - new ((void*)(((T*)Placement) + Idx)) T(Src[Idx]); + new ((void*)(((T*)Placement) + Idx), __ci_newtag) T(Src[Idx]); } template void __clang_Interpreter_SetValueCopyArr(const T (*Src)[N], void* Placement, unsigned long Size) { __clang_Interpreter_SetValueCopyArr(Src[0], Placement, Size); } +#endif // __cplusplus )"; llvm::Expected> @@ -280,7 +282,7 @@ Interpreter::create(std::unique_ptr CI) { if (!PTU) return PTU.takeError(); - Interp->ValuePrintingInfo.resize(3); + Interp->ValuePrintingInfo.resize(4); // FIXME: This is a ugly hack. Undo command checks its availability by looking // at the size of the PTU list. However we have parsed something in the // beginning of the REPL so we have to mark them as 'Irrevocable'. @@ -501,7 +503,7 @@ Interpreter::CompileDtorCall(CXXRecordDecl *CXXRD) { static constexpr llvm::StringRef MagicRuntimeInterface[] = { "__clang_Interpreter_SetValueNoAlloc", "__clang_Interpreter_SetValueWithAlloc", - "__clang_Interpreter_SetValueCopyArr"}; + "__clang_Interpreter_SetValueCopyArr", "__ci_newtag"}; bool Interpreter::FindRuntimeInterface() { if (llvm::all_of(ValuePrintingInfo, [](Expr *E) { return E != nullptr; })) @@ -531,6 +533,9 @@ bool Interpreter::FindRuntimeInterface() { if (!LookupInterface(ValuePrintingInfo[CopyArray], MagicRuntimeInterface[CopyArray])) return false; + if (!LookupInterface(ValuePrintingInfo[NewTag], + MagicRuntimeInterface[NewTag])) + return false; return true; } @@ -608,7 +613,9 @@ public: .getValuePrintingInfo()[Interpreter::InterfaceKind::CopyArray], SourceLocation(), Args, SourceLocation()); } - Expr *Args[] = {AllocCall.get()}; + Expr *Args[] = { + AllocCall.get(), + Interp.getValuePrintingInfo()[Interpreter::InterfaceKind::NewTag]}; ExprResult CXXNewCall = S.BuildCXXNew( E->getSourceRange(), /*UseGlobal=*/true, /*PlacementLParen=*/SourceLocation(), Args, @@ -629,8 +636,9 @@ public: Interp.getValuePrintingInfo()[Interpreter::InterfaceKind::NoAlloc], E->getBeginLoc(), Args, E->getEndLoc()); } + default: + llvm_unreachable("Unhandled Interpreter::InterfaceKind"); } - llvm_unreachable("Unhandled Interpreter::InterfaceKind"); } Interpreter::InterfaceKind VisitRecordType(const RecordType *Ty) { @@ -815,3 +823,15 @@ __clang_Interpreter_SetValueNoAlloc(void *This, void *OutVal, void *OpaqueType, VRef = Value(static_cast(This), OpaqueType); VRef.setLongDouble(Val); } + +// A trampoline to work around the fact that operator placement new cannot +// really be forward declared due to libc++ and libstdc++ declaration mismatch. +// FIXME: __clang_Interpreter_NewTag is ODR violation because we get the same +// definition in the interpreter runtime. We should move it in a runtime header +// which gets included by the interpreter and here. +struct __clang_Interpreter_NewTag {}; +REPL_EXTERNAL_VISIBILITY void * +operator new(size_t __sz, void *__p, __clang_Interpreter_NewTag) noexcept { + // Just forward to the standard operator placement new. + return operator new(__sz, __p); +} diff --git a/clang/lib/Lex/HeaderSearch.cpp b/clang/lib/Lex/HeaderSearch.cpp index 0f109018773..dfa974e9a67 100644 --- a/clang/lib/Lex/HeaderSearch.cpp +++ b/clang/lib/Lex/HeaderSearch.cpp @@ -1408,57 +1408,57 @@ bool HeaderSearch::ShouldEnterIncludeFile(Preprocessor &PP, // Get information about this file. HeaderFileInfo &FileInfo = getFileInfo(File); - // FIXME: this is a workaround for the lack of proper modules-aware support - // for #import / #pragma once - auto TryEnterImported = [&]() -> bool { - if (!ModulesEnabled) - return false; - // Ensure FileInfo bits are up to date. - ModMap.resolveHeaderDirectives(File); - // Modules with builtins are special; multiple modules use builtins as - // modular headers, example: - // - // module stddef { header "stddef.h" export * } - // - // After module map parsing, this expands to: - // - // module stddef { - // header "/path_to_builtin_dirs/stddef.h" - // textual "stddef.h" - // } - // - // It's common that libc++ and system modules will both define such - // submodules. Make sure cached results for a builtin header won't - // prevent other builtin modules from potentially entering the builtin - // header. Note that builtins are header guarded and the decision to - // actually enter them is postponed to the controlling macros logic below. - bool TryEnterHdr = false; - if (FileInfo.isCompilingModuleHeader && FileInfo.isModuleHeader) - TryEnterHdr = ModMap.isBuiltinHeader(File); - - // Textual headers can be #imported from different modules. Since ObjC - // headers find in the wild might rely only on #import and do not contain - // controlling macros, be conservative and only try to enter textual headers - // if such macro is present. - if (!FileInfo.isModuleHeader && - FileInfo.getControllingMacro(ExternalLookup)) - TryEnterHdr = true; - return TryEnterHdr; - }; - // If this is a #import directive, check that we have not already imported // this header. if (isImport) { // If this has already been imported, don't import it again. FileInfo.isImport = true; + // FIXME: this is a workaround for the lack of proper modules-aware support + // for #import / #pragma once + auto TryEnterImported = [&]() -> bool { + if (!ModulesEnabled) + return false; + // Ensure FileInfo bits are up to date. + ModMap.resolveHeaderDirectives(File); + // Modules with builtins are special; multiple modules use builtins as + // modular headers, example: + // + // module stddef { header "stddef.h" export * } + // + // After module map parsing, this expands to: + // + // module stddef { + // header "/path_to_builtin_dirs/stddef.h" + // textual "stddef.h" + // } + // + // It's common that libc++ and system modules will both define such + // submodules. Make sure cached results for a builtin header won't + // prevent other builtin modules from potentially entering the builtin + // header. Note that builtins are header guarded and the decision to + // actually enter them is postponed to the controlling macros logic below. + bool TryEnterHdr = false; + if (FileInfo.isCompilingModuleHeader && FileInfo.isModuleHeader) + TryEnterHdr = ModMap.isBuiltinHeader(File); + + // Textual headers can be #imported from different modules. Since ObjC + // headers find in the wild might rely only on #import and do not contain + // controlling macros, be conservative and only try to enter textual + // headers if such macro is present. + if (!FileInfo.isModuleHeader && + FileInfo.getControllingMacro(ExternalLookup)) + TryEnterHdr = true; + return TryEnterHdr; + }; + // Has this already been #import'ed or #include'd? if (PP.alreadyIncluded(File) && !TryEnterImported()) return false; } else { // Otherwise, if this is a #include of a file that was previously #import'd // or if this is the second #include of a #pragma once file, ignore it. - if ((FileInfo.isPragmaOnce || FileInfo.isImport) && !TryEnterImported()) + if (FileInfo.isPragmaOnce || FileInfo.isImport) return false; } diff --git a/clang/lib/Lex/ModuleMap.cpp b/clang/lib/Lex/ModuleMap.cpp index 42d55d09ea5..afb2948f05a 100644 --- a/clang/lib/Lex/ModuleMap.cpp +++ b/clang/lib/Lex/ModuleMap.cpp @@ -308,7 +308,7 @@ void ModuleMap::resolveHeader(Module *Mod, setUmbrellaHeaderAsWritten(Mod, *File, Header.FileName, RelativePathName.str()); } else { - Module::Header H = {Header.FileName, std::string(RelativePathName.str()), + Module::Header H = {Header.FileName, std::string(RelativePathName), *File}; addHeader(Mod, H, headerKindToRole(Header.Kind)); } diff --git a/clang/lib/Lex/Preprocessor.cpp b/clang/lib/Lex/Preprocessor.cpp index 64f54c6fc63..7fdb5d4c0d7 100644 --- a/clang/lib/Lex/Preprocessor.cpp +++ b/clang/lib/Lex/Preprocessor.cpp @@ -1457,6 +1457,11 @@ void Preprocessor::emitRestrictExpansionWarning(const Token &Identifier) const { Diag(Info.Location, diag::note_pp_macro_annotation) << 1; } +void Preprocessor::emitRestrictInfNaNWarning(const Token &Identifier, + unsigned DiagSelection) const { + Diag(Identifier, diag::warn_fp_nan_inf_when_disabled) << DiagSelection << 1; +} + void Preprocessor::emitFinalMacroWarning(const Token &Identifier, bool IsUndef) const { const MacroAnnotations &A = diff --git a/clang/lib/Lex/UnicodeCharSets.h b/clang/lib/Lex/UnicodeCharSets.h index 5316d2540b7..b63908024e5 100644 --- a/clang/lib/Lex/UnicodeCharSets.h +++ b/clang/lib/Lex/UnicodeCharSets.h @@ -10,7 +10,7 @@ #include "llvm/Support/UnicodeCharRanges.h" -// Unicode 15.0 XID_Start +// Unicode 15.1 XID_Start static const llvm::sys::UnicodeCharRange XIDStartRanges[] = { {0x0041, 0x005A}, {0x0061, 0x007A}, {0x00AA, 0x00AA}, {0x00B5, 0x00B5}, {0x00BA, 0x00BA}, {0x00C0, 0x00D6}, @@ -233,9 +233,10 @@ static const llvm::sys::UnicodeCharRange XIDStartRanges[] = { {0x1EE8B, 0x1EE9B}, {0x1EEA1, 0x1EEA3}, {0x1EEA5, 0x1EEA9}, {0x1EEAB, 0x1EEBB}, {0x20000, 0x2A6DF}, {0x2A700, 0x2B739}, {0x2B740, 0x2B81D}, {0x2B820, 0x2CEA1}, {0x2CEB0, 0x2EBE0}, - {0x2F800, 0x2FA1D}, {0x30000, 0x3134A}, {0x31350, 0x323AF}}; + {0x2EBF0, 0x2EE5D}, {0x2F800, 0x2FA1D}, {0x30000, 0x3134A}, + {0x31350, 0x323AF}}; -// Unicode 15.0 XID_Continue, excluding XID_Start +// Unicode 15.1 XID_Continue, excluding XID_Start // The Unicode Property XID_Continue is a super set of XID_Start. // To save Space, the table below only contains the codepoints // that are not also in XID_Start. @@ -299,24 +300,25 @@ static const llvm::sys::UnicodeCharRange XIDContinueRanges[] = { {0x1C24, 0x1C37}, {0x1C40, 0x1C49}, {0x1C50, 0x1C59}, {0x1CD0, 0x1CD2}, {0x1CD4, 0x1CE8}, {0x1CED, 0x1CED}, {0x1CF4, 0x1CF4}, {0x1CF7, 0x1CF9}, {0x1DC0, 0x1DFF}, - {0x203F, 0x2040}, {0x2054, 0x2054}, {0x20D0, 0x20DC}, - {0x20E1, 0x20E1}, {0x20E5, 0x20F0}, {0x2CEF, 0x2CF1}, - {0x2D7F, 0x2D7F}, {0x2DE0, 0x2DFF}, {0x302A, 0x302F}, - {0x3099, 0x309A}, {0xA620, 0xA629}, {0xA66F, 0xA66F}, - {0xA674, 0xA67D}, {0xA69E, 0xA69F}, {0xA6F0, 0xA6F1}, - {0xA802, 0xA802}, {0xA806, 0xA806}, {0xA80B, 0xA80B}, - {0xA823, 0xA827}, {0xA82C, 0xA82C}, {0xA880, 0xA881}, - {0xA8B4, 0xA8C5}, {0xA8D0, 0xA8D9}, {0xA8E0, 0xA8F1}, - {0xA8FF, 0xA909}, {0xA926, 0xA92D}, {0xA947, 0xA953}, - {0xA980, 0xA983}, {0xA9B3, 0xA9C0}, {0xA9D0, 0xA9D9}, - {0xA9E5, 0xA9E5}, {0xA9F0, 0xA9F9}, {0xAA29, 0xAA36}, - {0xAA43, 0xAA43}, {0xAA4C, 0xAA4D}, {0xAA50, 0xAA59}, - {0xAA7B, 0xAA7D}, {0xAAB0, 0xAAB0}, {0xAAB2, 0xAAB4}, - {0xAAB7, 0xAAB8}, {0xAABE, 0xAABF}, {0xAAC1, 0xAAC1}, - {0xAAEB, 0xAAEF}, {0xAAF5, 0xAAF6}, {0xABE3, 0xABEA}, - {0xABEC, 0xABED}, {0xABF0, 0xABF9}, {0xFB1E, 0xFB1E}, - {0xFE00, 0xFE0F}, {0xFE20, 0xFE2F}, {0xFE33, 0xFE34}, - {0xFE4D, 0xFE4F}, {0xFF10, 0xFF19}, {0xFF3F, 0xFF3F}, + {0x200C, 0x200D}, {0x203F, 0x2040}, {0x2054, 0x2054}, + {0x20D0, 0x20DC}, {0x20E1, 0x20E1}, {0x20E5, 0x20F0}, + {0x2CEF, 0x2CF1}, {0x2D7F, 0x2D7F}, {0x2DE0, 0x2DFF}, + {0x302A, 0x302F}, {0x3099, 0x309A}, {0x30FB, 0x30FB}, + {0xA620, 0xA629}, {0xA66F, 0xA66F}, {0xA674, 0xA67D}, + {0xA69E, 0xA69F}, {0xA6F0, 0xA6F1}, {0xA802, 0xA802}, + {0xA806, 0xA806}, {0xA80B, 0xA80B}, {0xA823, 0xA827}, + {0xA82C, 0xA82C}, {0xA880, 0xA881}, {0xA8B4, 0xA8C5}, + {0xA8D0, 0xA8D9}, {0xA8E0, 0xA8F1}, {0xA8FF, 0xA909}, + {0xA926, 0xA92D}, {0xA947, 0xA953}, {0xA980, 0xA983}, + {0xA9B3, 0xA9C0}, {0xA9D0, 0xA9D9}, {0xA9E5, 0xA9E5}, + {0xA9F0, 0xA9F9}, {0xAA29, 0xAA36}, {0xAA43, 0xAA43}, + {0xAA4C, 0xAA4D}, {0xAA50, 0xAA59}, {0xAA7B, 0xAA7D}, + {0xAAB0, 0xAAB0}, {0xAAB2, 0xAAB4}, {0xAAB7, 0xAAB8}, + {0xAABE, 0xAABF}, {0xAAC1, 0xAAC1}, {0xAAEB, 0xAAEF}, + {0xAAF5, 0xAAF6}, {0xABE3, 0xABEA}, {0xABEC, 0xABED}, + {0xABF0, 0xABF9}, {0xFB1E, 0xFB1E}, {0xFE00, 0xFE0F}, + {0xFE20, 0xFE2F}, {0xFE33, 0xFE34}, {0xFE4D, 0xFE4F}, + {0xFF10, 0xFF19}, {0xFF3F, 0xFF3F}, {0xFF65, 0xFF65}, {0xFF9E, 0xFF9F}, {0x101FD, 0x101FD}, {0x102E0, 0x102E0}, {0x10376, 0x1037A}, {0x104A0, 0x104A9}, {0x10A01, 0x10A03}, {0x10A05, 0x10A06}, {0x10A0C, 0x10A0F}, {0x10A38, 0x10A3A}, @@ -364,7 +366,8 @@ static const llvm::sys::UnicodeCharRange XIDContinueRanges[] = { {0x1E026, 0x1E02A}, {0x1E08F, 0x1E08F}, {0x1E130, 0x1E136}, {0x1E140, 0x1E149}, {0x1E2AE, 0x1E2AE}, {0x1E2EC, 0x1E2F9}, {0x1E4EC, 0x1E4F9}, {0x1E8D0, 0x1E8D6}, {0x1E944, 0x1E94A}, - {0x1E950, 0x1E959}, {0x1FBF0, 0x1FBF9}, {0xE0100, 0xE01EF}}; + {0x1E950, 0x1E959}, {0x1FBF0, 0x1FBF9}, {0xE0100, 0xE01EF}, +}; // Clang supports the "Mathematical notation profile" as an extension, // as described in https://www.unicode.org/L2/L2022/22230-math-profile.pdf diff --git a/clang/lib/Parse/ParseDecl.cpp b/clang/lib/Parse/ParseDecl.cpp index ed684c5d57b..356e7851ec6 100644 --- a/clang/lib/Parse/ParseDecl.cpp +++ b/clang/lib/Parse/ParseDecl.cpp @@ -79,7 +79,7 @@ TypeResult Parser::ParseTypeName(SourceRange *Range, DeclaratorContext Context, if (DeclaratorInfo.isInvalidType()) return true; - return Actions.ActOnTypeName(getCurScope(), DeclaratorInfo); + return Actions.ActOnTypeName(DeclaratorInfo); } /// Normalizes an attribute name by dropping prefixed and suffixed __. @@ -5011,7 +5011,7 @@ void Parser::ParseEnumSpecifier(SourceLocation StartLoc, DeclSpec &DS, DeclSpecContext::DSC_type_specifier); Declarator DeclaratorInfo(DS, ParsedAttributesView::none(), DeclaratorContext::TypeName); - BaseType = Actions.ActOnTypeName(getCurScope(), DeclaratorInfo); + BaseType = Actions.ActOnTypeName(DeclaratorInfo); BaseRange = SourceRange(ColonLoc, DeclaratorInfo.getSourceRange().getEnd()); @@ -6791,7 +6791,13 @@ void Parser::ParseDirectDeclarator(Declarator &D) { } else if (Tok.isRegularKeywordAttribute()) { // For consistency with attribute parsing. Diag(Tok, diag::err_keyword_not_allowed) << Tok.getIdentifierInfo(); + bool TakesArgs = doesKeywordAttributeTakeArgs(Tok.getKind()); ConsumeToken(); + if (TakesArgs) { + BalancedDelimiterTracker T(*this, tok::l_paren); + if (!T.consumeOpen()) + T.skipToEnd(); + } } else if (Tok.is(tok::kw_requires) && D.hasGroupingParens()) { // This declarator is declaring a function, but the requires clause is // in the wrong place: @@ -8045,6 +8051,71 @@ bool Parser::TryAltiVecTokenOutOfLine(DeclSpec &DS, SourceLocation Loc, return false; } +TypeResult Parser::ParseTypeFromString(StringRef TypeStr, StringRef Context, + SourceLocation IncludeLoc) { + // Consume (unexpanded) tokens up to the end-of-directive. + SmallVector Tokens; + { + // Create a new buffer from which we will parse the type. + auto &SourceMgr = PP.getSourceManager(); + FileID FID = SourceMgr.createFileID( + llvm::MemoryBuffer::getMemBufferCopy(TypeStr, Context), SrcMgr::C_User, + 0, 0, IncludeLoc); + + // Form a new lexer that references the buffer. + Lexer L(FID, SourceMgr.getBufferOrFake(FID), PP); + L.setParsingPreprocessorDirective(true); + + // Lex the tokens from that buffer. + Token Tok; + do { + L.Lex(Tok); + Tokens.push_back(Tok); + } while (Tok.isNot(tok::eod)); + } + + // Replace the "eod" token with an "eof" token identifying the end of + // the provided string. + Token &EndToken = Tokens.back(); + EndToken.startToken(); + EndToken.setKind(tok::eof); + EndToken.setLocation(Tok.getLocation()); + EndToken.setEofData(TypeStr.data()); + + // Add the current token back. + Tokens.push_back(Tok); + + // Enter the tokens into the token stream. + PP.EnterTokenStream(Tokens, /*DisableMacroExpansion=*/false, + /*IsReinject=*/false); + + // Consume the current token so that we'll start parsing the tokens we + // added to the stream. + ConsumeAnyToken(); + + // Enter a new scope. + ParseScope LocalScope(this, 0); + + // Parse the type. + TypeResult Result = ParseTypeName(nullptr); + + // Check if we parsed the whole thing. + if (Result.isUsable() && + (Tok.isNot(tok::eof) || Tok.getEofData() != TypeStr.data())) { + Diag(Tok.getLocation(), diag::err_type_unparsed); + } + + // There could be leftover tokens (e.g. because of an error). + // Skip through until we reach the 'end of directive' token. + while (Tok.isNot(tok::eof)) + ConsumeAnyToken(); + + // Consume the end token. + if (Tok.is(tok::eof) && Tok.getEofData() == TypeStr.data()) + ConsumeAnyToken(); + return Result; +} + void Parser::DiagnoseBitIntUse(const Token &Tok) { // If the token is for _ExtInt, diagnose it as being deprecated. Otherwise, // the token is about _BitInt and gets (potentially) diagnosed as use of an diff --git a/clang/lib/Parse/ParseDeclCXX.cpp b/clang/lib/Parse/ParseDeclCXX.cpp index d97081da420..c0d771dc93d 100644 --- a/clang/lib/Parse/ParseDeclCXX.cpp +++ b/clang/lib/Parse/ParseDeclCXX.cpp @@ -1290,7 +1290,7 @@ TypeResult Parser::ParseBaseTypeSpecifier(SourceLocation &BaseLoc, Declarator DeclaratorInfo(DS, ParsedAttributesView::none(), DeclaratorContext::TypeName); - return Actions.ActOnTypeName(getCurScope(), DeclaratorInfo); + return Actions.ActOnTypeName(DeclaratorInfo); } // Check whether we have a template-id that names a type. @@ -1385,7 +1385,7 @@ TypeResult Parser::ParseBaseTypeSpecifier(SourceLocation &BaseLoc, Declarator DeclaratorInfo(DS, ParsedAttributesView::none(), DeclaratorContext::TypeName); - return Actions.ActOnTypeName(getCurScope(), DeclaratorInfo); + return Actions.ActOnTypeName(DeclaratorInfo); } void Parser::ParseMicrosoftInheritanceClassAttributes(ParsedAttributes &attrs) { @@ -1890,7 +1890,13 @@ void Parser::ParseClassSpecifier(tok::TokenKind TagTokKind, if (!SkipUntil(tok::r_paren, StopAtSemi)) break; } else if (Tok.isRegularKeywordAttribute()) { + bool TakesArgs = doesKeywordAttributeTakeArgs(Tok.getKind()); ConsumeToken(); + if (TakesArgs) { + BalancedDelimiterTracker T(*this, tok::l_paren); + if (!T.consumeOpen()) + T.skipToEnd(); + } } else { break; } @@ -4539,8 +4545,18 @@ void Parser::ParseCXX11AttributeSpecifierInternal(ParsedAttributes &Attrs, if (Tok.isRegularKeywordAttribute()) { SourceLocation Loc = Tok.getLocation(); IdentifierInfo *AttrName = Tok.getIdentifierInfo(); - Attrs.addNew(AttrName, Loc, nullptr, Loc, nullptr, 0, Tok.getKind()); + ParsedAttr::Form Form = ParsedAttr::Form(Tok.getKind()); + bool TakesArgs = doesKeywordAttributeTakeArgs(Tok.getKind()); ConsumeToken(); + if (TakesArgs) { + if (!Tok.is(tok::l_paren)) + Diag(Tok.getLocation(), diag::err_expected_lparen_after) << AttrName; + else + ParseAttributeArgsCommon(AttrName, Loc, Attrs, EndLoc, + /*ScopeName*/ nullptr, + /*ScopeLoc*/ Loc, Form); + } else + Attrs.addNew(AttrName, Loc, nullptr, Loc, nullptr, 0, Form); return; } @@ -4706,11 +4722,13 @@ SourceLocation Parser::SkipCXX11Attributes() { T.consumeOpen(); T.skipToEnd(); EndLoc = T.getCloseLocation(); - } else if (Tok.isRegularKeywordAttribute()) { + } else if (Tok.isRegularKeywordAttribute() && + !doesKeywordAttributeTakeArgs(Tok.getKind())) { EndLoc = Tok.getLocation(); ConsumeToken(); } else { - assert(Tok.is(tok::kw_alignas) && "not an attribute specifier"); + assert((Tok.is(tok::kw_alignas) || Tok.isRegularKeywordAttribute()) && + "not an attribute specifier"); ConsumeToken(); BalancedDelimiterTracker T(*this, tok::l_paren); if (!T.consumeOpen()) diff --git a/clang/lib/Parse/ParseExpr.cpp b/clang/lib/Parse/ParseExpr.cpp index dcfd290d39c..e862856a08c 100644 --- a/clang/lib/Parse/ParseExpr.cpp +++ b/clang/lib/Parse/ParseExpr.cpp @@ -1243,8 +1243,7 @@ ExprResult Parser::ParseCastExpression(CastParseKind ParseKind, Declarator DeclaratorInfo(DS, ParsedAttributesView::none(), DeclaratorContext::TypeName); - TypeResult Ty = Actions.ActOnTypeName(getCurScope(), - DeclaratorInfo); + TypeResult Ty = Actions.ActOnTypeName(DeclaratorInfo); if (Ty.isInvalid()) break; @@ -1538,7 +1537,7 @@ ExprResult Parser::ParseCastExpression(CastParseKind ParseKind, Declarator DeclaratorInfo(DS, ParsedAttributesView::none(), DeclaratorContext::TypeName); - TypeResult Ty = Actions.ActOnTypeName(getCurScope(), DeclaratorInfo); + TypeResult Ty = Actions.ActOnTypeName(DeclaratorInfo); if (Ty.isInvalid()) break; @@ -3096,7 +3095,7 @@ Parser::ParseParenExpression(ParenParseOption &ExprType, bool stopIfCastExpr, TypeResult Ty; { InMessageExpressionRAIIObject InMessage(*this, false); - Ty = Actions.ActOnTypeName(getCurScope(), DeclaratorInfo); + Ty = Actions.ActOnTypeName(DeclaratorInfo); } Result = ParseObjCMessageExpressionBody(SourceLocation(), SourceLocation(), @@ -3111,7 +3110,7 @@ Parser::ParseParenExpression(ParenParseOption &ExprType, bool stopIfCastExpr, TypeResult Ty; { InMessageExpressionRAIIObject InMessage(*this, false); - Ty = Actions.ActOnTypeName(getCurScope(), DeclaratorInfo); + Ty = Actions.ActOnTypeName(DeclaratorInfo); } return ParseCompoundLiteralExpression(Ty.get(), OpenLoc, RParenLoc); } @@ -3123,7 +3122,7 @@ Parser::ParseParenExpression(ParenParseOption &ExprType, bool stopIfCastExpr, TypeResult Ty; { InMessageExpressionRAIIObject InMessage(*this, false); - Ty = Actions.ActOnTypeName(getCurScope(), DeclaratorInfo); + Ty = Actions.ActOnTypeName(DeclaratorInfo); } if(Ty.isInvalid()) { @@ -3170,7 +3169,7 @@ Parser::ParseParenExpression(ParenParseOption &ExprType, bool stopIfCastExpr, TypeResult Ty; { InMessageExpressionRAIIObject InMessage(*this, false); - Ty = Actions.ActOnTypeName(getCurScope(), DeclaratorInfo); + Ty = Actions.ActOnTypeName(DeclaratorInfo); } CastTy = Ty.get(); return ExprResult(); diff --git a/clang/lib/Parse/ParseExprCXX.cpp b/clang/lib/Parse/ParseExprCXX.cpp index ef9ea657520..d61f414406f 100644 --- a/clang/lib/Parse/ParseExprCXX.cpp +++ b/clang/lib/Parse/ParseExprCXX.cpp @@ -1916,7 +1916,7 @@ ExprResult Parser::ParseCXXTypeConstructExpression(const DeclSpec &DS) { Declarator DeclaratorInfo(DS, ParsedAttributesView::none(), DeclaratorContext::FunctionalCast); - ParsedType TypeRep = Actions.ActOnTypeName(getCurScope(), DeclaratorInfo).get(); + ParsedType TypeRep = Actions.ActOnTypeName(DeclaratorInfo).get(); assert((Tok.is(tok::l_paren) || (getLangOpts().CPlusPlus11 && Tok.is(tok::l_brace))) @@ -2815,7 +2815,7 @@ bool Parser::ParseUnqualifiedIdOperator(CXXScopeSpec &SS, bool EnteringContext, ParseDeclaratorInternal(D, /*DirectDeclParser=*/nullptr); // Finish up the type. - TypeResult Ty = Actions.ActOnTypeName(getCurScope(), D); + TypeResult Ty = Actions.ActOnTypeName(D); if (Ty.isInvalid()) return true; @@ -3252,8 +3252,7 @@ Parser::ParseCXXNewExpression(bool UseGlobal, SourceLocation Start) { ConstructorLParen = T.getOpenLocation(); if (Tok.isNot(tok::r_paren)) { auto RunSignatureHelp = [&]() { - ParsedType TypeRep = - Actions.ActOnTypeName(getCurScope(), DeclaratorInfo).get(); + ParsedType TypeRep = Actions.ActOnTypeName(DeclaratorInfo).get(); QualType PreferredType; // ActOnTypeName might adjust DeclaratorInfo and return a null type even // the passing DeclaratorInfo is valid, e.g. running SignatureHelp on @@ -4037,7 +4036,7 @@ Parser::ParseCXXAmbiguousParenExpression(ParenParseOption &ExprType, if (DeclaratorInfo.isInvalidType()) return ExprError(); - TypeResult Ty = Actions.ActOnTypeName(getCurScope(), DeclaratorInfo); + TypeResult Ty = Actions.ActOnTypeName(DeclaratorInfo); return ParseCompoundLiteralExpression(Ty.get(), Tracker.getOpenLocation(), Tracker.getCloseLocation()); diff --git a/clang/lib/Parse/ParseObjc.cpp b/clang/lib/Parse/ParseObjc.cpp index c0261c462b8..849fd1ac95a 100644 --- a/clang/lib/Parse/ParseObjc.cpp +++ b/clang/lib/Parse/ParseObjc.cpp @@ -1332,7 +1332,7 @@ ParsedType Parser::ParseObjCTypeName(ObjCDeclSpec &DS, DS.getNullabilityLoc(), addedToDeclSpec); - TypeResult type = Actions.ActOnTypeName(getCurScope(), declarator); + TypeResult type = Actions.ActOnTypeName(declarator); if (!type.isInvalid()) Ty = type.get(); @@ -1747,7 +1747,7 @@ void Parser::parseObjCTypeArgsOrProtocolQualifiers( // Form a declarator to turn this into a type. Declarator D(DS, ParsedAttributesView::none(), DeclaratorContext::TypeName); - TypeResult fullTypeArg = Actions.ActOnTypeName(getCurScope(), D); + TypeResult fullTypeArg = Actions.ActOnTypeName(D); if (fullTypeArg.isUsable()) { typeArgs.push_back(fullTypeArg.get()); if (!foundValidTypeId) { @@ -3024,7 +3024,7 @@ bool Parser::ParseObjCXXMessageReceiver(bool &IsExpr, void *&TypeOrExpr) { // remainder of the class message. Declarator DeclaratorInfo(DS, ParsedAttributesView::none(), DeclaratorContext::TypeName); - TypeResult Type = Actions.ActOnTypeName(getCurScope(), DeclaratorInfo); + TypeResult Type = Actions.ActOnTypeName(DeclaratorInfo); if (Type.isInvalid()) return true; diff --git a/clang/lib/Parse/ParseOpenACC.cpp b/clang/lib/Parse/ParseOpenACC.cpp index fc82324e235..9f7e63ecdc9 100644 --- a/clang/lib/Parse/ParseOpenACC.cpp +++ b/clang/lib/Parse/ParseOpenACC.cpp @@ -89,16 +89,43 @@ OpenACCClauseKind getOpenACCClauseKind(Token Tok) { return llvm::StringSwitch( Tok.getIdentifierInfo()->getName()) + .Case("attach", OpenACCClauseKind::Attach) .Case("auto", OpenACCClauseKind::Auto) + .Case("bind", OpenACCClauseKind::Bind) + .Case("create", OpenACCClauseKind::Create) + .Case("collapse", OpenACCClauseKind::Collapse) + .Case("copy", OpenACCClauseKind::Copy) + .Case("copyin", OpenACCClauseKind::CopyIn) + .Case("copyout", OpenACCClauseKind::CopyOut) .Case("default", OpenACCClauseKind::Default) + .Case("default_async", OpenACCClauseKind::DefaultAsync) + .Case("delete", OpenACCClauseKind::Delete) + .Case("detach", OpenACCClauseKind::Detach) + .Case("device", OpenACCClauseKind::Device) + .Case("device_num", OpenACCClauseKind::DeviceNum) + .Case("device_resident", OpenACCClauseKind::DeviceResident) + .Case("device_type", OpenACCClauseKind::DeviceType) + .Case("deviceptr", OpenACCClauseKind::DevicePtr) + .Case("dtype", OpenACCClauseKind::DType) .Case("finalize", OpenACCClauseKind::Finalize) + .Case("firstprivate", OpenACCClauseKind::FirstPrivate) + .Case("host", OpenACCClauseKind::Host) .Case("if", OpenACCClauseKind::If) .Case("if_present", OpenACCClauseKind::IfPresent) .Case("independent", OpenACCClauseKind::Independent) + .Case("link", OpenACCClauseKind::Link) + .Case("no_create", OpenACCClauseKind::NoCreate) + .Case("num_gangs", OpenACCClauseKind::NumGangs) + .Case("num_workers", OpenACCClauseKind::NumWorkers) .Case("nohost", OpenACCClauseKind::NoHost) + .Case("present", OpenACCClauseKind::Present) + .Case("private", OpenACCClauseKind::Private) + .Case("reduction", OpenACCClauseKind::Reduction) .Case("self", OpenACCClauseKind::Self) .Case("seq", OpenACCClauseKind::Seq) + .Case("use_device", OpenACCClauseKind::UseDevice) .Case("vector", OpenACCClauseKind::Vector) + .Case("vector_length", OpenACCClauseKind::VectorLength) .Case("worker", OpenACCClauseKind::Worker) .Default(OpenACCClauseKind::Invalid); } @@ -132,6 +159,10 @@ enum class OpenACCSpecialTokenKind { ReadOnly, DevNum, Queues, + Zero, + Force, + Num, + Length, }; bool isOpenACCSpecialToken(OpenACCSpecialTokenKind Kind, Token Tok) { @@ -145,10 +176,60 @@ bool isOpenACCSpecialToken(OpenACCSpecialTokenKind Kind, Token Tok) { return Tok.getIdentifierInfo()->isStr("devnum"); case OpenACCSpecialTokenKind::Queues: return Tok.getIdentifierInfo()->isStr("queues"); + case OpenACCSpecialTokenKind::Zero: + return Tok.getIdentifierInfo()->isStr("zero"); + case OpenACCSpecialTokenKind::Force: + return Tok.getIdentifierInfo()->isStr("force"); + case OpenACCSpecialTokenKind::Num: + return Tok.getIdentifierInfo()->isStr("num"); + case OpenACCSpecialTokenKind::Length: + return Tok.getIdentifierInfo()->isStr("length"); } llvm_unreachable("Unknown 'Kind' Passed"); } +/// Used for cases where we have a token we want to check against an +/// 'identifier-like' token, but don't want to give awkward error messages in +/// cases where it is accidentially a keyword. +bool isTokenIdentifierOrKeyword(Parser &P, Token Tok) { + if (Tok.is(tok::identifier)) + return true; + + if (!Tok.isAnnotation() && Tok.getIdentifierInfo() && + Tok.getIdentifierInfo()->isKeyword(P.getLangOpts())) + return true; + + return false; +} + +/// Parses and consumes an identifer followed immediately by a single colon, and +/// diagnoses if it is not the 'special token' kind that we require. Used when +/// the tag is the only valid value. +/// Return 'true' if the special token was matched, false if no special token, +/// or an invalid special token was found. +template +bool tryParseAndConsumeSpecialTokenKind(Parser &P, OpenACCSpecialTokenKind Kind, + DirOrClauseTy DirOrClause) { + Token IdentTok = P.getCurToken(); + // If this is an identifier-like thing followed by ':', it is one of the + // OpenACC 'special' name tags, so consume it. + if (isTokenIdentifierOrKeyword(P, IdentTok) && P.NextToken().is(tok::colon)) { + P.ConsumeToken(); + P.ConsumeToken(); + + if (!isOpenACCSpecialToken(Kind, IdentTok)) { + P.Diag(IdentTok, diag::err_acc_invalid_tag_kind) + << IdentTok.getIdentifierInfo() << DirOrClause + << std::is_same_v; + return false; + } + + return true; + } + + return false; +} + bool isOpenACCDirectiveKind(OpenACCDirectiveKind Kind, Token Tok) { if (!Tok.is(tok::identifier)) return false; @@ -198,16 +279,53 @@ bool isOpenACCDirectiveKind(OpenACCDirectiveKind Kind, Token Tok) { llvm_unreachable("Unknown 'Kind' Passed"); } +OpenACCReductionOperator ParseReductionOperator(Parser &P) { + // If there is no colon, treat as if the reduction operator was missing, else + // we probably will not recover from it in the case where an expression starts + // with one of the operator tokens. + if (P.NextToken().isNot(tok::colon)) { + P.Diag(P.getCurToken(), diag::err_acc_expected_reduction_operator); + return OpenACCReductionOperator::Invalid; + } + Token ReductionKindTok = P.getCurToken(); + // Consume both the kind and the colon. + P.ConsumeToken(); + P.ConsumeToken(); + + switch (ReductionKindTok.getKind()) { + case tok::plus: + return OpenACCReductionOperator::Addition; + case tok::star: + return OpenACCReductionOperator::Multiplication; + case tok::amp: + return OpenACCReductionOperator::BitwiseAnd; + case tok::pipe: + return OpenACCReductionOperator::BitwiseOr; + case tok::caret: + return OpenACCReductionOperator::BitwiseXOr; + case tok::ampamp: + return OpenACCReductionOperator::And; + case tok::pipepipe: + return OpenACCReductionOperator::Or; + case tok::identifier: + if (ReductionKindTok.getIdentifierInfo()->isStr("max")) + return OpenACCReductionOperator::Max; + if (ReductionKindTok.getIdentifierInfo()->isStr("min")) + return OpenACCReductionOperator::Min; + LLVM_FALLTHROUGH; + default: + P.Diag(ReductionKindTok, diag::err_acc_invalid_reduction_operator); + return OpenACCReductionOperator::Invalid; + } + llvm_unreachable("Reduction op token kind not caught by 'default'?"); +} + /// Used for cases where we expect an identifier-like token, but don't want to /// give awkward error messages in cases where it is accidentially a keyword. bool expectIdentifierOrKeyword(Parser &P) { Token Tok = P.getCurToken(); - if (Tok.is(tok::identifier)) - return false; - - if (!Tok.isAnnotation() && Tok.getIdentifierInfo() && - Tok.getIdentifierInfo()->isKeyword(P.getLangOpts())) + if (isTokenIdentifierOrKeyword(P, Tok)) return false; P.Diag(P.getCurToken(), diag::err_expected) << tok::identifier; @@ -329,12 +447,73 @@ OpenACCDirectiveKind ParseOpenACCDirectiveKind(Parser &P) { return DirKind; } -bool ClauseHasOptionalParens(OpenACCClauseKind Kind) { - return Kind == OpenACCClauseKind::Self; +enum ClauseParensKind { + None, + Optional, + Required +}; + +ClauseParensKind getClauseParensKind(OpenACCDirectiveKind DirKind, + OpenACCClauseKind Kind) { + switch (Kind) { + case OpenACCClauseKind::Self: + return DirKind == OpenACCDirectiveKind::Update ? ClauseParensKind::Required + : ClauseParensKind::Optional; + case OpenACCClauseKind::Worker: + case OpenACCClauseKind::Vector: + return ClauseParensKind::Optional; + + case OpenACCClauseKind::Default: + case OpenACCClauseKind::If: + case OpenACCClauseKind::Create: + case OpenACCClauseKind::Copy: + case OpenACCClauseKind::CopyIn: + case OpenACCClauseKind::CopyOut: + case OpenACCClauseKind::UseDevice: + case OpenACCClauseKind::NoCreate: + case OpenACCClauseKind::Present: + case OpenACCClauseKind::DevicePtr: + case OpenACCClauseKind::Attach: + case OpenACCClauseKind::Detach: + case OpenACCClauseKind::Private: + case OpenACCClauseKind::FirstPrivate: + case OpenACCClauseKind::Delete: + case OpenACCClauseKind::DeviceResident: + case OpenACCClauseKind::Device: + case OpenACCClauseKind::Link: + case OpenACCClauseKind::Host: + case OpenACCClauseKind::Reduction: + case OpenACCClauseKind::Collapse: + case OpenACCClauseKind::Bind: + case OpenACCClauseKind::VectorLength: + case OpenACCClauseKind::NumGangs: + case OpenACCClauseKind::NumWorkers: + case OpenACCClauseKind::DeviceNum: + case OpenACCClauseKind::DefaultAsync: + case OpenACCClauseKind::DeviceType: + case OpenACCClauseKind::DType: + return ClauseParensKind::Required; + + case OpenACCClauseKind::Auto: + case OpenACCClauseKind::Finalize: + case OpenACCClauseKind::IfPresent: + case OpenACCClauseKind::Independent: + case OpenACCClauseKind::Invalid: + case OpenACCClauseKind::NoHost: + case OpenACCClauseKind::Seq: + return ClauseParensKind::None; + } + llvm_unreachable("Unhandled clause kind"); } -bool ClauseHasRequiredParens(OpenACCClauseKind Kind) { - return Kind == OpenACCClauseKind::Default || Kind == OpenACCClauseKind::If; +bool ClauseHasOptionalParens(OpenACCDirectiveKind DirKind, + OpenACCClauseKind Kind) { + return getClauseParensKind(DirKind, Kind) == ClauseParensKind::Optional; +} + +bool ClauseHasRequiredParens(OpenACCDirectiveKind DirKind, + OpenACCClauseKind Kind) { + return getClauseParensKind(DirKind, Kind) == ClauseParensKind::Required; } ExprResult ParseOpenACCConditionalExpr(Parser &P) { @@ -345,91 +524,6 @@ ExprResult ParseOpenACCConditionalExpr(Parser &P) { return P.getActions().CorrectDelayedTyposInExpr(P.ParseExpression()); } -bool ParseOpenACCClauseParams(Parser &P, OpenACCClauseKind Kind) { - BalancedDelimiterTracker Parens(P, tok::l_paren, - tok::annot_pragma_openacc_end); - - if (ClauseHasRequiredParens(Kind)) { - if (Parens.expectAndConsume()) { - // We are missing a paren, so assume that the person just forgot the - // parameter. Return 'false' so we try to continue on and parse the next - // clause. - P.SkipUntil(tok::comma, tok::r_paren, tok::annot_pragma_openacc_end, - Parser::StopBeforeMatch); - return false; - } - - switch (Kind) { - case OpenACCClauseKind::Default: { - Token DefKindTok = P.getCurToken(); - - if (expectIdentifierOrKeyword(P)) - break; - - P.ConsumeToken(); - - if (getOpenACCDefaultClauseKind(DefKindTok) == - OpenACCDefaultClauseKind::Invalid) - P.Diag(DefKindTok, diag::err_acc_invalid_default_clause_kind); - - break; - } - case OpenACCClauseKind::If: { - ExprResult CondExpr = ParseOpenACCConditionalExpr(P); - // An invalid expression can be just about anything, so just give up on - // this clause list. - if (CondExpr.isInvalid()) - return true; - break; - } - default: - llvm_unreachable("Not a required parens type?"); - } - - return Parens.consumeClose(); - } else if (ClauseHasOptionalParens(Kind)) { - if (!Parens.consumeOpen()) { - switch (Kind) { - case OpenACCClauseKind::Self: { - ExprResult CondExpr = ParseOpenACCConditionalExpr(P); - // An invalid expression can be just about anything, so just give up on - // this clause list. - if (CondExpr.isInvalid()) - return true; - break; - } - default: - llvm_unreachable("Not an optional parens type?"); - } - Parens.consumeClose(); - } - } - return false; -} - -// The OpenACC Clause List is a comma or space-delimited list of clauses (see -// the comment on ParseOpenACCClauseList). The concept of a 'clause' doesn't -// really have its owner grammar and each individual one has its own definition. -// However, they all are named with a single-identifier (or auto/default!) -// token, followed in some cases by either braces or parens. -bool ParseOpenACCClause(Parser &P) { - // A number of clause names are actually keywords, so accept a keyword that - // can be converted to a name. - if (expectIdentifierOrKeyword(P)) - return true; - - OpenACCClauseKind Kind = getOpenACCClauseKind(P.getCurToken()); - - if (Kind == OpenACCClauseKind::Invalid) - return P.Diag(P.getCurToken(), diag::err_acc_invalid_clause) - << P.getCurToken().getIdentifierInfo(); - - // Consume the clause name. - P.ConsumeToken(); - - return ParseOpenACCClauseParams(P, Kind); -} - // Skip until we see the end of pragma token, but don't consume it. This is us // just giving up on the rest of the pragma so we can continue executing. We // have to do this because 'SkipUntil' considers paren balancing, which isn't @@ -439,29 +533,265 @@ void SkipUntilEndOfDirective(Parser &P) { P.ConsumeAnyToken(); } +} // namespace + // OpenACC 3.3, section 1.7: // To simplify the specification and convey appropriate constraint information, // a pqr-list is a comma-separated list of pdr items. The one exception is a // clause-list, which is a list of one or more clauses optionally separated by // commas. -void ParseOpenACCClauseList(Parser &P) { +void Parser::ParseOpenACCClauseList(OpenACCDirectiveKind DirKind) { bool FirstClause = true; - while (P.getCurToken().isNot(tok::annot_pragma_openacc_end)) { + while (getCurToken().isNot(tok::annot_pragma_openacc_end)) { // Comma is optional in a clause-list. - if (!FirstClause && P.getCurToken().is(tok::comma)) - P.ConsumeToken(); + if (!FirstClause && getCurToken().is(tok::comma)) + ConsumeToken(); FirstClause = false; // Recovering from a bad clause is really difficult, so we just give up on // error. - if (ParseOpenACCClause(P)) { - SkipUntilEndOfDirective(P); + if (ParseOpenACCClause(DirKind)) { + SkipUntilEndOfDirective(*this); return; } } } -} // namespace +ExprResult Parser::ParseOpenACCIntExpr() { + // FIXME: this is required to be an integer expression (or dependent), so we + // should ensure that is the case by passing this to SEMA here. + return getActions().CorrectDelayedTyposInExpr(ParseAssignmentExpression()); +} + +bool Parser::ParseOpenACCClauseVarList(OpenACCClauseKind Kind) { + // FIXME: Future clauses will require 'special word' parsing, check for one, + // then parse it based on whether it is a clause that requires a 'special + // word'. + (void)Kind; + + // If the var parsing fails, skip until the end of the directive as this is + // an expression and gets messy if we try to continue otherwise. + if (ParseOpenACCVar()) + return true; + + while (!getCurToken().isOneOf(tok::r_paren, tok::annot_pragma_openacc_end)) { + ExpectAndConsume(tok::comma); + + // If the var parsing fails, skip until the end of the directive as this is + // an expression and gets messy if we try to continue otherwise. + if (ParseOpenACCVar()) + return true; + } + return false; +} + +/// OpenACC 3.3 Section 2.4: +/// The argument to the device_type clause is a comma-separated list of one or +/// more device architecture name identifiers, or an asterisk. +/// +/// The syntax of the device_type clause is +/// device_type( * ) +/// device_type( device-type-list ) +/// +/// The device_type clause may be abbreviated to dtype. +bool Parser::ParseOpenACCDeviceTypeList() { + + if (expectIdentifierOrKeyword(*this)) { + SkipUntil(tok::r_paren, tok::annot_pragma_openacc_end, + Parser::StopBeforeMatch); + return false; + } + ConsumeToken(); + + while (!getCurToken().isOneOf(tok::r_paren, tok::annot_pragma_openacc_end)) { + ExpectAndConsume(tok::comma); + + if (expectIdentifierOrKeyword(*this)) { + SkipUntil(tok::r_paren, tok::annot_pragma_openacc_end, + Parser::StopBeforeMatch); + return false; + } + ConsumeToken(); + } + return false; +} + +// The OpenACC Clause List is a comma or space-delimited list of clauses (see +// the comment on ParseOpenACCClauseList). The concept of a 'clause' doesn't +// really have its owner grammar and each individual one has its own definition. +// However, they all are named with a single-identifier (or auto/default!) +// token, followed in some cases by either braces or parens. +bool Parser::ParseOpenACCClause(OpenACCDirectiveKind DirKind) { + // A number of clause names are actually keywords, so accept a keyword that + // can be converted to a name. + if (expectIdentifierOrKeyword(*this)) + return true; + + OpenACCClauseKind Kind = getOpenACCClauseKind(getCurToken()); + + if (Kind == OpenACCClauseKind::Invalid) + return Diag(getCurToken(), diag::err_acc_invalid_clause) + << getCurToken().getIdentifierInfo(); + + // Consume the clause name. + ConsumeToken(); + + return ParseOpenACCClauseParams(DirKind, Kind); +} + +bool Parser::ParseOpenACCClauseParams(OpenACCDirectiveKind DirKind, + OpenACCClauseKind Kind) { + BalancedDelimiterTracker Parens(*this, tok::l_paren, + tok::annot_pragma_openacc_end); + + if (ClauseHasRequiredParens(DirKind, Kind)) { + if (Parens.expectAndConsume()) { + // We are missing a paren, so assume that the person just forgot the + // parameter. Return 'false' so we try to continue on and parse the next + // clause. + SkipUntil(tok::comma, tok::r_paren, tok::annot_pragma_openacc_end, + Parser::StopBeforeMatch); + return false; + } + + switch (Kind) { + case OpenACCClauseKind::Default: { + Token DefKindTok = getCurToken(); + + if (expectIdentifierOrKeyword(*this)) + break; + + ConsumeToken(); + + if (getOpenACCDefaultClauseKind(DefKindTok) == + OpenACCDefaultClauseKind::Invalid) + Diag(DefKindTok, diag::err_acc_invalid_default_clause_kind); + + break; + } + case OpenACCClauseKind::If: { + ExprResult CondExpr = ParseOpenACCConditionalExpr(*this); + // An invalid expression can be just about anything, so just give up on + // this clause list. + if (CondExpr.isInvalid()) + return true; + break; + } + case OpenACCClauseKind::CopyIn: + tryParseAndConsumeSpecialTokenKind( + *this, OpenACCSpecialTokenKind::ReadOnly, Kind); + if (ParseOpenACCClauseVarList(Kind)) + return true; + break; + case OpenACCClauseKind::Create: + case OpenACCClauseKind::CopyOut: + tryParseAndConsumeSpecialTokenKind(*this, OpenACCSpecialTokenKind::Zero, + Kind); + if (ParseOpenACCClauseVarList(Kind)) + return true; + break; + case OpenACCClauseKind::Reduction: + // If we're missing a clause-kind (or it is invalid), see if we can parse + // the var-list anyway. + ParseReductionOperator(*this); + if (ParseOpenACCClauseVarList(Kind)) + return true; + break; + case OpenACCClauseKind::Self: + // The 'self' clause is a var-list instead of a 'condition' in the case of + // the 'update' clause, so we have to handle it here. U se an assert to + // make sure we get the right differentiator. + assert(DirKind == OpenACCDirectiveKind::Update); + LLVM_FALLTHROUGH; + case OpenACCClauseKind::Attach: + case OpenACCClauseKind::Copy: + case OpenACCClauseKind::Delete: + case OpenACCClauseKind::Detach: + case OpenACCClauseKind::Device: + case OpenACCClauseKind::DeviceResident: + case OpenACCClauseKind::DevicePtr: + case OpenACCClauseKind::FirstPrivate: + case OpenACCClauseKind::Host: + case OpenACCClauseKind::Link: + case OpenACCClauseKind::NoCreate: + case OpenACCClauseKind::Present: + case OpenACCClauseKind::Private: + case OpenACCClauseKind::UseDevice: + if (ParseOpenACCClauseVarList(Kind)) + return true; + break; + case OpenACCClauseKind::Collapse: { + tryParseAndConsumeSpecialTokenKind(*this, OpenACCSpecialTokenKind::Force, + Kind); + ExprResult NumLoops = + getActions().CorrectDelayedTyposInExpr(ParseConstantExpression()); + if (NumLoops.isInvalid()) + return true; + break; + } + case OpenACCClauseKind::Bind: { + ExprResult BindArg = ParseOpenACCBindClauseArgument(); + if (BindArg.isInvalid()) + return true; + break; + } + case OpenACCClauseKind::NumGangs: + case OpenACCClauseKind::NumWorkers: + case OpenACCClauseKind::DeviceNum: + case OpenACCClauseKind::DefaultAsync: + case OpenACCClauseKind::VectorLength: { + ExprResult IntExpr = ParseOpenACCIntExpr(); + if (IntExpr.isInvalid()) + return true; + break; + } + case OpenACCClauseKind::DType: + case OpenACCClauseKind::DeviceType: + if (getCurToken().is(tok::star)) { + // FIXME: We want to mark that this is an 'everything else' type of + // device_type in Sema. + ConsumeToken(); + } else if (ParseOpenACCDeviceTypeList()) { + return true; + } + break; + default: + llvm_unreachable("Not a required parens type?"); + } + + return Parens.consumeClose(); + } else if (ClauseHasOptionalParens(DirKind, Kind)) { + if (!Parens.consumeOpen()) { + switch (Kind) { + case OpenACCClauseKind::Self: { + assert(DirKind != OpenACCDirectiveKind::Update); + ExprResult CondExpr = ParseOpenACCConditionalExpr(*this); + // An invalid expression can be just about anything, so just give up on + // this clause list. + if (CondExpr.isInvalid()) + return true; + break; + } + case OpenACCClauseKind::Vector: + case OpenACCClauseKind::Worker: { + tryParseAndConsumeSpecialTokenKind(*this, + Kind == OpenACCClauseKind::Vector + ? OpenACCSpecialTokenKind::Length + : OpenACCSpecialTokenKind::Num, + Kind); + ExprResult IntExpr = ParseOpenACCIntExpr(); + if (IntExpr.isInvalid()) + return true; + break; + } + default: + llvm_unreachable("Not an optional parens type?"); + } + Parens.consumeClose(); + } + } + return false; +} /// OpenACC 3.3, section 2.16: /// In this section and throughout the specification, the term wait-argument @@ -527,7 +857,7 @@ bool Parser::ParseOpenACCWaitArgument() { ExprResult Parser::ParseOpenACCIDExpression() { ExprResult Res; if (getLangOpts().CPlusPlus) { - Res = ParseCXXIdExpression(/*isAddressOfOperand=*/false); + Res = ParseCXXIdExpression(/*isAddressOfOperand=*/true); } else { // There isn't anything quite the same as ParseCXXIdExpression for C, so we // need to get the identifier, then call into Sema ourselves. @@ -554,6 +884,25 @@ ExprResult Parser::ParseOpenACCIDExpression() { return getActions().CorrectDelayedTyposInExpr(Res); } +ExprResult Parser::ParseOpenACCBindClauseArgument() { + // OpenACC 3.3 section 2.15: + // The bind clause specifies the name to use when calling the procedure on a + // device other than the host. If the name is specified as an identifier, it + // is called as if that name were specified in the language being compiled. If + // the name is specified as a string, the string is used for the procedure + // name unmodified. + if (getCurToken().is(tok::r_paren)) { + Diag(getCurToken(), diag::err_acc_incorrect_bind_arg); + return ExprError(); + } + + if (tok::isStringLiteral(getCurToken().getKind())) + return getActions().CorrectDelayedTyposInExpr(ParseStringLiteralExpression( + /*AllowUserDefinedLiteral=*/false, /*Unevaluated=*/true)); + + return ParseOpenACCIDExpression(); +} + /// OpenACC 3.3, section 1.6: /// In this spec, a 'var' (in italics) is one of the following: /// - a variable name (a scalar, array, or compisite variable name) @@ -563,7 +912,8 @@ ExprResult Parser::ParseOpenACCIDExpression() { /// - a common block name between slashes (fortran only) bool Parser::ParseOpenACCVar() { OpenACCArraySectionRAII ArraySections(*this); - ExprResult Res = ParseAssignmentExpression(); + ExprResult Res = + getActions().CorrectDelayedTyposInExpr(ParseAssignmentExpression()); return Res.isInvalid(); } @@ -578,14 +928,11 @@ void Parser::ParseOpenACCCacheVarList() { return; // The VarList is an optional `readonly:` followed by a list of a variable - // specifications. First, see if we have `readonly:`, else we back-out and - // treat it like the beginning of a reference to a potentially-existing - // `readonly` variable. - if (isOpenACCSpecialToken(OpenACCSpecialTokenKind::ReadOnly, Tok) && - NextToken().is(tok::colon)) { - // Consume both tokens. - ConsumeToken(); - ConsumeToken(); + // specifications. Consume something that looks like a 'tag', and diagnose if + // it isn't 'readonly'. + if (tryParseAndConsumeSpecialTokenKind(*this, + OpenACCSpecialTokenKind::ReadOnly, + OpenACCDirectiveKind::Cache)) { // FIXME: Record that this is a 'readonly' so that we can use that during // Sema/AST generation. } @@ -664,7 +1011,7 @@ void Parser::ParseOpenACCDirective() { } // Parses the list of clauses, if present. - ParseOpenACCClauseList(*this); + ParseOpenACCClauseList(DirKind); Diag(getCurToken(), diag::warn_pragma_acc_unimplemented); assert(Tok.is(tok::annot_pragma_openacc_end) && diff --git a/clang/lib/Parse/ParseTentative.cpp b/clang/lib/Parse/ParseTentative.cpp index 242741c15b5..5bfabf55f50 100644 --- a/clang/lib/Parse/ParseTentative.cpp +++ b/clang/lib/Parse/ParseTentative.cpp @@ -894,7 +894,8 @@ bool Parser::TrySkipAttributes() { // Note that explicitly checking for `[[` and `]]` allows to fail as // expected in the case of the Objective-C message send syntax. ConsumeBracket(); - } else if (Tok.isRegularKeywordAttribute()) { + } else if (Tok.isRegularKeywordAttribute() && + !doesKeywordAttributeTakeArgs(Tok.getKind())) { ConsumeToken(); } else { ConsumeToken(); diff --git a/clang/lib/Parse/Parser.cpp b/clang/lib/Parse/Parser.cpp index b703c2d9b8e..0b092181bca 100644 --- a/clang/lib/Parse/Parser.cpp +++ b/clang/lib/Parse/Parser.cpp @@ -70,6 +70,11 @@ Parser::Parser(Preprocessor &pp, Sema &actions, bool skipFunctionBodies) PP.addCommentHandler(CommentSemaHandler.get()); PP.setCodeCompletionHandler(*this); + + Actions.ParseTypeFromStringCallback = + [this](StringRef TypeStr, StringRef Context, SourceLocation IncludeLoc) { + return this->ParseTypeFromString(TypeStr, Context, IncludeLoc); + }; } DiagnosticBuilder Parser::Diag(SourceLocation Loc, unsigned DiagID) { diff --git a/clang/lib/Sema/AnalysisBasedWarnings.cpp b/clang/lib/Sema/AnalysisBasedWarnings.cpp index 9eb1df5f024..9e9294572df 100644 --- a/clang/lib/Sema/AnalysisBasedWarnings.cpp +++ b/clang/lib/Sema/AnalysisBasedWarnings.cpp @@ -2263,15 +2263,18 @@ public: MsgParam = 3; } else if (const auto *ECE = dyn_cast(Operation)) { QualType destType = ECE->getType(); + if (!isa(destType)) + return; + const uint64_t dSize = Ctx.getTypeSize(destType.getTypePtr()->getPointeeType()); - if (const auto *CE = dyn_cast(ECE->getSubExpr())) { - QualType srcType = CE->getType(); - const uint64_t sSize = - Ctx.getTypeSize(srcType.getTypePtr()->getPointeeType()); - if (sSize >= dSize) - return; - } + + QualType srcType = ECE->getSubExpr()->getType(); + const uint64_t sSize = + Ctx.getTypeSize(srcType.getTypePtr()->getPointeeType()); + if (sSize >= dSize) + return; + MsgParam = 4; } Loc = Operation->getBeginLoc(); diff --git a/clang/lib/Sema/Sema.cpp b/clang/lib/Sema/Sema.cpp index cafbecebc8a..2d4e6d1d058 100644 --- a/clang/lib/Sema/Sema.cpp +++ b/clang/lib/Sema/Sema.cpp @@ -957,7 +957,7 @@ static bool MethodsAndNestedClassesComplete(const CXXRecordDecl *RD, I != E && Complete; ++I) { if (const CXXMethodDecl *M = dyn_cast(*I)) Complete = M->isDefined() || M->isDefaulted() || - (M->isPure() && !isa(M)); + (M->isPureVirtual() && !isa(M)); else if (const FunctionTemplateDecl *F = dyn_cast(*I)) // If the template function is marked as late template parsed at this // point, it has not been instantiated and therefore we have not @@ -2758,7 +2758,7 @@ bool Sema::isDeclaratorFunctionLike(Declarator &D) { return false; LookupQualifiedName(LR, DC); - bool Result = std::all_of(LR.begin(), LR.end(), [](Decl *Dcl) { + bool Result = llvm::all_of(LR, [](Decl *Dcl) { if (NamedDecl *ND = dyn_cast(Dcl)) { ND = ND->getUnderlyingDecl(); return isa(ND) || isa(ND) || diff --git a/clang/lib/Sema/SemaChecking.cpp b/clang/lib/Sema/SemaChecking.cpp index 74f8f626fb1..7833d5a2ea2 100644 --- a/clang/lib/Sema/SemaChecking.cpp +++ b/clang/lib/Sema/SemaChecking.cpp @@ -2169,6 +2169,7 @@ Sema::CheckBuiltinFunctionCall(FunctionDecl *FDecl, unsigned BuiltinID, ICEArguments &= ~(1 << ArgNo); } + FPOptions FPO; switch (BuiltinID) { case Builtin::BI__builtin___CFStringMakeConstantString: // CFStringMakeConstantString is currently not implemented for GOFF (i.e., @@ -2245,15 +2246,15 @@ Sema::CheckBuiltinFunctionCall(FunctionDecl *FDecl, unsigned BuiltinID, case Builtin::BI__builtin_islessequal: case Builtin::BI__builtin_islessgreater: case Builtin::BI__builtin_isunordered: - if (SemaBuiltinUnorderedCompare(TheCall)) + if (SemaBuiltinUnorderedCompare(TheCall, BuiltinID)) return ExprError(); break; case Builtin::BI__builtin_fpclassify: - if (SemaBuiltinFPClassification(TheCall, 6)) + if (SemaBuiltinFPClassification(TheCall, 6, BuiltinID)) return ExprError(); break; case Builtin::BI__builtin_isfpclass: - if (SemaBuiltinFPClassification(TheCall, 2)) + if (SemaBuiltinFPClassification(TheCall, 2, BuiltinID)) return ExprError(); break; case Builtin::BI__builtin_isfinite: @@ -2267,7 +2268,7 @@ Sema::CheckBuiltinFunctionCall(FunctionDecl *FDecl, unsigned BuiltinID, case Builtin::BI__builtin_signbit: case Builtin::BI__builtin_signbitf: case Builtin::BI__builtin_signbitl: - if (SemaBuiltinFPClassification(TheCall, 1)) + if (SemaBuiltinFPClassification(TheCall, 1, BuiltinID)) return ExprError(); break; case Builtin::BI__builtin_shufflevector: @@ -3005,6 +3006,20 @@ enum ArmStreamingType { ArmStreamingOrSVE2p1 }; +enum ArmSMEState : unsigned { + ArmNoState = 0, + + ArmInZA = 0b01, + ArmOutZA = 0b10, + ArmInOutZA = 0b11, + ArmZAMask = 0b11, + + ArmInZT0 = 0b01 << 2, + ArmOutZT0 = 0b10 << 2, + ArmInOutZT0 = 0b11 << 2, + ArmZT0Mask = 0b11 << 2 +}; + bool Sema::ParseSVEImmChecks( CallExpr *TheCall, SmallVector, 3> &ImmChecks) { // Perform all the immediate checks for this builtin call. @@ -3189,22 +3204,27 @@ static void checkArmStreamingBuiltin(Sema &S, CallExpr *TheCall, } } -static bool hasSMEZAState(const FunctionDecl *FD) { - if (FD->hasAttr()) - return true; - if (const auto *T = FD->getType()->getAs()) - if (T->getAArch64SMEAttributes() & FunctionType::SME_PStateZASharedMask) - return true; - return false; +static bool hasArmZAState(const FunctionDecl *FD) { + const auto *T = FD->getType()->getAs(); + return (T && FunctionType::getArmZAState(T->getAArch64SMEAttributes()) != + FunctionType::ARM_None) || + (FD->hasAttr() && FD->getAttr()->isNewZA()); } -static bool hasSMEZAState(unsigned BuiltinID) { +static bool hasArmZT0State(const FunctionDecl *FD) { + const auto *T = FD->getType()->getAs(); + return (T && FunctionType::getArmZT0State(T->getAArch64SMEAttributes()) != + FunctionType::ARM_None) || + (FD->hasAttr() && FD->getAttr()->isNewZT0()); +} + +static ArmSMEState getSMEState(unsigned BuiltinID) { switch (BuiltinID) { default: - return false; -#define GET_SME_BUILTIN_HAS_ZA_STATE + return ArmNoState; +#define GET_SME_BUILTIN_GET_STATE #include "clang/Basic/arm_sme_builtins_za_state.inc" -#undef GET_SME_BUILTIN_HAS_ZA_STATE +#undef GET_SME_BUILTIN_GET_STATE } } @@ -3221,10 +3241,15 @@ bool Sema::CheckSMEBuiltinFunctionCall(unsigned BuiltinID, CallExpr *TheCall) { if (BuiltinType) checkArmStreamingBuiltin(*this, TheCall, FD, *BuiltinType); - if (hasSMEZAState(BuiltinID) && !hasSMEZAState(FD)) + if ((getSMEState(BuiltinID) & ArmZAMask) && !hasArmZAState(FD)) Diag(TheCall->getBeginLoc(), diag::warn_attribute_arm_za_builtin_no_za_state) << TheCall->getSourceRange(); + + if ((getSMEState(BuiltinID) & ArmZT0Mask) && !hasArmZT0State(FD)) + Diag(TheCall->getBeginLoc(), + diag::warn_attribute_arm_zt0_builtin_no_zt0_state) + << TheCall->getSourceRange(); } // Range check SME intrinsics that take immediate values. @@ -7522,19 +7547,46 @@ void Sema::checkCall(NamedDecl *FDecl, const FunctionProtoType *Proto, // If the callee uses AArch64 SME ZA state but the caller doesn't define // any, then this is an error. - if (ExtInfo.AArch64SMEAttributes & FunctionType::SME_PStateZASharedMask) { + FunctionType::ArmStateValue ArmZAState = + FunctionType::getArmZAState(ExtInfo.AArch64SMEAttributes); + if (ArmZAState != FunctionType::ARM_None) { bool CallerHasZAState = false; if (const auto *CallerFD = dyn_cast(CurContext)) { - if (CallerFD->hasAttr()) + auto *Attr = CallerFD->getAttr(); + if (Attr && Attr->isNewZA()) CallerHasZAState = true; - else if (const auto *FPT = CallerFD->getType()->getAs()) - CallerHasZAState = FPT->getExtProtoInfo().AArch64SMEAttributes & - FunctionType::SME_PStateZASharedMask; + else if (const auto *FPT = + CallerFD->getType()->getAs()) + CallerHasZAState = FunctionType::getArmZAState( + FPT->getExtProtoInfo().AArch64SMEAttributes) != + FunctionType::ARM_None; } if (!CallerHasZAState) Diag(Loc, diag::err_sme_za_call_no_za_state); } + + // If the callee uses AArch64 SME ZT0 state but the caller doesn't define + // any, then this is an error. + FunctionType::ArmStateValue ArmZT0State = + FunctionType::getArmZT0State(ExtInfo.AArch64SMEAttributes); + if (ArmZT0State != FunctionType::ARM_None) { + bool CallerHasZT0State = false; + if (const auto *CallerFD = dyn_cast(CurContext)) { + auto *Attr = CallerFD->getAttr(); + if (Attr && Attr->isNewZT0()) + CallerHasZT0State = true; + else if (const auto *FPT = + CallerFD->getType()->getAs()) + CallerHasZT0State = + FunctionType::getArmZT0State( + FPT->getExtProtoInfo().AArch64SMEAttributes) != + FunctionType::ARM_None; + } + + if (!CallerHasZT0State) + Diag(Loc, diag::err_sme_zt0_call_no_zt0_state); + } } if (FDecl && FDecl->hasAttr()) { @@ -7636,6 +7688,7 @@ bool Sema::CheckFunctionCall(FunctionDecl *FDecl, CallExpr *TheCall, CheckAbsoluteValueFunction(TheCall, FDecl); CheckMaxUnsignedZero(TheCall, FDecl); + CheckInfNaNFunction(TheCall, FDecl); if (getLangOpts().ObjC) DiagnoseCStringFormatDirectiveInCFAPI(*this, FDecl, Args, NumArgs); @@ -9105,10 +9158,15 @@ bool Sema::SemaBuiltinVAStartARMMicrosoft(CallExpr *Call) { /// SemaBuiltinUnorderedCompare - Handle functions like __builtin_isgreater and /// friends. This is declared to take (...), so we have to check everything. -bool Sema::SemaBuiltinUnorderedCompare(CallExpr *TheCall) { +bool Sema::SemaBuiltinUnorderedCompare(CallExpr *TheCall, unsigned BuiltinID) { if (checkArgCount(*this, TheCall, 2)) return true; + if (BuiltinID == Builtin::BI__builtin_isunordered && + TheCall->getFPFeaturesInEffect(getLangOpts()).getNoHonorNaNs()) + Diag(TheCall->getBeginLoc(), diag::warn_fp_nan_inf_when_disabled) + << 1 << 0 << TheCall->getSourceRange(); + ExprResult OrigArg0 = TheCall->getArg(0); ExprResult OrigArg1 = TheCall->getArg(1); @@ -9143,10 +9201,23 @@ bool Sema::SemaBuiltinUnorderedCompare(CallExpr *TheCall) { /// SemaBuiltinSemaBuiltinFPClassification - Handle functions like /// __builtin_isnan and friends. This is declared to take (...), so we have /// to check everything. -bool Sema::SemaBuiltinFPClassification(CallExpr *TheCall, unsigned NumArgs) { +bool Sema::SemaBuiltinFPClassification(CallExpr *TheCall, unsigned NumArgs, + unsigned BuiltinID) { if (checkArgCount(*this, TheCall, NumArgs)) return true; + FPOptions FPO = TheCall->getFPFeaturesInEffect(getLangOpts()); + if (FPO.getNoHonorInfs() && (BuiltinID == Builtin::BI__builtin_isfinite || + BuiltinID == Builtin::BI__builtin_isinf || + BuiltinID == Builtin::BI__builtin_isinf_sign)) + Diag(TheCall->getBeginLoc(), diag::warn_fp_nan_inf_when_disabled) + << 0 << 0 << TheCall->getSourceRange(); + + if (FPO.getNoHonorNaNs() && (BuiltinID == Builtin::BI__builtin_isnan || + BuiltinID == Builtin::BI__builtin_isunordered)) + Diag(TheCall->getBeginLoc(), diag::warn_fp_nan_inf_when_disabled) + << 1 << 0 << TheCall->getSourceRange(); + bool IsFPClass = NumArgs == 2; // Find out position of floating-point argument. @@ -12893,6 +12964,22 @@ static bool IsStdFunction(const FunctionDecl *FDecl, return true; } +void Sema::CheckInfNaNFunction(const CallExpr *Call, + const FunctionDecl *FDecl) { + FPOptions FPO = Call->getFPFeaturesInEffect(getLangOpts()); + if ((IsStdFunction(FDecl, "isnan") || IsStdFunction(FDecl, "isunordered") || + (Call->getBuiltinCallee() == Builtin::BI__builtin_nanf)) && + FPO.getNoHonorNaNs()) + Diag(Call->getBeginLoc(), diag::warn_fp_nan_inf_when_disabled) + << 1 << 0 << Call->getSourceRange(); + else if ((IsStdFunction(FDecl, "isinf") || + (IsStdFunction(FDecl, "isfinite") || + (FDecl->getIdentifier() && FDecl->getName() == "infinity"))) && + FPO.getNoHonorInfs()) + Diag(Call->getBeginLoc(), diag::warn_fp_nan_inf_when_disabled) + << 0 << 0 << Call->getSourceRange(); +} + // Warn when using the wrong abs() function. void Sema::CheckAbsoluteValueFunction(const CallExpr *Call, const FunctionDecl *FDecl) { diff --git a/clang/lib/Sema/SemaCoroutine.cpp b/clang/lib/Sema/SemaCoroutine.cpp index bee80db8d16..4e600fd29ee 100644 --- a/clang/lib/Sema/SemaCoroutine.cpp +++ b/clang/lib/Sema/SemaCoroutine.cpp @@ -16,10 +16,12 @@ #include "CoroutineStmtBuilder.h" #include "clang/AST/ASTLambda.h" #include "clang/AST/Decl.h" +#include "clang/AST/Expr.h" #include "clang/AST/ExprCXX.h" #include "clang/AST/StmtCXX.h" #include "clang/Basic/Builtins.h" #include "clang/Lex/Preprocessor.h" +#include "clang/Sema/EnterExpressionEvaluationContext.h" #include "clang/Sema/Initialization.h" #include "clang/Sema/Overload.h" #include "clang/Sema/ScopeInfo.h" @@ -772,6 +774,9 @@ bool Sema::checkFinalSuspendNoThrow(const Stmt *FinalSuspend) { bool Sema::ActOnCoroutineBodyStart(Scope *SC, SourceLocation KWLoc, StringRef Keyword) { + // Ignore previous expr evaluation contexts. + EnterExpressionEvaluationContext PotentiallyEvaluated( + *this, Sema::ExpressionEvaluationContext::PotentiallyEvaluated); if (!checkCoroutineContext(*this, KWLoc, Keyword)) return false; auto *ScopeInfo = getCurFunction(); diff --git a/clang/lib/Sema/SemaDecl.cpp b/clang/lib/Sema/SemaDecl.cpp index e92fd104d78..f9bf1d14bdc 100644 --- a/clang/lib/Sema/SemaDecl.cpp +++ b/clang/lib/Sema/SemaDecl.cpp @@ -3819,8 +3819,7 @@ bool Sema::MergeFunctionDecl(FunctionDecl *New, NamedDecl *&OldD, Scope *S, // It is not permitted to redeclare an SME function with different SME // attributes. - if (IsInvalidSMECallConversion(Old->getType(), New->getType(), - AArch64SMECallConversionKind::MatchExactly)) { + if (IsInvalidSMECallConversion(Old->getType(), New->getType())) { Diag(New->getLocation(), diag::err_sme_attr_mismatch) << New->getType() << Old->getType(); Diag(OldLocation, diag::note_previous_declaration); @@ -4391,8 +4390,8 @@ bool Sema::MergeCompatibleFunctionDecls(FunctionDecl *New, FunctionDecl *Old, mergeDeclAttributes(New, Old); // Merge "pure" flag. - if (Old->isPure()) - New->setPure(); + if (Old->isPureVirtual()) + New->setIsPureVirtual(); // Merge "used" flag. if (Old->getMostRecentDecl()->isUsed(false)) @@ -5804,7 +5803,7 @@ Decl *Sema::BuildAnonymousStructOrUnion(Scope *S, DeclSpec &DS, // Mock up a declarator. Declarator Dc(DS, ParsedAttributesView::none(), DeclaratorContext::Member); StorageClass SC = StorageClassSpecToVarDeclStorageClass(DS); - TypeSourceInfo *TInfo = GetTypeForDeclarator(Dc, S); + TypeSourceInfo *TInfo = GetTypeForDeclarator(Dc); assert(TInfo && "couldn't build declarator info for anonymous struct/union"); // Create a declaration for this anonymous struct/union. @@ -5901,7 +5900,7 @@ Decl *Sema::BuildMicrosoftCAnonymousStruct(Scope *S, DeclSpec &DS, // Mock up a declarator. Declarator Dc(DS, ParsedAttributesView::none(), DeclaratorContext::TypeName); - TypeSourceInfo *TInfo = GetTypeForDeclarator(Dc, S); + TypeSourceInfo *TInfo = GetTypeForDeclarator(Dc); assert(TInfo && "couldn't build declarator info for anonymous struct"); auto *ParentDecl = cast(CurContext); @@ -6439,7 +6438,7 @@ NamedDecl *Sema::HandleDeclarator(Scope *S, Declarator &D, } } - TypeSourceInfo *TInfo = GetTypeForDeclarator(D, S); + TypeSourceInfo *TInfo = GetTypeForDeclarator(D); QualType R = TInfo->getType(); if (DiagnoseUnexpandedParameterPack(D.getIdentifierLoc(), TInfo, @@ -7069,8 +7068,7 @@ static void checkAttributesAfterMerging(Sema &S, NamedDecl &ND) { if (WeakRefAttr *Attr = ND.getAttr()) { if (ND.isExternallyVisible()) { S.Diag(Attr->getLocation(), diag::err_attribute_weakref_not_static); - ND.dropAttr(); - ND.dropAttr(); + ND.dropAttrs(); } } @@ -9880,7 +9878,7 @@ Sema::ActOnFunctionDeclarator(Scope *S, Declarator &D, DeclContext *DC, if (const CXXRecordDecl *Parent = dyn_cast(NewFD->getDeclContext())) { if (Parent->isInterface() && cast(NewFD)->isUserProvided()) - NewFD->setPure(true); + NewFD->setIsPureVirtual(true); // C++ [class.union]p2 // A union can have member functions, but not virtual functions. @@ -10847,9 +10845,19 @@ Sema::ActOnFunctionDeclarator(Scope *S, Declarator &D, DeclContext *DC, // Precalculate whether this is a friend function template with a constraint // that depends on an enclosing template, per [temp.friend]p9. if (isFriend && FunctionTemplate && - FriendConstraintsDependOnEnclosingTemplate(NewFD)) + FriendConstraintsDependOnEnclosingTemplate(NewFD)) { NewFD->setFriendConstraintRefersToEnclosingTemplate(true); + // C++ [temp.friend]p9: + // A friend function template with a constraint that depends on a + // template parameter from an enclosing template shall be a definition. + if (!D.isFunctionDefinition()) { + Diag(NewFD->getBeginLoc(), + diag::err_friend_decl_with_enclosing_temp_constraint_must_be_def); + NewFD->setInvalidDecl(); + } + } + if (FunctionTemplate) { if (NewFD->isInvalidDecl()) FunctionTemplate->setInvalidDecl(); @@ -11793,6 +11801,32 @@ static bool CheckMultiVersionFunction(Sema &S, FunctionDecl *NewFD, OldDecl, Previous); } +static void CheckConstPureAttributesUsage(Sema &S, FunctionDecl *NewFD) { + bool IsPure = NewFD->hasAttr(); + bool IsConst = NewFD->hasAttr(); + + // If there are no pure or const attributes, there's nothing to check. + if (!IsPure && !IsConst) + return; + + // If the function is marked both pure and const, we retain the const + // attribute because it makes stronger guarantees than the pure attribute, and + // we drop the pure attribute explicitly to prevent later confusion about + // semantics. + if (IsPure && IsConst) { + S.Diag(NewFD->getLocation(), diag::warn_const_attr_with_pure_attr); + NewFD->dropAttrs(); + } + + // Constructors and destructors are functions which return void, so are + // handled here as well. + if (NewFD->getReturnType()->isVoidType()) { + S.Diag(NewFD->getLocation(), diag::warn_pure_function_returns_void) + << IsConst; + NewFD->dropAttrs(); + } +} + /// Perform semantic checking of a new function declaration. /// /// Performs semantic analysis of the new function declaration @@ -11890,6 +11924,8 @@ bool Sema::CheckFunctionDeclaration(Scope *S, FunctionDecl *NewFD, NewFD->setInvalidDecl(); } + CheckConstPureAttributesUsage(*this, NewFD); + // C++11 [dcl.constexpr]p8: // A constexpr specifier for a non-static member function that is not // a constructor declares that member function to be const. @@ -12066,11 +12102,12 @@ bool Sema::CheckFunctionDeclaration(Scope *S, FunctionDecl *NewFD, checkThisInStaticMemberFunctionType(Method); } - // C++20: dcl.decl.general p4: - // The optional requires-clause ([temp.pre]) in an init-declarator or - // member-declarator shall be present only if the declarator declares a - // templated function ([dcl.fct]). if (Expr *TRC = NewFD->getTrailingRequiresClause()) { + // C++20: dcl.decl.general p4: + // The optional requires-clause ([temp.pre]) in an init-declarator or + // member-declarator shall be present only if the declarator declares a + // templated function ([dcl.fct]). + // // [temp.pre]/8: // An entity is templated if it is // - a template, @@ -12088,15 +12125,29 @@ bool Sema::CheckFunctionDeclaration(Scope *S, FunctionDecl *NewFD, // templated. A templated variable is a variable template or a variable // that is templated. - if (!NewFD->getDescribedFunctionTemplate() && // -a template - // defined... in a templated entity + bool IsTemplate = NewFD->getDescribedFunctionTemplate(); + bool IsFriend = NewFD->getFriendObjectKind(); + if (!IsTemplate && // -a template + // defined... in a templated entity !(DeclIsDefn && NewFD->isTemplated()) && // a member of a templated entity !(isa(NewFD) && NewFD->isTemplated()) && // Don't complain about instantiations, they've already had these // rules + others enforced. - !NewFD->isTemplateInstantiation()) { + !NewFD->isTemplateInstantiation() && + // If the function violates [temp.friend]p9 because it is missing + // a definition, and adding a definition would make it templated, + // then let that error take precedence. + !(!DeclIsDefn && IsFriend && NewFD->isTemplated())) { Diag(TRC->getBeginLoc(), diag::err_constrained_non_templated_function); + } else if (!DeclIsDefn && !IsTemplate && IsFriend && + !NewFD->isTemplateInstantiation()) { + // C++ [temp.friend]p9: + // A non-template friend declaration with a requires-clause shall be a + // definition. + Diag(NewFD->getBeginLoc(), + diag::err_non_temp_friend_decl_with_requires_clause_must_be_def); + NewFD->setInvalidDecl(); } } @@ -12180,13 +12231,18 @@ bool Sema::CheckFunctionDeclaration(Scope *S, FunctionDecl *NewFD, // Check if the function definition uses any AArch64 SME features without // having the '+sme' feature enabled. if (DeclIsDefn) { + const auto *Attr = NewFD->getAttr(); bool UsesSM = NewFD->hasAttr(); - bool UsesZA = NewFD->hasAttr(); + bool UsesZA = Attr && Attr->isNewZA(); + bool UsesZT0 = Attr && Attr->isNewZT0(); if (const auto *FPT = NewFD->getType()->getAs()) { FunctionProtoType::ExtProtoInfo EPI = FPT->getExtProtoInfo(); UsesSM |= EPI.AArch64SMEAttributes & FunctionType::SME_PStateSMEnabledMask; - UsesZA |= EPI.AArch64SMEAttributes & FunctionType::SME_PStateZASharedMask; + UsesZA |= FunctionType::getArmZAState(EPI.AArch64SMEAttributes) != + FunctionType::ARM_None; + UsesZT0 |= FunctionType::getArmZT0State(EPI.AArch64SMEAttributes) != + FunctionType::ARM_None; } if (UsesSM || UsesZA) { @@ -12201,6 +12257,14 @@ bool Sema::CheckFunctionDeclaration(Scope *S, FunctionDecl *NewFD, diag::err_sme_definition_using_za_in_non_sme_target); } } + if (UsesZT0) { + llvm::StringMap FeatureMap; + Context.getFunctionFeatureMap(FeatureMap, NewFD); + if (!FeatureMap.contains("sme2")) { + Diag(NewFD->getLocation(), + diag::err_sme_definition_using_zt0_in_non_sme2_target); + } + } } return Redeclaration; @@ -13576,6 +13640,15 @@ void Sema::AddInitializerToDecl(Decl *RealDecl, Expr *Init, bool DirectInit) { CreateRecoveryExpr(Init->getBeginLoc(), Init->getEndLoc(), Args); if (RecoveryExpr.get()) VDecl->setInit(RecoveryExpr.get()); + // In general, for error recovery purposes, the initalizer doesn't play + // part in the valid bit of the declaration. There are a few exceptions: + // 1) if the var decl has a deduced auto type, and the type cannot be + // deduced by an invalid initializer; + // 2) if the var decl is decompsition decl with a non-deduced type, and + // the initialization fails (e.g. `int [a] = {1, 2};`); + // Case 1) was already handled elsewhere. + if (isa(VDecl)) // Case 2) + VDecl->setInvalidDecl(); return; } @@ -15046,7 +15119,7 @@ Decl *Sema::ActOnParamDeclarator(Scope *S, Declarator &D, CheckFunctionOrTemplateParamDeclarator(S, D); - TypeSourceInfo *TInfo = GetTypeForDeclarator(D, S); + TypeSourceInfo *TInfo = GetTypeForDeclarator(D); QualType parmDeclType = TInfo->getType(); // Check for redeclaration of parameters, e.g. int foo(int x, int x); @@ -15170,6 +15243,37 @@ void Sema::DiagnoseSizeOfParametersAndReturnValue( } } +QualType Sema::AdjustParameterTypeForObjCAutoRefCount(QualType T, + SourceLocation NameLoc, + TypeSourceInfo *TSInfo) { + // In ARC, infer a lifetime qualifier for appropriate parameter types. + if (!getLangOpts().ObjCAutoRefCount || + T.getObjCLifetime() != Qualifiers::OCL_None || !T->isObjCLifetimeType()) + return T; + + Qualifiers::ObjCLifetime Lifetime; + + // Special cases for arrays: + // - if it's const, use __unsafe_unretained + // - otherwise, it's an error + if (T->isArrayType()) { + if (!T.isConstQualified()) { + if (DelayedDiagnostics.shouldDelayDiagnostics()) + DelayedDiagnostics.add(sema::DelayedDiagnostic::makeForbiddenType( + NameLoc, diag::err_arc_array_param_no_ownership, T, false)); + else + Diag(NameLoc, diag::err_arc_array_param_no_ownership) + << TSInfo->getTypeLoc().getSourceRange(); + } + Lifetime = Qualifiers::OCL_ExplicitNone; + } else { + Lifetime = T->getObjCARCImplicitLifetime(); + } + T = Context.getLifetimeQualifiedType(T, Lifetime); + + return T; +} + ParmVarDecl *Sema::CheckParameter(DeclContext *DC, SourceLocation StartLoc, SourceLocation NameLoc, IdentifierInfo *Name, QualType T, TypeSourceInfo *TSInfo, @@ -15847,13 +15951,26 @@ static void diagnoseImplicitlyRetainedSelf(Sema &S) { << FixItHint::CreateInsertion(P.first, "self->"); } +static bool methodHasName(const FunctionDecl *FD, StringRef Name) { + return isa(FD) && FD->param_empty() && + FD->getDeclName().isIdentifier() && FD->getName().equals(Name); +} + +bool Sema::CanBeGetReturnObject(const FunctionDecl *FD) { + return methodHasName(FD, "get_return_object"); +} + +bool Sema::CanBeGetReturnTypeOnAllocFailure(const FunctionDecl *FD) { + return FD->isStatic() && + methodHasName(FD, "get_return_object_on_allocation_failure"); +} + void Sema::CheckCoroutineWrapper(FunctionDecl *FD) { RecordDecl *RD = FD->getReturnType()->getAsRecordDecl(); if (!RD || !RD->getUnderlyingDecl()->hasAttr()) return; - // Allow `get_return_object()`. - if (FD->getDeclName().isIdentifier() && - FD->getName().equals("get_return_object") && FD->param_empty()) + // Allow some_promise_type::get_return_object(). + if (CanBeGetReturnObject(FD) || CanBeGetReturnTypeOnAllocFailure(FD)) return; if (!FD->hasAttr()) Diag(FD->getLocation(), diag::err_coroutine_return_type) << RD; @@ -15934,7 +16051,8 @@ Decl *Sema::ActOnFinishFunctionBody(Decl *dcl, Stmt *Body, // MSVC permits the use of pure specifier (=0) on function definition, // defined at class scope, warn about this non-standard construct. - if (getLangOpts().MicrosoftExt && FD->isPure() && !FD->isOutOfLine()) + if (getLangOpts().MicrosoftExt && FD->isPureVirtual() && + !FD->isOutOfLine()) Diag(FD->getLocation(), diag::ext_pure_function_definition); if (!FD->isInvalidDecl()) { @@ -18310,7 +18428,7 @@ FieldDecl *Sema::HandleField(Scope *S, RecordDecl *Record, SourceLocation Loc = DeclStart; if (II) Loc = D.getIdentifierLoc(); - TypeSourceInfo *TInfo = GetTypeForDeclarator(D, S); + TypeSourceInfo *TInfo = GetTypeForDeclarator(D); QualType T = TInfo->getType(); if (getLangOpts().CPlusPlus) { CheckExtraCXXDefaultArguments(D); @@ -18674,7 +18792,7 @@ Decl *Sema::ActOnIvar(Scope *S, SourceLocation DeclStart, Declarator &D, // FIXME: Unnamed fields can be handled in various different ways, for // example, unnamed unions inject all members into the struct namespace! - TypeSourceInfo *TInfo = GetTypeForDeclarator(D, S); + TypeSourceInfo *TInfo = GetTypeForDeclarator(D); QualType T = TInfo->getType(); if (BitWidth) { @@ -20219,7 +20337,7 @@ void Sema::ActOnEnumBody(SourceLocation EnumLoc, SourceRange BraceRange, // Adjust the APSInt value. InitVal = InitVal.extOrTrunc(NewWidth); InitVal.setIsSigned(NewSign); - ECD->setInitVal(InitVal); + ECD->setInitVal(Context, InitVal); // Adjust the Expr initializer and type. if (ECD->getInitExpr() && diff --git a/clang/lib/Sema/SemaDeclAttr.cpp b/clang/lib/Sema/SemaDeclAttr.cpp index 1a58cfd8e41..6f462de4be7 100644 --- a/clang/lib/Sema/SemaDeclAttr.cpp +++ b/clang/lib/Sema/SemaDeclAttr.cpp @@ -6236,29 +6236,35 @@ static void handleObjCRequiresSuperAttr(Sema &S, Decl *D, D->addAttr(::new (S.Context) ObjCRequiresSuperAttr(S.Context, Attrs)); } -static void handleNSErrorDomain(Sema &S, Decl *D, const ParsedAttr &AL) { - auto *E = AL.getArgAsExpr(0); - auto Loc = E ? E->getBeginLoc() : AL.getLoc(); +static void handleNSErrorDomain(Sema &S, Decl *D, const ParsedAttr &Attr) { + if (!isa(D)) { + S.Diag(D->getBeginLoc(), diag::err_nserrordomain_invalid_decl) << 0; + return; + } + + IdentifierLoc *IdentLoc = + Attr.isArgIdent(0) ? Attr.getArgAsIdent(0) : nullptr; + if (!IdentLoc || !IdentLoc->Ident) { + // Try to locate the argument directly. + SourceLocation Loc = Attr.getLoc(); + if (Attr.isArgExpr(0) && Attr.getArgAsExpr(0)) + Loc = Attr.getArgAsExpr(0)->getBeginLoc(); - auto *DRE = dyn_cast(AL.getArgAsExpr(0)); - if (!DRE) { S.Diag(Loc, diag::err_nserrordomain_invalid_decl) << 0; return; } - auto *VD = dyn_cast(DRE->getDecl()); - if (!VD) { - S.Diag(Loc, diag::err_nserrordomain_invalid_decl) << 1 << DRE->getDecl(); + // Verify that the identifier is a valid decl in the C decl namespace. + LookupResult Result(S, DeclarationName(IdentLoc->Ident), SourceLocation(), + Sema::LookupNameKind::LookupOrdinaryName); + if (!S.LookupName(Result, S.TUScope) || !Result.getAsSingle()) { + S.Diag(IdentLoc->Loc, diag::err_nserrordomain_invalid_decl) + << 1 << IdentLoc->Ident; return; } - if (!isNSStringType(VD->getType(), S.Context) && - !isCFStringType(VD->getType(), S.Context)) { - S.Diag(Loc, diag::err_nserrordomain_wrong_type) << VD; - return; - } - - D->addAttr(::new (S.Context) NSErrorDomainAttr(S.Context, AL, VD)); + D->addAttr(::new (S.Context) + NSErrorDomainAttr(S.Context, Attr, IdentLoc->Ident)); } static void handleObjCBridgeAttr(Sema &S, Decl *D, const ParsedAttr &AL) { @@ -8951,26 +8957,80 @@ static bool MustDelayAttributeArguments(const ParsedAttr &AL) { return false; } +static bool checkArmNewAttrMutualExclusion( + Sema &S, const ParsedAttr &AL, const FunctionProtoType *FPT, + FunctionType::ArmStateValue CurrentState, StringRef StateName) { + auto CheckForIncompatibleAttr = + [&](FunctionType::ArmStateValue IncompatibleState, + StringRef IncompatibleStateName) { + if (CurrentState == IncompatibleState) { + S.Diag(AL.getLoc(), diag::err_attributes_are_not_compatible) + << (std::string("'__arm_new(\"") + StateName.str() + "\")'") + << (std::string("'") + IncompatibleStateName.str() + "(\"" + + StateName.str() + "\")'") + << true; + AL.setInvalid(); + } + }; + + CheckForIncompatibleAttr(FunctionType::ARM_In, "__arm_in"); + CheckForIncompatibleAttr(FunctionType::ARM_Out, "__arm_out"); + CheckForIncompatibleAttr(FunctionType::ARM_InOut, "__arm_inout"); + CheckForIncompatibleAttr(FunctionType::ARM_Preserves, "__arm_preserves"); + return AL.isInvalid(); +} + +static void handleArmNewAttr(Sema &S, Decl *D, const ParsedAttr &AL) { + if (!AL.getNumArgs()) { + S.Diag(AL.getLoc(), diag::err_missing_arm_state) << AL; + AL.setInvalid(); + return; + } + + std::vector NewState; + if (const auto *ExistingAttr = D->getAttr()) { + for (StringRef S : ExistingAttr->newArgs()) + NewState.push_back(S); + } + + bool HasZA = false; + bool HasZT0 = false; + for (unsigned I = 0, E = AL.getNumArgs(); I != E; ++I) { + StringRef StateName; + SourceLocation LiteralLoc; + if (!S.checkStringLiteralArgumentAttr(AL, I, StateName, &LiteralLoc)) + return; + + if (StateName == "za") + HasZA = true; + else if (StateName == "zt0") + HasZT0 = true; + else { + S.Diag(LiteralLoc, diag::err_unknown_arm_state) << StateName; + AL.setInvalid(); + return; + } + + if (!llvm::is_contained(NewState, StateName)) // Avoid adding duplicates. + NewState.push_back(StateName); + } -static void handleArmNewZaAttr(Sema &S, Decl *D, const ParsedAttr &AL) { if (auto *FPT = dyn_cast(D->getFunctionType())) { - if (FPT->getAArch64SMEAttributes() & - FunctionType::SME_PStateZASharedMask) { - S.Diag(AL.getLoc(), diag::err_attributes_are_not_compatible) - << AL << "'__arm_shared_za'" << true; - AL.setInvalid(); - } - if (FPT->getAArch64SMEAttributes() & - FunctionType::SME_PStateZAPreservedMask) { - S.Diag(AL.getLoc(), diag::err_attributes_are_not_compatible) - << AL << "'__arm_preserves_za'" << true; - AL.setInvalid(); - } - if (AL.isInvalid()) + FunctionType::ArmStateValue ZAState = + FunctionType::getArmZAState(FPT->getAArch64SMEAttributes()); + if (HasZA && ZAState != FunctionType::ARM_None && + checkArmNewAttrMutualExclusion(S, AL, FPT, ZAState, "za")) + return; + FunctionType::ArmStateValue ZT0State = + FunctionType::getArmZT0State(FPT->getAArch64SMEAttributes()); + if (HasZT0 && ZT0State != FunctionType::ARM_None && + checkArmNewAttrMutualExclusion(S, AL, FPT, ZT0State, "zt0")) return; } - handleSimpleAttribute(S, D, AL); + D->dropAttr(); + D->addAttr(::new (S.Context) + ArmNewAttr(S.Context, AL, NewState.data(), NewState.size())); } /// ProcessDeclAttribute - Apply the specific attribute to the specified decl if @@ -9752,8 +9812,8 @@ ProcessDeclAttribute(Sema &S, Scope *scope, Decl *D, const ParsedAttr &AL, handleSimpleAttribute(S, D, AL); break; - case ParsedAttr::AT_ArmNewZA: - handleArmNewZaAttr(S, D, AL); + case ParsedAttr::AT_ArmNew: + handleArmNewAttr(S, D, AL); break; case ParsedAttr::AT_AcquireHandle: diff --git a/clang/lib/Sema/SemaDeclCXX.cpp b/clang/lib/Sema/SemaDeclCXX.cpp index 36e53c684ac..df5bd55e7c2 100644 --- a/clang/lib/Sema/SemaDeclCXX.cpp +++ b/clang/lib/Sema/SemaDeclCXX.cpp @@ -839,7 +839,7 @@ Sema::ActOnDecompositionDeclarator(Scope *S, Declarator &D, Diag(DS.getVolatileSpecLoc(), diag::warn_deprecated_volatile_structured_binding); - TypeSourceInfo *TInfo = GetTypeForDeclarator(D, S); + TypeSourceInfo *TInfo = GetTypeForDeclarator(D); QualType R = TInfo->getType(); if (DiagnoseUnexpandedParameterPack(D.getIdentifierLoc(), TInfo, @@ -6062,7 +6062,7 @@ void Sema::DiagnoseAbstractType(const CXXRecordDecl *RD) { if (SO->second.size() != 1) continue; - if (!SO->second.front().Method->isPure()) + if (!SO->second.front().Method->isPureVirtual()) continue; if (!SeenPureMethods.insert(SO->second.front().Method).second) @@ -6545,8 +6545,7 @@ void Sema::checkClassLevelDLLAttribute(CXXRecordDecl *Class) { if ((Context.getTargetInfo().getCXXABI().isMicrosoft() || Context.getTargetInfo().getTriple().isPS()) && (!Class->isExternallyVisible() && Class->hasExternalFormalLinkage())) { - Class->dropAttr(); - Class->dropAttr(); + Class->dropAttrs(); return; } @@ -11322,9 +11321,20 @@ Decl *Sema::ActOnConversionDeclarator(CXXConversionDecl *Conversion) { << ClassType << ConvType; } - if (FunctionTemplateDecl *ConversionTemplate - = Conversion->getDescribedFunctionTemplate()) + if (FunctionTemplateDecl *ConversionTemplate = + Conversion->getDescribedFunctionTemplate()) { + if (const auto *ConvTypePtr = ConvType->getAs()) { + ConvType = ConvTypePtr->getPointeeType(); + } + if (ConvType->isUndeducedAutoType()) { + Diag(Conversion->getTypeSpecStartLoc(), diag::err_auto_not_allowed) + << getReturnTypeLoc(Conversion).getSourceRange() + << llvm::to_underlying(ConvType->getAs()->getKeyword()) + << /* in declaration of conversion function template= */ 24; + } + return ConversionTemplate; + } return Conversion; } @@ -17011,7 +17021,7 @@ VarDecl *Sema::BuildExceptionDeclaration(Scope *S, /// ActOnExceptionDeclarator - Parsed the exception-declarator in a C++ catch /// handler. Decl *Sema::ActOnExceptionDeclarator(Scope *S, Declarator &D) { - TypeSourceInfo *TInfo = GetTypeForDeclarator(D, S); + TypeSourceInfo *TInfo = GetTypeForDeclarator(D); bool Invalid = D.isInvalidType(); // Check for unexpanded parameter packs. @@ -17762,7 +17772,7 @@ Decl *Sema::ActOnFriendTypeDecl(Scope *S, const DeclSpec &DS, // for a TUK_Friend. Declarator TheDeclarator(DS, ParsedAttributesView::none(), DeclaratorContext::Member); - TypeSourceInfo *TSI = GetTypeForDeclarator(TheDeclarator, S); + TypeSourceInfo *TSI = GetTypeForDeclarator(TheDeclarator); QualType T = TSI->getType(); if (TheDeclarator.isInvalidType()) return nullptr; @@ -17827,7 +17837,7 @@ NamedDecl *Sema::ActOnFriendFunctionDecl(Scope *S, Declarator &D, assert(DS.getStorageClassSpec() == DeclSpec::SCS_unspecified); SourceLocation Loc = D.getIdentifierLoc(); - TypeSourceInfo *TInfo = GetTypeForDeclarator(D, S); + TypeSourceInfo *TInfo = GetTypeForDeclarator(D); // C++ [class.friend]p1 // A friend of a class is a function or class.... @@ -18328,9 +18338,7 @@ bool Sema::CheckOverridingFunctionAttributes(const CXXMethodDecl *New, } // SME attributes must match when overriding a function declaration. - if (IsInvalidSMECallConversion( - Old->getType(), New->getType(), - AArch64SMECallConversionKind::MayAddPreservesZA)) { + if (IsInvalidSMECallConversion(Old->getType(), New->getType())) { Diag(New->getLocation(), diag::err_conflicting_overriding_attributes) << New << New->getType() << Old->getType(); Diag(Old->getLocation(), diag::note_overridden_virtual_function); @@ -18498,7 +18506,7 @@ bool Sema::CheckPureMethod(CXXMethodDecl *Method, SourceRange InitRange) { Method->setRangeEnd(EndLoc); if (Method->isVirtual() || Method->getParent()->isDependentContext()) { - Method->setPure(); + Method->setIsPureVirtual(); return false; } @@ -18769,7 +18777,7 @@ bool Sema::DefineUsedVTables() { void Sema::MarkVirtualMemberExceptionSpecsNeeded(SourceLocation Loc, const CXXRecordDecl *RD) { for (const auto *I : RD->methods()) - if (I->isVirtual() && !I->isPure()) + if (I->isVirtual() && !I->isPureVirtual()) ResolveExceptionSpec(Loc, I->getType()->castAs()); } @@ -18790,7 +18798,8 @@ void Sema::MarkVirtualMembersReferenced(SourceLocation Loc, // C++ [basic.def.odr]p2: // [...] A virtual member function is used if it is not pure. [...] - if (!Overrider->isPure() && (!ConstexprOnly || Overrider->isConstexpr())) + if (!Overrider->isPureVirtual() && + (!ConstexprOnly || Overrider->isConstexpr())) MarkFunctionReferenced(Loc, Overrider); } } @@ -19184,7 +19193,7 @@ MSPropertyDecl *Sema::HandleMSProperty(Scope *S, RecordDecl *Record, } SourceLocation Loc = D.getIdentifierLoc(); - TypeSourceInfo *TInfo = GetTypeForDeclarator(D, S); + TypeSourceInfo *TInfo = GetTypeForDeclarator(D); QualType T = TInfo->getType(); if (getLangOpts().CPlusPlus) { CheckExtraCXXDefaultArguments(D); diff --git a/clang/lib/Sema/SemaDeclObjC.cpp b/clang/lib/Sema/SemaDeclObjC.cpp index c3b95e168a6..bb0d0cd2030 100644 --- a/clang/lib/Sema/SemaDeclObjC.cpp +++ b/clang/lib/Sema/SemaDeclObjC.cpp @@ -1623,7 +1623,7 @@ void Sema::actOnObjCTypeArgsOrProtocolQualifiers( } // Convert this to a type. - return ActOnTypeName(S, D); + return ActOnTypeName(D); }; // Local function that updates the declaration specifiers with @@ -5211,7 +5211,7 @@ Decl *Sema::ActOnObjCExceptionDecl(Scope *S, Declarator &D) { if (getLangOpts().CPlusPlus) CheckExtraCXXDefaultArguments(D); - TypeSourceInfo *TInfo = GetTypeForDeclarator(D, S); + TypeSourceInfo *TInfo = GetTypeForDeclarator(D); QualType ExceptionType = TInfo->getType(); VarDecl *New = BuildObjCExceptionDecl(TInfo, ExceptionType, diff --git a/clang/lib/Sema/SemaExpr.cpp b/clang/lib/Sema/SemaExpr.cpp index 2f48ea237cd..6413a48f809 100644 --- a/clang/lib/Sema/SemaExpr.cpp +++ b/clang/lib/Sema/SemaExpr.cpp @@ -5058,8 +5058,6 @@ static QualType getDependentArraySubscriptType(Expr *LHS, Expr *RHS, return Result->isDependentType() ? Result : Ctx.DependentTy; } -static bool checkArgsForPlaceholders(Sema &S, MultiExprArg args); - ExprResult Sema::ActOnArraySubscriptExpr(Scope *S, Expr *base, SourceLocation lbLoc, MultiExprArg ArgExprs, @@ -5163,7 +5161,7 @@ ExprResult Sema::ActOnArraySubscriptExpr(Scope *S, Expr *base, return ExprError(); ArgExprs[0] = result.get(); } else { - if (checkArgsForPlaceholders(*this, ArgExprs)) + if (CheckArgsForPlaceholders(ArgExprs)) return ExprError(); } @@ -6912,15 +6910,13 @@ static bool isPlaceholderToRemoveAsArg(QualType type) { llvm_unreachable("bad builtin type kind"); } -/// Check an argument list for placeholders that we won't try to -/// handle later. -static bool checkArgsForPlaceholders(Sema &S, MultiExprArg args) { +bool Sema::CheckArgsForPlaceholders(MultiExprArg args) { // Apply this processing to all the arguments at once instead of // dying at the first failure. bool hasInvalid = false; for (size_t i = 0, e = args.size(); i != e; i++) { if (isPlaceholderToRemoveAsArg(args[i]->getType())) { - ExprResult result = S.CheckPlaceholderExpr(args[i]); + ExprResult result = CheckPlaceholderExpr(args[i]); if (result.isInvalid()) hasInvalid = true; else args[i] = result.get(); } @@ -7194,7 +7190,7 @@ ExprResult Sema::BuildCallExpr(Scope *Scope, Expr *Fn, SourceLocation LParenLoc, if (Result.isInvalid()) return ExprError(); Fn = Result.get(); - if (checkArgsForPlaceholders(*this, ArgExprs)) + if (CheckArgsForPlaceholders(ArgExprs)) return ExprError(); if (getLangOpts().CPlusPlus) { @@ -9803,8 +9799,7 @@ ExprResult Sema::ActOnConditionalOp(SourceLocation QuestionLoc, } // Check that the SME attributes for PSTATE.ZA and PSTATE.SM are compatible. -bool Sema::IsInvalidSMECallConversion(QualType FromType, QualType ToType, - AArch64SMECallConversionKind C) { +bool Sema::IsInvalidSMECallConversion(QualType FromType, QualType ToType) { unsigned FromAttributes = 0, ToAttributes = 0; if (const auto *FromFn = dyn_cast(Context.getCanonicalType(FromType))) @@ -9815,25 +9810,7 @@ bool Sema::IsInvalidSMECallConversion(QualType FromType, QualType ToType, ToAttributes = ToFn->getAArch64SMEAttributes() & FunctionType::SME_AttributeMask; - if (FromAttributes == ToAttributes) - return false; - - // If the '__arm_preserves_za' is the only difference between the types, - // check whether we're allowed to add or remove it. - if ((FromAttributes ^ ToAttributes) == - FunctionType::SME_PStateZAPreservedMask) { - switch (C) { - case AArch64SMECallConversionKind::MatchExactly: - return true; - case AArch64SMECallConversionKind::MayAddPreservesZA: - return !(ToAttributes & FunctionType::SME_PStateZAPreservedMask); - case AArch64SMECallConversionKind::MayDropPreservesZA: - return !(FromAttributes & FunctionType::SME_PStateZAPreservedMask); - } - } - - // There has been a mismatch of attributes - return true; + return FromAttributes != ToAttributes; } // Check if we have a conversion between incompatible cmse function pointer @@ -10002,9 +9979,7 @@ checkPointerTypesForAssignment(Sema &S, QualType LHSType, QualType RHSType, return Sema::IncompatibleFunctionPointer; if (IsInvalidCmseNSCallConversion(S, ltrans, rtrans)) return Sema::IncompatibleFunctionPointer; - if (S.IsInvalidSMECallConversion( - rtrans, ltrans, - Sema::AArch64SMECallConversionKind::MayDropPreservesZA)) + if (S.IsInvalidSMECallConversion(rtrans, ltrans)) return Sema::IncompatibleFunctionPointer; return ConvTy; } @@ -16995,7 +16970,7 @@ void Sema::ActOnBlockArguments(SourceLocation CaretLoc, Declarator &ParamInfo, assert(ParamInfo.getContext() == DeclaratorContext::BlockLiteral); BlockScopeInfo *CurBlock = getCurBlock(); - TypeSourceInfo *Sig = GetTypeForDeclarator(ParamInfo, CurScope); + TypeSourceInfo *Sig = GetTypeForDeclarator(ParamInfo); QualType T = Sig->getType(); // FIXME: We should allow unexpanded parameter packs here, but that would, @@ -20794,7 +20769,7 @@ void Sema::MarkMemberReferenced(MemberExpr *E) { bool MightBeOdrUse = true; if (E->performsVirtualDispatch(getLangOpts())) { if (CXXMethodDecl *Method = dyn_cast(E->getMemberDecl())) - if (Method->isPure()) + if (Method->isPureVirtual()) MightBeOdrUse = false; } SourceLocation Loc = diff --git a/clang/lib/Sema/SemaExprCXX.cpp b/clang/lib/Sema/SemaExprCXX.cpp index 4ae04358d5d..953bfe484a5 100644 --- a/clang/lib/Sema/SemaExprCXX.cpp +++ b/clang/lib/Sema/SemaExprCXX.cpp @@ -1931,7 +1931,7 @@ Sema::ActOnCXXNew(SourceLocation StartLoc, bool UseGlobal, } } - TypeSourceInfo *TInfo = GetTypeForDeclarator(D, /*Scope=*/nullptr); + TypeSourceInfo *TInfo = GetTypeForDeclarator(D); QualType AllocType = TInfo->getType(); if (D.isInvalidType()) return ExprError(); @@ -1947,17 +1947,17 @@ Sema::ActOnCXXNew(SourceLocation StartLoc, bool UseGlobal, } static bool isLegalArrayNewInitializer(CXXNewInitializationStyle Style, - Expr *Init) { + Expr *Init, bool IsCPlusPlus20) { if (!Init) return true; if (ParenListExpr *PLE = dyn_cast(Init)) - return PLE->getNumExprs() == 0; + return IsCPlusPlus20 || PLE->getNumExprs() == 0; if (isa(Init)) return true; else if (CXXConstructExpr *CCE = dyn_cast(Init)) return !CCE->isListInitialization() && CCE->getConstructor()->isDefaultConstructor(); - else if (Style == CXXNewInitializationStyle::List) { + else if (Style == CXXNewInitializationStyle::Braces) { assert(isa(Init) && "Shouldn't create list CXXConstructExprs for arrays."); return true; @@ -2011,9 +2011,9 @@ ExprResult Sema::BuildCXXNew(SourceRange Range, bool UseGlobal, CXXNewInitializationStyle InitStyle; if (DirectInitRange.isValid()) { assert(Initializer && "Have parens but no initializer."); - InitStyle = CXXNewInitializationStyle::Call; + InitStyle = CXXNewInitializationStyle::Parens; } else if (Initializer && isa(Initializer)) - InitStyle = CXXNewInitializationStyle::List; + InitStyle = CXXNewInitializationStyle::Braces; else { assert((!Initializer || isa(Initializer) || isa(Initializer)) && @@ -2023,7 +2023,7 @@ ExprResult Sema::BuildCXXNew(SourceRange Range, bool UseGlobal, MultiExprArg Exprs(&Initializer, Initializer ? 1 : 0); if (ParenListExpr *List = dyn_cast_or_null(Initializer)) { - assert(InitStyle == CXXNewInitializationStyle::Call && + assert(InitStyle == CXXNewInitializationStyle::Parens && "paren init for non-call init"); Exprs = MultiExprArg(List->getExprs(), List->getNumExprs()); } @@ -2037,15 +2037,14 @@ ExprResult Sema::BuildCXXNew(SourceRange Range, bool UseGlobal, // initialized (8.5); if no initialization is performed, // the object has indeterminate value case CXXNewInitializationStyle::None: - case CXXNewInitializationStyle::Implicit: return InitializationKind::CreateDefault(TypeRange.getBegin()); // - Otherwise, the new-initializer is interpreted according to the // initialization rules of 8.5 for direct-initialization. - case CXXNewInitializationStyle::Call: + case CXXNewInitializationStyle::Parens: return InitializationKind::CreateDirect(TypeRange.getBegin(), DirectInitRange.getBegin(), DirectInitRange.getEnd()); - case CXXNewInitializationStyle::List: + case CXXNewInitializationStyle::Braces: return InitializationKind::CreateDirectList(TypeRange.getBegin(), Initializer->getBeginLoc(), Initializer->getEndLoc()); @@ -2072,14 +2071,13 @@ ExprResult Sema::BuildCXXNew(SourceRange Range, bool UseGlobal, return ExprError(); } else if (Deduced && !Deduced->isDeduced()) { MultiExprArg Inits = Exprs; - bool Braced = (InitStyle == CXXNewInitializationStyle::List); + bool Braced = (InitStyle == CXXNewInitializationStyle::Braces); if (Braced) { auto *ILE = cast(Exprs[0]); Inits = MultiExprArg(ILE->getInits(), ILE->getNumInits()); } - if (InitStyle == CXXNewInitializationStyle::None || - InitStyle == CXXNewInitializationStyle::Implicit || Inits.empty()) + if (InitStyle == CXXNewInitializationStyle::None || Inits.empty()) return ExprError(Diag(StartLoc, diag::err_auto_new_requires_ctor_arg) << AllocType << TypeRange); if (Inits.size() > 1) { @@ -2286,6 +2284,9 @@ ExprResult Sema::BuildCXXNew(SourceRange Range, bool UseGlobal, bool PassAlignment = getLangOpts().AlignedAllocation && Alignment > NewAlignment; + if (CheckArgsForPlaceholders(PlacementArgs)) + return ExprError(); + AllocationFunctionScope Scope = UseGlobal ? AFS_Global : AFS_Both; if (!AllocType->isDependentType() && !Expr::hasAnyTypeDependentArguments(PlacementArgs) && @@ -2403,7 +2404,8 @@ ExprResult Sema::BuildCXXNew(SourceRange Range, bool UseGlobal, // Array 'new' can't have any initializers except empty parentheses. // Initializer lists are also allowed, in C++11. Rely on the parser for the // dialect distinction. - if (ArraySize && !isLegalArrayNewInitializer(InitStyle, Initializer)) { + if (ArraySize && !isLegalArrayNewInitializer(InitStyle, Initializer, + getLangOpts().CPlusPlus20)) { SourceRange InitRange(Exprs.front()->getBeginLoc(), Exprs.back()->getEndLoc()); Diag(StartLoc, diag::err_new_array_init_args) << InitRange; @@ -2443,14 +2445,6 @@ ExprResult Sema::BuildCXXNew(SourceRange Range, bool UseGlobal, FullInit = Binder->getSubExpr(); Initializer = FullInit.get(); - // We don't know that we're generating an implicit initializer until now, so - // we have to update the initialization style as well. - // - // FIXME: it would be nice to determine the correct initialization style - // earlier so InitStyle doesn't need adjusting. - if (InitStyle == CXXNewInitializationStyle::None && Initializer) { - InitStyle = CXXNewInitializationStyle::Implicit; - } // FIXME: If we have a KnownArraySize, check that the array bound of the // initializer is no greater than that constant value. @@ -3222,10 +3216,13 @@ void Sema::DeclareGlobalAllocationFunction(DeclarationName Name, Alloc->setLocalOwningModule(TheGlobalModuleFragment); } - Alloc->addAttr(VisibilityAttr::CreateImplicit( - Context, LangOpts.GlobalAllocationFunctionVisibilityHidden - ? VisibilityAttr::Hidden - : VisibilityAttr::Default)); + if (LangOpts.hasGlobalAllocationFunctionVisibility()) + Alloc->addAttr(VisibilityAttr::CreateImplicit( + Context, LangOpts.hasHiddenGlobalAllocationFunctionVisibility() + ? VisibilityAttr::Hidden + : LangOpts.hasProtectedGlobalAllocationFunctionVisibility() + ? VisibilityAttr::Protected + : VisibilityAttr::Default)); llvm::SmallVector ParamDecls; for (QualType T : Params) { diff --git a/clang/lib/Sema/SemaInit.cpp b/clang/lib/Sema/SemaInit.cpp index 408ee5f7758..91e4cb7b68a 100644 --- a/clang/lib/Sema/SemaInit.cpp +++ b/clang/lib/Sema/SemaInit.cpp @@ -12,6 +12,7 @@ #include "clang/AST/ASTContext.h" #include "clang/AST/DeclObjC.h" +#include "clang/AST/Expr.h" #include "clang/AST/ExprCXX.h" #include "clang/AST/ExprObjC.h" #include "clang/AST/ExprOpenMP.h" @@ -4199,7 +4200,7 @@ static OverloadingResult ResolveConstructorOverload( /// \param IsListInit Is this list-initialization? /// \param IsInitListCopy Is this non-list-initialization resulting from a /// list-initialization from {x} where x is the same -/// type as the entity? +/// aggregate type as the entity? static void TryConstructorInitialization(Sema &S, const InitializedEntity &Entity, const InitializationKind &Kind, @@ -4229,6 +4230,14 @@ static void TryConstructorInitialization(Sema &S, Entity.getKind() != InitializedEntity::EK_LambdaToBlockConversionBlockElement); + bool CopyElisionPossible = false; + auto ElideConstructor = [&] { + // Convert qualifications if necessary. + Sequence.AddQualificationConversionStep(DestType, VK_PRValue); + if (ILE) + Sequence.RewrapReferenceInitList(DestType, ILE); + }; + // C++17 [dcl.init]p17: // - If the initializer expression is a prvalue and the cv-unqualified // version of the source type is the same class as the class of the @@ -4241,11 +4250,17 @@ static void TryConstructorInitialization(Sema &S, if (S.getLangOpts().CPlusPlus17 && !RequireActualConstructor && UnwrappedArgs.size() == 1 && UnwrappedArgs[0]->isPRValue() && S.Context.hasSameUnqualifiedType(UnwrappedArgs[0]->getType(), DestType)) { - // Convert qualifications if necessary. - Sequence.AddQualificationConversionStep(DestType, VK_PRValue); - if (ILE) - Sequence.RewrapReferenceInitList(DestType, ILE); - return; + if (ILE && !DestType->isAggregateType()) { + // CWG2311: T{ prvalue_of_type_T } is not eligible for copy elision + // Make this an elision if this won't call an initializer-list + // constructor. (Always on an aggregate type or check constructors first.) + assert(!IsInitListCopy && + "IsInitListCopy only possible with aggregate types"); + CopyElisionPossible = true; + } else { + ElideConstructor(); + return; + } } const RecordType *DestRecordType = DestType->getAs(); @@ -4290,6 +4305,12 @@ static void TryConstructorInitialization(Sema &S, S, Kind.getLocation(), Args, CandidateSet, DestType, Ctors, Best, CopyInitialization, AllowExplicit, /*OnlyListConstructors=*/true, IsListInit, RequireActualConstructor); + + if (CopyElisionPossible && Result == OR_No_Viable_Function) { + // No initializer list candidate + ElideConstructor(); + return; + } } // C++11 [over.match.list]p1: @@ -4571,9 +4592,9 @@ static void TryListInitialization(Sema &S, return; } - // C++11 [dcl.init.list]p3, per DR1467: - // - If T is a class type and the initializer list has a single element of - // type cv U, where U is T or a class derived from T, the object is + // C++11 [dcl.init.list]p3, per DR1467 and DR2137: + // - If T is an aggregate class and the initializer list has a single element + // of type cv U, where U is T or a class derived from T, the object is // initialized from that element (by copy-initialization for // copy-list-initialization, or by direct-initialization for // direct-list-initialization). @@ -4584,7 +4605,7 @@ static void TryListInitialization(Sema &S, // - Otherwise, if T is an aggregate, [...] (continue below). if (S.getLangOpts().CPlusPlus11 && InitList->getNumInits() == 1 && !IsDesignatedInit) { - if (DestType->isRecordType()) { + if (DestType->isRecordType() && DestType->isAggregateType()) { QualType InitType = InitList->getInit(0)->getType(); if (S.Context.hasSameUnqualifiedType(InitType, DestType) || S.IsDerivedFrom(InitList->getBeginLoc(), InitType, DestType)) { @@ -5495,7 +5516,7 @@ static void TryOrBuildParenListInitialization( return; } // ...and value-initialized for each k < i <= n; - if (ArrayLength > Args.size()) { + if (ArrayLength > Args.size() || Entity.isVariableLengthArrayNew()) { InitializedEntity SubEntity = InitializedEntity::InitializeElement( S.getASTContext(), Args.size(), Entity); InitializationKind SubKind = InitializationKind::CreateValue( @@ -7583,15 +7604,27 @@ static void visitLifetimeBoundArguments(IndirectLocalPath &Path, Expr *Call, Path.pop_back(); }; - if (ObjectArg && implicitObjectParamIsLifetimeBound(Callee)) - VisitLifetimeBoundArg(Callee, ObjectArg); - bool CheckCoroCall = false; if (const auto *RD = Callee->getReturnType()->getAsRecordDecl()) { CheckCoroCall = RD->hasAttr() && RD->hasAttr() && !Callee->hasAttr(); } + + if (ObjectArg) { + bool CheckCoroObjArg = CheckCoroCall; + // Coroutine lambda objects with empty capture list are not lifetimebound. + if (auto *LE = dyn_cast(ObjectArg->IgnoreImplicit()); + LE && LE->captures().empty()) + CheckCoroObjArg = false; + // Allow `get_return_object()` as the object param (__promise) is not + // lifetimebound. + if (Sema::CanBeGetReturnObject(Callee)) + CheckCoroObjArg = false; + if (implicitObjectParamIsLifetimeBound(Callee) || CheckCoroObjArg) + VisitLifetimeBoundArg(Callee, ObjectArg); + } + for (unsigned I = 0, N = std::min(Callee->getNumParams(), Args.size()); I != N; ++I) { @@ -10718,7 +10751,14 @@ QualType Sema::DeduceTemplateSpecializationFromInitializer( bool HasAnyDeductionGuide = false; auto SynthesizeAggrGuide = [&](InitListExpr *ListInit) { - auto *RD = cast(Template->getTemplatedDecl()); + auto *Pattern = Template; + while (Pattern->getInstantiatedFromMemberTemplate()) { + if (Pattern->isMemberSpecialization()) + break; + Pattern = Pattern->getInstantiatedFromMemberTemplate(); + } + + auto *RD = cast(Pattern->getTemplatedDecl()); if (!(RD->getDefinition() && RD->isAggregate())) return; QualType Ty = Context.getRecordType(RD); diff --git a/clang/lib/Sema/SemaLambda.cpp b/clang/lib/Sema/SemaLambda.cpp index e7b6443c984..5b95bae567b 100644 --- a/clang/lib/Sema/SemaLambda.cpp +++ b/clang/lib/Sema/SemaLambda.cpp @@ -916,7 +916,7 @@ static TypeSourceInfo *getLambdaType(Sema &S, LambdaIntroducer &Intro, } } - MethodTyInfo = S.GetTypeForDeclarator(ParamInfo, CurScope); + MethodTyInfo = S.GetTypeForDeclarator(ParamInfo); assert(MethodTyInfo && "no type from lambda-declarator"); // Check for unexpanded parameter packs in the method type. diff --git a/clang/lib/Sema/SemaLookup.cpp b/clang/lib/Sema/SemaLookup.cpp index 996f8b57233..02b1a045df4 100644 --- a/clang/lib/Sema/SemaLookup.cpp +++ b/clang/lib/Sema/SemaLookup.cpp @@ -2982,6 +2982,7 @@ addAssociatedClassesAndNamespaces(AssociatedLookup &Result, case TemplateArgument::Integral: case TemplateArgument::Expression: case TemplateArgument::NullPtr: + case TemplateArgument::StructuralValue: // [Note: non-type template arguments do not contribute to the set of // associated namespaces. ] break; diff --git a/clang/lib/Sema/SemaObjCProperty.cpp b/clang/lib/Sema/SemaObjCProperty.cpp index 22540af1cda..349c7fc9c91 100644 --- a/clang/lib/Sema/SemaObjCProperty.cpp +++ b/clang/lib/Sema/SemaObjCProperty.cpp @@ -180,7 +180,7 @@ Decl *Sema::ActOnProperty(Scope *S, SourceLocation AtLoc, unsigned Attributes = ODS.getPropertyAttributes(); FD.D.setObjCWeakProperty((Attributes & ObjCPropertyAttribute::kind_weak) != 0); - TypeSourceInfo *TSI = GetTypeForDeclarator(FD.D, S); + TypeSourceInfo *TSI = GetTypeForDeclarator(FD.D); QualType T = TSI->getType(); if (!getOwnershipRule(Attributes)) { Attributes |= deducePropertyOwnershipFromType(*this, T); diff --git a/clang/lib/Sema/SemaOpenMP.cpp b/clang/lib/Sema/SemaOpenMP.cpp index 365032c9642..217fcb979de 100644 --- a/clang/lib/Sema/SemaOpenMP.cpp +++ b/clang/lib/Sema/SemaOpenMP.cpp @@ -7304,7 +7304,7 @@ void Sema::ActOnStartOfFunctionDefinitionInOpenMPDeclareVariantScope( LookupOrdinaryName); LookupParsedName(Lookup, S, &D.getCXXScopeSpec()); - TypeSourceInfo *TInfo = GetTypeForDeclarator(D, S); + TypeSourceInfo *TInfo = GetTypeForDeclarator(D); QualType FType = TInfo->getType(); bool IsConstexpr = @@ -22719,7 +22719,7 @@ Sema::DeclGroupPtrTy Sema::ActOnOpenMPDeclareReductionDirectiveEnd( } TypeResult Sema::ActOnOpenMPDeclareMapperVarDecl(Scope *S, Declarator &D) { - TypeSourceInfo *TInfo = GetTypeForDeclarator(D, S); + TypeSourceInfo *TInfo = GetTypeForDeclarator(D); QualType T = TInfo->getType(); if (D.isInvalidType()) return true; diff --git a/clang/lib/Sema/SemaOverload.cpp b/clang/lib/Sema/SemaOverload.cpp index 64bc3851980..030878899b8 100644 --- a/clang/lib/Sema/SemaOverload.cpp +++ b/clang/lib/Sema/SemaOverload.cpp @@ -1259,6 +1259,40 @@ static bool IsOverloadOrOverrideImpl(Sema &SemaRef, FunctionDecl *New, if ((OldTemplate == nullptr) != (NewTemplate == nullptr)) return true; + // Is the function New an overload of the function Old? + QualType OldQType = SemaRef.Context.getCanonicalType(Old->getType()); + QualType NewQType = SemaRef.Context.getCanonicalType(New->getType()); + + // Compare the signatures (C++ 1.3.10) of the two functions to + // determine whether they are overloads. If we find any mismatch + // in the signature, they are overloads. + + // If either of these functions is a K&R-style function (no + // prototype), then we consider them to have matching signatures. + if (isa(OldQType.getTypePtr()) || + isa(NewQType.getTypePtr())) + return false; + + const auto *OldType = cast(OldQType); + const auto *NewType = cast(NewQType); + + // The signature of a function includes the types of its + // parameters (C++ 1.3.10), which includes the presence or absence + // of the ellipsis; see C++ DR 357). + if (OldQType != NewQType && OldType->isVariadic() != NewType->isVariadic()) + return true; + + // For member-like friends, the enclosing class is part of the signature. + if ((New->isMemberLikeConstrainedFriend() || + Old->isMemberLikeConstrainedFriend()) && + !New->getLexicalDeclContext()->Equals(Old->getLexicalDeclContext())) + return true; + + // Compare the parameter lists. + // This can only be done once we have establish that friend functions + // inhabit the same context, otherwise we might tried to instantiate + // references to non-instantiated entities during constraint substitution. + // GH78101. if (NewTemplate) { // C++ [temp.over.link]p4: // The signature of a function template consists of its function @@ -1296,34 +1330,6 @@ static bool IsOverloadOrOverrideImpl(Sema &SemaRef, FunctionDecl *New, return true; } - // Is the function New an overload of the function Old? - QualType OldQType = SemaRef.Context.getCanonicalType(Old->getType()); - QualType NewQType = SemaRef.Context.getCanonicalType(New->getType()); - - // Compare the signatures (C++ 1.3.10) of the two functions to - // determine whether they are overloads. If we find any mismatch - // in the signature, they are overloads. - - // If either of these functions is a K&R-style function (no - // prototype), then we consider them to have matching signatures. - if (isa(OldQType.getTypePtr()) || - isa(NewQType.getTypePtr())) - return false; - - const FunctionProtoType *OldType = cast(OldQType); - const FunctionProtoType *NewType = cast(NewQType); - - // The signature of a function includes the types of its - // parameters (C++ 1.3.10), which includes the presence or absence - // of the ellipsis; see C++ DR 357). - if (OldQType != NewQType && OldType->isVariadic() != NewType->isVariadic()) - return true; - - // For member-like friends, the enclosing class is part of the signature. - if ((New->isMemberLikeConstrainedFriend() || - Old->isMemberLikeConstrainedFriend()) && - !New->getLexicalDeclContext()->Equals(Old->getLexicalDeclContext())) - return true; const auto *OldMethod = dyn_cast(Old); const auto *NewMethod = dyn_cast(New); @@ -1562,19 +1568,37 @@ TryUserDefinedConversion(Sema &S, Expr *From, QualType ToType, // called for those cases. if (CXXConstructorDecl *Constructor = dyn_cast(ICS.UserDefined.ConversionFunction)) { - QualType FromCanon - = S.Context.getCanonicalType(From->getType().getUnqualifiedType()); + QualType FromType; + SourceLocation FromLoc; + // C++11 [over.ics.list]p6, per DR2137: + // C++17 [over.ics.list]p6: + // If C is not an initializer-list constructor and the initializer list + // has a single element of type cv U, where U is X or a class derived + // from X, the implicit conversion sequence has Exact Match rank if U is + // X, or Conversion rank if U is derived from X. + if (const auto *InitList = dyn_cast(From); + InitList && InitList->getNumInits() == 1 && + !S.isInitListConstructor(Constructor)) { + const Expr *SingleInit = InitList->getInit(0); + FromType = SingleInit->getType(); + FromLoc = SingleInit->getBeginLoc(); + } else { + FromType = From->getType(); + FromLoc = From->getBeginLoc(); + } + QualType FromCanon = + S.Context.getCanonicalType(FromType.getUnqualifiedType()); QualType ToCanon = S.Context.getCanonicalType(ToType).getUnqualifiedType(); if (Constructor->isCopyConstructor() && (FromCanon == ToCanon || - S.IsDerivedFrom(From->getBeginLoc(), FromCanon, ToCanon))) { + S.IsDerivedFrom(FromLoc, FromCanon, ToCanon))) { // Turn this into a "standard" conversion sequence, so that it // gets ranked with standard conversion sequences. DeclAccessPair Found = ICS.UserDefined.FoundConversionFunction; ICS.setStandard(); ICS.Standard.setAsIdentityConversion(); - ICS.Standard.setFromType(From->getType()); + ICS.Standard.setFromType(FromType); ICS.Standard.setAllToTypes(ToType); ICS.Standard.CopyConstructor = Constructor; ICS.Standard.FoundCopyConstructor = Found; @@ -1784,26 +1808,6 @@ bool Sema::IsFunctionConversion(QualType FromType, QualType ToType, Changed = true; } - // Drop the 'arm_preserves_za' if not present in the target type (we can do - // that because it is merely a hint). - if (const auto *FromFPT = dyn_cast(FromFn)) { - FunctionProtoType::ExtProtoInfo ExtInfo = FromFPT->getExtProtoInfo(); - if (ExtInfo.AArch64SMEAttributes & - FunctionType::SME_PStateZAPreservedMask) { - unsigned ToFlags = 0; - if (const auto *ToFPT = dyn_cast(ToFn)) - ToFlags = ToFPT->getExtProtoInfo().AArch64SMEAttributes; - if (!(ToFlags & FunctionType::SME_PStateZAPreservedMask)) { - ExtInfo.setArmSMEAttribute(FunctionType::SME_PStateZAPreservedMask, - false); - QualType QT = Context.getFunctionType( - FromFPT->getReturnType(), FromFPT->getParamTypes(), ExtInfo); - FromFn = QT->getAs(); - Changed = true; - } - } - } - // Drop 'noexcept' if not present in target type. if (const auto *FromFPT = dyn_cast(FromFn)) { const auto *ToFPT = cast(ToFn); @@ -5320,18 +5324,18 @@ TryListConversion(Sema &S, InitListExpr *From, QualType ToType, IsDesignatedInit) return Result; - // Per DR1467: - // If the parameter type is a class X and the initializer list has a single - // element of type cv U, where U is X or a class derived from X, the - // implicit conversion sequence is the one required to convert the element - // to the parameter type. + // Per DR1467 and DR2137: + // If the parameter type is an aggregate class X and the initializer list + // has a single element of type cv U, where U is X or a class derived from + // X, the implicit conversion sequence is the one required to convert the + // element to the parameter type. // // Otherwise, if the parameter type is a character array [... ] // and the initializer list has a single element that is an // appropriately-typed string literal (8.5.2 [dcl.init.string]), the // implicit conversion sequence is the identity conversion. if (From->getNumInits() == 1 && !IsDesignatedInit) { - if (ToType->isRecordType()) { + if (ToType->isRecordType() && ToType->isAggregateType()) { QualType InitType = From->getInit(0)->getType(); if (S.Context.hasSameUnqualifiedType(InitType, ToType) || S.IsDerivedFrom(From->getBeginLoc(), InitType, ToType)) @@ -6213,7 +6217,15 @@ Sema::EvaluateConvertedConstantExpression(Expr *E, QualType T, APValue &Value, if (Notes.empty()) { // It's a constant expression. - Expr *E = ConstantExpr::Create(Context, Result.get(), Value); + Expr *E = Result.get(); + if (const auto *CE = dyn_cast(E)) { + // We expect a ConstantExpr to have a value associated with it + // by this point. + assert(CE->getResultStorageKind() != ConstantResultStorageKind::None && + "ConstantExpr has no value associated with it"); + } else { + E = ConstantExpr::Create(Context, Result.get(), Value); + } if (!PreNarrowingValue.isAbsent()) Value = std::move(PreNarrowingValue); return E; @@ -7723,9 +7735,19 @@ bool Sema::CheckNonDependentConversions( ++I) { QualType ParamType = ParamTypes[I + Offset]; if (!ParamType->isDependentType()) { - unsigned ConvIdx = PO == OverloadCandidateParamOrder::Reversed - ? 0 - : (ThisConversions + I); + unsigned ConvIdx; + if (PO == OverloadCandidateParamOrder::Reversed) { + ConvIdx = Args.size() - 1 - I; + assert(Args.size() + ThisConversions == 2 && + "number of args (including 'this') must be exactly 2 for " + "reversed order"); + // For members, there would be only one arg 'Args[0]' whose ConvIdx + // would also be 0. 'this' got ConvIdx = 1 previously. + assert(!HasThisConversion || (ConvIdx == 0 && I == 0)); + } else { + // For members, 'this' got ConvIdx = 0 previously. + ConvIdx = ThisConversions + I; + } Conversions[ConvIdx] = TryCopyInitialization(*this, Args[I], ParamType, SuppressUserConversions, @@ -10121,11 +10143,23 @@ getImplicitObjectParamType(ASTContext &Context, const FunctionDecl *F) { return M->getFunctionObjectParameterReferenceType(); } -static bool haveSameParameterTypes(ASTContext &Context, const FunctionDecl *F1, - const FunctionDecl *F2) { +// As a Clang extension, allow ambiguity among F1 and F2 if they represent +// represent the same entity. +static bool allowAmbiguity(ASTContext &Context, const FunctionDecl *F1, + const FunctionDecl *F2) { if (declaresSameEntity(F1, F2)) return true; - + auto PT1 = F1->getPrimaryTemplate(); + auto PT2 = F2->getPrimaryTemplate(); + if (PT1 && PT2) { + if (declaresSameEntity(PT1, PT2) || + declaresSameEntity(PT1->getInstantiatedFromMemberTemplate(), + PT2->getInstantiatedFromMemberTemplate())) + return true; + } + // TODO: It is not clear whether comparing parameters is necessary (i.e. + // different functions with same params). Consider removing this (as no test + // fail w/o it). auto NextParam = [&](const FunctionDecl *F, unsigned &I, bool First) { if (First) { if (std::optional T = getImplicitObjectParamType(Context, F)) @@ -10329,14 +10363,14 @@ bool clang::isBetterOverloadCandidate( case ImplicitConversionSequence::Worse: if (Cand1.Function && Cand2.Function && Cand1.isReversed() != Cand2.isReversed() && - haveSameParameterTypes(S.Context, Cand1.Function, Cand2.Function)) { + allowAmbiguity(S.Context, Cand1.Function, Cand2.Function)) { // Work around large-scale breakage caused by considering reversed // forms of operator== in C++20: // - // When comparing a function against a reversed function with the same - // parameter types, if we have a better conversion for one argument and - // a worse conversion for the other, the implicit conversion sequences - // are treated as being equally good. + // When comparing a function against a reversed function, if we have a + // better conversion for one argument and a worse conversion for the + // other, the implicit conversion sequences are treated as being equally + // good. // // This prevents a comparison function from being considered ambiguous // with a reversed form that is written in the same way. @@ -14298,12 +14332,17 @@ Sema::CreateOverloadedUnaryOp(SourceLocation OpLoc, UnaryOperatorKind Opc, return ExprError(); case OR_Deleted: + // CreateOverloadedUnaryOp fills the first element of ArgsArray with the + // object whose method was called. Later in NoteCandidates size of ArgsArray + // is passed further and it eventually ends up compared to number of + // function candidate parameters which never includes the object parameter, + // so slice ArgsArray to make sure apples are compared to apples. CandidateSet.NoteCandidates( PartialDiagnosticAt(OpLoc, PDiag(diag::err_ovl_deleted_oper) << UnaryOperator::getOpcodeStr(Opc) << Input->getSourceRange()), - *this, OCD_AllCandidates, ArgsArray, UnaryOperator::getOpcodeStr(Opc), - OpLoc); + *this, OCD_AllCandidates, ArgsArray.drop_front(), + UnaryOperator::getOpcodeStr(Opc), OpLoc); return ExprError(); } @@ -14526,7 +14565,7 @@ ExprResult Sema::CreateOverloadedBinOp(SourceLocation OpLoc, llvm::SmallVector AmbiguousWith; for (OverloadCandidate &Cand : CandidateSet) { if (Cand.Viable && Cand.Function && Cand.isReversed() && - haveSameParameterTypes(Context, Cand.Function, FnDecl)) { + allowAmbiguity(Context, Cand.Function, FnDecl)) { for (unsigned ArgIdx = 0; ArgIdx < 2; ++ArgIdx) { if (CompareImplicitConversionSequences( *this, OpLoc, Cand.Conversions[ArgIdx], @@ -15464,7 +15503,7 @@ ExprResult Sema::BuildCallToMemberFunction(Scope *S, Expr *MemExprE, } if (isa(CurContext) && - TheCall->getDirectCallee()->isPure()) { + TheCall->getDirectCallee()->isPureVirtual()) { const FunctionDecl *MD = TheCall->getDirectCallee(); if (isa(MemExpr->getBase()->IgnoreParenCasts()) && diff --git a/clang/lib/Sema/SemaRISCVVectorLookup.cpp b/clang/lib/Sema/SemaRISCVVectorLookup.cpp index 3ed3e619544..00a5ea65f3f 100644 --- a/clang/lib/Sema/SemaRISCVVectorLookup.cpp +++ b/clang/lib/Sema/SemaRISCVVectorLookup.cpp @@ -274,9 +274,8 @@ void RISCVIntrinsicManagerImpl::ConstructRVVIntrinsics( continue; if (BaseType == BasicType::Float16) { - if ((Record.RequiredExtensions & RVV_REQ_ZvfhminOrZvfh) == - RVV_REQ_ZvfhminOrZvfh) { - if (!TI.hasFeature("zvfh") && !TI.hasFeature("zvfhmin")) + if ((Record.RequiredExtensions & RVV_REQ_Zvfhmin) == RVV_REQ_Zvfhmin) { + if (!TI.hasFeature("zvfhmin")) continue; } else if (!TI.hasFeature("zvfh")) { continue; diff --git a/clang/lib/Sema/SemaStmt.cpp b/clang/lib/Sema/SemaStmt.cpp index 21efe25ed84..9e7c8c7e4e8 100644 --- a/clang/lib/Sema/SemaStmt.cpp +++ b/clang/lib/Sema/SemaStmt.cpp @@ -786,6 +786,12 @@ bool Sema::checkMustTailAttr(const Stmt *St, const Attr &MTA) { return false; } + const auto *CalleeDecl = CE->getCalleeDecl(); + if (CalleeDecl && CalleeDecl->hasAttr()) { + Diag(St->getBeginLoc(), diag::err_musttail_no_return) << &MTA; + return false; + } + // Caller and callee must match in whether they have a "this" parameter. if (CallerType.This.isNull() != CalleeType.This.isNull()) { if (const auto *ND = dyn_cast_or_null(CE->getCalleeDecl())) { diff --git a/clang/lib/Sema/SemaTemplate.cpp b/clang/lib/Sema/SemaTemplate.cpp index 5fcc39ec700..9bfa71dc8bc 100644 --- a/clang/lib/Sema/SemaTemplate.cpp +++ b/clang/lib/Sema/SemaTemplate.cpp @@ -1498,7 +1498,7 @@ NamedDecl *Sema::ActOnNonTypeTemplateParameter(Scope *S, Declarator &D, unsigned Position, SourceLocation EqualLoc, Expr *Default) { - TypeSourceInfo *TInfo = GetTypeForDeclarator(D, S); + TypeSourceInfo *TInfo = GetTypeForDeclarator(D); // Check that we have valid decl-specifiers specified. auto CheckValidDeclSpecifiers = [this, &D] { @@ -2418,6 +2418,9 @@ struct ConvertConstructorToDeductionGuideTransform { QualType Result = SemaRef.BuildFunctionType(DeducedType, ParamTypes, Loc, DeductionGuideName, EPI); TypeSourceInfo *TSI = SemaRef.Context.getTrivialTypeSourceInfo(Result, Loc); + if (NestedPattern) + TSI = SemaRef.SubstType(TSI, OuterInstantiationArgs, Loc, + DeductionGuideName); FunctionProtoTypeLoc FPTL = TSI->getTypeLoc().castAs(); @@ -2425,9 +2428,13 @@ struct ConvertConstructorToDeductionGuideTransform { // Build the parameters, needed during deduction / substitution. SmallVector Params; for (auto T : ParamTypes) { - ParmVarDecl *NewParam = ParmVarDecl::Create( - SemaRef.Context, DC, Loc, Loc, nullptr, T, - SemaRef.Context.getTrivialTypeSourceInfo(T, Loc), SC_None, nullptr); + auto *TSI = SemaRef.Context.getTrivialTypeSourceInfo(T, Loc); + if (NestedPattern) + TSI = SemaRef.SubstType(TSI, OuterInstantiationArgs, Loc, + DeclarationName()); + ParmVarDecl *NewParam = + ParmVarDecl::Create(SemaRef.Context, DC, Loc, Loc, nullptr, + TSI->getType(), TSI, SC_None, nullptr); NewParam->setScopeInfo(0, Params.size()); FPTL.setParam(Params.size(), NewParam); Params.push_back(NewParam); @@ -2587,15 +2594,15 @@ private: : ParamTy->isRValueReferenceType() ? VK_XValue : VK_PRValue); } + // Handle arrays and functions decay. + auto NewType = NewDI->getType(); + if (NewType->isArrayType() || NewType->isFunctionType()) + NewType = SemaRef.Context.getDecayedType(NewType); - ParmVarDecl *NewParam = ParmVarDecl::Create(SemaRef.Context, DC, - OldParam->getInnerLocStart(), - OldParam->getLocation(), - OldParam->getIdentifier(), - NewDI->getType(), - NewDI, - OldParam->getStorageClass(), - NewDefArg.get()); + ParmVarDecl *NewParam = ParmVarDecl::Create( + SemaRef.Context, DC, OldParam->getInnerLocStart(), + OldParam->getLocation(), OldParam->getIdentifier(), NewType, NewDI, + OldParam->getStorageClass(), NewDefArg.get()); NewParam->setScopeInfo(OldParam->getFunctionScopeDepth(), OldParam->getFunctionScopeIndex()); SemaRef.CurrentInstantiationScope->InstantiatedLocal(OldParam, NewParam); @@ -2670,8 +2677,14 @@ FunctionTemplateDecl *Sema::DeclareImplicitDeductionGuideFromInitList( if (BuildingDeductionGuides.isInvalid()) return nullptr; - return cast( + ClassTemplateDecl *Pattern = + Transform.NestedPattern ? Transform.NestedPattern : Transform.Template; + ContextRAII SavedContext(*this, Pattern->getTemplatedDecl()); + + auto *DG = cast( Transform.buildSimpleDeductionGuide(ParamTypes)); + SavedContext.pop(); + return DG; } void Sema::DeclareImplicitDeductionGuides(TemplateDecl *Template, @@ -4414,6 +4427,7 @@ static bool isTemplateArgumentTemplateParameter( case TemplateArgument::NullPtr: case TemplateArgument::Integral: case TemplateArgument::Declaration: + case TemplateArgument::StructuralValue: case TemplateArgument::Pack: case TemplateArgument::TemplateExpansion: return false; @@ -5745,6 +5759,7 @@ bool Sema::CheckTemplateArgument( case TemplateArgument::Declaration: case TemplateArgument::Integral: + case TemplateArgument::StructuralValue: case TemplateArgument::NullPtr: // We've already checked this template argument, so just copy // it to the list of converted arguments. @@ -5899,11 +5914,10 @@ bool Sema::CheckTemplateArgument( return true; case TemplateArgument::Declaration: - llvm_unreachable("Declaration argument with template template parameter"); case TemplateArgument::Integral: - llvm_unreachable("Integral argument with template template parameter"); + case TemplateArgument::StructuralValue: case TemplateArgument::NullPtr: - llvm_unreachable("Null pointer argument with template template parameter"); + llvm_unreachable("non-type argument with template template parameter"); case TemplateArgument::Pack: llvm_unreachable("Caller must expand template argument packs"); @@ -7398,44 +7412,9 @@ ExprResult Sema::CheckTemplateArgument(NonTypeTemplateParmDecl *Param, if (ArgResult.isInvalid()) return ExprError(); - // Convert the APValue to a TemplateArgument. - switch (Value.getKind()) { - case APValue::None: - assert(ParamType->isNullPtrType()); - SugaredConverted = TemplateArgument(ParamType, /*isNullPtr=*/true); - CanonicalConverted = TemplateArgument(CanonParamType, /*isNullPtr=*/true); - break; - case APValue::Indeterminate: - llvm_unreachable("result of constant evaluation should be initialized"); - break; - case APValue::Int: - assert(ParamType->isIntegralOrEnumerationType()); - SugaredConverted = TemplateArgument(Context, Value.getInt(), ParamType); - CanonicalConverted = - TemplateArgument(Context, Value.getInt(), CanonParamType); - break; - case APValue::MemberPointer: { - assert(ParamType->isMemberPointerType()); - - // FIXME: We need TemplateArgument representation and mangling for these. - if (!Value.getMemberPointerPath().empty()) { - Diag(Arg->getBeginLoc(), - diag::err_template_arg_member_ptr_base_derived_not_supported) - << Value.getMemberPointerDecl() << ParamType - << Arg->getSourceRange(); - return ExprError(); - } - - auto *VD = const_cast(Value.getMemberPointerDecl()); - SugaredConverted = VD ? TemplateArgument(VD, ParamType) - : TemplateArgument(ParamType, /*isNullPtr=*/true); - CanonicalConverted = - VD ? TemplateArgument(cast(VD->getCanonicalDecl()), - CanonParamType) - : TemplateArgument(CanonParamType, /*isNullPtr=*/true); - break; - } - case APValue::LValue: { + // Prior to C++20, enforce restrictions on possible template argument + // values. + if (!getLangOpts().CPlusPlus20 && Value.isLValue()) { // For a non-type template-parameter of pointer or reference type, // the value of the constant expression shall not refer to assert(ParamType->isPointerType() || ParamType->isReferenceType() || @@ -7453,8 +7432,7 @@ ExprResult Sema::CheckTemplateArgument(NonTypeTemplateParmDecl *Param, << Arg->getSourceRange(); return ExprError(); } - // -- a subobject - // FIXME: Until C++20 + // -- a subobject [until C++20] if (Value.hasLValuePath() && Value.getLValuePath().size() == 1 && VD && VD->getType()->isArrayType() && Value.getLValuePath()[0].getAsArrayIndex() == 0 && @@ -7472,37 +7450,13 @@ ExprResult Sema::CheckTemplateArgument(NonTypeTemplateParmDecl *Param, "null reference should not be a constant expression"); assert((!VD || !ParamType->isNullPtrType()) && "non-null value of type nullptr_t?"); + } - SugaredConverted = VD ? TemplateArgument(VD, ParamType) - : TemplateArgument(ParamType, /*isNullPtr=*/true); - CanonicalConverted = - VD ? TemplateArgument(cast(VD->getCanonicalDecl()), - CanonParamType) - : TemplateArgument(CanonParamType, /*isNullPtr=*/true); - break; - } - case APValue::Struct: - case APValue::Union: { - // Get or create the corresponding template parameter object. - TemplateParamObjectDecl *D = - Context.getTemplateParamObjectDecl(ParamType, Value); - SugaredConverted = TemplateArgument(D, ParamType); - CanonicalConverted = - TemplateArgument(D->getCanonicalDecl(), CanonParamType); - break; - } - case APValue::AddrLabelDiff: + if (Value.isAddrLabelDiff()) return Diag(StartLoc, diag::err_non_type_template_arg_addr_label_diff); - case APValue::FixedPoint: - case APValue::Float: - case APValue::ComplexInt: - case APValue::ComplexFloat: - case APValue::Vector: - case APValue::Array: - return Diag(StartLoc, diag::err_non_type_template_arg_unsupported) - << ParamType; - } + SugaredConverted = TemplateArgument(Context, ParamType, Value); + CanonicalConverted = TemplateArgument(Context, CanonParamType, Value); return ArgResult.get(); } @@ -8086,12 +8040,9 @@ Sema::BuildExpressionFromDeclTemplateArgument(const TemplateArgument &Arg, /// This routine takes care of the mapping from an integral template /// argument (which may have any integral type) to the appropriate /// literal value. -ExprResult -Sema::BuildExpressionFromIntegralTemplateArgument(const TemplateArgument &Arg, - SourceLocation Loc) { - assert(Arg.getKind() == TemplateArgument::Integral && - "Operation is only valid for integral template arguments"); - QualType OrigT = Arg.getIntegralType(); +static Expr *BuildExpressionFromIntegralTemplateArgumentValue( + Sema &S, QualType OrigT, const llvm::APSInt &Int, SourceLocation Loc) { + assert(OrigT->isIntegralOrEnumerationType()); // If this is an enum type that we're instantiating, we need to use an integer // type the same size as the enumerator. We don't want to build an @@ -8107,7 +8058,7 @@ Sema::BuildExpressionFromIntegralTemplateArgument(const TemplateArgument &Arg, CharacterLiteralKind Kind; if (T->isWideCharType()) Kind = CharacterLiteralKind::Wide; - else if (T->isChar8Type() && getLangOpts().Char8) + else if (T->isChar8Type() && S.getLangOpts().Char8) Kind = CharacterLiteralKind::UTF8; else if (T->isChar16Type()) Kind = CharacterLiteralKind::UTF16; @@ -8116,29 +8067,133 @@ Sema::BuildExpressionFromIntegralTemplateArgument(const TemplateArgument &Arg, else Kind = CharacterLiteralKind::Ascii; - E = new (Context) CharacterLiteral(Arg.getAsIntegral().getZExtValue(), - Kind, T, Loc); + E = new (S.Context) CharacterLiteral(Int.getZExtValue(), Kind, T, Loc); } else if (T->isBooleanType()) { - E = CXXBoolLiteralExpr::Create(Context, Arg.getAsIntegral().getBoolValue(), - T, Loc); - } else if (T->isNullPtrType()) { - E = new (Context) CXXNullPtrLiteralExpr(Context.NullPtrTy, Loc); + E = CXXBoolLiteralExpr::Create(S.Context, Int.getBoolValue(), T, Loc); } else { - E = IntegerLiteral::Create(Context, Arg.getAsIntegral(), T, Loc); + E = IntegerLiteral::Create(S.Context, Int, T, Loc); } if (OrigT->isEnumeralType()) { // FIXME: This is a hack. We need a better way to handle substituted // non-type template parameters. - E = CStyleCastExpr::Create(Context, OrigT, VK_PRValue, CK_IntegralCast, E, - nullptr, CurFPFeatureOverrides(), - Context.getTrivialTypeSourceInfo(OrigT, Loc), + E = CStyleCastExpr::Create(S.Context, OrigT, VK_PRValue, CK_IntegralCast, E, + nullptr, S.CurFPFeatureOverrides(), + S.Context.getTrivialTypeSourceInfo(OrigT, Loc), Loc, Loc); } return E; } +static Expr *BuildExpressionFromNonTypeTemplateArgumentValue( + Sema &S, QualType T, const APValue &Val, SourceLocation Loc) { + auto MakeInitList = [&](ArrayRef Elts) -> Expr * { + auto *ILE = new (S.Context) InitListExpr(S.Context, Loc, Elts, Loc); + ILE->setType(T); + return ILE; + }; + + switch (Val.getKind()) { + case APValue::AddrLabelDiff: + // This cannot occur in a template argument at all. + case APValue::Array: + case APValue::Struct: + case APValue::Union: + // These can only occur within a template parameter object, which is + // represented as a TemplateArgument::Declaration. + llvm_unreachable("unexpected template argument value"); + + case APValue::Int: + return BuildExpressionFromIntegralTemplateArgumentValue(S, T, Val.getInt(), + Loc); + + case APValue::Float: + return FloatingLiteral::Create(S.Context, Val.getFloat(), /*IsExact=*/true, + T, Loc); + + case APValue::FixedPoint: + return FixedPointLiteral::CreateFromRawInt( + S.Context, Val.getFixedPoint().getValue(), T, Loc, + Val.getFixedPoint().getScale()); + + case APValue::ComplexInt: { + QualType ElemT = T->castAs()->getElementType(); + return MakeInitList({BuildExpressionFromIntegralTemplateArgumentValue( + S, ElemT, Val.getComplexIntReal(), Loc), + BuildExpressionFromIntegralTemplateArgumentValue( + S, ElemT, Val.getComplexIntImag(), Loc)}); + } + + case APValue::ComplexFloat: { + QualType ElemT = T->castAs()->getElementType(); + return MakeInitList( + {FloatingLiteral::Create(S.Context, Val.getComplexFloatReal(), true, + ElemT, Loc), + FloatingLiteral::Create(S.Context, Val.getComplexFloatImag(), true, + ElemT, Loc)}); + } + + case APValue::Vector: { + QualType ElemT = T->castAs()->getElementType(); + llvm::SmallVector Elts; + for (unsigned I = 0, N = Val.getVectorLength(); I != N; ++I) + Elts.push_back(BuildExpressionFromNonTypeTemplateArgumentValue( + S, ElemT, Val.getVectorElt(I), Loc)); + return MakeInitList(Elts); + } + + case APValue::None: + case APValue::Indeterminate: + llvm_unreachable("Unexpected APValue kind."); + case APValue::LValue: + case APValue::MemberPointer: + // There isn't necessarily a valid equivalent source-level syntax for + // these; in particular, a naive lowering might violate access control. + // So for now we lower to a ConstantExpr holding the value, wrapped around + // an OpaqueValueExpr. + // FIXME: We should have a better representation for this. + ExprValueKind VK = VK_PRValue; + if (T->isReferenceType()) { + T = T->getPointeeType(); + VK = VK_LValue; + } + auto *OVE = new (S.Context) OpaqueValueExpr(Loc, T, VK); + return ConstantExpr::Create(S.Context, OVE, Val); + } + llvm_unreachable("Unhandled APValue::ValueKind enum"); +} + +ExprResult +Sema::BuildExpressionFromNonTypeTemplateArgument(const TemplateArgument &Arg, + SourceLocation Loc) { + switch (Arg.getKind()) { + case TemplateArgument::Null: + case TemplateArgument::Type: + case TemplateArgument::Template: + case TemplateArgument::TemplateExpansion: + case TemplateArgument::Pack: + llvm_unreachable("not a non-type template argument"); + + case TemplateArgument::Expression: + return Arg.getAsExpr(); + + case TemplateArgument::NullPtr: + case TemplateArgument::Declaration: + return BuildExpressionFromDeclTemplateArgument( + Arg, Arg.getNonTypeTemplateArgumentType(), Loc); + + case TemplateArgument::Integral: + return BuildExpressionFromIntegralTemplateArgumentValue( + *this, Arg.getIntegralType(), Arg.getAsIntegral(), Loc); + + case TemplateArgument::StructuralValue: + return BuildExpressionFromNonTypeTemplateArgumentValue( + *this, Arg.getStructuralValueType(), Arg.getAsStructuralValue(), Loc); + } + llvm_unreachable("Unhandled TemplateArgument::ArgKind enum"); +} + /// Match two template parameters within template parameter lists. static bool MatchTemplateParameterKind( Sema &S, NamedDecl *New, @@ -9229,10 +9284,8 @@ void Sema::CheckConceptRedefinition(ConceptDecl *NewDecl, /// that has just been explicitly specialized. static void StripImplicitInstantiation(NamedDecl *D, bool MinGW) { if (MinGW || (isa(D) && - cast(D)->isFunctionTemplateSpecialization())) { - D->dropAttr(); - D->dropAttr(); - } + cast(D)->isFunctionTemplateSpecialization())) + D->dropAttrs(); if (FunctionDecl *FD = dyn_cast(D)) FD->setInlineSpecified(false); @@ -10521,7 +10574,7 @@ DeclResult Sema::ActOnExplicitInstantiation(Scope *S, S = S->getParent(); // Determine the type of the declaration. - TypeSourceInfo *T = GetTypeForDeclarator(D, S); + TypeSourceInfo *T = GetTypeForDeclarator(D); QualType R = T->getType(); if (R.isNull()) return true; diff --git a/clang/lib/Sema/SemaTemplateDeduction.cpp b/clang/lib/Sema/SemaTemplateDeduction.cpp index 015b0abaf0e..e9e7ab5bb66 100644 --- a/clang/lib/Sema/SemaTemplateDeduction.cpp +++ b/clang/lib/Sema/SemaTemplateDeduction.cpp @@ -268,6 +268,16 @@ checkDeducedTemplateArguments(ASTContext &Context, // All other combinations are incompatible. return DeducedTemplateArgument(); + case TemplateArgument::StructuralValue: + // If we deduced a value and a dependent expression, keep the value. + if (Y.getKind() == TemplateArgument::Expression || + (Y.getKind() == TemplateArgument::StructuralValue && + X.structurallyEquals(Y))) + return X; + + // All other combinations are incompatible. + return DeducedTemplateArgument(); + case TemplateArgument::Template: if (Y.getKind() == TemplateArgument::Template && Context.hasSameTemplateName(X.getAsTemplate(), Y.getAsTemplate())) @@ -2300,27 +2310,45 @@ DeduceTemplateArguments(Sema &S, TemplateParameterList *TemplateParams, Info.SecondArg = A; return Sema::TDK_NonDeducedMismatch; + case TemplateArgument::StructuralValue: + if (A.getKind() == TemplateArgument::StructuralValue && + A.structurallyEquals(P)) + return Sema::TDK_Success; + + Info.FirstArg = P; + Info.SecondArg = A; + return Sema::TDK_NonDeducedMismatch; + case TemplateArgument::Expression: if (const NonTypeTemplateParmDecl *NTTP = getDeducedParameterFromExpr(Info, P.getAsExpr())) { - if (A.getKind() == TemplateArgument::Integral) + switch (A.getKind()) { + case TemplateArgument::Integral: + case TemplateArgument::Expression: + case TemplateArgument::StructuralValue: return DeduceNonTypeTemplateArgument( - S, TemplateParams, NTTP, A.getAsIntegral(), A.getIntegralType(), - /*ArrayBound=*/false, Info, Deduced); - if (A.getKind() == TemplateArgument::NullPtr) + S, TemplateParams, NTTP, DeducedTemplateArgument(A), + A.getNonTypeTemplateArgumentType(), Info, Deduced); + + case TemplateArgument::NullPtr: return DeduceNullPtrTemplateArgument(S, TemplateParams, NTTP, A.getNullPtrType(), Info, Deduced); - if (A.getKind() == TemplateArgument::Expression) - return DeduceNonTypeTemplateArgument(S, TemplateParams, NTTP, - A.getAsExpr(), Info, Deduced); - if (A.getKind() == TemplateArgument::Declaration) + + case TemplateArgument::Declaration: return DeduceNonTypeTemplateArgument( S, TemplateParams, NTTP, A.getAsDecl(), A.getParamTypeForDecl(), Info, Deduced); - Info.FirstArg = P; - Info.SecondArg = A; - return Sema::TDK_NonDeducedMismatch; + case TemplateArgument::Null: + case TemplateArgument::Type: + case TemplateArgument::Template: + case TemplateArgument::TemplateExpansion: + case TemplateArgument::Pack: + Info.FirstArg = P; + Info.SecondArg = A; + return Sema::TDK_NonDeducedMismatch; + } + llvm_unreachable("Unknown template argument kind"); } // Can't deduce anything, but that's okay. @@ -2505,6 +2533,9 @@ static bool isSameTemplateArg(ASTContext &Context, case TemplateArgument::Integral: return hasSameExtendedValue(X.getAsIntegral(), Y.getAsIntegral()); + case TemplateArgument::StructuralValue: + return X.structurallyEquals(Y); + case TemplateArgument::Expression: { llvm::FoldingSetNodeID XID, YID; X.getAsExpr()->Profile(XID, Context, true); @@ -2585,9 +2616,9 @@ Sema::getTrivialTemplateArgumentLoc(const TemplateArgument &Arg, E); } - case TemplateArgument::Integral: { - Expr *E = - BuildExpressionFromIntegralTemplateArgument(Arg, Loc).getAs(); + case TemplateArgument::Integral: + case TemplateArgument::StructuralValue: { + Expr *E = BuildExpressionFromNonTypeTemplateArgument(Arg, Loc).get(); return TemplateArgumentLoc(TemplateArgument(E), E); } @@ -6449,11 +6480,8 @@ MarkUsedTemplateParameters(ASTContext &Ctx, case TemplateArgument::Null: case TemplateArgument::Integral: case TemplateArgument::Declaration: - break; - case TemplateArgument::NullPtr: - MarkUsedTemplateParameters(Ctx, TemplateArg.getNullPtrType(), OnlyDeduced, - Depth, Used); + case TemplateArgument::StructuralValue: break; case TemplateArgument::Type: diff --git a/clang/lib/Sema/SemaTemplateInstantiate.cpp b/clang/lib/Sema/SemaTemplateInstantiate.cpp index 7f20413c104..e12186d7d82 100644 --- a/clang/lib/Sema/SemaTemplateInstantiate.cpp +++ b/clang/lib/Sema/SemaTemplateInstantiate.cpp @@ -223,6 +223,9 @@ Response HandleFunction(const FunctionDecl *Function, (!Pattern || !Pattern->getLexicalDeclContext()->isFileContext())) { return Response::ChangeDecl(Function->getLexicalDeclContext()); } + + if (ForConstraintInstantiation && Function->getFriendObjectKind()) + return Response::ChangeDecl(Function->getLexicalDeclContext()); return Response::UseNextDecl(Function); } @@ -1972,9 +1975,8 @@ ExprResult TemplateInstantiator::transformNonTypeTemplateParmRef( } } else if (arg.getKind() == TemplateArgument::Declaration || arg.getKind() == TemplateArgument::NullPtr) { - ValueDecl *VD; if (arg.getKind() == TemplateArgument::Declaration) { - VD = arg.getAsDecl(); + ValueDecl *VD = arg.getAsDecl(); // Find the instantiation of the template argument. This is // required for nested templates. @@ -1982,21 +1984,20 @@ ExprResult TemplateInstantiator::transformNonTypeTemplateParmRef( getSema().FindInstantiatedDecl(loc, VD, TemplateArgs)); if (!VD) return ExprError(); - } else { - // Propagate NULL template argument. - VD = nullptr; } - QualType paramType = VD ? arg.getParamTypeForDecl() : arg.getNullPtrType(); + QualType paramType = arg.getNonTypeTemplateArgumentType(); assert(!paramType.isNull() && "type substitution failed for param type"); assert(!paramType->isDependentType() && "param type still dependent"); result = SemaRef.BuildExpressionFromDeclTemplateArgument(arg, paramType, loc); refParam = paramType->isReferenceType(); } else { - result = SemaRef.BuildExpressionFromIntegralTemplateArgument(arg, loc); + QualType paramType = arg.getNonTypeTemplateArgumentType(); + result = SemaRef.BuildExpressionFromNonTypeTemplateArgument(arg, loc); + refParam = paramType->isReferenceType(); assert(result.isInvalid() || SemaRef.Context.hasSameType(result.get()->getType(), - arg.getIntegralType())); + paramType.getNonReferenceType())); } if (result.isInvalid()) diff --git a/clang/lib/Sema/SemaTemplateInstantiateDecl.cpp b/clang/lib/Sema/SemaTemplateInstantiateDecl.cpp index d768bb72e07..fbc8572ea0e 100644 --- a/clang/lib/Sema/SemaTemplateInstantiateDecl.cpp +++ b/clang/lib/Sema/SemaTemplateInstantiateDecl.cpp @@ -2755,7 +2755,7 @@ Decl *TemplateDeclInstantiator::VisitCXXMethodDecl( IsExplicitSpecialization, Method->isThisDeclarationADefinition()); - if (D->isPure()) + if (D->isPureVirtual()) SemaRef.CheckPureMethod(Method, SourceRange()); // Propagate access. For a non-friend declaration, the access is @@ -3056,16 +3056,21 @@ Decl *TemplateDeclInstantiator::VisitNonTypeTemplateParmDecl( D->getPosition(), D->getIdentifier(), T, D->isParameterPack(), DI); if (AutoTypeLoc AutoLoc = DI->getTypeLoc().getContainedAutoTypeLoc()) - if (AutoLoc.isConstrained()) + if (AutoLoc.isConstrained()) { + SourceLocation EllipsisLoc; + if (IsExpandedParameterPack) + EllipsisLoc = + DI->getTypeLoc().getAs().getEllipsisLoc(); + else if (auto *Constraint = dyn_cast_if_present( + D->getPlaceholderTypeConstraint())) + EllipsisLoc = Constraint->getEllipsisLoc(); // Note: We attach the uninstantiated constriant here, so that it can be - // instantiated relative to the top level, like all our other constraints. - if (SemaRef.AttachTypeConstraint( - AutoLoc, Param, D, - IsExpandedParameterPack - ? DI->getTypeLoc().getAs() - .getEllipsisLoc() - : SourceLocation())) + // instantiated relative to the top level, like all our other + // constraints. + if (SemaRef.AttachTypeConstraint(AutoLoc, /*NewConstrainedParm=*/Param, + /*OrigConstrainedParm=*/D, EllipsisLoc)) Invalid = true; + } Param->setAccess(AS_public); Param->setImplicit(D->isImplicit()); diff --git a/clang/lib/Sema/SemaTemplateVariadic.cpp b/clang/lib/Sema/SemaTemplateVariadic.cpp index 0f4e9e7f94c..4a7872b2cc7 100644 --- a/clang/lib/Sema/SemaTemplateVariadic.cpp +++ b/clang/lib/Sema/SemaTemplateVariadic.cpp @@ -1112,6 +1112,7 @@ TemplateArgumentLoc Sema::getTemplateArgumentPackExpansionPattern( case TemplateArgument::NullPtr: case TemplateArgument::Template: case TemplateArgument::Integral: + case TemplateArgument::StructuralValue: case TemplateArgument::Pack: case TemplateArgument::Null: return TemplateArgumentLoc(); @@ -1162,6 +1163,7 @@ std::optional Sema::getFullyPackExpandedSize(TemplateArgument Arg) { case TemplateArgument::NullPtr: case TemplateArgument::TemplateExpansion: case TemplateArgument::Integral: + case TemplateArgument::StructuralValue: case TemplateArgument::Pack: case TemplateArgument::Null: return std::nullopt; diff --git a/clang/lib/Sema/SemaType.cpp b/clang/lib/Sema/SemaType.cpp index a376f20fa4f..9cb6c0a4ef2 100644 --- a/clang/lib/Sema/SemaType.cpp +++ b/clang/lib/Sema/SemaType.cpp @@ -147,8 +147,10 @@ static void diagnoseBadTypeAttribute(Sema &S, const ParsedAttr &attr, case ParsedAttr::AT_CmseNSCall: \ case ParsedAttr::AT_ArmStreaming: \ case ParsedAttr::AT_ArmStreamingCompatible: \ - case ParsedAttr::AT_ArmSharedZA: \ - case ParsedAttr::AT_ArmPreservesZA: \ + case ParsedAttr::AT_ArmPreserves: \ + case ParsedAttr::AT_ArmIn: \ + case ParsedAttr::AT_ArmOut: \ + case ParsedAttr::AT_ArmInOut: \ case ParsedAttr::AT_AnyX86NoCallerSavedRegisters: \ case ParsedAttr::AT_AnyX86NoCfCheck: \ CALLING_CONV_ATTRS_CASELIST @@ -6068,7 +6070,7 @@ static TypeSourceInfo *GetFullTypeForDeclarator(TypeProcessingState &state, /// /// The result of this call will never be null, but the associated /// type may be a null type if there's an unrecoverable error. -TypeSourceInfo *Sema::GetTypeForDeclarator(Declarator &D, Scope *S) { +TypeSourceInfo *Sema::GetTypeForDeclarator(Declarator &D) { // Determine the type of the declarator. Not all forms of declarator // have a type. @@ -6746,13 +6748,13 @@ void LocInfoType::getAsStringInternal(std::string &Str, " GetTypeFromParser"); } -TypeResult Sema::ActOnTypeName(Scope *S, Declarator &D) { +TypeResult Sema::ActOnTypeName(Declarator &D) { // C99 6.7.6: Type names have no identifier. This is already validated by // the parser. assert(D.getIdentifier() == nullptr && "Type name should have no identifier!"); - TypeSourceInfo *TInfo = GetTypeForDeclarator(D, S); + TypeSourceInfo *TInfo = GetTypeForDeclarator(D); QualType T = TInfo->getType(); if (D.isInvalidType()) return true; @@ -7519,6 +7521,25 @@ static bool HandleWebAssemblyFuncrefAttr(TypeProcessingState &State, return false; } +/// Rebuild an attributed type without the nullability attribute on it. +static QualType rebuildAttributedTypeWithoutNullability(ASTContext &Ctx, + QualType Type) { + auto Attributed = dyn_cast(Type.getTypePtr()); + if (!Attributed) + return Type; + + // Skip the nullability attribute; we're done. + if (Attributed->getImmediateNullability()) + return Attributed->getModifiedType(); + + // Build the modified type. + QualType Modified = rebuildAttributedTypeWithoutNullability( + Ctx, Attributed->getModifiedType()); + assert(Modified.getTypePtr() != Attributed->getModifiedType().getTypePtr()); + return Ctx.getAttributedType(Attributed->getAttrKind(), Modified, + Attributed->getEquivalentType()); +} + /// Map a nullability attribute kind to a nullability kind. static NullabilityKind mapNullabilityAttrKind(ParsedAttr::Kind kind) { switch (kind) { @@ -7539,74 +7560,65 @@ static NullabilityKind mapNullabilityAttrKind(ParsedAttr::Kind kind) { } } -/// Applies a nullability type specifier to the given type, if possible. -/// -/// \param state The type processing state. -/// -/// \param type The type to which the nullability specifier will be -/// added. On success, this type will be updated appropriately. -/// -/// \param attr The attribute as written on the type. -/// -/// \param allowOnArrayType Whether to accept nullability specifiers on an -/// array type (e.g., because it will decay to a pointer). -/// -/// \returns true if a problem has been diagnosed, false on success. -static bool checkNullabilityTypeSpecifier(TypeProcessingState &state, - QualType &type, - ParsedAttr &attr, - bool allowOnArrayType) { - Sema &S = state.getSema(); - - NullabilityKind nullability = mapNullabilityAttrKind(attr.getKind()); - SourceLocation nullabilityLoc = attr.getLoc(); - bool isContextSensitive = attr.isContextSensitiveKeywordAttribute(); - - recordNullabilitySeen(S, nullabilityLoc); +static bool CheckNullabilityTypeSpecifier( + Sema &S, TypeProcessingState *State, ParsedAttr *PAttr, QualType &QT, + NullabilityKind Nullability, SourceLocation NullabilityLoc, + bool IsContextSensitive, bool AllowOnArrayType, bool OverrideExisting) { + bool Implicit = (State == nullptr); + if (!Implicit) + recordNullabilitySeen(S, NullabilityLoc); // Check for existing nullability attributes on the type. - QualType desugared = type; - while (auto attributed = dyn_cast(desugared.getTypePtr())) { + QualType Desugared = QT; + while (auto *Attributed = dyn_cast(Desugared.getTypePtr())) { // Check whether there is already a null - if (auto existingNullability = attributed->getImmediateNullability()) { + if (auto ExistingNullability = Attributed->getImmediateNullability()) { // Duplicated nullability. - if (nullability == *existingNullability) { - S.Diag(nullabilityLoc, diag::warn_nullability_duplicate) - << DiagNullabilityKind(nullability, isContextSensitive) - << FixItHint::CreateRemoval(nullabilityLoc); + if (Nullability == *ExistingNullability) { + if (Implicit) + break; + + S.Diag(NullabilityLoc, diag::warn_nullability_duplicate) + << DiagNullabilityKind(Nullability, IsContextSensitive) + << FixItHint::CreateRemoval(NullabilityLoc); break; } - // Conflicting nullability. - S.Diag(nullabilityLoc, diag::err_nullability_conflicting) - << DiagNullabilityKind(nullability, isContextSensitive) - << DiagNullabilityKind(*existingNullability, false); - return true; + if (!OverrideExisting) { + // Conflicting nullability. + S.Diag(NullabilityLoc, diag::err_nullability_conflicting) + << DiagNullabilityKind(Nullability, IsContextSensitive) + << DiagNullabilityKind(*ExistingNullability, false); + return true; + } + + // Rebuild the attributed type, dropping the existing nullability. + QT = rebuildAttributedTypeWithoutNullability(S.Context, QT); } - desugared = attributed->getModifiedType(); + Desugared = Attributed->getModifiedType(); } // If there is already a different nullability specifier, complain. // This (unlike the code above) looks through typedefs that might // have nullability specifiers on them, which means we cannot // provide a useful Fix-It. - if (auto existingNullability = desugared->getNullability()) { - if (nullability != *existingNullability) { - S.Diag(nullabilityLoc, diag::err_nullability_conflicting) - << DiagNullabilityKind(nullability, isContextSensitive) - << DiagNullabilityKind(*existingNullability, false); + if (auto ExistingNullability = Desugared->getNullability()) { + if (Nullability != *ExistingNullability && !Implicit) { + S.Diag(NullabilityLoc, diag::err_nullability_conflicting) + << DiagNullabilityKind(Nullability, IsContextSensitive) + << DiagNullabilityKind(*ExistingNullability, false); // Try to find the typedef with the existing nullability specifier. - if (auto typedefType = desugared->getAs()) { - TypedefNameDecl *typedefDecl = typedefType->getDecl(); + if (auto TT = Desugared->getAs()) { + TypedefNameDecl *typedefDecl = TT->getDecl(); QualType underlyingType = typedefDecl->getUnderlyingType(); - if (auto typedefNullability - = AttributedType::stripOuterNullability(underlyingType)) { - if (*typedefNullability == *existingNullability) { + if (auto typedefNullability = + AttributedType::stripOuterNullability(underlyingType)) { + if (*typedefNullability == *ExistingNullability) { S.Diag(typedefDecl->getLocation(), diag::note_nullability_here) - << DiagNullabilityKind(*existingNullability, false); + << DiagNullabilityKind(*ExistingNullability, false); } } } @@ -7616,44 +7628,73 @@ static bool checkNullabilityTypeSpecifier(TypeProcessingState &state, } // If this definitely isn't a pointer type, reject the specifier. - if (!desugared->canHaveNullability() && - !(allowOnArrayType && desugared->isArrayType())) { - S.Diag(nullabilityLoc, diag::err_nullability_nonpointer) - << DiagNullabilityKind(nullability, isContextSensitive) << type; + if (!Desugared->canHaveNullability() && + !(AllowOnArrayType && Desugared->isArrayType())) { + if (!Implicit) + S.Diag(NullabilityLoc, diag::err_nullability_nonpointer) + << DiagNullabilityKind(Nullability, IsContextSensitive) << QT; + return true; } // For the context-sensitive keywords/Objective-C property // attributes, require that the type be a single-level pointer. - if (isContextSensitive) { + if (IsContextSensitive) { // Make sure that the pointee isn't itself a pointer type. const Type *pointeeType = nullptr; - if (desugared->isArrayType()) - pointeeType = desugared->getArrayElementTypeNoTypeQual(); - else if (desugared->isAnyPointerType()) - pointeeType = desugared->getPointeeType().getTypePtr(); + if (Desugared->isArrayType()) + pointeeType = Desugared->getArrayElementTypeNoTypeQual(); + else if (Desugared->isAnyPointerType()) + pointeeType = Desugared->getPointeeType().getTypePtr(); if (pointeeType && (pointeeType->isAnyPointerType() || pointeeType->isObjCObjectPointerType() || pointeeType->isMemberPointerType())) { - S.Diag(nullabilityLoc, diag::err_nullability_cs_multilevel) - << DiagNullabilityKind(nullability, true) - << type; - S.Diag(nullabilityLoc, diag::note_nullability_type_specifier) - << DiagNullabilityKind(nullability, false) - << type - << FixItHint::CreateReplacement(nullabilityLoc, - getNullabilitySpelling(nullability)); + S.Diag(NullabilityLoc, diag::err_nullability_cs_multilevel) + << DiagNullabilityKind(Nullability, true) << QT; + S.Diag(NullabilityLoc, diag::note_nullability_type_specifier) + << DiagNullabilityKind(Nullability, false) << QT + << FixItHint::CreateReplacement(NullabilityLoc, + getNullabilitySpelling(Nullability)); return true; } } // Form the attributed type. - type = state.getAttributedType( - createNullabilityAttr(S.Context, attr, nullability), type, type); + if (State) { + assert(PAttr); + Attr *A = createNullabilityAttr(S.Context, *PAttr, Nullability); + QT = State->getAttributedType(A, QT, QT); + } else { + attr::Kind attrKind = AttributedType::getNullabilityAttrKind(Nullability); + QT = S.Context.getAttributedType(attrKind, QT, QT); + } return false; } +static bool CheckNullabilityTypeSpecifier(TypeProcessingState &State, + QualType &Type, ParsedAttr &Attr, + bool AllowOnArrayType) { + NullabilityKind Nullability = mapNullabilityAttrKind(Attr.getKind()); + SourceLocation NullabilityLoc = Attr.getLoc(); + bool IsContextSensitive = Attr.isContextSensitiveKeywordAttribute(); + + return CheckNullabilityTypeSpecifier(State.getSema(), &State, &Attr, Type, + Nullability, NullabilityLoc, + IsContextSensitive, AllowOnArrayType, + /*overrideExisting*/ false); +} + +bool Sema::CheckImplicitNullabilityTypeSpecifier(QualType &Type, + NullabilityKind Nullability, + SourceLocation DiagLoc, + bool AllowArrayTypes, + bool OverrideExisting) { + return CheckNullabilityTypeSpecifier( + *this, nullptr, nullptr, Type, Nullability, DiagLoc, + /*isContextSensitive*/ false, AllowArrayTypes, OverrideExisting); +} + /// Check the application of the Objective-C '__kindof' qualifier to /// the given type. static bool checkObjCKindOfType(TypeProcessingState &state, QualType &type, @@ -7876,6 +7917,52 @@ static bool checkMutualExclusion(TypeProcessingState &state, return true; } +static bool handleArmStateAttribute(Sema &S, + FunctionProtoType::ExtProtoInfo &EPI, + ParsedAttr &Attr, + FunctionType::ArmStateValue State) { + if (!Attr.getNumArgs()) { + S.Diag(Attr.getLoc(), diag::err_missing_arm_state) << Attr; + Attr.setInvalid(); + return true; + } + + for (unsigned I = 0; I < Attr.getNumArgs(); ++I) { + StringRef StateName; + SourceLocation LiteralLoc; + if (!S.checkStringLiteralArgumentAttr(Attr, I, StateName, &LiteralLoc)) + return true; + + unsigned Shift; + FunctionType::ArmStateValue ExistingState; + if (StateName == "za") { + Shift = FunctionType::SME_ZAShift; + ExistingState = FunctionType::getArmZAState(EPI.AArch64SMEAttributes); + } else if (StateName == "zt0") { + Shift = FunctionType::SME_ZT0Shift; + ExistingState = FunctionType::getArmZT0State(EPI.AArch64SMEAttributes); + } else { + S.Diag(LiteralLoc, diag::err_unknown_arm_state) << StateName; + Attr.setInvalid(); + return true; + } + + // __arm_in(S), __arm_out(S), __arm_inout(S) and __arm_preserves(S) + // are all mutually exclusive for the same S, so check if there are + // conflicting attributes. + if (ExistingState != FunctionType::ARM_None && ExistingState != State) { + S.Diag(LiteralLoc, diag::err_conflicting_attributes_arm_state) + << StateName; + Attr.setInvalid(); + return true; + } + + EPI.setArmSMEAttribute( + (FunctionType::AArch64SMETypeAttributes)((State << Shift))); + } + return false; +} + /// Process an individual function attribute. Returns true to /// indicate that the attribute was handled, false if it wasn't. static bool handleFunctionTypeAttr(TypeProcessingState &state, ParsedAttr &attr, @@ -8008,11 +8095,18 @@ static bool handleFunctionTypeAttr(TypeProcessingState &state, ParsedAttr &attr, if (attr.getKind() == ParsedAttr::AT_ArmStreaming || attr.getKind() == ParsedAttr::AT_ArmStreamingCompatible || - attr.getKind() == ParsedAttr::AT_ArmSharedZA || - attr.getKind() == ParsedAttr::AT_ArmPreservesZA){ - if (S.CheckAttrTarget(attr) || S.CheckAttrNoArgs(attr)) + attr.getKind() == ParsedAttr::AT_ArmPreserves || + attr.getKind() == ParsedAttr::AT_ArmIn || + attr.getKind() == ParsedAttr::AT_ArmOut || + attr.getKind() == ParsedAttr::AT_ArmInOut) { + if (S.CheckAttrTarget(attr)) return true; + if (attr.getKind() == ParsedAttr::AT_ArmStreaming || + attr.getKind() == ParsedAttr::AT_ArmStreamingCompatible) + if (S.CheckAttrNoArgs(attr)) + return true; + if (!unwrapped.isFunctionType()) return false; @@ -8039,11 +8133,21 @@ static bool handleFunctionTypeAttr(TypeProcessingState &state, ParsedAttr &attr, return true; EPI.setArmSMEAttribute(FunctionType::SME_PStateSMCompatibleMask); break; - case ParsedAttr::AT_ArmSharedZA: - EPI.setArmSMEAttribute(FunctionType::SME_PStateZASharedMask); + case ParsedAttr::AT_ArmPreserves: + if (handleArmStateAttribute(S, EPI, attr, FunctionType::ARM_Preserves)) + return true; break; - case ParsedAttr::AT_ArmPreservesZA: - EPI.setArmSMEAttribute(FunctionType::SME_PStateZAPreservedMask); + case ParsedAttr::AT_ArmIn: + if (handleArmStateAttribute(S, EPI, attr, FunctionType::ARM_In)) + return true; + break; + case ParsedAttr::AT_ArmOut: + if (handleArmStateAttribute(S, EPI, attr, FunctionType::ARM_Out)) + return true; + break; + case ParsedAttr::AT_ArmInOut: + if (handleArmStateAttribute(S, EPI, attr, FunctionType::ARM_InOut)) + return true; break; default: llvm_unreachable("Unsupported attribute"); @@ -8888,11 +8992,8 @@ static void processTypeAttrs(TypeProcessingState &state, QualType &type, bool allowOnArrayType = state.getDeclarator().isPrototypeContext() && !hasOuterPointerLikeChunk(state.getDeclarator(), endIndex); - if (checkNullabilityTypeSpecifier( - state, - type, - attr, - allowOnArrayType)) { + if (CheckNullabilityTypeSpecifier(state, type, attr, + allowOnArrayType)) { attr.setInvalid(); } diff --git a/clang/lib/Sema/TreeTransform.h b/clang/lib/Sema/TreeTransform.h index 1a1bc87d2b3..e55e752b9cc 100644 --- a/clang/lib/Sema/TreeTransform.h +++ b/clang/lib/Sema/TreeTransform.h @@ -3908,6 +3908,7 @@ public: case TemplateArgument::Null: case TemplateArgument::Integral: case TemplateArgument::Declaration: + case TemplateArgument::StructuralValue: case TemplateArgument::Pack: case TemplateArgument::TemplateExpansion: case TemplateArgument::NullPtr: @@ -4577,7 +4578,8 @@ bool TreeTransform::TransformTemplateArgument( case TemplateArgument::Integral: case TemplateArgument::NullPtr: - case TemplateArgument::Declaration: { + case TemplateArgument::Declaration: + case TemplateArgument::StructuralValue: { // Transform a resolved template argument straight to a resolved template // argument. We get here when substituting into an already-substituted // template type argument during concept satisfaction checking. @@ -4604,9 +4606,15 @@ bool TreeTransform::TransformTemplateArgument( else if (Arg.getKind() == TemplateArgument::NullPtr) Output = TemplateArgumentLoc(TemplateArgument(NewT, /*IsNullPtr=*/true), TemplateArgumentLocInfo()); - else + else if (Arg.getKind() == TemplateArgument::Declaration) Output = TemplateArgumentLoc(TemplateArgument(NewD, NewT), TemplateArgumentLocInfo()); + else if (Arg.getKind() == TemplateArgument::StructuralValue) + Output = TemplateArgumentLoc( + TemplateArgument(getSema().Context, NewT, Arg.getAsStructuralValue()), + TemplateArgumentLocInfo()); + else + llvm_unreachable("unexpected template argument kind"); return false; } @@ -6081,12 +6089,11 @@ QualType TreeTransform::TransformFunctionProtoType(TypeLocBuilder &TLB, FunctionProtoTypeLoc TL) { SmallVector ExceptionStorage; - TreeTransform *This = this; // Work around gcc.gnu.org/PR56135. return getDerived().TransformFunctionProtoType( TLB, TL, nullptr, Qualifiers(), [&](FunctionProtoType::ExceptionSpecInfo &ESI, bool &Changed) { - return This->getDerived().TransformExceptionSpec( - TL.getBeginLoc(), ESI, ExceptionStorage, Changed); + return getDerived().TransformExceptionSpec(TL.getBeginLoc(), ESI, + ExceptionStorage, Changed); }); } @@ -12148,7 +12155,7 @@ TreeTransform::TransformCXXMemberCallExpr(CXXMemberCallExpr *E) { template ExprResult TreeTransform::TransformSourceLocExpr(SourceLocExpr *E) { - bool NeedRebuildFunc = E->getIdentKind() == SourceLocIdentKind::Function && + bool NeedRebuildFunc = SourceLocExpr::MayBeDependent(E->getIdentKind()) && getSema().CurContext != E->getParentContext(); if (!getDerived().AlwaysRebuild() && !NeedRebuildFunc) @@ -13637,12 +13644,11 @@ TreeTransform::TransformLambdaExpr(LambdaExpr *E) { auto TransformFunctionProtoTypeLoc = [this](TypeLocBuilder &TLB, FunctionProtoTypeLoc FPTL) -> QualType { SmallVector ExceptionStorage; - TreeTransform *This = this; // Work around gcc.gnu.org/PR56135. return this->TransformFunctionProtoType( TLB, FPTL, nullptr, Qualifiers(), [&](FunctionProtoType::ExceptionSpecInfo &ESI, bool &Changed) { - return This->TransformExceptionSpec(FPTL.getBeginLoc(), ESI, - ExceptionStorage, Changed); + return TransformExceptionSpec(FPTL.getBeginLoc(), ESI, + ExceptionStorage, Changed); }); }; diff --git a/clang/lib/Serialization/ASTReader.cpp b/clang/lib/Serialization/ASTReader.cpp index 9effd333dac..fecd94e875f 100644 --- a/clang/lib/Serialization/ASTReader.cpp +++ b/clang/lib/Serialization/ASTReader.cpp @@ -3037,12 +3037,17 @@ ASTReader::ReadControlBlock(ModuleFile &F, // location info are setup, in ReadAST. SourceLocation ImportLoc = ReadUntranslatedSourceLocation(Record[Idx++]); - off_t StoredSize = (off_t)Record[Idx++]; - time_t StoredModTime = (time_t)Record[Idx++]; - auto FirstSignatureByte = Record.begin() + Idx; - ASTFileSignature StoredSignature = ASTFileSignature::create( - FirstSignatureByte, FirstSignatureByte + ASTFileSignature::size); - Idx += ASTFileSignature::size; + off_t StoredSize = !IsImportingStdCXXModule ? (off_t)Record[Idx++] : 0; + time_t StoredModTime = + !IsImportingStdCXXModule ? (time_t)Record[Idx++] : 0; + + ASTFileSignature StoredSignature; + if (!IsImportingStdCXXModule) { + auto FirstSignatureByte = Record.begin() + Idx; + StoredSignature = ASTFileSignature::create( + FirstSignatureByte, FirstSignatureByte + ASTFileSignature::size); + Idx += ASTFileSignature::size; + } std::string ImportedName = ReadString(Record, Idx); std::string ImportedFile; @@ -3057,18 +3062,19 @@ ASTReader::ReadControlBlock(ModuleFile &F, ImportedFile = PP.getHeaderSearchInfo().getPrebuiltModuleFileName( ImportedName, /*FileMapOnly*/ !IsImportingStdCXXModule); - if (ImportedFile.empty()) { - // It is deprecated for C++20 Named modules to use the implicitly - // paths. - if (IsImportingStdCXXModule) - Diag(clang::diag::warn_reading_std_cxx_module_by_implicit_paths) - << ImportedName; - - // Use BaseDirectoryAsWritten to ensure we use the same path in the - // ModuleCache as when writing. - ImportedFile = ReadPath(BaseDirectoryAsWritten, Record, Idx); - } else - SkipPath(Record, Idx); + // For C++20 Modules, we won't record the path to the imported modules + // in the BMI + if (!IsImportingStdCXXModule) { + if (ImportedFile.empty()) { + // Use BaseDirectoryAsWritten to ensure we use the same path in the + // ModuleCache as when writing. + ImportedFile = ReadPath(BaseDirectoryAsWritten, Record, Idx); + } else + SkipPath(Record, Idx); + } else if (ImportedFile.empty()) { + Diag(clang::diag::err_failed_to_find_module_file) << ImportedName; + return Missing; + } // If our client can't cope with us being out of date, we can't cope with // our dependency being missing. @@ -5584,8 +5590,23 @@ bool ASTReader::readASTFileControlBlock( while (Idx < N) { // Read information about the AST file. - // Kind, StandardCXXModule, ImportLoc, Size, ModTime, Signature - Idx += 1 + 1 + 1 + 1 + 1 + ASTFileSignature::size; + // Skip Kind + Idx++; + bool IsStandardCXXModule = Record[Idx++]; + + // Skip ImportLoc + Idx++; + + // In C++20 Modules, we don't record the path to imported + // modules in the BMI files. + if (IsStandardCXXModule) { + std::string ModuleName = ReadString(Record, Idx); + Listener.visitImport(ModuleName, /*Filename=*/""); + continue; + } + + // Skip Size, ModTime and Signature + Idx += 1 + 1 + ASTFileSignature::size; std::string ModuleName = ReadString(Record, Idx); std::string Filename = ReadString(Record, Idx); ResolveImportedPath(Filename, ModuleDir); @@ -7439,6 +7460,7 @@ ASTRecordReader::readTemplateArgumentLocInfo(TemplateArgument::ArgKind Kind) { case TemplateArgument::Integral: case TemplateArgument::Declaration: case TemplateArgument::NullPtr: + case TemplateArgument::StructuralValue: case TemplateArgument::Pack: // FIXME: Is this right? return TemplateArgumentLocInfo(); @@ -9512,12 +9534,21 @@ void ASTReader::finishPendingActions() { auto *FD = PendingDeducedFunctionTypes[I].first; FD->setType(GetType(PendingDeducedFunctionTypes[I].second)); - // If we gave a function a deduced return type, remember that we need to - // propagate that along the redeclaration chain. - auto *DT = FD->getReturnType()->getContainedDeducedType(); - if (DT && DT->isDeduced()) - PendingDeducedTypeUpdates.insert( - {FD->getCanonicalDecl(), FD->getReturnType()}); + if (auto *DT = FD->getReturnType()->getContainedDeducedType()) { + // If we gave a function a deduced return type, remember that we need to + // propagate that along the redeclaration chain. + if (DT->isDeduced()) { + PendingDeducedTypeUpdates.insert( + {FD->getCanonicalDecl(), FD->getReturnType()}); + continue; + } + + // The function has undeduced DeduceType return type. We hope we can + // find the deduced type by iterating the redecls in other modules + // later. + PendingUndeducedFunctionDecls.push_back(FD); + continue; + } } PendingDeducedFunctionTypes.clear(); @@ -10083,6 +10114,13 @@ void ASTReader::FinishedDeserializing() { getContext().adjustDeducedFunctionResultType(Update.first, Update.second); } + + auto UDTUpdates = std::move(PendingUndeducedFunctionDecls); + PendingUndeducedFunctionDecls.clear(); + // We hope we can find the deduced type for the functions by iterating + // redeclarations in other modules. + for (FunctionDecl *UndeducedFD : UDTUpdates) + (void)UndeducedFD->getMostRecentDecl(); } if (ReadTimer) diff --git a/clang/lib/Serialization/ASTReaderDecl.cpp b/clang/lib/Serialization/ASTReaderDecl.cpp index 547eb77930b..a149d821530 100644 --- a/clang/lib/Serialization/ASTReaderDecl.cpp +++ b/clang/lib/Serialization/ASTReaderDecl.cpp @@ -910,7 +910,7 @@ void ASTDeclReader::VisitEnumConstantDecl(EnumConstantDecl *ECD) { VisitValueDecl(ECD); if (Record.readInt()) ECD->setInitExpr(Record.readExpr()); - ECD->setInitVal(Record.readAPSInt()); + ECD->setInitVal(Reader.getContext(), Record.readAPSInt()); mergeMergeable(ECD); } @@ -1135,7 +1135,7 @@ void ASTDeclReader::VisitFunctionDecl(FunctionDecl *FD) { // Defer calling `setPure` until merging above has guaranteed we've set // `DefinitionData` (as this will need to access it). - FD->setPure(Pure); + FD->setIsPureVirtual(Pure); // Read in the parameters. unsigned NumParams = Record.readInt(); @@ -3095,6 +3095,8 @@ public: Expr *readExpr() { return Reader.readExpr(); } + Attr *readAttr() { return Reader.readAttr(); } + std::string readString() { return Reader.readString(); } diff --git a/clang/lib/Serialization/ASTReaderStmt.cpp b/clang/lib/Serialization/ASTReaderStmt.cpp index 21aed570ba2..85ecfa1a1a0 100644 --- a/clang/lib/Serialization/ASTReaderStmt.cpp +++ b/clang/lib/Serialization/ASTReaderStmt.cpp @@ -1901,6 +1901,7 @@ void ASTStmtReader::VisitCXXNewExpr(CXXNewExpr *E) { E->CXXNewExprBits.IsGlobalNew = Record.readInt(); E->CXXNewExprBits.ShouldPassAlignment = Record.readInt(); E->CXXNewExprBits.UsualArrayDeleteWantsSize = Record.readInt(); + E->CXXNewExprBits.HasInitializer = Record.readInt(); E->CXXNewExprBits.StoredInitializationStyle = Record.readInt(); assert((IsArray == E->isArray()) && "Wrong IsArray!"); diff --git a/clang/lib/Serialization/ASTWriter.cpp b/clang/lib/Serialization/ASTWriter.cpp index 78939bfd533..03bddfe0f50 100644 --- a/clang/lib/Serialization/ASTWriter.cpp +++ b/clang/lib/Serialization/ASTWriter.cpp @@ -1411,15 +1411,20 @@ void ASTWriter::WriteControlBlock(Preprocessor &PP, ASTContext &Context, Record.push_back(M.StandardCXXModule); AddSourceLocation(M.ImportLoc, Record); - // If we have calculated signature, there is no need to store - // the size or timestamp. - Record.push_back(M.Signature ? 0 : M.File.getSize()); - Record.push_back(M.Signature ? 0 : getTimestampForOutput(M.File)); - - llvm::append_range(Record, M.Signature); + // We don't want to hard code the information about imported modules + // in the C++20 named modules. + if (!M.StandardCXXModule) { + // If we have calculated signature, there is no need to store + // the size or timestamp. + Record.push_back(M.Signature ? 0 : M.File.getSize()); + Record.push_back(M.Signature ? 0 : getTimestampForOutput(M.File)); + llvm::append_range(Record, M.Signature); + } AddString(M.ModuleName, Record); - AddPath(M.FileName, Record); + + if (!M.StandardCXXModule) + AddPath(M.FileName, Record); } Stream.EmitRecord(IMPORTS, Record); } @@ -1892,7 +1897,8 @@ namespace { unsigned char Flags = (Data.AlreadyIncluded << 6) | (Data.HFI.isImport << 5) - | (Data.HFI.isPragmaOnce << 4) + | (Writer.isWritingStdCXXNamedModules() ? 0 : + Data.HFI.isPragmaOnce << 4) | (Data.HFI.DirInfo << 1) | Data.HFI.IndexHeaderMapHeader; LE.write(Flags); @@ -5603,6 +5609,7 @@ void ASTRecordWriter::AddTemplateArgumentLocInfo( case TemplateArgument::Integral: case TemplateArgument::Declaration: case TemplateArgument::NullPtr: + case TemplateArgument::StructuralValue: case TemplateArgument::Pack: // FIXME: Is this right? break; diff --git a/clang/lib/Serialization/ASTWriterDecl.cpp b/clang/lib/Serialization/ASTWriterDecl.cpp index 9e3299f0491..bb1f51786d2 100644 --- a/clang/lib/Serialization/ASTWriterDecl.cpp +++ b/clang/lib/Serialization/ASTWriterDecl.cpp @@ -680,7 +680,7 @@ void ASTDeclWriter::VisitFunctionDecl(FunctionDecl *D) { FunctionDeclBits.addBit(D->isInlined()); FunctionDeclBits.addBit(D->hasSkippedBody()); FunctionDeclBits.addBit(D->isVirtualAsWritten()); - FunctionDeclBits.addBit(D->isPure()); + FunctionDeclBits.addBit(D->isPureVirtual()); FunctionDeclBits.addBit(D->hasInheritedPrototype()); FunctionDeclBits.addBit(D->hasWrittenPrototype()); FunctionDeclBits.addBit(D->isDeletedBit()); diff --git a/clang/lib/Serialization/ASTWriterStmt.cpp b/clang/lib/Serialization/ASTWriterStmt.cpp index 7f888e44dde..e5836f5dcbe 100644 --- a/clang/lib/Serialization/ASTWriterStmt.cpp +++ b/clang/lib/Serialization/ASTWriterStmt.cpp @@ -1901,6 +1901,7 @@ void ASTStmtWriter::VisitCXXNewExpr(CXXNewExpr *E) { Record.push_back(E->isGlobalNew()); Record.push_back(E->passAlignment()); Record.push_back(E->doesUsualArrayDeleteWantSize()); + Record.push_back(E->CXXNewExprBits.HasInitializer); Record.push_back(E->CXXNewExprBits.StoredInitializationStyle); Record.AddDeclRef(E->getOperatorNew()); diff --git a/clang/lib/StaticAnalyzer/Checkers/CheckSecuritySyntaxOnly.cpp b/clang/lib/StaticAnalyzer/Checkers/CheckSecuritySyntaxOnly.cpp index ce05d2d3c90..17af1aebd6d 100644 --- a/clang/lib/StaticAnalyzer/Checkers/CheckSecuritySyntaxOnly.cpp +++ b/clang/lib/StaticAnalyzer/Checkers/CheckSecuritySyntaxOnly.cpp @@ -973,6 +973,8 @@ void WalkAST::checkMsg_decodeValueOfObjCType(const ObjCMessageExpr *ME) { if (VT < VersionTuple(11, 0)) return; break; + case llvm::Triple::XROS: + break; default: return; } diff --git a/clang/lib/StaticAnalyzer/Checkers/LocalizationChecker.cpp b/clang/lib/StaticAnalyzer/Checkers/LocalizationChecker.cpp index de9efe17d22..812d787e2e3 100644 --- a/clang/lib/StaticAnalyzer/Checkers/LocalizationChecker.cpp +++ b/clang/lib/StaticAnalyzer/Checkers/LocalizationChecker.cpp @@ -712,7 +712,7 @@ void NonLocalizedStringChecker::setNonLocalizedState(const SVal S, static bool isDebuggingName(std::string name) { - return StringRef(name).lower().find("debug") != StringRef::npos; + return StringRef(name).contains_insensitive("debug"); } /// Returns true when, heuristically, the analyzer may be analyzing debugging @@ -1248,8 +1248,8 @@ bool PluralMisuseChecker::MethodCrawler::isCheckingPlurality( BO = B; } } - if (VD->getName().lower().find("plural") != StringRef::npos || - VD->getName().lower().find("singular") != StringRef::npos) { + if (VD->getName().contains_insensitive("plural") || + VD->getName().contains_insensitive("singular")) { return true; } } diff --git a/clang/lib/StaticAnalyzer/Checkers/StdLibraryFunctionsChecker.cpp b/clang/lib/StaticAnalyzer/Checkers/StdLibraryFunctionsChecker.cpp index 3b36565681a..fcd907a9bb0 100644 --- a/clang/lib/StaticAnalyzer/Checkers/StdLibraryFunctionsChecker.cpp +++ b/clang/lib/StaticAnalyzer/Checkers/StdLibraryFunctionsChecker.cpp @@ -2146,6 +2146,8 @@ void StdLibraryFunctionsChecker::initFunctionSummaries( ConstraintSet{ReturnValueCondition(WithinRange, SingleValue(0))}; const auto ReturnsMinusOne = ConstraintSet{ReturnValueCondition(WithinRange, SingleValue(-1))}; + const auto ReturnsEOF = + ConstraintSet{ReturnValueCondition(WithinRange, SingleValue(EOFv))}; const auto ReturnsNonnegative = ConstraintSet{ReturnValueCondition(WithinRange, Range(0, IntMax))}; const auto ReturnsNonZero = @@ -2171,6 +2173,16 @@ void StdLibraryFunctionsChecker::initFunctionSummaries( .ArgConstraint(NotNull(ArgNo(0))) .ArgConstraint(NotNull(ArgNo(1)))); + // FILE *fdopen(int fd, const char *mode); + addToFunctionSummaryMap( + "fdopen", + Signature(ArgTypes{IntTy, ConstCharPtrTy}, RetType{FilePtrTy}), + Summary(NoEvalCall) + .Case({NotNull(Ret)}, ErrnoMustNotBeChecked, GenericSuccessMsg) + .Case({IsNull(Ret)}, ErrnoNEZeroIrrelevant, GenericFailureMsg) + .ArgConstraint(ArgumentCondition(0, WithinRange, Range(0, IntMax))) + .ArgConstraint(NotNull(ArgNo(1)))); + // FILE *tmpfile(void); addToFunctionSummaryMap( "tmpfile", Signature(ArgTypes{}, RetType{FilePtrTy}), @@ -2197,8 +2209,7 @@ void StdLibraryFunctionsChecker::initFunctionSummaries( "fclose", Signature(ArgTypes{FilePtrTy}, RetType{IntTy}), Summary(NoEvalCall) .Case(ReturnsZero, ErrnoMustNotBeChecked, GenericSuccessMsg) - .Case({ReturnValueCondition(WithinRange, SingleValue(EOFv))}, - ErrnoNEZeroIrrelevant, GenericFailureMsg) + .Case(ReturnsEOF, ErrnoNEZeroIrrelevant, GenericFailureMsg) .ArgConstraint(NotNull(ArgNo(0)))); // int ungetc(int c, FILE *stream); @@ -2209,7 +2220,7 @@ void StdLibraryFunctionsChecker::initFunctionSummaries( ArgumentCondition(0, WithinRange, {{0, UCharRangeMax}})}, ErrnoMustNotBeChecked, GenericSuccessMsg) .Case({ReturnValueCondition(WithinRange, SingleValue(EOFv)), - ArgumentCondition(0, WithinRange, {{EOFv, EOFv}})}, + ArgumentCondition(0, WithinRange, SingleValue(EOFv))}, ErrnoNEZeroIrrelevant, "Assuming that 'ungetc' fails because EOF was passed as " "character") @@ -2220,6 +2231,9 @@ void StdLibraryFunctionsChecker::initFunctionSummaries( 0, WithinRange, {{EOFv, EOFv}, {0, UCharRangeMax}})) .ArgConstraint(NotNull(ArgNo(1)))); + std::optional Off_tTy = lookupTy("off_t"); + std::optional Off_tMax = getMaxValue(Off_tTy); + // int fseek(FILE *stream, long offset, int whence); // FIXME: It can be possible to get the 'SEEK_' values (like EOFv) and use // these for condition of arg 2. @@ -2232,6 +2246,16 @@ void StdLibraryFunctionsChecker::initFunctionSummaries( .ArgConstraint(NotNull(ArgNo(0))) .ArgConstraint(ArgumentCondition(2, WithinRange, {{0, 2}}))); + // int fseeko(FILE *stream, off_t offset, int whence); + addToFunctionSummaryMap( + "fseeko", + Signature(ArgTypes{FilePtrTy, Off_tTy, IntTy}, RetType{IntTy}), + Summary(NoEvalCall) + .Case(ReturnsZero, ErrnoMustNotBeChecked, GenericSuccessMsg) + .Case(ReturnsMinusOne, ErrnoNEZeroIrrelevant, GenericFailureMsg) + .ArgConstraint(NotNull(ArgNo(0))) + .ArgConstraint(ArgumentCondition(2, WithinRange, {{0, 2}}))); + // int fgetpos(FILE *restrict stream, fpos_t *restrict pos); // From 'The Open Group Base Specifications Issue 7, 2018 edition': // "The fgetpos() function shall not change the setting of errno if @@ -2264,8 +2288,7 @@ void StdLibraryFunctionsChecker::initFunctionSummaries( "fflush", Signature(ArgTypes{FilePtrTy}, RetType{IntTy}), Summary(NoEvalCall) .Case(ReturnsZero, ErrnoMustNotBeChecked, GenericSuccessMsg) - .Case({ReturnValueCondition(WithinRange, SingleValue(EOFv))}, - ErrnoNEZeroIrrelevant, GenericFailureMsg)); + .Case(ReturnsEOF, ErrnoNEZeroIrrelevant, GenericFailureMsg)); // long ftell(FILE *stream); // From 'The Open Group Base Specifications Issue 7, 2018 edition': @@ -2279,6 +2302,15 @@ void StdLibraryFunctionsChecker::initFunctionSummaries( .Case(ReturnsMinusOne, ErrnoNEZeroIrrelevant, GenericFailureMsg) .ArgConstraint(NotNull(ArgNo(0)))); + // off_t ftello(FILE *stream); + addToFunctionSummaryMap( + "ftello", Signature(ArgTypes{FilePtrTy}, RetType{Off_tTy}), + Summary(NoEvalCall) + .Case({ReturnValueCondition(WithinRange, Range(0, Off_tMax))}, + ErrnoMustNotBeChecked, GenericSuccessMsg) + .Case(ReturnsMinusOne, ErrnoNEZeroIrrelevant, GenericFailureMsg) + .ArgConstraint(NotNull(ArgNo(0)))); + // int fileno(FILE *stream); addToFunctionSummaryMap( "fileno", Signature(ArgTypes{FilePtrTy}, RetType{IntTy}), @@ -2410,8 +2442,6 @@ void StdLibraryFunctionsChecker::initFunctionSummaries( .ArgConstraint( ArgumentCondition(0, WithinRange, Range(0, IntMax)))); - std::optional Off_tTy = lookupTy("off_t"); - // int truncate(const char *path, off_t length); addToFunctionSummaryMap( "truncate", @@ -2772,18 +2802,21 @@ void StdLibraryFunctionsChecker::initFunctionSummaries( .ArgConstraint(NotNull(ArgNo(2)))); // DIR *opendir(const char *name); - // FIXME: Improve for errno modeling. addToFunctionSummaryMap( "opendir", Signature(ArgTypes{ConstCharPtrTy}, RetType{DirPtrTy}), - Summary(NoEvalCall).ArgConstraint(NotNull(ArgNo(0)))); + Summary(NoEvalCall) + .Case({NotNull(Ret)}, ErrnoMustNotBeChecked, GenericSuccessMsg) + .Case({IsNull(Ret)}, ErrnoNEZeroIrrelevant, GenericFailureMsg) + .ArgConstraint(NotNull(ArgNo(0)))); // DIR *fdopendir(int fd); - // FIXME: Improve for errno modeling. - addToFunctionSummaryMap("fdopendir", - Signature(ArgTypes{IntTy}, RetType{DirPtrTy}), - Summary(NoEvalCall) - .ArgConstraint(ArgumentCondition( - 0, WithinRange, Range(0, IntMax)))); + addToFunctionSummaryMap( + "fdopendir", Signature(ArgTypes{IntTy}, RetType{DirPtrTy}), + Summary(NoEvalCall) + .Case({NotNull(Ret)}, ErrnoMustNotBeChecked, GenericSuccessMsg) + .Case({IsNull(Ret)}, ErrnoNEZeroIrrelevant, GenericFailureMsg) + .ArgConstraint( + ArgumentCondition(0, WithinRange, Range(0, IntMax)))); // int isatty(int fildes); addToFunctionSummaryMap( @@ -2830,15 +2863,6 @@ void StdLibraryFunctionsChecker::initFunctionSummaries( "pathconf", Signature(ArgTypes{ConstCharPtrTy, IntTy}, RetType{LongTy}), Summary(NoEvalCall).ArgConstraint(NotNull(ArgNo(0)))); - // FILE *fdopen(int fd, const char *mode); - // FIXME: Improve for errno modeling. - addToFunctionSummaryMap( - "fdopen", - Signature(ArgTypes{IntTy, ConstCharPtrTy}, RetType{FilePtrTy}), - Summary(NoEvalCall) - .ArgConstraint(ArgumentCondition(0, WithinRange, Range(0, IntMax))) - .ArgConstraint(NotNull(ArgNo(1)))); - // void rewinddir(DIR *dir); addToFunctionSummaryMap( "rewinddir", Signature(ArgTypes{DirPtrTy}, RetType{VoidTy}), @@ -2854,19 +2878,6 @@ void StdLibraryFunctionsChecker::initFunctionSummaries( "rand_r", Signature(ArgTypes{UnsignedIntPtrTy}, RetType{IntTy}), Summary(NoEvalCall).ArgConstraint(NotNull(ArgNo(0)))); - // int fseeko(FILE *stream, off_t offset, int whence); - addToFunctionSummaryMap( - "fseeko", - Signature(ArgTypes{FilePtrTy, Off_tTy, IntTy}, RetType{IntTy}), - Summary(NoEvalCall) - .Case(ReturnsZeroOrMinusOne, ErrnoIrrelevant) - .ArgConstraint(NotNull(ArgNo(0)))); - - // off_t ftello(FILE *stream); - addToFunctionSummaryMap( - "ftello", Signature(ArgTypes{FilePtrTy}, RetType{Off_tTy}), - Summary(NoEvalCall).ArgConstraint(NotNull(ArgNo(0)))); - // void *mmap(void *addr, size_t length, int prot, int flags, int fd, // off_t offset); // FIXME: Improve for errno modeling. @@ -2991,8 +3002,7 @@ void StdLibraryFunctionsChecker::initFunctionSummaries( "execv", Signature(ArgTypes{ConstCharPtrTy, CharPtrConstPtr}, RetType{IntTy}), Summary(NoEvalCall) - .Case({ReturnValueCondition(WithinRange, SingleValue(-1))}, - ErrnoIrrelevant) + .Case(ReturnsMinusOne, ErrnoIrrelevant) .ArgConstraint(NotNull(ArgNo(0)))); // int execvp(const char *file, char *const argv[]); @@ -3000,8 +3010,7 @@ void StdLibraryFunctionsChecker::initFunctionSummaries( "execvp", Signature(ArgTypes{ConstCharPtrTy, CharPtrConstPtr}, RetType{IntTy}), Summary(NoEvalCall) - .Case({ReturnValueCondition(WithinRange, SingleValue(-1))}, - ErrnoIrrelevant) + .Case(ReturnsMinusOne, ErrnoIrrelevant) .ArgConstraint(NotNull(ArgNo(0)))); // int getopt(int argc, char * const argv[], const char *optstring); diff --git a/clang/lib/StaticAnalyzer/Checkers/StreamChecker.cpp b/clang/lib/StaticAnalyzer/Checkers/StreamChecker.cpp index 742426a628e..07727b339d9 100644 --- a/clang/lib/StaticAnalyzer/Checkers/StreamChecker.cpp +++ b/clang/lib/StaticAnalyzer/Checkers/StreamChecker.cpp @@ -263,9 +263,21 @@ private: {{{"fputs"}, 2}, {std::bind(&StreamChecker::preReadWrite, _1, _2, _3, _4, false), std::bind(&StreamChecker::evalFputx, _1, _2, _3, _4, false), 1}}, + {{{"fprintf"}}, + {std::bind(&StreamChecker::preReadWrite, _1, _2, _3, _4, false), + std::bind(&StreamChecker::evalFprintf, _1, _2, _3, _4), 0}}, + {{{"fscanf"}}, + {std::bind(&StreamChecker::preReadWrite, _1, _2, _3, _4, true), + std::bind(&StreamChecker::evalFscanf, _1, _2, _3, _4), 0}}, {{{"ungetc"}, 2}, {std::bind(&StreamChecker::preReadWrite, _1, _2, _3, _4, false), std::bind(&StreamChecker::evalUngetc, _1, _2, _3, _4), 1}}, + {{{"getdelim"}, 4}, + {std::bind(&StreamChecker::preReadWrite, _1, _2, _3, _4, true), + std::bind(&StreamChecker::evalGetdelim, _1, _2, _3, _4), 3}}, + {{{"getline"}, 3}, + {std::bind(&StreamChecker::preReadWrite, _1, _2, _3, _4, true), + std::bind(&StreamChecker::evalGetdelim, _1, _2, _3, _4), 2}}, {{{"fseek"}, 3}, {&StreamChecker::preFseek, &StreamChecker::evalFseek, 0}}, {{{"fseeko"}, 3}, @@ -339,9 +351,18 @@ private: void evalFputx(const FnDescription *Desc, const CallEvent &Call, CheckerContext &C, bool IsSingleChar) const; + void evalFprintf(const FnDescription *Desc, const CallEvent &Call, + CheckerContext &C) const; + + void evalFscanf(const FnDescription *Desc, const CallEvent &Call, + CheckerContext &C) const; + void evalUngetc(const FnDescription *Desc, const CallEvent &Call, CheckerContext &C) const; + void evalGetdelim(const FnDescription *Desc, const CallEvent &Call, + CheckerContext &C) const; + void preFseek(const FnDescription *Desc, const CallEvent &Call, CheckerContext &C) const; void evalFseek(const FnDescription *Desc, const CallEvent &Call, @@ -926,6 +947,112 @@ void StreamChecker::evalFputx(const FnDescription *Desc, const CallEvent &Call, C.addTransition(StateFailed); } +void StreamChecker::evalFprintf(const FnDescription *Desc, + const CallEvent &Call, + CheckerContext &C) const { + ProgramStateRef State = C.getState(); + if (Call.getNumArgs() < 2) + return; + SymbolRef StreamSym = getStreamArg(Desc, Call).getAsSymbol(); + if (!StreamSym) + return; + + const CallExpr *CE = dyn_cast_or_null(Call.getOriginExpr()); + if (!CE) + return; + + const StreamState *OldSS = State->get(StreamSym); + if (!OldSS) + return; + + assertStreamStateOpened(OldSS); + + NonLoc RetVal = makeRetVal(C, CE).castAs(); + State = State->BindExpr(CE, C.getLocationContext(), RetVal); + SValBuilder &SVB = C.getSValBuilder(); + auto &ACtx = C.getASTContext(); + auto Cond = SVB.evalBinOp(State, BO_GE, RetVal, SVB.makeZeroVal(ACtx.IntTy), + SVB.getConditionType()) + .getAs(); + if (!Cond) + return; + ProgramStateRef StateNotFailed, StateFailed; + std::tie(StateNotFailed, StateFailed) = State->assume(*Cond); + + StateNotFailed = + StateNotFailed->set(StreamSym, StreamState::getOpened(Desc)); + C.addTransition(StateNotFailed); + + // Add transition for the failed state. The resulting value of the file + // position indicator for the stream is indeterminate. + StateFailed = StateFailed->set( + StreamSym, StreamState::getOpened(Desc, ErrorFError, true)); + C.addTransition(StateFailed); +} + +void StreamChecker::evalFscanf(const FnDescription *Desc, const CallEvent &Call, + CheckerContext &C) const { + ProgramStateRef State = C.getState(); + if (Call.getNumArgs() < 2) + return; + SymbolRef StreamSym = getStreamArg(Desc, Call).getAsSymbol(); + if (!StreamSym) + return; + + const CallExpr *CE = dyn_cast_or_null(Call.getOriginExpr()); + if (!CE) + return; + + const StreamState *OldSS = State->get(StreamSym); + if (!OldSS) + return; + + assertStreamStateOpened(OldSS); + + SValBuilder &SVB = C.getSValBuilder(); + ASTContext &ACtx = C.getASTContext(); + + // Add the success state. + // In this context "success" means there is not an EOF or other read error + // before any item is matched in 'fscanf'. But there may be match failure, + // therefore return value can be 0 or greater. + // It is not specified what happens if some items (not all) are matched and + // then EOF or read error happens. Now this case is handled like a "success" + // case, and no error flags are set on the stream. This is probably not + // accurate, and the POSIX documentation does not tell more. + if (OldSS->ErrorState != ErrorFEof) { + NonLoc RetVal = makeRetVal(C, CE).castAs(); + ProgramStateRef StateNotFailed = + State->BindExpr(CE, C.getLocationContext(), RetVal); + auto RetGeZero = + SVB.evalBinOp(StateNotFailed, BO_GE, RetVal, + SVB.makeZeroVal(ACtx.IntTy), SVB.getConditionType()) + .getAs(); + if (!RetGeZero) + return; + StateNotFailed = StateNotFailed->assume(*RetGeZero, true); + + C.addTransition(StateNotFailed); + } + + // Add transition for the failed state. + // Error occurs if nothing is matched yet and reading the input fails. + // Error can be EOF, or other error. At "other error" FERROR or 'errno' can + // be set but it is not further specified if all are required to be set. + // Documentation does not mention, but file position will be set to + // indeterminate similarly as at 'fread'. + ProgramStateRef StateFailed = bindInt(*EofVal, State, C, CE); + StreamErrorState NewES = (OldSS->ErrorState == ErrorFEof) + ? ErrorFEof + : ErrorNone | ErrorFEof | ErrorFError; + StreamState NewSS = StreamState::getOpened(Desc, NewES, !NewES.isFEof()); + StateFailed = StateFailed->set(StreamSym, NewSS); + if (OldSS->ErrorState != ErrorFEof) + C.addTransition(StateFailed, constructSetEofNoteTag(C, StreamSym)); + else + C.addTransition(StateFailed); +} + void StreamChecker::evalUngetc(const FnDescription *Desc, const CallEvent &Call, CheckerContext &C) const { ProgramStateRef State = C.getState(); @@ -965,6 +1092,62 @@ void StreamChecker::evalUngetc(const FnDescription *Desc, const CallEvent &Call, C.addTransition(StateFailed); } +void StreamChecker::evalGetdelim(const FnDescription *Desc, + const CallEvent &Call, + CheckerContext &C) const { + ProgramStateRef State = C.getState(); + SymbolRef StreamSym = getStreamArg(Desc, Call).getAsSymbol(); + if (!StreamSym) + return; + + const CallExpr *CE = dyn_cast_or_null(Call.getOriginExpr()); + if (!CE) + return; + + const StreamState *OldSS = State->get(StreamSym); + if (!OldSS) + return; + + assertStreamStateOpened(OldSS); + + // Upon successful completion, the getline() and getdelim() functions shall + // return the number of bytes written into the buffer. + // If the end-of-file indicator for the stream is set, the function shall + // return -1. + // If an error occurs, the function shall return -1 and set 'errno'. + + // Add transition for the successful state. + if (OldSS->ErrorState != ErrorFEof) { + NonLoc RetVal = makeRetVal(C, CE).castAs(); + ProgramStateRef StateNotFailed = + State->BindExpr(CE, C.getLocationContext(), RetVal); + SValBuilder &SVB = C.getSValBuilder(); + auto Cond = + SVB.evalBinOp(State, BO_GE, RetVal, SVB.makeZeroVal(CE->getType()), + SVB.getConditionType()) + .getAs(); + if (!Cond) + return; + StateNotFailed = StateNotFailed->assume(*Cond, true); + if (!StateNotFailed) + return; + C.addTransition(StateNotFailed); + } + + // Add transition for the failed state. + // If a (non-EOF) error occurs, the resulting value of the file position + // indicator for the stream is indeterminate. + ProgramStateRef StateFailed = bindInt(-1, State, C, CE); + StreamErrorState NewES = + OldSS->ErrorState == ErrorFEof ? ErrorFEof : ErrorFEof | ErrorFError; + StreamState NewSS = StreamState::getOpened(Desc, NewES, !NewES.isFEof()); + StateFailed = StateFailed->set(StreamSym, NewSS); + if (OldSS->ErrorState != ErrorFEof) + C.addTransition(StateFailed, constructSetEofNoteTag(C, StreamSym)); + else + C.addTransition(StateFailed); +} + void StreamChecker::preFseek(const FnDescription *Desc, const CallEvent &Call, CheckerContext &C) const { ProgramStateRef State = C.getState(); diff --git a/clang/lib/StaticAnalyzer/Checkers/VirtualCallChecker.cpp b/clang/lib/StaticAnalyzer/Checkers/VirtualCallChecker.cpp index 1c589e3468c..33a9a07f9d3 100644 --- a/clang/lib/StaticAnalyzer/Checkers/VirtualCallChecker.cpp +++ b/clang/lib/StaticAnalyzer/Checkers/VirtualCallChecker.cpp @@ -116,7 +116,7 @@ void VirtualCallChecker::checkPreCall(const CallEvent &Call, if (!ObState) return; - bool IsPure = MD->isPure(); + bool IsPure = MD->isPureVirtual(); // At this point we're sure that we're calling a virtual method // during construction or destruction, so we'll emit a report. diff --git a/clang/lib/StaticAnalyzer/Core/HTMLDiagnostics.cpp b/clang/lib/StaticAnalyzer/Core/HTMLDiagnostics.cpp index 69d25120dcd..86947b7929e 100644 --- a/clang/lib/StaticAnalyzer/Core/HTMLDiagnostics.cpp +++ b/clang/lib/StaticAnalyzer/Core/HTMLDiagnostics.cpp @@ -68,6 +68,7 @@ class HTMLDiagnostics : public PathDiagnosticConsumer { bool noDir = false; const Preprocessor &PP; const bool SupportsCrossFileDiagnostics; + llvm::StringSet<> EmittedHashes; public: HTMLDiagnostics(PathDiagnosticConsumerOptions DiagOpts, @@ -301,6 +302,17 @@ void HTMLDiagnostics::ReportDiag(const PathDiagnostic& D, } } + SmallString<32> IssueHash = getIssueHash(D, PP); + auto [It, IsNew] = EmittedHashes.insert(IssueHash); + if (!IsNew) { + // We've already emitted a duplicate issue. It'll get overwritten anyway. + return; + } + + // FIXME: This causes each file to be re-parsed and syntax-highlighted + // and macro-expanded separately for each report. We could cache such rewrites + // across all reports and only re-do the part that's actually different: + // the warning/note bubbles. std::string report = GenerateHTML(D, R, SMgr, path, declName.c_str()); if (report.empty()) { llvm::errs() << "warning: no diagnostics generated for main file.\n"; @@ -332,7 +344,7 @@ void HTMLDiagnostics::ReportDiag(const PathDiagnostic& D, << declName.c_str() << "-" << offsetDecl << "-"; } - FileName << StringRef(getIssueHash(D, PP)).substr(0, 6).str() << ".html"; + FileName << StringRef(IssueHash).substr(0, 6).str() << ".html"; SmallString<128> ResultPath; llvm::sys::path::append(ResultPath, Directory, FileName.str()); diff --git a/clang/lib/Tooling/ASTDiff/ASTDiff.cpp b/clang/lib/Tooling/ASTDiff/ASTDiff.cpp index 356b4bd5a1b..5f7153cd53a 100644 --- a/clang/lib/Tooling/ASTDiff/ASTDiff.cpp +++ b/clang/lib/Tooling/ASTDiff/ASTDiff.cpp @@ -453,12 +453,12 @@ std::string SyntaxTree::Impl::getStmtValue(const Stmt *S) const { if (auto *I = dyn_cast(S)) { SmallString<256> Str; I->getValue().toString(Str, /*Radix=*/10, /*Signed=*/false); - return std::string(Str.str()); + return std::string(Str); } if (auto *F = dyn_cast(S)) { SmallString<256> Str; F->getValue().toString(Str); - return std::string(Str.str()); + return std::string(Str); } if (auto *D = dyn_cast(S)) return getRelativeName(D->getDecl(), getEnclosingDeclContext(AST, S)); diff --git a/clang/lib/Tooling/CompilationDatabase.cpp b/clang/lib/Tooling/CompilationDatabase.cpp index 87ad8f25a1a..af18194ae0f 100644 --- a/clang/lib/Tooling/CompilationDatabase.cpp +++ b/clang/lib/Tooling/CompilationDatabase.cpp @@ -156,6 +156,7 @@ private: bool CollectChildren = Collect; switch (A->getKind()) { case driver::Action::CompileJobClass: + case driver::Action::PrecompileJobClass: CollectChildren = true; break; @@ -215,7 +216,7 @@ std::string GetClangToolCommand() { SmallString<128> ClangToolPath; ClangToolPath = llvm::sys::path::parent_path(ClangExecutable); llvm::sys::path::append(ClangToolPath, "clang-tool"); - return std::string(ClangToolPath.str()); + return std::string(ClangToolPath); } } // namespace @@ -293,7 +294,8 @@ static bool stripPositionalArgs(std::vector Args, // -flto* flags make the BackendJobClass, which still needs analyzer. if (Cmd.getSource().getKind() == driver::Action::AssembleJobClass || Cmd.getSource().getKind() == driver::Action::BackendJobClass || - Cmd.getSource().getKind() == driver::Action::CompileJobClass) { + Cmd.getSource().getKind() == driver::Action::CompileJobClass || + Cmd.getSource().getKind() == driver::Action::PrecompileJobClass) { CompileAnalyzer.run(&Cmd.getSource()); } } diff --git a/clang/lib/Tooling/DependencyScanning/DependencyScanningWorker.cpp b/clang/lib/Tooling/DependencyScanning/DependencyScanningWorker.cpp index c54e6d52380..7ab4a699af6 100644 --- a/clang/lib/Tooling/DependencyScanning/DependencyScanningWorker.cpp +++ b/clang/lib/Tooling/DependencyScanning/DependencyScanningWorker.cpp @@ -103,7 +103,7 @@ static void visitPrebuiltModule(StringRef PrebuiltModuleFilename, static std::string makeObjFileName(StringRef FileName) { SmallString<128> ObjFileName(FileName); llvm::sys::path::replace_extension(ObjFileName, "o"); - return std::string(ObjFileName.str()); + return std::string(ObjFileName); } /// Deduce the dependency target based on the output file and input files. diff --git a/clang/lib/Tooling/Syntax/Tokens.cpp b/clang/lib/Tooling/Syntax/Tokens.cpp index 2f28b9cf286..8d32c45a4a7 100644 --- a/clang/lib/Tooling/Syntax/Tokens.cpp +++ b/clang/lib/Tooling/Syntax/Tokens.cpp @@ -401,6 +401,12 @@ std::string TokenBuffer::Mapping::str() const { std::optional> TokenBuffer::spelledForExpanded(llvm::ArrayRef Expanded) const { + // In cases of invalid code, AST nodes can have source ranges that include + // the `eof` token. As there's no spelling for this token, exclude it from + // the range. + if (!Expanded.empty() && Expanded.back().kind() == tok::eof) { + Expanded = Expanded.drop_back(); + } // Mapping an empty range is ambiguous in case of empty mappings at either end // of the range, bail out in that case. if (Expanded.empty()) diff --git a/clang/lib/Tooling/Tooling.cpp b/clang/lib/Tooling/Tooling.cpp index d82cd5e886e..c5c3cdb47e9 100644 --- a/clang/lib/Tooling/Tooling.cpp +++ b/clang/lib/Tooling/Tooling.cpp @@ -261,7 +261,7 @@ llvm::Expected getAbsolutePath(llvm::vfs::FileSystem &FS, if (auto EC = FS.makeAbsolute(AbsolutePath)) return llvm::errorCodeToError(EC); llvm::sys::path::native(AbsolutePath); - return std::string(AbsolutePath.str()); + return std::string(AbsolutePath); } std::string getAbsolutePath(StringRef File) { diff --git a/clang/tools/clang-format/ClangFormat.cpp b/clang/tools/clang-format/ClangFormat.cpp index 49ab7677a3e..5ee6092bb9b 100644 --- a/clang/tools/clang-format/ClangFormat.cpp +++ b/clang/tools/clang-format/ClangFormat.cpp @@ -547,18 +547,20 @@ static void PrintVersion(raw_ostream &OS) { // Dump the configuration. static int dumpConfig(bool IsSTDIN) { std::unique_ptr Code; - // We can't read the code to detect the language if there's no file name. - if (!IsSTDIN) { - // Read in the code in case the filename alone isn't enough to detect the - // language. - ErrorOr> CodeOrErr = - MemoryBuffer::getFileOrSTDIN(FileNames[0]); - if (std::error_code EC = CodeOrErr.getError()) { - llvm::errs() << EC.message() << "\n"; - return 1; - } - Code = std::move(CodeOrErr.get()); + + // `FileNames` must have at least "-" in it even if no file was specified. + assert(!FileNames.empty()); + + // Read in the code in case the filename alone isn't enough to detect the + // language. + ErrorOr> CodeOrErr = + MemoryBuffer::getFileOrSTDIN(FileNames[0]); + if (std::error_code EC = CodeOrErr.getError()) { + llvm::errs() << EC.message() << "\n"; + return 1; } + Code = std::move(CodeOrErr.get()); + llvm::Expected FormatStyle = clang::format::getStyle(Style, IsSTDIN ? AssumeFileName : FileNames[0], FallbackStyle, Code ? Code->getBuffer() : ""); diff --git a/clang/tools/driver/driver.cpp b/clang/tools/driver/driver.cpp index 4adc7f7ad0d..1407c7fcdab 100644 --- a/clang/tools/driver/driver.cpp +++ b/clang/tools/driver/driver.cpp @@ -36,7 +36,6 @@ #include "llvm/Support/CrashRecoveryContext.h" #include "llvm/Support/ErrorHandling.h" #include "llvm/Support/FileSystem.h" -#include "llvm/Support/InitLLVM.h" #include "llvm/Support/LLVMDriver.h" #include "llvm/Support/Path.h" #include "llvm/Support/PrettyStackTrace.h" @@ -65,7 +64,7 @@ std::string GetExecutablePath(const char *Argv0, bool CanonicalPrefixes) { if (llvm::ErrorOr P = llvm::sys::findProgramByName(ExecutablePath)) ExecutablePath = *P; - return std::string(ExecutablePath.str()); + return std::string(ExecutablePath); } // This just needs to be some symbol in the binary; C++ doesn't @@ -377,7 +376,6 @@ static int ExecuteCC1Tool(SmallVectorImpl &ArgV, int clang_main(int Argc, char **Argv, const llvm::ToolContext &ToolContext) { noteBottomOfStack(); - llvm::InitLLVM X(Argc, Argv); llvm::setBugReportMsg("PLEASE submit a bug report to " BUG_REPORT_URL " and include the crash backtrace, preprocessed " "source, and associated run script.\n"); diff --git a/clang/utils/TableGen/ClangAttrEmitter.cpp b/clang/utils/TableGen/ClangAttrEmitter.cpp index 4ec00573e8a..89b88e386f2 100644 --- a/clang/utils/TableGen/ClangAttrEmitter.cpp +++ b/clang/utils/TableGen/ClangAttrEmitter.cpp @@ -1414,7 +1414,29 @@ namespace { } }; -} // end anonymous namespace + class WrappedAttr : public SimpleArgument { + public: + WrappedAttr(const Record &Arg, StringRef Attr) + : SimpleArgument(Arg, Attr, "Attr *") {} + + void writePCHReadDecls(raw_ostream &OS) const override { + OS << " Attr *" << getLowerName() << " = Record.readAttr();"; + } + + void writePCHWrite(raw_ostream &OS) const override { + OS << " AddAttr(SA->get" << getUpperName() << "());"; + } + + void writeDump(raw_ostream &OS) const override {} + + void writeDumpChildren(raw_ostream &OS) const override { + OS << " Visit(SA->get" << getUpperName() << "());\n"; + } + + void writeHasChildren(raw_ostream &OS) const override { OS << "true"; } + }; + + } // end anonymous namespace static std::unique_ptr createArgument(const Record &Arg, StringRef Attr, @@ -1470,6 +1492,8 @@ createArgument(const Record &Arg, StringRef Attr, Ptr = std::make_unique(Arg, Attr); else if (ArgName == "VersionArgument") Ptr = std::make_unique(Arg, Attr); + else if (ArgName == "WrappedAttr") + Ptr = std::make_unique(Arg, Attr); else if (ArgName == "OMPTraitInfoArgument") Ptr = std::make_unique(Arg, Attr, "OMPTraitInfo *"); else if (ArgName == "VariadicOMPInteropInfoArgument") @@ -1722,8 +1746,7 @@ SpellingNamesAreCommon(const std::vector& Spellings) { assert(!Spellings.empty() && "An empty list of spellings was provided"); std::string FirstName = std::string(NormalizeNameForSpellingComparison(Spellings.front().name())); - for (const auto &Spelling : - llvm::make_range(std::next(Spellings.begin()), Spellings.end())) { + for (const auto &Spelling : llvm::drop_begin(Spellings)) { std::string Name = std::string(NormalizeNameForSpellingComparison(Spelling.name())); if (Name != FirstName) @@ -1896,7 +1919,7 @@ struct AttributeSubjectMatchRule { } if (isAbstractRule()) Result += "_abstract"; - return std::string(Result.str()); + return std::string(Result); } std::string getEnumValue() const { return "attr::" + getEnumValueName(); } @@ -3547,23 +3570,27 @@ static void GenerateHasAttrSpellingStringSwitch( OS << " .Default(0);\n"; } -// Emits the list of tokens for regular keyword attributes. -void EmitClangAttrTokenKinds(RecordKeeper &Records, raw_ostream &OS) { - emitSourceFileHeader("A list of tokens generated from the attribute" - " definitions", - OS); +// Emits list of regular keyword attributes with info about their arguments. +void EmitClangRegularKeywordAttributeInfo(RecordKeeper &Records, + raw_ostream &OS) { + emitSourceFileHeader( + "A list of regular keyword attributes generated from the attribute" + " definitions", + OS); // Assume for now that the same token is not used in multiple regular // keyword attributes. for (auto *R : Records.getAllDerivedDefinitions("Attr")) - for (const auto &S : GetFlattenedSpellings(*R)) - if (isRegularKeywordAttribute(S)) { - if (!R->getValueAsListOfDefs("Args").empty()) - PrintError(R->getLoc(), - "RegularKeyword attributes with arguments are not " - "yet supported"); - OS << "KEYWORD_ATTRIBUTE(" - << S.getSpellingRecord().getValueAsString("Name") << ")\n"; - } + for (const auto &S : GetFlattenedSpellings(*R)) { + if (!isRegularKeywordAttribute(S)) + continue; + std::vector Args = R->getValueAsListOfDefs("Args"); + bool HasArgs = llvm::any_of( + Args, [](const Record *Arg) { return !Arg->getValueAsBit("Fake"); }); + + OS << "KEYWORD_ATTRIBUTE(" + << S.getSpellingRecord().getValueAsString("Name") << ", " + << (HasArgs ? "true" : "false") << ", )\n"; + } OS << "#undef KEYWORD_ATTRIBUTE\n"; } diff --git a/clang/utils/TableGen/ClangCommentHTMLNamedCharacterReferenceEmitter.cpp b/clang/utils/TableGen/ClangCommentHTMLNamedCharacterReferenceEmitter.cpp index 47b871afdee..f1cd9af0519 100644 --- a/clang/utils/TableGen/ClangCommentHTMLNamedCharacterReferenceEmitter.cpp +++ b/clang/utils/TableGen/ClangCommentHTMLNamedCharacterReferenceEmitter.cpp @@ -66,7 +66,7 @@ void clang::EmitClangCommentHTMLNamedCharacterReferences(RecordKeeper &Records, } CLiteral.append(";"); - StringMatcher::StringPair Match(Spelling, std::string(CLiteral.str())); + StringMatcher::StringPair Match(Spelling, std::string(CLiteral)); NameToUTF8.push_back(Match); } diff --git a/clang/utils/TableGen/ClangDiagnosticsEmitter.cpp b/clang/utils/TableGen/ClangDiagnosticsEmitter.cpp index a8a80ed882b..480c7c83f5f 100644 --- a/clang/utils/TableGen/ClangDiagnosticsEmitter.cpp +++ b/clang/utils/TableGen/ClangDiagnosticsEmitter.cpp @@ -1343,7 +1343,7 @@ static std::string getDiagCategoryEnum(llvm::StringRef name) { SmallString<256> enumName = llvm::StringRef("DiagCat_"); for (llvm::StringRef::iterator I = name.begin(), E = name.end(); I != E; ++I) enumName += isalnum(*I) ? *I : '_'; - return std::string(enumName.str()); + return std::string(enumName); } /// Emit the array of diagnostic subgroups. diff --git a/clang/utils/TableGen/MveEmitter.cpp b/clang/utils/TableGen/MveEmitter.cpp index f0bd0865c1c..496cb10d14f 100644 --- a/clang/utils/TableGen/MveEmitter.cpp +++ b/clang/utils/TableGen/MveEmitter.cpp @@ -896,7 +896,7 @@ public: llvm::APInt i = iOrig.trunc(64); SmallString<40> s; i.toString(s, 16, true, true); - return std::string(s.str()); + return std::string(s); } std::string genSema() const { diff --git a/clang/utils/TableGen/RISCVVEmitter.cpp b/clang/utils/TableGen/RISCVVEmitter.cpp index d570bcae8d8..2ca47f1ba59 100644 --- a/clang/utils/TableGen/RISCVVEmitter.cpp +++ b/clang/utils/TableGen/RISCVVEmitter.cpp @@ -656,7 +656,7 @@ void RVVEmitter::createRVVIntrinsics( RVVRequire RequireExt = StringSwitch(RequiredFeature) .Case("RV64", RVV_REQ_RV64) - .Case("ZvfhminOrZvfh", RVV_REQ_ZvfhminOrZvfh) + .Case("Zvfhmin", RVV_REQ_Zvfhmin) .Case("Xsfvcp", RVV_REQ_Xsfvcp) .Case("Xsfvfnrclipxfqf", RVV_REQ_Xsfvfnrclipxfqf) .Case("Xsfvfwmaccqqq", RVV_REQ_Xsfvfwmaccqqq) diff --git a/clang/utils/TableGen/SveEmitter.cpp b/clang/utils/TableGen/SveEmitter.cpp index 5de2223e71b..174304f0900 100644 --- a/clang/utils/TableGen/SveEmitter.cpp +++ b/clang/utils/TableGen/SveEmitter.cpp @@ -1066,17 +1066,6 @@ void Intrinsic::emitIntrinsic(raw_ostream &OS, SVEEmitter &Emitter, std::string FullName = mangleName(ClassS); std::string ProtoName = mangleName(getClassKind()); - std::string SMEAttrs = ""; - - if (Flags & Emitter.getEnumValueForFlag("IsStreaming")) - SMEAttrs += ", arm_streaming"; - if (Flags & Emitter.getEnumValueForFlag("IsStreamingCompatible")) - SMEAttrs += ", arm_streaming_compatible"; - if (Flags & Emitter.getEnumValueForFlag("IsSharedZA")) - SMEAttrs += ", arm_shared_za"; - if (Flags & Emitter.getEnumValueForFlag("IsPreservesZA")) - SMEAttrs += ", arm_preserves_za"; - OS << (IsOverloaded ? "__aio " : "__ai ") << "__attribute__((__clang_arm_builtin_alias("; @@ -1089,8 +1078,6 @@ void Intrinsic::emitIntrinsic(raw_ostream &OS, SVEEmitter &Emitter, break; } - if (!SMEAttrs.empty()) - OS << SMEAttrs; OS << "))\n"; OS << getTypes()[0].str() << " " << ProtoName << "("; @@ -1571,7 +1558,7 @@ void SVEEmitter::createTypeFlags(raw_ostream &OS) { } void SVEEmitter::createSMEHeader(raw_ostream &OS) { - OS << "/*===---- arm_sme_draft_spec_subject_to_change.h - ARM SME intrinsics " + OS << "/*===---- arm_sme.h - ARM SME intrinsics " "------===\n" " *\n" " *\n" @@ -1588,7 +1575,7 @@ void SVEEmitter::createSMEHeader(raw_ostream &OS) { OS << "#define __ARM_SME_H\n\n"; OS << "#if !defined(__LITTLE_ENDIAN__)\n"; - OS << "#error \"Big endian is currently not supported for arm_sme_draft_spec_subject_to_change.h\"\n"; + OS << "#error \"Big endian is currently not supported for arm_sme.h\"\n"; OS << "#endif\n"; OS << "#include \n\n"; @@ -1619,7 +1606,7 @@ void SVEEmitter::createSMEHeader(raw_ostream &OS) { OS << "}\n\n"; OS << "__ai __attribute__((target(\"sme\"))) void svundef_za(void) " - "__arm_streaming_compatible __arm_shared_za " + "__arm_streaming_compatible __arm_out(\"za\") " "{ }\n\n"; createCoreHeaderIntrinsics(OS, *this, ACLEKind::SME); @@ -1733,21 +1720,36 @@ void SVEEmitter::createBuiltinZAState(raw_ostream &OS) { for (auto *R : RV) createIntrinsic(R, Defs); - std::map> DefsZAState; - - uint64_t IsSharedZAFlag = getEnumValueForFlag("IsSharedZA"); + std::map> IntrinsicsPerState; for (auto &Def : Defs) { - bool HasZAState = Def->isFlagSet(IsSharedZAFlag); - DefsZAState[HasZAState].insert(Def->getMangledName()); + std::string Key; + auto AddToKey = [&Key](const std::string &S) -> void { + Key = Key.empty() ? S : (Key + " | " + S); + }; + + if (Def->isFlagSet(getEnumValueForFlag("IsInZA"))) + AddToKey("ArmInZA"); + else if (Def->isFlagSet(getEnumValueForFlag("IsOutZA"))) + AddToKey("ArmOutZA"); + else if (Def->isFlagSet(getEnumValueForFlag("IsInOutZA"))) + AddToKey("ArmInOutZA"); + + if (Def->isFlagSet(getEnumValueForFlag("IsInZT0"))) + AddToKey("ArmInZT0"); + else if (Def->isFlagSet(getEnumValueForFlag("IsOutZT0"))) + AddToKey("ArmOutZT0"); + else if (Def->isFlagSet(getEnumValueForFlag("IsInOutZT0"))) + AddToKey("ArmInOutZT0"); + + if (!Key.empty()) + IntrinsicsPerState[Key].insert(Def->getMangledName()); } - OS << "#ifdef GET_SME_BUILTIN_HAS_ZA_STATE\n"; - - for (auto HasZA : {true, false}) { - auto Names = DefsZAState[HasZA]; - for (auto Name : Names) + OS << "#ifdef GET_SME_BUILTIN_GET_STATE\n"; + for (auto &KV : IntrinsicsPerState) { + for (StringRef Name : KV.second) OS << "case SME::BI__builtin_sme_" << Name << ":\n"; - OS << " return " << (HasZA ? "true" : "false") << ";\n"; + OS << " return " << KV.first << ";\n"; } OS << "#endif\n\n"; } diff --git a/clang/utils/TableGen/TableGen.cpp b/clang/utils/TableGen/TableGen.cpp index 3859555d647..158d10e2b3d 100644 --- a/clang/utils/TableGen/TableGen.cpp +++ b/clang/utils/TableGen/TableGen.cpp @@ -37,7 +37,7 @@ enum ActionType { GenClangAttrSubjectMatchRuleList, GenClangAttrPCHRead, GenClangAttrPCHWrite, - GenClangAttrTokenKinds, + GenClangRegularKeywordAttributeInfo, GenClangAttrHasAttributeImpl, GenClangAttrSpellingListIndex, GenClangAttrASTVisitor, @@ -150,8 +150,10 @@ cl::opt Action( "Generate clang PCH attribute reader"), clEnumValN(GenClangAttrPCHWrite, "gen-clang-attr-pch-write", "Generate clang PCH attribute writer"), - clEnumValN(GenClangAttrTokenKinds, "gen-clang-attr-token-kinds", - "Generate a list of attribute-related clang tokens"), + clEnumValN(GenClangRegularKeywordAttributeInfo, + "gen-clang-regular-keyword-attr-info", + "Generate a list of regular keyword attributes with info " + "about their arguments"), clEnumValN(GenClangAttrHasAttributeImpl, "gen-clang-attr-has-attribute-impl", "Generate a clang attribute spelling list"), @@ -291,11 +293,14 @@ cl::opt Action( "Generate riscv_vector_builtin_cg.inc for clang"), clEnumValN(GenRISCVVectorBuiltinSema, "gen-riscv-vector-builtin-sema", "Generate riscv_vector_builtin_sema.inc for clang"), - clEnumValN(GenRISCVSiFiveVectorBuiltins, "gen-riscv-sifive-vector-builtins", + clEnumValN(GenRISCVSiFiveVectorBuiltins, + "gen-riscv-sifive-vector-builtins", "Generate riscv_sifive_vector_builtins.inc for clang"), - clEnumValN(GenRISCVSiFiveVectorBuiltinCG, "gen-riscv-sifive-vector-builtin-codegen", + clEnumValN(GenRISCVSiFiveVectorBuiltinCG, + "gen-riscv-sifive-vector-builtin-codegen", "Generate riscv_sifive_vector_builtin_cg.inc for clang"), - clEnumValN(GenRISCVSiFiveVectorBuiltinSema, "gen-riscv-sifive-vector-builtin-sema", + clEnumValN(GenRISCVSiFiveVectorBuiltinSema, + "gen-riscv-sifive-vector-builtin-sema", "Generate riscv_sifive_vector_builtin_sema.inc for clang"), clEnumValN(GenAttrDocs, "gen-attr-docs", "Generate attribute documentation"), @@ -355,8 +360,8 @@ bool ClangTableGenMain(raw_ostream &OS, RecordKeeper &Records) { case GenClangAttrPCHWrite: EmitClangAttrPCHWrite(Records, OS); break; - case GenClangAttrTokenKinds: - EmitClangAttrTokenKinds(Records, OS); + case GenClangRegularKeywordAttributeInfo: + EmitClangRegularKeywordAttributeInfo(Records, OS); break; case GenClangAttrHasAttributeImpl: EmitClangAttrHasAttrImpl(Records, OS); diff --git a/clang/utils/TableGen/TableGenBackends.h b/clang/utils/TableGen/TableGenBackends.h index faa0c5d2cff..58a4af3c23a 100644 --- a/clang/utils/TableGen/TableGenBackends.h +++ b/clang/utils/TableGen/TableGenBackends.h @@ -53,8 +53,8 @@ void EmitClangAttrSubjectMatchRuleList(llvm::RecordKeeper &Records, llvm::raw_ostream &OS); void EmitClangAttrPCHRead(llvm::RecordKeeper &Records, llvm::raw_ostream &OS); void EmitClangAttrPCHWrite(llvm::RecordKeeper &Records, llvm::raw_ostream &OS); -void EmitClangAttrTokenKinds(llvm::RecordKeeper &Records, - llvm::raw_ostream &OS); +void EmitClangRegularKeywordAttributeInfo(llvm::RecordKeeper &Records, + llvm::raw_ostream &OS); void EmitClangAttrHasAttrImpl(llvm::RecordKeeper &Records, llvm::raw_ostream &OS); void EmitClangAttrSpellingListIndex(llvm::RecordKeeper &Records, diff --git a/compiler-rt/include/profile/instr_prof_interface.h b/compiler-rt/include/profile/instr_prof_interface.h new file mode 100644 index 00000000000..be40f268593 --- /dev/null +++ b/compiler-rt/include/profile/instr_prof_interface.h @@ -0,0 +1,92 @@ +/*===---- instr_prof_interface.h - Instrumentation PGO User Program API ----=== + * + * Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. + * See https://llvm.org/LICENSE.txt for license information. + * SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception + * + *===-----------------------------------------------------------------------=== + * + * This header provides a public interface for fine-grained control of counter + * reset and profile dumping. These interface functions can be directly called + * in user programs. + * +\*===---------------------------------------------------------------------===*/ + +#ifndef COMPILER_RT_INSTR_PROFILING +#define COMPILER_RT_INSTR_PROFILING + +#ifdef __cplusplus +extern "C" { +#endif + +#ifdef __LLVM_INSTR_PROFILE_GENERATE +// Profile file reset and dump interfaces. +// When `-fprofile[-instr]-generate`/`-fcs-profile-generate` is in effect, +// clang defines __LLVM_INSTR_PROFILE_GENERATE to pick up the API calls. + +/*! + * \brief Set the filename for writing instrumentation data. + * + * Sets the filename to be used for subsequent calls to + * \a __llvm_profile_write_file(). + * + * \c Name is not copied, so it must remain valid. Passing NULL resets the + * filename logic to the default behaviour. + * + * Note: There may be multiple copies of the profile runtime (one for each + * instrumented image/DSO). This API only modifies the filename within the + * copy of the runtime available to the calling image. + * + * Warning: This is a no-op if continuous mode (\ref + * __llvm_profile_is_continuous_mode_enabled) is on. The reason for this is + * that in continuous mode, profile counters are mmap()'d to the profile at + * program initialization time. Support for transferring the mmap'd profile + * counts to a new file has not been implemented. + */ +void __llvm_profile_set_filename(const char *Name); + +/*! + * \brief Interface to set all PGO counters to zero for the current process. + * + */ +void __llvm_profile_reset_counters(void); + +/*! + * \brief this is a wrapper interface to \c __llvm_profile_write_file. + * After this interface is invoked, an already dumped flag will be set + * so that profile won't be dumped again during program exit. + * Invocation of interface __llvm_profile_reset_counters will clear + * the flag. This interface is designed to be used to collect profile + * data from user selected hot regions. The use model is + * __llvm_profile_reset_counters(); + * ... hot region 1 + * __llvm_profile_dump(); + * .. some other code + * __llvm_profile_reset_counters(); + * ... hot region 2 + * __llvm_profile_dump(); + * + * It is expected that on-line profile merging is on with \c %m specifier + * used in profile filename . If merging is not turned on, user is expected + * to invoke __llvm_profile_set_filename to specify different profile names + * for different regions before dumping to avoid profile write clobbering. + */ +int __llvm_profile_dump(void); + +// Interface to dump the current process' order file to disk. +int __llvm_orderfile_dump(void); + +#else + +#define __llvm_profile_set_filename(Name) +#define __llvm_profile_reset_counters() +#define __llvm_profile_dump() (0) +#define __llvm_orderfile_dump() (0) + +#endif + +#ifdef __cplusplus +} // extern "C" +#endif + +#endif diff --git a/compiler-rt/lib/asan/asan_win.cpp b/compiler-rt/lib/asan/asan_win.cpp index f16ce677618..8507e675684 100644 --- a/compiler-rt/lib/asan/asan_win.cpp +++ b/compiler-rt/lib/asan/asan_win.cpp @@ -266,12 +266,7 @@ void PlatformTSDDtor(void *tsd) { AsanThread::TSDDtor(tsd); } // }}} // ---------------------- Various stuff ---------------- {{{ -void *AsanDoesNotSupportStaticLinkage() { -#if defined(_DEBUG) -#error Please build the runtime with a non-debug CRT: /MD or /MT -#endif - return 0; -} +void *AsanDoesNotSupportStaticLinkage() { return 0; } uptr FindDynamicShadowStart() { return MapDynamicShadow(MemToShadowSize(kHighMemEnd), ASAN_SHADOW_SCALE, diff --git a/compiler-rt/lib/builtins/aarch64/sme-libc-routines.c b/compiler-rt/lib/builtins/aarch64/sme-libc-routines.c new file mode 100644 index 00000000000..cd73025a19c --- /dev/null +++ b/compiler-rt/lib/builtins/aarch64/sme-libc-routines.c @@ -0,0 +1,87 @@ +#include + +// WARNING: When building the scalar versions of these functions you need to +// use the compiler flag "-mllvm -disable-loop-idiom-all" to prevent clang +// from recognising a loop idiom and planting calls to memcpy! + +static void *__arm_sc_memcpy_fwd(void *dest, const void *src, + size_t n) __arm_streaming_compatible { + unsigned char *destp = (unsigned char *)dest; + const unsigned char *srcp = (const unsigned char *)src; + for (size_t i = 0; i < n; ++i) + destp[i] = srcp[i]; + + return dest; +} + +// If dest and src overlap then behaviour is undefined, hence we can add the +// restrict keywords here. This also matches the definition of the libc memcpy +// according to the man page. +void *__arm_sc_memcpy(void *__restrict__ dest, const void *__restrict__ src, + size_t n) __arm_streaming_compatible { + return __arm_sc_memcpy_fwd(dest, src, n); +} + +void *__arm_sc_memset(void *dest, int c, size_t n) __arm_streaming_compatible { + unsigned char *destp = (unsigned char *)dest; + unsigned char c8 = (unsigned char)c; + for (size_t i = 0; i < n; ++i) + destp[i] = c8; + + return dest; +} + +static void *__arm_sc_memcpy_rev(void *dest, const void *src, + size_t n) __arm_streaming_compatible { + unsigned char *destp = (unsigned char *)dest; + const unsigned char *srcp = (const unsigned char *)src; + // TODO: Improve performance by copying larger chunks in reverse, or by + // using SVE. + while (n > 0) { + --n; + destp[n] = srcp[n]; + } + return dest; +} + +// Semantically a memmove is equivalent to the following: +// 1. Copy the entire contents of src to a temporary array that does not +// overlap with src or dest. +// 2. Copy the contents of the temporary array into dest. +void *__arm_sc_memmove(void *dest, const void *src, + size_t n) __arm_streaming_compatible { + unsigned char *destp = (unsigned char *)dest; + const unsigned char *srcp = (const unsigned char *)src; + + // If src and dest don't overlap then just invoke memcpy + if ((srcp > (destp + n)) || (destp > (srcp + n))) + return __arm_sc_memcpy_fwd(dest, src, n); + + // Overlap case 1: + // src: Low | -> | High + // dest: Low | -> | High + // Here src is always ahead of dest at a higher addres. If we first read a + // chunk of data from src we can safely write the same chunk to dest without + // corrupting future reads of src. + if (srcp > destp) + return __arm_sc_memcpy_fwd(dest, src, n); + + // Overlap case 2: + // src: Low | -> | High + // dest: Low | -> | High + // While we're in the overlap region we're always corrupting future reads of + // src when writing to dest. An efficient way to do this is to copy the data + // in reverse by starting at the highest address. + return __arm_sc_memcpy_rev(dest, src, n); +} + +const void *__arm_sc_memchr(const void *src, int c, + size_t n) __arm_streaming_compatible { + const unsigned char *srcp = (const unsigned char *)src; + unsigned char c8 = (unsigned char)c; + for (size_t i = 0; i < n; ++i) + if (srcp[i] == c8) + return &srcp[i]; + + return NULL; +} diff --git a/compiler-rt/lib/builtins/cpu_model/aarch64.c b/compiler-rt/lib/builtins/cpu_model/aarch64.c index 44e1cf49d1e..17bddfca46f 100644 --- a/compiler-rt/lib/builtins/cpu_model/aarch64.c +++ b/compiler-rt/lib/builtins/cpu_model/aarch64.c @@ -115,6 +115,7 @@ enum CPUFeatures { FEAT_SME_I64, FEAT_SME2, FEAT_RCPC3, + FEAT_MOPS, FEAT_MAX, FEAT_EXT = 62, // Reserved to indicate presence of additional features field // in __aarch64_cpu_features diff --git a/compiler-rt/lib/builtins/cpu_model/aarch64/fmv/apple.inc b/compiler-rt/lib/builtins/cpu_model/aarch64/fmv/apple.inc index 79d4ac70bd1..0bb755f4b30 100644 --- a/compiler-rt/lib/builtins/cpu_model/aarch64/fmv/apple.inc +++ b/compiler-rt/lib/builtins/cpu_model/aarch64/fmv/apple.inc @@ -14,19 +14,17 @@ static bool isKnownAndSupported(const char *name) { void __init_cpu_features_resolver(void) { // On Darwin platforms, this may be called concurrently by multiple threads // because the resolvers that use it are called lazily at runtime (unlike on - // ELF platforms, where IFuncs are resolved serially at load time). This - // function's effect on __aarch64_cpu_features should be idempotent, but even - // so we need dispatch_once to resolve the race condition. Dispatch is - // available through libSystem, which we need anyway for the sysctl, so this - // does not add a new dependency. + // ELF platforms, where IFuncs are resolved serially at load time). This + // function's effect on __aarch64_cpu_features must be idempotent. + + if (!__atomic_load_n(&__aarch64_cpu_features.features, __ATOMIC_RELAXED)) { + uint64_t features = 0; - static dispatch_once_t onceToken = 0; - dispatch_once(&onceToken, ^{ // https://developer.apple.com/documentation/kernel/1387446-sysctlbyname/determining_instruction_set_characteristics - static struct { + static const struct { const char *sysctl_name; enum CPUFeatures feature; - } features[] = { + } feature_checks[] = { {"hw.optional.arm.FEAT_FlagM", FEAT_FLAGM}, {"hw.optional.arm.FEAT_FlagM2", FEAT_FLAGM2}, {"hw.optional.arm.FEAT_FHM", FEAT_FP16FML}, @@ -58,12 +56,16 @@ void __init_cpu_features_resolver(void) { {"hw.optional.arm.FEAT_BTI", FEAT_BTI}, }; - for (size_t I = 0, E = sizeof(features) / sizeof(features[0]); I != E; ++I) - if (isKnownAndSupported(features[I].sysctl_name)) - __aarch64_cpu_features.features |= (1ULL << features[I].feature); + for (size_t I = 0, E = sizeof(feature_checks) / sizeof(feature_checks[0]); + I != E; ++I) + if (isKnownAndSupported(feature_checks[I].sysctl_name)) + features |= (1ULL << feature_checks[I].feature); - __aarch64_cpu_features.features |= (1ULL << FEAT_INIT); - }); + features |= (1ULL << FEAT_INIT); + + __atomic_store(&__aarch64_cpu_features.features, &features, + __ATOMIC_RELAXED); + } } #endif // TARGET_OS_OSX || TARGET_OS_IPHONE diff --git a/compiler-rt/lib/builtins/cpu_model/aarch64/fmv/mrs.inc b/compiler-rt/lib/builtins/cpu_model/aarch64/fmv/mrs.inc index 2f712f41f49..32a21a2fba9 100644 --- a/compiler-rt/lib/builtins/cpu_model/aarch64/fmv/mrs.inc +++ b/compiler-rt/lib/builtins/cpu_model/aarch64/fmv/mrs.inc @@ -109,6 +109,8 @@ static void __init_cpu_features_constructor(unsigned long hwcap, setCPUFeature(FEAT_SME_I64); if (hwcap2 & HWCAP2_SME_F64F64) setCPUFeature(FEAT_SME_F64); + if (hwcap2 & HWCAP2_MOPS) + setCPUFeature(FEAT_MOPS); if (hwcap & HWCAP_CPUID) { unsigned long ftr; getCPUFeature(ID_AA64PFR1_EL1, ftr); diff --git a/compiler-rt/lib/builtins/cpu_model/aarch64/hwcap.inc b/compiler-rt/lib/builtins/cpu_model/aarch64/hwcap.inc index 328d9c4140b..7ddc125b26d 100644 --- a/compiler-rt/lib/builtins/cpu_model/aarch64/hwcap.inc +++ b/compiler-rt/lib/builtins/cpu_model/aarch64/hwcap.inc @@ -178,3 +178,6 @@ #ifndef HWCAP2_SVE_EBF16 #define HWCAP2_SVE_EBF16 (1ULL << 33) #endif +#ifndef HWCAP2_MOPS +#define HWCAP2_MOPS (1ULL << 43) +#endif diff --git a/compiler-rt/lib/builtins/cpu_model/x86.c b/compiler-rt/lib/builtins/cpu_model/x86.c index 9d9a5d3f154..0750e29f989 100644 --- a/compiler-rt/lib/builtins/cpu_model/x86.c +++ b/compiler-rt/lib/builtins/cpu_model/x86.c @@ -148,7 +148,8 @@ enum ProcessorFeatures { FEATURE_LZCNT, FEATURE_MOVBE, - FEATURE_X86_64_BASELINE = 95, + FEATURE_AVX512FP16 = 94, + FEATURE_X86_64_BASELINE, FEATURE_X86_64_V2, FEATURE_X86_64_V3, FEATURE_X86_64_V4, @@ -812,6 +813,8 @@ static void getAvailableFeatures(unsigned ECX, unsigned EDX, unsigned MaxLeaf, setFeature(FEATURE_AVX5124FMAPS); if (HasLeaf7 && ((EDX >> 8) & 1) && HasAVX512Save) setFeature(FEATURE_AVX512VP2INTERSECT); + if (HasLeaf7 && ((EDX >> 23) & 1) && HasAVX512Save) + setFeature(FEATURE_AVX512FP16); // EAX from subleaf 0 is the maximum subleaf supported. Some CPUs don't // return all 0s for invalid subleaves so check the limit. diff --git a/compiler-rt/lib/builtins/fp_extend_impl.inc b/compiler-rt/lib/builtins/fp_extend_impl.inc index e16b55d150d..f4f66306643 100644 --- a/compiler-rt/lib/builtins/fp_extend_impl.inc +++ b/compiler-rt/lib/builtins/fp_extend_impl.inc @@ -60,7 +60,7 @@ static __inline dst_t __extendXfYf2__(src_t a) { dst_rep_t dstExp; dst_rep_t dstSigFrac; - if (srcExp >= 1 && srcExp < srcInfExp) { + if (srcExp >= 1 && srcExp < (src_rep_t)srcInfExp) { // a is a normal number. dstExp = (dst_rep_t)srcExp + (dst_rep_t)(dstExpBias - srcExpBias); dstSigFrac = (dst_rep_t)srcSigFrac << (dstSigFracBits - srcSigFracBits); diff --git a/compiler-rt/lib/builtins/int_lib.h b/compiler-rt/lib/builtins/int_lib.h index 04ea2d91057..f6c1b7cff4b 100644 --- a/compiler-rt/lib/builtins/int_lib.h +++ b/compiler-rt/lib/builtins/int_lib.h @@ -119,14 +119,14 @@ COMPILER_RT_ABI tu_int __udivmodti4(tu_int a, tu_int b, tu_int *rem); #if defined(_MSC_VER) && !defined(__clang__) #include -int __inline __builtin_ctz(uint32_t value) { +static int __inline __builtin_ctz(uint32_t value) { unsigned long trailing_zero = 0; if (_BitScanForward(&trailing_zero, value)) return trailing_zero; return 32; } -int __inline __builtin_clz(uint32_t value) { +static int __inline __builtin_clz(uint32_t value) { unsigned long leading_zero = 0; if (_BitScanReverse(&leading_zero, value)) return 31 - leading_zero; @@ -134,14 +134,14 @@ int __inline __builtin_clz(uint32_t value) { } #if defined(_M_ARM) || defined(_M_X64) -int __inline __builtin_clzll(uint64_t value) { +static int __inline __builtin_clzll(uint64_t value) { unsigned long leading_zero = 0; if (_BitScanReverse64(&leading_zero, value)) return 63 - leading_zero; return 64; } #else -int __inline __builtin_clzll(uint64_t value) { +static int __inline __builtin_clzll(uint64_t value) { if (value == 0) return 64; uint32_t msh = (uint32_t)(value >> 32); @@ -154,7 +154,7 @@ int __inline __builtin_clzll(uint64_t value) { #define __builtin_clzl __builtin_clzll -bool __inline __builtin_sadd_overflow(int x, int y, int *result) { +static bool __inline __builtin_sadd_overflow(int x, int y, int *result) { if ((x < 0) != (y < 0)) { *result = x + y; return false; diff --git a/compiler-rt/lib/dfsan/dfsan_custom.cpp b/compiler-rt/lib/dfsan/dfsan_custom.cpp index 05b48fd0525..85b796bd634 100644 --- a/compiler-rt/lib/dfsan/dfsan_custom.cpp +++ b/compiler-rt/lib/dfsan/dfsan_custom.cpp @@ -842,7 +842,7 @@ __dfsw_dlopen(const char *filename, int flag, dfsan_label filename_label, dfsan_label flag_label, dfsan_label *ret_label) { void *handle = dlopen(filename, flag); link_map *map = GET_LINK_MAP_BY_DLOPEN_HANDLE(handle); - if (map) + if (filename && map) ForEachMappedRegion(map, dfsan_set_zero_label); *ret_label = 0; return handle; @@ -2792,7 +2792,7 @@ int __dfsw_sprintf(char *str, const char *format, dfsan_label str_label, va_list ap; va_start(ap, ret_label); - int ret = format_buffer(str, ~0ul, format, va_labels, ret_label, nullptr, + int ret = format_buffer(str, INT32_MAX, format, va_labels, ret_label, nullptr, nullptr, ap); va_end(ap); return ret; @@ -2806,8 +2806,8 @@ int __dfso_sprintf(char *str, const char *format, dfsan_label str_label, dfsan_origin *ret_origin, ...) { va_list ap; va_start(ap, ret_origin); - int ret = format_buffer(str, ~0ul, format, va_labels, ret_label, va_origins, - ret_origin, ap); + int ret = format_buffer(str, INT32_MAX, format, va_labels, ret_label, + va_origins, ret_origin, ap); va_end(ap); return ret; } diff --git a/compiler-rt/lib/hwasan/hwasan_report.cpp b/compiler-rt/lib/hwasan/hwasan_report.cpp index 784cfb904aa..12a4fa47f21 100644 --- a/compiler-rt/lib/hwasan/hwasan_report.cpp +++ b/compiler-rt/lib/hwasan/hwasan_report.cpp @@ -222,7 +222,7 @@ static void PrintStackAllocations(const StackAllocationsRingBuffer *sa, if (!local.has_frame_offset || !local.has_size || !local.has_tag_offset) continue; if (!(local.name && internal_strlen(local.name)) && - !(local.function_name && internal_strlen(local.name)) && + !(local.function_name && internal_strlen(local.function_name)) && !(local.decl_file && internal_strlen(local.decl_file))) continue; tag_t obj_tag = base_tag ^ local.tag_offset; diff --git a/compiler-rt/lib/interception/interception.h b/compiler-rt/lib/interception/interception.h index 9d8b60b2eef..58e969378a9 100644 --- a/compiler-rt/lib/interception/interception.h +++ b/compiler-rt/lib/interception/interception.h @@ -205,8 +205,9 @@ const interpose_substitution substitution_##func_name[] \ ASM_TYPE_FUNCTION_STR "\n" \ SANITIZER_STRINGIFY(TRAMPOLINE(func)) ":\n" \ SANITIZER_STRINGIFY(CFI_STARTPROC) "\n" \ - SANITIZER_STRINGIFY(ASM_TAIL_CALL) " __interceptor_" \ - SANITIZER_STRINGIFY(ASM_PREEMPTIBLE_SYM(func)) "\n" \ + C_ASM_TAIL_CALL(SANITIZER_STRINGIFY(TRAMPOLINE(func)), \ + "__interceptor_" \ + SANITIZER_STRINGIFY(ASM_PREEMPTIBLE_SYM(func))) "\n" \ SANITIZER_STRINGIFY(CFI_ENDPROC) "\n" \ ".size " SANITIZER_STRINGIFY(TRAMPOLINE(func)) ", " \ ".-" SANITIZER_STRINGIFY(TRAMPOLINE(func)) "\n" \ diff --git a/compiler-rt/lib/interception/interception_win.cpp b/compiler-rt/lib/interception/interception_win.cpp index f1a549b938e..1829358705f 100644 --- a/compiler-rt/lib/interception/interception_win.cpp +++ b/compiler-rt/lib/interception/interception_win.cpp @@ -945,19 +945,26 @@ bool OverrideFunction( static void **InterestingDLLsAvailable() { static const char *InterestingDLLs[] = { - "kernel32.dll", - "msvcr100.dll", // VS2010 - "msvcr110.dll", // VS2012 - "msvcr120.dll", // VS2013 - "vcruntime140.dll", // VS2015 - "ucrtbase.dll", // Universal CRT -#if (defined(__MINGW32__) && defined(__i386__)) - "libc++.dll", // libc++ - "libunwind.dll", // libunwind -#endif - // NTDLL should go last as it exports some functions that we should - // override in the CRT [presumably only used internally]. - "ntdll.dll", NULL}; + "kernel32.dll", + "msvcr100d.dll", // VS2010 + "msvcr110d.dll", // VS2012 + "msvcr120d.dll", // VS2013 + "vcruntime140d.dll", // VS2015 + "ucrtbased.dll", // Universal CRT + "msvcr100.dll", // VS2010 + "msvcr110.dll", // VS2012 + "msvcr120.dll", // VS2013 + "vcruntime140.dll", // VS2015 + "ucrtbase.dll", // Universal CRT +# if (defined(__MINGW32__) && defined(__i386__)) + "libc++.dll", // libc++ + "libunwind.dll", // libunwind +# endif + // NTDLL should go last as it exports some functions that we should + // override in the CRT [presumably only used internally]. + "ntdll.dll", + NULL + }; static void *result[ARRAY_SIZE(InterestingDLLs)] = { 0 }; if (!result[0]) { for (size_t i = 0, j = 0; InterestingDLLs[i]; ++i) { diff --git a/compiler-rt/lib/orc/coff_platform.cpp b/compiler-rt/lib/orc/coff_platform.cpp index 78c86c855dc..9fe5c0b0628 100644 --- a/compiler-rt/lib/orc/coff_platform.cpp +++ b/compiler-rt/lib/orc/coff_platform.cpp @@ -509,7 +509,6 @@ Error COFFPlatformRuntimeState::deregisterObjectSections( << HeaderAddr.getValue(); return make_error(ErrStream.str()); } - auto &JDState = I->second; for (auto &KV : Secs) { if (auto Err = deregisterBlockRange(HeaderAddr, KV.second)) return Err; @@ -687,7 +686,14 @@ struct ThrowInfo { ORC_RT_INTERFACE void __stdcall __orc_rt_coff_cxx_throw_exception( void *pExceptionObject, ThrowInfo *pThrowInfo) { +#ifdef __clang__ +#pragma clang diagnostic push +#pragma clang diagnostic ignored "-Wmultichar" +#endif constexpr uint32_t EH_EXCEPTION_NUMBER = 'msc' | 0xE0000000; +#ifdef __clang__ +#pragma clang diagnostic pop +#endif constexpr uint32_t EH_MAGIC_NUMBER1 = 0x19930520; auto BaseAddr = COFFPlatformRuntimeState::get().findJITDylibBaseByPC( reinterpret_cast(pThrowInfo)); diff --git a/compiler-rt/lib/orc/wrapper_function_utils.h b/compiler-rt/lib/orc/wrapper_function_utils.h index dcb6d0e6add..8009438547a 100644 --- a/compiler-rt/lib/orc/wrapper_function_utils.h +++ b/compiler-rt/lib/orc/wrapper_function_utils.h @@ -296,11 +296,15 @@ public: // operation fails. detail::ResultDeserializer::makeSafe(Result); + // Since the functions cannot be zero/unresolved on Windows, the following + // reference taking would always be non-zero, thus generating a compiler + // warning otherwise. +#if !defined(_WIN32) if (ORC_RT_UNLIKELY(!&__orc_rt_jit_dispatch_ctx)) return make_error("__orc_rt_jit_dispatch_ctx not set"); if (ORC_RT_UNLIKELY(!&__orc_rt_jit_dispatch)) return make_error("__orc_rt_jit_dispatch not set"); - +#endif auto ArgBuffer = WrapperFunctionResult::fromSPSArgs>(Args...); if (const char *ErrMsg = ArgBuffer.getOutOfBandError()) diff --git a/compiler-rt/lib/profile/InstrProfiling.h b/compiler-rt/lib/profile/InstrProfiling.h index 13711599674..01239083369 100644 --- a/compiler-rt/lib/profile/InstrProfiling.h +++ b/compiler-rt/lib/profile/InstrProfiling.h @@ -12,6 +12,17 @@ #include "InstrProfilingPort.h" #include +// Make sure __LLVM_INSTR_PROFILE_GENERATE is always defined before +// including instr_prof_interface.h so the interface functions are +// declared correctly for the runtime. +// __LLVM_INSTR_PROFILE_GENERATE is always `#undef`ed after the header, +// because compiler-rt does not support profiling the profiling runtime itself. +#ifndef __LLVM_INSTR_PROFILE_GENERATE +#define __LLVM_INSTR_PROFILE_GENERATE +#endif +#include "profile/instr_prof_interface.h" +#undef __LLVM_INSTR_PROFILE_GENERATE + #define INSTR_PROF_VISIBILITY COMPILER_RT_VISIBILITY #include "profile/InstrProfData.inc" @@ -100,12 +111,6 @@ ValueProfNode *__llvm_profile_begin_vnodes(); ValueProfNode *__llvm_profile_end_vnodes(); uint32_t *__llvm_profile_begin_orderfile(); -/*! - * \brief Clear profile counters to zero. - * - */ -void __llvm_profile_reset_counters(void); - /*! * \brief Merge profile data from buffer. * @@ -156,50 +161,6 @@ void __llvm_profile_instrument_target_value(uint64_t TargetValue, void *Data, int __llvm_profile_write_file(void); int __llvm_orderfile_write_file(void); -/*! - * \brief this is a wrapper interface to \c __llvm_profile_write_file. - * After this interface is invoked, an already dumped flag will be set - * so that profile won't be dumped again during program exit. - * Invocation of interface __llvm_profile_reset_counters will clear - * the flag. This interface is designed to be used to collect profile - * data from user selected hot regions. The use model is - * __llvm_profile_reset_counters(); - * ... hot region 1 - * __llvm_profile_dump(); - * .. some other code - * __llvm_profile_reset_counters(); - * ... hot region 2 - * __llvm_profile_dump(); - * - * It is expected that on-line profile merging is on with \c %m specifier - * used in profile filename . If merging is not turned on, user is expected - * to invoke __llvm_profile_set_filename to specify different profile names - * for different regions before dumping to avoid profile write clobbering. - */ -int __llvm_profile_dump(void); - -int __llvm_orderfile_dump(void); - -/*! - * \brief Set the filename for writing instrumentation data. - * - * Sets the filename to be used for subsequent calls to - * \a __llvm_profile_write_file(). - * - * \c Name is not copied, so it must remain valid. Passing NULL resets the - * filename logic to the default behaviour. - * - * Note: There may be multiple copies of the profile runtime (one for each - * instrumented image/DSO). This API only modifies the filename within the - * copy of the runtime available to the calling image. - * - * Warning: This is a no-op if continuous mode (\ref - * __llvm_profile_is_continuous_mode_enabled) is on. The reason for this is - * that in continuous mode, profile counters are mmap()'d to the profile at - * program initialization time. Support for transferring the mmap'd profile - * counts to a new file has not been implemented. - */ -void __llvm_profile_set_filename(const char *Name); /*! * \brief Set the FILE object for writing instrumentation data. Return 0 if set diff --git a/compiler-rt/lib/profile/InstrProfilingFile.c b/compiler-rt/lib/profile/InstrProfilingFile.c index 745c567f216..867ae73f0d3 100644 --- a/compiler-rt/lib/profile/InstrProfilingFile.c +++ b/compiler-rt/lib/profile/InstrProfilingFile.c @@ -335,10 +335,10 @@ static void initFileWriter(ProfDataWriter *This, FILE *File) { COMPILER_RT_VISIBILITY ProfBufferIO * lprofCreateBufferIOInternal(void *File, uint32_t BufferSz) { FreeHook = &free; - DynamicBufferIOBuffer = (uint8_t *)calloc(BufferSz, 1); + DynamicBufferIOBuffer = (uint8_t *)calloc(1, BufferSz); VPBufferSize = BufferSz; ProfDataWriter *fileWriter = - (ProfDataWriter *)calloc(sizeof(ProfDataWriter), 1); + (ProfDataWriter *)calloc(1, sizeof(ProfDataWriter)); initFileWriter(fileWriter, File); ProfBufferIO *IO = lprofCreateBufferIO(fileWriter); IO->OwnFileWriter = 1; @@ -702,10 +702,15 @@ static void resetFilenameToDefault(void) { #ifdef __GNUC__ #pragma GCC diagnostic push #pragma GCC diagnostic ignored "-Wcast-qual" +#elif defined(__clang__) +#pragma clang diagnostic push +#pragma clang diagnostic ignored "-Wcast-qual" #endif free((void *)lprofCurFilename.FilenamePat); #ifdef __GNUC__ #pragma GCC diagnostic pop +#elif defined(__clang__) +#pragma clang diagnostic pop #endif } memset(&lprofCurFilename, 0, sizeof(lprofCurFilename)); @@ -751,6 +756,9 @@ static int parseFilenamePattern(const char *FilenamePat, #ifdef __GNUC__ #pragma GCC diagnostic push #pragma GCC diagnostic ignored "-Wcast-qual" +#elif defined(__clang__) +#pragma clang diagnostic push +#pragma clang diagnostic ignored "-Wcast-qual" #endif /* Clean up cached prefix and filename. */ if (lprofCurFilename.ProfilePathPrefix) @@ -761,6 +769,8 @@ static int parseFilenamePattern(const char *FilenamePat, } #ifdef __GNUC__ #pragma GCC diagnostic pop +#elif defined(__clang__) +#pragma clang diagnostic pop #endif memset(&lprofCurFilename, 0, sizeof(lprofCurFilename)); diff --git a/compiler-rt/lib/profile/InstrProfilingMerge.c b/compiler-rt/lib/profile/InstrProfilingMerge.c index e8ae2189ccc..b5850e99ee3 100644 --- a/compiler-rt/lib/profile/InstrProfilingMerge.c +++ b/compiler-rt/lib/profile/InstrProfilingMerge.c @@ -41,6 +41,9 @@ uint64_t lprofGetLoadModuleSignature(void) { #ifdef __GNUC__ #pragma GCC diagnostic push #pragma GCC diagnostic ignored "-Wcast-qual" +#elif defined(__clang__) +#pragma clang diagnostic push +#pragma clang diagnostic ignored "-Wcast-qual" #endif /* Returns 1 if profile is not structurally compatible. */ @@ -234,4 +237,6 @@ int __llvm_profile_merge_from_buffer(const char *ProfileData, #ifdef __GNUC__ #pragma GCC diagnostic pop +#elif defined(__clang__) +#pragma clang diagnostic pop #endif diff --git a/compiler-rt/lib/profile/InstrProfilingValue.c b/compiler-rt/lib/profile/InstrProfilingValue.c index 3d7c245f795..a608d41d39e 100644 --- a/compiler-rt/lib/profile/InstrProfilingValue.c +++ b/compiler-rt/lib/profile/InstrProfilingValue.c @@ -62,10 +62,15 @@ __llvm_profile_set_num_value_sites(__llvm_profile_data *Data, #ifdef __GNUC__ #pragma GCC diagnostic push #pragma GCC diagnostic ignored "-Wcast-qual" +#elif defined(__clang__) +#pragma clang diagnostic push +#pragma clang diagnostic ignored "-Wcast-qual" #endif *((uint16_t *)&Data->NumValueSites[ValueKind]) = NumValueSites; #ifdef __GNUC__ #pragma GCC diagnostic pop +#elif defined(__clang__) +#pragma clang diagnostic pop #endif } diff --git a/compiler-rt/lib/profile/WindowsMMap.c b/compiler-rt/lib/profile/WindowsMMap.c index 07c0a689fea..9d7da835b1e 100644 --- a/compiler-rt/lib/profile/WindowsMMap.c +++ b/compiler-rt/lib/profile/WindowsMMap.c @@ -124,8 +124,7 @@ int madvise(void *addr, size_t length, int advice) return 0; } -COMPILER_RT_VISIBILITY -int lock(HANDLE handle, DWORD lockType, BOOL blocking) { +static int lock(HANDLE handle, DWORD lockType, BOOL blocking) { DWORD flags = lockType; if (!blocking) flags |= LOCKFILE_FAIL_IMMEDIATELY; diff --git a/compiler-rt/lib/profile/WindowsMMap.h b/compiler-rt/lib/profile/WindowsMMap.h index 68b8de2398d..1df1a0be0b0 100644 --- a/compiler-rt/lib/profile/WindowsMMap.h +++ b/compiler-rt/lib/profile/WindowsMMap.h @@ -60,6 +60,12 @@ # define DWORD_LO(x) (x) #endif +#define mmap __llvm_profile_mmap +#define munmap __llvm_profile_munmap +#define msync __llvm_profile_msync +#define madvise __llvm_profile_madvise +#define flock __llvm_profile_flock + void *mmap(void *start, size_t length, int prot, int flags, int fd, off_t offset); diff --git a/compiler-rt/lib/sanitizer_common/sanitizer_asm.h b/compiler-rt/lib/sanitizer_common/sanitizer_asm.h index bbb18cfbdf1..3af66a4e449 100644 --- a/compiler-rt/lib/sanitizer_common/sanitizer_asm.h +++ b/compiler-rt/lib/sanitizer_common/sanitizer_asm.h @@ -53,6 +53,29 @@ # define ASM_TAIL_CALL tail #endif +// Currently, almost all of the shared libraries rely on the value of +// $t9 to get the address of current function, instead of PCREL, even +// on MIPSr6. To be compatiable with them, we have to set $t9 properly. +// MIPS uses GOT to get the address of preemptible functions. +#if defined(__mips64) +# define C_ASM_TAIL_CALL(t_func, i_func) \ + "lui $t8, %hi(%neg(%gp_rel(" t_func ")))\n" \ + "daddu $t8, $t8, $t9\n" \ + "daddiu $t8, $t8, %lo(%neg(%gp_rel(" t_func ")))\n" \ + "ld $t9, %got_disp(" i_func ")($t8)\n" \ + "jr $t9\n" +#elif defined(__mips__) +# define C_ASM_TAIL_CALL(t_func, i_func) \ + ".set noreorder\n" \ + ".cpload $t9\n" \ + ".set reorder\n" \ + "lw $t9, %got(" i_func ")($gp)\n" \ + "jr $t9\n" +#elif defined(ASM_TAIL_CALL) +# define C_ASM_TAIL_CALL(t_func, i_func) \ + SANITIZER_STRINGIFY(ASM_TAIL_CALL) " " i_func +#endif + #if defined(__ELF__) && defined(__x86_64__) || defined(__i386__) || \ defined(__riscv) # define ASM_PREEMPTIBLE_SYM(sym) sym@plt diff --git a/compiler-rt/lib/sanitizer_common/sanitizer_common_interceptors.inc b/compiler-rt/lib/sanitizer_common/sanitizer_common_interceptors.inc index 77fa1b4965a..1b56bebac64 100644 --- a/compiler-rt/lib/sanitizer_common/sanitizer_common_interceptors.inc +++ b/compiler-rt/lib/sanitizer_common/sanitizer_common_interceptors.inc @@ -9965,7 +9965,13 @@ INTERCEPTOR(void, sl_free, void *sl, int freeall) { INTERCEPTOR(SSIZE_T, getrandom, void *buf, SIZE_T buflen, unsigned int flags) { void *ctx; COMMON_INTERCEPTOR_ENTER(ctx, getrandom, buf, buflen, flags); - SSIZE_T n = REAL(getrandom)(buf, buflen, flags); + // If GRND_NONBLOCK is set in the flags, it is non blocking. + static const int grnd_nonblock = 1; + SSIZE_T n; + if ((flags & grnd_nonblock)) + n = REAL(getrandom)(buf, buflen, flags); + else + n = COMMON_INTERCEPTOR_BLOCK_REAL(getrandom)(buf, buflen, flags); if (n > 0) { COMMON_INTERCEPTOR_WRITE_RANGE(ctx, buf, n); } diff --git a/compiler-rt/lib/sanitizer_common/sanitizer_fuchsia.cpp b/compiler-rt/lib/sanitizer_common/sanitizer_fuchsia.cpp index 0245164403c..5f4f8c8c007 100644 --- a/compiler-rt/lib/sanitizer_common/sanitizer_fuchsia.cpp +++ b/compiler-rt/lib/sanitizer_common/sanitizer_fuchsia.cpp @@ -129,6 +129,60 @@ uptr GetMaxVirtualAddress() { return GetMaxUserVirtualAddress(); } bool ErrorIsOOM(error_t err) { return err == ZX_ERR_NO_MEMORY; } +// For any sanitizer internal that needs to map something which can be unmapped +// later, first attempt to map to a pre-allocated VMAR. This helps reduce +// fragmentation from many small anonymous mmap calls. A good value for this +// VMAR size would be the total size of your typical sanitizer internal objects +// allocated in an "average" process lifetime. Examples of this include: +// FakeStack, LowLevelAllocator mappings, TwoLevelMap, InternalMmapVector, +// StackStore, CreateAsanThread, etc. +// +// This is roughly equal to the total sum of sanitizer internal mappings for a +// large test case. +constexpr size_t kSanitizerHeapVmarSize = 13ULL << 20; +static zx_handle_t gSanitizerHeapVmar = ZX_HANDLE_INVALID; + +static zx_status_t GetSanitizerHeapVmar(zx_handle_t *vmar) { + zx_status_t status = ZX_OK; + if (gSanitizerHeapVmar == ZX_HANDLE_INVALID) { + CHECK_EQ(kSanitizerHeapVmarSize % GetPageSizeCached(), 0); + uintptr_t base; + status = _zx_vmar_allocate( + _zx_vmar_root_self(), + ZX_VM_CAN_MAP_READ | ZX_VM_CAN_MAP_WRITE | ZX_VM_CAN_MAP_SPECIFIC, 0, + kSanitizerHeapVmarSize, &gSanitizerHeapVmar, &base); + } + *vmar = gSanitizerHeapVmar; + if (status == ZX_OK) + CHECK_NE(gSanitizerHeapVmar, ZX_HANDLE_INVALID); + return status; +} + +static zx_status_t TryVmoMapSanitizerVmar(zx_vm_option_t options, + size_t vmar_offset, zx_handle_t vmo, + size_t size, uintptr_t *addr, + zx_handle_t *vmar_used = nullptr) { + zx_handle_t vmar; + zx_status_t status = GetSanitizerHeapVmar(&vmar); + if (status != ZX_OK) + return status; + + status = _zx_vmar_map(gSanitizerHeapVmar, options, vmar_offset, vmo, + /*vmo_offset=*/0, size, addr); + if (vmar_used) + *vmar_used = gSanitizerHeapVmar; + if (status == ZX_ERR_NO_RESOURCES || status == ZX_ERR_INVALID_ARGS) { + // This means there's no space in the heap VMAR, so fallback to the root + // VMAR. + status = _zx_vmar_map(_zx_vmar_root_self(), options, vmar_offset, vmo, + /*vmo_offset=*/0, size, addr); + if (vmar_used) + *vmar_used = _zx_vmar_root_self(); + } + + return status; +} + static void *DoAnonymousMmapOrDie(uptr size, const char *mem_type, bool raw_report, bool die_for_nomem) { size = RoundUpTo(size, GetPageSize()); @@ -144,11 +198,9 @@ static void *DoAnonymousMmapOrDie(uptr size, const char *mem_type, _zx_object_set_property(vmo, ZX_PROP_NAME, mem_type, internal_strlen(mem_type)); - // TODO(mcgrathr): Maybe allocate a VMAR for all sanitizer heap and use that? uintptr_t addr; - status = - _zx_vmar_map(_zx_vmar_root_self(), ZX_VM_PERM_READ | ZX_VM_PERM_WRITE, 0, - vmo, 0, size, &addr); + status = TryVmoMapSanitizerVmar(ZX_VM_PERM_READ | ZX_VM_PERM_WRITE, + /*vmar_offset=*/0, vmo, size, &addr); _zx_handle_close(vmo); if (status != ZX_OK) { @@ -243,6 +295,12 @@ void UnmapOrDieVmar(void *addr, uptr size, zx_handle_t target_vmar) { zx_status_t status = _zx_vmar_unmap(target_vmar, reinterpret_cast(addr), size); + if (status == ZX_ERR_INVALID_ARGS && target_vmar == gSanitizerHeapVmar) { + // If there wasn't any space in the heap vmar, the fallback was the root + // vmar. + status = _zx_vmar_unmap(_zx_vmar_root_self(), + reinterpret_cast(addr), size); + } if (status != ZX_OK) { Report("ERROR: %s failed to deallocate 0x%zx (%zd) bytes at address %p\n", SanitizerToolName, size, size, addr); @@ -308,17 +366,16 @@ void *MmapAlignedOrDieOnFatalError(uptr size, uptr alignment, _zx_object_set_property(vmo, ZX_PROP_NAME, mem_type, internal_strlen(mem_type)); - // TODO(mcgrathr): Maybe allocate a VMAR for all sanitizer heap and use that? - // Map a larger size to get a chunk of address space big enough that // it surely contains an aligned region of the requested size. Then // overwrite the aligned middle portion with a mapping from the // beginning of the VMO, and unmap the excess before and after. size_t map_size = size + alignment; uintptr_t addr; - status = - _zx_vmar_map(_zx_vmar_root_self(), ZX_VM_PERM_READ | ZX_VM_PERM_WRITE, 0, - vmo, 0, map_size, &addr); + zx_handle_t vmar_used; + status = TryVmoMapSanitizerVmar(ZX_VM_PERM_READ | ZX_VM_PERM_WRITE, + /*vmar_offset=*/0, vmo, map_size, &addr, + &vmar_used); if (status == ZX_OK) { uintptr_t map_addr = addr; uintptr_t map_end = map_addr + map_size; @@ -326,12 +383,12 @@ void *MmapAlignedOrDieOnFatalError(uptr size, uptr alignment, uintptr_t end = addr + size; if (addr != map_addr) { zx_info_vmar_t info; - status = _zx_object_get_info(_zx_vmar_root_self(), ZX_INFO_VMAR, &info, - sizeof(info), NULL, NULL); + status = _zx_object_get_info(vmar_used, ZX_INFO_VMAR, &info, sizeof(info), + NULL, NULL); if (status == ZX_OK) { uintptr_t new_addr; status = _zx_vmar_map( - _zx_vmar_root_self(), + vmar_used, ZX_VM_PERM_READ | ZX_VM_PERM_WRITE | ZX_VM_SPECIFIC_OVERWRITE, addr - info.base, vmo, 0, size, &new_addr); if (status == ZX_OK) @@ -339,9 +396,9 @@ void *MmapAlignedOrDieOnFatalError(uptr size, uptr alignment, } } if (status == ZX_OK && addr != map_addr) - status = _zx_vmar_unmap(_zx_vmar_root_self(), map_addr, addr - map_addr); + status = _zx_vmar_unmap(vmar_used, map_addr, addr - map_addr); if (status == ZX_OK && end != map_end) - status = _zx_vmar_unmap(_zx_vmar_root_self(), end, map_end - end); + status = _zx_vmar_unmap(vmar_used, end, map_end - end); } _zx_handle_close(vmo); @@ -357,7 +414,7 @@ void *MmapAlignedOrDieOnFatalError(uptr size, uptr alignment, } void UnmapOrDie(void *addr, uptr size) { - UnmapOrDieVmar(addr, size, _zx_vmar_root_self()); + UnmapOrDieVmar(addr, size, gSanitizerHeapVmar); } void ReleaseMemoryPagesToOS(uptr beg, uptr end) { diff --git a/compiler-rt/lib/sanitizer_common/sanitizer_internal_defs.h b/compiler-rt/lib/sanitizer_common/sanitizer_internal_defs.h index 3809669dd48..992721757e8 100644 --- a/compiler-rt/lib/sanitizer_common/sanitizer_internal_defs.h +++ b/compiler-rt/lib/sanitizer_common/sanitizer_internal_defs.h @@ -35,13 +35,20 @@ # define SANITIZER_INTERFACE_ATTRIBUTE __declspec(dllexport) #endif # define SANITIZER_WEAK_ATTRIBUTE +# define SANITIZER_WEAK_IMPORT #elif SANITIZER_GO # define SANITIZER_INTERFACE_ATTRIBUTE # define SANITIZER_WEAK_ATTRIBUTE +# define SANITIZER_WEAK_IMPORT #else # define SANITIZER_INTERFACE_ATTRIBUTE __attribute__((visibility("default"))) # define SANITIZER_WEAK_ATTRIBUTE __attribute__((weak)) -#endif +# if SANITIZER_APPLE +# define SANITIZER_WEAK_IMPORT extern "C" __attribute((weak_import)) +# else +# define SANITIZER_WEAK_IMPORT extern "C" SANITIZER_WEAK_ATTRIBUTE +# endif // SANITIZER_APPLE +#endif // SANITIZER_WINDOWS //--------------------------- WEAK FUNCTIONS ---------------------------------// // When working with weak functions, to simplify the code and make it more diff --git a/compiler-rt/lib/sanitizer_common/sanitizer_symbolizer_report.cpp b/compiler-rt/lib/sanitizer_common/sanitizer_symbolizer_report.cpp index 253dc10607a..8438e019591 100644 --- a/compiler-rt/lib/sanitizer_common/sanitizer_symbolizer_report.cpp +++ b/compiler-rt/lib/sanitizer_common/sanitizer_symbolizer_report.cpp @@ -34,7 +34,8 @@ static bool FrameIsInternal(const SymbolizedStack *frame) { return true; const char *file = frame->info.file; const char *module = frame->info.module; - if (file && (internal_strstr(file, "/compiler-rt/lib/"))) + if (file && (internal_strstr(file, "/compiler-rt/lib/") || + internal_strstr(file, "/include/c++/"))) return true; if (module && (internal_strstr(module, "libclang_rt."))) return true; diff --git a/compiler-rt/lib/sanitizer_common/symbolizer/scripts/build_symbolizer.sh b/compiler-rt/lib/sanitizer_common/symbolizer/scripts/build_symbolizer.sh index c9e31be61cb..f24d42cc84e 100755 --- a/compiler-rt/lib/sanitizer_common/symbolizer/scripts/build_symbolizer.sh +++ b/compiler-rt/lib/sanitizer_common/symbolizer/scripts/build_symbolizer.sh @@ -104,6 +104,7 @@ if [[ ! -f ${LLVM_BUILD}/build.ninja ]]; then -DCMAKE_CXX_FLAGS_RELEASE="${LIBCXX_FLAGS}" \ -DLIBCXXABI_ENABLE_ASSERTIONS=OFF \ -DLIBCXXABI_ENABLE_EXCEPTIONS=OFF \ + -DLIBCXXABI_USE_LLVM_UNWINDER=OFF \ -DLIBCXX_ENABLE_ASSERTIONS=OFF \ -DLIBCXX_ENABLE_EXCEPTIONS=OFF \ -DLIBCXX_ENABLE_RTTI=OFF \ diff --git a/compiler-rt/lib/tsan/rtl/tsan_dispatch_defs.h b/compiler-rt/lib/tsan/rtl/tsan_dispatch_defs.h index 54c0b0ba4b4..8d38beb0b0a 100644 --- a/compiler-rt/lib/tsan/rtl/tsan_dispatch_defs.h +++ b/compiler-rt/lib/tsan/rtl/tsan_dispatch_defs.h @@ -56,13 +56,6 @@ extern const dispatch_block_t _dispatch_data_destructor_munmap; # define DISPATCH_NOESCAPE #endif -#if SANITIZER_APPLE -# define SANITIZER_WEAK_IMPORT extern "C" __attribute((weak_import)) -#else -# define SANITIZER_WEAK_IMPORT extern "C" __attribute((weak)) -#endif - - // Data types used in dispatch APIs typedef unsigned long size_t; typedef unsigned long uintptr_t; diff --git a/compiler-rt/lib/tsan/rtl/tsan_platform.h b/compiler-rt/lib/tsan/rtl/tsan_platform.h index 84ff4bfade0..377f8aeb8d6 100644 --- a/compiler-rt/lib/tsan/rtl/tsan_platform.h +++ b/compiler-rt/lib/tsan/rtl/tsan_platform.h @@ -1024,7 +1024,7 @@ inline uptr RestoreAddr(uptr addr) { void InitializePlatform(); void InitializePlatformEarly(); -void CheckAndProtect(); +bool CheckAndProtect(bool protect, bool ignore_heap, bool print_warnings); void InitializeShadowMemoryPlatform(); void WriteMemoryProfile(char *buf, uptr buf_size, u64 uptime_ns); int ExtractResolvFDs(void *state, int *fds, int nfd); diff --git a/compiler-rt/lib/tsan/rtl/tsan_platform_linux.cpp b/compiler-rt/lib/tsan/rtl/tsan_platform_linux.cpp index b45adea45b2..0d0b1aba1f8 100644 --- a/compiler-rt/lib/tsan/rtl/tsan_platform_linux.cpp +++ b/compiler-rt/lib/tsan/rtl/tsan_platform_linux.cpp @@ -214,6 +214,88 @@ void InitializeShadowMemoryPlatform() { #endif // #if !SANITIZER_GO +# if !SANITIZER_GO +static void ReExecIfNeeded() { + // Go maps shadow memory lazily and works fine with limited address space. + // Unlimited stack is not a problem as well, because the executable + // is not compiled with -pie. + bool reexec = false; + // TSan doesn't play well with unlimited stack size (as stack + // overlaps with shadow memory). If we detect unlimited stack size, + // we re-exec the program with limited stack size as a best effort. + if (StackSizeIsUnlimited()) { + const uptr kMaxStackSize = 32 * 1024 * 1024; + VReport(1, + "Program is run with unlimited stack size, which wouldn't " + "work with ThreadSanitizer.\n" + "Re-execing with stack size limited to %zd bytes.\n", + kMaxStackSize); + SetStackSizeLimitInBytes(kMaxStackSize); + reexec = true; + } + + if (!AddressSpaceIsUnlimited()) { + Report( + "WARNING: Program is run with limited virtual address space," + " which wouldn't work with ThreadSanitizer.\n"); + Report("Re-execing with unlimited virtual address space.\n"); + SetAddressSpaceUnlimited(); + reexec = true; + } + +# if SANITIZER_LINUX + // ASLR personality check. + int old_personality = personality(0xffffffff); + bool aslr_on = + (old_personality != -1) && ((old_personality & ADDR_NO_RANDOMIZE) == 0); + +# if SANITIZER_ANDROID && (defined(__aarch64__) || defined(__x86_64__)) + // After patch "arm64: mm: support ARCH_MMAP_RND_BITS." is introduced in + // linux kernel, the random gap between stack and mapped area is increased + // from 128M to 36G on 39-bit aarch64. As it is almost impossible to cover + // this big range, we should disable randomized virtual space on aarch64. + if (aslr_on) { + VReport(1, + "WARNING: Program is run with randomized virtual address " + "space, which wouldn't work with ThreadSanitizer on Android.\n" + "Re-execing with fixed virtual address space.\n"); + CHECK_NE(personality(old_personality | ADDR_NO_RANDOMIZE), -1); + reexec = true; + } +# endif + + if (reexec) { + // Don't check the address space since we're going to re-exec anyway. + } else if (!CheckAndProtect(false, false, false)) { + if (aslr_on) { + // Disable ASLR if the memory layout was incompatible. + // Alternatively, we could just keep re-execing until we get lucky + // with a compatible randomized layout, but the risk is that if it's + // not an ASLR-related issue, we will be stuck in an infinite loop of + // re-execing (unless we change ReExec to pass a parameter of the + // number of retries allowed.) + VReport(1, + "WARNING: ThreadSanitizer: memory layout is incompatible, " + "possibly due to high-entropy ASLR.\n" + "Re-execing with fixed virtual address space.\n" + "N.B. reducing ASLR entropy is preferable.\n"); + CHECK_NE(personality(old_personality | ADDR_NO_RANDOMIZE), -1); + reexec = true; + } else { + VReport(1, + "FATAL: ThreadSanitizer: memory layout is incompatible, " + "even though ASLR is disabled.\n" + "Please file a bug.\n"); + Die(); + } + } +# endif // SANITIZER_LINUX + + if (reexec) + ReExec(); +} +# endif + void InitializePlatformEarly() { vmaSize = (MostSignificantSetBitIndex(GET_CURRENT_FRAME()) + 1); @@ -284,6 +366,10 @@ void InitializePlatformEarly() { } # endif # endif + +# if !SANITIZER_GO + ReExecIfNeeded(); +# endif } void InitializePlatform() { @@ -294,52 +380,22 @@ void InitializePlatform() { // is not compiled with -pie. #if !SANITIZER_GO { - bool reexec = false; - // TSan doesn't play well with unlimited stack size (as stack - // overlaps with shadow memory). If we detect unlimited stack size, - // we re-exec the program with limited stack size as a best effort. - if (StackSizeIsUnlimited()) { - const uptr kMaxStackSize = 32 * 1024 * 1024; - VReport(1, "Program is run with unlimited stack size, which wouldn't " - "work with ThreadSanitizer.\n" - "Re-execing with stack size limited to %zd bytes.\n", - kMaxStackSize); - SetStackSizeLimitInBytes(kMaxStackSize); - reexec = true; - } - - if (!AddressSpaceIsUnlimited()) { - Report("WARNING: Program is run with limited virtual address space," - " which wouldn't work with ThreadSanitizer.\n"); - Report("Re-execing with unlimited virtual address space.\n"); - SetAddressSpaceUnlimited(); - reexec = true; - } -#if SANITIZER_ANDROID && (defined(__aarch64__) || defined(__x86_64__)) - // After patch "arm64: mm: support ARCH_MMAP_RND_BITS." is introduced in - // linux kernel, the random gap between stack and mapped area is increased - // from 128M to 36G on 39-bit aarch64. As it is almost impossible to cover - // this big range, we should disable randomized virtual space on aarch64. - // ASLR personality check. - int old_personality = personality(0xffffffff); - if (old_personality != -1 && (old_personality & ADDR_NO_RANDOMIZE) == 0) { - VReport(1, "WARNING: Program is run with randomized virtual address " - "space, which wouldn't work with ThreadSanitizer.\n" - "Re-execing with fixed virtual address space.\n"); - CHECK_NE(personality(old_personality | ADDR_NO_RANDOMIZE), -1); - reexec = true; - } - -#endif -#if SANITIZER_LINUX && (defined(__aarch64__) || defined(__loongarch_lp64)) +# if SANITIZER_LINUX && (defined(__aarch64__) || defined(__loongarch_lp64)) // Initialize the xor key used in {sig}{set,long}jump. InitializeLongjmpXorKey(); -#endif - if (reexec) - ReExec(); +# endif + } + + // Earlier initialization steps already re-exec'ed until we got a compatible + // memory layout, so we don't expect any more issues here. + if (!CheckAndProtect(true, true, true)) { + Printf( + "FATAL: ThreadSanitizer: unexpectedly found incompatible memory " + "layout.\n"); + Printf("FATAL: Please file a bug.\n"); + Die(); } - CheckAndProtect(); InitTlsSize(); #endif // !SANITIZER_GO } diff --git a/compiler-rt/lib/tsan/rtl/tsan_platform_mac.cpp b/compiler-rt/lib/tsan/rtl/tsan_platform_mac.cpp index 1aac0fb2752..07d83e1a9a9 100644 --- a/compiler-rt/lib/tsan/rtl/tsan_platform_mac.cpp +++ b/compiler-rt/lib/tsan/rtl/tsan_platform_mac.cpp @@ -239,7 +239,10 @@ static uptr longjmp_xor_key = 0; void InitializePlatform() { DisableCoreDumperIfNecessary(); #if !SANITIZER_GO - CheckAndProtect(); + if (!CheckAndProtect(true, true, true)) { + Printf("FATAL: ThreadSanitizer: found incompatible memory layout.\n"); + Die(); + } InitializeThreadStateStorage(); diff --git a/compiler-rt/lib/tsan/rtl/tsan_platform_posix.cpp b/compiler-rt/lib/tsan/rtl/tsan_platform_posix.cpp index e7dcd664dc0..7d5a992dc66 100644 --- a/compiler-rt/lib/tsan/rtl/tsan_platform_posix.cpp +++ b/compiler-rt/lib/tsan/rtl/tsan_platform_posix.cpp @@ -94,22 +94,51 @@ static void ProtectRange(uptr beg, uptr end) { } } -void CheckAndProtect() { +// CheckAndProtect will check if the memory layout is compatible with TSan. +// Optionally (if 'protect' is true), it will set the memory regions between +// app memory to be inaccessible. +// 'ignore_heap' means it will not consider heap memory allocations to be a +// conflict. Set this based on whether we are calling CheckAndProtect before +// or after the allocator has initialized the heap. +bool CheckAndProtect(bool protect, bool ignore_heap, bool print_warnings) { // Ensure that the binary is indeed compiled with -pie. MemoryMappingLayout proc_maps(true); MemoryMappedSegment segment; while (proc_maps.Next(&segment)) { - if (IsAppMem(segment.start)) continue; + if (segment.start >= HeapMemBeg() && segment.end <= HeapEnd()) { + if (ignore_heap) { + continue; + } else { + return false; + } + } + + // Note: IsAppMem includes if it is heap memory, hence we must + // put this check after the heap bounds check. + if (IsAppMem(segment.start) && IsAppMem(segment.end - 1)) + continue; + + // Guard page after the heap end if (segment.start >= HeapMemEnd() && segment.start < HeapEnd()) continue; + if (segment.protection == 0) // Zero page or mprotected. continue; + if (segment.start >= VdsoBeg()) // vdso break; - Printf("FATAL: ThreadSanitizer: unexpected memory mapping 0x%zx-0x%zx\n", - segment.start, segment.end); - Die(); + + // Debug output can break tests. Suppress this message in most cases. + if (print_warnings) + Printf( + "WARNING: ThreadSanitizer: unexpected memory mapping 0x%zx-0x%zx\n", + segment.start, segment.end); + + return false; } + if (!protect) + return true; + # if SANITIZER_IOS && !SANITIZER_IOSSIM ProtectRange(HeapMemEnd(), ShadowBeg()); ProtectRange(ShadowEnd(), MetaShadowBeg()); @@ -135,8 +164,10 @@ void CheckAndProtect() { // Older s390x kernels may not support 5-level page tables. TryProtectRange(user_addr_max_l4, user_addr_max_l5); #endif + + return true; } -#endif +# endif } // namespace __tsan diff --git a/libcxx/include/__algorithm/clamp.h b/libcxx/include/__algorithm/clamp.h index 1631b2673c3..003bf70dd4f 100644 --- a/libcxx/include/__algorithm/clamp.h +++ b/libcxx/include/__algorithm/clamp.h @@ -26,7 +26,7 @@ clamp(_LIBCPP_LIFETIMEBOUND const _Tp& __v, _LIBCPP_LIFETIMEBOUND const _Tp& __lo, _LIBCPP_LIFETIMEBOUND const _Tp& __hi, _Compare __comp) { - _LIBCPP_ASSERT_UNCATEGORIZED(!__comp(__hi, __lo), "Bad bounds passed to std::clamp"); + _LIBCPP_ASSERT_ARGUMENT_WITHIN_DOMAIN(!__comp(__hi, __lo), "Bad bounds passed to std::clamp"); return __comp(__v, __lo) ? __lo : __comp(__hi, __v) ? __hi : __v; } diff --git a/libcxx/include/__algorithm/comp_ref_type.h b/libcxx/include/__algorithm/comp_ref_type.h index 15f4a535a30..aa9350c38ca 100644 --- a/libcxx/include/__algorithm/comp_ref_type.h +++ b/libcxx/include/__algorithm/comp_ref_type.h @@ -44,7 +44,7 @@ struct __debug_less { _LIBCPP_CONSTEXPR_SINCE_CXX14 inline _LIBCPP_HIDE_FROM_ABI decltype((void)std::declval<_Compare&>()( std::declval<_LHS&>(), std::declval<_RHS&>())) __do_compare_assert(int, _LHS& __l, _RHS& __r) { - _LIBCPP_ASSERT_UNCATEGORIZED(!__comp_(__l, __r), "Comparator does not induce a strict weak ordering"); + _LIBCPP_ASSERT_SEMANTIC_REQUIREMENT(!__comp_(__l, __r), "Comparator does not induce a strict weak ordering"); (void)__l; (void)__r; } @@ -53,8 +53,7 @@ struct __debug_less { _LIBCPP_CONSTEXPR_SINCE_CXX14 inline _LIBCPP_HIDE_FROM_ABI void __do_compare_assert(long, _LHS&, _RHS&) {} }; -// Pass the comparator by lvalue reference. Or in debug mode, using a -// debugging wrapper that stores a reference. +// Pass the comparator by lvalue reference. Or in the debug mode, using a debugging wrapper that stores a reference. #if _LIBCPP_HARDENING_MODE == _LIBCPP_HARDENING_MODE_DEBUG template using __comp_ref_type = __debug_less<_Comp>; diff --git a/libcxx/include/__algorithm/nth_element.h b/libcxx/include/__algorithm/nth_element.h index a0597051259..37ddfbdacf0 100644 --- a/libcxx/include/__algorithm/nth_element.h +++ b/libcxx/include/__algorithm/nth_element.h @@ -114,12 +114,12 @@ __nth_element( while (true) { while (!__comp(*__first, *__i)) { ++__i; - _LIBCPP_ASSERT_UNCATEGORIZED( + _LIBCPP_ASSERT_VALID_ELEMENT_ACCESS( __i != __last, "Would read out of bounds, does your comparator satisfy the strict-weak ordering requirement?"); } do { - _LIBCPP_ASSERT_UNCATEGORIZED( + _LIBCPP_ASSERT_VALID_ELEMENT_ACCESS( __j != __first, "Would read out of bounds, does your comparator satisfy the strict-weak ordering requirement?"); --__j; @@ -150,13 +150,13 @@ __nth_element( // __m still guards upward moving __i while (__comp(*__i, *__m)) { ++__i; - _LIBCPP_ASSERT_UNCATEGORIZED( + _LIBCPP_ASSERT_VALID_ELEMENT_ACCESS( __i != __last, "Would read out of bounds, does your comparator satisfy the strict-weak ordering requirement?"); } // It is now known that a guard exists for downward moving __j do { - _LIBCPP_ASSERT_UNCATEGORIZED( + _LIBCPP_ASSERT_VALID_ELEMENT_ACCESS( __j != __first, "Would read out of bounds, does your comparator satisfy the strict-weak ordering requirement?"); --__j; diff --git a/libcxx/include/__algorithm/ranges_clamp.h b/libcxx/include/__algorithm/ranges_clamp.h index e6c86207254..a1185e7278f 100644 --- a/libcxx/include/__algorithm/ranges_clamp.h +++ b/libcxx/include/__algorithm/ranges_clamp.h @@ -34,8 +34,9 @@ struct __fn { indirect_strict_weak_order> _Comp = ranges::less> _LIBCPP_NODISCARD_EXT _LIBCPP_HIDE_FROM_ABI constexpr const _Type& operator()( const _Type& __value, const _Type& __low, const _Type& __high, _Comp __comp = {}, _Proj __proj = {}) const { - _LIBCPP_ASSERT_UNCATEGORIZED(!bool(std::invoke(__comp, std::invoke(__proj, __high), std::invoke(__proj, __low))), - "Bad bounds passed to std::ranges::clamp"); + _LIBCPP_ASSERT_ARGUMENT_WITHIN_DOMAIN( + !bool(std::invoke(__comp, std::invoke(__proj, __high), std::invoke(__proj, __low))), + "Bad bounds passed to std::ranges::clamp"); auto&& __projected = std::invoke(__proj, __value); if (std::invoke(__comp, std::forward(__projected), std::invoke(__proj, __low))) diff --git a/libcxx/include/__algorithm/sort.h b/libcxx/include/__algorithm/sort.h index ac47489af0a..451133a2d19 100644 --- a/libcxx/include/__algorithm/sort.h +++ b/libcxx/include/__algorithm/sort.h @@ -325,7 +325,7 @@ __insertion_sort_unguarded(_RandomAccessIterator const __first, _RandomAccessIte do { *__j = _Ops::__iter_move(__k); __j = __k; - _LIBCPP_ASSERT_UNCATEGORIZED( + _LIBCPP_ASSERT_VALID_ELEMENT_ACCESS( __k != __leftmost, "Would read out of bounds, does your comparator satisfy the strict-weak ordering requirement?"); } while (__comp(__t, *--__k)); // No need for bounds check due to the assumption stated above. @@ -544,7 +544,7 @@ __bitset_partition(_RandomAccessIterator __first, _RandomAccessIterator __last, // Not guarded since we know the last element is greater than the pivot. do { ++__first; - _LIBCPP_ASSERT_UNCATEGORIZED( + _LIBCPP_ASSERT_VALID_ELEMENT_ACCESS( __first != __end, "Would read out of bounds, does your comparator satisfy the strict-weak ordering requirement?"); } while (!__comp(__pivot, *__first)); @@ -557,7 +557,7 @@ __bitset_partition(_RandomAccessIterator __first, _RandomAccessIterator __last, // It will be always guarded because __introsort will do the median-of-three // before calling this. do { - _LIBCPP_ASSERT_UNCATEGORIZED( + _LIBCPP_ASSERT_VALID_ELEMENT_ACCESS( __last != __begin, "Would read out of bounds, does your comparator satisfy the strict-weak ordering requirement?"); --__last; @@ -635,7 +635,7 @@ __partition_with_equals_on_right(_RandomAccessIterator __first, _RandomAccessIte // this. do { ++__first; - _LIBCPP_ASSERT_UNCATEGORIZED( + _LIBCPP_ASSERT_VALID_ELEMENT_ACCESS( __first != __end, "Would read out of bounds, does your comparator satisfy the strict-weak ordering requirement?"); } while (__comp(*__first, __pivot)); @@ -647,7 +647,7 @@ __partition_with_equals_on_right(_RandomAccessIterator __first, _RandomAccessIte } else { // Guarded. do { - _LIBCPP_ASSERT_UNCATEGORIZED( + _LIBCPP_ASSERT_VALID_ELEMENT_ACCESS( __last != __begin, "Would read out of bounds, does your comparator satisfy the strict-weak ordering requirement?"); --__last; @@ -665,12 +665,12 @@ __partition_with_equals_on_right(_RandomAccessIterator __first, _RandomAccessIte _Ops::iter_swap(__first, __last); do { ++__first; - _LIBCPP_ASSERT_UNCATEGORIZED( + _LIBCPP_ASSERT_VALID_ELEMENT_ACCESS( __first != __end, "Would read out of bounds, does your comparator satisfy the strict-weak ordering requirement?"); } while (__comp(*__first, __pivot)); do { - _LIBCPP_ASSERT_UNCATEGORIZED( + _LIBCPP_ASSERT_VALID_ELEMENT_ACCESS( __last != __begin, "Would read out of bounds, does your comparator satisfy the strict-weak ordering requirement?"); --__last; @@ -702,7 +702,7 @@ __partition_with_equals_on_left(_RandomAccessIterator __first, _RandomAccessIter // Guarded. do { ++__first; - _LIBCPP_ASSERT_UNCATEGORIZED( + _LIBCPP_ASSERT_VALID_ELEMENT_ACCESS( __first != __end, "Would read out of bounds, does your comparator satisfy the strict-weak ordering requirement?"); } while (!__comp(__pivot, *__first)); @@ -715,7 +715,7 @@ __partition_with_equals_on_left(_RandomAccessIterator __first, _RandomAccessIter // It will be always guarded because __introsort will do the // median-of-three before calling this. do { - _LIBCPP_ASSERT_UNCATEGORIZED( + _LIBCPP_ASSERT_VALID_ELEMENT_ACCESS( __last != __begin, "Would read out of bounds, does your comparator satisfy the strict-weak ordering requirement?"); --__last; @@ -725,12 +725,12 @@ __partition_with_equals_on_left(_RandomAccessIterator __first, _RandomAccessIter _Ops::iter_swap(__first, __last); do { ++__first; - _LIBCPP_ASSERT_UNCATEGORIZED( + _LIBCPP_ASSERT_VALID_ELEMENT_ACCESS( __first != __end, "Would read out of bounds, does your comparator satisfy the strict-weak ordering requirement?"); } while (!__comp(__pivot, *__first)); do { - _LIBCPP_ASSERT_UNCATEGORIZED( + _LIBCPP_ASSERT_VALID_ELEMENT_ACCESS( __last != __begin, "Would read out of bounds, does your comparator satisfy the strict-weak ordering requirement?"); --__last; diff --git a/libcxx/include/__algorithm/three_way_comp_ref_type.h b/libcxx/include/__algorithm/three_way_comp_ref_type.h index 8fd15c5d66f..70c5818976f 100644 --- a/libcxx/include/__algorithm/three_way_comp_ref_type.h +++ b/libcxx/include/__algorithm/three_way_comp_ref_type.h @@ -50,14 +50,14 @@ struct __debug_three_way_comp { __expected = _Order::greater; if (__o == _Order::greater) __expected = _Order::less; - _LIBCPP_ASSERT_UNCATEGORIZED(__comp_(__l, __r) == __expected, "Comparator does not induce a strict weak ordering"); + _LIBCPP_ASSERT_SEMANTIC_REQUIREMENT( + __comp_(__l, __r) == __expected, "Comparator does not induce a strict weak ordering"); (void)__l; (void)__r; } }; -// Pass the comparator by lvalue reference. Or in debug mode, using a -// debugging wrapper that stores a reference. +// Pass the comparator by lvalue reference. Or in the debug mode, using a debugging wrapper that stores a reference. # if _LIBCPP_HARDENING_MODE == _LIBCPP_HARDENING_MODE_DEBUG template using __three_way_comp_ref_type = __debug_three_way_comp<_Comp>; diff --git a/libcxx/include/__assert b/libcxx/include/__assert index d4af7e6c719..eb862b5369b 100644 --- a/libcxx/include/__assert +++ b/libcxx/include/__assert @@ -10,8 +10,8 @@ #ifndef _LIBCPP___ASSERT #define _LIBCPP___ASSERT +#include <__assertion_handler> // Note: this include is generated by CMake and is potentially vendor-provided. #include <__config> -#include <__verbose_abort> #if !defined(_LIBCPP_HAS_NO_PRAGMA_SYSTEM_HEADER) # pragma GCC system_header @@ -20,8 +20,8 @@ #define _LIBCPP_ASSERT(expression, message) \ (__builtin_expect(static_cast(expression), 1) \ ? (void)0 \ - : _LIBCPP_VERBOSE_ABORT( \ - "%s:%d: assertion %s failed: %s\n", __builtin_FILE(), __builtin_LINE(), #expression, message)) + : _LIBCPP_ASSERTION_HANDLER(__FILE__ ":" _LIBCPP_TOSTRING(__LINE__) ": assertion " _LIBCPP_TOSTRING( \ + expression) " failed: " message "\n")) // TODO: __builtin_assume can currently inhibit optimizations. Until this has been fixed and we can add // assumptions without a clear optimization intent, disable that to avoid worsening the code generation. diff --git a/libcxx/include/__atomic/is_always_lock_free.h b/libcxx/include/__atomic/is_always_lock_free.h index fbbd4370749..f928e79f70c 100644 --- a/libcxx/include/__atomic/is_always_lock_free.h +++ b/libcxx/include/__atomic/is_always_lock_free.h @@ -20,7 +20,7 @@ _LIBCPP_BEGIN_NAMESPACE_STD template struct __libcpp_is_always_lock_free { // __atomic_always_lock_free is available in all Standard modes - static const bool __value = __atomic_always_lock_free(sizeof(_Tp), 0); + static const bool __value = __atomic_always_lock_free(sizeof(_Tp), nullptr); }; _LIBCPP_END_NAMESPACE_STD diff --git a/libcxx/include/__availability b/libcxx/include/__availability index 5df2783dd0c..c5069a02775 100644 --- a/libcxx/include/__availability +++ b/libcxx/include/__availability @@ -101,6 +101,12 @@ # define _LIBCPP_AVAILABILITY_HAS_BAD_ANY_CAST 1 # define _LIBCPP_AVAILABILITY_BAD_ANY_CAST +// These macros controls the availability of __cxa_init_primary_exception +// in the built library, which std::make_exception_ptr might use +// (see libcxx/include/__exception/exception_ptr.h). +# define _LIBCPP_AVAILABILITY_HAS_INIT_PRIMARY_EXCEPTION 1 +# define _LIBCPP_AVAILABILITY_INIT_PRIMARY_EXCEPTION + // These macros control the availability of all parts of that // depend on something in the dylib. # define _LIBCPP_AVAILABILITY_HAS_FILESYSTEM_LIBRARY 1 @@ -136,9 +142,9 @@ # define _LIBCPP_AVAILABILITY_HAS_TZDB 1 # define _LIBCPP_AVAILABILITY_TZDB - // This controls the availability of C++23 , which - // has a dependency on the built library (it needs access to - // the underlying buffer types of std::cout, std::cerr, and std::clog. +// This controls the availability of C++23 , which +// has a dependency on the built library (it needs access to +// the underlying buffer types of std::cout, std::cerr, and std::clog. # define _LIBCPP_AVAILABILITY_HAS_PRINT 1 # define _LIBCPP_AVAILABILITY_PRINT @@ -167,6 +173,10 @@ # define _LIBCPP_AVAILABILITY_BAD_VARIANT_ACCESS _LIBCPP_AVAILABILITY_BAD_OPTIONAL_ACCESS # define _LIBCPP_AVAILABILITY_BAD_ANY_CAST _LIBCPP_AVAILABILITY_BAD_OPTIONAL_ACCESS +// TODO: Update once this is released +# define _LIBCPP_AVAILABILITY_HAS_INIT_PRIMARY_EXCEPTION 0 +# define _LIBCPP_AVAILABILITY_INIT_PRIMARY_EXCEPTION __attribute__((unavailable)) + // // clang-format off # if (defined(__ENVIRONMENT_MAC_OS_X_VERSION_MIN_REQUIRED__) && __ENVIRONMENT_MAC_OS_X_VERSION_MIN_REQUIRED__ < 101500) || \ @@ -264,6 +274,10 @@ # define _LIBCPP_AVAILABILITY_HAS_TZDB 0 # define _LIBCPP_AVAILABILITY_TZDB __attribute__((unavailable)) +// Warning: This availability macro works differently than the other macros. +// The dylib part of print is not needed on Apple platforms. Therefore when +// the macro is not available the code calling the dylib is commented out. +// The macro _LIBCPP_AVAILABILITY_PRINT is not used. # define _LIBCPP_AVAILABILITY_HAS_PRINT 0 # define _LIBCPP_AVAILABILITY_PRINT __attribute__((unavailable)) @@ -299,4 +313,13 @@ # define _LIBCPP_AVAILABILITY_THROW_BAD_VARIANT_ACCESS _LIBCPP_AVAILABILITY_BAD_VARIANT_ACCESS #endif +// Define availability attributes that depend on both +// _LIBCPP_HAS_NO_EXCEPTIONS and _LIBCPP_HAS_NO_RTTI. +#if defined(_LIBCPP_HAS_NO_EXCEPTIONS) || defined(_LIBCPP_HAS_NO_RTTI) +# undef _LIBCPP_AVAILABILITY_HAS_INIT_PRIMARY_EXCEPTION +# undef _LIBCPP_AVAILABILITY_INIT_PRIMARY_EXCEPTION +# define _LIBCPP_AVAILABILITY_HAS_INIT_PRIMARY_EXCEPTION 0 +# define _LIBCPP_AVAILABILITY_INIT_PRIMARY_EXCEPTION +#endif + #endif // _LIBCPP___AVAILABILITY diff --git a/libcxx/include/__bit/bit_ceil.h b/libcxx/include/__bit/bit_ceil.h index 17fe06aa41c..77fa739503b 100644 --- a/libcxx/include/__bit/bit_ceil.h +++ b/libcxx/include/__bit/bit_ceil.h @@ -28,7 +28,7 @@ _LIBCPP_NODISCARD_EXT _LIBCPP_HIDE_FROM_ABI constexpr _Tp __bit_ceil(_Tp __t) no if (__t < 2) return 1; const unsigned __n = numeric_limits<_Tp>::digits - std::__countl_zero((_Tp)(__t - 1u)); - _LIBCPP_ASSERT_UNCATEGORIZED(__n != numeric_limits<_Tp>::digits, "Bad input to bit_ceil"); + _LIBCPP_ASSERT_ARGUMENT_WITHIN_DOMAIN(__n != numeric_limits<_Tp>::digits, "Bad input to bit_ceil"); if constexpr (sizeof(_Tp) >= sizeof(unsigned)) return _Tp{1} << __n; diff --git a/libcxx/include/__chrono/ostream.h b/libcxx/include/__chrono/ostream.h index f171944b5ca..b687ef8059d 100644 --- a/libcxx/include/__chrono/ostream.h +++ b/libcxx/include/__chrono/ostream.h @@ -42,11 +42,18 @@ _LIBCPP_BEGIN_NAMESPACE_STD namespace chrono { template + requires(!treat_as_floating_point_v && _Duration{1} < days{1}) _LIBCPP_HIDE_FROM_ABI basic_ostream<_CharT, _Traits>& -operator<<(basic_ostream<_CharT, _Traits>& __os, const sys_time<_Duration> __tp) { +operator<<(basic_ostream<_CharT, _Traits>& __os, const sys_time<_Duration>& __tp) { return __os << std::format(__os.getloc(), _LIBCPP_STATICALLY_WIDEN(_CharT, "{:L%F %T}"), __tp); } +template +_LIBCPP_HIDE_FROM_ABI basic_ostream<_CharT, _Traits>& +operator<<(basic_ostream<_CharT, _Traits>& __os, const sys_days& __dp) { + return __os << year_month_day{__dp}; +} + template _LIBCPP_HIDE_FROM_ABI basic_ostream<_CharT, _Traits>& operator<<(basic_ostream<_CharT, _Traits>& __os, const file_time<_Duration> __tp) { diff --git a/libcxx/include/__concepts/arithmetic.h b/libcxx/include/__concepts/arithmetic.h index f41e4c9f274..0c44f117805 100644 --- a/libcxx/include/__concepts/arithmetic.h +++ b/libcxx/include/__concepts/arithmetic.h @@ -42,9 +42,13 @@ concept floating_point = is_floating_point_v<_Tp>; template concept __libcpp_unsigned_integer = __libcpp_is_unsigned_integer<_Tp>::value; + template concept __libcpp_signed_integer = __libcpp_is_signed_integer<_Tp>::value; +template +concept __libcpp_integer = __libcpp_unsigned_integer<_Tp> || __libcpp_signed_integer<_Tp>; + #endif // _LIBCPP_STD_VER >= 20 _LIBCPP_END_NAMESPACE_STD diff --git a/libcxx/include/__config b/libcxx/include/__config index 1958d5c50ca..9557e8e8cf9 100644 --- a/libcxx/include/__config +++ b/libcxx/include/__config @@ -16,6 +16,17 @@ # pragma GCC system_header #endif +#if defined(_LIBCPP_ENABLE_CXX17_REMOVED_FEATURES) && !defined(_LIBCPP_DISABLE_DEPRECATION_WARNINGS) +# pragma clang deprecated( \ + _LIBCPP_ENABLE_CXX17_REMOVED_FEATURES, \ + "_LIBCPP_ENABLE_CXX17_REMOVED_FEATURES is deprecated in LLVM 18 and will be removed in LLVM 19") +#endif +#if defined(_LIBCPP_ENABLE_CXX20_REMOVED_FEATURES) && !defined(_LIBCPP_DISABLE_DEPRECATION_WARNINGS) +# pragma clang deprecated( \ + _LIBCPP_ENABLE_CXX20_REMOVED_FEATURES, \ + "_LIBCPP_ENABLE_CXX20_REMOVED_FEATURES is deprecated in LLVM 18 and will be removed in LLVM 19") +#endif + #if defined(__apple_build_version__) // Given AppleClang XX.Y.Z, _LIBCPP_APPLE_CLANG_VER is XXYZ (e.g. AppleClang 14.0.3 => 1403) # define _LIBCPP_COMPILER_CLANG_BASED @@ -207,8 +218,8 @@ // https://github.com/llvm/llvm-project/issues/70494 // // To fix the bug we had to change the ABI of some classes to remove [[no_unique_address]] under certain conditions. -// The below macro is used for all classes whose ABI have changed as part of fixing these bugs. -# define _LIBCPP_ABI_2023_OVERLAPPING_SUBOBJECT_FIX_TAG __attribute__((__abi_tag__("subobj_fix_2023"))) +// The macro below is used for all classes whose ABI have changed as part of fixing these bugs. +# define _LIBCPP_ABI_LLVM18_NO_UNIQUE_ADDRESS __attribute__((__abi_tag__("llvm18_nua"))) // Changes the iterator type of select containers (see below) to a bounded iterator that keeps track of whether it's // within the bounds of the original container and asserts it on every dereference. @@ -280,12 +291,32 @@ // - `_LIBCPP_ASSERT_NON_OVERLAPPING_RANGES` -- for functions that take several ranges as arguments, checks that the // given ranges do not overlap. // +// - `_LIBCPP_ASSERT_VALID_DEALLOCATION` -- checks that an attempt to deallocate memory is valid (e.g. the given object +// was allocated by the given allocator). Violating this category typically results in a memory leak. +// +// - `_LIBCPP_ASSERT_VALID_EXTERNAL_API_CALL` -- checks that a call to an external API doesn't fail in +// an unexpected manner. This includes triggering documented cases of undefined behavior in an external library (like +// attempting to unlock an unlocked mutex in pthreads). Any API external to the library falls under this category +// (from system calls to compiler intrinsics). We generally don't expect these failures to compromize memory safety or +// otherwise create an immediate security issue. +// // - `_LIBCPP_ASSERT_COMPATIBLE_ALLOCATOR` -- checks any operations that exchange nodes between containers to make sure // the containers have compatible allocators. // +// - `_LIBCPP_ASSERT_ARGUMENT_WITHIN_DOMAIN` -- checks that the given argument is within the domain of valid arguments +// for the function. Violating this typically produces an incorrect result (e.g. the clamp algorithm returns the +// original value without clamping it due to incorrect functors) or puts an object into an invalid state (e.g. +// a string view where only a subset of elements is possible to access). This category is for assertions violating +// which doesn't cause any immediate issues in the library -- whatever the consequences are, they will happen in the +// user code. +// // - `_LIBCPP_ASSERT_PEDANTIC` -- checks prerequisites which are imposed by the Standard, but violating which happens to // be benign in our implementation. // +// - `_LIBCPP_ASSERT_SEMANTIC_REQUIREMENT` -- checks that the given argument satisfies the semantic requirements imposed +// by the Standard. Typically, there is no simple way to completely prove that a semantic requirement is satisfied; +// thus, this would often be a heuristic check and it might be quite expensive. +// // - `_LIBCPP_ASSERT_INTERNAL` -- checks that internal invariants of the library hold. These assertions don't depend on // user input. // @@ -327,8 +358,12 @@ _LIBCPP_HARDENING_MODE_DEBUG // Overlapping ranges will make algorithms produce incorrect results but don't directly lead to a security // vulnerability. # define _LIBCPP_ASSERT_NON_OVERLAPPING_RANGES(expression, message) _LIBCPP_ASSUME(expression) +# define _LIBCPP_ASSERT_VALID_DEALLOCATION(expression, message) _LIBCPP_ASSUME(expression) +# define _LIBCPP_ASSERT_VALID_EXTERNAL_API_CALL(expression, message) _LIBCPP_ASSUME(expression) # define _LIBCPP_ASSERT_COMPATIBLE_ALLOCATOR(expression, message) _LIBCPP_ASSUME(expression) +# define _LIBCPP_ASSERT_ARGUMENT_WITHIN_DOMAIN(expression, message) _LIBCPP_ASSUME(expression) # define _LIBCPP_ASSERT_PEDANTIC(expression, message) _LIBCPP_ASSUME(expression) +# define _LIBCPP_ASSERT_SEMANTIC_REQUIREMENT(expression, message) _LIBCPP_ASSUME(expression) # define _LIBCPP_ASSERT_INTERNAL(expression, message) _LIBCPP_ASSUME(expression) # define _LIBCPP_ASSERT_UNCATEGORIZED(expression, message) _LIBCPP_ASSUME(expression) @@ -341,10 +376,14 @@ _LIBCPP_HARDENING_MODE_DEBUG # define _LIBCPP_ASSERT_VALID_ELEMENT_ACCESS(expression, message) _LIBCPP_ASSERT(expression, message) # define _LIBCPP_ASSERT_NON_NULL(expression, message) _LIBCPP_ASSERT(expression, message) # define _LIBCPP_ASSERT_NON_OVERLAPPING_RANGES(expression, message) _LIBCPP_ASSERT(expression, message) +# define _LIBCPP_ASSERT_VALID_DEALLOCATION(expression, message) _LIBCPP_ASSERT(expression, message) +# define _LIBCPP_ASSERT_VALID_EXTERNAL_API_CALL(expression, message) _LIBCPP_ASSERT(expression, message) # define _LIBCPP_ASSERT_COMPATIBLE_ALLOCATOR(expression, message) _LIBCPP_ASSERT(expression, message) -# define _LIBCPP_ASSERT_UNCATEGORIZED(expression, message) _LIBCPP_ASSERT(expression, message) +# define _LIBCPP_ASSERT_ARGUMENT_WITHIN_DOMAIN(expression, message) _LIBCPP_ASSERT(expression, message) # define _LIBCPP_ASSERT_PEDANTIC(expression, message) _LIBCPP_ASSERT(expression, message) +# define _LIBCPP_ASSERT_UNCATEGORIZED(expression, message) _LIBCPP_ASSERT(expression, message) // Disabled checks. +# define _LIBCPP_ASSERT_SEMANTIC_REQUIREMENT(expression, message) _LIBCPP_ASSUME(expression) # define _LIBCPP_ASSERT_INTERNAL(expression, message) _LIBCPP_ASSUME(expression) // Debug hardening mode checks. @@ -356,8 +395,12 @@ _LIBCPP_HARDENING_MODE_DEBUG # define _LIBCPP_ASSERT_VALID_ELEMENT_ACCESS(expression, message) _LIBCPP_ASSERT(expression, message) # define _LIBCPP_ASSERT_NON_NULL(expression, message) _LIBCPP_ASSERT(expression, message) # define _LIBCPP_ASSERT_NON_OVERLAPPING_RANGES(expression, message) _LIBCPP_ASSERT(expression, message) +# define _LIBCPP_ASSERT_VALID_DEALLOCATION(expression, message) _LIBCPP_ASSERT(expression, message) +# define _LIBCPP_ASSERT_VALID_EXTERNAL_API_CALL(expression, message) _LIBCPP_ASSERT(expression, message) # define _LIBCPP_ASSERT_COMPATIBLE_ALLOCATOR(expression, message) _LIBCPP_ASSERT(expression, message) +# define _LIBCPP_ASSERT_ARGUMENT_WITHIN_DOMAIN(expression, message) _LIBCPP_ASSERT(expression, message) # define _LIBCPP_ASSERT_PEDANTIC(expression, message) _LIBCPP_ASSERT(expression, message) +# define _LIBCPP_ASSERT_SEMANTIC_REQUIREMENT(expression, message) _LIBCPP_ASSERT(expression, message) # define _LIBCPP_ASSERT_INTERNAL(expression, message) _LIBCPP_ASSERT(expression, message) # define _LIBCPP_ASSERT_UNCATEGORIZED(expression, message) _LIBCPP_ASSERT(expression, message) @@ -370,8 +413,12 @@ _LIBCPP_HARDENING_MODE_DEBUG # define _LIBCPP_ASSERT_VALID_ELEMENT_ACCESS(expression, message) _LIBCPP_ASSUME(expression) # define _LIBCPP_ASSERT_NON_NULL(expression, message) _LIBCPP_ASSUME(expression) # define _LIBCPP_ASSERT_NON_OVERLAPPING_RANGES(expression, message) _LIBCPP_ASSUME(expression) +# define _LIBCPP_ASSERT_VALID_DEALLOCATION(expression, message) _LIBCPP_ASSUME(expression) +# define _LIBCPP_ASSERT_VALID_EXTERNAL_API_CALL(expression, message) _LIBCPP_ASSUME(expression) # define _LIBCPP_ASSERT_COMPATIBLE_ALLOCATOR(expression, message) _LIBCPP_ASSUME(expression) +# define _LIBCPP_ASSERT_ARGUMENT_WITHIN_DOMAIN(expression, message) _LIBCPP_ASSUME(expression) # define _LIBCPP_ASSERT_PEDANTIC(expression, message) _LIBCPP_ASSUME(expression) +# define _LIBCPP_ASSERT_SEMANTIC_REQUIREMENT(expression, message) _LIBCPP_ASSUME(expression) # define _LIBCPP_ASSERT_INTERNAL(expression, message) _LIBCPP_ASSUME(expression) # define _LIBCPP_ASSERT_UNCATEGORIZED(expression, message) _LIBCPP_ASSUME(expression) @@ -1188,7 +1235,18 @@ __sanitizer_verify_double_ended_contiguous_container(const void*, const void*, c # define _LIBCPP_CONSTINIT # endif -# if __has_attribute(__noinline__) +# if defined(__CUDACC__) || defined(__CUDA_ARCH__) || defined(__CUDA_LIBDEVICE__) +// The CUDA SDK contains an unfortunate definition for the __noinline__ macro, +// which breaks the regular __attribute__((__noinline__)) syntax. Therefore, +// when compiling for CUDA we use the non-underscored version of the noinline +// attribute. +// +// This is a temporary workaround and we still expect the CUDA SDK team to solve +// this issue properly in the SDK headers. +// +// See https://github.com/llvm/llvm-project/pull/73838 for more details. +# define _LIBCPP_NOINLINE __attribute__((noinline)) +# elif __has_attribute(__noinline__) # define _LIBCPP_NOINLINE __attribute__((__noinline__)) # else # define _LIBCPP_NOINLINE @@ -1502,6 +1560,11 @@ __sanitizer_verify_double_ended_contiguous_container(const void*, const void*, c # define _LIBCPP_DISABLE_UBSAN_UNSIGNED_INTEGER_CHECK # endif +// Clang-18 has support for deducing this, but it does not set the FTM. +# if defined(__cpp_explicit_this_parameter) || (defined(_LIBCPP_CLANG_VER) && _LIBCPP_CLANG_VER >= 1800) +# define _LIBCPP_HAS_EXPLICIT_THIS_PARAMETER +# endif + #endif // __cplusplus #endif // _LIBCPP___CONFIG diff --git a/libcxx/include/__coroutine/coroutine_handle.h b/libcxx/include/__coroutine/coroutine_handle.h index 54bfe5b44f4..4557a6643c2 100644 --- a/libcxx/include/__coroutine/coroutine_handle.h +++ b/libcxx/include/__coroutine/coroutine_handle.h @@ -55,7 +55,7 @@ public: _LIBCPP_HIDE_FROM_ABI constexpr explicit operator bool() const noexcept { return __handle_ != nullptr; } _LIBCPP_HIDE_FROM_ABI bool done() const { - _LIBCPP_ASSERT_UNCATEGORIZED(__is_suspended(), "done() can be called only on suspended coroutines"); + _LIBCPP_ASSERT_VALID_EXTERNAL_API_CALL(__is_suspended(), "done() can be called only on suspended coroutines"); return __builtin_coro_done(__handle_); } @@ -63,13 +63,13 @@ public: _LIBCPP_HIDE_FROM_ABI void operator()() const { resume(); } _LIBCPP_HIDE_FROM_ABI void resume() const { - _LIBCPP_ASSERT_UNCATEGORIZED(__is_suspended(), "resume() can be called only on suspended coroutines"); - _LIBCPP_ASSERT_UNCATEGORIZED(!done(), "resume() has undefined behavior when the coroutine is done"); + _LIBCPP_ASSERT_VALID_EXTERNAL_API_CALL(__is_suspended(), "resume() can be called only on suspended coroutines"); + _LIBCPP_ASSERT_VALID_EXTERNAL_API_CALL(!done(), "resume() has undefined behavior when the coroutine is done"); __builtin_coro_resume(__handle_); } _LIBCPP_HIDE_FROM_ABI void destroy() const { - _LIBCPP_ASSERT_UNCATEGORIZED(__is_suspended(), "destroy() can be called only on suspended coroutines"); + _LIBCPP_ASSERT_VALID_EXTERNAL_API_CALL(__is_suspended(), "destroy() can be called only on suspended coroutines"); __builtin_coro_destroy(__handle_); } @@ -130,7 +130,7 @@ public: _LIBCPP_HIDE_FROM_ABI constexpr explicit operator bool() const noexcept { return __handle_ != nullptr; } _LIBCPP_HIDE_FROM_ABI bool done() const { - _LIBCPP_ASSERT_UNCATEGORIZED(__is_suspended(), "done() can be called only on suspended coroutines"); + _LIBCPP_ASSERT_VALID_EXTERNAL_API_CALL(__is_suspended(), "done() can be called only on suspended coroutines"); return __builtin_coro_done(__handle_); } @@ -138,13 +138,13 @@ public: _LIBCPP_HIDE_FROM_ABI void operator()() const { resume(); } _LIBCPP_HIDE_FROM_ABI void resume() const { - _LIBCPP_ASSERT_UNCATEGORIZED(__is_suspended(), "resume() can be called only on suspended coroutines"); - _LIBCPP_ASSERT_UNCATEGORIZED(!done(), "resume() has undefined behavior when the coroutine is done"); + _LIBCPP_ASSERT_VALID_EXTERNAL_API_CALL(__is_suspended(), "resume() can be called only on suspended coroutines"); + _LIBCPP_ASSERT_VALID_EXTERNAL_API_CALL(!done(), "resume() has undefined behavior when the coroutine is done"); __builtin_coro_resume(__handle_); } _LIBCPP_HIDE_FROM_ABI void destroy() const { - _LIBCPP_ASSERT_UNCATEGORIZED(__is_suspended(), "destroy() can be called only on suspended coroutines"); + _LIBCPP_ASSERT_VALID_EXTERNAL_API_CALL(__is_suspended(), "destroy() can be called only on suspended coroutines"); __builtin_coro_destroy(__handle_); } diff --git a/libcxx/include/__debug_utils/strict_weak_ordering_check.h b/libcxx/include/__debug_utils/strict_weak_ordering_check.h index 99200ad65ea..3a9d8872841 100644 --- a/libcxx/include/__debug_utils/strict_weak_ordering_check.h +++ b/libcxx/include/__debug_utils/strict_weak_ordering_check.h @@ -26,12 +26,12 @@ _LIBCPP_BEGIN_NAMESPACE_STD template _LIBCPP_HIDE_FROM_ABI _LIBCPP_CONSTEXPR_SINCE_CXX14 void __check_strict_weak_ordering_sorted(_RandomAccessIterator __first, _RandomAccessIterator __last, _Comp& __comp) { -#ifdef _LIBCPP_DEBUG_STRICT_WEAK_ORDERING_CHECK +#if _LIBCPP_HARDENING_MODE == _LIBCPP_HARDENING_MODE_DEBUG using __diff_t = __iter_diff_t<_RandomAccessIterator>; using _Comp_ref = __comp_ref_type<_Comp>; if (!__libcpp_is_constant_evaluated()) { // Check if the range is actually sorted. - _LIBCPP_ASSERT_UNCATEGORIZED( + _LIBCPP_ASSERT_SEMANTIC_REQUIREMENT( (std::is_sorted<_RandomAccessIterator, _Comp_ref>(__first, __last, _Comp_ref(__comp))), "The range is not sorted after the sort, your comparator is not a valid strict-weak ordering"); // Limit the number of elements we need to check. @@ -46,18 +46,18 @@ __check_strict_weak_ordering_sorted(_RandomAccessIterator __first, _RandomAccess // Check that the elements from __p to __q are equal between each other. for (__diff_t __b = __p; __b < __q; ++__b) { for (__diff_t __a = __p; __a <= __b; ++__a) { - _LIBCPP_ASSERT_UNCATEGORIZED( + _LIBCPP_ASSERT_SEMANTIC_REQUIREMENT( !__comp(*(__first + __a), *(__first + __b)), "Your comparator is not a valid strict-weak ordering"); - _LIBCPP_ASSERT_UNCATEGORIZED( + _LIBCPP_ASSERT_SEMANTIC_REQUIREMENT( !__comp(*(__first + __b), *(__first + __a)), "Your comparator is not a valid strict-weak ordering"); } } // Check that elements between __p and __q are less than between __q and __size. for (__diff_t __a = __p; __a < __q; ++__a) { for (__diff_t __b = __q; __b < __size; ++__b) { - _LIBCPP_ASSERT_UNCATEGORIZED( + _LIBCPP_ASSERT_SEMANTIC_REQUIREMENT( __comp(*(__first + __a), *(__first + __b)), "Your comparator is not a valid strict-weak ordering"); - _LIBCPP_ASSERT_UNCATEGORIZED( + _LIBCPP_ASSERT_SEMANTIC_REQUIREMENT( !__comp(*(__first + __b), *(__first + __a)), "Your comparator is not a valid strict-weak ordering"); } } @@ -69,7 +69,7 @@ __check_strict_weak_ordering_sorted(_RandomAccessIterator __first, _RandomAccess (void)__first; (void)__last; (void)__comp; -#endif +#endif // _LIBCPP_HARDENING_MODE == _LIBCPP_HARDENING_MODE_DEBUG } _LIBCPP_END_NAMESPACE_STD diff --git a/libcxx/include/__exception/exception_ptr.h b/libcxx/include/__exception/exception_ptr.h index 970d8196724..53e2f718bc1 100644 --- a/libcxx/include/__exception/exception_ptr.h +++ b/libcxx/include/__exception/exception_ptr.h @@ -9,16 +9,44 @@ #ifndef _LIBCPP___EXCEPTION_EXCEPTION_PTR_H #define _LIBCPP___EXCEPTION_EXCEPTION_PTR_H +#include <__availability> #include <__config> #include <__exception/operations.h> #include <__memory/addressof.h> +#include <__memory/construct_at.h> +#include <__type_traits/decay.h> #include #include +#include +#include #if !defined(_LIBCPP_HAS_NO_PRAGMA_SYSTEM_HEADER) # pragma GCC system_header #endif +#ifndef _LIBCPP_ABI_MICROSOFT + +namespace __cxxabiv1 { + +extern "C" { +_LIBCPP_OVERRIDABLE_FUNC_VIS void* __cxa_allocate_exception(size_t) throw(); +_LIBCPP_OVERRIDABLE_FUNC_VIS void __cxa_free_exception(void*) throw(); + +struct __cxa_exception; +_LIBCPP_OVERRIDABLE_FUNC_VIS __cxa_exception* __cxa_init_primary_exception( + void*, + std::type_info*, + void( +# if defined(_WIN32) + __thiscall +# endif + *)(void*)) throw(); +} + +} // namespace __cxxabiv1 + +#endif + namespace std { // purposefully not using versioning namespace #ifndef _LIBCPP_ABI_MICROSOFT @@ -26,6 +54,11 @@ namespace std { // purposefully not using versioning namespace class _LIBCPP_EXPORTED_FROM_ABI exception_ptr { void* __ptr_; + static exception_ptr __from_native_exception_pointer(void*) _NOEXCEPT; + + template + friend _LIBCPP_HIDE_FROM_ABI exception_ptr make_exception_ptr(_Ep) _NOEXCEPT; + public: _LIBCPP_HIDE_FROM_ABI exception_ptr() _NOEXCEPT : __ptr_() {} _LIBCPP_HIDE_FROM_ABI exception_ptr(nullptr_t) _NOEXCEPT : __ptr_() {} @@ -51,11 +84,28 @@ public: template _LIBCPP_HIDE_FROM_ABI exception_ptr make_exception_ptr(_Ep __e) _NOEXCEPT { # ifndef _LIBCPP_HAS_NO_EXCEPTIONS +# if _LIBCPP_AVAILABILITY_HAS_INIT_PRIMARY_EXCEPTION && __cplusplus >= 201103L + using _Ep2 = __decay_t<_Ep>; + + void* __ex = __cxxabiv1::__cxa_allocate_exception(sizeof(_Ep)); + (void)__cxxabiv1::__cxa_init_primary_exception(__ex, const_cast(&typeid(_Ep)), [](void* __p) { + std::__destroy_at(static_cast<_Ep2*>(__p)); + }); + + try { + ::new (__ex) _Ep2(__e); + return exception_ptr::__from_native_exception_pointer(__ex); + } catch (...) { + __cxxabiv1::__cxa_free_exception(__ex); + return current_exception(); + } +# else try { throw __e; } catch (...) { return current_exception(); } +# endif # else ((void)__e); std::abort(); diff --git a/libcxx/include/__expected/expected.h b/libcxx/include/__expected/expected.h index 97f92bdfe44..443d9257dc5 100644 --- a/libcxx/include/__expected/expected.h +++ b/libcxx/include/__expected/expected.h @@ -88,8 +88,372 @@ _LIBCPP_HIDE_FROM_ABI void __throw_bad_expected_access(_Arg&& __arg) { # endif } +// If parameter type `_Tp` of `__conditional_no_unique_address` is neither +// copyable nor movable, a constructor with this tag is provided. For that +// constructor, the user has to provide a function and arguments. The function +// must return an object of type `_Tp`. When the function is invoked by the +// constructor, guaranteed copy elision kicks in and the `_Tp` is constructed +// in place. +struct __conditional_no_unique_address_invoke_tag {}; + +// This class implements an object with `[[no_unique_address]]` conditionally applied to it, +// based on the value of `_NoUnique`. +// +// A member of this class must always have `[[no_unique_address]]` applied to +// it. Otherwise, the `[[no_unique_address]]` in the "`_NoUnique == true`" case +// would not have any effect. In the `false` case, the `__v` is not +// `[[no_unique_address]]`, so nullifies the effects of the "outer" +// `[[no_unique_address]]` regarding data layout. +// +// If we had a language feature, this class would basically be replaced by `[[no_unique_address(condition)]]`. +template +struct __conditional_no_unique_address; + +template +struct __conditional_no_unique_address { + template + _LIBCPP_HIDE_FROM_ABI constexpr explicit __conditional_no_unique_address(in_place_t, _Args&&... __args) + : __v(std::forward<_Args>(__args)...) {} + + template + _LIBCPP_HIDE_FROM_ABI constexpr explicit __conditional_no_unique_address( + __conditional_no_unique_address_invoke_tag, _Func&& __f, _Args&&... __args) + : __v(std::invoke(std::forward<_Func>(__f), std::forward<_Args>(__args)...)) {} + + _LIBCPP_NO_UNIQUE_ADDRESS _Tp __v; +}; + +template +struct __conditional_no_unique_address { + template + _LIBCPP_HIDE_FROM_ABI constexpr explicit __conditional_no_unique_address(in_place_t, _Args&&... __args) + : __v(std::forward<_Args>(__args)...) {} + + template + _LIBCPP_HIDE_FROM_ABI constexpr explicit __conditional_no_unique_address( + __conditional_no_unique_address_invoke_tag, _Func&& __f, _Args&&... __args) + : __v(std::invoke(std::forward<_Func>(__f), std::forward<_Args>(__args)...)) {} + + _Tp __v; +}; + +// This function returns whether the type `_Second` can be stuffed into the tail padding +// of the `_First` type if both of them are given `[[no_unique_address]]`. +template +inline constexpr bool __fits_in_tail_padding = []() { + struct __x { + _LIBCPP_NO_UNIQUE_ADDRESS _First __first; + _LIBCPP_NO_UNIQUE_ADDRESS _Second __second; + }; + return sizeof(__x) == sizeof(_First); +}(); + +// This class implements the storage used by `std::expected`. We have a few +// goals for this storage: +// 1. Whenever the underlying {_Tp | _Unex} combination has free bytes in its +// tail padding, we should reuse it to store the bool discriminator of the +// expected, so as to save space. +// 2. Whenever the `expected<_Tp, _Unex>` as a whole has free bytes in its tail +// padding, we should allow an object following the expected to be stored in +// its tail padding. +// 3. However, we never want a user object (say `X`) that would follow an +// `expected<_Tp, _Unex>` to be stored in the padding bytes of the +// underlying {_Tp | _Unex} union, if any. That is because we use +// `construct_at` on that union, which would end up overwriting the `X` +// member if it is stored in the tail padding of the union. +// +// To achieve this, `__expected_base`'s logic is implemented in an inner +// `__repr` class. `__expected_base` holds one `__repr` member which is +// conditionally `[[no_unique_address]]`. The `__repr` class holds the +// underlying {_Tp | _Unex} union and a boolean "has value" flag. +// +// Which one of the `__repr_`/`__union_` members is `[[no_unique_address]]` +// depends on whether the "has value" boolean fits into the tail padding of +// the underlying {_Tp | _Unex} union: +// +// - In case the "has value" bool fits into the tail padding of the union, the +// whole `__repr_` member is _not_ `[[no_unique_address]]` as it needs to be +// transparently replaced on `emplace()`/`swap()` etc. +// - In case the "has value" bool does not fit into the tail padding of the +// union, only the union member must be transparently replaced (therefore is +// _not_ `[[no_unique_address]]`) and the "has value" flag must be adjusted +// manually. +// +// This way, the member that is transparently replaced on mutating operations +// is never `[[no_unique_address]]`, satisfying the requirements from +// "[basic.life]" in the standard. +// +// Stripped away of all superfluous elements, the layout of `__expected_base` +// then looks like this: +// +// template +// class expected_base { +// union union_t { +// [[no_unique_address]] Tp val; +// [[no_unique_address]] Err unex; +// }; +// +// static constexpr bool put_flag_in_tail = fits_in_tail_padding; +// static constexpr bool allow_reusing_expected_tail_padding = !put_flag_in_tail; +// +// struct repr { +// private: +// // If "has value" fits into the tail, this should be +// // `[[no_unique_address]]`, otherwise not. +// [[no_unique_address]] conditional_no_unique_address< +// put_flag_in_tail, +// union_t>::type union_; +// [[no_unique_address]] bool has_val_; +// }; +// +// protected: +// // If "has value" fits into the tail, this must _not_ be +// // `[[no_unique_address]]` so that we fill out the +// // complete `expected` object. +// [[no_unique_address]] conditional_no_unique_address< +// allow_reusing_expected_tail_padding, +// repr>::type repr_; +// }; +// template -class expected { +class __expected_base { + // use named union because [[no_unique_address]] cannot be applied to an unnamed union, + // also guaranteed elision into a potentially-overlapping subobject is unsettled (and + // it's not clear that it's implementable, given that the function is allowed to clobber + // the tail padding) - see https://github.com/itanium-cxx-abi/cxx-abi/issues/107. + union __union_t { + _LIBCPP_HIDE_FROM_ABI constexpr __union_t(const __union_t&) = delete; + _LIBCPP_HIDE_FROM_ABI constexpr __union_t(const __union_t&) + requires(is_copy_constructible_v<_Tp> && is_copy_constructible_v<_Err> && + is_trivially_copy_constructible_v<_Tp> && is_trivially_copy_constructible_v<_Err>) + = default; + _LIBCPP_HIDE_FROM_ABI constexpr __union_t(__union_t&&) = delete; + _LIBCPP_HIDE_FROM_ABI constexpr __union_t(__union_t&&) + requires(is_move_constructible_v<_Tp> && is_move_constructible_v<_Err> && + is_trivially_move_constructible_v<_Tp> && is_trivially_move_constructible_v<_Err>) + = default; + _LIBCPP_HIDE_FROM_ABI constexpr __union_t& operator=(const __union_t&) = delete; + _LIBCPP_HIDE_FROM_ABI constexpr __union_t& operator=(__union_t&&) = delete; + + template + _LIBCPP_HIDE_FROM_ABI constexpr explicit __union_t(in_place_t, _Args&&... __args) + : __val_(std::forward<_Args>(__args)...) {} + + template + _LIBCPP_HIDE_FROM_ABI constexpr explicit __union_t(unexpect_t, _Args&&... __args) + : __unex_(std::forward<_Args>(__args)...) {} + + template + _LIBCPP_HIDE_FROM_ABI constexpr explicit __union_t( + std::__expected_construct_in_place_from_invoke_tag, _Func&& __f, _Args&&... __args) + : __val_(std::invoke(std::forward<_Func>(__f), std::forward<_Args>(__args)...)) {} + + template + _LIBCPP_HIDE_FROM_ABI constexpr explicit __union_t( + std::__expected_construct_unexpected_from_invoke_tag, _Func&& __f, _Args&&... __args) + : __unex_(std::invoke(std::forward<_Func>(__f), std::forward<_Args>(__args)...)) {} + + _LIBCPP_HIDE_FROM_ABI constexpr ~__union_t() + requires(is_trivially_destructible_v<_Tp> && is_trivially_destructible_v<_Err>) + = default; + + // __repr's destructor handles this + _LIBCPP_HIDE_FROM_ABI constexpr ~__union_t() {} + + _LIBCPP_NO_UNIQUE_ADDRESS _Tp __val_; + _LIBCPP_NO_UNIQUE_ADDRESS _Err __unex_; + }; + + static constexpr bool __put_flag_in_tail = __fits_in_tail_padding<__union_t, bool>; + static constexpr bool __allow_reusing_expected_tail_padding = !__put_flag_in_tail; + + struct __repr { + _LIBCPP_HIDE_FROM_ABI constexpr explicit __repr() = delete; + + template + _LIBCPP_HIDE_FROM_ABI constexpr explicit __repr(in_place_t __tag, _Args&&... __args) + : __union_(in_place, __tag, std::forward<_Args>(__args)...), __has_val_(true) {} + + template + _LIBCPP_HIDE_FROM_ABI constexpr explicit __repr(unexpect_t __tag, _Args&&... __args) + : __union_(in_place, __tag, std::forward<_Args>(__args)...), __has_val_(false) {} + + template + _LIBCPP_HIDE_FROM_ABI constexpr explicit __repr(std::__expected_construct_in_place_from_invoke_tag __tag, + _Args&&... __args) + : __union_(in_place, __tag, std::forward<_Args>(__args)...), __has_val_(true) {} + + template + _LIBCPP_HIDE_FROM_ABI constexpr explicit __repr(std::__expected_construct_unexpected_from_invoke_tag __tag, + _Args&&... __args) + : __union_(in_place, __tag, std::forward<_Args>(__args)...), __has_val_(false) {} + + // The return value of `__make_union` must be constructed in place in the + // `__v` member of `__union_`, relying on guaranteed copy elision. To do + // this, the `__conditional_no_unique_address_invoke_tag` constructor is + // called with a lambda that is immediately called inside + // `__conditional_no_unique_address`'s constructor. + template + _LIBCPP_HIDE_FROM_ABI constexpr explicit __repr(bool __has_val, _OtherUnion&& __other) + requires(__allow_reusing_expected_tail_padding) + : __union_(__conditional_no_unique_address_invoke_tag{}, + [&] { return __make_union(__has_val, std::forward<_OtherUnion>(__other)); }), + __has_val_(__has_val) {} + + _LIBCPP_HIDE_FROM_ABI constexpr __repr(const __repr&) = delete; + _LIBCPP_HIDE_FROM_ABI constexpr __repr(const __repr&) + requires(is_copy_constructible_v<_Tp> && is_copy_constructible_v<_Err> && + is_trivially_copy_constructible_v<_Tp> && is_trivially_copy_constructible_v<_Err>) + = default; + _LIBCPP_HIDE_FROM_ABI constexpr __repr(__repr&&) = delete; + _LIBCPP_HIDE_FROM_ABI constexpr __repr(__repr&&) + requires(is_move_constructible_v<_Tp> && is_move_constructible_v<_Err> && + is_trivially_move_constructible_v<_Tp> && is_trivially_move_constructible_v<_Err>) + = default; + + _LIBCPP_HIDE_FROM_ABI constexpr __repr& operator=(const __repr&) = delete; + _LIBCPP_HIDE_FROM_ABI constexpr __repr& operator=(__repr&&) = delete; + + _LIBCPP_HIDE_FROM_ABI constexpr ~__repr() + requires(is_trivially_destructible_v<_Tp> && is_trivially_destructible_v<_Err>) + = default; + + _LIBCPP_HIDE_FROM_ABI constexpr ~__repr() + requires(!is_trivially_destructible_v<_Tp> || !is_trivially_destructible_v<_Err>) + { + __destroy_union_member(); + } + + _LIBCPP_HIDE_FROM_ABI constexpr void __destroy_union() + requires(__allow_reusing_expected_tail_padding && + (is_trivially_destructible_v<_Tp> && is_trivially_destructible_v<_Err>)) + { + // Note: Since the destructor of the union is trivial, this does nothing + // except to end the lifetime of the union. + std::destroy_at(&__union_.__v); + } + + _LIBCPP_HIDE_FROM_ABI constexpr void __destroy_union() + requires(__allow_reusing_expected_tail_padding && + (!is_trivially_destructible_v<_Tp> || !is_trivially_destructible_v<_Err>)) + { + __destroy_union_member(); + std::destroy_at(&__union_.__v); + } + + template + _LIBCPP_HIDE_FROM_ABI constexpr void __construct_union(in_place_t, _Args&&... __args) + requires(__allow_reusing_expected_tail_padding) + { + std::construct_at(&__union_.__v, in_place, std::forward<_Args>(__args)...); + __has_val_ = true; + } + + template + _LIBCPP_HIDE_FROM_ABI constexpr void __construct_union(unexpect_t, _Args&&... __args) + requires(__allow_reusing_expected_tail_padding) + { + std::construct_at(&__union_.__v, unexpect, std::forward<_Args>(__args)...); + __has_val_ = false; + } + + private: + template + friend class __expected_base; + + _LIBCPP_HIDE_FROM_ABI constexpr void __destroy_union_member() + requires(!is_trivially_destructible_v<_Tp> || !is_trivially_destructible_v<_Err>) + { + if (__has_val_) { + std::destroy_at(std::addressof(__union_.__v.__val_)); + } else { + std::destroy_at(std::addressof(__union_.__v.__unex_)); + } + } + + template + _LIBCPP_HIDE_FROM_ABI static constexpr __union_t __make_union(bool __has_val, _OtherUnion&& __other) + requires(__allow_reusing_expected_tail_padding) + { + if (__has_val) + return __union_t(in_place, std::forward<_OtherUnion>(__other).__val_); + else + return __union_t(unexpect, std::forward<_OtherUnion>(__other).__unex_); + } + + _LIBCPP_NO_UNIQUE_ADDRESS __conditional_no_unique_address<__put_flag_in_tail, __union_t> __union_; + _LIBCPP_NO_UNIQUE_ADDRESS bool __has_val_; + }; + + template + _LIBCPP_HIDE_FROM_ABI static constexpr __repr __make_repr(bool __has_val, _OtherUnion&& __other) + requires(__put_flag_in_tail) + { + if (__has_val) + return __repr(in_place, std::forward<_OtherUnion>(__other).__val_); + else + return __repr(unexpect, std::forward<_OtherUnion>(__other).__unex_); + } + +protected: + template + _LIBCPP_HIDE_FROM_ABI constexpr explicit __expected_base(_Args&&... __args) + : __repr_(in_place, std::forward<_Args>(__args)...) {} + + // In case we copy/move construct from another `expected` we need to create + // our `expected` so that it either has a value or not, depending on the "has + // value" flag of the other `expected`. To do this without falling back on + // `std::construct_at` we rely on guaranteed copy elision using two helper + // functions `__make_repr` and `__make_union`. There have to be two since + // there are two data layouts with different members being + // `[[no_unique_address]]`. GCC (as of version 13) does not do guaranteed + // copy elision when initializing `[[no_unique_address]]` members. The two + // cases are: + // + // - `__make_repr`: This is used when the "has value" flag lives in the tail + // of the union. In this case, the `__repr` member is _not_ + // `[[no_unique_address]]`. + // - `__make_union`: When the "has value" flag does _not_ fit in the tail of + // the union, the `__repr` member is `[[no_unique_address]]` and the union + // is not. + // + // This constructor "catches" the first case and leaves the second case to + // `__union_t`, its constructors and `__make_union`. + template + _LIBCPP_HIDE_FROM_ABI constexpr explicit __expected_base(bool __has_val, _OtherUnion&& __other) + requires(__put_flag_in_tail) + : __repr_(__conditional_no_unique_address_invoke_tag{}, + [&] { return __make_repr(__has_val, std::forward<_OtherUnion>(__other)); }) {} + + _LIBCPP_HIDE_FROM_ABI constexpr void __destroy() { + if constexpr (__put_flag_in_tail) + std::destroy_at(&__repr_.__v); + else + __repr_.__v.__destroy_union(); + } + + template + _LIBCPP_HIDE_FROM_ABI constexpr void __construct(_Tag __tag, _Args&&... __args) { + if constexpr (__put_flag_in_tail) + std::construct_at(&__repr_.__v, __tag, std::forward<_Args>(__args)...); + else + __repr_.__v.__construct_union(__tag, std::forward<_Args>(__args)...); + } + + _LIBCPP_HIDE_FROM_ABI constexpr bool __has_val() const { return __repr_.__v.__has_val_; } + _LIBCPP_HIDE_FROM_ABI constexpr __union_t& __union() { return __repr_.__v.__union_.__v; } + _LIBCPP_HIDE_FROM_ABI constexpr const __union_t& __union() const { return __repr_.__v.__union_.__v; } + _LIBCPP_HIDE_FROM_ABI constexpr _Tp& __val() { return __repr_.__v.__union_.__v.__val_; } + _LIBCPP_HIDE_FROM_ABI constexpr const _Tp& __val() const { return __repr_.__v.__union_.__v.__val_; } + _LIBCPP_HIDE_FROM_ABI constexpr _Err& __unex() { return __repr_.__v.__union_.__v.__unex_; } + _LIBCPP_HIDE_FROM_ABI constexpr const _Err& __unex() const { return __repr_.__v.__union_.__v.__unex_; } + +private: + _LIBCPP_NO_UNIQUE_ADDRESS __conditional_no_unique_address<__allow_reusing_expected_tail_padding, __repr> __repr_; +}; + +template +class expected : private __expected_base<_Tp, _Err> { static_assert(!is_reference_v<_Tp> && !is_function_v<_Tp> && !is_same_v, in_place_t> && !is_same_v, unexpect_t> && !__is_std_unexpected>::value && __valid_std_unexpected<_Err>::value, @@ -102,6 +466,8 @@ class expected { template friend class expected; + using __base = __expected_base<_Tp, _Err>; + public: using value_type = _Tp; using error_type = _Err; @@ -113,7 +479,7 @@ public: // [expected.object.ctor], constructors _LIBCPP_HIDE_FROM_ABI constexpr expected() noexcept(is_nothrow_default_constructible_v<_Tp>) // strengthened requires is_default_constructible_v<_Tp> - : __union_(std::in_place), __has_val_(true) {} + : __base(in_place) {} _LIBCPP_HIDE_FROM_ABI constexpr expected(const expected&) = delete; @@ -126,7 +492,7 @@ public: is_nothrow_copy_constructible_v<_Tp> && is_nothrow_copy_constructible_v<_Err>) // strengthened requires(is_copy_constructible_v<_Tp> && is_copy_constructible_v<_Err> && !(is_trivially_copy_constructible_v<_Tp> && is_trivially_copy_constructible_v<_Err>)) - : __union_(__other.__has_val_, __other.__union_), __has_val_(__other.__has_val_) {} + : __base(__other.__has_val(), __other.__union()) {} _LIBCPP_HIDE_FROM_ABI constexpr expected(expected&&) requires(is_move_constructible_v<_Tp> && is_move_constructible_v<_Err> && is_trivially_move_constructible_v<_Tp> && @@ -137,7 +503,7 @@ public: is_nothrow_move_constructible_v<_Tp> && is_nothrow_move_constructible_v<_Err>) requires(is_move_constructible_v<_Tp> && is_move_constructible_v<_Err> && !(is_trivially_move_constructible_v<_Tp> && is_trivially_move_constructible_v<_Err>)) - : __union_(__other.__has_val_, std::move(__other.__union_)), __has_val_(__other.__has_val_) {} + : __base(__other.__has_val(), std::move(__other.__union())) {} private: template @@ -162,12 +528,12 @@ private: template _LIBCPP_HIDE_FROM_ABI constexpr explicit expected( std::__expected_construct_in_place_from_invoke_tag __tag, _Func&& __f, _Args&&... __args) - : __union_(__tag, std::forward<_Func>(__f), std::forward<_Args>(__args)...), __has_val_(true) {} + : __base(__tag, std::forward<_Func>(__f), std::forward<_Args>(__args)...) {} template _LIBCPP_HIDE_FROM_ABI constexpr explicit expected( std::__expected_construct_unexpected_from_invoke_tag __tag, _Func&& __f, _Args&&... __args) - : __union_(__tag, std::forward<_Func>(__f), std::forward<_Args>(__args)...), __has_val_(false) {} + : __base(__tag, std::forward<_Func>(__f), std::forward<_Args>(__args)...) {} public: template @@ -177,14 +543,14 @@ public: expected(const expected<_Up, _OtherErr>& __other) noexcept( is_nothrow_constructible_v<_Tp, const _Up&> && is_nothrow_constructible_v<_Err, const _OtherErr&>) // strengthened - : __union_(__other.__has_val_, __other.__union_), __has_val_(__other.__has_val_) {} + : __base(__other.__has_val(), __other.__union()) {} template requires __can_convert<_Up, _OtherErr, _Up, _OtherErr>::value _LIBCPP_HIDE_FROM_ABI constexpr explicit(!is_convertible_v<_Up, _Tp> || !is_convertible_v<_OtherErr, _Err>) expected(expected<_Up, _OtherErr>&& __other) noexcept( is_nothrow_constructible_v<_Tp, _Up> && is_nothrow_constructible_v<_Err, _OtherErr>) // strengthened - : __union_(__other.__has_val_, std::move(__other.__union_)), __has_val_(__other.__has_val_) {} + : __base(__other.__has_val(), std::move(__other.__union())) {} template requires(!is_same_v, in_place_t> && !is_same_v> && @@ -192,80 +558,67 @@ public: (!is_same_v, bool> || !__is_std_expected>::value)) _LIBCPP_HIDE_FROM_ABI constexpr explicit(!is_convertible_v<_Up, _Tp>) expected(_Up&& __u) noexcept(is_nothrow_constructible_v<_Tp, _Up>) // strengthened - : __union_(std::in_place, std::forward<_Up>(__u)), __has_val_(true) {} + : __base(in_place, std::forward<_Up>(__u)) {} template requires is_constructible_v<_Err, const _OtherErr&> _LIBCPP_HIDE_FROM_ABI constexpr explicit(!is_convertible_v) expected( const unexpected<_OtherErr>& __unex) noexcept(is_nothrow_constructible_v<_Err, const _OtherErr&>) // strengthened - : __union_(std::unexpect, __unex.error()), __has_val_(false) {} + : __base(unexpect, __unex.error()) {} template requires is_constructible_v<_Err, _OtherErr> _LIBCPP_HIDE_FROM_ABI constexpr explicit(!is_convertible_v<_OtherErr, _Err>) expected(unexpected<_OtherErr>&& __unex) noexcept(is_nothrow_constructible_v<_Err, _OtherErr>) // strengthened - : __union_(std::unexpect, std::move(__unex.error())), __has_val_(false) {} + : __base(unexpect, std::move(__unex.error())) {} template requires is_constructible_v<_Tp, _Args...> _LIBCPP_HIDE_FROM_ABI constexpr explicit expected(in_place_t, _Args&&... __args) noexcept( is_nothrow_constructible_v<_Tp, _Args...>) // strengthened - : __union_(std::in_place, std::forward<_Args>(__args)...), __has_val_(true) {} + : __base(in_place, std::forward<_Args>(__args)...) {} template requires is_constructible_v< _Tp, initializer_list<_Up>&, _Args... > _LIBCPP_HIDE_FROM_ABI constexpr explicit expected(in_place_t, initializer_list<_Up> __il, _Args&&... __args) noexcept( is_nothrow_constructible_v<_Tp, initializer_list<_Up>&, _Args...>) // strengthened - : __union_(std::in_place, __il, std::forward<_Args>(__args)...), __has_val_(true) {} + : __base(in_place, __il, std::forward<_Args>(__args)...) {} template requires is_constructible_v<_Err, _Args...> _LIBCPP_HIDE_FROM_ABI constexpr explicit expected(unexpect_t, _Args&&... __args) noexcept( is_nothrow_constructible_v<_Err, _Args...>) // strengthened - : __union_(std::unexpect, std::forward<_Args>(__args)...), __has_val_(false) {} + : __base(unexpect, std::forward<_Args>(__args)...) {} template requires is_constructible_v< _Err, initializer_list<_Up>&, _Args... > _LIBCPP_HIDE_FROM_ABI constexpr explicit expected(unexpect_t, initializer_list<_Up> __il, _Args&&... __args) noexcept( is_nothrow_constructible_v<_Err, initializer_list<_Up>&, _Args...>) // strengthened - : __union_(std::unexpect, __il, std::forward<_Args>(__args)...), __has_val_(false) {} + : __base(unexpect, __il, std::forward<_Args>(__args)...) {} // [expected.object.dtor], destructor - _LIBCPP_HIDE_FROM_ABI constexpr ~expected() - requires(is_trivially_destructible_v<_Tp> && is_trivially_destructible_v<_Err>) - = default; - - _LIBCPP_HIDE_FROM_ABI constexpr ~expected() - requires(!is_trivially_destructible_v<_Tp> || !is_trivially_destructible_v<_Err>) - { - if (__has_val_) { - std::destroy_at(std::addressof(__union_.__val_)); - } else { - std::destroy_at(std::addressof(__union_.__unex_)); - } - } + _LIBCPP_HIDE_FROM_ABI constexpr ~expected() = default; private: - template - _LIBCPP_HIDE_FROM_ABI static constexpr void __reinit_expected(_T1& __newval, _T2& __oldval, _Args&&... __args) { + template + _LIBCPP_HIDE_FROM_ABI constexpr void __reinit_expected(_T2& __oldval, _Args&&... __args) { if constexpr (is_nothrow_constructible_v<_T1, _Args...>) { - std::destroy_at(std::addressof(__oldval)); - std::construct_at(std::addressof(__newval), std::forward<_Args>(__args)...); + this->__destroy(); + this->__construct(_Tag{}, std::forward<_Args>(__args)...); } else if constexpr (is_nothrow_move_constructible_v<_T1>) { _T1 __tmp(std::forward<_Args>(__args)...); - std::destroy_at(std::addressof(__oldval)); - std::construct_at(std::addressof(__newval), std::move(__tmp)); + this->__destroy(); + this->__construct(_Tag{}, std::move(__tmp)); } else { static_assert( is_nothrow_move_constructible_v<_T2>, "To provide strong exception guarantee, T2 has to satisfy `is_nothrow_move_constructible_v` so that it can " "be reverted to the previous state in case an exception is thrown during the assignment."); _T2 __tmp(std::move(__oldval)); - std::destroy_at(std::addressof(__oldval)); - auto __trans = - std::__make_exception_guard([&] { std::construct_at(std::addressof(__oldval), std::move(__tmp)); }); - std::construct_at(std::addressof(__newval), std::forward<_Args>(__args)...); + this->__destroy(); + auto __trans = std::__make_exception_guard([&] { this->__construct(_OtherTag{}, std::move(__tmp)); }); + this->__construct(_Tag{}, std::forward<_Args>(__args)...); __trans.__complete(); } } @@ -281,17 +634,15 @@ public: is_copy_constructible_v<_Err> && (is_nothrow_move_constructible_v<_Tp> || is_nothrow_move_constructible_v<_Err>)) { - if (__has_val_ && __rhs.__has_val_) { - __union_.__val_ = __rhs.__union_.__val_; - } else if (__has_val_) { - __reinit_expected(__union_.__unex_, __union_.__val_, __rhs.__union_.__unex_); - } else if (__rhs.__has_val_) { - __reinit_expected(__union_.__val_, __union_.__unex_, __rhs.__union_.__val_); + if (this->__has_val() && __rhs.__has_val()) { + this->__val() = __rhs.__val(); + } else if (this->__has_val()) { + __reinit_expected(this->__val(), __rhs.__unex()); + } else if (__rhs.__has_val()) { + __reinit_expected(this->__unex(), __rhs.__val()); } else { - __union_.__unex_ = __rhs.__union_.__unex_; + this->__unex() = __rhs.__unex(); } - // note: only reached if no exception+rollback was done inside __reinit_expected - __has_val_ = __rhs.__has_val_; return *this; } @@ -302,17 +653,15 @@ public: is_move_assignable_v<_Err> && (is_nothrow_move_constructible_v<_Tp> || is_nothrow_move_constructible_v<_Err>)) { - if (__has_val_ && __rhs.__has_val_) { - __union_.__val_ = std::move(__rhs.__union_.__val_); - } else if (__has_val_) { - __reinit_expected(__union_.__unex_, __union_.__val_, std::move(__rhs.__union_.__unex_)); - } else if (__rhs.__has_val_) { - __reinit_expected(__union_.__val_, __union_.__unex_, std::move(__rhs.__union_.__val_)); + if (this->__has_val() && __rhs.__has_val()) { + this->__val() = std::move(__rhs.__val()); + } else if (this->__has_val()) { + __reinit_expected(this->__val(), std::move(__rhs.__unex())); + } else if (__rhs.__has_val()) { + __reinit_expected(this->__unex(), std::move(__rhs.__val())); } else { - __union_.__unex_ = std::move(__rhs.__union_.__unex_); + this->__unex() = std::move(__rhs.__unex()); } - // note: only reached if no exception+rollback was done inside __reinit_expected - __has_val_ = __rhs.__has_val_; return *this; } @@ -323,11 +672,10 @@ public: (is_nothrow_constructible_v<_Tp, _Up> || is_nothrow_move_constructible_v<_Tp> || is_nothrow_move_constructible_v<_Err>)) { - if (__has_val_) { - __union_.__val_ = std::forward<_Up>(__v); + if (this->__has_val()) { + this->__val() = std::forward<_Up>(__v); } else { - __reinit_expected(__union_.__val_, __union_.__unex_, std::forward<_Up>(__v)); - __has_val_ = true; + __reinit_expected(this->__unex(), std::forward<_Up>(__v)); } return *this; } @@ -346,11 +694,10 @@ public: template requires(__can_assign_from_unexpected) _LIBCPP_HIDE_FROM_ABI constexpr expected& operator=(const unexpected<_OtherErr>& __un) { - if (__has_val_) { - __reinit_expected(__union_.__unex_, __union_.__val_, __un.error()); - __has_val_ = false; + if (this->__has_val()) { + __reinit_expected(this->__val(), __un.error()); } else { - __union_.__unex_ = __un.error(); + this->__unex() = __un.error(); } return *this; } @@ -358,11 +705,10 @@ public: template requires(__can_assign_from_unexpected<_OtherErr>) _LIBCPP_HIDE_FROM_ABI constexpr expected& operator=(unexpected<_OtherErr>&& __un) { - if (__has_val_) { - __reinit_expected(__union_.__unex_, __union_.__val_, std::move(__un.error())); - __has_val_ = false; + if (this->__has_val()) { + __reinit_expected(this->__val(), std::move(__un.error())); } else { - __union_.__unex_ = std::move(__un.error()); + this->__unex() = std::move(__un.error()); } return *this; } @@ -370,27 +716,17 @@ public: template requires is_nothrow_constructible_v<_Tp, _Args...> _LIBCPP_HIDE_FROM_ABI constexpr _Tp& emplace(_Args&&... __args) noexcept { - if (__has_val_) { - std::destroy_at(std::addressof(__union_.__val_)); - } else { - std::destroy_at(std::addressof(__union_.__unex_)); - } - std::construct_at(std::addressof(__union_.__val_), std::forward<_Args>(__args)...); - __has_val_ = true; - return __union_.__val_; + this->__destroy(); + this->__construct(in_place, std::forward<_Args>(__args)...); + return this->__val(); } template - requires is_nothrow_constructible_v< _Tp, initializer_list<_Up>&, _Args... > + requires is_nothrow_constructible_v<_Tp, initializer_list<_Up>&, _Args...> _LIBCPP_HIDE_FROM_ABI constexpr _Tp& emplace(initializer_list<_Up> __il, _Args&&... __args) noexcept { - if (__has_val_) { - std::destroy_at(std::addressof(__union_.__val_)); - } else { - std::destroy_at(std::addressof(__union_.__unex_)); - } - std::construct_at(std::addressof(__union_.__val_), __il, std::forward<_Args>(__args)...); - __has_val_ = true; - return __union_.__val_; + this->__destroy(); + this->__construct(in_place, __il, std::forward<_Args>(__args)...); + return this->__val(); } public: @@ -402,48 +738,42 @@ public: is_move_constructible_v<_Err> && (is_nothrow_move_constructible_v<_Tp> || is_nothrow_move_constructible_v<_Err>)) { - auto __swap_val_unex_impl = [&](expected& __with_val, expected& __with_err) { + auto __swap_val_unex_impl = [](expected& __with_val, expected& __with_err) { if constexpr (is_nothrow_move_constructible_v<_Err>) { - _Err __tmp(std::move(__with_err.__union_.__unex_)); - std::destroy_at(std::addressof(__with_err.__union_.__unex_)); - auto __trans = std::__make_exception_guard([&] { - std::construct_at(std::addressof(__with_err.__union_.__unex_), std::move(__tmp)); - }); - std::construct_at(std::addressof(__with_err.__union_.__val_), std::move(__with_val.__union_.__val_)); + _Err __tmp(std::move(__with_err.__unex())); + __with_err.__destroy(); + auto __trans = std::__make_exception_guard([&] { __with_err.__construct(unexpect, std::move(__tmp)); }); + __with_err.__construct(in_place, std::move(__with_val.__val())); __trans.__complete(); - std::destroy_at(std::addressof(__with_val.__union_.__val_)); - std::construct_at(std::addressof(__with_val.__union_.__unex_), std::move(__tmp)); + __with_val.__destroy(); + __with_val.__construct(unexpect, std::move(__tmp)); } else { static_assert(is_nothrow_move_constructible_v<_Tp>, "To provide strong exception guarantee, Tp has to satisfy `is_nothrow_move_constructible_v` so " "that it can be reverted to the previous state in case an exception is thrown during swap."); - _Tp __tmp(std::move(__with_val.__union_.__val_)); - std::destroy_at(std::addressof(__with_val.__union_.__val_)); - auto __trans = std::__make_exception_guard([&] { - std::construct_at(std::addressof(__with_val.__union_.__val_), std::move(__tmp)); - }); - std::construct_at(std::addressof(__with_val.__union_.__unex_), std::move(__with_err.__union_.__unex_)); + _Tp __tmp(std::move(__with_val.__val())); + __with_val.__destroy(); + auto __trans = std::__make_exception_guard([&] { __with_val.__construct(in_place, std::move(__tmp)); }); + __with_val.__construct(unexpect, std::move(__with_err.__unex())); __trans.__complete(); - std::destroy_at(std::addressof(__with_err.__union_.__unex_)); - std::construct_at(std::addressof(__with_err.__union_.__val_), std::move(__tmp)); + __with_err.__destroy(); + __with_err.__construct(in_place, std::move(__tmp)); } - __with_val.__has_val_ = false; - __with_err.__has_val_ = true; }; - if (__has_val_) { - if (__rhs.__has_val_) { + if (this->__has_val()) { + if (__rhs.__has_val()) { using std::swap; - swap(__union_.__val_, __rhs.__union_.__val_); + swap(this->__val(), __rhs.__val()); } else { __swap_val_unex_impl(*this, __rhs); } } else { - if (__rhs.__has_val_) { + if (__rhs.__has_val()) { __swap_val_unex_impl(__rhs, *this); } else { using std::swap; - swap(__union_.__unex_, __rhs.__union_.__unex_); + swap(this->__unex(), __rhs.__unex()); } } } @@ -456,105 +786,115 @@ public: // [expected.object.obs], observers _LIBCPP_HIDE_FROM_ABI constexpr const _Tp* operator->() const noexcept { - _LIBCPP_ASSERT_VALID_ELEMENT_ACCESS(__has_val_, "expected::operator-> requires the expected to contain a value"); - return std::addressof(__union_.__val_); + _LIBCPP_ASSERT_VALID_ELEMENT_ACCESS( + this->__has_val(), "expected::operator-> requires the expected to contain a value"); + return std::addressof(this->__val()); } _LIBCPP_HIDE_FROM_ABI constexpr _Tp* operator->() noexcept { - _LIBCPP_ASSERT_VALID_ELEMENT_ACCESS(__has_val_, "expected::operator-> requires the expected to contain a value"); - return std::addressof(__union_.__val_); + _LIBCPP_ASSERT_VALID_ELEMENT_ACCESS( + this->__has_val(), "expected::operator-> requires the expected to contain a value"); + return std::addressof(this->__val()); } _LIBCPP_HIDE_FROM_ABI constexpr const _Tp& operator*() const& noexcept { - _LIBCPP_ASSERT_VALID_ELEMENT_ACCESS(__has_val_, "expected::operator* requires the expected to contain a value"); - return __union_.__val_; + _LIBCPP_ASSERT_VALID_ELEMENT_ACCESS( + this->__has_val(), "expected::operator* requires the expected to contain a value"); + return this->__val(); } _LIBCPP_HIDE_FROM_ABI constexpr _Tp& operator*() & noexcept { - _LIBCPP_ASSERT_VALID_ELEMENT_ACCESS(__has_val_, "expected::operator* requires the expected to contain a value"); - return __union_.__val_; + _LIBCPP_ASSERT_VALID_ELEMENT_ACCESS( + this->__has_val(), "expected::operator* requires the expected to contain a value"); + return this->__val(); } _LIBCPP_HIDE_FROM_ABI constexpr const _Tp&& operator*() const&& noexcept { - _LIBCPP_ASSERT_VALID_ELEMENT_ACCESS(__has_val_, "expected::operator* requires the expected to contain a value"); - return std::move(__union_.__val_); + _LIBCPP_ASSERT_VALID_ELEMENT_ACCESS( + this->__has_val(), "expected::operator* requires the expected to contain a value"); + return std::move(this->__val()); } _LIBCPP_HIDE_FROM_ABI constexpr _Tp&& operator*() && noexcept { - _LIBCPP_ASSERT_VALID_ELEMENT_ACCESS(__has_val_, "expected::operator* requires the expected to contain a value"); - return std::move(__union_.__val_); + _LIBCPP_ASSERT_VALID_ELEMENT_ACCESS( + this->__has_val(), "expected::operator* requires the expected to contain a value"); + return std::move(this->__val()); } - _LIBCPP_HIDE_FROM_ABI constexpr explicit operator bool() const noexcept { return __has_val_; } + _LIBCPP_HIDE_FROM_ABI constexpr explicit operator bool() const noexcept { return this->__has_val(); } - _LIBCPP_HIDE_FROM_ABI constexpr bool has_value() const noexcept { return __has_val_; } + _LIBCPP_HIDE_FROM_ABI constexpr bool has_value() const noexcept { return this->__has_val(); } _LIBCPP_HIDE_FROM_ABI constexpr const _Tp& value() const& { static_assert(is_copy_constructible_v<_Err>, "error_type has to be copy constructible"); - if (!__has_val_) { + if (!this->__has_val()) { std::__throw_bad_expected_access<_Err>(std::as_const(error())); } - return __union_.__val_; + return this->__val(); } _LIBCPP_HIDE_FROM_ABI constexpr _Tp& value() & { static_assert(is_copy_constructible_v<_Err>, "error_type has to be copy constructible"); - if (!__has_val_) { + if (!this->__has_val()) { std::__throw_bad_expected_access<_Err>(std::as_const(error())); } - return __union_.__val_; + return this->__val(); } _LIBCPP_HIDE_FROM_ABI constexpr const _Tp&& value() const&& { static_assert(is_copy_constructible_v<_Err> && is_constructible_v<_Err, decltype(std::move(error()))>, "error_type has to be both copy constructible and constructible from decltype(std::move(error()))"); - if (!__has_val_) { + if (!this->__has_val()) { std::__throw_bad_expected_access<_Err>(std::move(error())); } - return std::move(__union_.__val_); + return std::move(this->__val()); } _LIBCPP_HIDE_FROM_ABI constexpr _Tp&& value() && { static_assert(is_copy_constructible_v<_Err> && is_constructible_v<_Err, decltype(std::move(error()))>, "error_type has to be both copy constructible and constructible from decltype(std::move(error()))"); - if (!__has_val_) { + if (!this->__has_val()) { std::__throw_bad_expected_access<_Err>(std::move(error())); } - return std::move(__union_.__val_); + return std::move(this->__val()); } _LIBCPP_HIDE_FROM_ABI constexpr const _Err& error() const& noexcept { - _LIBCPP_ASSERT_VALID_ELEMENT_ACCESS(!__has_val_, "expected::error requires the expected to contain an error"); - return __union_.__unex_; + _LIBCPP_ASSERT_VALID_ELEMENT_ACCESS( + !this->__has_val(), "expected::error requires the expected to contain an error"); + return this->__unex(); } _LIBCPP_HIDE_FROM_ABI constexpr _Err& error() & noexcept { - _LIBCPP_ASSERT_VALID_ELEMENT_ACCESS(!__has_val_, "expected::error requires the expected to contain an error"); - return __union_.__unex_; + _LIBCPP_ASSERT_VALID_ELEMENT_ACCESS( + !this->__has_val(), "expected::error requires the expected to contain an error"); + return this->__unex(); } _LIBCPP_HIDE_FROM_ABI constexpr const _Err&& error() const&& noexcept { - _LIBCPP_ASSERT_VALID_ELEMENT_ACCESS(!__has_val_, "expected::error requires the expected to contain an error"); - return std::move(__union_.__unex_); + _LIBCPP_ASSERT_VALID_ELEMENT_ACCESS( + !this->__has_val(), "expected::error requires the expected to contain an error"); + return std::move(this->__unex()); } _LIBCPP_HIDE_FROM_ABI constexpr _Err&& error() && noexcept { - _LIBCPP_ASSERT_VALID_ELEMENT_ACCESS(!__has_val_, "expected::error requires the expected to contain an error"); - return std::move(__union_.__unex_); + _LIBCPP_ASSERT_VALID_ELEMENT_ACCESS( + !this->__has_val(), "expected::error requires the expected to contain an error"); + return std::move(this->__unex()); } template _LIBCPP_HIDE_FROM_ABI constexpr _Tp value_or(_Up&& __v) const& { static_assert(is_copy_constructible_v<_Tp>, "value_type has to be copy constructible"); static_assert(is_convertible_v<_Up, _Tp>, "argument has to be convertible to value_type"); - return __has_val_ ? __union_.__val_ : static_cast<_Tp>(std::forward<_Up>(__v)); + return this->__has_val() ? this->__val() : static_cast<_Tp>(std::forward<_Up>(__v)); } template _LIBCPP_HIDE_FROM_ABI constexpr _Tp value_or(_Up&& __v) && { static_assert(is_move_constructible_v<_Tp>, "value_type has to be move constructible"); static_assert(is_convertible_v<_Up, _Tp>, "argument has to be convertible to value_type"); - return __has_val_ ? std::move(__union_.__val_) : static_cast<_Tp>(std::forward<_Up>(__v)); + return this->__has_val() ? std::move(this->__val()) : static_cast<_Tp>(std::forward<_Up>(__v)); } template @@ -584,7 +924,7 @@ public: static_assert(is_same_v, "The result of f(**this) must have the same error_type as this expected"); if (has_value()) { - return std::invoke(std::forward<_Func>(__f), __union_.__val_); + return std::invoke(std::forward<_Func>(__f), this->__val()); } return _Up(unexpect, error()); } @@ -597,7 +937,7 @@ public: static_assert(is_same_v, "The result of f(**this) must have the same error_type as this expected"); if (has_value()) { - return std::invoke(std::forward<_Func>(__f), __union_.__val_); + return std::invoke(std::forward<_Func>(__f), this->__val()); } return _Up(unexpect, error()); } @@ -611,7 +951,7 @@ public: static_assert(is_same_v, "The result of f(std::move(**this)) must have the same error_type as this expected"); if (has_value()) { - return std::invoke(std::forward<_Func>(__f), std::move(__union_.__val_)); + return std::invoke(std::forward<_Func>(__f), std::move(this->__val())); } return _Up(unexpect, std::move(error())); } @@ -625,7 +965,7 @@ public: static_assert(is_same_v, "The result of f(std::move(**this)) must have the same error_type as this expected"); if (has_value()) { - return std::invoke(std::forward<_Func>(__f), std::move(__union_.__val_)); + return std::invoke(std::forward<_Func>(__f), std::move(this->__val())); } return _Up(unexpect, std::move(error())); } @@ -638,7 +978,7 @@ public: static_assert(is_same_v, "The result of f(error()) must have the same value_type as this expected"); if (has_value()) { - return _Gp(in_place, __union_.__val_); + return _Gp(in_place, this->__val()); } return std::invoke(std::forward<_Func>(__f), error()); } @@ -651,7 +991,7 @@ public: static_assert(is_same_v, "The result of f(error()) must have the same value_type as this expected"); if (has_value()) { - return _Gp(in_place, __union_.__val_); + return _Gp(in_place, this->__val()); } return std::invoke(std::forward<_Func>(__f), error()); } @@ -665,7 +1005,7 @@ public: static_assert(is_same_v, "The result of f(std::move(error())) must have the same value_type as this expected"); if (has_value()) { - return _Gp(in_place, std::move(__union_.__val_)); + return _Gp(in_place, std::move(this->__val())); } return std::invoke(std::forward<_Func>(__f), std::move(error())); } @@ -679,7 +1019,7 @@ public: static_assert(is_same_v, "The result of f(std::move(error())) must have the same value_type as this expected"); if (has_value()) { - return _Gp(in_place, std::move(__union_.__val_)); + return _Gp(in_place, std::move(this->__val())); } return std::invoke(std::forward<_Func>(__f), std::move(error())); } @@ -693,9 +1033,9 @@ public: } if constexpr (!is_void_v<_Up>) { return expected<_Up, _Err>( - __expected_construct_in_place_from_invoke_tag{}, std::forward<_Func>(__f), __union_.__val_); + __expected_construct_in_place_from_invoke_tag{}, std::forward<_Func>(__f), this->__val()); } else { - std::invoke(std::forward<_Func>(__f), __union_.__val_); + std::invoke(std::forward<_Func>(__f), this->__val()); return expected<_Up, _Err>(); } } @@ -709,9 +1049,9 @@ public: } if constexpr (!is_void_v<_Up>) { return expected<_Up, _Err>( - __expected_construct_in_place_from_invoke_tag{}, std::forward<_Func>(__f), __union_.__val_); + __expected_construct_in_place_from_invoke_tag{}, std::forward<_Func>(__f), this->__val()); } else { - std::invoke(std::forward<_Func>(__f), __union_.__val_); + std::invoke(std::forward<_Func>(__f), this->__val()); return expected<_Up, _Err>(); } } @@ -725,9 +1065,9 @@ public: } if constexpr (!is_void_v<_Up>) { return expected<_Up, _Err>( - __expected_construct_in_place_from_invoke_tag{}, std::forward<_Func>(__f), std::move(__union_.__val_)); + __expected_construct_in_place_from_invoke_tag{}, std::forward<_Func>(__f), std::move(this->__val())); } else { - std::invoke(std::forward<_Func>(__f), std::move(__union_.__val_)); + std::invoke(std::forward<_Func>(__f), std::move(this->__val())); return expected<_Up, _Err>(); } } @@ -741,9 +1081,9 @@ public: } if constexpr (!is_void_v<_Up>) { return expected<_Up, _Err>( - __expected_construct_in_place_from_invoke_tag{}, std::forward<_Func>(__f), std::move(__union_.__val_)); + __expected_construct_in_place_from_invoke_tag{}, std::forward<_Func>(__f), std::move(this->__val())); } else { - std::invoke(std::forward<_Func>(__f), std::move(__union_.__val_)); + std::invoke(std::forward<_Func>(__f), std::move(this->__val())); return expected<_Up, _Err>(); } } @@ -755,7 +1095,7 @@ public: static_assert(__valid_std_unexpected<_Gp>::value, "The result of f(error()) must be a valid template argument for unexpected"); if (has_value()) { - return expected<_Tp, _Gp>(in_place, __union_.__val_); + return expected<_Tp, _Gp>(in_place, this->__val()); } return expected<_Tp, _Gp>(__expected_construct_unexpected_from_invoke_tag{}, std::forward<_Func>(__f), error()); } @@ -767,7 +1107,7 @@ public: static_assert(__valid_std_unexpected<_Gp>::value, "The result of f(error()) must be a valid template argument for unexpected"); if (has_value()) { - return expected<_Tp, _Gp>(in_place, __union_.__val_); + return expected<_Tp, _Gp>(in_place, this->__val()); } return expected<_Tp, _Gp>(__expected_construct_unexpected_from_invoke_tag{}, std::forward<_Func>(__f), error()); } @@ -779,7 +1119,7 @@ public: static_assert(__valid_std_unexpected<_Gp>::value, "The result of f(std::move(error())) must be a valid template argument for unexpected"); if (has_value()) { - return expected<_Tp, _Gp>(in_place, std::move(__union_.__val_)); + return expected<_Tp, _Gp>(in_place, std::move(this->__val())); } return expected<_Tp, _Gp>( __expected_construct_unexpected_from_invoke_tag{}, std::forward<_Func>(__f), std::move(error())); @@ -792,7 +1132,7 @@ public: static_assert(__valid_std_unexpected<_Gp>::value, "The result of f(std::move(error())) must be a valid template argument for unexpected"); if (has_value()) { - return expected<_Tp, _Gp>(in_place, std::move(__union_.__val_)); + return expected<_Tp, _Gp>(in_place, std::move(this->__val())); } return expected<_Tp, _Gp>( __expected_construct_unexpected_from_invoke_tag{}, std::forward<_Func>(__f), std::move(error())); @@ -802,123 +1142,220 @@ public: template requires(!is_void_v<_T2>) _LIBCPP_HIDE_FROM_ABI friend constexpr bool operator==(const expected& __x, const expected<_T2, _E2>& __y) { - if (__x.__has_val_ != __y.__has_val_) { + if (__x.__has_val() != __y.__has_val()) { return false; } else { - if (__x.__has_val_) { - return __x.__union_.__val_ == __y.__union_.__val_; + if (__x.__has_val()) { + return __x.__val() == __y.__val(); } else { - return __x.__union_.__unex_ == __y.__union_.__unex_; + return __x.__unex() == __y.__unex(); } } } template _LIBCPP_HIDE_FROM_ABI friend constexpr bool operator==(const expected& __x, const _T2& __v) { - return __x.__has_val_ && static_cast(__x.__union_.__val_ == __v); + return __x.__has_val() && static_cast(__x.__val() == __v); } template _LIBCPP_HIDE_FROM_ABI friend constexpr bool operator==(const expected& __x, const unexpected<_E2>& __e) { - return !__x.__has_val_ && static_cast(__x.__union_.__unex_ == __e.error()); + return !__x.__has_val() && static_cast(__x.__unex() == __e.error()); } +}; -private: - template - union __union_t { - template - _LIBCPP_HIDE_FROM_ABI constexpr explicit __union_t(std::in_place_t, _Args&&... __args) - : __val_(std::forward<_Args>(__args)...) {} - - template - _LIBCPP_HIDE_FROM_ABI constexpr explicit __union_t(std::unexpect_t, _Args&&... __args) - : __unex_(std::forward<_Args>(__args)...) {} - - template - _LIBCPP_HIDE_FROM_ABI constexpr explicit __union_t( - std::__expected_construct_in_place_from_invoke_tag, _Func&& __f, _Args&&... __args) - : __val_(std::invoke(std::forward<_Func>(__f), std::forward<_Args>(__args)...)) {} - - template - _LIBCPP_HIDE_FROM_ABI constexpr explicit __union_t( - std::__expected_construct_unexpected_from_invoke_tag, _Func&& __f, _Args&&... __args) - : __unex_(std::invoke(std::forward<_Func>(__f), std::forward<_Args>(__args)...)) {} - - template - _LIBCPP_HIDE_FROM_ABI constexpr explicit __union_t(bool __has_val, _Union&& __other) { - if (__has_val) - std::construct_at(std::addressof(__val_), std::forward<_Union>(__other).__val_); - else - std::construct_at(std::addressof(__unex_), std::forward<_Union>(__other).__unex_); - } - - _LIBCPP_HIDE_FROM_ABI constexpr ~__union_t() - requires(is_trivially_destructible_v<_ValueType> && is_trivially_destructible_v<_ErrorType>) - = default; - - // the expected's destructor handles this - _LIBCPP_HIDE_FROM_ABI constexpr ~__union_t() {} - - _ValueType __val_; - _ErrorType __unex_; - }; - +template +class __expected_void_base { + struct __empty_t {}; // use named union because [[no_unique_address]] cannot be applied to an unnamed union, // also guaranteed elision into a potentially-overlapping subobject is unsettled (and // it's not clear that it's implementable, given that the function is allowed to clobber // the tail padding) - see https://github.com/itanium-cxx-abi/cxx-abi/issues/107. - template - requires(is_trivially_move_constructible_v<_ValueType> && is_trivially_move_constructible_v<_ErrorType>) - union __union_t<_ValueType, _ErrorType> { - _LIBCPP_HIDE_FROM_ABI constexpr __union_t(const __union_t&) = default; - _LIBCPP_HIDE_FROM_ABI constexpr __union_t& operator=(const __union_t&) = default; + union __union_t { + _LIBCPP_HIDE_FROM_ABI constexpr __union_t(const __union_t&) = delete; + _LIBCPP_HIDE_FROM_ABI constexpr __union_t(const __union_t&) + requires(is_copy_constructible_v<_Err> && is_trivially_copy_constructible_v<_Err>) + = default; + _LIBCPP_HIDE_FROM_ABI constexpr __union_t(__union_t&&) = delete; + _LIBCPP_HIDE_FROM_ABI constexpr __union_t(__union_t&&) + requires(is_move_constructible_v<_Err> && is_trivially_move_constructible_v<_Err>) + = default; + _LIBCPP_HIDE_FROM_ABI constexpr __union_t& operator=(const __union_t&) = delete; + _LIBCPP_HIDE_FROM_ABI constexpr __union_t& operator=(__union_t&&) = delete; + + _LIBCPP_HIDE_FROM_ABI constexpr explicit __union_t(in_place_t) : __empty_() {} template - _LIBCPP_HIDE_FROM_ABI constexpr explicit __union_t(std::in_place_t, _Args&&... __args) - : __val_(std::forward<_Args>(__args)...) {} - - template - _LIBCPP_HIDE_FROM_ABI constexpr explicit __union_t(std::unexpect_t, _Args&&... __args) + _LIBCPP_HIDE_FROM_ABI constexpr explicit __union_t(unexpect_t, _Args&&... __args) : __unex_(std::forward<_Args>(__args)...) {} template _LIBCPP_HIDE_FROM_ABI constexpr explicit __union_t( - std::__expected_construct_in_place_from_invoke_tag, _Func&& __f, _Args&&... __args) - : __val_(std::invoke(std::forward<_Func>(__f), std::forward<_Args>(__args)...)) {} - - template - _LIBCPP_HIDE_FROM_ABI constexpr explicit __union_t( - std::__expected_construct_unexpected_from_invoke_tag, _Func&& __f, _Args&&... __args) + __expected_construct_unexpected_from_invoke_tag, _Func&& __f, _Args&&... __args) : __unex_(std::invoke(std::forward<_Func>(__f), std::forward<_Args>(__args)...)) {} - template - _LIBCPP_HIDE_FROM_ABI constexpr explicit __union_t(bool __has_val, _Union&& __other) { - if (__has_val) - std::construct_at(std::addressof(__val_), std::forward<_Union>(__other).__val_); - else - std::construct_at(std::addressof(__unex_), std::forward<_Union>(__other).__unex_); - } - _LIBCPP_HIDE_FROM_ABI constexpr ~__union_t() - requires(is_trivially_destructible_v<_ValueType> && is_trivially_destructible_v<_ErrorType>) + requires(is_trivially_destructible_v<_Err>) = default; - // the expected's destructor handles this + // __repr's destructor handles this _LIBCPP_HIDE_FROM_ABI constexpr ~__union_t() - requires(!is_trivially_destructible_v<_ValueType> || !is_trivially_destructible_v<_ErrorType>) + requires(!is_trivially_destructible_v<_Err>) {} - _LIBCPP_NO_UNIQUE_ADDRESS _ValueType __val_; - _LIBCPP_NO_UNIQUE_ADDRESS _ErrorType __unex_; + _LIBCPP_NO_UNIQUE_ADDRESS __empty_t __empty_; + _LIBCPP_NO_UNIQUE_ADDRESS _Err __unex_; }; - _LIBCPP_NO_UNIQUE_ADDRESS __union_t<_Tp, _Err> __union_; - bool __has_val_; + static constexpr bool __put_flag_in_tail = __fits_in_tail_padding<__union_t, bool>; + static constexpr bool __allow_reusing_expected_tail_padding = !__put_flag_in_tail; + + struct __repr { + _LIBCPP_HIDE_FROM_ABI constexpr explicit __repr() = delete; + + template + _LIBCPP_HIDE_FROM_ABI constexpr explicit __repr(in_place_t __tag) : __union_(in_place, __tag), __has_val_(true) {} + + template + _LIBCPP_HIDE_FROM_ABI constexpr explicit __repr(unexpect_t __tag, _Args&&... __args) + : __union_(in_place, __tag, std::forward<_Args>(__args)...), __has_val_(false) {} + + template + _LIBCPP_HIDE_FROM_ABI constexpr explicit __repr(std::__expected_construct_unexpected_from_invoke_tag __tag, + _Args&&... __args) + : __union_(in_place, __tag, std::forward<_Args>(__args)...), __has_val_(false) {} + + template + _LIBCPP_HIDE_FROM_ABI constexpr explicit __repr(bool __has_val, _OtherUnion&& __other) + requires(__allow_reusing_expected_tail_padding) + : __union_(__conditional_no_unique_address_invoke_tag{}, + [&] { return __make_union(__has_val, std::forward<_OtherUnion>(__other)); }), + __has_val_(__has_val) {} + + _LIBCPP_HIDE_FROM_ABI constexpr __repr(const __repr&) = delete; + _LIBCPP_HIDE_FROM_ABI constexpr __repr(const __repr&) + requires(is_copy_constructible_v<_Err> && is_trivially_copy_constructible_v<_Err>) + = default; + _LIBCPP_HIDE_FROM_ABI constexpr __repr(__repr&&) = delete; + _LIBCPP_HIDE_FROM_ABI constexpr __repr(__repr&&) + requires(is_move_constructible_v<_Err> && is_trivially_move_constructible_v<_Err>) + = default; + + _LIBCPP_HIDE_FROM_ABI constexpr __repr& operator=(const __repr&) = delete; + _LIBCPP_HIDE_FROM_ABI constexpr __repr& operator=(__repr&&) = delete; + + _LIBCPP_HIDE_FROM_ABI constexpr ~__repr() + requires(is_trivially_destructible_v<_Err>) + = default; + + _LIBCPP_HIDE_FROM_ABI constexpr ~__repr() + requires(!is_trivially_destructible_v<_Err>) + { + __destroy_union_member(); + } + + _LIBCPP_HIDE_FROM_ABI constexpr void __destroy_union() + requires(__allow_reusing_expected_tail_padding && is_trivially_destructible_v<_Err>) + { + std::destroy_at(&__union_.__v); + } + + _LIBCPP_HIDE_FROM_ABI constexpr void __destroy_union() + requires(__allow_reusing_expected_tail_padding && !is_trivially_destructible_v<_Err>) + { + __destroy_union_member(); + std::destroy_at(&__union_.__v); + } + + _LIBCPP_HIDE_FROM_ABI constexpr void __construct_union(in_place_t) + requires(__allow_reusing_expected_tail_padding) + { + std::construct_at(&__union_.__v, in_place); + __has_val_ = true; + } + + template + _LIBCPP_HIDE_FROM_ABI constexpr void __construct_union(unexpect_t, _Args&&... __args) + requires(__allow_reusing_expected_tail_padding) + { + std::construct_at(&__union_.__v, unexpect, std::forward<_Args>(__args)...); + __has_val_ = false; + } + + private: + template + friend class __expected_void_base; + + _LIBCPP_HIDE_FROM_ABI constexpr void __destroy_union_member() + requires(!is_trivially_destructible_v<_Err>) + { + if (!__has_val_) + std::destroy_at(std::addressof(__union_.__v.__unex_)); + } + + template + _LIBCPP_HIDE_FROM_ABI static constexpr __union_t __make_union(bool __has_val, _OtherUnion&& __other) + requires(__allow_reusing_expected_tail_padding) + { + if (__has_val) + return __union_t(in_place); + else + return __union_t(unexpect, std::forward<_OtherUnion>(__other).__unex_); + } + + _LIBCPP_NO_UNIQUE_ADDRESS __conditional_no_unique_address<__put_flag_in_tail, __union_t> __union_; + _LIBCPP_NO_UNIQUE_ADDRESS bool __has_val_; + }; + + template + _LIBCPP_HIDE_FROM_ABI static constexpr __repr __make_repr(bool __has_val, _OtherUnion&& __other) + requires(__put_flag_in_tail) + { + if (__has_val) + return __repr(in_place); + else + return __repr(unexpect, std::forward<_OtherUnion>(__other).__unex_); + } + +protected: + template + _LIBCPP_HIDE_FROM_ABI constexpr explicit __expected_void_base(_Args&&... __args) + : __repr_(in_place, std::forward<_Args>(__args)...) {} + + template + _LIBCPP_HIDE_FROM_ABI constexpr explicit __expected_void_base(bool __has_val, _OtherUnion&& __other) + requires(__put_flag_in_tail) + : __repr_(__conditional_no_unique_address_invoke_tag{}, + [&] { return __make_repr(__has_val, std::forward<_OtherUnion>(__other)); }) {} + + _LIBCPP_HIDE_FROM_ABI constexpr void __destroy() { + if constexpr (__put_flag_in_tail) + std::destroy_at(&__repr_.__v); + else + __repr_.__v.__destroy_union(); + } + + template + _LIBCPP_HIDE_FROM_ABI constexpr void __construct(_Tag __tag, _Args&&... __args) { + if constexpr (__put_flag_in_tail) + std::construct_at(&__repr_.__v, __tag, std::forward<_Args>(__args)...); + else + __repr_.__v.__construct_union(__tag, std::forward<_Args>(__args)...); + } + + _LIBCPP_HIDE_FROM_ABI constexpr bool __has_val() const { return __repr_.__v.__has_val_; } + _LIBCPP_HIDE_FROM_ABI constexpr __union_t& __union() { return __repr_.__v.__union_.__v; } + _LIBCPP_HIDE_FROM_ABI constexpr const __union_t& __union() const { return __repr_.__v.__union_.__v; } + _LIBCPP_HIDE_FROM_ABI constexpr _Err& __unex() { return __repr_.__v.__union_.__v.__unex_; } + _LIBCPP_HIDE_FROM_ABI constexpr const _Err& __unex() const { return __repr_.__v.__union_.__v.__unex_; } + +private: + _LIBCPP_NO_UNIQUE_ADDRESS __conditional_no_unique_address<__allow_reusing_expected_tail_padding, __repr> __repr_; }; template requires is_void_v<_Tp> -class expected<_Tp, _Err> { +class expected<_Tp, _Err> : private __expected_void_base<_Err> { static_assert(__valid_std_unexpected<_Err>::value, "[expected.void.general] A program that instantiates expected with a E that is not a " "valid argument for unexpected is ill-formed"); @@ -935,6 +1372,8 @@ class expected<_Tp, _Err> { _Not, const expected<_Up, _OtherErr>&>>, _Not, const expected<_Up, _OtherErr>>>>; + using __base = __expected_void_base<_Err>; + public: using value_type = _Tp; using error_type = _Err; @@ -944,7 +1383,7 @@ public: using rebind = expected<_Up, error_type>; // [expected.void.ctor], constructors - _LIBCPP_HIDE_FROM_ABI constexpr expected() noexcept : __has_val_(true) {} + _LIBCPP_HIDE_FROM_ABI constexpr expected() noexcept : __base(in_place) {} _LIBCPP_HIDE_FROM_ABI constexpr expected(const expected&) = delete; @@ -955,7 +1394,7 @@ public: _LIBCPP_HIDE_FROM_ABI constexpr expected(const expected& __rhs) noexcept( is_nothrow_copy_constructible_v<_Err>) // strengthened requires(is_copy_constructible_v<_Err> && !is_trivially_copy_constructible_v<_Err>) - : __union_(__rhs.__has_val_, __rhs.__union_), __has_val_(__rhs.__has_val_) {} + : __base(__rhs.__has_val(), __rhs.__union()) {} _LIBCPP_HIDE_FROM_ABI constexpr expected(expected&&) requires(is_move_constructible_v<_Err> && is_trivially_move_constructible_v<_Err>) @@ -963,93 +1402,93 @@ public: _LIBCPP_HIDE_FROM_ABI constexpr expected(expected&& __rhs) noexcept(is_nothrow_move_constructible_v<_Err>) requires(is_move_constructible_v<_Err> && !is_trivially_move_constructible_v<_Err>) - : __union_(__rhs.__has_val_, std::move(__rhs.__union_)), __has_val_(__rhs.__has_val_) {} + : __base(__rhs.__has_val(), std::move(__rhs.__union())) {} template requires __can_convert<_Up, _OtherErr, const _OtherErr&>::value _LIBCPP_HIDE_FROM_ABI constexpr explicit(!is_convertible_v) expected(const expected<_Up, _OtherErr>& __rhs) noexcept( is_nothrow_constructible_v<_Err, const _OtherErr&>) // strengthened - : __union_(__rhs.__has_val_, __rhs.__union_), __has_val_(__rhs.__has_val_) {} + : __base(__rhs.__has_val(), __rhs.__union()) {} template requires __can_convert<_Up, _OtherErr, _OtherErr>::value _LIBCPP_HIDE_FROM_ABI constexpr explicit(!is_convertible_v<_OtherErr, _Err>) expected(expected<_Up, _OtherErr>&& __rhs) noexcept(is_nothrow_constructible_v<_Err, _OtherErr>) // strengthened - : __union_(__rhs.__has_val_, std::move(__rhs.__union_)), __has_val_(__rhs.__has_val_) {} + : __base(__rhs.__has_val(), std::move(__rhs.__union())) {} template requires is_constructible_v<_Err, const _OtherErr&> _LIBCPP_HIDE_FROM_ABI constexpr explicit(!is_convertible_v) expected( const unexpected<_OtherErr>& __unex) noexcept(is_nothrow_constructible_v<_Err, const _OtherErr&>) // strengthened - : __union_(std::unexpect, __unex.error()), __has_val_(false) {} + : __base(unexpect, __unex.error()) {} template requires is_constructible_v<_Err, _OtherErr> _LIBCPP_HIDE_FROM_ABI constexpr explicit(!is_convertible_v<_OtherErr, _Err>) expected(unexpected<_OtherErr>&& __unex) noexcept(is_nothrow_constructible_v<_Err, _OtherErr>) // strengthened - : __union_(std::unexpect, std::move(__unex.error())), __has_val_(false) {} + : __base(unexpect, std::move(__unex.error())) {} - _LIBCPP_HIDE_FROM_ABI constexpr explicit expected(in_place_t) noexcept : __has_val_(true) {} + _LIBCPP_HIDE_FROM_ABI constexpr explicit expected(in_place_t) noexcept : __base(in_place) {} template requires is_constructible_v<_Err, _Args...> _LIBCPP_HIDE_FROM_ABI constexpr explicit expected(unexpect_t, _Args&&... __args) noexcept( is_nothrow_constructible_v<_Err, _Args...>) // strengthened - : __union_(std::unexpect, std::forward<_Args>(__args)...), __has_val_(false) {} + : __base(unexpect, std::forward<_Args>(__args)...) {} template requires is_constructible_v< _Err, initializer_list<_Up>&, _Args... > _LIBCPP_HIDE_FROM_ABI constexpr explicit expected(unexpect_t, initializer_list<_Up> __il, _Args&&... __args) noexcept( is_nothrow_constructible_v<_Err, initializer_list<_Up>&, _Args...>) // strengthened - : __union_(std::unexpect, __il, std::forward<_Args>(__args)...), __has_val_(false) {} + : __base(unexpect, __il, std::forward<_Args>(__args)...) {} private: - template - _LIBCPP_HIDE_FROM_ABI constexpr explicit expected(__expected_construct_in_place_from_invoke_tag, _Func&& __f) - : __has_val_(true) { - std::invoke(std::forward<_Func>(__f)); - } - template _LIBCPP_HIDE_FROM_ABI constexpr explicit expected( __expected_construct_unexpected_from_invoke_tag __tag, _Func&& __f, _Args&&... __args) - : __union_(__tag, std::forward<_Func>(__f), std::forward<_Args>(__args)...), __has_val_(false) {} + : __base(__tag, std::forward<_Func>(__f), std::forward<_Args>(__args)...) {} public: // [expected.void.dtor], destructor - _LIBCPP_HIDE_FROM_ABI constexpr ~expected() - requires is_trivially_destructible_v<_Err> - = default; + _LIBCPP_HIDE_FROM_ABI constexpr ~expected() = default; - _LIBCPP_HIDE_FROM_ABI constexpr ~expected() - requires(!is_trivially_destructible_v<_Err>) - { - if (!__has_val_) { - std::destroy_at(std::addressof(__union_.__unex_)); - } +private: + template + _LIBCPP_HIDE_FROM_ABI constexpr void __reinit_expected(unexpect_t, _Args&&... __args) { + _LIBCPP_ASSERT_INTERNAL(this->__has_val(), "__reinit_expected(unexpect_t, ...) needs value to be set"); + + this->__destroy(); + auto __trans = std::__make_exception_guard([&] { this->__construct(in_place); }); + this->__construct(unexpect, std::forward<_Args>(__args)...); + __trans.__complete(); } - // [expected.void.assign], assignment + _LIBCPP_HIDE_FROM_ABI constexpr void __reinit_expected(in_place_t) { + _LIBCPP_ASSERT_INTERNAL(!this->__has_val(), "__reinit_expected(in_place_t, ...) needs value to be unset"); + this->__destroy(); + this->__construct(in_place); + } + +public: + // [expected.void.assign], assignment _LIBCPP_HIDE_FROM_ABI constexpr expected& operator=(const expected&) = delete; _LIBCPP_HIDE_FROM_ABI constexpr expected& operator=(const expected& __rhs) noexcept( is_nothrow_copy_assignable_v<_Err> && is_nothrow_copy_constructible_v<_Err>) // strengthened requires(is_copy_assignable_v<_Err> && is_copy_constructible_v<_Err>) { - if (__has_val_) { - if (!__rhs.__has_val_) { - std::construct_at(std::addressof(__union_.__unex_), __rhs.__union_.__unex_); - __has_val_ = false; + if (this->__has_val()) { + if (!__rhs.__has_val()) { + __reinit_expected(unexpect, __rhs.__unex()); } } else { - if (__rhs.__has_val_) { - std::destroy_at(std::addressof(__union_.__unex_)); - __has_val_ = true; + if (__rhs.__has_val()) { + __reinit_expected(in_place); } else { - __union_.__unex_ = __rhs.__union_.__unex_; + this->__unex() = __rhs.__unex(); } } return *this; @@ -1061,17 +1500,15 @@ public: operator=(expected&& __rhs) noexcept(is_nothrow_move_assignable_v<_Err> && is_nothrow_move_constructible_v<_Err>) requires(is_move_assignable_v<_Err> && is_move_constructible_v<_Err>) { - if (__has_val_) { - if (!__rhs.__has_val_) { - std::construct_at(std::addressof(__union_.__unex_), std::move(__rhs.__union_.__unex_)); - __has_val_ = false; + if (this->__has_val()) { + if (!__rhs.__has_val()) { + __reinit_expected(unexpect, std::move(__rhs.__unex())); } } else { - if (__rhs.__has_val_) { - std::destroy_at(std::addressof(__union_.__unex_)); - __has_val_ = true; + if (__rhs.__has_val()) { + __reinit_expected(in_place); } else { - __union_.__unex_ = std::move(__rhs.__union_.__unex_); + this->__unex() = std::move(__rhs.__unex()); } } return *this; @@ -1080,11 +1517,10 @@ public: template requires(is_constructible_v<_Err, const _OtherErr&> && is_assignable_v<_Err&, const _OtherErr&>) _LIBCPP_HIDE_FROM_ABI constexpr expected& operator=(const unexpected<_OtherErr>& __un) { - if (__has_val_) { - std::construct_at(std::addressof(__union_.__unex_), __un.error()); - __has_val_ = false; + if (this->__has_val()) { + __reinit_expected(unexpect, __un.error()); } else { - __union_.__unex_ = __un.error(); + this->__unex() = __un.error(); } return *this; } @@ -1092,19 +1528,17 @@ public: template requires(is_constructible_v<_Err, _OtherErr> && is_assignable_v<_Err&, _OtherErr>) _LIBCPP_HIDE_FROM_ABI constexpr expected& operator=(unexpected<_OtherErr>&& __un) { - if (__has_val_) { - std::construct_at(std::addressof(__union_.__unex_), std::move(__un.error())); - __has_val_ = false; + if (this->__has_val()) { + __reinit_expected(unexpect, std::move(__un.error())); } else { - __union_.__unex_ = std::move(__un.error()); + this->__unex() = std::move(__un.error()); } return *this; } _LIBCPP_HIDE_FROM_ABI constexpr void emplace() noexcept { - if (!__has_val_) { - std::destroy_at(std::addressof(__union_.__unex_)); - __has_val_ = true; + if (!this->__has_val()) { + __reinit_expected(in_place); } } @@ -1113,23 +1547,23 @@ public: swap(expected& __rhs) noexcept(is_nothrow_move_constructible_v<_Err> && is_nothrow_swappable_v<_Err>) requires(is_swappable_v<_Err> && is_move_constructible_v<_Err>) { - auto __swap_val_unex_impl = [&](expected& __with_val, expected& __with_err) { - std::construct_at(std::addressof(__with_val.__union_.__unex_), std::move(__with_err.__union_.__unex_)); - std::destroy_at(std::addressof(__with_err.__union_.__unex_)); - __with_val.__has_val_ = false; - __with_err.__has_val_ = true; + auto __swap_val_unex_impl = [](expected& __with_val, expected& __with_err) { + // May throw, but will re-engage `__with_val` in that case. + __with_val.__reinit_expected(unexpect, std::move(__with_err.__unex())); + // Will not throw. + __with_err.__reinit_expected(in_place); }; - if (__has_val_) { - if (!__rhs.__has_val_) { + if (this->__has_val()) { + if (!__rhs.__has_val()) { __swap_val_unex_impl(*this, __rhs); } } else { - if (__rhs.__has_val_) { + if (__rhs.__has_val()) { __swap_val_unex_impl(__rhs, *this); } else { using std::swap; - swap(__union_.__unex_, __rhs.__union_.__unex_); + swap(this->__unex(), __rhs.__unex()); } } } @@ -1141,44 +1575,51 @@ public: } // [expected.void.obs], observers - _LIBCPP_HIDE_FROM_ABI constexpr explicit operator bool() const noexcept { return __has_val_; } + _LIBCPP_HIDE_FROM_ABI constexpr explicit operator bool() const noexcept { return this->__has_val(); } - _LIBCPP_HIDE_FROM_ABI constexpr bool has_value() const noexcept { return __has_val_; } + _LIBCPP_HIDE_FROM_ABI constexpr bool has_value() const noexcept { return this->__has_val(); } _LIBCPP_HIDE_FROM_ABI constexpr void operator*() const noexcept { - _LIBCPP_ASSERT_VALID_ELEMENT_ACCESS(__has_val_, "expected::operator* requires the expected to contain a value"); + _LIBCPP_ASSERT_VALID_ELEMENT_ACCESS( + this->__has_val(), "expected::operator* requires the expected to contain a value"); } _LIBCPP_HIDE_FROM_ABI constexpr void value() const& { - if (!__has_val_) { - std::__throw_bad_expected_access<_Err>(__union_.__unex_); + static_assert(is_copy_constructible_v<_Err>); + if (!this->__has_val()) { + std::__throw_bad_expected_access<_Err>(this->__unex()); } } _LIBCPP_HIDE_FROM_ABI constexpr void value() && { - if (!__has_val_) { - std::__throw_bad_expected_access<_Err>(std::move(__union_.__unex_)); + static_assert(is_copy_constructible_v<_Err> && is_move_constructible_v<_Err>); + if (!this->__has_val()) { + std::__throw_bad_expected_access<_Err>(std::move(this->__unex())); } } _LIBCPP_HIDE_FROM_ABI constexpr const _Err& error() const& noexcept { - _LIBCPP_ASSERT_VALID_ELEMENT_ACCESS(!__has_val_, "expected::error requires the expected to contain an error"); - return __union_.__unex_; + _LIBCPP_ASSERT_VALID_ELEMENT_ACCESS( + !this->__has_val(), "expected::error requires the expected to contain an error"); + return this->__unex(); } _LIBCPP_HIDE_FROM_ABI constexpr _Err& error() & noexcept { - _LIBCPP_ASSERT_VALID_ELEMENT_ACCESS(!__has_val_, "expected::error requires the expected to contain an error"); - return __union_.__unex_; + _LIBCPP_ASSERT_VALID_ELEMENT_ACCESS( + !this->__has_val(), "expected::error requires the expected to contain an error"); + return this->__unex(); } _LIBCPP_HIDE_FROM_ABI constexpr const _Err&& error() const&& noexcept { - _LIBCPP_ASSERT_VALID_ELEMENT_ACCESS(!__has_val_, "expected::error requires the expected to contain an error"); - return std::move(__union_.__unex_); + _LIBCPP_ASSERT_VALID_ELEMENT_ACCESS( + !this->__has_val(), "expected::error requires the expected to contain an error"); + return std::move(this->__unex()); } _LIBCPP_HIDE_FROM_ABI constexpr _Err&& error() && noexcept { - _LIBCPP_ASSERT_VALID_ELEMENT_ACCESS(!__has_val_, "expected::error requires the expected to contain an error"); - return std::move(__union_.__unex_); + _LIBCPP_ASSERT_VALID_ELEMENT_ACCESS( + !this->__has_val(), "expected::error requires the expected to contain an error"); + return std::move(this->__unex()); } template @@ -1414,96 +1855,17 @@ public: template requires is_void_v<_T2> _LIBCPP_HIDE_FROM_ABI friend constexpr bool operator==(const expected& __x, const expected<_T2, _E2>& __y) { - if (__x.__has_val_ != __y.__has_val_) { + if (__x.__has_val() != __y.__has_val()) { return false; } else { - return __x.__has_val_ || static_cast(__x.__union_.__unex_ == __y.__union_.__unex_); + return __x.__has_val() || static_cast(__x.__unex() == __y.__unex()); } } template _LIBCPP_HIDE_FROM_ABI friend constexpr bool operator==(const expected& __x, const unexpected<_E2>& __y) { - return !__x.__has_val_ && static_cast(__x.__union_.__unex_ == __y.error()); + return !__x.__has_val() && static_cast(__x.__unex() == __y.error()); } - -private: - struct __empty_t {}; - - template - union __union_t { - _LIBCPP_HIDE_FROM_ABI constexpr __union_t() : __empty_() {} - - template - _LIBCPP_HIDE_FROM_ABI constexpr explicit __union_t(std::unexpect_t, _Args&&... __args) - : __unex_(std::forward<_Args>(__args)...) {} - - template - _LIBCPP_HIDE_FROM_ABI constexpr explicit __union_t( - __expected_construct_unexpected_from_invoke_tag, _Func&& __f, _Args&&... __args) - : __unex_(std::invoke(std::forward<_Func>(__f), std::forward<_Args>(__args)...)) {} - - template - _LIBCPP_HIDE_FROM_ABI constexpr explicit __union_t(bool __has_val, _Union&& __other) { - if (__has_val) - std::construct_at(std::addressof(__empty_)); - else - std::construct_at(std::addressof(__unex_), std::forward<_Union>(__other).__unex_); - } - - _LIBCPP_HIDE_FROM_ABI constexpr ~__union_t() - requires(is_trivially_destructible_v<_ErrorType>) - = default; - - // the expected's destructor handles this - _LIBCPP_HIDE_FROM_ABI constexpr ~__union_t() {} - - __empty_t __empty_; - _ErrorType __unex_; - }; - - // use named union because [[no_unique_address]] cannot be applied to an unnamed union, - // also guaranteed elision into a potentially-overlapping subobject is unsettled (and - // it's not clear that it's implementable, given that the function is allowed to clobber - // the tail padding) - see https://github.com/itanium-cxx-abi/cxx-abi/issues/107. - template - requires is_trivially_move_constructible_v<_ErrorType> - union __union_t<_ErrorType> { - _LIBCPP_HIDE_FROM_ABI constexpr __union_t() : __empty_() {} - _LIBCPP_HIDE_FROM_ABI constexpr __union_t(const __union_t&) = default; - _LIBCPP_HIDE_FROM_ABI constexpr __union_t& operator=(const __union_t&) = default; - - template - _LIBCPP_HIDE_FROM_ABI constexpr explicit __union_t(std::unexpect_t, _Args&&... __args) - : __unex_(std::forward<_Args>(__args)...) {} - - template - _LIBCPP_HIDE_FROM_ABI constexpr explicit __union_t( - __expected_construct_unexpected_from_invoke_tag, _Func&& __f, _Args&&... __args) - : __unex_(std::invoke(std::forward<_Func>(__f), std::forward<_Args>(__args)...)) {} - - template - _LIBCPP_HIDE_FROM_ABI constexpr explicit __union_t(bool __has_val, _Union&& __other) { - if (__has_val) - std::construct_at(std::addressof(__empty_)); - else - std::construct_at(std::addressof(__unex_), std::forward<_Union>(__other).__unex_); - } - - _LIBCPP_HIDE_FROM_ABI constexpr ~__union_t() - requires(is_trivially_destructible_v<_ErrorType>) - = default; - - // the expected's destructor handles this - _LIBCPP_HIDE_FROM_ABI constexpr ~__union_t() - requires(!is_trivially_destructible_v<_ErrorType>) - {} - - _LIBCPP_NO_UNIQUE_ADDRESS __empty_t __empty_; - _LIBCPP_NO_UNIQUE_ADDRESS _ErrorType __unex_; - }; - - _LIBCPP_NO_UNIQUE_ADDRESS __union_t<_Err> __union_; - bool __has_val_; }; _LIBCPP_END_NAMESPACE_STD diff --git a/libcxx/include/__hash_table b/libcxx/include/__hash_table index 4ca49fe4260..13420012006 100644 --- a/libcxx/include/__hash_table +++ b/libcxx/include/__hash_table @@ -861,7 +861,7 @@ public: template _LIBCPP_HIDE_FROM_ABI size_type bucket(const _Key& __k) const { - _LIBCPP_ASSERT_UNCATEGORIZED( + _LIBCPP_ASSERT_ARGUMENT_WITHIN_DOMAIN( bucket_count() > 0, "unordered container::bucket(key) called when bucket_count() == 0"); return std::__constrain_hash(hash_function()(__k), bucket_count()); } diff --git a/libcxx/include/__iterator/iterator_traits.h b/libcxx/include/__iterator/iterator_traits.h index dae8cc75ae3..2cd82525ba0 100644 --- a/libcxx/include/__iterator/iterator_traits.h +++ b/libcxx/include/__iterator/iterator_traits.h @@ -121,7 +121,7 @@ private: __void_t* = nullptr); public: - static const bool value = decltype(__test<_Tp>(0, 0, 0, 0, 0))::value; + static const bool value = decltype(__test<_Tp>(nullptr, nullptr, nullptr, nullptr, nullptr))::value; }; template diff --git a/libcxx/include/__memory/allocator.h b/libcxx/include/__memory/allocator.h index 747ce30d8fe..4e6303914c3 100644 --- a/libcxx/include/__memory/allocator.h +++ b/libcxx/include/__memory/allocator.h @@ -31,6 +31,12 @@ _LIBCPP_BEGIN_NAMESPACE_STD template class allocator; +#if defined(_LIBCPP_ENABLE_CXX20_REMOVED_ALLOCATOR_MEMBERS) && !defined(_LIBCPP_DISABLE_DEPRECATION_WARNINGS) +# pragma clang deprecated( \ + _LIBCPP_ENABLE_CXX20_REMOVED_ALLOCATOR_MEMBERS, \ + "_LIBCPP_ENABLE_CXX20_REMOVED_ALLOCATOR_MEMBERS is deprecated in LLVM 18 and will be removed in LLVM 19") +#endif + #if _LIBCPP_STD_VER <= 17 || defined(_LIBCPP_ENABLE_CXX20_REMOVED_ALLOCATOR_VOID_SPECIALIZATION) // These specializations shouldn't be marked _LIBCPP_DEPRECATED_IN_CXX17. // Specializing allocator is deprecated, but not using it. @@ -101,7 +107,9 @@ public: typedef ptrdiff_t difference_type; typedef _Tp value_type; typedef true_type propagate_on_container_move_assignment; - typedef true_type is_always_equal; +#if _LIBCPP_STD_VER <= 23 || defined(_LIBCPP_ENABLE_CXX26_REMOVED_ALLOCATOR_MEMBERS) + _LIBCPP_DEPRECATED_IN_CXX23 typedef true_type is_always_equal; +#endif _LIBCPP_HIDE_FROM_ABI _LIBCPP_CONSTEXPR_SINCE_CXX20 allocator() _NOEXCEPT = default; @@ -179,7 +187,9 @@ public: typedef ptrdiff_t difference_type; typedef const _Tp value_type; typedef true_type propagate_on_container_move_assignment; - typedef true_type is_always_equal; +#if _LIBCPP_STD_VER <= 23 || defined(_LIBCPP_ENABLE_CXX26_REMOVED_ALLOCATOR_MEMBERS) + _LIBCPP_DEPRECATED_IN_CXX23 typedef true_type is_always_equal; +#endif _LIBCPP_HIDE_FROM_ABI _LIBCPP_CONSTEXPR_SINCE_CXX20 allocator() _NOEXCEPT = default; diff --git a/libcxx/include/__memory/assume_aligned.h b/libcxx/include/__memory/assume_aligned.h index c66fb49ebb3..526eb3334f9 100644 --- a/libcxx/include/__memory/assume_aligned.h +++ b/libcxx/include/__memory/assume_aligned.h @@ -27,9 +27,11 @@ _LIBCPP_NODISCARD _LIBCPP_HIDE_FROM_ABI _LIBCPP_CONSTEXPR_SINCE_CXX14 _Tp* __ass static_assert(_Np != 0 && (_Np & (_Np - 1)) == 0, "std::assume_aligned(p) requires N to be a power of two"); if (__libcpp_is_constant_evaluated()) { + (void)__builtin_assume_aligned(__ptr, _Np); return __ptr; } else { - _LIBCPP_ASSERT_UNCATEGORIZED(reinterpret_cast(__ptr) % _Np == 0, "Alignment assumption is violated"); + _LIBCPP_ASSERT_ARGUMENT_WITHIN_DOMAIN( + reinterpret_cast(__ptr) % _Np == 0, "Alignment assumption is violated"); return static_cast<_Tp*>(__builtin_assume_aligned(__ptr, _Np)); } } diff --git a/libcxx/include/__memory_resource/polymorphic_allocator.h b/libcxx/include/__memory_resource/polymorphic_allocator.h index 3a279493176..cfd07bc84fe 100644 --- a/libcxx/include/__memory_resource/polymorphic_allocator.h +++ b/libcxx/include/__memory_resource/polymorphic_allocator.h @@ -68,7 +68,10 @@ public: } _LIBCPP_HIDE_FROM_ABI void deallocate(_ValueType* __p, size_t __n) { - _LIBCPP_ASSERT_UNCATEGORIZED(__n <= __max_size(), "deallocate called for size which exceeds max_size()"); + _LIBCPP_ASSERT_VALID_DEALLOCATION( + __n <= __max_size(), + "deallocate() called for a size which exceeds max_size(), leading to a memory leak " + "(the argument will overflow and result in too few objects being deleted)"); __res_->deallocate(__p, __n * sizeof(_ValueType), alignof(_ValueType)); } diff --git a/libcxx/include/__numeric/gcd_lcm.h b/libcxx/include/__numeric/gcd_lcm.h index 3e9c244f25c..48df2338051 100644 --- a/libcxx/include/__numeric/gcd_lcm.h +++ b/libcxx/include/__numeric/gcd_lcm.h @@ -77,7 +77,7 @@ _LIBCPP_CONSTEXPR _LIBCPP_HIDE_FROM_ABI common_type_t<_Tp, _Up> lcm(_Tp __m, _Up using _Rp = common_type_t<_Tp, _Up>; _Rp __val1 = __ct_abs<_Rp, _Tp>()(__m) / std::gcd(__m, __n); _Rp __val2 = __ct_abs<_Rp, _Up>()(__n); - _LIBCPP_ASSERT_UNCATEGORIZED((numeric_limits<_Rp>::max() / __val1 > __val2), "Overflow in lcm"); + _LIBCPP_ASSERT_ARGUMENT_WITHIN_DOMAIN((numeric_limits<_Rp>::max() / __val1 > __val2), "Overflow in lcm"); return __val1 * __val2; } diff --git a/libcxx/include/__numeric/saturation_arithmetic.h b/libcxx/include/__numeric/saturation_arithmetic.h new file mode 100644 index 00000000000..50274c6bbd9 --- /dev/null +++ b/libcxx/include/__numeric/saturation_arithmetic.h @@ -0,0 +1,110 @@ +// -*- C++ -*- +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +#ifndef _LIBCPP___NUMERIC_SATURATION_ARITHMETIC_H +#define _LIBCPP___NUMERIC_SATURATION_ARITHMETIC_H + +#include <__concepts/arithmetic.h> +#include <__config> +#include <__utility/cmp.h> +#include + +#if !defined(_LIBCPP_HAS_NO_PRAGMA_SYSTEM_HEADER) +# pragma GCC system_header +#endif + +_LIBCPP_BEGIN_NAMESPACE_STD + +#if _LIBCPP_STD_VER >= 26 + +template <__libcpp_integer _Tp> +_LIBCPP_HIDE_FROM_ABI constexpr _Tp add_sat(_Tp __x, _Tp __y) noexcept { + if (_Tp __sum; !__builtin_add_overflow(__x, __y, &__sum)) + return __sum; + // Handle overflow + if constexpr (__libcpp_unsigned_integer<_Tp>) { + return std::numeric_limits<_Tp>::max(); + } else { + // Signed addition overflow + if (__x > 0) + // Overflows if (x > 0 && y > 0) + return std::numeric_limits<_Tp>::max(); + else + // Overflows if (x < 0 && y < 0) + return std::numeric_limits<_Tp>::min(); + } +} + +template <__libcpp_integer _Tp> +_LIBCPP_HIDE_FROM_ABI constexpr _Tp sub_sat(_Tp __x, _Tp __y) noexcept { + if (_Tp __sub; !__builtin_sub_overflow(__x, __y, &__sub)) + return __sub; + // Handle overflow + if constexpr (__libcpp_unsigned_integer<_Tp>) { + // Overflows if (x < y) + return std::numeric_limits<_Tp>::min(); + } else { + // Signed subtration overflow + if (__x >= 0) + // Overflows if (x >= 0 && y < 0) + return std::numeric_limits<_Tp>::max(); + else + // Overflows if (x < 0 && y > 0) + return std::numeric_limits<_Tp>::min(); + } +} + +template <__libcpp_integer _Tp> +_LIBCPP_HIDE_FROM_ABI constexpr _Tp mul_sat(_Tp __x, _Tp __y) noexcept { + if (_Tp __mul; !__builtin_mul_overflow(__x, __y, &__mul)) + return __mul; + // Handle overflow + if constexpr (__libcpp_unsigned_integer<_Tp>) { + return std::numeric_limits<_Tp>::max(); + } else { + // Signed multiplication overflow + if ((__x > 0 && __y > 0) || (__x < 0 && __y < 0)) + return std::numeric_limits<_Tp>::max(); + // Overflows if (x < 0 && y > 0) || (x > 0 && y < 0) + return std::numeric_limits<_Tp>::min(); + } +} + +template <__libcpp_integer _Tp> +_LIBCPP_HIDE_FROM_ABI constexpr _Tp div_sat(_Tp __x, _Tp __y) noexcept { + _LIBCPP_ASSERT_UNCATEGORIZED(__y != 0, "Division by 0 is undefined"); + if constexpr (__libcpp_unsigned_integer<_Tp>) { + return __x / __y; + } else { + // Handle signed division overflow + if (__x == std::numeric_limits<_Tp>::min() && __y == _Tp{-1}) + return std::numeric_limits<_Tp>::max(); + return __x / __y; + } +} + +template <__libcpp_integer _Rp, __libcpp_integer _Tp> +_LIBCPP_HIDE_FROM_ABI constexpr _Rp saturate_cast(_Tp __x) noexcept { + // Saturation is impossible edge case when ((min _Rp) < (min _Tp) && (max _Rp) > (max _Tp)) and it is expected to be + // optimized out by the compiler. + + // Handle overflow + if (std::cmp_less(__x, std::numeric_limits<_Rp>::min())) + return std::numeric_limits<_Rp>::min(); + if (std::cmp_greater(__x, std::numeric_limits<_Rp>::max())) + return std::numeric_limits<_Rp>::max(); + // No overflow + return static_cast<_Rp>(__x); +} + +#endif // _LIBCPP_STD_VER >= 26 + +_LIBCPP_END_NAMESPACE_STD + +#endif // _LIBCPP___NUMERIC_SATURATION_ARITHMETIC_H diff --git a/libcxx/include/__ranges/chunk_by_view.h b/libcxx/include/__ranges/chunk_by_view.h index c5b3240a7d0..b04a23de99f 100644 --- a/libcxx/include/__ranges/chunk_by_view.h +++ b/libcxx/include/__ranges/chunk_by_view.h @@ -54,8 +54,7 @@ namespace ranges { template , iterator_t<_View>> _Pred> requires view<_View> && is_object_v<_Pred> -class _LIBCPP_ABI_2023_OVERLAPPING_SUBOBJECT_FIX_TAG chunk_by_view - : public view_interface> { +class _LIBCPP_ABI_LLVM18_NO_UNIQUE_ADDRESS chunk_by_view : public view_interface> { _LIBCPP_NO_UNIQUE_ADDRESS _View __base_ = _View(); _LIBCPP_NO_UNIQUE_ADDRESS __movable_box<_Pred> __pred_; diff --git a/libcxx/include/__ranges/drop_while_view.h b/libcxx/include/__ranges/drop_while_view.h index b367f735c14..4e3ef61678f 100644 --- a/libcxx/include/__ranges/drop_while_view.h +++ b/libcxx/include/__ranges/drop_while_view.h @@ -45,8 +45,7 @@ namespace ranges { template requires input_range<_View> && is_object_v<_Pred> && indirect_unary_predicate> -class _LIBCPP_ABI_2023_OVERLAPPING_SUBOBJECT_FIX_TAG drop_while_view - : public view_interface> { +class _LIBCPP_ABI_LLVM18_NO_UNIQUE_ADDRESS drop_while_view : public view_interface> { public: _LIBCPP_HIDE_FROM_ABI drop_while_view() requires default_initializable<_View> && default_initializable<_Pred> diff --git a/libcxx/include/__ranges/filter_view.h b/libcxx/include/__ranges/filter_view.h index ecb78eee381..6e6719c1447 100644 --- a/libcxx/include/__ranges/filter_view.h +++ b/libcxx/include/__ranges/filter_view.h @@ -51,7 +51,7 @@ _LIBCPP_BEGIN_NAMESPACE_STD namespace ranges { template > _Pred> requires view<_View> && is_object_v<_Pred> -class _LIBCPP_ABI_2023_OVERLAPPING_SUBOBJECT_FIX_TAG filter_view : public view_interface> { +class _LIBCPP_ABI_LLVM18_NO_UNIQUE_ADDRESS filter_view : public view_interface> { _LIBCPP_NO_UNIQUE_ADDRESS _View __base_ = _View(); _LIBCPP_NO_UNIQUE_ADDRESS __movable_box<_Pred> __pred_; diff --git a/libcxx/include/__ranges/repeat_view.h b/libcxx/include/__ranges/repeat_view.h index 479eca96acb..d9759abe1cb 100644 --- a/libcxx/include/__ranges/repeat_view.h +++ b/libcxx/include/__ranges/repeat_view.h @@ -68,7 +68,7 @@ struct __fn; template requires(is_object_v<_Tp> && same_as<_Tp, remove_cv_t<_Tp>> && (__integer_like_with_usable_difference_type<_Bound> || same_as<_Bound, unreachable_sentinel_t>)) -class _LIBCPP_ABI_2023_OVERLAPPING_SUBOBJECT_FIX_TAG repeat_view : public view_interface> { +class _LIBCPP_ABI_LLVM18_NO_UNIQUE_ADDRESS repeat_view : public view_interface> { friend struct views::__take::__fn; friend struct views::__drop::__fn; class __iterator; diff --git a/libcxx/include/__ranges/single_view.h b/libcxx/include/__ranges/single_view.h index 0ae2036a66a..ead597a9be1 100644 --- a/libcxx/include/__ranges/single_view.h +++ b/libcxx/include/__ranges/single_view.h @@ -37,7 +37,7 @@ template template # endif requires is_object_v<_Tp> -class _LIBCPP_ABI_2023_OVERLAPPING_SUBOBJECT_FIX_TAG single_view : public view_interface> { +class _LIBCPP_ABI_LLVM18_NO_UNIQUE_ADDRESS single_view : public view_interface> { _LIBCPP_NO_UNIQUE_ADDRESS __movable_box<_Tp> __value_; public: diff --git a/libcxx/include/__ranges/take_while_view.h b/libcxx/include/__ranges/take_while_view.h index 4534210d979..46cfe4f70ac 100644 --- a/libcxx/include/__ranges/take_while_view.h +++ b/libcxx/include/__ranges/take_while_view.h @@ -43,8 +43,7 @@ namespace ranges { template requires input_range<_View> && is_object_v<_Pred> && indirect_unary_predicate> -class _LIBCPP_ABI_2023_OVERLAPPING_SUBOBJECT_FIX_TAG take_while_view - : public view_interface> { +class _LIBCPP_ABI_LLVM18_NO_UNIQUE_ADDRESS take_while_view : public view_interface> { template class __sentinel; diff --git a/libcxx/include/__ranges/transform_view.h b/libcxx/include/__ranges/transform_view.h index 744f597ccef..3c8d825789c 100644 --- a/libcxx/include/__ranges/transform_view.h +++ b/libcxx/include/__ranges/transform_view.h @@ -67,8 +67,7 @@ template template # endif requires __transform_view_constraints<_View, _Fn> -class _LIBCPP_ABI_2023_OVERLAPPING_SUBOBJECT_FIX_TAG transform_view - : public view_interface> { +class _LIBCPP_ABI_LLVM18_NO_UNIQUE_ADDRESS transform_view : public view_interface> { template class __iterator; template diff --git a/libcxx/include/__utility/cmp.h b/libcxx/include/__utility/cmp.h index 5f88f4b3270..b7c1ed614df 100644 --- a/libcxx/include/__utility/cmp.h +++ b/libcxx/include/__utility/cmp.h @@ -9,14 +9,10 @@ #ifndef _LIBCPP___UTILITY_CMP_H #define _LIBCPP___UTILITY_CMP_H +#include <__concepts/arithmetic.h> #include <__config> -#include <__type_traits/disjunction.h> -#include <__type_traits/is_integral.h> -#include <__type_traits/is_same.h> #include <__type_traits/is_signed.h> #include <__type_traits/make_unsigned.h> -#include <__utility/forward.h> -#include <__utility/move.h> #include #if !defined(_LIBCPP_HAS_NO_PRAGMA_SYSTEM_HEADER) @@ -29,28 +25,8 @@ _LIBCPP_PUSH_MACROS _LIBCPP_BEGIN_NAMESPACE_STD #if _LIBCPP_STD_VER >= 20 -template -struct _IsSameAsAny : _Or<_IsSame<_Tp, _Up>...> {}; -template -concept __is_safe_integral_cmp = - is_integral_v<_Tp> && - !_IsSameAsAny<_Tp, - bool, - char, - char16_t, - char32_t -# ifndef _LIBCPP_HAS_NO_CHAR8_T - , - char8_t -# endif -# ifndef _LIBCPP_HAS_NO_WIDE_CHARACTERS - , - wchar_t -# endif - >::value; - -template <__is_safe_integral_cmp _Tp, __is_safe_integral_cmp _Up> +template <__libcpp_integer _Tp, __libcpp_integer _Up> _LIBCPP_HIDE_FROM_ABI constexpr bool cmp_equal(_Tp __t, _Up __u) noexcept { if constexpr (is_signed_v<_Tp> == is_signed_v<_Up>) return __t == __u; @@ -60,12 +36,12 @@ _LIBCPP_HIDE_FROM_ABI constexpr bool cmp_equal(_Tp __t, _Up __u) noexcept { return __u < 0 ? false : __t == make_unsigned_t<_Up>(__u); } -template <__is_safe_integral_cmp _Tp, __is_safe_integral_cmp _Up> +template <__libcpp_integer _Tp, __libcpp_integer _Up> _LIBCPP_HIDE_FROM_ABI constexpr bool cmp_not_equal(_Tp __t, _Up __u) noexcept { return !std::cmp_equal(__t, __u); } -template <__is_safe_integral_cmp _Tp, __is_safe_integral_cmp _Up> +template <__libcpp_integer _Tp, __libcpp_integer _Up> _LIBCPP_HIDE_FROM_ABI constexpr bool cmp_less(_Tp __t, _Up __u) noexcept { if constexpr (is_signed_v<_Tp> == is_signed_v<_Up>) return __t < __u; @@ -75,26 +51,27 @@ _LIBCPP_HIDE_FROM_ABI constexpr bool cmp_less(_Tp __t, _Up __u) noexcept { return __u < 0 ? false : __t < make_unsigned_t<_Up>(__u); } -template <__is_safe_integral_cmp _Tp, __is_safe_integral_cmp _Up> +template <__libcpp_integer _Tp, __libcpp_integer _Up> _LIBCPP_HIDE_FROM_ABI constexpr bool cmp_greater(_Tp __t, _Up __u) noexcept { return std::cmp_less(__u, __t); } -template <__is_safe_integral_cmp _Tp, __is_safe_integral_cmp _Up> +template <__libcpp_integer _Tp, __libcpp_integer _Up> _LIBCPP_HIDE_FROM_ABI constexpr bool cmp_less_equal(_Tp __t, _Up __u) noexcept { return !std::cmp_greater(__t, __u); } -template <__is_safe_integral_cmp _Tp, __is_safe_integral_cmp _Up> +template <__libcpp_integer _Tp, __libcpp_integer _Up> _LIBCPP_HIDE_FROM_ABI constexpr bool cmp_greater_equal(_Tp __t, _Up __u) noexcept { return !std::cmp_less(__t, __u); } -template <__is_safe_integral_cmp _Tp, __is_safe_integral_cmp _Up> +template <__libcpp_integer _Tp, __libcpp_integer _Up> _LIBCPP_HIDE_FROM_ABI constexpr bool in_range(_Up __u) noexcept { return std::cmp_less_equal(__u, numeric_limits<_Tp>::max()) && std::cmp_greater_equal(__u, numeric_limits<_Tp>::min()); } + #endif // _LIBCPP_STD_VER >= 20 _LIBCPP_END_NAMESPACE_STD diff --git a/libcxx/include/any b/libcxx/include/any index b9e0a8d9455..378dfb6e21b 100644 --- a/libcxx/include/any +++ b/libcxx/include/any @@ -98,6 +98,7 @@ namespace std { #include <__type_traits/is_nothrow_move_constructible.h> #include <__type_traits/is_reference.h> #include <__type_traits/is_same.h> +#include <__type_traits/is_void.h> #include <__type_traits/remove_cv.h> #include <__type_traits/remove_cvref.h> #include <__type_traits/remove_reference.h> @@ -555,6 +556,7 @@ inline _LIBCPP_HIDE_FROM_ABI _LIBCPP_AVAILABILITY_THROW_BAD_ANY_CAST _ValueType template inline _LIBCPP_HIDE_FROM_ABI add_pointer_t> any_cast(any const* __any) _NOEXCEPT { + static_assert(!is_void_v<_ValueType>, "_ValueType may not be void."); static_assert(!is_reference<_ValueType>::value, "_ValueType may not be a reference."); return std::any_cast<_ValueType>(const_cast(__any)); } @@ -572,6 +574,7 @@ inline _LIBCPP_HIDE_FROM_ABI _RetType __pointer_or_func_cast(void*, /*IsFunction template _LIBCPP_HIDE_FROM_ABI add_pointer_t<_ValueType> any_cast(any* __any) _NOEXCEPT { using __any_imp::_Action; + static_assert(!is_void_v<_ValueType>, "_ValueType may not be void."); static_assert(!is_reference<_ValueType>::value, "_ValueType may not be a reference."); typedef add_pointer_t<_ValueType> _ReturnType; if (__any && __any->__h_) { diff --git a/libcxx/include/barrier b/libcxx/include/barrier index fcfc96cb048..f91452c8d00 100644 --- a/libcxx/include/barrier +++ b/libcxx/include/barrier @@ -45,11 +45,16 @@ namespace std */ +#include <__config> + +#ifdef _LIBCPP_HAS_NO_THREADS +# error " is not supported since libc++ has been configured without support for threads." +#endif + #include <__assert> // all public C++ headers provide the assertion handler #include <__atomic/atomic_base.h> #include <__atomic/memory_order.h> #include <__availability> -#include <__config> #include <__memory/unique_ptr.h> #include <__thread/poll_with_backoff.h> #include <__thread/timed_backoff_policy.h> @@ -63,10 +68,6 @@ namespace std # pragma GCC system_header #endif -#ifdef _LIBCPP_HAS_NO_THREADS -# error " is not supported since libc++ has been configured without support for threads." -#endif - _LIBCPP_PUSH_MACROS #include <__undef_macros> @@ -128,7 +129,7 @@ public: __completion_(std::move(__completion)), __phase_(0) {} [[__nodiscard__]] _LIBCPP_AVAILABILITY_SYNC _LIBCPP_HIDE_FROM_ABI arrival_token arrive(ptrdiff_t __update) { - _LIBCPP_ASSERT_UNCATEGORIZED( + _LIBCPP_ASSERT_ARGUMENT_WITHIN_DOMAIN( __update <= __expected_, "update is greater than the expected count for the current barrier phase"); auto const __old_phase = __phase_.load(memory_order_relaxed); @@ -186,7 +187,7 @@ public: auto const __result = __arrived.fetch_sub(update, memory_order_acq_rel) - update; auto const new_expected = __expected.load(memory_order_relaxed); - _LIBCPP_ASSERT_UNCATEGORIZED( + _LIBCPP_ASSERT_ARGUMENT_WITHIN_DOMAIN( update <= new_expected, "update is greater than the expected count for the current barrier phase"); if (0 == __result) { @@ -231,7 +232,7 @@ public: auto const __inc = __arrived_unit * update; auto const __old = __phase_arrived_expected.fetch_add(__inc, memory_order_acq_rel); - _LIBCPP_ASSERT_UNCATEGORIZED( + _LIBCPP_ASSERT_ARGUMENT_WITHIN_DOMAIN( update <= __old, "update is greater than the expected count for the current barrier phase"); if ((__old ^ (__old + __inc)) & __phase_bit) { @@ -267,10 +268,10 @@ public: _LIBCPP_AVAILABILITY_SYNC _LIBCPP_HIDE_FROM_ABI explicit barrier( ptrdiff_t __count, _CompletionF __completion = _CompletionF()) : __b_(__count, std::move(__completion)) { - _LIBCPP_ASSERT_UNCATEGORIZED( + _LIBCPP_ASSERT_ARGUMENT_WITHIN_DOMAIN( __count >= 0, "barrier::barrier(ptrdiff_t, CompletionFunction): barrier cannot be initialized with a negative value"); - _LIBCPP_ASSERT_UNCATEGORIZED( + _LIBCPP_ASSERT_ARGUMENT_WITHIN_DOMAIN( __count <= max(), "barrier::barrier(ptrdiff_t, CompletionFunction): barrier cannot be initialized with " "a value greater than max()"); @@ -280,7 +281,7 @@ public: barrier& operator=(barrier const&) = delete; [[__nodiscard__]] _LIBCPP_AVAILABILITY_SYNC _LIBCPP_HIDE_FROM_ABI arrival_token arrive(ptrdiff_t __update = 1) { - _LIBCPP_ASSERT_UNCATEGORIZED(__update > 0, "barrier:arrive must be called with a value greater than 0"); + _LIBCPP_ASSERT_ARGUMENT_WITHIN_DOMAIN(__update > 0, "barrier:arrive must be called with a value greater than 0"); return __b_.arrive(__update); } _LIBCPP_AVAILABILITY_SYNC _LIBCPP_HIDE_FROM_ABI void wait(arrival_token&& __phase) const { diff --git a/libcxx/include/chrono b/libcxx/include/chrono index b3ed9acc5e5..c80fa78a56b 100644 --- a/libcxx/include/chrono +++ b/libcxx/include/chrono @@ -296,6 +296,10 @@ template // C++20 basic_ostream& operator<<(basic_ostream& os, const sys_time& tp); +template // C++20 + basic_ostream& + operator<<(basic_ostream& os, const sys_days& dp); + class file_clock // C++20 { public: diff --git a/libcxx/include/concepts b/libcxx/include/concepts index 196fa2e0ea7..5fdf30ecfbd 100644 --- a/libcxx/include/concepts +++ b/libcxx/include/concepts @@ -155,7 +155,7 @@ namespace std { #include <__config> #include -#if _LIBCPP_STD_VER <= 20 && !defined(_LIPCPP_REMOVE_TRANSITIVE_INCLUDES) +#if _LIBCPP_STD_VER <= 20 && !defined(_LIBCPP_REMOVE_TRANSITIVE_INCLUDES) # include #endif diff --git a/libcxx/include/condition_variable b/libcxx/include/condition_variable index cf7a570b6cb..e375c986e7f 100644 --- a/libcxx/include/condition_variable +++ b/libcxx/include/condition_variable @@ -126,11 +126,11 @@ public: #include <__condition_variable/condition_variable.h> #include <__config> #include <__memory/shared_ptr.h> -#include <__memory/unique_ptr.h> #include <__mutex/lock_guard.h> #include <__mutex/mutex.h> #include <__mutex/tag_types.h> #include <__mutex/unique_lock.h> +#include <__stop_token/stop_callback.h> #include <__stop_token/stop_token.h> #include <__utility/move.h> #include @@ -200,19 +200,26 @@ inline void condition_variable_any::notify_all() _NOEXCEPT { __cv_.notify_all(); } -struct __lock_external { - template - _LIBCPP_HIDE_FROM_ABI void operator()(_Lock* __m) { - __m->lock(); +template +struct __unlock_guard { + _Lock& __lock_; + + _LIBCPP_HIDE_FROM_ABI __unlock_guard(_Lock& __lock) : __lock_(__lock) { __lock_.unlock(); } + + _LIBCPP_HIDE_FROM_ABI ~__unlock_guard() _NOEXCEPT // turns exception to std::terminate + { + __lock_.lock(); } + + __unlock_guard(const __unlock_guard&) = delete; + __unlock_guard& operator=(const __unlock_guard&) = delete; }; template void condition_variable_any::wait(_Lock& __lock) { shared_ptr __mut = __mut_; unique_lock __lk(*__mut); - __lock.unlock(); - unique_ptr<_Lock, __lock_external> __lxx(&__lock); + __unlock_guard<_Lock> __unlock(__lock); lock_guard > __lx(__lk, adopt_lock_t()); __cv_.wait(__lk); } // __mut_.unlock(), __lock.lock() @@ -227,8 +234,7 @@ template cv_status condition_variable_any::wait_until(_Lock& __lock, const chrono::time_point<_Clock, _Duration>& __t) { shared_ptr __mut = __mut_; unique_lock __lk(*__mut); - __lock.unlock(); - unique_ptr<_Lock, __lock_external> __lxx(&__lock); + __unlock_guard<_Lock> __unlock(__lock); lock_guard > __lx(__lk, adopt_lock_t()); return __cv_.wait_until(__lk, __t); } // __mut_.unlock(), __lock.lock() @@ -256,24 +262,75 @@ condition_variable_any::wait_for(_Lock& __lock, const chrono::duration<_Rep, _Pe # if _LIBCPP_STD_VER >= 20 && !defined(_LIBCPP_HAS_NO_EXPERIMENTAL_STOP_TOKEN) template -bool condition_variable_any::wait(_Lock& __lock, stop_token __stoken, _Predicate __pred) { - while (!__stoken.stop_requested()) { +bool condition_variable_any::wait(_Lock& __user_lock, stop_token __stoken, _Predicate __pred) { + if (__stoken.stop_requested()) + return __pred(); + + // Per https://eel.is/c++draft/thread.condition.condvarany#general-note-2, + // we do need to take a copy of the shared pointer __mut_ + // This ensures that a thread can call the destructor immediately after calling + // notify_all, without waiting all the wait calls. + // A thread can also safely call the destructor immediately after calling + // request_stop, as the call to request_stop would evaluate the callback, + // which accesses the internal condition variable, immediately on the same thread. + // In this situation, it is OK even without copying a shared ownership the internal + // condition variable. However, this needs the evaluation of stop_callback to + // happen-before the destruction. + // The spec only says "Only the notification to unblock the wait needs to happen + // before destruction". To make this work, we need to copy the shared ownership of + // the internal condition variable inside this function, which is not possible + // with the current ABI. + shared_ptr __mut = __mut_; + + stop_callback __cb(__stoken, [this] { notify_all(); }); + + while (true) { if (__pred()) return true; - wait(__lock); - } + + // We need to take the internal lock before checking stop_requested, + // so that the notification cannot come in between the stop_requested + // check and entering the wait. + // Note that the stop_callback takes the same internal lock before notifying + unique_lock __internal_lock(*__mut); + if (__stoken.stop_requested()) + break; + + __unlock_guard<_Lock> __unlock(__user_lock); + unique_lock __internal_lock2( + std::move(__internal_lock)); // switch unlock order between __internal_lock and __user_lock + __cv_.wait(__internal_lock2); + } // __internal_lock2.unlock(), __user_lock.lock() return __pred(); } template bool condition_variable_any::wait_until( - _Lock& __lock, stop_token __stoken, const chrono::time_point<_Clock, _Duration>& __abs_time, _Predicate __pred) { - while (!__stoken.stop_requested()) { + _Lock& __user_lock, + stop_token __stoken, + const chrono::time_point<_Clock, _Duration>& __abs_time, + _Predicate __pred) { + if (__stoken.stop_requested()) + return __pred(); + + shared_ptr __mut = __mut_; + stop_callback __cb(__stoken, [this] { notify_all(); }); + + while (true) { if (__pred()) return true; - if (wait_until(__lock, __abs_time) == cv_status::timeout) - return __pred(); - } + + unique_lock __internal_lock(*__mut); + if (__stoken.stop_requested()) + break; + + __unlock_guard<_Lock> __unlock(__user_lock); + unique_lock __internal_lock2( + std::move(__internal_lock)); // switch unlock order between __internal_lock and __user_lock + + if (__cv_.wait_until(__internal_lock2, __abs_time) == cv_status::timeout) + break; + } // __internal_lock2.unlock(), __user_lock.lock() return __pred(); } diff --git a/libcxx/include/experimental/__simd/aligned_tag.h b/libcxx/include/experimental/__simd/aligned_tag.h index edbb3b24931..31d2b50aa1d 100644 --- a/libcxx/include/experimental/__simd/aligned_tag.h +++ b/libcxx/include/experimental/__simd/aligned_tag.h @@ -11,6 +11,7 @@ #define _LIBCPP_EXPERIMENTAL___SIMD_ALIGNED_TAG_H #include <__memory/assume_aligned.h> +#include <__type_traits/remove_const.h> #include #include #include @@ -35,7 +36,7 @@ inline constexpr bool is_simd_flag_type_v = true; struct vector_aligned_tag { template - static constexpr size_t __alignment = memory_alignment_v<_Tp, _Up>; + static constexpr size_t __alignment = memory_alignment_v<_Tp, remove_const_t<_Up>>; template static _LIBCPP_HIDE_FROM_ABI constexpr _Up* __apply(_Up* __ptr) { diff --git a/libcxx/include/experimental/__simd/scalar.h b/libcxx/include/experimental/__simd/scalar.h index 5eeff4c1e82..717fd6cd92d 100644 --- a/libcxx/include/experimental/__simd/scalar.h +++ b/libcxx/include/experimental/__simd/scalar.h @@ -56,6 +56,11 @@ struct __simd_operations<_Tp, simd_abi::__scalar> { static _LIBCPP_HIDE_FROM_ABI _SimdStorage __generate(_Generator&& __g) noexcept { return {__g(std::integral_constant())}; } + + template + static _LIBCPP_HIDE_FROM_ABI void __load(_SimdStorage& __s, const _Up* __mem) noexcept { + __s.__data = static_cast<_Tp>(__mem[0]); + } }; template @@ -63,6 +68,8 @@ struct __mask_operations<_Tp, simd_abi::__scalar> { using _MaskStorage = __mask_storage<_Tp, simd_abi::__scalar>; static _LIBCPP_HIDE_FROM_ABI _MaskStorage __broadcast(bool __v) noexcept { return {__v}; } + + static _LIBCPP_HIDE_FROM_ABI void __load(_MaskStorage& __s, const bool* __mem) noexcept { __s.__data = __mem[0]; } }; } // namespace parallelism_v2 diff --git a/libcxx/include/experimental/__simd/simd.h b/libcxx/include/experimental/__simd/simd.h index c345811fee7..db4ebb8e4a3 100644 --- a/libcxx/include/experimental/__simd/simd.h +++ b/libcxx/include/experimental/__simd/simd.h @@ -64,6 +64,12 @@ public: explicit _LIBCPP_HIDE_FROM_ABI simd(_Generator&& __g) noexcept : __s_(_Impl::__generate(std::forward<_Generator>(__g))) {} + // load constructor + template && is_simd_flag_type_v<_Flags>, int> = 0> + _LIBCPP_HIDE_FROM_ABI simd(const _Up* __mem, _Flags) { + _Impl::__load(__s_, _Flags::template __apply(__mem)); + } + // scalar access [simd.subscr] _LIBCPP_HIDE_FROM_ABI reference operator[](size_t __i) noexcept { return reference(__s_, __i); } _LIBCPP_HIDE_FROM_ABI value_type operator[](size_t __i) const noexcept { return __s_.__get(__i); } diff --git a/libcxx/include/experimental/__simd/simd_mask.h b/libcxx/include/experimental/__simd/simd_mask.h index db03843b46e..754db799268 100644 --- a/libcxx/include/experimental/__simd/simd_mask.h +++ b/libcxx/include/experimental/__simd/simd_mask.h @@ -52,6 +52,12 @@ public: } } + // load constructor + template , int> = 0> + _LIBCPP_HIDE_FROM_ABI simd_mask(const value_type* __mem, _Flags) { + _Impl::__load(__s_, _Flags::template __apply(__mem)); + } + // scalar access [simd.mask.subscr] _LIBCPP_HIDE_FROM_ABI reference operator[](size_t __i) noexcept { return reference(__s_, __i); } _LIBCPP_HIDE_FROM_ABI value_type operator[](size_t __i) const noexcept { return __s_.__get(__i); } diff --git a/libcxx/include/experimental/__simd/vec_ext.h b/libcxx/include/experimental/__simd/vec_ext.h index 07ba032f493..7883132ba6c 100644 --- a/libcxx/include/experimental/__simd/vec_ext.h +++ b/libcxx/include/experimental/__simd/vec_ext.h @@ -73,6 +73,12 @@ struct __simd_operations<_Tp, simd_abi::__vec_ext<_Np>> { static _LIBCPP_HIDE_FROM_ABI _SimdStorage __generate(_Generator&& __g) noexcept { return __generate_init(std::forward<_Generator>(__g), std::make_index_sequence<_Np>()); } + + template + static _LIBCPP_HIDE_FROM_ABI void __load(_SimdStorage& __s, const _Up* __mem) noexcept { + for (size_t __i = 0; __i < _Np; __i++) + __s.__data[__i] = static_cast<_Tp>(__mem[__i]); + } }; template @@ -87,6 +93,11 @@ struct __mask_operations<_Tp, simd_abi::__vec_ext<_Np>> { } return __result; } + + static _LIBCPP_HIDE_FROM_ABI void __load(_MaskStorage& __s, const bool* __mem) noexcept { + for (size_t __i = 0; __i < _Np; __i++) + __s.__data[__i] = experimental::__set_all_bits<_Tp>(__mem[__i]); + } }; } // namespace parallelism_v2 diff --git a/libcxx/include/future b/libcxx/include/future index 92ba1882106..5602ae41c14 100644 --- a/libcxx/include/future +++ b/libcxx/include/future @@ -362,11 +362,16 @@ template struct uses_allocator, Alloc>; */ +#include <__config> + +#ifdef _LIBCPP_HAS_NO_THREADS +# error " is not supported since libc++ has been configured without support for threads." +#endif + #include <__assert> // all public C++ headers provide the assertion handler #include <__availability> #include <__chrono/duration.h> #include <__chrono/time_point.h> -#include <__config> #include <__exception/exception_ptr.h> #include <__memory/addressof.h> #include <__memory/allocator.h> @@ -396,10 +401,6 @@ template struct uses_allocator, Alloc>; # pragma GCC system_header #endif -#ifdef _LIBCPP_HAS_NO_THREADS -# error " is not supported since libc++ has been configured without support for threads." -#endif - _LIBCPP_BEGIN_NAMESPACE_STD // enum class future_errc diff --git a/libcxx/include/latch b/libcxx/include/latch index ef52c0562a7..ad7b3557991 100644 --- a/libcxx/include/latch +++ b/libcxx/include/latch @@ -40,12 +40,17 @@ namespace std */ +#include <__config> + +#ifdef _LIBCPP_HAS_NO_THREADS +# error " is not supported since libc++ has been configured without support for threads." +#endif + #include <__assert> // all public C++ headers provide the assertion handler #include <__atomic/atomic_base.h> #include <__atomic/atomic_sync.h> #include <__atomic/memory_order.h> #include <__availability> -#include <__config> #include #include #include @@ -54,10 +59,6 @@ namespace std # pragma GCC system_header #endif -#ifdef _LIBCPP_HAS_NO_THREADS -# error " is not supported since libc++ has been configured without support for threads." -#endif - _LIBCPP_PUSH_MACROS #include <__undef_macros> @@ -72,11 +73,11 @@ public: static _LIBCPP_HIDE_FROM_ABI constexpr ptrdiff_t max() noexcept { return numeric_limits::max(); } inline _LIBCPP_HIDE_FROM_ABI constexpr explicit latch(ptrdiff_t __expected) : __a_(__expected) { - _LIBCPP_ASSERT_UNCATEGORIZED( + _LIBCPP_ASSERT_ARGUMENT_WITHIN_DOMAIN( __expected >= 0, "latch::latch(ptrdiff_t): latch cannot be " "initialized with a negative value"); - _LIBCPP_ASSERT_UNCATEGORIZED( + _LIBCPP_ASSERT_ARGUMENT_WITHIN_DOMAIN( __expected <= max(), "latch::latch(ptrdiff_t): latch cannot be " "initialized with a value greater than max()"); @@ -87,9 +88,9 @@ public: latch& operator=(const latch&) = delete; inline _LIBCPP_AVAILABILITY_SYNC _LIBCPP_HIDE_FROM_ABI void count_down(ptrdiff_t __update = 1) { - _LIBCPP_ASSERT_UNCATEGORIZED(__update >= 0, "latch::count_down called with a negative value"); + _LIBCPP_ASSERT_ARGUMENT_WITHIN_DOMAIN(__update >= 0, "latch::count_down called with a negative value"); auto const __old = __a_.fetch_sub(__update, memory_order_release); - _LIBCPP_ASSERT_UNCATEGORIZED( + _LIBCPP_ASSERT_ARGUMENT_WITHIN_DOMAIN( __update <= __old, "latch::count_down called with a value greater " "than the internal counter"); @@ -101,7 +102,7 @@ public: __cxx_atomic_wait(&__a_.__a_, [this]() -> bool { return try_wait(); }); } inline _LIBCPP_AVAILABILITY_SYNC _LIBCPP_HIDE_FROM_ABI void arrive_and_wait(ptrdiff_t __update = 1) { - _LIBCPP_ASSERT_UNCATEGORIZED(__update >= 0, "latch::arrive_and_wait called with a negative value"); + _LIBCPP_ASSERT_ARGUMENT_WITHIN_DOMAIN(__update >= 0, "latch::arrive_and_wait called with a negative value"); // other preconditions on __update are checked in count_down() count_down(__update); diff --git a/libcxx/include/libcxx.imp b/libcxx/include/libcxx.imp index 3eb2aa84931..45fa4a95419 100644 --- a/libcxx/include/libcxx.imp +++ b/libcxx/include/libcxx.imp @@ -1,53 +1,839 @@ [ - { include: [ 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"private", "", "public" ] }, + { include: [ "<__utility/exchange.h>", "private", "", "public" ] }, + { include: [ "<__utility/forward.h>", "private", "", "public" ] }, + { include: [ "<__utility/forward_like.h>", "private", "", "public" ] }, + { include: [ "<__utility/in_place.h>", "private", "", "public" ] }, + { include: [ "<__utility/integer_sequence.h>", "private", "", "public" ] }, + { include: [ "<__utility/is_pointer_in_range.h>", "private", "", "public" ] }, + { include: [ "<__utility/move.h>", "private", "", "public" ] }, + { include: [ "<__utility/no_destroy.h>", "private", "", "public" ] }, + { include: [ "<__utility/pair.h>", "private", "", "public" ] }, + { include: [ "<__utility/piecewise_construct.h>", "private", "", "public" ] }, + { include: [ "<__utility/priority_tag.h>", "private", "", "public" ] }, + { include: [ "<__utility/rel_ops.h>", "private", "", "public" ] }, + { include: [ "<__utility/small_buffer.h>", "private", "", "public" ] }, + { include: [ "<__utility/swap.h>", "private", "", "public" ] }, + { include: [ "<__utility/to_underlying.h>", "private", "", "public" ] }, + { include: [ "<__utility/unreachable.h>", "private", "", "public" ] }, + { include: [ "<__variant/monostate.h>", "private", "", "public" ] }, ] diff --git a/libcxx/include/locale b/libcxx/include/locale index 70d22ff95e1..9e97eb9f339 100644 --- a/libcxx/include/locale +++ b/libcxx/include/locale @@ -3421,7 +3421,7 @@ wbuffer_convert<_Codecvt, _Elem, _Tr>::~wbuffer_convert() { template typename wbuffer_convert<_Codecvt, _Elem, _Tr>::int_type wbuffer_convert<_Codecvt, _Elem, _Tr>::underflow() { _LIBCPP_SUPPRESS_DEPRECATED_POP - if (__cv_ == 0 || __bufptr_ == 0) + if (__cv_ == 0 || __bufptr_ == nullptr) return traits_type::eof(); bool __initial = __read_mode(); char_type __1buf; @@ -3478,7 +3478,7 @@ template typename wbuffer_convert<_Codecvt, _Elem, _Tr>::int_type wbuffer_convert<_Codecvt, _Elem, _Tr>::pbackfail(int_type __c) { _LIBCPP_SUPPRESS_DEPRECATED_POP - if (__cv_ != 0 && __bufptr_ != 0 && this->eback() < this->gptr()) { + if (__cv_ != 0 && __bufptr_ && this->eback() < this->gptr()) { if (traits_type::eq_int_type(__c, traits_type::eof())) { this->gbump(-1); return traits_type::not_eof(__c); @@ -3496,7 +3496,7 @@ _LIBCPP_SUPPRESS_DEPRECATED_PUSH template typename wbuffer_convert<_Codecvt, _Elem, _Tr>::int_type wbuffer_convert<_Codecvt, _Elem, _Tr>::overflow(int_type __c) { _LIBCPP_SUPPRESS_DEPRECATED_POP - if (__cv_ == 0 || __bufptr_ == 0) + if (__cv_ == 0 || !__bufptr_) return traits_type::eof(); __write_mode(); char_type __1buf; @@ -3588,7 +3588,7 @@ template typename wbuffer_convert<_Codecvt, _Elem, _Tr>::pos_type wbuffer_convert<_Codecvt, _Elem, _Tr>::seekoff(off_type __off, ios_base::seekdir __way, ios_base::openmode __om) { int __width = __cv_->encoding(); - if (__cv_ == 0 || __bufptr_ == 0 || (__width <= 0 && __off != 0) || sync()) + if (__cv_ == 0 || !__bufptr_ || (__width <= 0 && __off != 0) || sync()) return pos_type(off_type(-1)); // __width > 0 || __off == 0, now check __way if (__way != ios_base::beg && __way != ios_base::cur && __way != ios_base::end) @@ -3601,7 +3601,7 @@ wbuffer_convert<_Codecvt, _Elem, _Tr>::seekoff(off_type __off, ios_base::seekdir template typename wbuffer_convert<_Codecvt, _Elem, _Tr>::pos_type wbuffer_convert<_Codecvt, _Elem, _Tr>::seekpos(pos_type __sp, ios_base::openmode __wch) { - if (__cv_ == 0 || __bufptr_ == 0 || sync()) + if (__cv_ == 0 || !__bufptr_ || sync()) return pos_type(off_type(-1)); if (__bufptr_->pubseekpos(__sp, __wch) == pos_type(off_type(-1))) return pos_type(off_type(-1)); @@ -3611,7 +3611,7 @@ wbuffer_convert<_Codecvt, _Elem, _Tr>::seekpos(pos_type __sp, ios_base::openmode template int wbuffer_convert<_Codecvt, _Elem, _Tr>::sync() { _LIBCPP_SUPPRESS_DEPRECATED_POP - if (__cv_ == 0 || __bufptr_ == 0) + if (__cv_ == 0 || !__bufptr_) return 0; if (__cm_ & ios_base::out) { if (this->pptr() != this->pbase()) diff --git a/libcxx/include/memory b/libcxx/include/memory index ee245d5fd2d..19c11ee9498 100644 --- a/libcxx/include/memory +++ b/libcxx/include/memory @@ -139,7 +139,7 @@ public: template struct rebind {typedef allocator other;}; // deprecated in C++17, removed in C++20 typedef true_type propagate_on_container_move_assignment; - typedef true_type is_always_equal; + typedef true_type is_always_equal; // Deprecated in C++23, removed in C++26 constexpr allocator() noexcept; // constexpr in C++20 constexpr allocator(const allocator&) noexcept; // constexpr in C++20 diff --git a/libcxx/include/module.modulemap.in b/libcxx/include/module.modulemap.in index d10670d4faa..194a74a1e07 100644 --- a/libcxx/include/module.modulemap.in +++ b/libcxx/include/module.modulemap.in @@ -1580,6 +1580,7 @@ module std_private_numeric_pstl_transform_reduce [system] { export * } module std_private_numeric_reduce [system] { header "__numeric/reduce.h" } +module std_private_numeric_saturation_arithmetic [system] { header "__numeric/saturation_arithmetic.h" } module std_private_numeric_transform_exclusive_scan [system] { header "__numeric/transform_exclusive_scan.h" } module std_private_numeric_transform_inclusive_scan [system] { header "__numeric/transform_inclusive_scan.h" } module std_private_numeric_transform_reduce [system] { header "__numeric/transform_reduce.h" } diff --git a/libcxx/include/new b/libcxx/include/new index 136adc41c24..86fbcb524b6 100644 --- a/libcxx/include/new +++ b/libcxx/include/new @@ -362,7 +362,6 @@ _LIBCPP_END_NAMESPACE_STD #if !defined(_LIBCPP_REMOVE_TRANSITIVE_INCLUDES) && _LIBCPP_STD_VER <= 20 # include -# include # include #endif diff --git a/libcxx/include/numeric b/libcxx/include/numeric index d09d0a81fcc..0fe7115f1c6 100644 --- a/libcxx/include/numeric +++ b/libcxx/include/numeric @@ -140,6 +140,18 @@ template template constexpr T* midpoint(T* a, T* b); // C++20 +// [numeric.sat], saturation arithmetic +template +constexpr T add_sat(T x, T y) noexcept; // freestanding, Since C++26 +template +constexpr T sub_sat(T x, T y) noexcept; // freestanding, Since C++26 +template +constexpr T mul_sat(T x, T y) noexcept; // freestanding, Since C++26 +template +constexpr T div_sat(T x, T y) noexcept; // freestanding, Since C++26 +template +constexpr T saturate_cast(U x) noexcept; // freestanding, Since C++26 + } // std */ @@ -160,6 +172,7 @@ template #include <__numeric/pstl_reduce.h> #include <__numeric/pstl_transform_reduce.h> #include <__numeric/reduce.h> +#include <__numeric/saturation_arithmetic.h> #include <__numeric/transform_exclusive_scan.h> #include <__numeric/transform_inclusive_scan.h> #include <__numeric/transform_reduce.h> diff --git a/libcxx/include/ostream b/libcxx/include/ostream index 88ee9d93a1d..e2b2c0cbaaf 100644 --- a/libcxx/include/ostream +++ b/libcxx/include/ostream @@ -175,8 +175,6 @@ void vprint_nonunicode(ostream& os, string_view fmt, format_args args); #include <__availability> #include <__config> #include <__exception/operations.h> -#include <__format/format_args.h> -#include <__format/format_functions.h> #include <__fwd/ostream.h> #include <__memory/shared_ptr.h> #include <__memory/unique_ptr.h> @@ -188,6 +186,7 @@ void vprint_nonunicode(ostream& os, string_view fmt, format_args args); #include <__utility/declval.h> #include #include +#include #include #include #include @@ -1084,12 +1083,15 @@ _LIBCPP_HIDE_FROM_ABI inline void vprint_nonunicode(ostream& __os, string_view _ // native Unicode API; // Whether the returned FILE* is "a terminal capable of displaying Unicode" // is determined in the same way as the print(FILE*, ...) overloads. -_LIBCPP_AVAILABILITY_PRINT _LIBCPP_EXPORTED_FROM_ABI FILE* __get_ostream_file(ostream& __os); +_LIBCPP_EXPORTED_FROM_ABI FILE* __get_ostream_file(ostream& __os); # ifndef _LIBCPP_HAS_NO_UNICODE template // TODO PRINT template or availability markup fires too eagerly (http://llvm.org/PR61563). -_LIBCPP_AVAILABILITY_PRINT _LIBCPP_HIDE_FROM_ABI void +_LIBCPP_HIDE_FROM_ABI void __vprint_unicode(ostream& __os, string_view __fmt, format_args __args, bool __write_nl) { +#if _LIBCPP_AVAILABILITY_HAS_PRINT == 0 + return std::__vprint_nonunicode(__os, __fmt, __args, __write_nl); +#else FILE* __file = std::__get_ostream_file(__os); if (!__file || !__print::__is_terminal(__file)) return std::__vprint_nonunicode(__os, __fmt, __args, __write_nl); @@ -1124,20 +1126,21 @@ __vprint_unicode(ostream& __os, string_view __fmt, format_args __args, bool __wr __os.__set_badbit_and_consider_rethrow(); } # endif // _LIBCPP_HAS_NO_EXCEPTIONS +#endif // _LIBCPP_AVAILABILITY_HAS_PRINT } template // TODO PRINT template or availability markup fires too eagerly (http://llvm.org/PR61563). -_LIBCPP_AVAILABILITY_PRINT _LIBCPP_HIDE_FROM_ABI inline void +_LIBCPP_HIDE_FROM_ABI inline void vprint_unicode(ostream& __os, string_view __fmt, format_args __args) { std::__vprint_unicode(__os, __fmt, __args, false); } # endif // _LIBCPP_HAS_NO_UNICODE template -_LIBCPP_AVAILABILITY_PRINT _LIBCPP_HIDE_FROM_ABI void +_LIBCPP_HIDE_FROM_ABI void print(ostream& __os, format_string<_Args...> __fmt, _Args&&... __args) { # ifndef _LIBCPP_HAS_NO_UNICODE - if constexpr (__print::__use_unicode) + if constexpr (__print::__use_unicode_execution_charset) std::__vprint_unicode(__os, __fmt.get(), std::make_format_args(__args...), false); else std::__vprint_nonunicode(__os, __fmt.get(), std::make_format_args(__args...), false); @@ -1147,13 +1150,13 @@ print(ostream& __os, format_string<_Args...> __fmt, _Args&&... __args) { } template -_LIBCPP_AVAILABILITY_PRINT _LIBCPP_HIDE_FROM_ABI void +_LIBCPP_HIDE_FROM_ABI void println(ostream& __os, format_string<_Args...> __fmt, _Args&&... __args) { # ifndef _LIBCPP_HAS_NO_UNICODE // Note the wording in the Standard is inefficient. The output of // std::format is a std::string which is then copied. This solution // just appends a newline at the end of the output. - if constexpr (__print::__use_unicode) + if constexpr (__print::__use_unicode_execution_charset) std::__vprint_unicode(__os, __fmt.get(), std::make_format_args(__args...), true); else std::__vprint_nonunicode(__os, __fmt.get(), std::make_format_args(__args...), true); diff --git a/libcxx/include/print b/libcxx/include/print index 5e00fc87f47..7f2b5bac3dc 100644 --- a/libcxx/include/print +++ b/libcxx/include/print @@ -34,17 +34,11 @@ namespace std { #include <__assert> // all public C++ headers provide the assertion handler #include <__concepts/same_as.h> #include <__config> -#include <__format/buffer.h> -#include <__format/format_arg_store.h> -#include <__format/format_args.h> -#include <__format/format_context.h> -#include <__format/format_error.h> -#include <__format/format_functions.h> -#include <__format/unicode.h> #include <__system_error/system_error.h> #include <__utility/forward.h> #include #include +#include #include #include #include @@ -192,13 +186,13 @@ namespace __print { // # ifdef _LIBCPP_HAS_NO_UNICODE -inline constexpr bool __use_unicode = false; +inline constexpr bool __use_unicode_execution_charset = false; # elif defined(_MSVC_EXECUTION_CHARACTER_SET) // This is the same test MSVC STL uses in their implementation of // See: https://learn.microsoft.com/en-us/windows/win32/intl/code-page-identifiers -inline constexpr bool __use_unicode = _MSVC_EXECUTION_CHARACTER_SET == 65001; +inline constexpr bool __use_unicode_execution_charset = _MSVC_EXECUTION_CHARACTER_SET == 65001; # else -inline constexpr bool __use_unicode = true; +inline constexpr bool __use_unicode_execution_charset = true; # endif _LIBCPP_HIDE_FROM_ABI inline bool __is_terminal(FILE* __stream) { @@ -333,7 +327,7 @@ __vprint_unicode([[maybe_unused]] FILE* __stream, template _LIBCPP_HIDE_FROM_ABI void print(FILE* __stream, format_string<_Args...> __fmt, _Args&&... __args) { # ifndef _LIBCPP_HAS_NO_UNICODE - if constexpr (__print::__use_unicode) + if constexpr (__print::__use_unicode_execution_charset) __print::__vprint_unicode(__stream, __fmt.get(), std::make_format_args(__args...), false); else __print::__vprint_nonunicode(__stream, __fmt.get(), std::make_format_args(__args...), false); @@ -353,7 +347,7 @@ _LIBCPP_HIDE_FROM_ABI void println(FILE* __stream, format_string<_Args...> __fmt // Note the wording in the Standard is inefficient. The output of // std::format is a std::string which is then copied. This solution // just appends a newline at the end of the output. - if constexpr (__print::__use_unicode) + if constexpr (__print::__use_unicode_execution_charset) __print::__vprint_unicode(__stream, __fmt.get(), std::make_format_args(__args...), true); else __print::__vprint_nonunicode(__stream, __fmt.get(), std::make_format_args(__args...), true); diff --git a/libcxx/include/regex b/libcxx/include/regex index 0761d9de54a..48af5b8b57f 100644 --- a/libcxx/include/regex +++ b/libcxx/include/regex @@ -1889,9 +1889,6 @@ void __r_anchor_multiline<_CharT>::__exec(__state& __s) const { if (__s.__current_ == __s.__last_ && !(__s.__flags_ & regex_constants::match_not_eol)) { __s.__do_ = __state::__accept_but_not_consume; __s.__node_ = this->first(); - } else if (__s.__current_ == __s.__first_ && !(__s.__flags_ & regex_constants::match_not_eol)) { - __s.__do_ = __state::__accept_but_not_consume; - __s.__node_ = this->first(); } else if (__multiline_ && std::__is_eol(*__s.__current_)) { __s.__do_ = __state::__accept_but_not_consume; __s.__node_ = this->first(); @@ -5127,6 +5124,14 @@ bool basic_regex<_CharT, _Traits>::__search( } __m.__matches_.assign(__m.size(), __m.__unmatched_); } + __m.__matches_.assign(__m.size(), __m.__unmatched_); + if (__match_at_start(__first, __last, __m, __flags, false)) { + __m.__prefix_.second = __m[0].first; + __m.__prefix_.matched = __m.__prefix_.first != __m.__prefix_.second; + __m.__suffix_.first = __m[0].second; + __m.__suffix_.matched = __m.__suffix_.first != __m.__suffix_.second; + return true; + } } __m.__matches_.clear(); return false; diff --git a/libcxx/include/semaphore b/libcxx/include/semaphore index de45b8b5db1..ac3d2d7fe02 100644 --- a/libcxx/include/semaphore +++ b/libcxx/include/semaphore @@ -45,13 +45,18 @@ using binary_semaphore = counting_semaphore<1>; */ +#include <__config> + +#ifdef _LIBCPP_HAS_NO_THREADS +# error " is not supported since libc++ has been configured without support for threads." +#endif + #include <__assert> // all public C++ headers provide the assertion handler #include <__atomic/atomic_base.h> #include <__atomic/atomic_sync.h> #include <__atomic/memory_order.h> #include <__availability> #include <__chrono/time_point.h> -#include <__config> #include <__thread/poll_with_backoff.h> #include <__thread/timed_backoff_policy.h> #include <__threading_support> @@ -63,10 +68,6 @@ using binary_semaphore = counting_semaphore<1>; # pragma GCC system_header #endif -#ifdef _LIBCPP_HAS_NO_THREADS -# error " is not supported since libc++ has been configured without support for threads." -#endif - _LIBCPP_PUSH_MACROS #include <__undef_macros> @@ -91,7 +92,7 @@ public: _LIBCPP_HIDE_FROM_ABI constexpr explicit __atomic_semaphore_base(ptrdiff_t __count) : __a_(__count) {} _LIBCPP_AVAILABILITY_SYNC _LIBCPP_HIDE_FROM_ABI void release(ptrdiff_t __update = 1) { auto __old = __a_.fetch_add(__update, memory_order_release); - _LIBCPP_ASSERT_UNCATEGORIZED( + _LIBCPP_ASSERT_ARGUMENT_WITHIN_DOMAIN( __update <= _LIBCPP_SEMAPHORE_MAX - __old, "update is greater than the expected value"); if (__old > 0) { @@ -137,11 +138,11 @@ public: static constexpr ptrdiff_t max() noexcept { return __least_max_value; } _LIBCPP_HIDE_FROM_ABI constexpr explicit counting_semaphore(ptrdiff_t __count) : __semaphore_(__count) { - _LIBCPP_ASSERT_UNCATEGORIZED( + _LIBCPP_ASSERT_ARGUMENT_WITHIN_DOMAIN( __count >= 0, "counting_semaphore::counting_semaphore(ptrdiff_t): counting_semaphore cannot be " "initialized with a negative value"); - _LIBCPP_ASSERT_UNCATEGORIZED( + _LIBCPP_ASSERT_ARGUMENT_WITHIN_DOMAIN( __count <= max(), "counting_semaphore::counting_semaphore(ptrdiff_t): counting_semaphore cannot be " "initialized with a value greater than max()"); @@ -152,7 +153,7 @@ public: counting_semaphore& operator=(const counting_semaphore&) = delete; _LIBCPP_AVAILABILITY_SYNC _LIBCPP_HIDE_FROM_ABI void release(ptrdiff_t __update = 1) { - _LIBCPP_ASSERT_UNCATEGORIZED(__update >= 0, "counting_semaphore:release called with a negative value"); + _LIBCPP_ASSERT_ARGUMENT_WITHIN_DOMAIN(__update >= 0, "counting_semaphore:release called with a negative value"); __semaphore_.release(__update); } _LIBCPP_AVAILABILITY_SYNC _LIBCPP_HIDE_FROM_ABI void acquire() { __semaphore_.acquire(); } diff --git a/libcxx/include/shared_mutex b/libcxx/include/shared_mutex index 1528d108d74..ac66b3a568b 100644 --- a/libcxx/include/shared_mutex +++ b/libcxx/include/shared_mutex @@ -122,13 +122,18 @@ template */ +#include <__config> + +# ifdef _LIBCPP_HAS_NO_THREADS +# error " is not supported since libc++ has been configured without support for threads." +# endif + #include <__assert> // all public C++ headers provide the assertion handler #include <__availability> #include <__chrono/duration.h> #include <__chrono/steady_clock.h> #include <__chrono/time_point.h> #include <__condition_variable/condition_variable.h> -#include <__config> #include <__memory/addressof.h> #include <__mutex/mutex.h> #include <__mutex/tag_types.h> @@ -147,10 +152,6 @@ _LIBCPP_PUSH_MACROS # pragma GCC system_header # endif -# ifdef _LIBCPP_HAS_NO_THREADS -# error " is not supported since libc++ has been configured without support for threads." -# endif - _LIBCPP_BEGIN_NAMESPACE_STD struct _LIBCPP_EXPORTED_FROM_ABI __shared_mutex_base { diff --git a/libcxx/include/span b/libcxx/include/span index 007a32597f9..32364b4270b 100644 --- a/libcxx/include/span +++ b/libcxx/include/span @@ -68,6 +68,7 @@ public: constexpr span(const array& arr) noexcept; template constexpr explicit(Extent != dynamic_extent) span(R&& r); + constexpr explicit(extent != dynamic_extent) span(std::initializer_list il); // Since C++26 constexpr span(const span& other) noexcept = default; template constexpr explicit(Extent != dynamic_extent) span(const span& s) noexcept; @@ -228,6 +229,15 @@ public: requires(_Sz == 0) _LIBCPP_HIDE_FROM_ABI constexpr span() noexcept : __data_{nullptr} {} +# if _LIBCPP_STD_VER >= 26 + _LIBCPP_HIDE_FROM_ABI constexpr explicit span(std::initializer_list __il) + requires is_const_v + : __data_{__il.begin()} { + _LIBCPP_ASSERT_VALID_INPUT_RANGE( + _Extent == __il.size(), "Size mismatch in span's constructor _Extent != __il.size()."); + } +# endif + constexpr span(const span&) noexcept = default; constexpr span& operator=(const span&) noexcept = default; @@ -397,6 +407,12 @@ public: // [span.cons], span constructors, copy, assignment, and destructor _LIBCPP_HIDE_FROM_ABI constexpr span() noexcept : __data_{nullptr}, __size_{0} {} +# if _LIBCPP_STD_VER >= 26 + _LIBCPP_HIDE_FROM_ABI constexpr span(std::initializer_list __il) + requires is_const_v + : __data_{__il.begin()}, __size_{__il.size()} {} +# endif + constexpr span(const span&) noexcept = default; constexpr span& operator=(const span&) noexcept = default; diff --git a/libcxx/include/sstream b/libcxx/include/sstream index 9f75b7e0ac9..6c354cf0b39 100644 --- a/libcxx/include/sstream +++ b/libcxx/include/sstream @@ -1108,7 +1108,7 @@ _LIBCPP_END_NAMESPACE_STD _LIBCPP_POP_MACROS -#if _LIBCPP_STD_VER <= 20 && !defined(_LIPCPP_REMOVE_TRANSITIVE_INCLUDES) +#if _LIBCPP_STD_VER <= 20 && !defined(_LIBCPP_REMOVE_TRANSITIVE_INCLUDES) # include #endif diff --git a/libcxx/include/stop_token b/libcxx/include/stop_token index b223ceb27f0..66c7a6ab599 100644 --- a/libcxx/include/stop_token +++ b/libcxx/include/stop_token @@ -31,8 +31,13 @@ namespace std { */ -#include <__assert> // all public C++ headers provide the assertion handler #include <__config> + +#ifdef _LIBCPP_HAS_NO_THREADS +# error " is not supported since libc++ has been configured without support for threads." +#endif + +#include <__assert> // all public C++ headers provide the assertion handler #include <__stop_token/stop_callback.h> #include <__stop_token/stop_source.h> #include <__stop_token/stop_token.h> @@ -42,10 +47,6 @@ namespace std { # pragma GCC system_header #endif -#ifdef _LIBCPP_HAS_NO_THREADS -# error " is not supported since libc++ has been configured without support for threads." -#endif - #if !defined(_LIBCPP_REMOVE_TRANSITIVE_INCLUDES) && _LIBCPP_STD_VER <= 20 # include #endif diff --git a/libcxx/include/string b/libcxx/include/string index c676182fba8..e97139206d4 100644 --- a/libcxx/include/string +++ b/libcxx/include/string @@ -922,7 +922,7 @@ public: // Turning off ASan instrumentation for variable initialization with _LIBCPP_STRING_INTERNAL_MEMORY_ACCESS // does not work consistently during initialization of __r_, so we instead unpoison __str's memory manually first. // __str's memory needs to be unpoisoned only in the case where it's a short string. - : __r_(((__str.__is_long() ? 0 : (__str.__annotate_delete(), 0)), std::move(__str.__r_))) { + : __r_([](basic_string &__s) -> decltype(__s.__r_)&& { if(!__s.__is_long()) __s.__annotate_delete(); return std::move(__s.__r_); }(__str)) { __str.__r_.first() = __rep(); __str.__annotate_new(0); if (!__is_long()) @@ -1891,8 +1891,7 @@ private: #if !defined(_LIBCPP_HAS_NO_ASAN) && defined(_LIBCPP_INSTRUMENTED_WITH_ASAN) const void* __begin = data(); const void* __end = data() + capacity() + 1; - if (!__libcpp_is_constant_evaluated() && __begin != nullptr && - is_same::value) + if (__asan_annotate_container_with_allocator::value && !__libcpp_is_constant_evaluated()) __sanitizer_annotate_contiguous_container(__begin, __end, __old_mid, __new_mid); #endif } diff --git a/libcxx/include/string_view b/libcxx/include/string_view index 909224fe7e3..e414507a793 100644 --- a/libcxx/include/string_view +++ b/libcxx/include/string_view @@ -307,8 +307,11 @@ public: : __data_(__s), __size_(__len) { #if _LIBCPP_STD_VER >= 14 - _LIBCPP_ASSERT_UNCATEGORIZED(__len <= static_cast(numeric_limits::max()), - "string_view::string_view(_CharT *, size_t): length does not fit in difference_type"); + // This will result in creating an invalid `string_view` object -- some calculations involving `size` would + // overflow, making it effectively truncated. + _LIBCPP_ASSERT_ARGUMENT_WITHIN_DOMAIN( + __len <= static_cast(numeric_limits::max()), + "string_view::string_view(_CharT *, size_t): length does not fit in difference_type"); _LIBCPP_ASSERT_NON_NULL( __len == 0 || __s != nullptr, "string_view::string_view(_CharT *, size_t): received nullptr"); #endif diff --git a/libcxx/include/thread b/libcxx/include/thread index 1cf22bf6aaf..84c80d04cf0 100644 --- a/libcxx/include/thread +++ b/libcxx/include/thread @@ -86,9 +86,14 @@ void sleep_for(const chrono::duration& rel_time); */ +#include <__config> + +#ifdef _LIBCPP_HAS_NO_THREADS +# error " is not supported since libc++ has been configured without support for threads." +#endif + #include <__assert> // all public C++ headers provide the assertion handler #include <__availability> -#include <__config> #include <__thread/formatter.h> #include <__thread/jthread.h> #include <__thread/this_thread.h> @@ -105,10 +110,6 @@ void sleep_for(const chrono::duration& rel_time); # pragma GCC system_header #endif -#ifdef _LIBCPP_HAS_NO_THREADS -# error " is not supported since libc++ has been configured without support for threads." -#endif - #if !defined(_LIBCPP_REMOVE_TRANSITIVE_INCLUDES) # include # include diff --git a/libcxx/include/typeinfo b/libcxx/include/typeinfo index 39a90676cc4..1144b5b1291 100644 --- a/libcxx/include/typeinfo +++ b/libcxx/include/typeinfo @@ -372,7 +372,6 @@ _LIBCPP_END_NAMESPACE_STD #if !defined(_LIBCPP_REMOVE_TRANSITIVE_INCLUDES) && _LIBCPP_STD_VER <= 20 # include -# include # include #endif diff --git a/libcxx/include/variant b/libcxx/include/variant index 6179b2a1a0a..6063739e52c 100644 --- a/libcxx/include/variant +++ b/libcxx/include/variant @@ -69,6 +69,12 @@ namespace std { // 20.7.2.6, swap void swap(variant&) noexcept(see below); + + // [variant.visit], visitation + template + constexpr decltype(auto) visit(this Self&&, Visitor&&); // Since C++26 + template + constexpr R visit(this Self&&, Visitor&&); // Since C++26 }; // 20.7.3, variant helper classes @@ -235,6 +241,7 @@ namespace std { #include <__type_traits/void_t.h> #include <__utility/declval.h> #include <__utility/forward.h> +#include <__utility/forward_like.h> #include <__utility/in_place.h> #include <__utility/move.h> #include <__utility/swap.h> @@ -801,14 +808,15 @@ protected: _LIBCPP_HIDE_FROM_ABI static void __generic_construct(__ctor& __lhs, _Rhs&& __rhs) { __lhs.__destroy(); if (!__rhs.valueless_by_exception()) { + auto __rhs_index = __rhs.index(); __visitation::__base::__visit_alt_at( - __rhs.index(), + __rhs_index, [](auto& __lhs_alt, auto&& __rhs_alt) { __construct_alt(__lhs_alt, std::forward(__rhs_alt).__value); }, __lhs, std::forward<_Rhs>(__rhs)); - __lhs.__index = __rhs.index(); + __lhs.__index = __rhs_index; } } }; @@ -1130,6 +1138,19 @@ using __best_match_t = typename invoke_result_t<_MakeOverloads<_Types...>, _Tp, } // namespace __variant_detail +template ()))...>> +_LIBCPP_HIDE_FROM_ABI _LIBCPP_AVAILABILITY_THROW_BAD_VARIANT_ACCESS constexpr decltype(auto) +visit(_Visitor&& __visitor, _Vs&&... __vs); + +# if _LIBCPP_STD_VER >= 20 +template ()))...>> +_LIBCPP_HIDE_FROM_ABI _LIBCPP_AVAILABILITY_THROW_BAD_VARIANT_ACCESS constexpr _Rp +visit(_Visitor&& __visitor, _Vs&&... __vs); +# endif + template class _LIBCPP_TEMPLATE_VIS _LIBCPP_DECLSPEC_EMPTY_BASES variant : private __sfinae_ctor_base< __all...>::value, @@ -1273,6 +1294,27 @@ public: __impl_.__swap(__that.__impl_); } +# if _LIBCPP_STD_VER >= 26 && defined(_LIBCPP_HAS_EXPLICIT_THIS_PARAMETER) + // Helper class to implement [variant.visit]/10 + // Constraints: The call to visit does not use an explicit template-argument-list + // that begins with a type template-argument. + struct __variant_visit_barrier_tag { + _LIBCPP_HIDE_FROM_ABI explicit __variant_visit_barrier_tag() = default; + }; + + template <__variant_visit_barrier_tag = __variant_visit_barrier_tag{}, class _Self, class _Visitor> + _LIBCPP_HIDE_FROM_ABI constexpr decltype(auto) visit(this _Self&& __self, _Visitor&& __visitor) { + using _VariantT = _OverrideRef<_Self&&, _CopyConst, variant>>; + return std::visit(std::forward<_Visitor>(__visitor), (_VariantT)__self); + } + + template + _LIBCPP_HIDE_FROM_ABI constexpr _Rp visit(this _Self&& __self, _Visitor&& __visitor) { + using _VariantT = _OverrideRef<_Self&&, _CopyConst, variant>>; + return std::visit<_Rp>(std::forward<_Visitor>(__visitor), (_VariantT)__self); + } +# endif + private: __variant_detail::__impl<_Types...> __impl_; @@ -1511,7 +1553,7 @@ _LIBCPP_HIDE_FROM_ABI _LIBCPP_AVAILABILITY_THROW_BAD_VARIANT_ACCESS constexpr vo } } -template < class _Visitor, class... _Vs, typename = void_t()))...> > +template < class _Visitor, class... _Vs, typename> _LIBCPP_HIDE_FROM_ABI _LIBCPP_AVAILABILITY_THROW_BAD_VARIANT_ACCESS constexpr decltype(auto) visit(_Visitor&& __visitor, _Vs&&... __vs) { using __variant_detail::__visitation::__variant; @@ -1520,10 +1562,7 @@ visit(_Visitor&& __visitor, _Vs&&... __vs) { } # if _LIBCPP_STD_VER >= 20 -template < class _Rp, - class _Visitor, - class... _Vs, - typename = void_t()))...> > +template < class _Rp, class _Visitor, class... _Vs, typename> _LIBCPP_HIDE_FROM_ABI _LIBCPP_AVAILABILITY_THROW_BAD_VARIANT_ACCESS constexpr _Rp visit(_Visitor&& __visitor, _Vs&&... __vs) { using __variant_detail::__visitation::__variant; diff --git a/libcxx/include/vector b/libcxx/include/vector index 0098273a195..e9dd57055cb 100644 --- a/libcxx/include/vector +++ b/libcxx/include/vector @@ -832,12 +832,12 @@ private: // the documentation for __sanitizer_annotate_contiguous_container. _LIBCPP_CONSTEXPR_SINCE_CXX20 _LIBCPP_HIDE_FROM_ABI void __annotate_contiguous_container( - const void* __beg, const void* __end, const void* __old_mid, const void* __new_mid) const { - (void)__beg; - (void)__end; + const void* __old_mid, const void* __new_mid) const { (void)__old_mid; (void)__new_mid; #ifndef _LIBCPP_HAS_NO_ASAN + const void* __beg = data(); + const void* __end = data() + capacity(); if (!__libcpp_is_constant_evaluated() && __beg != nullptr && __asan_annotate_container_with_allocator<_Allocator>::value) __sanitizer_annotate_contiguous_container(__beg, __end, __old_mid, __new_mid); @@ -847,27 +847,27 @@ private: _LIBCPP_CONSTEXPR_SINCE_CXX20 _LIBCPP_HIDE_FROM_ABI void __annotate_new(size_type __current_size) const _NOEXCEPT { (void)__current_size; #ifndef _LIBCPP_HAS_NO_ASAN - __annotate_contiguous_container(data(), data() + capacity(), data() + capacity(), data() + __current_size); + __annotate_contiguous_container(data() + capacity(), data() + __current_size); #endif } _LIBCPP_CONSTEXPR_SINCE_CXX20 _LIBCPP_HIDE_FROM_ABI void __annotate_delete() const _NOEXCEPT { #ifndef _LIBCPP_HAS_NO_ASAN - __annotate_contiguous_container(data(), data() + capacity(), data() + size(), data() + capacity()); + __annotate_contiguous_container(data() + size(), data() + capacity()); #endif } _LIBCPP_CONSTEXPR_SINCE_CXX20 _LIBCPP_HIDE_FROM_ABI void __annotate_increase(size_type __n) const _NOEXCEPT { (void)__n; #ifndef _LIBCPP_HAS_NO_ASAN - __annotate_contiguous_container(data(), data() + capacity(), data() + size(), data() + size() + __n); + __annotate_contiguous_container(data() + size(), data() + size() + __n); #endif } _LIBCPP_CONSTEXPR_SINCE_CXX20 _LIBCPP_HIDE_FROM_ABI void __annotate_shrink(size_type __old_size) const _NOEXCEPT { (void)__old_size; #ifndef _LIBCPP_HAS_NO_ASAN - __annotate_contiguous_container(data(), data() + capacity(), data() + __old_size, data() + size()); + __annotate_contiguous_container(data() + __old_size, data() + size()); #endif } diff --git a/libcxx/include/version b/libcxx/include/version index c96647894dc..9e26da8c1b2 100644 --- a/libcxx/include/version +++ b/libcxx/include/version @@ -504,10 +504,10 @@ __cpp_lib_within_lifetime 202306L // # define __cpp_lib_out_ptr 202311L # define __cpp_lib_ratio 202306L // # define __cpp_lib_rcu 202306L -// # define __cpp_lib_saturation_arithmetic 202311L +# define __cpp_lib_saturation_arithmetic 202311L // # define __cpp_lib_smart_ptr_owner_equality 202306L # define __cpp_lib_span_at 202311L -// # define __cpp_lib_span_initializer_list 202311L +# define __cpp_lib_span_initializer_list 202311L // # define __cpp_lib_sstream_from_string_view 202306L // # define __cpp_lib_submdspan 202306L // # define __cpp_lib_text_encoding 202306L diff --git a/libcxx/modules/modules.json.in b/libcxx/modules/modules.json.in new file mode 100644 index 00000000000..ddc377f28f9 --- /dev/null +++ b/libcxx/modules/modules.json.in @@ -0,0 +1,26 @@ +{ + "version": 1, + "revision": 1, + "modules": [ + { + "logical-name": "std", + "source-path": "@LIBCXX_MODULE_RELATIVE_PATH@/std.cppm", + "is-standard-library": true, + "local-arguments": { + "system-include-directories": [ + "@LIBCXX_MODULE_RELATIVE_PATH@" + ] + } + }, + { + "logical-name": "std.compat", + "source-path": "@LIBCXX_MODULE_RELATIVE_PATH@/std.compat.cppm", + "is-std-library": true, + "local-arguments": { + "system-include-directories": [ + "@LIBCXX_MODULE_RELATIVE_PATH@" + ] + } + } + ] +} diff --git a/libcxx/modules/std.compat.cppm.in b/libcxx/modules/std.compat.cppm.in index f199e194e60..651d6ec7b9f 100644 --- a/libcxx/modules/std.compat.cppm.in +++ b/libcxx/modules/std.compat.cppm.in @@ -17,38 +17,17 @@ module; // The headers of Table 24: C++ library headers [tab:headers.cpp] // and the headers of Table 25: C++ headers for C library facilities [tab:headers.cpp.c] -#include -#include -#include -#if !defined(_LIBCPP_HAS_NO_ATOMIC_HEADER) -# include -#endif -#if !defined(_LIBCPP_HAS_NO_THREADS) -# include -#endif -#include -#include #include #include #include #include #include -#include -#include #include #include #if !defined(_LIBCPP_HAS_NO_LOCALIZATION) # include #endif #include -#if !defined(_LIBCPP_HAS_NO_LOCALIZATION) -# include -#endif -#include -#include -#include -#include -#include #include #include #include @@ -65,107 +44,6 @@ module; #if !defined(_LIBCPP_HAS_NO_WIDE_CHARACTERS) # include #endif -#include -#include -#include -#include -#include -#include -#include -#if !defined(_LIBCPP_HAS_NO_LOCALIZATION) -# include -#endif -#include -#if !defined(_LIBCPP_HAS_NO_THREADS) -# include -#endif -#include -#if !defined(_LIBCPP_HAS_NO_LOCALIZATION) -# include -#endif -#if !defined(_LIBCPP_HAS_NO_LOCALIZATION) -# include -#endif -#include -#if !defined(_LIBCPP_HAS_NO_LOCALIZATION) -# include -#endif -#if !defined(_LIBCPP_HAS_NO_LOCALIZATION) -# include -#endif -#include -#if !defined(_LIBCPP_HAS_NO_THREADS) -# include -#endif -#include -#include -#if !defined(_LIBCPP_HAS_NO_LOCALIZATION) -# include -#endif -#include -#include -#include -#include -#include -#include -#include -#include -#include -#if !defined(_LIBCPP_HAS_NO_LOCALIZATION) -# include -#endif -#include -#include -#include -#include -#include -#if !defined(_LIBCPP_HAS_NO_LOCALIZATION) -# include -#endif -#include -#if !defined(_LIBCPP_HAS_NO_THREADS) -# include -#endif -#include -#if !defined(_LIBCPP_HAS_NO_THREADS) -# include -#endif -#include -#include -#if !defined(_LIBCPP_HAS_NO_LOCALIZATION) -# include -#endif -#include -#include -#if !defined(_LIBCPP_HAS_NO_THREADS) -# include -#endif -#if !defined(_LIBCPP_HAS_NO_LOCALIZATION) -# include -#endif -#include -#include -#if !defined(_LIBCPP_HAS_NO_LOCALIZATION) -# include -#endif -#if !defined(_LIBCPP_HAS_NO_LOCALIZATION) -# include -#endif -#include -#if !defined(_LIBCPP_HAS_NO_THREADS) -# include -#endif -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include // *** Headers not yet available *** #if __has_include() @@ -203,6 +81,7 @@ module; #endif // __has_include() export module std.compat; +export import std; + -@LIBCXX_MODULE_STD_INCLUDE_SOURCES@ @LIBCXX_MODULE_STD_COMPAT_INCLUDE_SOURCES@ \ No newline at end of file diff --git a/libcxx/modules/std.compat/cstdlib.inc b/libcxx/modules/std.compat/cstdlib.inc index 9333d848707..a45a0a1caf8 100644 --- a/libcxx/modules/std.compat/cstdlib.inc +++ b/libcxx/modules/std.compat/cstdlib.inc @@ -16,10 +16,10 @@ export { // [support.start.term], start and termination using ::_Exit; using ::abort; - using ::at_quick_exit; + using ::at_quick_exit _LIBCPP_USING_IF_EXISTS; using ::atexit; using ::exit; - using ::quick_exit; + using ::quick_exit _LIBCPP_USING_IF_EXISTS; using ::getenv; using ::system; diff --git a/libcxx/modules/std.compat/ctime.inc b/libcxx/modules/std.compat/ctime.inc index 92e3403a5e5..6e621f49434 100644 --- a/libcxx/modules/std.compat/ctime.inc +++ b/libcxx/modules/std.compat/ctime.inc @@ -24,5 +24,5 @@ export { using ::mktime; using ::strftime; using ::time; - using ::timespec_get; + using ::timespec_get _LIBCPP_USING_IF_EXISTS; } // export diff --git a/libcxx/modules/std.cppm.in b/libcxx/modules/std.cppm.in index b46c52e781f..6ce8e287737 100644 --- a/libcxx/modules/std.cppm.in +++ b/libcxx/modules/std.cppm.in @@ -204,4 +204,5 @@ module; export module std; + @LIBCXX_MODULE_STD_INCLUDE_SOURCES@ diff --git a/libcxx/modules/std/ctime.inc b/libcxx/modules/std/ctime.inc index c407ffc35e3..c98cb28e649 100644 --- a/libcxx/modules/std/ctime.inc +++ b/libcxx/modules/std/ctime.inc @@ -24,5 +24,5 @@ export namespace std { using std::mktime; using std::strftime; using std::time; - using std::timespec_get; + using std::timespec_get _LIBCPP_USING_IF_EXISTS; } // namespace std diff --git a/libcxx/modules/std/memory.inc b/libcxx/modules/std/memory.inc index fba2461732c..ef89845457f 100644 --- a/libcxx/modules/std/memory.inc +++ b/libcxx/modules/std/memory.inc @@ -156,7 +156,9 @@ export namespace std { using std::reinterpret_pointer_cast; using std::static_pointer_cast; +#ifndef _LIBCPP_HAS_NO_RTTI using std::get_deleter; +#endif // _LIBCPP_HAS_NO_RTTI // [util.smartptr.shared.io], shared_ptr I/O diff --git a/libcxx/modules/std/numeric.inc b/libcxx/modules/std/numeric.inc index d2b7688d4e5..3bc7b231681 100644 --- a/libcxx/modules/std/numeric.inc +++ b/libcxx/modules/std/numeric.inc @@ -54,4 +54,14 @@ export namespace std { // [numeric.ops.midpoint], midpoint using std::midpoint; + +#if _LIBCPP_STD_VER >= 26 + // [numeric.sat], saturation arithmetic + using std::add_sat; + using std::div_sat; + using std::mul_sat; + using std::saturate_cast; + using std::sub_sat; +#endif + } // namespace std diff --git a/libcxx/src/filesystem/operations.cpp b/libcxx/src/filesystem/operations.cpp index 6bee340e0d1..6253d1551b0 100644 --- a/libcxx/src/filesystem/operations.cpp +++ b/libcxx/src/filesystem/operations.cpp @@ -460,8 +460,21 @@ path __current_path(error_code* ec) { typedef decltype(&::free) Deleter; Deleter deleter = &::free; #else + errno = 0; // Note: POSIX mandates that modifying `errno` is thread-safe. auto size = ::pathconf(".", _PC_PATH_MAX); - _LIBCPP_ASSERT_UNCATEGORIZED(size >= 0, "pathconf returned a 0 as max size"); + if (size == -1) { + if (errno != 0) { + return err.report(capture_errno(), "call to pathconf failed"); + + // `pathconf` returns `-1` without an error to indicate no limit. + } else { +# if defined(__MVS__) && !defined(PATH_MAX) + size = _XOPEN_PATH_MAX + 1; +# else + size = PATH_MAX + 1; +# endif + } + } auto buff = unique_ptr(new path::value_type[size + 1]); path::value_type* ptr = buff.get(); @@ -608,10 +621,9 @@ void __permissions(const path& p, perms prms, perm_options opts, error_code* ec) const bool resolve_symlinks = !has_opt(perm_options::nofollow); const bool add_perms = has_opt(perm_options::add); const bool remove_perms = has_opt(perm_options::remove); - _LIBCPP_ASSERT_UNCATEGORIZED( + _LIBCPP_ASSERT_ARGUMENT_WITHIN_DOMAIN( (add_perms + remove_perms + has_opt(perm_options::replace)) == 1, - "One and only one of the perm_options constants replace, add, or remove " - "is present in opts"); + "One and only one of the perm_options constants 'replace', 'add', or 'remove' must be present in opts"); bool set_sym_perms = false; prms &= perms::mask; @@ -621,7 +633,9 @@ void __permissions(const path& p, perms prms, perm_options opts, error_code* ec) set_sym_perms = is_symlink(st); if (m_ec) return err.report(m_ec); - _LIBCPP_ASSERT_UNCATEGORIZED(st.permissions() != perms::unknown, "Permissions unexpectedly unknown"); + // TODO(hardening): double-check this assertion -- it might be a valid (if rare) case when the permissions are + // unknown. + _LIBCPP_ASSERT_VALID_EXTERNAL_API_CALL(st.permissions() != perms::unknown, "Permissions unexpectedly unknown"); if (add_perms) prms |= st.permissions(); else if (remove_perms) @@ -668,7 +682,7 @@ path __read_symlink(const path& p, error_code* ec) { detail::SSizeT ret; if ((ret = detail::readlink(p.c_str(), buff.get(), size)) == -1) return err.report(capture_errno()); - _LIBCPP_ASSERT_UNCATEGORIZED(ret > 0, "TODO"); + // Note that `ret` returning `0` would work, resulting in a valid empty string being returned. if (static_cast(ret) >= size) return err.report(errc::value_too_large); buff[ret] = 0; diff --git a/libcxx/src/include/overridable_function.h b/libcxx/src/include/overridable_function.h new file mode 100644 index 00000000000..7b0fba10f47 --- /dev/null +++ b/libcxx/src/include/overridable_function.h @@ -0,0 +1,119 @@ +// -*- C++ -*- +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +#ifndef _LIBCPP_SRC_INCLUDE_OVERRIDABLE_FUNCTION_H +#define _LIBCPP_SRC_INCLUDE_OVERRIDABLE_FUNCTION_H + +#include <__config> +#include + +#if !defined(_LIBCPP_HAS_NO_PRAGMA_SYSTEM_HEADER) +# pragma GCC system_header +#endif + +// +// This file provides the std::__is_function_overridden utility, which allows checking +// whether an overridable function (typically a weak symbol) like `operator new` +// has been overridden by a user or not. +// +// This is a low-level utility which does not work on all platforms, since it needs +// to make assumptions about the object file format in use. Furthermore, it requires +// the "base definition" of the function (the one we want to check whether it has been +// overridden) to be annotated with the _LIBCPP_MAKE_OVERRIDABLE_FUNCTION_DETECTABLE macro. +// +// This currently works with Mach-O files (used on Darwin) and with ELF files (used on Linux +// and others). On platforms where we know how to implement this detection, the macro +// _LIBCPP_CAN_DETECT_OVERRIDDEN_FUNCTION is defined to 1, and it is defined to 0 on +// other platforms. The _LIBCPP_MAKE_OVERRIDABLE_FUNCTION_DETECTABLE macro is defined to +// nothing on unsupported platforms so that it can be used to decorate functions regardless +// of whether detection is actually supported. +// +// How does this work? +// ------------------- +// +// Let's say we want to check whether a weak function `f` has been overridden by the user. +// The general mechanism works by placing `f`'s definition (in the libc++ built library) +// inside a special section, which we do using the `__section__` attribute via the +// _LIBCPP_MAKE_OVERRIDABLE_FUNCTION_DETECTABLE macro. +// +// Then, when comes the time to check whether the function has been overridden, we take +// the address of the function and we check whether it falls inside the special function +// we created. This can be done by finding pointers to the start and the end of the section +// (which is done differently for ELF and Mach-O), and then checking whether `f` falls +// within those bounds. If it falls within those bounds, then `f` is still inside the +// special section and so it is the version we defined in the libc++ built library, i.e. +// it was not overridden. Otherwise, it was overridden by the user because it falls +// outside of the section. +// +// Important note +// -------------- +// +// This mechanism should never be used outside of the libc++ built library. In particular, +// attempting to use this within the libc++ headers will not work at all because we don't +// want to be defining special sections inside user's executables which use our headers. +// This is provided inside libc++'s include tree solely to make it easier to share with +// libc++abi, which needs the same mechanism. +// + +#if defined(_LIBCPP_OBJECT_FORMAT_MACHO) + +# define _LIBCPP_CAN_DETECT_OVERRIDDEN_FUNCTION 1 +# define _LIBCPP_MAKE_OVERRIDABLE_FUNCTION_DETECTABLE \ + __attribute__((__section__("__TEXT,__lcxx_override,regular,pure_instructions"))) + +_LIBCPP_BEGIN_NAMESPACE_STD +template +_LIBCPP_HIDE_FROM_ABI bool __is_function_overridden(_Ret (*__fptr)(_Args...)) noexcept { + // Declare two dummy bytes and give them these special `__asm` values. These values are + // defined by the linker, which means that referring to `&__lcxx_override_start` will + // effectively refer to the address where the section starts (and same for the end). + extern char __lcxx_override_start __asm("section$start$__TEXT$__lcxx_override"); + extern char __lcxx_override_end __asm("section$end$__TEXT$__lcxx_override"); + + // Now get a uintptr_t out of these locations, and out of the function pointer. + uintptr_t __start = reinterpret_cast(&__lcxx_override_start); + uintptr_t __end = reinterpret_cast(&__lcxx_override_end); + uintptr_t __ptr = reinterpret_cast(__fptr); + + // Finally, the function was overridden if it falls outside of the section's bounds. + return __ptr < __start || __ptr > __end; +} +_LIBCPP_END_NAMESPACE_STD + +#elif defined(_LIBCPP_OBJECT_FORMAT_ELF) + +# define _LIBCPP_CAN_DETECT_OVERRIDDEN_FUNCTION 1 +# define _LIBCPP_MAKE_OVERRIDABLE_FUNCTION_DETECTABLE __attribute__((__section__("__lcxx_override"))) + +// This is very similar to what we do for Mach-O above. The ELF linker will implicitly define +// variables with those names corresponding to the start and the end of the section. +// +// See https://stackoverflow.com/questions/16552710/how-do-you-get-the-start-and-end-addresses-of-a-custom-elf-section +extern char __start___lcxx_override; +extern char __stop___lcxx_override; + +_LIBCPP_BEGIN_NAMESPACE_STD +template +_LIBCPP_HIDE_FROM_ABI bool __is_function_overridden(_Ret (*__fptr)(_Args...)) noexcept { + uintptr_t __start = reinterpret_cast(&__start___lcxx_override); + uintptr_t __end = reinterpret_cast(&__stop___lcxx_override); + uintptr_t __ptr = reinterpret_cast(__fptr); + + return __ptr < __start || __ptr > __end; +} +_LIBCPP_END_NAMESPACE_STD + +#else + +# define _LIBCPP_CAN_DETECT_OVERRIDDEN_FUNCTION 0 +# define _LIBCPP_MAKE_OVERRIDABLE_FUNCTION_DETECTABLE /* nothing */ + +#endif + +#endif // _LIBCPP_SRC_INCLUDE_OVERRIDABLE_FUNCTION_H diff --git a/libcxx/src/include/to_chars_floating_point.h b/libcxx/src/include/to_chars_floating_point.h index e4715d10d97..01c26181697 100644 --- a/libcxx/src/include/to_chars_floating_point.h +++ b/libcxx/src/include/to_chars_floating_point.h @@ -994,7 +994,7 @@ to_chars_result _Floating_to_chars( if constexpr (_Overload == _Floating_to_chars_overload::_Plain) { _LIBCPP_ASSERT_INTERNAL(_Fmt == chars_format{}, ""); // plain overload must pass chars_format{} internally } else { - _LIBCPP_ASSERT_UNCATEGORIZED(_Fmt == chars_format::general || _Fmt == chars_format::scientific + _LIBCPP_ASSERT_ARGUMENT_WITHIN_DOMAIN(_Fmt == chars_format::general || _Fmt == chars_format::scientific || _Fmt == chars_format::fixed || _Fmt == chars_format::hex, "invalid format in to_chars()"); } diff --git a/libcxx/src/memory_resource.cpp b/libcxx/src/memory_resource.cpp index 42c366893f7..2117238e634 100644 --- a/libcxx/src/memory_resource.cpp +++ b/libcxx/src/memory_resource.cpp @@ -189,7 +189,8 @@ void unsynchronized_pool_resource::__adhoc_pool::__do_deallocate( return; } } - _LIBCPP_ASSERT_UNCATEGORIZED(false, "deallocating a block that was not allocated with this allocator"); + // The request to deallocate memory ends up being a no-op, likely resulting in a memory leak. + _LIBCPP_ASSERT_VALID_DEALLOCATION(false, "deallocating a block that was not allocated with this allocator"); } } diff --git a/libcxx/src/mutex.cpp b/libcxx/src/mutex.cpp index ce854757ac0..2f8504d602d 100644 --- a/libcxx/src/mutex.cpp +++ b/libcxx/src/mutex.cpp @@ -36,7 +36,8 @@ bool mutex::try_lock() noexcept { return __libcpp_mutex_trylock(&__m_); } void mutex::unlock() noexcept { int ec = __libcpp_mutex_unlock(&__m_); (void)ec; - _LIBCPP_ASSERT_UNCATEGORIZED(ec == 0, "call to mutex::unlock failed"); + _LIBCPP_ASSERT_VALID_EXTERNAL_API_CALL( + ec == 0, "call to mutex::unlock failed. A possible reason is that the mutex wasn't locked"); } // recursive_mutex @@ -50,7 +51,7 @@ recursive_mutex::recursive_mutex() { recursive_mutex::~recursive_mutex() { int e = __libcpp_recursive_mutex_destroy(&__m_); (void)e; - _LIBCPP_ASSERT_UNCATEGORIZED(e == 0, "call to ~recursive_mutex() failed"); + _LIBCPP_ASSERT_VALID_EXTERNAL_API_CALL(e == 0, "call to ~recursive_mutex() failed"); } void recursive_mutex::lock() { @@ -62,7 +63,8 @@ void recursive_mutex::lock() { void recursive_mutex::unlock() noexcept { int e = __libcpp_recursive_mutex_unlock(&__m_); (void)e; - _LIBCPP_ASSERT_UNCATEGORIZED(e == 0, "call to recursive_mutex::unlock() failed"); + _LIBCPP_ASSERT_VALID_EXTERNAL_API_CALL( + e == 0, "call to recursive_mutex::unlock() failed. A possible reason is that the mutex wasn't locked"); } bool recursive_mutex::try_lock() noexcept { return __libcpp_recursive_mutex_trylock(&__m_); } diff --git a/libcxx/src/new.cpp b/libcxx/src/new.cpp index 033bba5c1fc..0869d90661d 100644 --- a/libcxx/src/new.cpp +++ b/libcxx/src/new.cpp @@ -6,7 +6,9 @@ // //===----------------------------------------------------------------------===// +#include "include/overridable_function.h" #include <__memory/aligned_alloc.h> +#include #include #include @@ -15,12 +17,16 @@ // The code below is copied as-is into libc++abi's libcxxabi/src/stdlib_new_delete.cpp // file. The version in this file is the canonical one. +inline void __throw_bad_alloc_shim() { std::__throw_bad_alloc(); } + +# define _LIBCPP_ASSERT_SHIM(expr, str) _LIBCPP_ASSERT(expr, str) + // ------------------ BEGIN COPY ------------------ // Implement all new and delete operators as weak definitions // in this shared library, so that they can be overridden by programs // that define non-weak copies of the functions. -static void* operator_new_impl(std::size_t size) noexcept { +static void* operator_new_impl(std::size_t size) { if (size == 0) size = 1; void* p; @@ -36,41 +42,63 @@ static void* operator_new_impl(std::size_t size) noexcept { return p; } -_LIBCPP_WEAK void* operator new(std::size_t size) _THROW_BAD_ALLOC { +_LIBCPP_MAKE_OVERRIDABLE_FUNCTION_DETECTABLE _LIBCPP_WEAK void* operator new(std::size_t size) _THROW_BAD_ALLOC { void* p = operator_new_impl(size); -# ifndef _LIBCPP_HAS_NO_EXCEPTIONS if (p == nullptr) - throw std::bad_alloc(); -# endif + __throw_bad_alloc_shim(); return p; } _LIBCPP_WEAK void* operator new(size_t size, const std::nothrow_t&) noexcept { +# ifdef _LIBCPP_HAS_NO_EXCEPTIONS +# if _LIBCPP_CAN_DETECT_OVERRIDDEN_FUNCTION + _LIBCPP_ASSERT_SHIM( + !std::__is_function_overridden(static_cast(&operator new)), + "libc++ was configured with exceptions disabled and `operator new(size_t)` has been overridden, " + "but `operator new(size_t, nothrow_t)` has not been overridden. This is problematic because " + "`operator new(size_t, nothrow_t)` must call `operator new(size_t)`, which will terminate in case " + "it fails to allocate, making it impossible for `operator new(size_t, nothrow_t)` to fulfill its " + "contract (since it should return nullptr upon failure). Please make sure you override " + "`operator new(size_t, nothrow_t)` as well."); +# endif + + return operator_new_impl(size); +# else void* p = nullptr; -# ifndef _LIBCPP_HAS_NO_EXCEPTIONS try { -# endif // _LIBCPP_HAS_NO_EXCEPTIONS p = ::operator new(size); -# ifndef _LIBCPP_HAS_NO_EXCEPTIONS } catch (...) { } -# endif // _LIBCPP_HAS_NO_EXCEPTIONS return p; +# endif } -_LIBCPP_WEAK void* operator new[](size_t size) _THROW_BAD_ALLOC { return ::operator new(size); } +_LIBCPP_MAKE_OVERRIDABLE_FUNCTION_DETECTABLE _LIBCPP_WEAK void* operator new[](size_t size) _THROW_BAD_ALLOC { + return ::operator new(size); +} _LIBCPP_WEAK void* operator new[](size_t size, const std::nothrow_t&) noexcept { +# ifdef _LIBCPP_HAS_NO_EXCEPTIONS +# if _LIBCPP_CAN_DETECT_OVERRIDDEN_FUNCTION + _LIBCPP_ASSERT_SHIM( + !std::__is_function_overridden(static_cast(&operator new[])), + "libc++ was configured with exceptions disabled and `operator new[](size_t)` has been overridden, " + "but `operator new[](size_t, nothrow_t)` has not been overridden. This is problematic because " + "`operator new[](size_t, nothrow_t)` must call `operator new[](size_t)`, which will terminate in case " + "it fails to allocate, making it impossible for `operator new[](size_t, nothrow_t)` to fulfill its " + "contract (since it should return nullptr upon failure). Please make sure you override " + "`operator new[](size_t, nothrow_t)` as well."); +# endif + + return operator_new_impl(size); +# else void* p = nullptr; -# ifndef _LIBCPP_HAS_NO_EXCEPTIONS try { -# endif // _LIBCPP_HAS_NO_EXCEPTIONS p = ::operator new[](size); -# ifndef _LIBCPP_HAS_NO_EXCEPTIONS } catch (...) { } -# endif // _LIBCPP_HAS_NO_EXCEPTIONS return p; +# endif } _LIBCPP_WEAK void operator delete(void* ptr) noexcept { std::free(ptr); } @@ -87,7 +115,7 @@ _LIBCPP_WEAK void operator delete[](void* ptr, size_t) noexcept { ::operator del # if !defined(_LIBCPP_HAS_NO_LIBRARY_ALIGNED_ALLOCATION) -static void* operator_new_aligned_impl(std::size_t size, std::align_val_t alignment) noexcept { +static void* operator_new_aligned_impl(std::size_t size, std::align_val_t alignment) { if (size == 0) size = 1; if (static_cast(alignment) < sizeof(void*)) @@ -107,43 +135,66 @@ static void* operator_new_aligned_impl(std::size_t size, std::align_val_t alignm return p; } -_LIBCPP_WEAK void* operator new(std::size_t size, std::align_val_t alignment) _THROW_BAD_ALLOC { +_LIBCPP_MAKE_OVERRIDABLE_FUNCTION_DETECTABLE _LIBCPP_WEAK void* +operator new(std::size_t size, std::align_val_t alignment) _THROW_BAD_ALLOC { void* p = operator_new_aligned_impl(size, alignment); -# ifndef _LIBCPP_HAS_NO_EXCEPTIONS if (p == nullptr) - throw std::bad_alloc(); -# endif + __throw_bad_alloc_shim(); return p; } _LIBCPP_WEAK void* operator new(size_t size, std::align_val_t alignment, const std::nothrow_t&) noexcept { +# ifdef _LIBCPP_HAS_NO_EXCEPTIONS +# if _LIBCPP_CAN_DETECT_OVERRIDDEN_FUNCTION + _LIBCPP_ASSERT_SHIM( + !std::__is_function_overridden(static_cast(&operator new)), + "libc++ was configured with exceptions disabled and `operator new(size_t, align_val_t)` has been overridden, " + "but `operator new(size_t, align_val_t, nothrow_t)` has not been overridden. This is problematic because " + "`operator new(size_t, align_val_t, nothrow_t)` must call `operator new(size_t, align_val_t)`, which will " + "terminate in case it fails to allocate, making it impossible for `operator new(size_t, align_val_t, nothrow_t)` " + "to fulfill its contract (since it should return nullptr upon failure). Please make sure you override " + "`operator new(size_t, align_val_t, nothrow_t)` as well."); +# endif + + return operator_new_aligned_impl(size, alignment); +# else void* p = nullptr; -# ifndef _LIBCPP_HAS_NO_EXCEPTIONS try { -# endif // _LIBCPP_HAS_NO_EXCEPTIONS p = ::operator new(size, alignment); -# ifndef _LIBCPP_HAS_NO_EXCEPTIONS } catch (...) { } -# endif // _LIBCPP_HAS_NO_EXCEPTIONS return p; +# endif } -_LIBCPP_WEAK void* operator new[](size_t size, std::align_val_t alignment) _THROW_BAD_ALLOC { +_LIBCPP_MAKE_OVERRIDABLE_FUNCTION_DETECTABLE _LIBCPP_WEAK void* +operator new[](size_t size, std::align_val_t alignment) _THROW_BAD_ALLOC { return ::operator new(size, alignment); } _LIBCPP_WEAK void* operator new[](size_t size, std::align_val_t alignment, const std::nothrow_t&) noexcept { +# ifdef _LIBCPP_HAS_NO_EXCEPTIONS +# if _LIBCPP_CAN_DETECT_OVERRIDDEN_FUNCTION + _LIBCPP_ASSERT_SHIM( + !std::__is_function_overridden(static_cast(&operator new[])), + "libc++ was configured with exceptions disabled and `operator new[](size_t, align_val_t)` has been overridden, " + "but `operator new[](size_t, align_val_t, nothrow_t)` has not been overridden. This is problematic because " + "`operator new[](size_t, align_val_t, nothrow_t)` must call `operator new[](size_t, align_val_t)`, which will " + "terminate in case it fails to allocate, making it impossible for `operator new[](size_t, align_val_t, " + "nothrow_t)` to fulfill its contract (since it should return nullptr upon failure). Please make sure you " + "override " + "`operator new[](size_t, align_val_t, nothrow_t)` as well."); +# endif + + return operator_new_aligned_impl(size, alignment); +# else void* p = nullptr; -# ifndef _LIBCPP_HAS_NO_EXCEPTIONS try { -# endif // _LIBCPP_HAS_NO_EXCEPTIONS p = ::operator new[](size, alignment); -# ifndef _LIBCPP_HAS_NO_EXCEPTIONS } catch (...) { } -# endif // _LIBCPP_HAS_NO_EXCEPTIONS return p; +# endif } _LIBCPP_WEAK void operator delete(void* ptr, std::align_val_t) noexcept { std::__libcpp_aligned_free(ptr); } diff --git a/libcxx/src/ostream.cpp b/libcxx/src/ostream.cpp index bba8e655071..443dce9a390 100644 --- a/libcxx/src/ostream.cpp +++ b/libcxx/src/ostream.cpp @@ -17,7 +17,7 @@ _LIBCPP_BEGIN_NAMESPACE_STD -_LIBCPP_AVAILABILITY_PRINT _LIBCPP_EXPORTED_FROM_ABI FILE* __get_ostream_file(ostream& __os) { +_LIBCPP_EXPORTED_FROM_ABI FILE* __get_ostream_file(ostream& __os) { // dynamic_cast requires RTTI, this only affects users whose vendor builds // the dylib with RTTI disabled. It does not affect users who build with RTTI // disabled but use a dylib where the RTTI is enabled. diff --git a/libcxx/src/support/runtime/exception_pointer_cxxabi.ipp b/libcxx/src/support/runtime/exception_pointer_cxxabi.ipp index c07de5838b1..bdb17b9996b 100644 --- a/libcxx/src/support/runtime/exception_pointer_cxxabi.ipp +++ b/libcxx/src/support/runtime/exception_pointer_cxxabi.ipp @@ -28,6 +28,14 @@ exception_ptr& exception_ptr::operator=(const exception_ptr& other) noexcept { return *this; } +exception_ptr exception_ptr::__from_native_exception_pointer(void* __e) noexcept { + exception_ptr ptr; + ptr.__ptr_ = __e; + __cxa_increment_exception_refcount(ptr.__ptr_); + + return ptr; +} + nested_exception::nested_exception() noexcept : __ptr_(current_exception()) {} nested_exception::~nested_exception() noexcept {} diff --git a/libcxx/src/support/runtime/exception_pointer_glibcxx.ipp b/libcxx/src/support/runtime/exception_pointer_glibcxx.ipp index 8e0e63cd4d4..6dad248f9e1 100644 --- a/libcxx/src/support/runtime/exception_pointer_glibcxx.ipp +++ b/libcxx/src/support/runtime/exception_pointer_glibcxx.ipp @@ -23,6 +23,7 @@ namespace __exception_ptr { struct exception_ptr { void* __ptr_; + explicit exception_ptr(void*) noexcept; exception_ptr(const exception_ptr&) noexcept; exception_ptr& operator=(const exception_ptr&) noexcept; ~exception_ptr() noexcept; @@ -45,6 +46,13 @@ exception_ptr& exception_ptr::operator=(const exception_ptr& other) noexcept { return *this; } +exception_ptr exception_ptr::__from_native_exception_pointer(void* __e) noexcept { + exception_ptr ptr{}; + new (reinterpret_cast(&ptr)) __exception_ptr::exception_ptr(__e); + + return ptr; +} + nested_exception::nested_exception() noexcept : __ptr_(current_exception()) {} _LIBCPP_NORETURN void nested_exception::rethrow_nested() const { diff --git a/libcxx/src/support/runtime/exception_pointer_unimplemented.ipp b/libcxx/src/support/runtime/exception_pointer_unimplemented.ipp index de0605d7774..e12b0caf419 100644 --- a/libcxx/src/support/runtime/exception_pointer_unimplemented.ipp +++ b/libcxx/src/support/runtime/exception_pointer_unimplemented.ipp @@ -30,6 +30,12 @@ exception_ptr& exception_ptr::operator=(const exception_ptr& other) noexcept { ::abort(); } +exception_ptr exception_ptr::__from_native_exception_pointer(void *__e) noexcept { +#warning exception_ptr not yet implemented + fprintf(stderr, "exception_ptr not yet implemented\n"); + ::abort(); +} + nested_exception::nested_exception() noexcept : __ptr_(current_exception()) {} #if !defined(__GLIBCXX__) diff --git a/libcxx/vendor/llvm/default_assertion_handler.in b/libcxx/vendor/llvm/default_assertion_handler.in new file mode 100644 index 00000000000..8bc0553c078 --- /dev/null +++ b/libcxx/vendor/llvm/default_assertion_handler.in @@ -0,0 +1,31 @@ +// -*- C++ -*- +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +#ifndef _LIBCPP___ASSERTION_HANDLER +#define _LIBCPP___ASSERTION_HANDLER + +#include <__config> +#include <__verbose_abort> + +#if !defined(_LIBCPP_HAS_NO_PRAGMA_SYSTEM_HEADER) +# pragma GCC system_header +#endif + +#if _LIBCPP_HARDENING_MODE == _LIBCPP_HARDENING_MODE_DEBUG + +# define _LIBCPP_ASSERTION_HANDLER(message) _LIBCPP_VERBOSE_ABORT("%s", message) + +#else + +// TODO(hardening): use `__builtin_verbose_trap(message)` once that becomes available. +# define _LIBCPP_ASSERTION_HANDLER(message) ((void)message, __builtin_trap()) + +#endif // _LIBCPP_HARDENING_MODE == _LIBCPP_HARDENING_MODE_DEBUG + +#endif // _LIBCPP___ASSERTION_HANDLER diff --git a/libunwind/src/UnwindCursor.hpp b/libunwind/src/UnwindCursor.hpp index 8517d328bd0..7753936a589 100644 --- a/libunwind/src/UnwindCursor.hpp +++ b/libunwind/src/UnwindCursor.hpp @@ -12,8 +12,6 @@ #define __UNWINDCURSOR_HPP__ #include "cet_unwind.h" -#include -#include #include #include #include @@ -35,6 +33,8 @@ #if defined(_LIBUNWIND_TARGET_LINUX) && \ (defined(_LIBUNWIND_TARGET_AARCH64) || defined(_LIBUNWIND_TARGET_RISCV) || \ defined(_LIBUNWIND_TARGET_S390X)) +#include +#include #include #include #include diff --git a/libunwind/src/libunwind.cpp b/libunwind/src/libunwind.cpp index cd610377b63..217dde90986 100644 --- a/libunwind/src/libunwind.cpp +++ b/libunwind/src/libunwind.cpp @@ -26,7 +26,7 @@ #include #endif -#if !defined(__USING_SJLJ_EXCEPTIONS__) || !defined(__USING_WASM_EXCEPTIONS__) +#if !defined(__USING_SJLJ_EXCEPTIONS__) && !defined(__USING_WASM_EXCEPTIONS__) #include "AddressSpace.hpp" #include "UnwindCursor.hpp" @@ -324,7 +324,7 @@ void __unw_add_dynamic_eh_frame_section(unw_word_t eh_frame_start) { CFI_Parser::CIE_Info cieInfo; CFI_Parser::FDE_Info fdeInfo; auto p = (LocalAddressSpace::pint_t)eh_frame_start; - while (true) { + while (LocalAddressSpace::sThisAddressSpace.get32(p)) { if (CFI_Parser::decodeFDE( LocalAddressSpace::sThisAddressSpace, p, &fdeInfo, &cieInfo, true) == NULL) { @@ -347,7 +347,7 @@ void __unw_remove_dynamic_eh_frame_section(unw_word_t eh_frame_start) { } #endif // defined(_LIBUNWIND_SUPPORT_DWARF_UNWIND) -#endif // !defined(__USING_SJLJ_EXCEPTIONS__) || +#endif // !defined(__USING_SJLJ_EXCEPTIONS__) && // !defined(__USING_WASM_EXCEPTIONS__) #ifdef __APPLE__ diff --git a/lld/COFF/Driver.cpp b/lld/COFF/Driver.cpp index cd2985b035b..e0afb6b1880 100644 --- a/lld/COFF/Driver.cpp +++ b/lld/COFF/Driver.cpp @@ -855,7 +855,7 @@ static std::string createResponseFile(const opt::InputArgList &args, for (StringRef path : filePaths) os << quote(relativeToRoot(path)) << "\n"; - return std::string(data.str()); + return std::string(data); } static unsigned parseDebugTypes(const opt::InputArgList &args) { @@ -910,7 +910,7 @@ std::string LinkerDriver::getImplibPath() { return std::string(ctx.config.implib); SmallString<128> out = StringRef(ctx.config.outputFile); sys::path::replace_extension(out, ".lib"); - return std::string(out.str()); + return std::string(out); } // The import name is calculated as follows: @@ -934,7 +934,7 @@ std::string LinkerDriver::getImportName(bool asLib) { (ctx.config.dll || asLib) ? ".dll" : ".exe"); } - return std::string(out.str()); + return std::string(out); } void LinkerDriver::createImportLibrary(bool asLib) { @@ -1548,15 +1548,13 @@ void LinkerDriver::linkerMain(ArrayRef argsArr) { { llvm::TimeTraceScope timeScope2("Search paths"); searchPaths.emplace_back(""); + for (auto *arg : args.filtered(OPT_libpath)) + searchPaths.push_back(arg->getValue()); if (!config->mingw) { // Prefer the Clang provided builtins over the ones bundled with MSVC. // In MinGW mode, the compiler driver passes the necessary libpath // options explicitly. addClangLibSearchPaths(argsArr[0]); - } - for (auto *arg : args.filtered(OPT_libpath)) - searchPaths.push_back(arg->getValue()); - if (!config->mingw) { // Don't automatically deduce the lib path from the environment or MSVC // installations when operating in mingw mode. (This also makes LLD ignore // winsysroot and vctoolsdir arguments.) diff --git a/lld/COFF/DriverUtils.cpp b/lld/COFF/DriverUtils.cpp index ab10e2d1ae7..fc8eb327be4 100644 --- a/lld/COFF/DriverUtils.cpp +++ b/lld/COFF/DriverUtils.cpp @@ -310,13 +310,11 @@ void LinkerDriver::parseManifestUAC(StringRef arg) { arg = arg.ltrim(); if (arg.empty()) return; - if (arg.starts_with_insensitive("level=")) { - arg = arg.substr(strlen("level=")); + if (arg.consume_front_insensitive("level=")) { std::tie(ctx.config.manifestLevel, arg) = arg.split(" "); continue; } - if (arg.starts_with_insensitive("uiaccess=")) { - arg = arg.substr(strlen("uiaccess=")); + if (arg.consume_front_insensitive("uiaccess=")) { std::tie(ctx.config.manifestUIAccess, arg) = arg.split(" "); continue; } @@ -352,7 +350,7 @@ public: SmallString<128> s; if (auto ec = sys::fs::createTemporaryFile("lld-" + prefix, extn, s)) fatal("cannot create a temporary file: " + ec.message()); - path = std::string(s.str()); + path = std::string(s); if (!contents.empty()) { std::error_code ec; diff --git a/lld/COFF/InputFiles.cpp b/lld/COFF/InputFiles.cpp index cd744800cb0..1ed90d74229 100644 --- a/lld/COFF/InputFiles.cpp +++ b/lld/COFF/InputFiles.cpp @@ -828,7 +828,7 @@ static std::string getPdbBaseName(ObjFile *file, StringRef tSPath) { // on Windows, so we can assume type server paths are Windows style. sys::path::append(path, sys::path::filename(tSPath, sys::path::Style::windows)); - return std::string(path.str()); + return std::string(path); } // The casing of the PDB path stamped in the OBJ can differ from the actual path @@ -1081,7 +1081,7 @@ void BitcodeFile::parse() { if (objSym.isUsed()) ctx.config.gcroot.push_back(sym); } - directives = obj->getCOFFLinkerOpts(); + directives = saver.save(obj->getCOFFLinkerOpts()); } void BitcodeFile::parseLazy() { diff --git a/lld/COFF/Writer.cpp b/lld/COFF/Writer.cpp index 2e34a6c5cfa..9c20bbb83d8 100644 --- a/lld/COFF/Writer.cpp +++ b/lld/COFF/Writer.cpp @@ -1802,6 +1802,8 @@ void Writer::createSEHTable() { // symbol's offset into that Chunk. static void addSymbolToRVASet(SymbolRVASet &rvaSet, Defined *s) { Chunk *c = s->getChunk(); + if (!c) + return; if (auto *sc = dyn_cast(c)) c = sc->repl; // Look through ICF replacement. uint32_t off = s->getRVA() - (c ? c->getRVA() : 0); diff --git a/lld/Common/Args.cpp b/lld/Common/Args.cpp index 48c934df3a2..5546b2aece6 100644 --- a/lld/Common/Args.cpp +++ b/lld/Common/Args.cpp @@ -31,8 +31,8 @@ static int64_t getInteger(opt::InputArgList &args, unsigned key, int64_t v; StringRef s = a->getValue(); - if (base == 16 && (s.starts_with("0x") || s.starts_with("0X"))) - s = s.drop_front(2); + if (base == 16) + s.consume_front_insensitive("0x"); if (to_integer(s, v, base)) return v; @@ -60,17 +60,16 @@ SmallVector lld::args::getStrings(opt::InputArgList &args, } uint64_t lld::args::getZOptionValue(opt::InputArgList &args, int id, - StringRef key, uint64_t Default) { - for (auto *arg : args.filtered_reverse(id)) { + StringRef key, uint64_t defaultValue) { + for (auto *arg : args.filtered(id)) { std::pair kv = StringRef(arg->getValue()).split('='); if (kv.first == key) { - uint64_t result = Default; - if (!to_integer(kv.second, result)) + if (!to_integer(kv.second, defaultValue)) error("invalid " + key + ": " + kv.second); - return result; + arg->claim(); } } - return Default; + return defaultValue; } std::vector lld::args::getLines(MemoryBufferRef mb) { diff --git a/lld/Common/DriverDispatcher.cpp b/lld/Common/DriverDispatcher.cpp index 379a4c6ddab..435acfd2776 100644 --- a/lld/Common/DriverDispatcher.cpp +++ b/lld/Common/DriverDispatcher.cpp @@ -16,7 +16,6 @@ #include "llvm/ADT/Twine.h" #include "llvm/Support/CommandLine.h" #include "llvm/Support/CrashRecoveryContext.h" -#include "llvm/Support/InitLLVM.h" #include "llvm/Support/Path.h" #include "llvm/Support/Process.h" #include "llvm/TargetParser/Host.h" diff --git a/lld/ELF/Arch/ARM.cpp b/lld/ELF/Arch/ARM.cpp index d34e74a11c6..687f9499009 100644 --- a/lld/ELF/Arch/ARM.cpp +++ b/lld/ELF/Arch/ARM.cpp @@ -1381,9 +1381,9 @@ template void elf::writeARMCmseImportLib() { // Copy the secure gateway entry symbols to the import library symbol table. for (auto &p : symtab.cmseSymMap) { Defined *d = cast(p.second.sym); - impSymTab->addSymbol(makeDefined(nullptr, d->getName(), d->computeBinding(), - /*stOther=*/0, STT_FUNC, d->getVA(), - d->getSize(), nullptr)); + impSymTab->addSymbol(makeDefined( + ctx.internalFile, d->getName(), d->computeBinding(), + /*stOther=*/0, STT_FUNC, d->getVA(), d->getSize(), nullptr)); } size_t idx = 0; diff --git a/lld/ELF/Arch/Mips.cpp b/lld/ELF/Arch/Mips.cpp index d6c70aeba95..b02ad10649d 100644 --- a/lld/ELF/Arch/Mips.cpp +++ b/lld/ELF/Arch/Mips.cpp @@ -771,12 +771,11 @@ template bool elf::isMipsPIC(const Defined *sym) { if (!sym->section) return false; - ObjFile *file = - cast(sym->section)->template getFile(); - if (!file) + InputFile *file = cast(sym->section)->file; + if (!file || file->isInternal()) return false; - return file->getObj().getHeader().e_flags & EF_MIPS_PIC; + return cast>(file)->getObj().getHeader().e_flags & EF_MIPS_PIC; } template TargetInfo *elf::getMipsTargetInfo() { diff --git a/lld/ELF/Arch/PPC64.cpp b/lld/ELF/Arch/PPC64.cpp index 097a5751477..de52f6a79a4 100644 --- a/lld/ELF/Arch/PPC64.cpp +++ b/lld/ELF/Arch/PPC64.cpp @@ -253,7 +253,7 @@ static bool addOptional(StringRef name, uint64_t value, Symbol *sym = symtab.find(name); if (!sym || sym->isDefined()) return false; - sym->resolve(Defined{/*file=*/nullptr, StringRef(), STB_GLOBAL, STV_HIDDEN, + sym->resolve(Defined{ctx.internalFile, StringRef(), STB_GLOBAL, STV_HIDDEN, STT_FUNC, value, /*size=*/0, /*section=*/nullptr}); defined.push_back(cast(sym)); diff --git a/lld/ELF/Arch/RISCV.cpp b/lld/ELF/Arch/RISCV.cpp index 8906de07373..d7d3d3e4781 100644 --- a/lld/ELF/Arch/RISCV.cpp +++ b/lld/ELF/Arch/RISCV.cpp @@ -731,8 +731,14 @@ static bool relax(InputSection &sec) { const uint64_t align = PowerOf2Ceil(r.addend + 2); // All bytes beyond the alignment boundary should be removed. remove = nextLoc - ((loc + align - 1) & -align); - assert(static_cast(remove) >= 0 && - "R_RISCV_ALIGN needs expanding the content"); + // If we can't satisfy this alignment, we've found a bad input. + if (LLVM_UNLIKELY(static_cast(remove) < 0)) { + errorOrWarn(getErrorLocation((const uint8_t*)loc) + + "insufficient padding bytes for " + lld::toString(r.type) + + ": " + Twine(r.addend) + " bytes available " + "for requested alignment of " + Twine(align) + " bytes"); + remove = 0; + } break; } case R_RISCV_CALL: diff --git a/lld/ELF/Arch/X86_64.cpp b/lld/ELF/Arch/X86_64.cpp index c28e01e4819..de459013595 100644 --- a/lld/ELF/Arch/X86_64.cpp +++ b/lld/ELF/Arch/X86_64.cpp @@ -403,10 +403,10 @@ RelExpr X86_64::getRelExpr(RelType type, const Symbol &s, } void X86_64::writeGotPltHeader(uint8_t *buf) const { - // The first entry holds the value of _DYNAMIC. It is not clear why that is - // required, but it is documented in the psabi and the glibc dynamic linker - // seems to use it (note that this is relevant for linking ld.so, not any - // other program). + // The first entry holds the link-time address of _DYNAMIC. It is documented + // in the psABI and glibc before Aug 2021 used the entry to compute run-time + // load address of the shared object (note that this is relevant for linking + // ld.so, not any other program). write64le(buf, mainPart->dynamic->getVA()); } diff --git a/lld/ELF/Config.h b/lld/ELF/Config.h index 56229334f9a..3a4a47d900f 100644 --- a/lld/ELF/Config.h +++ b/lld/ELF/Config.h @@ -473,6 +473,8 @@ struct Ctx { std::pair> backwardReferences; llvm::SmallSet auxiliaryFiles; + // InputFile for linker created symbols with no source location. + InputFile *internalFile; // True if SHT_LLVM_SYMPART is used. std::atomic hasSympart{false}; // True if there are TLS IE relocations. Set DF_STATIC_TLS if -shared. diff --git a/lld/ELF/Driver.cpp b/lld/ELF/Driver.cpp index 6bef09eeca0..f4b7d1c9d5b 100644 --- a/lld/ELF/Driver.cpp +++ b/lld/ELF/Driver.cpp @@ -105,6 +105,7 @@ void Ctx::reset() { whyExtractRecords.clear(); backwardReferences.clear(); auxiliaryFiles.clear(); + internalFile = nullptr; hasSympart.store(false, std::memory_order_relaxed); hasTlsIe.store(false, std::memory_order_relaxed); needsTlsLd.store(false, std::memory_order_relaxed); @@ -473,126 +474,95 @@ static const char *getReproduceOption(opt::InputArgList &args) { } static bool hasZOption(opt::InputArgList &args, StringRef key) { + bool ret = false; for (auto *arg : args.filtered(OPT_z)) - if (key == arg->getValue()) - return true; - return false; + if (key == arg->getValue()) { + ret = true; + arg->claim(); + } + return ret; } static bool getZFlag(opt::InputArgList &args, StringRef k1, StringRef k2, - bool Default) { - for (auto *arg : args.filtered_reverse(OPT_z)) { - if (k1 == arg->getValue()) - return true; - if (k2 == arg->getValue()) - return false; + bool defaultValue) { + for (auto *arg : args.filtered(OPT_z)) { + StringRef v = arg->getValue(); + if (k1 == v) + defaultValue = true; + else if (k2 == v) + defaultValue = false; + else + continue; + arg->claim(); } - return Default; + return defaultValue; } static SeparateSegmentKind getZSeparate(opt::InputArgList &args) { - for (auto *arg : args.filtered_reverse(OPT_z)) { + auto ret = SeparateSegmentKind::None; + for (auto *arg : args.filtered(OPT_z)) { StringRef v = arg->getValue(); if (v == "noseparate-code") - return SeparateSegmentKind::None; - if (v == "separate-code") - return SeparateSegmentKind::Code; - if (v == "separate-loadable-segments") - return SeparateSegmentKind::Loadable; + ret = SeparateSegmentKind::None; + else if (v == "separate-code") + ret = SeparateSegmentKind::Code; + else if (v == "separate-loadable-segments") + ret = SeparateSegmentKind::Loadable; + else + continue; + arg->claim(); } - return SeparateSegmentKind::None; + return ret; } static GnuStackKind getZGnuStack(opt::InputArgList &args) { - for (auto *arg : args.filtered_reverse(OPT_z)) { - if (StringRef("execstack") == arg->getValue()) - return GnuStackKind::Exec; - if (StringRef("noexecstack") == arg->getValue()) - return GnuStackKind::NoExec; - if (StringRef("nognustack") == arg->getValue()) - return GnuStackKind::None; + auto ret = GnuStackKind::NoExec; + for (auto *arg : args.filtered(OPT_z)) { + StringRef v = arg->getValue(); + if (v == "execstack") + ret = GnuStackKind::Exec; + else if (v == "noexecstack") + ret = GnuStackKind::NoExec; + else if (v == "nognustack") + ret = GnuStackKind::None; + else + continue; + arg->claim(); } - - return GnuStackKind::NoExec; + return ret; } static uint8_t getZStartStopVisibility(opt::InputArgList &args) { - for (auto *arg : args.filtered_reverse(OPT_z)) { + uint8_t ret = STV_PROTECTED; + for (auto *arg : args.filtered(OPT_z)) { std::pair kv = StringRef(arg->getValue()).split('='); if (kv.first == "start-stop-visibility") { + arg->claim(); if (kv.second == "default") - return STV_DEFAULT; + ret = STV_DEFAULT; else if (kv.second == "internal") - return STV_INTERNAL; + ret = STV_INTERNAL; else if (kv.second == "hidden") - return STV_HIDDEN; + ret = STV_HIDDEN; else if (kv.second == "protected") - return STV_PROTECTED; - error("unknown -z start-stop-visibility= value: " + StringRef(kv.second)); + ret = STV_PROTECTED; + else + error("unknown -z start-stop-visibility= value: " + + StringRef(kv.second)); } } - return STV_PROTECTED; -} - -constexpr const char *knownZFlags[] = { - "combreloc", - "copyreloc", - "defs", - "execstack", - "force-bti", - "force-ibt", - "global", - "hazardplt", - "ifunc-noplt", - "initfirst", - "interpose", - "keep-text-section-prefix", - "lazy", - "muldefs", - "nocombreloc", - "nocopyreloc", - "nodefaultlib", - "nodelete", - "nodlopen", - "noexecstack", - "nognustack", - "nokeep-text-section-prefix", - "nopack-relative-relocs", - "norelro", - "noseparate-code", - "nostart-stop-gc", - "notext", - "now", - "origin", - "pac-plt", - "pack-relative-relocs", - "rel", - "rela", - "relro", - "retpolineplt", - "rodynamic", - "separate-code", - "separate-loadable-segments", - "shstk", - "start-stop-gc", - "text", - "undefs", - "wxneeded", -}; - -static bool isKnownZFlag(StringRef s) { - return llvm::is_contained(knownZFlags, s) || - s.starts_with("common-page-size=") || s.starts_with("bti-report=") || - s.starts_with("cet-report=") || - s.starts_with("dead-reloc-in-nonalloc=") || - s.starts_with("max-page-size=") || s.starts_with("stack-size=") || - s.starts_with("start-stop-visibility="); + return ret; } // Report a warning for an unknown -z option. static void checkZOptions(opt::InputArgList &args) { + // This function is called before getTarget(), when certain options are not + // initialized yet. Claim them here. + args::getZOptionValue(args, OPT_z, "max-page-size", 0); + args::getZOptionValue(args, OPT_z, "common-page-size", 0); + getZFlag(args, "rel", "rela", false); for (auto *arg : args.filtered(OPT_z)) - if (!isKnownZFlag(arg->getValue())) + if (!arg->isClaimed()) warn("unknown -z value: " + StringRef(arg->getValue())); } @@ -610,7 +580,6 @@ void LinkerDriver::linkerMain(ArrayRef argsArr) { args.hasFlag(OPT_fatal_warnings, OPT_no_fatal_warnings, false) && !args.hasArg(OPT_no_warnings); errorHandler().suppressWarnings = args.hasArg(OPT_no_warnings); - checkZOptions(args); // Handle -help if (args.hasArg(OPT_help)) { @@ -653,6 +622,7 @@ void LinkerDriver::linkerMain(ArrayRef argsArr) { } readConfigs(args); + checkZOptions(args); // The behavior of -v or --version is a bit strange, but this is // needed for compatibility with GNU linkers. @@ -734,6 +704,9 @@ static void setUnresolvedSymbolPolicy(opt::InputArgList &args) { diagRegular = true; else if (StringRef(arg->getValue()) == "undefs") diagRegular = false; + else + break; + arg->claim(); break; case OPT_allow_shlib_undefined: diagShlib = false; @@ -1081,7 +1054,11 @@ static void ltoValidateAllVtablesHaveTypeInfos(opt::InputArgList &args) { error("--lto-known-safe-vtables=: expected symbol to start with _ZTV, " "but got " + knownSafeName); - vtableSymbolsWithNoRTTI.remove(knownSafeName); + Expected pat = GlobPattern::create(knownSafeName); + if (!pat) + error("--lto-known-safe-vtables=: " + toString(pat.takeError())); + vtableSymbolsWithNoRTTI.remove_if( + [&](StringRef s) { return pat->match(s); }); } ctx.ltoAllVtablesHaveTypeInfos = vtableSymbolsWithNoRTTI.empty(); @@ -1158,20 +1135,22 @@ static SmallVector getSymbolOrderingFile(MemoryBufferRef mb) { } static bool getIsRela(opt::InputArgList &args) { + // The psABI specifies the default relocation entry format. + bool rela = is_contained({EM_AARCH64, EM_AMDGPU, EM_HEXAGON, EM_LOONGARCH, + EM_PPC, EM_PPC64, EM_RISCV, EM_X86_64}, + config->emachine); // If -z rel or -z rela is specified, use the last option. - for (auto *arg : args.filtered_reverse(OPT_z)) { + for (auto *arg : args.filtered(OPT_z)) { StringRef s(arg->getValue()); if (s == "rel") - return false; - if (s == "rela") - return true; + rela = false; + else if (s == "rela") + rela = true; + else + continue; + arg->claim(); } - - // Otherwise use the psABI defined relocation entry format. - uint16_t m = config->emachine; - return m == EM_AARCH64 || m == EM_AMDGPU || m == EM_HEXAGON || - m == EM_LOONGARCH || m == EM_PPC || m == EM_PPC64 || m == EM_RISCV || - m == EM_X86_64; + return rela; } static void parseClangOption(StringRef opt, const Twine &msg) { @@ -1216,9 +1195,9 @@ static void readConfigs(opt::InputArgList &args) { args.hasArg(OPT_visual_studio_diagnostics_format, false); config->allowMultipleDefinition = + hasZOption(args, "muldefs") || args.hasFlag(OPT_allow_multiple_definition, - OPT_no_allow_multiple_definition, false) || - hasZOption(args, "muldefs"); + OPT_no_allow_multiple_definition, false); config->androidMemtagHeap = args.hasFlag(OPT_android_memtag_heap, OPT_no_android_memtag_heap, false); config->androidMemtagStack = args.hasFlag(OPT_android_memtag_stack, @@ -1521,6 +1500,7 @@ static void readConfigs(opt::InputArgList &args) { for (auto reportArg : reports) { if (option.first != reportArg.first) continue; + arg->claim(); if (!isValidReportString(option.second)) { error(Twine("-z ") + reportArg.first + "= parameter " + option.second + " is not recognized"); @@ -1535,6 +1515,7 @@ static void readConfigs(opt::InputArgList &args) { StringRef(arg->getValue()).split('='); if (option.first != "dead-reloc-in-nonalloc") continue; + arg->claim(); constexpr StringRef errPrefix = "-z dead-reloc-in-nonalloc=: "; std::pair kv = option.second.split('='); if (kv.first.empty() || kv.second.empty()) { @@ -2077,13 +2058,7 @@ static void handleUndefinedGlob(StringRef arg) { static void handleLibcall(StringRef name) { Symbol *sym = symtab.find(name); - if (!sym || !sym->isLazy()) - return; - - MemoryBufferRef mb; - mb = cast(sym)->file->mb; - - if (isBitcode(mb)) + if (sym && sym->isLazy() && isa(sym->file)) sym->extract(); } @@ -2364,7 +2339,8 @@ static void readSymbolPartitionSection(InputSectionBase *s) { static Symbol *addUnusedUndefined(StringRef name, uint8_t binding = STB_GLOBAL) { - return symtab.addSymbol(Undefined{nullptr, name, binding, STV_DEFAULT, 0}); + return symtab.addSymbol( + Undefined{ctx.internalFile, name, binding, STV_DEFAULT, 0}); } static void markBuffersAsDontNeed(bool skipLinkedOutput) { @@ -2723,6 +2699,8 @@ void LinkerDriver::link(opt::InputArgList &args) { for (auto *arg : args.filtered(OPT_trace_symbol)) symtab.insert(arg->getValue())->traced = true; + ctx.internalFile = createInternalFile(""); + // Handle -u/--undefined before input files. If both a.a and b.so define foo, // -u foo a.a b.so will extract a.a. for (StringRef name : config->undefined) diff --git a/lld/ELF/DriverUtils.cpp b/lld/ELF/DriverUtils.cpp index 0a27422e3b2..de8ffab0e21 100644 --- a/lld/ELF/DriverUtils.cpp +++ b/lld/ELF/DriverUtils.cpp @@ -204,7 +204,7 @@ std::string elf::createResponseFile(const opt::InputArgList &args) { os << toString(*arg) << "\n"; } } - return std::string(data.str()); + return std::string(data); } // Find a file by concatenating given paths. If a resulting path diff --git a/lld/ELF/InputFiles.cpp b/lld/ELF/InputFiles.cpp index cc2c5916e05..75e5ee1d0da 100644 --- a/lld/ELF/InputFiles.cpp +++ b/lld/ELF/InputFiles.cpp @@ -1546,6 +1546,7 @@ template void SharedFile::parse() { auto *s = symtab.addSymbol( SharedSymbol{*this, name, sym.getBinding(), sym.st_other, sym.getType(), sym.st_value, sym.st_size, alignment}); + s->dsoDefined = true; if (s->file == this) s->versionId = ver; } @@ -1563,6 +1564,7 @@ template void SharedFile::parse() { auto *s = symtab.addSymbol( SharedSymbol{*this, saver().save(name), sym.getBinding(), sym.st_other, sym.getType(), sym.st_value, sym.st_size, alignment}); + s->dsoDefined = true; if (s->file == this) s->versionId = idx; } @@ -1739,7 +1741,7 @@ void BitcodeFile::parseLazy() { for (auto [i, irSym] : llvm::enumerate(obj->symbols())) if (!irSym.isUndefined()) { auto *sym = symtab.insert(saver().save(irSym.getName())); - sym->resolve(LazyObject{*this}); + sym->resolve(LazySymbol{*this}); symbols[i] = sym; } } @@ -1785,6 +1787,10 @@ void BinaryFile::parse() { nullptr}); } +InputFile *elf::createInternalFile(StringRef name) { + return make(InputFile::InternalKind, MemoryBufferRef("", name)); +} + ELFFileBase *elf::createObjFile(MemoryBufferRef mb, StringRef archiveName, bool lazy) { ELFFileBase *f; @@ -1821,7 +1827,7 @@ template void ObjFile::parseLazy() { if (eSyms[i].st_shndx == SHN_UNDEF) continue; symbols[i] = symtab.insert(CHECK(eSyms[i].getName(stringTable), this)); - symbols[i]->resolve(LazyObject{*this}); + symbols[i]->resolve(LazySymbol{*this}); if (!lazy) break; } diff --git a/lld/ELF/InputFiles.h b/lld/ELF/InputFiles.h index ab98d78fcf1..0cbe00aa396 100644 --- a/lld/ELF/InputFiles.h +++ b/lld/ELF/InputFiles.h @@ -63,14 +63,17 @@ public: SharedKind, BitcodeKind, BinaryKind, + InternalKind, }; + InputFile(Kind k, MemoryBufferRef m); Kind kind() const { return fileKind; } bool isElf() const { Kind k = kind(); return k == ObjKind || k == SharedKind; } + bool isInternal() const { return kind() == InternalKind; } StringRef getName() const { return mb.getBufferIdentifier(); } MemoryBufferRef mb; @@ -126,8 +129,8 @@ public: uint8_t osabi = 0; uint8_t abiVersion = 0; - // True if this is a relocatable object file/bitcode file between --start-lib - // and --end-lib. + // True if this is a relocatable object file/bitcode file in an ar archive + // or between --start-lib and --end-lib. bool lazy = false; // True if this is an argument for --just-symbols. Usually false. @@ -151,9 +154,6 @@ public: // R_PPC64_TLSLD. Disable TLS relaxation to avoid bad code generation. bool ppc64DisableTLSRelax = false; -protected: - InputFile(Kind k, MemoryBufferRef m); - public: // If not empty, this stores the name of the archive containing this file. // We use this string for creating error messages. @@ -380,6 +380,7 @@ public: void parse(); }; +InputFile *createInternalFile(StringRef name); ELFFileBase *createObjFile(MemoryBufferRef mb, StringRef archiveName = "", bool lazy = false); diff --git a/lld/ELF/InputSection.cpp b/lld/ELF/InputSection.cpp index 586404643cc..c728dd6c630 100644 --- a/lld/ELF/InputSection.cpp +++ b/lld/ELF/InputSection.cpp @@ -245,6 +245,8 @@ InputSection *InputSectionBase::getLinkOrderDep() const { // Find a symbol that encloses a given location. Defined *InputSectionBase::getEnclosingSymbol(uint64_t offset, uint8_t type) const { + if (file->isInternal()) + return nullptr; for (Symbol *b : file->getSymbols()) if (Defined *d = dyn_cast(b)) if (d->section == this && d->value <= offset && @@ -344,7 +346,7 @@ template void InputSection::copyShtGroup(uint8_t *buf) { } InputSectionBase *InputSection::getRelocatedSection() const { - if (!file || (type != SHT_RELA && type != SHT_REL)) + if (!file || file->isInternal() || (type != SHT_RELA && type != SHT_REL)) return nullptr; ArrayRef sections = file->getSections(); return sections[info]; diff --git a/lld/ELF/InputSection.h b/lld/ELF/InputSection.h index fbaea57bd58..dda4242d8be 100644 --- a/lld/ELF/InputSection.h +++ b/lld/ELF/InputSection.h @@ -9,6 +9,7 @@ #ifndef LLD_ELF_INPUT_SECTION_H #define LLD_ELF_INPUT_SECTION_H +#include "Config.h" #include "Relocations.h" #include "lld/Common/CommonLinkerContext.h" #include "lld/Common/LLVM.h" @@ -413,7 +414,7 @@ class SyntheticSection : public InputSection { public: SyntheticSection(uint64_t flags, uint32_t type, uint32_t addralign, StringRef name) - : InputSection(nullptr, flags, type, addralign, {}, name, + : InputSection(ctx.internalFile, flags, type, addralign, {}, name, InputSectionBase::Synthetic) {} virtual ~SyntheticSection() = default; diff --git a/lld/ELF/LTO.cpp b/lld/ELF/LTO.cpp index 504c12aac6c..c39c6e6ea74 100644 --- a/lld/ELF/LTO.cpp +++ b/lld/ELF/LTO.cpp @@ -12,6 +12,7 @@ #include "SymbolTable.h" #include "Symbols.h" #include "lld/Common/Args.h" +#include "lld/Common/CommonLinkerContext.h" #include "lld/Common/ErrorHandler.h" #include "lld/Common/Filesystem.h" #include "lld/Common/Strings.h" @@ -28,6 +29,7 @@ #include "llvm/Support/Error.h" #include "llvm/Support/FileSystem.h" #include "llvm/Support/MemoryBuffer.h" +#include "llvm/Support/Path.h" #include #include #include @@ -256,10 +258,12 @@ void BitcodeCompiler::add(BitcodeFile &f) { // Symbol section is always null for bitcode symbols, hence the check // for isElf(). Skip linker script defined symbols as well: they have // no File defined. - !(dr->section == nullptr && (!sym->file || sym->file->isElf())); + !(dr->section == nullptr && + (sym->file->isInternal() || sym->file->isElf())); if (r.Prevailing) - Undefined(nullptr, StringRef(), STB_GLOBAL, STV_DEFAULT, sym->type) + Undefined(ctx.internalFile, StringRef(), STB_GLOBAL, STV_DEFAULT, + sym->type) .overwrite(*sym); // We tell LTO to not apply interprocedural optimization for wrapped @@ -303,6 +307,7 @@ std::vector BitcodeCompiler::compile() { unsigned maxTasks = ltoObj->getMaxTasks(); buf.resize(maxTasks); files.resize(maxTasks); + filenames.resize(maxTasks); // The --thinlto-cache-dir option specifies the path to a directory in which // to cache native object files for ThinLTO incremental builds. If a path was @@ -313,13 +318,15 @@ std::vector BitcodeCompiler::compile() { [&](size_t task, const Twine &moduleName, std::unique_ptr mb) { files[task] = std::move(mb); + filenames[task] = moduleName.str(); })); if (!ctx.bitcodeFiles.empty()) checkError(ltoObj->run( [&](size_t task, const Twine &moduleName) { + buf[task].first = moduleName.str(); return std::make_unique( - std::make_unique(buf[task])); + std::make_unique(buf[task].second)); }, cache)); @@ -338,7 +345,7 @@ std::vector BitcodeCompiler::compile() { if (config->thinLTOIndexOnly) { if (!config->ltoObjPath.empty()) - saveBuffer(buf[0], config->ltoObjPath); + saveBuffer(buf[0].second, config->ltoObjPath); // ThinLTO with index only option is required to generate only the index // files. After that, we exit from linker and ThinLTO backend runs in a @@ -352,32 +359,57 @@ std::vector BitcodeCompiler::compile() { pruneCache(config->thinLTOCacheDir, config->thinLTOCachePolicy, files); if (!config->ltoObjPath.empty()) { - saveBuffer(buf[0], config->ltoObjPath); + saveBuffer(buf[0].second, config->ltoObjPath); for (unsigned i = 1; i != maxTasks; ++i) - saveBuffer(buf[i], config->ltoObjPath + Twine(i)); - } - - if (config->saveTempsArgs.contains("prelink")) { - if (!buf[0].empty()) - saveBuffer(buf[0], config->outputFile + ".lto.o"); - for (unsigned i = 1; i != maxTasks; ++i) - saveBuffer(buf[i], config->outputFile + Twine(i) + ".lto.o"); - } - - if (config->ltoEmitAsm) { - saveBuffer(buf[0], config->outputFile); - for (unsigned i = 1; i != maxTasks; ++i) - saveBuffer(buf[i], config->outputFile + Twine(i)); - return {}; + saveBuffer(buf[i].second, config->ltoObjPath + Twine(i)); } + bool savePrelink = config->saveTempsArgs.contains("prelink"); std::vector ret; - for (unsigned i = 0; i != maxTasks; ++i) - if (!buf[i].empty()) - ret.push_back(createObjFile(MemoryBufferRef(buf[i], "lto.tmp"))); + const char *ext = config->ltoEmitAsm ? ".s" : ".o"; + for (unsigned i = 0; i != maxTasks; ++i) { + StringRef bitcodeFilePath; + StringRef objBuf; + if (files[i]) { + // When files[i] is not null, we get the native relocatable file from the + // cache. filenames[i] contains the original BitcodeFile's identifier. + objBuf = files[i]->getBuffer(); + bitcodeFilePath = filenames[i]; + } else { + // Get the native relocatable file after in-process LTO compilation. + objBuf = buf[i].second; + bitcodeFilePath = buf[i].first; + } + if (objBuf.empty()) + continue; - for (std::unique_ptr &file : files) - if (file) - ret.push_back(createObjFile(*file)); + // If the input bitcode file is path/to/x.o and -o specifies a.out, the + // corresponding native relocatable file path will look like: + // path/to/a.out.lto.x.o. + StringRef ltoObjName; + if (bitcodeFilePath == "ld-temp.o") { + ltoObjName = + saver().save(Twine(config->outputFile) + ".lto" + + (i == 0 ? Twine("") : Twine('.') + Twine(i)) + ext); + } else { + StringRef directory = sys::path::parent_path(bitcodeFilePath); + // For an archive member, which has an identifier like "d/a.a(coll.o at + // 8)" (see BitcodeFile::BitcodeFile), use the filename; otherwise, use + // the stem (d/a.o => a). + StringRef baseName = bitcodeFilePath.ends_with(")") + ? sys::path::filename(bitcodeFilePath) + : sys::path::stem(bitcodeFilePath); + StringRef outputFileBaseName = sys::path::filename(config->outputFile); + SmallString<256> path; + sys::path::append(path, directory, + outputFileBaseName + ".lto." + baseName + ext); + sys::path::remove_dots(path, true); + ltoObjName = saver().save(path.str()); + } + if (savePrelink || config->ltoEmitAsm) + saveBuffer(buf[i].second, ltoObjName); + if (!config->ltoEmitAsm) + ret.push_back(createObjFile(MemoryBufferRef(objBuf, ltoObjName))); + } return ret; } diff --git a/lld/ELF/LTO.h b/lld/ELF/LTO.h index 7ab654101f2..405e7f4a649 100644 --- a/lld/ELF/LTO.h +++ b/lld/ELF/LTO.h @@ -46,8 +46,10 @@ public: private: std::unique_ptr ltoObj; - std::vector> buf; + // An array of (module name, native relocatable file content) pairs. + SmallVector>, 0> buf; std::vector> files; + SmallVector filenames; llvm::DenseSet usedStartStop; std::unique_ptr indexFile; llvm::DenseSet thinIndices; diff --git a/lld/ELF/LinkerScript.cpp b/lld/ELF/LinkerScript.cpp index 03aec187668..9e7647f63ca 100644 --- a/lld/ELF/LinkerScript.cpp +++ b/lld/ELF/LinkerScript.cpp @@ -233,8 +233,8 @@ void LinkerScript::addSymbol(SymbolAssignment *cmd) { // write expressions like this: `alignment = 16; . = ALIGN(., alignment)`. uint64_t symValue = value.sec ? 0 : value.getValue(); - Defined newSym(nullptr, cmd->name, STB_GLOBAL, visibility, value.type, - symValue, 0, sec); + Defined newSym(createInternalFile(cmd->location), cmd->name, STB_GLOBAL, + visibility, value.type, symValue, 0, sec); Symbol *sym = symtab.insert(cmd->name); sym->mergeProperties(newSym); @@ -250,8 +250,8 @@ static void declareSymbol(SymbolAssignment *cmd) { return; uint8_t visibility = cmd->hidden ? STV_HIDDEN : STV_DEFAULT; - Defined newSym(nullptr, cmd->name, STB_GLOBAL, visibility, STT_NOTYPE, 0, 0, - nullptr); + Defined newSym(ctx.internalFile, cmd->name, STB_GLOBAL, visibility, + STT_NOTYPE, 0, 0, nullptr); // If the symbol is already defined, its order is 0 (with absence indicating // 0); otherwise it's assigned the order of the SymbolAssignment. diff --git a/lld/ELF/Relocations.cpp b/lld/ELF/Relocations.cpp index 20eb02b8798..b6a317bc3b6 100644 --- a/lld/ELF/Relocations.cpp +++ b/lld/ELF/Relocations.cpp @@ -105,6 +105,13 @@ void elf::reportRangeError(uint8_t *loc, const Relocation &rel, const Twine &v, hint = "; references '" + lld::toString(*rel.sym) + '\''; else if (auto *d = dyn_cast(rel.sym)) hint = ("; references section '" + d->section->name + "'").str(); + + if (config->emachine == EM_X86_64 && rel.type == R_X86_64_PC32 && + rel.sym->getOutputSection() && + (rel.sym->getOutputSection()->flags & SHF_X86_64_LARGE)) { + hint += "; R_X86_64_PC32 should not reference a section marked " + "SHF_X86_64_LARGE"; + } } if (!errPlace.srcLoc.empty()) hint += "\n>>> referenced by " + errPlace.srcLoc; @@ -210,10 +217,10 @@ bool lld::elf::needsGot(RelExpr expr) { // True if this expression is of the form Sym - X, where X is a position in the // file (PC, or GOT for example). static bool isRelExpr(RelExpr expr) { - return oneof( - expr); + return oneof(expr); } static RelExpr toPlt(RelExpr expr) { @@ -1750,7 +1757,7 @@ void elf::postScanRelocations() { GotSection *got = in.got.get(); if (ctx.needsTlsLd.load(std::memory_order_relaxed) && got->addTlsIndex()) { - static Undefined dummy(nullptr, "", STB_LOCAL, 0, 0); + static Undefined dummy(ctx.internalFile, "", STB_LOCAL, 0, 0); if (config->shared) mainPart->relaDyn->addReloc( {target->tlsModuleIndexRel, got, got->getTlsIndexOff()}); diff --git a/lld/ELF/ScriptLexer.h b/lld/ELF/ScriptLexer.h index 17c0b529fa1..7919e493fa2 100644 --- a/lld/ELF/ScriptLexer.h +++ b/lld/ELF/ScriptLexer.h @@ -32,6 +32,7 @@ public: void expect(StringRef expect); bool consumeLabel(StringRef tok); std::string getCurrentLocation(); + MemoryBufferRef getCurrentMB(); std::vector mbs; std::vector tokens; @@ -41,9 +42,6 @@ public: size_t lastLineNumber = 0; size_t lastLineNumberOffset = 0; -protected: - MemoryBufferRef getCurrentMB(); - private: void maybeSplitExpr(); StringRef getLine(); diff --git a/lld/ELF/ScriptParser.cpp b/lld/ELF/ScriptParser.cpp index 4fdb8c7075a..dd69916d6b0 100644 --- a/lld/ELF/ScriptParser.cpp +++ b/lld/ELF/ScriptParser.cpp @@ -288,7 +288,8 @@ void ScriptParser::readDefsym(StringRef name) { Expr e = readExpr(); if (!atEOF()) setError("EOF expected, but got " + next()); - auto *cmd = make(name, e, 0, getCurrentLocation()); + auto *cmd = make( + name, e, 0, getCurrentMB().getBufferIdentifier().str()); script->sectionCommands.push_back(cmd); } diff --git a/lld/ELF/Symbols.cpp b/lld/ELF/Symbols.cpp index 734ca6bfcb4..cd2b9e22ab3 100644 --- a/lld/ELF/Symbols.cpp +++ b/lld/ELF/Symbols.cpp @@ -40,7 +40,7 @@ LLVM_ATTRIBUTE_UNUSED static inline void assertSymbols() { AssertSymbol(); AssertSymbol(); AssertSymbol(); - AssertSymbol(); + AssertSymbol(); } // Returns a symbol for an error message. @@ -146,7 +146,7 @@ static uint64_t getSymVA(const Symbol &sym, int64_t addend) { case Symbol::SharedKind: case Symbol::UndefinedKind: return 0; - case Symbol::LazyObjectKind: + case Symbol::LazyKind: llvm_unreachable("lazy symbol reached writer"); case Symbol::CommonKind: llvm_unreachable("common symbol reached writer"); @@ -623,7 +623,7 @@ void Symbol::resolve(const Defined &other) { other.overwrite(*this); } -void Symbol::resolve(const LazyObject &other) { +void Symbol::resolve(const LazySymbol &other) { if (isPlaceholder()) { other.overwrite(*this); return; diff --git a/lld/ELF/Symbols.h b/lld/ELF/Symbols.h index e34a31e12f9..c65c5d6cd0d 100644 --- a/lld/ELF/Symbols.h +++ b/lld/ELF/Symbols.h @@ -37,7 +37,7 @@ class InputSectionBase; class SharedSymbol; class Symbol; class Undefined; -class LazyObject; +class LazySymbol; class InputFile; void printTraceSymbol(const Symbol &sym, StringRef name); @@ -76,7 +76,7 @@ public: CommonKind, SharedKind, UndefinedKind, - LazyObjectKind, + LazyKind, }; Kind kind() const { return static_cast(symbolKind); } @@ -181,7 +181,7 @@ public: bool isLocal() const { return binding == llvm::ELF::STB_LOCAL; } - bool isLazy() const { return symbolKind == LazyObjectKind; } + bool isLazy() const { return symbolKind == LazyKind; } // True if this is an undefined weak symbol. This only works once // all input files have been added. @@ -237,7 +237,7 @@ public: void resolve(const Undefined &other); void resolve(const CommonSymbol &other); void resolve(const Defined &other); - void resolve(const LazyObject &other); + void resolve(const LazySymbol &other); void resolve(const SharedSymbol &other); // If this is a lazy symbol, extract an input file and add the symbol @@ -298,12 +298,13 @@ public: // of the symbol. uint8_t scriptDefined : 1; + // True if defined in a DSO. There may also be a definition in a relocatable + // object file. + uint8_t dsoDefined : 1; + // True if defined in a DSO as protected visibility. uint8_t dsoProtected : 1; - // True if targeted by a range extension thunk. - uint8_t thunkAccessed : 1; - // Temporary flags used to communicate which symbol entries need PLT and GOT // entries during postScanRelocations(); std::atomic flags; @@ -320,6 +321,9 @@ public: uint16_t versionId; uint8_t versionScriptAssigned : 1; + // True if targeted by a range extension thunk. + uint8_t thunkAccessed : 1; + void setFlags(uint16_t bits) { flags.fetch_or(bits, std::memory_order_relaxed); } @@ -471,7 +475,7 @@ public: uint32_t alignment; }; -// LazyObject symbols represent symbols in object files between --start-lib and +// LazySymbol symbols represent symbols in object files between --start-lib and // --end-lib options. LLD also handles traditional archives as if all the files // in the archive are surrounded by --start-lib and --end-lib. // @@ -480,14 +484,14 @@ public: // and the lazy. We represent that with a lazy symbol with a weak binding. This // means that code looking for undefined symbols normally also has to take lazy // symbols into consideration. -class LazyObject : public Symbol { +class LazySymbol : public Symbol { public: - LazyObject(InputFile &file) - : Symbol(LazyObjectKind, &file, {}, llvm::ELF::STB_GLOBAL, + LazySymbol(InputFile &file) + : Symbol(LazyKind, &file, {}, llvm::ELF::STB_GLOBAL, llvm::ELF::STV_DEFAULT, llvm::ELF::STT_NOTYPE) {} - void overwrite(Symbol &sym) const { Symbol::overwrite(sym, LazyObjectKind); } + void overwrite(Symbol &sym) const { Symbol::overwrite(sym, LazyKind); } - static bool classof(const Symbol *s) { return s->kind() == LazyObjectKind; } + static bool classof(const Symbol *s) { return s->kind() == LazyKind; } }; // Some linker-generated symbols need to be created as @@ -541,7 +545,7 @@ union SymbolUnion { alignas(CommonSymbol) char b[sizeof(CommonSymbol)]; alignas(Undefined) char c[sizeof(Undefined)]; alignas(SharedSymbol) char d[sizeof(SharedSymbol)]; - alignas(LazyObject) char e[sizeof(LazyObject)]; + alignas(LazySymbol) char e[sizeof(LazySymbol)]; }; template Defined *makeDefined(T &&...args) { diff --git a/lld/ELF/SyntheticSections.cpp b/lld/ELF/SyntheticSections.cpp index 1c1b0ee2f9c..4b413163314 100644 --- a/lld/ELF/SyntheticSections.cpp +++ b/lld/ELF/SyntheticSections.cpp @@ -261,8 +261,8 @@ InputSection *elf::createInterpSection() { StringRef s = saver().save(config->dynamicLinker); ArrayRef contents = {(const uint8_t *)s.data(), s.size() + 1}; - return make(nullptr, SHF_ALLOC, SHT_PROGBITS, 1, contents, - ".interp"); + return make(ctx.internalFile, SHF_ALLOC, SHT_PROGBITS, 1, + contents, ".interp"); } Defined *elf::addSyntheticLocal(StringRef name, uint8_t type, uint64_t value, diff --git a/lld/ELF/Target.cpp b/lld/ELF/Target.cpp index 41990f40f68..671d22cc66a 100644 --- a/lld/ELF/Target.cpp +++ b/lld/ELF/Target.cpp @@ -112,7 +112,7 @@ ErrorPlace elf::getErrorPlace(const uint8_t *loc) { std::string objLoc = isec->getLocation(loc - isecLoc); // Return object file location and source file location. // TODO: Refactor getSrcMsg not to take a variable. - Undefined dummy(nullptr, "", STB_LOCAL, 0, 0); + Undefined dummy(ctx.internalFile, "", STB_LOCAL, 0, 0); return {isec, objLoc + ": ", isec->file ? isec->getSrcMsg(dummy, loc - isecLoc) : ""}; } diff --git a/lld/ELF/Writer.cpp b/lld/ELF/Writer.cpp index dfec5e07301..6f66f3615fa 100644 --- a/lld/ELF/Writer.cpp +++ b/lld/ELF/Writer.cpp @@ -148,23 +148,24 @@ static Defined *addOptionalRegular(StringRef name, SectionBase *sec, if (!s || s->isDefined() || s->isCommon()) return nullptr; - s->resolve(Defined{nullptr, StringRef(), STB_GLOBAL, stOther, STT_NOTYPE, val, + s->resolve(Defined{ctx.internalFile, StringRef(), STB_GLOBAL, stOther, + STT_NOTYPE, val, /*size=*/0, sec}); s->isUsedInRegularObj = true; return cast(s); } -static Defined *addAbsolute(StringRef name) { - Symbol *sym = symtab.addSymbol(Defined{nullptr, name, STB_GLOBAL, STV_HIDDEN, - STT_NOTYPE, 0, 0, nullptr}); - sym->isUsedInRegularObj = true; - return cast(sym); -} - // The linker is expected to define some symbols depending on // the linking result. This function defines such symbols. void elf::addReservedSymbols() { if (config->emachine == EM_MIPS) { + auto addAbsolute = [](StringRef name) { + Symbol *sym = + symtab.addSymbol(Defined{ctx.internalFile, name, STB_GLOBAL, + STV_HIDDEN, STT_NOTYPE, 0, 0, nullptr}); + sym->isUsedInRegularObj = true; + return cast(sym); + }; // Define _gp for MIPS. st_value of _gp symbol will be updated by Writer // so that it points to an absolute address which by default is relative // to GOT. Default offset is 0x7ff0. @@ -213,7 +214,7 @@ void elf::addReservedSymbols() { if (config->emachine == EM_PPC64) gotOff = 0x8000; - s->resolve(Defined{/*file=*/nullptr, StringRef(), STB_GLOBAL, STV_HIDDEN, + s->resolve(Defined{ctx.internalFile, StringRef(), STB_GLOBAL, STV_HIDDEN, STT_NOTYPE, gotOff, /*size=*/0, Out::elfHeader}); ElfSym::globalOffsetTable = cast(s); } @@ -280,7 +281,8 @@ static void demoteSymbolsAndComputeIsPreemptible() { auto *s = dyn_cast(sym); if (sym->isLazy() || (s && !cast(s->file)->isNeeded)) { uint8_t binding = sym->isLazy() ? sym->binding : uint8_t(STB_WEAK); - Undefined(nullptr, sym->getName(), binding, sym->stOther, sym->type) + Undefined(ctx.internalFile, sym->getName(), binding, sym->stOther, + sym->type) .overwrite(*sym); sym->versionId = VER_NDX_GLOBAL; } @@ -1922,7 +1924,7 @@ template void Writer::finalizeSections() { // https://sourceware.org/ml/binutils/2002-03/msg00360.html if (mainPart->dynamic->parent) { Symbol *s = symtab.addSymbol(Defined{ - /*file=*/nullptr, "_DYNAMIC", STB_WEAK, STV_HIDDEN, STT_NOTYPE, + ctx.internalFile, "_DYNAMIC", STB_WEAK, STV_HIDDEN, STT_NOTYPE, /*value=*/0, /*size=*/0, mainPart->dynamic.get()}); s->isUsedInRegularObj = true; } @@ -1964,7 +1966,7 @@ template void Writer::finalizeSections() { // define _TLS_MODULE_BASE_ relative to the first TLS section. Symbol *s = symtab.find("_TLS_MODULE_BASE_"); if (s && s->isUndefined()) { - s->resolve(Defined{/*file=*/nullptr, StringRef(), STB_GLOBAL, + s->resolve(Defined{ctx.internalFile, StringRef(), STB_GLOBAL, STV_HIDDEN, STT_TLS, /*value=*/0, 0, /*section=*/nullptr}); ElfSym::tlsModuleBase = cast(s); @@ -2023,6 +2025,11 @@ template void Writer::finalizeSections() { // to catch more cases. That is too much for us. Our approach resembles // the one used in ld.gold, achieves a good balance to be useful but not // too smart. + // + // If a DSO reference is resolved by a SharedSymbol, but the SharedSymbol + // is overridden by a hidden visibility Defined (which is later discarded + // due to GC), don't report the diagnostic. However, this may indicate an + // unintended SharedSymbol. for (SharedFile *file : ctx.sharedFiles) { bool allNeededIsKnown = llvm::all_of(file->dtNeeded, [&](StringRef needed) { @@ -2031,6 +2038,8 @@ template void Writer::finalizeSections() { if (!allNeededIsKnown) continue; for (Symbol *sym : file->requiredSymbols) { + if (sym->dsoDefined) + continue; if (sym->isUndefined() && !sym->isWeak()) { diagnose("undefined reference due to --no-allow-shlib-undefined: " + toString(*sym) + "\n>>> referenced by " + toString(file)); @@ -2106,8 +2115,9 @@ template void Writer::finalizeSections() { // With the outputSections available check for GDPLT relocations // and add __tls_get_addr symbol if needed. if (config->emachine == EM_HEXAGON && hexagonNeedsTLSSymbol(outputSections)) { - Symbol *sym = symtab.addSymbol(Undefined{ - nullptr, "__tls_get_addr", STB_GLOBAL, STV_DEFAULT, STT_NOTYPE}); + Symbol *sym = + symtab.addSymbol(Undefined{ctx.internalFile, "__tls_get_addr", + STB_GLOBAL, STV_DEFAULT, STT_NOTYPE}); sym->isPreemptible = true; partitions[0].dynSymTab->addSymbol(sym); } diff --git a/lld/MachO/Arch/ARM64.cpp b/lld/MachO/Arch/ARM64.cpp index e3781763c61..2741df9c307 100644 --- a/lld/MachO/Arch/ARM64.cpp +++ b/lld/MachO/Arch/ARM64.cpp @@ -37,9 +37,9 @@ struct ARM64 : ARM64Common { uint64_t entryAddr) const override; void writeObjCMsgSendStub(uint8_t *buf, Symbol *sym, uint64_t stubsAddr, - uint64_t stubOffset, uint64_t selrefsVA, - uint64_t selectorIndex, uint64_t gotAddr, - uint64_t msgSendIndex) const override; + uint64_t &stubOffset, uint64_t selrefsVA, + uint64_t selectorIndex, + Symbol *objcMsgSend) const override; void populateThunk(InputSection *thunk, Symbol *funcSym) override; void applyOptimizationHints(uint8_t *, const ObjFile &) const override; }; @@ -117,13 +117,42 @@ static constexpr uint32_t objcStubsFastCode[] = { 0xd4200020, // brk #0x1 }; +static constexpr uint32_t objcStubsSmallCode[] = { + 0x90000001, // adrp x1, __objc_selrefs@page + 0xf9400021, // ldr x1, [x1, @selector("foo")@pageoff] + 0x14000000, // b _objc_msgSend +}; + void ARM64::writeObjCMsgSendStub(uint8_t *buf, Symbol *sym, uint64_t stubsAddr, - uint64_t stubOffset, uint64_t selrefsVA, - uint64_t selectorIndex, uint64_t gotAddr, - uint64_t msgSendIndex) const { - ::writeObjCMsgSendStub(buf, objcStubsFastCode, sym, stubsAddr, - stubOffset, selrefsVA, selectorIndex, gotAddr, - msgSendIndex); + uint64_t &stubOffset, uint64_t selrefsVA, + uint64_t selectorIndex, + Symbol *objcMsgSend) const { + uint64_t objcMsgSendAddr; + uint64_t objcStubSize; + uint64_t objcMsgSendIndex; + + if (config->objcStubsMode == ObjCStubsMode::fast) { + objcStubSize = target->objcStubsFastSize; + objcMsgSendAddr = in.got->addr; + objcMsgSendIndex = objcMsgSend->gotIndex; + ::writeObjCMsgSendFastStub(buf, objcStubsFastCode, sym, stubsAddr, + stubOffset, selrefsVA, selectorIndex, + objcMsgSendAddr, objcMsgSendIndex); + } else { + assert(config->objcStubsMode == ObjCStubsMode::small); + objcStubSize = target->objcStubsSmallSize; + if (auto *d = dyn_cast(objcMsgSend)) { + objcMsgSendAddr = d->getVA(); + objcMsgSendIndex = 0; + } else { + objcMsgSendAddr = in.stubs->addr; + objcMsgSendIndex = objcMsgSend->stubsIndex; + } + ::writeObjCMsgSendSmallStub(buf, objcStubsSmallCode, sym, stubsAddr, + stubOffset, selrefsVA, selectorIndex, + objcMsgSendAddr, objcMsgSendIndex); + } + stubOffset += objcStubSize; } // A thunk is the relaxed variation of stubCode. We don't need the @@ -157,7 +186,9 @@ ARM64::ARM64() : ARM64Common(LP64()) { thunkSize = sizeof(thunkCode); objcStubsFastSize = sizeof(objcStubsFastCode); - objcStubsAlignment = 32; + objcStubsFastAlignment = 32; + objcStubsSmallSize = sizeof(objcStubsSmallCode); + objcStubsSmallAlignment = 4; // Branch immediate is two's complement 26 bits, which is implicitly // multiplied by 4 (since all functions are 4-aligned: The branch range diff --git a/lld/MachO/Arch/ARM64Common.h b/lld/MachO/Arch/ARM64Common.h index 8dc2412b29b..b038b6200f4 100644 --- a/lld/MachO/Arch/ARM64Common.h +++ b/lld/MachO/Arch/ARM64Common.h @@ -154,10 +154,10 @@ inline void writeStubHelperEntry(uint8_t *buf8, template inline void -writeObjCMsgSendStub(uint8_t *buf, const uint32_t objcStubsFastCode[8], - Symbol *sym, uint64_t stubsAddr, uint64_t stubOffset, - uint64_t selrefsVA, uint64_t selectorIndex, - uint64_t gotAddr, uint64_t msgSendIndex) { +writeObjCMsgSendFastStub(uint8_t *buf, const uint32_t objcStubsFastCode[8], + Symbol *sym, uint64_t stubsAddr, uint64_t stubOffset, + uint64_t selrefsVA, uint64_t selectorIndex, + uint64_t gotAddr, uint64_t msgSendIndex) { SymbolDiagnostic d = {sym, sym->getName()}; auto *buf32 = reinterpret_cast(buf); @@ -170,15 +170,40 @@ writeObjCMsgSendStub(uint8_t *buf, const uint32_t objcStubsFastCode[8], pageBits(selrefsVA + selectorOffset) - pcPageBits(0)); encodePageOff12(&buf32[1], d, objcStubsFastCode[1], selrefsVA + selectorOffset); + uint64_t gotOffset = msgSendIndex * LP::wordSize; encodePage21(&buf32[2], d, objcStubsFastCode[2], - pageBits(gotAddr) - pcPageBits(2)); - encodePage21(&buf32[3], d, objcStubsFastCode[3], msgSendIndex * LP::wordSize); + pageBits(gotAddr + gotOffset) - pcPageBits(2)); + encodePageOff12(&buf32[3], d, objcStubsFastCode[3], gotAddr + gotOffset); buf32[4] = objcStubsFastCode[4]; buf32[5] = objcStubsFastCode[5]; buf32[6] = objcStubsFastCode[6]; buf32[7] = objcStubsFastCode[7]; } +template +inline void +writeObjCMsgSendSmallStub(uint8_t *buf, const uint32_t objcStubsSmallCode[3], + Symbol *sym, uint64_t stubsAddr, uint64_t stubOffset, + uint64_t selrefsVA, uint64_t selectorIndex, + uint64_t msgSendAddr, uint64_t msgSendIndex) { + SymbolDiagnostic d = {sym, sym->getName()}; + auto *buf32 = reinterpret_cast(buf); + + auto pcPageBits = [stubsAddr, stubOffset](int i) { + return pageBits(stubsAddr + stubOffset + i * sizeof(uint32_t)); + }; + + uint64_t selectorOffset = selectorIndex * LP::wordSize; + encodePage21(&buf32[0], d, objcStubsSmallCode[0], + pageBits(selrefsVA + selectorOffset) - pcPageBits(0)); + encodePageOff12(&buf32[1], d, objcStubsSmallCode[1], + selrefsVA + selectorOffset); + uint64_t msgSendStubVA = msgSendAddr + msgSendIndex * target->stubSize; + uint64_t pcVA = stubsAddr + stubOffset + 2 * sizeof(uint32_t); + encodeBranch26(&buf32[2], {nullptr, "objc_msgSend stub"}, + objcStubsSmallCode[2], msgSendStubVA - pcVA); +} + } // namespace lld::macho #endif diff --git a/lld/MachO/Arch/ARM64_32.cpp b/lld/MachO/Arch/ARM64_32.cpp index c6bb6ee6c1c..16c7cbee9ba 100644 --- a/lld/MachO/Arch/ARM64_32.cpp +++ b/lld/MachO/Arch/ARM64_32.cpp @@ -34,9 +34,9 @@ struct ARM64_32 : ARM64Common { void writeStubHelperEntry(uint8_t *buf, const Symbol &, uint64_t entryAddr) const override; void writeObjCMsgSendStub(uint8_t *buf, Symbol *sym, uint64_t stubsAddr, - uint64_t stubOffset, uint64_t selrefsVA, - uint64_t selectorIndex, uint64_t gotAddr, - uint64_t msgSendIndex) const override; + uint64_t &stubOffset, uint64_t selrefsVA, + uint64_t selectorIndex, + Symbol *objcMsgSend) const override; }; } // namespace @@ -100,10 +100,9 @@ void ARM64_32::writeStubHelperEntry(uint8_t *buf8, const Symbol &sym, } void ARM64_32::writeObjCMsgSendStub(uint8_t *buf, Symbol *sym, - uint64_t stubsAddr, uint64_t stubOffset, + uint64_t stubsAddr, uint64_t &stubOffset, uint64_t selrefsVA, uint64_t selectorIndex, - uint64_t gotAddr, - uint64_t msgSendIndex) const { + Symbol *objcMsgSend) const { fatal("TODO: implement this"); } diff --git a/lld/MachO/Arch/X86_64.cpp b/lld/MachO/Arch/X86_64.cpp index a0d4e1a28a1..9e8e1d01e49 100644 --- a/lld/MachO/Arch/X86_64.cpp +++ b/lld/MachO/Arch/X86_64.cpp @@ -38,9 +38,9 @@ struct X86_64 : TargetInfo { uint64_t entryAddr) const override; void writeObjCMsgSendStub(uint8_t *buf, Symbol *sym, uint64_t stubsAddr, - uint64_t stubOffset, uint64_t selrefsVA, - uint64_t selectorIndex, uint64_t gotAddr, - uint64_t msgSendIndex) const override; + uint64_t &stubOffset, uint64_t selrefsVA, + uint64_t selectorIndex, + Symbol *objcMsgSend) const override; void relaxGotLoad(uint8_t *loc, uint8_t type) const override; uint64_t getPageSize() const override { return 4 * 1024; } @@ -182,16 +182,20 @@ static constexpr uint8_t objcStubsFastCode[] = { }; void X86_64::writeObjCMsgSendStub(uint8_t *buf, Symbol *sym, uint64_t stubsAddr, - uint64_t stubOffset, uint64_t selrefsVA, - uint64_t selectorIndex, uint64_t gotAddr, - uint64_t msgSendIndex) const { + uint64_t &stubOffset, uint64_t selrefsVA, + uint64_t selectorIndex, + Symbol *objcMsgSend) const { + uint64_t objcMsgSendAddr = in.got->addr; + uint64_t objcMsgSendIndex = objcMsgSend->gotIndex; + memcpy(buf, objcStubsFastCode, sizeof(objcStubsFastCode)); SymbolDiagnostic d = {sym, sym->getName()}; uint64_t stubAddr = stubsAddr + stubOffset; writeRipRelative(d, buf, stubAddr, 7, selrefsVA + selectorIndex * LP64::wordSize); writeRipRelative(d, buf, stubAddr, 0xd, - gotAddr + msgSendIndex * LP64::wordSize); + objcMsgSendAddr + objcMsgSendIndex * LP64::wordSize); + stubOffset += target->objcStubsFastSize; } void X86_64::relaxGotLoad(uint8_t *loc, uint8_t type) const { @@ -214,7 +218,7 @@ X86_64::X86_64() : TargetInfo(LP64()) { stubHelperEntrySize = sizeof(stubHelperEntry); objcStubsFastSize = sizeof(objcStubsFastCode); - objcStubsAlignment = 1; + objcStubsFastAlignment = 1; relocAttrs = {relocAttrsArray.data(), relocAttrsArray.size()}; } diff --git a/lld/MachO/Driver.cpp b/lld/MachO/Driver.cpp index 5885a1fae4f..411fbcfcf23 100644 --- a/lld/MachO/Driver.cpp +++ b/lld/MachO/Driver.cpp @@ -90,6 +90,10 @@ static std::optional findLibrary(StringRef name) { return entry->second; auto doFind = [&] { + // Special case for Csu support files required for Mac OS X 10.7 and older + // (crt1.o) + if (name.ends_with(".o")) + return findPathCombination(name, config->librarySearchPaths, {""}); if (config->searchDylibsFirst) { if (std::optional path = findPathCombination("lib" + name, config->librarySearchPaths, @@ -823,9 +827,13 @@ static ObjCStubsMode getObjCStubsMode(const ArgList &args) { if (!arg) return ObjCStubsMode::fast; - if (arg->getOption().getID() == OPT_objc_stubs_small) - warn("-objc_stubs_small is not yet implemented, defaulting to " - "-objc_stubs_fast"); + if (arg->getOption().getID() == OPT_objc_stubs_small) { + if (is_contained({AK_arm64e, AK_arm64}, config->arch())) + return ObjCStubsMode::small; + else + warn("-objc_stubs_small is not yet implemented, defaulting to " + "-objc_stubs_fast"); + } return ObjCStubsMode::fast; } @@ -952,8 +960,7 @@ static std::vector parseSectAlign(const opt::InputArgList &args) { StringRef segName = arg->getValue(0); StringRef sectName = arg->getValue(1); StringRef alignStr = arg->getValue(2); - if (alignStr.starts_with("0x") || alignStr.starts_with("0X")) - alignStr = alignStr.drop_front(2); + alignStr.consume_front_insensitive("0x"); uint32_t align; if (alignStr.getAsInteger(16, align)) { error("-sectalign: failed to parse '" + StringRef(arg->getValue(2)) + diff --git a/lld/MachO/DriverUtils.cpp b/lld/MachO/DriverUtils.cpp index 17499451382..d6f18ecb85b 100644 --- a/lld/MachO/DriverUtils.cpp +++ b/lld/MachO/DriverUtils.cpp @@ -180,7 +180,7 @@ std::string macho::createResponseFile(const InputArgList &args) { os << toString(*arg) << "\n"; } } - return std::string(data.str()); + return std::string(data); } static void searchedDylib(const Twine &path, bool found) { diff --git a/lld/MachO/SyntheticSections.cpp b/lld/MachO/SyntheticSections.cpp index e123dcb6803..53220ad04b8 100644 --- a/lld/MachO/SyntheticSections.cpp +++ b/lld/MachO/SyntheticSections.cpp @@ -809,7 +809,9 @@ void StubHelperSection::setUp() { ObjCStubsSection::ObjCStubsSection() : SyntheticSection(segment_names::text, section_names::objcStubs) { flags = S_ATTR_SOME_INSTRUCTIONS | S_ATTR_PURE_INSTRUCTIONS; - align = target->objcStubsAlignment; + align = config->objcStubsMode == ObjCStubsMode::fast + ? target->objcStubsFastAlignment + : target->objcStubsSmallAlignment; } void ObjCStubsSection::addEntry(Symbol *sym) { @@ -817,10 +819,14 @@ void ObjCStubsSection::addEntry(Symbol *sym) { StringRef methname = sym->getName().drop_front(symbolPrefix.size()); offsets.push_back( in.objcMethnameSection->getStringOffset(methname).outSecOff); + + auto stubSize = config->objcStubsMode == ObjCStubsMode::fast + ? target->objcStubsFastSize + : target->objcStubsSmallSize; Defined *newSym = replaceSymbol( sym, sym->getName(), nullptr, isec, - /*value=*/symbols.size() * target->objcStubsFastSize, - /*size=*/target->objcStubsFastSize, + /*value=*/symbols.size() * stubSize, + /*size=*/stubSize, /*isWeakDef=*/false, /*isExternal=*/true, /*isPrivateExtern=*/true, /*includeInSymtab=*/true, /*isReferencedDynamically=*/false, /*noDeadStrip=*/false); @@ -828,12 +834,24 @@ void ObjCStubsSection::addEntry(Symbol *sym) { } void ObjCStubsSection::setUp() { - Symbol *objcMsgSend = symtab->addUndefined("_objc_msgSend", /*file=*/nullptr, - /*isWeakRef=*/false); + objcMsgSend = symtab->addUndefined("_objc_msgSend", /*file=*/nullptr, + /*isWeakRef=*/false); + if (auto *undefined = dyn_cast(objcMsgSend)) + treatUndefinedSymbol(*undefined, + "lazy binding (normally in libobjc.dylib)"); objcMsgSend->used = true; - in.got->addEntry(objcMsgSend); - assert(objcMsgSend->isInGot()); - objcMsgSendGotIndex = objcMsgSend->gotIndex; + if (config->objcStubsMode == ObjCStubsMode::fast) { + in.got->addEntry(objcMsgSend); + assert(objcMsgSend->isInGot()); + } else { + assert(config->objcStubsMode == ObjCStubsMode::small); + // In line with ld64's behavior, when objc_msgSend is a direct symbol, + // we directly reference it. + // In other cases, typically when binding in libobjc.dylib, + // we generate a stub to invoke objc_msgSend. + if (!isa(objcMsgSend)) + in.stubs->addEntry(objcMsgSend); + } size_t size = offsets.size() * target->wordSize; uint8_t *selrefsData = bAlloc().Allocate(size); @@ -863,7 +881,10 @@ void ObjCStubsSection::setUp() { } uint64_t ObjCStubsSection::getSize() const { - return target->objcStubsFastSize * symbols.size(); + auto stubSize = config->objcStubsMode == ObjCStubsMode::fast + ? target->objcStubsFastSize + : target->objcStubsSmallSize; + return stubSize * symbols.size(); } void ObjCStubsSection::writeTo(uint8_t *buf) const { @@ -875,8 +896,7 @@ void ObjCStubsSection::writeTo(uint8_t *buf) const { Defined *sym = symbols[i]; target->writeObjCMsgSendStub(buf + stubOffset, sym, in.objcStubs->addr, stubOffset, in.objcSelrefs->getVA(), i, - in.got->addr, objcMsgSendGotIndex); - stubOffset += target->objcStubsFastSize; + objcMsgSend); } } diff --git a/lld/MachO/SyntheticSections.h b/lld/MachO/SyntheticSections.h index e9d564f3c83..5fb7b6e09e8 100644 --- a/lld/MachO/SyntheticSections.h +++ b/lld/MachO/SyntheticSections.h @@ -336,7 +336,7 @@ public: private: std::vector symbols; std::vector offsets; - int objcMsgSendGotIndex = 0; + Symbol *objcMsgSend = nullptr; }; // Note that this section may also be targeted by non-lazy bindings. In diff --git a/lld/MachO/Target.h b/lld/MachO/Target.h index bc7e09d394d..b07967d0abb 100644 --- a/lld/MachO/Target.h +++ b/lld/MachO/Target.h @@ -70,10 +70,9 @@ public: uint64_t entryAddr) const = 0; virtual void writeObjCMsgSendStub(uint8_t *buf, Symbol *sym, - uint64_t stubsAddr, uint64_t stubOffset, + uint64_t stubsAddr, uint64_t &stubOffset, uint64_t selrefsVA, uint64_t selectorIndex, - uint64_t gotAddr, - uint64_t msgSendIndex) const = 0; + Symbol *objcMsgSend) const = 0; // Symbols may be referenced via either the GOT or the stubs section, // depending on the relocation type. prepareSymbolRelocation() will set up the @@ -121,7 +120,9 @@ public: size_t stubHelperHeaderSize; size_t stubHelperEntrySize; size_t objcStubsFastSize; - size_t objcStubsAlignment; + size_t objcStubsSmallSize; + size_t objcStubsFastAlignment; + size_t objcStubsSmallAlignment; uint8_t p2WordSize; size_t wordSize; diff --git a/lld/docs/ReleaseNotes.rst b/lld/docs/ReleaseNotes.rst index c322b776ff5..01669543cd5 100644 --- a/lld/docs/ReleaseNotes.rst +++ b/lld/docs/ReleaseNotes.rst @@ -50,5 +50,9 @@ MachO Improvements WebAssembly Improvements ------------------------ +* Indexes are no longer required on archive files. Instead symbol information + is read from object files within the archive. This matches the behaviour of + the ELF linker. + Fixes ##### diff --git a/lld/tools/lld/lld.cpp b/lld/tools/lld/lld.cpp index a0a7cb0be8f..d6800fa1eea 100644 --- a/lld/tools/lld/lld.cpp +++ b/lld/tools/lld/lld.cpp @@ -33,7 +33,6 @@ #include "llvm/ADT/Twine.h" #include "llvm/Support/CommandLine.h" #include "llvm/Support/CrashRecoveryContext.h" -#include "llvm/Support/InitLLVM.h" #include "llvm/Support/LLVMDriver.h" #include "llvm/Support/Path.h" #include "llvm/Support/PluginLoader.h" @@ -74,7 +73,6 @@ LLD_HAS_DRIVER(macho) LLD_HAS_DRIVER(wasm) int lld_main(int argc, char **argv, const llvm::ToolContext &) { - InitLLVM x(argc, argv); sys::Process::UseANSIEscapeCodes(true); if (::getenv("FORCE_LLD_DIAGNOSTICS_CRASH")) { diff --git a/lldb/include/lldb/API/LLDB.h b/lldb/include/lldb/API/LLDB.h index f652d1bdb83..f5f1b87a046 100644 --- a/lldb/include/lldb/API/LLDB.h +++ b/lldb/include/lldb/API/LLDB.h @@ -33,6 +33,7 @@ #include "lldb/API/SBFile.h" #include "lldb/API/SBFileSpec.h" #include "lldb/API/SBFileSpecList.h" +#include "lldb/API/SBFormat.h" #include "lldb/API/SBFrame.h" #include "lldb/API/SBFunction.h" #include "lldb/API/SBHostOS.h" diff --git a/lldb/include/lldb/Breakpoint/Breakpoint.h b/lldb/include/lldb/Breakpoint/Breakpoint.h index 3a8b29aee54..8c4308ab0bc 100644 --- a/lldb/include/lldb/Breakpoint/Breakpoint.h +++ b/lldb/include/lldb/Breakpoint/Breakpoint.h @@ -672,7 +672,7 @@ private: void SendBreakpointChangedEvent(lldb::BreakpointEventType eventKind); - void SendBreakpointChangedEvent(BreakpointEventData *data); + void SendBreakpointChangedEvent(const lldb::EventDataSP &breakpoint_data_sp); Breakpoint(const Breakpoint &) = delete; const Breakpoint &operator=(const Breakpoint &) = delete; diff --git a/lldb/include/lldb/Breakpoint/BreakpointIDList.h b/lldb/include/lldb/Breakpoint/BreakpointIDList.h index 6910024695d..6c57d9bc507 100644 --- a/lldb/include/lldb/Breakpoint/BreakpointIDList.h +++ b/lldb/include/lldb/Breakpoint/BreakpointIDList.h @@ -12,12 +12,13 @@ #include #include - -#include "lldb/lldb-enumerations.h" #include "lldb/Breakpoint/BreakpointID.h" #include "lldb/Breakpoint/BreakpointName.h" +#include "lldb/lldb-enumerations.h" #include "lldb/lldb-private.h" +#include "llvm/Support/Error.h" + namespace lldb_private { // class BreakpointIDList @@ -41,8 +42,6 @@ public: bool AddBreakpointID(BreakpointID bp_id); - bool AddBreakpointID(const char *bp_id); - // TODO: This should take a const BreakpointID. bool FindBreakpointID(BreakpointID &bp_id, size_t *position) const; @@ -54,12 +53,10 @@ public: static std::pair SplitIDRangeExpression(llvm::StringRef in_string); - static void FindAndReplaceIDRanges(Args &old_args, Target *target, - bool allow_locations, - BreakpointName::Permissions - ::PermissionKinds purpose, - CommandReturnObject &result, - Args &new_args); + static llvm::Error + FindAndReplaceIDRanges(Args &old_args, Target *target, bool allow_locations, + BreakpointName::Permissions ::PermissionKinds purpose, + Args &new_args); private: BreakpointIDArray m_breakpoint_ids; diff --git a/lldb/include/lldb/Breakpoint/Watchpoint.h b/lldb/include/lldb/Breakpoint/Watchpoint.h index 851162af24c..22fdfd686c3 100644 --- a/lldb/include/lldb/Breakpoint/Watchpoint.h +++ b/lldb/include/lldb/Breakpoint/Watchpoint.h @@ -235,8 +235,6 @@ private: void SendWatchpointChangedEvent(lldb::WatchpointEventType eventKind); - void SendWatchpointChangedEvent(WatchpointEventData *data); - Watchpoint(const Watchpoint &) = delete; const Watchpoint &operator=(const Watchpoint &) = delete; }; diff --git a/lldb/include/lldb/Core/Address.h b/lldb/include/lldb/Core/Address.h index 725b5d9f91d..9b5874f8b1f 100644 --- a/lldb/include/lldb/Core/Address.h +++ b/lldb/include/lldb/Core/Address.h @@ -9,6 +9,7 @@ #ifndef LLDB_CORE_ADDRESS_H #define LLDB_CORE_ADDRESS_H +#include "lldb/Utility/Stream.h" #include "lldb/lldb-defines.h" #include "lldb/lldb-forward.h" #include "lldb/lldb-private-enumerations.h" @@ -252,10 +253,11 @@ public: /// in such cases. /// /// \see Address::DumpStyle - bool Dump(Stream *s, ExecutionContextScope *exe_scope, DumpStyle style, - DumpStyle fallback_style = DumpStyleInvalid, - uint32_t addr_byte_size = UINT32_MAX, bool all_ranges = false, - llvm::StringRef pattern = "") const; + bool + Dump(Stream *s, ExecutionContextScope *exe_scope, DumpStyle style, + DumpStyle fallback_style = DumpStyleInvalid, + uint32_t addr_byte_size = UINT32_MAX, bool all_ranges = false, + std::optional settings = std::nullopt) const; AddressClass GetAddressClass() const; diff --git a/lldb/include/lldb/Core/DebuggerEvents.h b/lldb/include/lldb/Core/DebuggerEvents.h index 982b2222970..4a27766e94e 100644 --- a/lldb/include/lldb/Core/DebuggerEvents.h +++ b/lldb/include/lldb/Core/DebuggerEvents.h @@ -20,9 +20,10 @@ class Stream; class ProgressEventData : public EventData { public: - ProgressEventData(uint64_t progress_id, std::string title, std::string update, - uint64_t completed, uint64_t total, bool debugger_specific) - : m_title(std::move(title)), m_details(std::move(update)), + ProgressEventData(uint64_t progress_id, std::string title, + std::string details, uint64_t completed, uint64_t total, + bool debugger_specific) + : m_title(std::move(title)), m_details(std::move(details)), m_id(progress_id), m_completed(completed), m_total(total), m_debugger_specific(debugger_specific) {} diff --git a/lldb/include/lldb/Core/Progress.h b/lldb/include/lldb/Core/Progress.h index b2b8781a43b..65d30ea25cd 100644 --- a/lldb/include/lldb/Core/Progress.h +++ b/lldb/include/lldb/Core/Progress.h @@ -64,12 +64,13 @@ public: /// @param [in] title The title of this progress activity. /// /// @param [in] total The total units of work to be done if specified, if - /// set to UINT64_MAX then an indeterminate progress indicator should be + /// set to std::nullopt then an indeterminate progress indicator should be /// displayed. /// /// @param [in] debugger An optional debugger pointer to specify that this /// progress is to be reported only to specific debuggers. - Progress(std::string title, uint64_t total = UINT64_MAX, + Progress(std::string title, std::string details = {}, + std::optional total = std::nullopt, lldb_private::Debugger *debugger = nullptr); /// Destroy the progress object. @@ -89,20 +90,23 @@ public: /// @param [in] amount The amount to increment m_completed by. /// /// @param [in] an optional message associated with this update. - void Increment(uint64_t amount = 1, std::string update = {}); + void Increment(uint64_t amount = 1, + std::optional updated_detail = {}); private: - void ReportProgress(std::string update = {}); + void ReportProgress(); static std::atomic g_id; /// The title of the progress activity. std::string m_title; + std::string m_details; std::mutex m_mutex; /// A unique integer identifier for progress reporting. const uint64_t m_id; /// How much work ([0...m_total]) that has been completed. uint64_t m_completed; - /// Total amount of work, UINT64_MAX for non deterministic progress. - const uint64_t m_total; + /// Total amount of work, use a std::nullopt in the constructor for non + /// deterministic progress. + uint64_t m_total; /// The optional debugger ID to report progress to. If this has no value then /// all debuggers will receive this event. std::optional m_debugger_id; diff --git a/lldb/include/lldb/Core/ValueObject.h b/lldb/include/lldb/Core/ValueObject.h index 3f8005ba696..4c0b0b2dae6 100644 --- a/lldb/include/lldb/Core/ValueObject.h +++ b/lldb/include/lldb/Core/ValueObject.h @@ -670,8 +670,7 @@ public: std::pair ReadPointedString(lldb::WritableDataBufferSP &buffer_sp, Status &error, - uint32_t max_length = 0, bool honor_array = true, - lldb::Format item_format = lldb::eFormatCharArray); + bool honor_array); virtual size_t GetPointeeData(DataExtractor &data, uint32_t item_idx = 0, uint32_t item_count = 1); diff --git a/lldb/include/lldb/Host/Config.h.cmake b/lldb/include/lldb/Host/Config.h.cmake index 14ce46f6559..3defa454f6d 100644 --- a/lldb/include/lldb/Host/Config.h.cmake +++ b/lldb/include/lldb/Host/Config.h.cmake @@ -55,4 +55,6 @@ #cmakedefine LLDB_GLOBAL_INIT_DIRECTORY R"(${LLDB_GLOBAL_INIT_DIRECTORY})" +#define LLDB_BUG_REPORT_URL "${LLDB_BUG_REPORT_URL}" + #endif // #ifndef LLDB_HOST_CONFIG_H diff --git a/lldb/include/lldb/Symbol/CompileUnit.h b/lldb/include/lldb/Symbol/CompileUnit.h index 89e853ab599..c20a37e3283 100644 --- a/lldb/include/lldb/Symbol/CompileUnit.h +++ b/lldb/include/lldb/Symbol/CompileUnit.h @@ -91,7 +91,7 @@ public: /// \param[in] user_data /// User data where the SymbolFile parser can store data. /// - /// \param[in] file_spec + /// \param[in] support_file_sp /// The file specification for the source file of this compile /// unit. /// @@ -116,7 +116,7 @@ public: /// An rvalue list of already parsed support files. /// \see lldb::LanguageType CompileUnit(const lldb::ModuleSP &module_sp, void *user_data, - const FileSpec &file_spec, lldb::user_id_t uid, + lldb::SupportFileSP support_file_sp, lldb::user_id_t uid, lldb::LanguageType language, lldb_private::LazyBool is_optimized, SupportFileList &&support_files = {}); @@ -226,11 +226,15 @@ public: const FileSpec *file_spec_ptr, bool exact, LineEntry *line_entry); - /// Return the primary source file associated with this compile unit. - const FileSpec &GetPrimaryFile() const { return m_file_spec; } + /// Return the primary source spec associated with this compile unit. + const FileSpec &GetPrimaryFile() const { + return m_primary_support_file_sp->GetSpecOnly(); + } /// Return the primary source file associated with this compile unit. - void SetPrimaryFile(const FileSpec &fs) { m_file_spec = fs; } + lldb::SupportFileSP GetPrimarySupportFile() const { + return m_primary_support_file_sp; + } /// Get the line table for the compile unit. /// @@ -419,7 +423,7 @@ protected: /// compile unit. std::vector m_imported_modules; /// The primary file associated with this compile unit. - FileSpec m_file_spec; + lldb::SupportFileSP m_primary_support_file_sp; /// Files associated with this compile unit's line table and declarations. SupportFileList m_support_files; /// Line table that will get parsed on demand. diff --git a/lldb/include/lldb/Symbol/LineEntry.h b/lldb/include/lldb/Symbol/LineEntry.h index 698d89974dc..c2daba916e3 100644 --- a/lldb/include/lldb/Symbol/LineEntry.h +++ b/lldb/include/lldb/Symbol/LineEntry.h @@ -11,6 +11,7 @@ #include "lldb/Core/AddressRange.h" #include "lldb/Utility/FileSpec.h" +#include "lldb/Utility/SupportFile.h" #include "lldb/lldb-private.h" namespace lldb_private { @@ -23,12 +24,6 @@ struct LineEntry { /// Initialize all member variables to invalid values. LineEntry(); - LineEntry(const lldb::SectionSP §ion_sp, lldb::addr_t section_offset, - lldb::addr_t byte_size, const FileSpec &file, uint32_t _line, - uint16_t _column, bool _is_start_of_statement, - bool _is_start_of_basic_block, bool _is_prologue_end, - bool _is_epilogue_begin, bool _is_terminal_entry); - /// Clear the object's state. /// /// Clears all member variables to invalid values. @@ -139,7 +134,8 @@ struct LineEntry { AddressRange range; ///< The section offset address range for this line entry. FileSpec file; ///< The source file, possibly mapped by the target.source-map ///setting - FileSpec original_file; ///< The original source file, from debug info. + lldb::SupportFileSP + original_file_sp; ///< The original source file, from debug info. uint32_t line = LLDB_INVALID_LINE_NUMBER; ///< The source line number, or zero ///< if there is no line number /// information. diff --git a/lldb/include/lldb/Symbol/Symbol.h b/lldb/include/lldb/Symbol/Symbol.h index e6c0b495bcf..e05c845a69f 100644 --- a/lldb/include/lldb/Symbol/Symbol.h +++ b/lldb/include/lldb/Symbol/Symbol.h @@ -13,6 +13,7 @@ #include "lldb/Core/Mangled.h" #include "lldb/Core/Section.h" #include "lldb/Symbol/SymbolContextScope.h" +#include "lldb/Utility/Stream.h" #include "lldb/Utility/UserID.h" #include "lldb/lldb-private.h" #include "llvm/Support/JSON.h" @@ -174,8 +175,9 @@ public: void SetFlags(uint32_t flags) { m_flags = flags; } - void GetDescription(Stream *s, lldb::DescriptionLevel level, Target *target, - llvm::StringRef pattern = "") const; + void GetDescription( + Stream *s, lldb::DescriptionLevel level, Target *target, + std::optional settings = std::nullopt) const; bool IsSynthetic() const { return m_is_synthetic; } diff --git a/lldb/include/lldb/Symbol/SymbolContext.h b/lldb/include/lldb/Symbol/SymbolContext.h index 26f3bac09a9..bd33a71b46c 100644 --- a/lldb/include/lldb/Symbol/SymbolContext.h +++ b/lldb/include/lldb/Symbol/SymbolContext.h @@ -17,6 +17,7 @@ #include "lldb/Core/Mangled.h" #include "lldb/Symbol/LineEntry.h" #include "lldb/Utility/Iterable.h" +#include "lldb/Utility/Stream.h" #include "lldb/lldb-private.h" namespace lldb_private { @@ -153,11 +154,11 @@ public: /// /// \return /// \b true if some text was dumped, \b false otherwise. - bool DumpStopContext(Stream *s, ExecutionContextScope *exe_scope, - const Address &so_addr, bool show_fullpaths, - bool show_module, bool show_inlined_frames, - bool show_function_arguments, bool show_function_name, - llvm::StringRef pattern = "") const; + bool DumpStopContext( + Stream *s, ExecutionContextScope *exe_scope, const Address &so_addr, + bool show_fullpaths, bool show_module, bool show_inlined_frames, + bool show_function_arguments, bool show_function_name, + std::optional settings = std::nullopt) const; /// Get the address range contained within a symbol context. /// @@ -223,8 +224,9 @@ public: /// The symbol that was found, or \b nullptr if none was found. const Symbol *FindBestGlobalDataSymbol(ConstString name, Status &error); - void GetDescription(Stream *s, lldb::DescriptionLevel level, Target *target, - llvm::StringRef pattern = "") const; + void GetDescription( + Stream *s, lldb::DescriptionLevel level, Target *target, + std::optional settings = std::nullopt) const; uint32_t GetResolvedMask() const; diff --git a/lldb/include/lldb/Target/Platform.h b/lldb/include/lldb/Target/Platform.h index 129e4565d9f..13196ff74d6 100644 --- a/lldb/include/lldb/Target/Platform.h +++ b/lldb/include/lldb/Target/Platform.h @@ -288,6 +288,32 @@ public: LocateExecutableScriptingResources(Target *target, Module &module, Stream &feedback_stream); + /// \param[in] module_spec + /// The ModuleSpec of a binary to find. + /// + /// \param[in] process + /// A Process. + /// + /// \param[out] module_sp + /// A Module that matches the ModuleSpec, if one is found. + /// + /// \param[in] module_search_paths_ptr + /// Locations to possibly look for a binary that matches the ModuleSpec. + /// + /// \param[out] old_modules + /// Existing Modules in the Process' Target image list which match + /// the FileSpec. + /// + /// \param[out] did_create_ptr + /// Optional boolean, nullptr may be passed for this argument. + /// If this method is returning a *new* ModuleSP, this + /// will be set to true. + /// If this method is returning a ModuleSP that is already in the + /// Target's image list, it will be false. + /// + /// \return + /// The Status object for any errors found while searching for + /// the binary. virtual Status GetSharedModule( const ModuleSpec &module_spec, Process *process, lldb::ModuleSP &module_sp, const FileSpecList *module_search_paths_ptr, diff --git a/lldb/include/lldb/Utility/Broadcaster.h b/lldb/include/lldb/Utility/Broadcaster.h index 8444c38f6ec..c8127f0a921 100644 --- a/lldb/include/lldb/Utility/Broadcaster.h +++ b/lldb/include/lldb/Utility/Broadcaster.h @@ -177,8 +177,8 @@ public: m_broadcaster_sp->BroadcastEvent(event_type, event_data_sp); } - void BroadcastEvent(uint32_t event_type, EventData *event_data = nullptr) { - m_broadcaster_sp->BroadcastEvent(event_type, event_data); + void BroadcastEvent(uint32_t event_type) { + m_broadcaster_sp->BroadcastEvent(event_type); } void BroadcastEventIfUnique(uint32_t event_type, @@ -346,7 +346,7 @@ protected: void BroadcastEventIfUnique(lldb::EventSP &event_sp); - void BroadcastEvent(uint32_t event_type, EventData *event_data = nullptr); + void BroadcastEvent(uint32_t event_type); void BroadcastEvent(uint32_t event_type, const lldb::EventDataSP &event_data_sp); diff --git a/lldb/include/lldb/Utility/FileSpec.h b/lldb/include/lldb/Utility/FileSpec.h index e4276e8398b..2e867b2b40b 100644 --- a/lldb/include/lldb/Utility/FileSpec.h +++ b/lldb/include/lldb/Utility/FileSpec.h @@ -13,7 +13,6 @@ #include #include -#include "lldb/Utility/Checksum.h" #include "lldb/Utility/ConstString.h" #include "llvm/ADT/StringRef.h" @@ -72,12 +71,8 @@ public: /// \param[in] style /// The style of the path /// - /// \param[in] checksum - /// The MD5 checksum of the path. - /// /// \see FileSpec::SetFile (const char *path) - explicit FileSpec(llvm::StringRef path, Style style = Style::native, - const Checksum &checksum = {}); + explicit FileSpec(llvm::StringRef path, Style style = Style::native); explicit FileSpec(llvm::StringRef path, const llvm::Triple &triple); @@ -367,11 +362,7 @@ public: /// /// \param[in] style /// The style for the given path. - /// - /// \param[in] checksum - /// The checksum for the given path. - void SetFile(llvm::StringRef path, Style style, - const Checksum &checksum = {}); + void SetFile(llvm::StringRef path, Style style); /// Change the file specified with a new path. /// @@ -414,19 +405,13 @@ public: /// The lifetime of the StringRefs is tied to the lifetime of the FileSpec. std::vector GetComponents() const; - /// Return the checksum for this FileSpec or all zeros if there is none. - const Checksum &GetChecksum() const { return m_checksum; }; - protected: // Convenience method for setting the file without changing the style. void SetFile(llvm::StringRef path); /// Called anytime m_directory or m_filename is changed to clear any cached /// state in this object. - void PathWasModified() { - m_checksum = Checksum(); - m_absolute = Absolute::Calculate; - } + void PathWasModified() { m_absolute = Absolute::Calculate; } enum class Absolute : uint8_t { Calculate, @@ -440,9 +425,6 @@ protected: /// The unique'd filename path. ConstString m_filename; - /// The optional MD5 checksum of the file. - Checksum m_checksum; - /// Cache whether this path is absolute. mutable Absolute m_absolute = Absolute::Calculate; diff --git a/lldb/include/lldb/Utility/FileSpecList.h b/lldb/include/lldb/Utility/FileSpecList.h index 8cccb194999..49edc667ddd 100644 --- a/lldb/include/lldb/Utility/FileSpecList.h +++ b/lldb/include/lldb/Utility/FileSpecList.h @@ -10,6 +10,8 @@ #define LLDB_CORE_FILESPECLIST_H #include "lldb/Utility/FileSpec.h" +#include "lldb/Utility/SupportFile.h" +#include "lldb/lldb-forward.h" #include #include @@ -17,28 +19,6 @@ namespace lldb_private { class Stream; -/// Wraps either a FileSpec that represents a local file or a source -/// file whose contents is known (for example because it can be -/// reconstructed from debug info), but that hasn't been written to a -/// file yet. -class SupportFile { -protected: - FileSpec m_file_spec; - -public: - SupportFile(const FileSpec &spec) : m_file_spec(spec) {} - SupportFile(const SupportFile &other) = delete; - SupportFile(SupportFile &&other) = default; - virtual ~SupportFile() = default; - bool operator==(const SupportFile &other) { - return m_file_spec == other.m_file_spec; - } - /// Return the file name only. Useful for resolving breakpoints by file name. - const FileSpec &GetSpecOnly() const { return m_file_spec; }; - /// Materialize the file to disk and return the path to that temporary file. - virtual const FileSpec &Materialize() { return m_file_spec; } -}; - /// A list of support files for a CompileUnit. class SupportFileList { public: @@ -46,21 +26,22 @@ public: SupportFileList(const SupportFileList &) = delete; SupportFileList(SupportFileList &&other) = default; - typedef std::vector> collection; + typedef std::vector> collection; typedef collection::const_iterator const_iterator; const_iterator begin() const { return m_files.begin(); } const_iterator end() const { return m_files.end(); } void Append(const FileSpec &file) { - return Append(std::make_unique(file)); + return Append(std::make_shared(file)); } - void Append(std::unique_ptr &&file) { + void Append(std::shared_ptr &&file) { m_files.push_back(std::move(file)); } // FIXME: Only used by SymbolFilePDB. Replace with a DenseSet at call site. bool AppendIfUnique(const FileSpec &file); size_t GetSize() const { return m_files.size(); } const FileSpec &GetFileSpecAtIndex(size_t idx) const; + lldb::SupportFileSP GetSupportFileAtIndex(size_t idx) const; size_t FindFileIndex(size_t idx, const FileSpec &file, bool full) const; /// Find a compatible file index. /// @@ -90,7 +71,7 @@ public: template void EmplaceBack(Args &&...args) { m_files.push_back( - std::make_unique(FileSpec(std::forward(args)...))); + std::make_shared(std::forward(args)...)); } protected: diff --git a/lldb/include/lldb/Utility/Stream.h b/lldb/include/lldb/Utility/Stream.h index 20c55ac4597..37bcdc99241 100644 --- a/lldb/include/lldb/Utility/Stream.h +++ b/lldb/include/lldb/Utility/Stream.h @@ -33,6 +33,17 @@ public: /// string mode. }; + /// Struct to store information for color highlighting in the stream. + struct HighlightSettings { + llvm::StringRef pattern; ///< Regex pattern for highlighting. + llvm::StringRef prefix; ///< ANSI color code to start colorization. + llvm::StringRef suffix; ///< ANSI color code to end colorization. + + HighlightSettings(llvm::StringRef p, llvm::StringRef pre, + llvm::StringRef suf) + : pattern(p), prefix(pre), suffix(suf) {} + }; + /// Utility class for counting the bytes that were written to a stream in a /// certain time span. /// @@ -260,10 +271,9 @@ public: /// The ANSI color code to end colorization. This is /// environment-dependent. - void PutCStringColorHighlighted(llvm::StringRef text, - llvm::StringRef pattern = "", - llvm::StringRef prefix = "", - llvm::StringRef suffix = ""); + void PutCStringColorHighlighted( + llvm::StringRef text, + std::optional settings = std::nullopt); /// Output and End of Line character to the stream. size_t EOL(); diff --git a/lldb/include/lldb/Utility/SupportFile.h b/lldb/include/lldb/Utility/SupportFile.h new file mode 100644 index 00000000000..0ea0ca4e7c9 --- /dev/null +++ b/lldb/include/lldb/Utility/SupportFile.h @@ -0,0 +1,55 @@ +//===-- SupportFile.h -------------------------------------------*- C++ -*-===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +#ifndef LLDB_UTILITY_SUPPORTFILE_H +#define LLDB_UTILITY_SUPPORTFILE_H + +#include "lldb/Utility/Checksum.h" +#include "lldb/Utility/FileSpec.h" + +namespace lldb_private { + +/// Wraps either a FileSpec that represents a local file or a source +/// file whose contents is known (for example because it can be +/// reconstructed from debug info), but that hasn't been written to a +/// file yet. This also stores an optional checksum of the on-disk content. +class SupportFile { +public: + SupportFile() : m_file_spec(), m_checksum() {} + SupportFile(const FileSpec &spec) : m_file_spec(spec), m_checksum() {} + SupportFile(const FileSpec &spec, const Checksum &checksum) + : m_file_spec(spec), m_checksum(checksum) {} + + SupportFile(const SupportFile &other) = delete; + SupportFile(SupportFile &&other) = default; + + virtual ~SupportFile() = default; + + bool operator==(const SupportFile &other) const { + return m_file_spec == other.m_file_spec && m_checksum == other.m_checksum; + } + + bool operator!=(const SupportFile &other) const { return !(*this == other); } + + /// Return the file name only. Useful for resolving breakpoints by file name. + const FileSpec &GetSpecOnly() const { return m_file_spec; }; + + /// Return the checksum or all zeros if there is none. + const Checksum &GetChecksum() const { return m_checksum; }; + + /// Materialize the file to disk and return the path to that temporary file. + virtual const FileSpec &Materialize() { return m_file_spec; } + +protected: + FileSpec m_file_spec; + Checksum m_checksum; +}; + +} // namespace lldb_private + +#endif // LLDB_UTILITY_SUPPORTFILE_H diff --git a/lldb/include/lldb/Utility/XcodeSDK.h b/lldb/include/lldb/Utility/XcodeSDK.h index f8528995d54..673ea578ffc 100644 --- a/lldb/include/lldb/Utility/XcodeSDK.h +++ b/lldb/include/lldb/Utility/XcodeSDK.h @@ -34,6 +34,8 @@ public: AppleTVOS, WatchSimulator, watchOS, + XRSimulator, + XROS, bridgeOS, Linux, unknown = -1 diff --git a/lldb/include/lldb/lldb-enumerations.h b/lldb/include/lldb/lldb-enumerations.h index ed1dec85d48..392d333c23a 100644 --- a/lldb/include/lldb/lldb-enumerations.h +++ b/lldb/include/lldb/lldb-enumerations.h @@ -875,6 +875,7 @@ enum TemplateArgumentKind { eTemplateArgumentKindExpression, eTemplateArgumentKindPack, eTemplateArgumentKindNullPtr, + eTemplateArgumentKindStructuralValue, }; /// Type of match to be performed when looking for a formatter for a data type. diff --git a/lldb/include/lldb/lldb-forward.h b/lldb/include/lldb/lldb-forward.h index 4e0c62fa26c..d89ad215122 100644 --- a/lldb/include/lldb/lldb-forward.h +++ b/lldb/include/lldb/lldb-forward.h @@ -212,6 +212,7 @@ class StringList; class StringTableReader; class StructuredDataImpl; class StructuredDataPlugin; +class SupportFile; class Symbol; class SymbolContext; class SymbolContextList; @@ -462,6 +463,7 @@ typedef std::shared_ptr TypeSummaryImplSP; typedef std::shared_ptr TypeSummaryOptionsSP; typedef std::shared_ptr ScriptedSyntheticChildrenSP; +typedef std::shared_ptr SupportFileSP; typedef std::shared_ptr UnixSignalsSP; typedef std::weak_ptr UnixSignalsWP; typedef std::shared_ptr UnwindAssemblySP; diff --git a/lldb/source/API/SBTypeFilter.cpp b/lldb/source/API/SBTypeFilter.cpp index 8bbf3a8b526..f1b5bc952b8 100644 --- a/lldb/source/API/SBTypeFilter.cpp +++ b/lldb/source/API/SBTypeFilter.cpp @@ -166,7 +166,7 @@ SBTypeFilter::SBTypeFilter(const lldb::TypeFilterImplSP &typefilter_impl_sp) bool SBTypeFilter::CopyOnWrite_Impl() { if (!IsValid()) return false; - if (m_opaque_sp.unique()) + if (m_opaque_sp.use_count() == 1) return true; TypeFilterImplSP new_sp(new TypeFilterImpl(GetOptions())); diff --git a/lldb/source/API/SBTypeFormat.cpp b/lldb/source/API/SBTypeFormat.cpp index 86e11e8b8fd..a0c37de2a73 100644 --- a/lldb/source/API/SBTypeFormat.cpp +++ b/lldb/source/API/SBTypeFormat.cpp @@ -157,7 +157,7 @@ bool SBTypeFormat::CopyOnWrite_Impl(Type type) { if (!IsValid()) return false; - if (m_opaque_sp.unique() && + if (m_opaque_sp.use_count() == 1 && ((type == Type::eTypeKeepSame) || (type == Type::eTypeFormat && m_opaque_sp->GetType() == TypeFormatImpl::Type::eTypeFormat) || diff --git a/lldb/source/API/SBTypeSummary.cpp b/lldb/source/API/SBTypeSummary.cpp index be43aeb4826..a5e87188c9f 100644 --- a/lldb/source/API/SBTypeSummary.cpp +++ b/lldb/source/API/SBTypeSummary.cpp @@ -381,7 +381,7 @@ bool SBTypeSummary::CopyOnWrite_Impl() { if (!IsValid()) return false; - if (m_opaque_sp.unique()) + if (m_opaque_sp.use_count() == 1) return true; TypeSummaryImplSP new_sp; diff --git a/lldb/source/API/SBTypeSynthetic.cpp b/lldb/source/API/SBTypeSynthetic.cpp index e2441eea7e1..19a4c53bad6 100644 --- a/lldb/source/API/SBTypeSynthetic.cpp +++ b/lldb/source/API/SBTypeSynthetic.cpp @@ -184,7 +184,7 @@ SBTypeSynthetic::SBTypeSynthetic( bool SBTypeSynthetic::CopyOnWrite_Impl() { if (!IsValid()) return false; - if (m_opaque_sp.unique()) + if (m_opaque_sp.use_count() == 1) return true; ScriptedSyntheticChildrenSP new_sp(new ScriptedSyntheticChildren( diff --git a/lldb/source/Breakpoint/Breakpoint.cpp b/lldb/source/Breakpoint/Breakpoint.cpp index 6e6b51b5624..af5dcc9cd88 100644 --- a/lldb/source/Breakpoint/Breakpoint.cpp +++ b/lldb/source/Breakpoint/Breakpoint.cpp @@ -460,17 +460,13 @@ void Breakpoint::ResolveBreakpointInModules(ModuleList &module_list, // If this is not an internal breakpoint, set up to record the new // locations, then dispatch an event with the new locations. if (!IsInternal() && send_event) { - BreakpointEventData *new_locations_event = new BreakpointEventData( - eBreakpointEventTypeLocationsAdded, shared_from_this()); - + std::shared_ptr new_locations_event = + std::make_shared( + eBreakpointEventTypeLocationsAdded, shared_from_this()); ResolveBreakpointInModules( module_list, new_locations_event->GetBreakpointLocationCollection()); - - if (new_locations_event->GetBreakpointLocationCollection().GetSize() != - 0) { + if (new_locations_event->GetBreakpointLocationCollection().GetSize() != 0) SendBreakpointChangedEvent(new_locations_event); - } else - delete new_locations_event; } else { ElapsedTime elapsed(m_resolve_time); m_resolver_sp->ResolveBreakpointInModules(*m_filter_sp, module_list); @@ -565,12 +561,10 @@ void Breakpoint::ModulesChanged(ModuleList &module_list, bool load, // the module list, then remove their breakpoint sites, and their locations // if asked to. - BreakpointEventData *removed_locations_event; + std::shared_ptr removed_locations_event; if (!IsInternal()) - removed_locations_event = new BreakpointEventData( + removed_locations_event = std::make_shared( eBreakpointEventTypeLocationsRemoved, shared_from_this()); - else - removed_locations_event = nullptr; for (ModuleSP module_sp : module_list.Modules()) { if (m_filter_sp->ModulePasses(module_sp)) { @@ -795,31 +789,30 @@ void Breakpoint::ModuleReplaced(ModuleSP old_module_sp, // about telling the world about removing a location we didn't tell them // about adding. - BreakpointEventData *locations_event; + std::shared_ptr removed_locations_event; if (!IsInternal()) - locations_event = new BreakpointEventData( + removed_locations_event = std::make_shared( eBreakpointEventTypeLocationsRemoved, shared_from_this()); - else - locations_event = nullptr; for (BreakpointLocationSP loc_sp : locations_to_remove.BreakpointLocations()) { m_locations.RemoveLocation(loc_sp); - if (locations_event) - locations_event->GetBreakpointLocationCollection().Add(loc_sp); + if (removed_locations_event) + removed_locations_event->GetBreakpointLocationCollection().Add(loc_sp); } - SendBreakpointChangedEvent(locations_event); + SendBreakpointChangedEvent(removed_locations_event); // And announce the new ones. if (!IsInternal()) { - locations_event = new BreakpointEventData( - eBreakpointEventTypeLocationsAdded, shared_from_this()); + std::shared_ptr added_locations_event = + std::make_shared( + eBreakpointEventTypeLocationsAdded, shared_from_this()); for (BreakpointLocationSP loc_sp : locations_to_announce.BreakpointLocations()) - locations_event->GetBreakpointLocationCollection().Add(loc_sp); + added_locations_event->GetBreakpointLocationCollection().Add(loc_sp); - SendBreakpointChangedEvent(locations_event); + SendBreakpointChangedEvent(added_locations_event); } m_locations.Compact(); } @@ -989,22 +982,22 @@ void Breakpoint::SendBreakpointChangedEvent( if (!m_being_created && !IsInternal() && GetTarget().EventTypeHasListeners( Target::eBroadcastBitBreakpointChanged)) { - BreakpointEventData *data = - new Breakpoint::BreakpointEventData(eventKind, shared_from_this()); + std::shared_ptr data = + std::make_shared(eventKind, shared_from_this()); GetTarget().BroadcastEvent(Target::eBroadcastBitBreakpointChanged, data); } } -void Breakpoint::SendBreakpointChangedEvent(BreakpointEventData *data) { - if (data == nullptr) +void Breakpoint::SendBreakpointChangedEvent( + const lldb::EventDataSP &breakpoint_data_sp) { + if (!breakpoint_data_sp) return; if (!m_being_created && !IsInternal() && GetTarget().EventTypeHasListeners(Target::eBroadcastBitBreakpointChanged)) - GetTarget().BroadcastEvent(Target::eBroadcastBitBreakpointChanged, data); - else - delete data; + GetTarget().BroadcastEvent(Target::eBroadcastBitBreakpointChanged, + breakpoint_data_sp); } const char *Breakpoint::BreakpointEventTypeAsCString(BreakpointEventType type) { diff --git a/lldb/source/Breakpoint/BreakpointIDList.cpp b/lldb/source/Breakpoint/BreakpointIDList.cpp index 05c461827ca..5ab2c9a8dc3 100644 --- a/lldb/source/Breakpoint/BreakpointIDList.cpp +++ b/lldb/source/Breakpoint/BreakpointIDList.cpp @@ -11,9 +11,9 @@ #include "lldb/Breakpoint/Breakpoint.h" #include "lldb/Breakpoint/BreakpointLocation.h" -#include "lldb/Interpreter/CommandReturnObject.h" #include "lldb/Target/Target.h" #include "lldb/Utility/Args.h" +#include "lldb/Utility/StreamString.h" using namespace lldb; using namespace lldb_private; @@ -48,15 +48,6 @@ bool BreakpointIDList::AddBreakpointID(BreakpointID bp_id) { // return true. } -bool BreakpointIDList::AddBreakpointID(const char *bp_id_str) { - auto bp_id = BreakpointID::ParseCanonicalReference(bp_id_str); - if (!bp_id) - return false; - - m_breakpoint_ids.push_back(*bp_id); - return true; -} - bool BreakpointIDList::FindBreakpointID(BreakpointID &bp_id, size_t *position) const { for (size_t i = 0; i < m_breakpoint_ids.size(); ++i) { @@ -93,12 +84,9 @@ bool BreakpointIDList::FindBreakpointID(const char *bp_id_str, // NEW_ARGS should be a copy of OLD_ARGS, with and ID range specifiers replaced // by the members of the range. -void BreakpointIDList::FindAndReplaceIDRanges(Args &old_args, Target *target, - bool allow_locations, - BreakpointName::Permissions - ::PermissionKinds purpose, - CommandReturnObject &result, - Args &new_args) { +llvm::Error BreakpointIDList::FindAndReplaceIDRanges( + Args &old_args, Target *target, bool allow_locations, + BreakpointName::Permissions ::PermissionKinds purpose, Args &new_args) { llvm::StringRef range_from; llvm::StringRef range_to; llvm::StringRef current_arg; @@ -109,11 +97,11 @@ void BreakpointIDList::FindAndReplaceIDRanges(Args &old_args, Target *target, current_arg = old_args[i].ref(); if (!allow_locations && current_arg.contains('.')) { - result.AppendErrorWithFormat( + new_args.Clear(); + return llvm::createStringError( + llvm::inconvertibleErrorCode(), "Breakpoint locations not allowed, saw location: %s.", current_arg.str().c_str()); - new_args.Clear(); - return; } Status error; @@ -125,8 +113,8 @@ void BreakpointIDList::FindAndReplaceIDRanges(Args &old_args, Target *target, } else if (BreakpointID::StringIsBreakpointName(current_arg, error)) { if (!error.Success()) { new_args.Clear(); - result.AppendError(error.AsCString()); - return; + return llvm::createStringError(llvm::inconvertibleErrorCode(), + error.AsCString()); } else names_found.insert(std::string(current_arg)); } else if ((i + 2 < old_args.size()) && @@ -152,9 +140,10 @@ void BreakpointIDList::FindAndReplaceIDRanges(Args &old_args, Target *target, breakpoint_sp = target->GetBreakpointByID(bp_id->GetBreakpointID()); if (!breakpoint_sp) { new_args.Clear(); - result.AppendErrorWithFormat("'%d' is not a valid breakpoint ID.\n", - bp_id->GetBreakpointID()); - return; + return llvm::createStringError( + llvm::inconvertibleErrorCode(), + "'%d' is not a valid breakpoint ID.\n", + bp_id->GetBreakpointID()); } const size_t num_locations = breakpoint_sp->GetNumLocations(); for (size_t j = 0; j < num_locations; ++j) { @@ -180,17 +169,17 @@ void BreakpointIDList::FindAndReplaceIDRanges(Args &old_args, Target *target, if (!start_bp || !target->GetBreakpointByID(start_bp->GetBreakpointID())) { new_args.Clear(); - result.AppendErrorWithFormat("'%s' is not a valid breakpoint ID.\n", - range_from.str().c_str()); - return; + return llvm::createStringError(llvm::inconvertibleErrorCode(), + "'%s' is not a valid breakpoint ID.\n", + range_from.str().c_str()); } if (!end_bp || !target->GetBreakpointByID(end_bp->GetBreakpointID())) { new_args.Clear(); - result.AppendErrorWithFormat("'%s' is not a valid breakpoint ID.\n", - range_to.str().c_str()); - return; + return llvm::createStringError(llvm::inconvertibleErrorCode(), + "'%s' is not a valid breakpoint ID.\n", + range_to.str().c_str()); } break_id_t start_bp_id = start_bp->GetBreakpointID(); break_id_t start_loc_id = start_bp->GetLocationID(); @@ -201,11 +190,11 @@ void BreakpointIDList::FindAndReplaceIDRanges(Args &old_args, Target *target, ((start_loc_id != LLDB_INVALID_BREAK_ID) && (end_loc_id == LLDB_INVALID_BREAK_ID))) { new_args.Clear(); - result.AppendError("Invalid breakpoint id range: Either " - "both ends of range must specify" - " a breakpoint location, or neither can " - "specify a breakpoint location."); - return; + return llvm::createStringError(llvm::inconvertibleErrorCode(), + "Invalid breakpoint id range: Either " + "both ends of range must specify" + " a breakpoint location, or neither can " + "specify a breakpoint location."); } // We have valid range starting & ending breakpoint IDs. Go through all @@ -221,13 +210,13 @@ void BreakpointIDList::FindAndReplaceIDRanges(Args &old_args, Target *target, (end_loc_id != LLDB_INVALID_BREAK_ID)) { if (start_bp_id != end_bp_id) { new_args.Clear(); - result.AppendErrorWithFormat( + return llvm::createStringError( + llvm::inconvertibleErrorCode(), "Invalid range: Ranges that specify particular breakpoint " "locations" " must be within the same major breakpoint; you specified two" " different major breakpoints, %d and %d.\n", start_bp_id, end_bp_id); - return; } } @@ -302,8 +291,7 @@ void BreakpointIDList::FindAndReplaceIDRanges(Args &old_args, Target *target, } } } - - result.SetStatus(eReturnStatusSuccessFinishNoResult); + return llvm::Error::success(); } std::pair diff --git a/lldb/source/Breakpoint/BreakpointList.cpp b/lldb/source/Breakpoint/BreakpointList.cpp index f7c2cdb938e..2c47b3b1263 100644 --- a/lldb/source/Breakpoint/BreakpointList.cpp +++ b/lldb/source/Breakpoint/BreakpointList.cpp @@ -17,9 +17,12 @@ using namespace lldb_private; static void NotifyChange(const BreakpointSP &bp, BreakpointEventType event) { Target &target = bp->GetTarget(); - if (target.EventTypeHasListeners(Target::eBroadcastBitBreakpointChanged)) + if (target.EventTypeHasListeners(Target::eBroadcastBitBreakpointChanged)) { + auto event_data_sp = + std::make_shared(event, bp); target.BroadcastEvent(Target::eBroadcastBitBreakpointChanged, - new Breakpoint::BreakpointEventData(event, bp)); + event_data_sp); + } } BreakpointList::BreakpointList(bool is_internal) diff --git a/lldb/source/Breakpoint/BreakpointLocation.cpp b/lldb/source/Breakpoint/BreakpointLocation.cpp index 99f94d04bb3..98de059c2e2 100644 --- a/lldb/source/Breakpoint/BreakpointLocation.cpp +++ b/lldb/source/Breakpoint/BreakpointLocation.cpp @@ -649,11 +649,11 @@ void BreakpointLocation::SendBreakpointLocationChangedEvent( if (!m_being_created && !m_owner.IsInternal() && m_owner.GetTarget().EventTypeHasListeners( Target::eBroadcastBitBreakpointChanged)) { - Breakpoint::BreakpointEventData *data = new Breakpoint::BreakpointEventData( + auto data_sp = std::make_shared( eventKind, m_owner.shared_from_this()); - data->GetBreakpointLocationCollection().Add(shared_from_this()); + data_sp->GetBreakpointLocationCollection().Add(shared_from_this()); m_owner.GetTarget().BroadcastEvent(Target::eBroadcastBitBreakpointChanged, - data); + data_sp); } } diff --git a/lldb/source/Breakpoint/BreakpointResolver.cpp b/lldb/source/Breakpoint/BreakpointResolver.cpp index 89ea308b1eb..bc6348716ef 100644 --- a/lldb/source/Breakpoint/BreakpointResolver.cpp +++ b/lldb/source/Breakpoint/BreakpointResolver.cpp @@ -214,7 +214,8 @@ void BreakpointResolver::SetSCMatchesByLine( auto worklist_begin = std::partition( all_scs.begin(), all_scs.end(), [&](const SymbolContext &sc) { if (sc.line_entry.file == match.line_entry.file || - sc.line_entry.original_file == match.line_entry.original_file) { + *sc.line_entry.original_file_sp == + *match.line_entry.original_file_sp) { // When a match is found, keep track of the smallest line number. closest_line = std::min(closest_line, sc.line_entry.line); return false; diff --git a/lldb/source/Breakpoint/Watchpoint.cpp b/lldb/source/Breakpoint/Watchpoint.cpp index 4602ce4213b..1a8ef87c1e6 100644 --- a/lldb/source/Breakpoint/Watchpoint.cpp +++ b/lldb/source/Breakpoint/Watchpoint.cpp @@ -462,26 +462,14 @@ const char *Watchpoint::GetConditionText() const { void Watchpoint::SendWatchpointChangedEvent( lldb::WatchpointEventType eventKind) { - if (!m_being_created && - GetTarget().EventTypeHasListeners( - Target::eBroadcastBitWatchpointChanged)) { - WatchpointEventData *data = - new Watchpoint::WatchpointEventData(eventKind, shared_from_this()); - GetTarget().BroadcastEvent(Target::eBroadcastBitWatchpointChanged, data); + if (!m_being_created && GetTarget().EventTypeHasListeners( + Target::eBroadcastBitWatchpointChanged)) { + auto data_sp = + std::make_shared(eventKind, shared_from_this()); + GetTarget().BroadcastEvent(Target::eBroadcastBitWatchpointChanged, data_sp); } } -void Watchpoint::SendWatchpointChangedEvent(WatchpointEventData *data) { - if (data == nullptr) - return; - - if (!m_being_created && - GetTarget().EventTypeHasListeners(Target::eBroadcastBitWatchpointChanged)) - GetTarget().BroadcastEvent(Target::eBroadcastBitWatchpointChanged, data); - else - delete data; -} - Watchpoint::WatchpointEventData::WatchpointEventData( WatchpointEventType sub_type, const WatchpointSP &new_watchpoint_sp) : m_watchpoint_event(sub_type), m_new_watchpoint_sp(new_watchpoint_sp) {} diff --git a/lldb/source/Breakpoint/WatchpointList.cpp b/lldb/source/Breakpoint/WatchpointList.cpp index fc0cc9126d6..f7564483e6f 100644 --- a/lldb/source/Breakpoint/WatchpointList.cpp +++ b/lldb/source/Breakpoint/WatchpointList.cpp @@ -23,10 +23,12 @@ lldb::watch_id_t WatchpointList::Add(const WatchpointSP &wp_sp, bool notify) { m_watchpoints.push_back(wp_sp); if (notify) { if (wp_sp->GetTarget().EventTypeHasListeners( - Target::eBroadcastBitWatchpointChanged)) + Target::eBroadcastBitWatchpointChanged)) { + auto data_sp = std::make_shared( + eWatchpointEventTypeAdded, wp_sp); wp_sp->GetTarget().BroadcastEvent(Target::eBroadcastBitWatchpointChanged, - new Watchpoint::WatchpointEventData( - eWatchpointEventTypeAdded, wp_sp)); + data_sp); + } } return wp_sp->GetID(); } @@ -171,11 +173,12 @@ bool WatchpointList::Remove(lldb::watch_id_t watch_id, bool notify) { WatchpointSP wp_sp = *pos; if (notify) { if (wp_sp->GetTarget().EventTypeHasListeners( - Target::eBroadcastBitWatchpointChanged)) + Target::eBroadcastBitWatchpointChanged)) { + auto data_sp = std::make_shared( + eWatchpointEventTypeRemoved, wp_sp); wp_sp->GetTarget().BroadcastEvent( - Target::eBroadcastBitWatchpointChanged, - new Watchpoint::WatchpointEventData(eWatchpointEventTypeRemoved, - wp_sp)); + Target::eBroadcastBitWatchpointChanged, data_sp); + } } m_watchpoints.erase(pos); return true; @@ -234,10 +237,10 @@ void WatchpointList::RemoveAll(bool notify) { for (pos = m_watchpoints.begin(); pos != end; ++pos) { if ((*pos)->GetTarget().EventTypeHasListeners( Target::eBroadcastBitBreakpointChanged)) { + auto data_sp = std::make_shared( + eWatchpointEventTypeRemoved, *pos); (*pos)->GetTarget().BroadcastEvent( - Target::eBroadcastBitWatchpointChanged, - new Watchpoint::WatchpointEventData(eWatchpointEventTypeRemoved, - *pos)); + Target::eBroadcastBitWatchpointChanged, data_sp); } } } diff --git a/lldb/source/Commands/CommandObjectBreakpoint.cpp b/lldb/source/Commands/CommandObjectBreakpoint.cpp index f9ba68eda3f..1661d5d9b74 100644 --- a/lldb/source/Commands/CommandObjectBreakpoint.cpp +++ b/lldb/source/Commands/CommandObjectBreakpoint.cpp @@ -2488,8 +2488,12 @@ void CommandObjectMultiwordBreakpoint::VerifyIDs( // breakpoint ids in the range, and shove all of those breakpoint id strings // into TEMP_ARGS. - BreakpointIDList::FindAndReplaceIDRanges(args, target, allow_locations, - purpose, result, temp_args); + if (llvm::Error err = BreakpointIDList::FindAndReplaceIDRanges( + args, target, allow_locations, purpose, temp_args)) { + result.SetError(std::move(err)); + return; + } + result.SetStatus(eReturnStatusSuccessFinishNoResult); // NOW, convert the list of breakpoint id strings in TEMP_ARGS into an actual // BreakpointIDList: @@ -2501,33 +2505,31 @@ void CommandObjectMultiwordBreakpoint::VerifyIDs( // At this point, all of the breakpoint ids that the user passed in have // been converted to breakpoint IDs and put into valid_ids. - if (result.Succeeded()) { - // Now that we've converted everything from args into a list of breakpoint - // ids, go through our tentative list of breakpoint id's and verify that - // they correspond to valid/currently set breakpoints. + // Now that we've converted everything from args into a list of breakpoint + // ids, go through our tentative list of breakpoint id's and verify that + // they correspond to valid/currently set breakpoints. - const size_t count = valid_ids->GetSize(); - for (size_t i = 0; i < count; ++i) { - BreakpointID cur_bp_id = valid_ids->GetBreakpointIDAtIndex(i); - Breakpoint *breakpoint = - target->GetBreakpointByID(cur_bp_id.GetBreakpointID()).get(); - if (breakpoint != nullptr) { - const size_t num_locations = breakpoint->GetNumLocations(); - if (static_cast(cur_bp_id.GetLocationID()) > num_locations) { - StreamString id_str; - BreakpointID::GetCanonicalReference( - &id_str, cur_bp_id.GetBreakpointID(), cur_bp_id.GetLocationID()); - i = valid_ids->GetSize() + 1; - result.AppendErrorWithFormat( - "'%s' is not a currently valid breakpoint/location id.\n", - id_str.GetData()); - } - } else { + const size_t count = valid_ids->GetSize(); + for (size_t i = 0; i < count; ++i) { + BreakpointID cur_bp_id = valid_ids->GetBreakpointIDAtIndex(i); + Breakpoint *breakpoint = + target->GetBreakpointByID(cur_bp_id.GetBreakpointID()).get(); + if (breakpoint != nullptr) { + const size_t num_locations = breakpoint->GetNumLocations(); + if (static_cast(cur_bp_id.GetLocationID()) > num_locations) { + StreamString id_str; + BreakpointID::GetCanonicalReference( + &id_str, cur_bp_id.GetBreakpointID(), cur_bp_id.GetLocationID()); i = valid_ids->GetSize() + 1; result.AppendErrorWithFormat( - "'%d' is not a currently valid breakpoint ID.\n", - cur_bp_id.GetBreakpointID()); + "'%s' is not a currently valid breakpoint/location id.\n", + id_str.GetData()); } + } else { + i = valid_ids->GetSize() + 1; + result.AppendErrorWithFormat( + "'%d' is not a currently valid breakpoint ID.\n", + cur_bp_id.GetBreakpointID()); } } } diff --git a/lldb/source/Commands/CommandObjectFrame.cpp b/lldb/source/Commands/CommandObjectFrame.cpp index e7cb861c2b0..17a7e858b24 100644 --- a/lldb/source/Commands/CommandObjectFrame.cpp +++ b/lldb/source/Commands/CommandObjectFrame.cpp @@ -494,6 +494,7 @@ protected: case eValueTypeVTableEntry: return false; } + llvm_unreachable("Unexpected scope value"); } /// Finds all the variables in `all_variables` whose name matches `regex`, diff --git a/lldb/source/Commands/CommandObjectSource.cpp b/lldb/source/Commands/CommandObjectSource.cpp index cabf6f0436f..fde74f02aea 100644 --- a/lldb/source/Commands/CommandObjectSource.cpp +++ b/lldb/source/Commands/CommandObjectSource.cpp @@ -747,13 +747,13 @@ protected: bool operator==(const SourceInfo &rhs) const { return function == rhs.function && - line_entry.original_file == rhs.line_entry.original_file && + *line_entry.original_file_sp == *rhs.line_entry.original_file_sp && line_entry.line == rhs.line_entry.line; } bool operator!=(const SourceInfo &rhs) const { return function != rhs.function || - line_entry.original_file != rhs.line_entry.original_file || + *line_entry.original_file_sp != *rhs.line_entry.original_file_sp || line_entry.line != rhs.line_entry.line; } diff --git a/lldb/source/Commands/CommandObjectTarget.cpp b/lldb/source/Commands/CommandObjectTarget.cpp index bc8bc51356c..c3ecdb7700c 100644 --- a/lldb/source/Commands/CommandObjectTarget.cpp +++ b/lldb/source/Commands/CommandObjectTarget.cpp @@ -53,6 +53,7 @@ #include "lldb/Utility/FileSpec.h" #include "lldb/Utility/LLDBLog.h" #include "lldb/Utility/State.h" +#include "lldb/Utility/Stream.h" #include "lldb/Utility/StructuredData.h" #include "lldb/Utility/Timer.h" #include "lldb/lldb-enumerations.h" @@ -1531,9 +1532,10 @@ static void DumpOsoFilesTable(Stream &strm, }); } -static void DumpAddress(ExecutionContextScope *exe_scope, - const Address &so_addr, bool verbose, bool all_ranges, - Stream &strm, llvm::StringRef pattern = "") { +static void +DumpAddress(ExecutionContextScope *exe_scope, const Address &so_addr, + bool verbose, bool all_ranges, Stream &strm, + std::optional settings = std::nullopt) { strm.IndentMore(); strm.Indent(" Address: "); so_addr.Dump(&strm, exe_scope, Address::DumpStyleModuleWithFileAddress); @@ -1544,13 +1546,13 @@ static void DumpAddress(ExecutionContextScope *exe_scope, const uint32_t save_indent = strm.GetIndentLevel(); strm.SetIndentLevel(save_indent + 13); so_addr.Dump(&strm, exe_scope, Address::DumpStyleResolvedDescription, - Address::DumpStyleInvalid, UINT32_MAX, false, pattern); + Address::DumpStyleInvalid, UINT32_MAX, false, settings); strm.SetIndentLevel(save_indent); // Print out detailed address information when verbose is enabled if (verbose) { strm.EOL(); so_addr.Dump(&strm, exe_scope, Address::DumpStyleDetailedSymbolContext, - Address::DumpStyleInvalid, UINT32_MAX, all_ranges, pattern); + Address::DumpStyleInvalid, UINT32_MAX, all_ranges, settings); } strm.IndentLess(); } @@ -1615,6 +1617,9 @@ static uint32_t LookupSymbolInModule(CommandInterpreter &interpreter, DumpFullpath(strm, &module->GetFileSpec(), 0); strm.PutCString(":\n"); strm.IndentMore(); + Stream::HighlightSettings settings( + name, interpreter.GetDebugger().GetRegexMatchAnsiPrefix(), + interpreter.GetDebugger().GetRegexMatchAnsiSuffix()); for (uint32_t i = 0; i < num_matches; ++i) { Symbol *symbol = symtab->SymbolAtIndex(match_indexes[i]); if (symbol) { @@ -1622,18 +1627,18 @@ static uint32_t LookupSymbolInModule(CommandInterpreter &interpreter, DumpAddress( interpreter.GetExecutionContext().GetBestExecutionContextScope(), symbol->GetAddressRef(), verbose, all_ranges, strm, - use_color && name_is_regex ? name : nullptr); + use_color && name_is_regex + ? std::optional{settings} + : std::nullopt); strm.EOL(); } else { strm.IndentMore(); strm.Indent(" Name: "); - llvm::StringRef ansi_prefix = - interpreter.GetDebugger().GetRegexMatchAnsiPrefix(); - llvm::StringRef ansi_suffix = - interpreter.GetDebugger().GetRegexMatchAnsiSuffix(); strm.PutCStringColorHighlighted( symbol->GetDisplayName().GetStringRef(), - use_color ? name : nullptr, ansi_prefix, ansi_suffix); + use_color && name_is_regex + ? std::optional{settings} + : std::nullopt); strm.EOL(); strm.Indent(" Value: "); strm.Printf("0x%16.16" PRIx64 "\n", symbol->GetRawValue()); @@ -1650,10 +1655,10 @@ static uint32_t LookupSymbolInModule(CommandInterpreter &interpreter, return num_matches; } -static void DumpSymbolContextList(ExecutionContextScope *exe_scope, - Stream &strm, - const SymbolContextList &sc_list, - bool verbose, bool all_ranges) { +static void DumpSymbolContextList( + ExecutionContextScope *exe_scope, Stream &strm, + const SymbolContextList &sc_list, bool verbose, bool all_ranges, + std::optional settings = std::nullopt) { strm.IndentMore(); bool first_module = true; for (const SymbolContext &sc : sc_list) { @@ -1664,7 +1669,8 @@ static void DumpSymbolContextList(ExecutionContextScope *exe_scope, sc.GetAddressRange(eSymbolContextEverything, 0, true, range); - DumpAddress(exe_scope, range.GetBaseAddress(), verbose, all_ranges, strm); + DumpAddress(exe_scope, range.GetBaseAddress(), verbose, all_ranges, strm, + settings); first_module = false; } strm.IndentLess(); diff --git a/lldb/source/Core/Address.cpp b/lldb/source/Core/Address.cpp index 19d34db44ea..6f5c366ab38 100644 --- a/lldb/source/Core/Address.cpp +++ b/lldb/source/Core/Address.cpp @@ -407,7 +407,8 @@ bool Address::GetDescription(Stream &s, Target &target, bool Address::Dump(Stream *s, ExecutionContextScope *exe_scope, DumpStyle style, DumpStyle fallback_style, uint32_t addr_size, - bool all_ranges, llvm::StringRef pattern) const { + bool all_ranges, + std::optional settings) const { // If the section was nullptr, only load address is going to work unless we // are trying to deref a pointer SectionSP section_sp(GetSection()); @@ -516,16 +517,7 @@ bool Address::Dump(Stream *s, ExecutionContextScope *exe_scope, DumpStyle style, if (symbol) { const char *symbol_name = symbol->GetName().AsCString(); if (symbol_name) { - llvm::StringRef ansi_prefix; - llvm::StringRef ansi_suffix; - if (target) { - ansi_prefix = - target->GetDebugger().GetRegexMatchAnsiPrefix(); - ansi_suffix = - target->GetDebugger().GetRegexMatchAnsiSuffix(); - } - s->PutCStringColorHighlighted(symbol_name, pattern, - ansi_prefix, ansi_suffix); + s->PutCStringColorHighlighted(symbol_name, settings); addr_t delta = file_Addr - symbol->GetAddressRef().GetFileAddress(); if (delta) @@ -653,7 +645,7 @@ bool Address::Dump(Stream *s, ExecutionContextScope *exe_scope, DumpStyle style, pointer_sc.symbol != nullptr) { s->PutCString(": "); pointer_sc.DumpStopContext(s, exe_scope, so_addr, true, false, - false, true, true, pattern); + false, true, true, settings); } } } @@ -693,13 +685,13 @@ bool Address::Dump(Stream *s, ExecutionContextScope *exe_scope, DumpStyle style, sc.DumpStopContext(s, exe_scope, *this, show_fullpaths, show_module, show_inlined_frames, show_function_arguments, show_function_name, - pattern); + settings); } else { // We found a symbol but it was in a different section so it // isn't the symbol we should be showing, just show the section // name + offset Dump(s, exe_scope, DumpStyleSectionNameOffset, DumpStyleInvalid, - UINT32_MAX, false, pattern); + UINT32_MAX, false, settings); } } } @@ -707,7 +699,7 @@ bool Address::Dump(Stream *s, ExecutionContextScope *exe_scope, DumpStyle style, } else { if (fallback_style != DumpStyleInvalid) return Dump(s, exe_scope, fallback_style, DumpStyleInvalid, addr_size, - false, pattern); + false, settings); return false; } break; @@ -728,7 +720,7 @@ bool Address::Dump(Stream *s, ExecutionContextScope *exe_scope, DumpStyle style, sc.symbol->GetAddressRef().GetSection() != GetSection()) sc.symbol = nullptr; } - sc.GetDescription(s, eDescriptionLevelBrief, target, pattern); + sc.GetDescription(s, eDescriptionLevelBrief, target, settings); if (sc.block) { bool can_create = true; @@ -777,7 +769,7 @@ bool Address::Dump(Stream *s, ExecutionContextScope *exe_scope, DumpStyle style, } else { if (fallback_style != DumpStyleInvalid) return Dump(s, exe_scope, fallback_style, DumpStyleInvalid, addr_size, - false, pattern); + false, settings); return false; } break; diff --git a/lldb/source/Core/Disassembler.cpp b/lldb/source/Core/Disassembler.cpp index 166b5fdf22f..7b07fcb2681 100644 --- a/lldb/source/Core/Disassembler.cpp +++ b/lldb/source/Core/Disassembler.cpp @@ -202,7 +202,7 @@ Disassembler::GetFunctionDeclLineEntry(const SymbolContext &sc) { sc.function->GetStartLineSourceInfo(func_decl_file, func_decl_line); if (func_decl_file != prologue_end_line.file && - func_decl_file != prologue_end_line.original_file) + func_decl_file != prologue_end_line.original_file_sp->GetSpecOnly()) return {}; SourceLine decl_line; @@ -407,7 +407,8 @@ void Disassembler::PrintInstructions(Debugger &debugger, const ArchSpec &arch, sc.function->GetStartLineSourceInfo(func_decl_file, func_decl_line); if (func_decl_file == prologue_end_line.file || - func_decl_file == prologue_end_line.original_file) { + func_decl_file == + prologue_end_line.original_file_sp->GetSpecOnly()) { // Add all the lines between the function declaration and // the first non-prologue source line to the list of lines // to print. diff --git a/lldb/source/Core/FormatEntity.cpp b/lldb/source/Core/FormatEntity.cpp index 94986457552..3c665c2eb21 100644 --- a/lldb/source/Core/FormatEntity.cpp +++ b/lldb/source/Core/FormatEntity.cpp @@ -1093,6 +1093,19 @@ static void PrettyPrintFunctionNameWithArgs(Stream &out_stream, out_stream.PutChar(')'); } +static void FormatInlinedBlock(Stream &out_stream, Block *block) { + if (!block) + return; + Block *inline_block = block->GetContainingInlinedBlock(); + if (inline_block) { + if (const InlineFunctionInfo *inline_info = + inline_block->GetInlinedFunctionInfo()) { + out_stream.PutCString(" [inlined] "); + inline_info->GetName().Dump(&out_stream); + } + } +} + bool FormatEntity::FormatStringRef(const llvm::StringRef &format_str, Stream &s, const SymbolContext *sc, const ExecutionContext *exe_ctx, @@ -1592,18 +1605,7 @@ bool FormatEntity::Format(const Entry &entry, Stream &s, if (name) { s.PutCString(name); - - if (sc->block) { - Block *inline_block = sc->block->GetContainingInlinedBlock(); - if (inline_block) { - const InlineFunctionInfo *inline_info = - sc->block->GetInlinedFunctionInfo(); - if (inline_info) { - s.PutCString(" [inlined] "); - inline_info->GetName().Dump(&s); - } - } - } + FormatInlinedBlock(s, sc->block); return true; } } @@ -1638,6 +1640,7 @@ bool FormatEntity::Format(const Entry &entry, Stream &s, name = sc->symbol->GetNameNoArguments(); if (name) { s.PutCString(name.GetCString()); + FormatInlinedBlock(s, sc->block); return true; } } @@ -1678,7 +1681,7 @@ bool FormatEntity::Format(const Entry &entry, Stream &s, if (inline_block) { get_function_vars = false; - inline_info = sc->block->GetInlinedFunctionInfo(); + inline_info = inline_block->GetInlinedFunctionInfo(); if (inline_info) variable_list_sp = inline_block->GetBlockVariableList(true); } @@ -1733,14 +1736,7 @@ bool FormatEntity::Format(const Entry &entry, Stream &s, if (!name) return false; s.PutCString(name); - - if (sc->block && sc->block->GetContainingInlinedBlock()) { - if (const InlineFunctionInfo *inline_info = - sc->block->GetInlinedFunctionInfo()) { - s.PutCString(" [inlined] "); - inline_info->GetName().Dump(&s); - } - } + FormatInlinedBlock(s, sc->block); return true; } case Entry::Type::FunctionAddrOffset: diff --git a/lldb/source/Core/Module.cpp b/lldb/source/Core/Module.cpp index 331cf324664..8ffa35518b3 100644 --- a/lldb/source/Core/Module.cpp +++ b/lldb/source/Core/Module.cpp @@ -971,14 +971,14 @@ void Module::FindTypes(const TypeQuery &query, TypeResults &results) { symbols->FindTypes(query, results); } -static Debugger::DebuggerList +static Debugger::DebuggerList DebuggersOwningModuleRequestingInterruption(Module &module) { - Debugger::DebuggerList requestors - = Debugger::DebuggersRequestingInterruption(); + Debugger::DebuggerList requestors = + Debugger::DebuggersRequestingInterruption(); Debugger::DebuggerList interruptors; if (requestors.empty()) return interruptors; - + for (auto debugger_sp : requestors) { if (!debugger_sp->InterruptRequested()) continue; @@ -993,12 +993,12 @@ SymbolFile *Module::GetSymbolFile(bool can_create, Stream *feedback_strm) { if (!m_did_load_symfile.load()) { std::lock_guard guard(m_mutex); if (!m_did_load_symfile.load() && can_create) { - Debugger::DebuggerList interruptors - = DebuggersOwningModuleRequestingInterruption(*this); + Debugger::DebuggerList interruptors = + DebuggersOwningModuleRequestingInterruption(*this); if (!interruptors.empty()) { for (auto debugger_sp : interruptors) { - REPORT_INTERRUPTION(*(debugger_sp.get()), - "Interrupted fetching symbols for module {0}", + REPORT_INTERRUPTION(*(debugger_sp.get()), + "Interrupted fetching symbols for module {0}", this->GetFileSpec()); } return nullptr; diff --git a/lldb/source/Core/ModuleList.cpp b/lldb/source/Core/ModuleList.cpp index 2180f29f369..b7f393636ba 100644 --- a/lldb/source/Core/ModuleList.cpp +++ b/lldb/source/Core/ModuleList.cpp @@ -211,7 +211,29 @@ ModuleList::~ModuleList() = default; void ModuleList::AppendImpl(const ModuleSP &module_sp, bool use_notifier) { if (module_sp) { std::lock_guard guard(m_modules_mutex); - m_modules.push_back(module_sp); + // We are required to keep the first element of the Module List as the + // executable module. So check here and if the first module is NOT an + // but the new one is, we insert this module at the beginning, rather than + // at the end. + // We don't need to do any of this if the list is empty: + if (m_modules.empty()) { + m_modules.push_back(module_sp); + } else { + // Since producing the ObjectFile may take some work, first check the 0th + // element, and only if that's NOT an executable look at the incoming + // ObjectFile. That way in the normal case we only look at the element + // 0 ObjectFile. + const bool elem_zero_is_executable + = m_modules[0]->GetObjectFile()->GetType() + == ObjectFile::Type::eTypeExecutable; + lldb_private::ObjectFile *obj = module_sp->GetObjectFile(); + if (!elem_zero_is_executable && obj + && obj->GetType() == ObjectFile::Type::eTypeExecutable) { + m_modules.insert(m_modules.begin(), module_sp); + } else { + m_modules.push_back(module_sp); + } + } if (use_notifier && m_notifier) m_notifier->NotifyModuleAdded(*this, module_sp); } @@ -324,7 +346,7 @@ bool ModuleList::RemoveIfOrphaned(const Module *module_ptr) { collection::iterator pos, end = m_modules.end(); for (pos = m_modules.begin(); pos != end; ++pos) { if (pos->get() == module_ptr) { - if (pos->unique()) { + if (pos->use_count() == 1) { pos = RemoveImpl(pos); return true; } else @@ -355,7 +377,7 @@ size_t ModuleList::RemoveOrphans(bool mandatory) { made_progress = false; collection::iterator pos = m_modules.begin(); while (pos != m_modules.end()) { - if (pos->unique()) { + if (pos->use_count() == 1) { pos = RemoveImpl(pos); ++remove_count; // We did make progress. diff --git a/lldb/source/Core/Progress.cpp b/lldb/source/Core/Progress.cpp index ea3f874916a..355d6952e53 100644 --- a/lldb/source/Core/Progress.cpp +++ b/lldb/source/Core/Progress.cpp @@ -11,15 +11,22 @@ #include "lldb/Core/Debugger.h" #include "lldb/Utility/StreamString.h" +#include + using namespace lldb; using namespace lldb_private; std::atomic Progress::g_id(0); -Progress::Progress(std::string title, uint64_t total, +Progress::Progress(std::string title, std::string details, + std::optional total, lldb_private::Debugger *debugger) - : m_title(title), m_id(++g_id), m_completed(0), m_total(total) { - assert(total > 0); + : m_title(title), m_details(details), m_id(++g_id), m_completed(0), + m_total(1) { + assert(total == std::nullopt || total > 0); + if (total) + m_total = *total; + if (debugger) m_debugger_id = debugger->GetID(); std::lock_guard guard(m_mutex); @@ -35,25 +42,28 @@ Progress::~Progress() { ReportProgress(); } -void Progress::Increment(uint64_t amount, std::string update) { +void Progress::Increment(uint64_t amount, + std::optional updated_detail) { if (amount > 0) { std::lock_guard guard(m_mutex); + if (updated_detail) + m_details = std::move(updated_detail.value()); // Watch out for unsigned overflow and make sure we don't increment too // much and exceed m_total. - if (amount > (m_total - m_completed)) + if (m_total && (amount > (m_total - m_completed))) m_completed = m_total; else m_completed += amount; - ReportProgress(update); + ReportProgress(); } } -void Progress::ReportProgress(std::string update) { +void Progress::ReportProgress() { if (!m_complete) { // Make sure we only send one notification that indicates the progress is - // complete. + // complete m_complete = m_completed == m_total; - Debugger::ReportProgress(m_id, m_title, std::move(update), m_completed, - m_total, m_debugger_id); + Debugger::ReportProgress(m_id, m_title, m_details, m_completed, m_total, + m_debugger_id); } } diff --git a/lldb/source/Core/ValueObject.cpp b/lldb/source/Core/ValueObject.cpp index b2a6d9412ab..d58bf2ca763 100644 --- a/lldb/source/Core/ValueObject.cpp +++ b/lldb/source/Core/ValueObject.cpp @@ -813,8 +813,7 @@ static bool CopyStringDataToBufferSP(const StreamString &source, std::pair ValueObject::ReadPointedString(lldb::WritableDataBufferSP &buffer_sp, - Status &error, uint32_t max_length, - bool honor_array, Format item_format) { + Status &error, bool honor_array) { bool was_capped = false; StreamString s; ExecutionContext exe_ctx(GetExecutionContextRef()); @@ -827,8 +826,7 @@ ValueObject::ReadPointedString(lldb::WritableDataBufferSP &buffer_sp, return {0, was_capped}; } - if (max_length == 0) - max_length = target->GetMaximumSizeOfStringSummary(); + const auto max_length = target->GetMaximumSizeOfStringSummary(); size_t bytes_read = 0; size_t total_bytes_read = 0; @@ -1149,9 +1147,10 @@ bool ValueObject::DumpPrintableRepresentation( { Status error; lldb::WritableDataBufferSP buffer_sp; - std::pair read_string = ReadPointedString( - buffer_sp, error, 0, (custom_format == eFormatVectorOfChar) || - (custom_format == eFormatCharArray)); + std::pair read_string = + ReadPointedString(buffer_sp, error, + (custom_format == eFormatVectorOfChar) || + (custom_format == eFormatCharArray)); lldb_private::formatters::StringPrinter:: ReadBufferAndDumpToStreamOptions options(*this); options.SetData(DataExtractor( @@ -1583,62 +1582,64 @@ bool ValueObject::IsUninitializedReference() { ValueObjectSP ValueObject::GetSyntheticArrayMember(size_t index, bool can_create) { - ValueObjectSP synthetic_child_sp; - if (IsPointerType() || IsArrayType()) { - std::string index_str = llvm::formatv("[{0}]", index); - ConstString index_const_str(index_str); - // Check if we have already created a synthetic array member in this valid - // object. If we have we will re-use it. - synthetic_child_sp = GetSyntheticChild(index_const_str); - if (!synthetic_child_sp) { - ValueObject *synthetic_child; - // We haven't made a synthetic array member for INDEX yet, so lets make - // one and cache it for any future reference. - synthetic_child = CreateChildAtIndex(0, true, index); + if (!IsPointerType() && !IsArrayType()) + return ValueObjectSP(); - // Cache the value if we got one back... - if (synthetic_child) { - AddSyntheticChild(index_const_str, synthetic_child); - synthetic_child_sp = synthetic_child->GetSP(); - synthetic_child_sp->SetName(ConstString(index_str)); - synthetic_child_sp->m_flags.m_is_array_item_for_pointer = true; - } - } - } + std::string index_str = llvm::formatv("[{0}]", index); + ConstString index_const_str(index_str); + // Check if we have already created a synthetic array member in this valid + // object. If we have we will re-use it. + if (auto existing_synthetic_child = GetSyntheticChild(index_const_str)) + return existing_synthetic_child; + + // We haven't made a synthetic array member for INDEX yet, so lets make + // one and cache it for any future reference. + ValueObject *synthetic_child = CreateChildAtIndex(0, true, index); + + if (!synthetic_child) + return ValueObjectSP(); + + // Cache the synthetic child's value because it's valid. + AddSyntheticChild(index_const_str, synthetic_child); + auto synthetic_child_sp = synthetic_child->GetSP(); + synthetic_child_sp->SetName(ConstString(index_str)); + synthetic_child_sp->m_flags.m_is_array_item_for_pointer = true; return synthetic_child_sp; } ValueObjectSP ValueObject::GetSyntheticBitFieldChild(uint32_t from, uint32_t to, bool can_create) { - ValueObjectSP synthetic_child_sp; - if (IsScalarType()) { - std::string index_str = llvm::formatv("[{0}-{1}]", from, to); - ConstString index_const_str(index_str); - // Check if we have already created a synthetic array member in this valid - // object. If we have we will re-use it. - synthetic_child_sp = GetSyntheticChild(index_const_str); - if (!synthetic_child_sp) { - uint32_t bit_field_size = to - from + 1; - uint32_t bit_field_offset = from; - if (GetDataExtractor().GetByteOrder() == eByteOrderBig) - bit_field_offset = - GetByteSize().value_or(0) * 8 - bit_field_size - bit_field_offset; - // We haven't made a synthetic array member for INDEX yet, so lets make - // one and cache it for any future reference. - ValueObjectChild *synthetic_child = new ValueObjectChild( - *this, GetCompilerType(), index_const_str, GetByteSize().value_or(0), - 0, bit_field_size, bit_field_offset, false, false, - eAddressTypeInvalid, 0); + if (!IsScalarType()) + return ValueObjectSP(); - // Cache the value if we got one back... - if (synthetic_child) { - AddSyntheticChild(index_const_str, synthetic_child); - synthetic_child_sp = synthetic_child->GetSP(); - synthetic_child_sp->SetName(ConstString(index_str)); - synthetic_child_sp->m_flags.m_is_bitfield_for_scalar = true; - } - } - } + std::string index_str = llvm::formatv("[{0}-{1}]", from, to); + ConstString index_const_str(index_str); + + // Check if we have already created a synthetic array member in this valid + // object. If we have we will re-use it. + if (auto existing_synthetic_child = GetSyntheticChild(index_const_str)) + return existing_synthetic_child; + + uint32_t bit_field_size = to - from + 1; + uint32_t bit_field_offset = from; + if (GetDataExtractor().GetByteOrder() == eByteOrderBig) + bit_field_offset = + GetByteSize().value_or(0) * 8 - bit_field_size - bit_field_offset; + + // We haven't made a synthetic array member for INDEX yet, so lets make + // one and cache it for any future reference. + ValueObjectChild *synthetic_child = new ValueObjectChild( + *this, GetCompilerType(), index_const_str, GetByteSize().value_or(0), 0, + bit_field_size, bit_field_offset, false, false, eAddressTypeInvalid, 0); + + if (!synthetic_child) + return ValueObjectSP(); + + // Cache the synthetic child's value because it's valid. + AddSyntheticChild(index_const_str, synthetic_child); + auto synthetic_child_sp = synthetic_child->GetSP(); + synthetic_child_sp->SetName(ConstString(index_str)); + synthetic_child_sp->m_flags.m_is_bitfield_for_scalar = true; return synthetic_child_sp; } @@ -1648,9 +1649,8 @@ ValueObjectSP ValueObject::GetSyntheticChildAtOffset( ValueObjectSP synthetic_child_sp; - if (name_const_str.IsEmpty()) { + if (name_const_str.IsEmpty()) name_const_str.SetString("@" + std::to_string(offset)); - } // Check if we have already created a synthetic array member in this valid // object. If we have we will re-use it. @@ -1660,13 +1660,13 @@ ValueObjectSP ValueObject::GetSyntheticChildAtOffset( return synthetic_child_sp; if (!can_create) - return {}; + return ValueObjectSP(); ExecutionContext exe_ctx(GetExecutionContextRef()); std::optional size = type.GetByteSize(exe_ctx.GetBestExecutionContextScope()); if (!size) - return {}; + return ValueObjectSP(); ValueObjectChild *synthetic_child = new ValueObjectChild(*this, type, name_const_str, *size, offset, 0, 0, false, false, eAddressTypeInvalid, 0); @@ -1700,7 +1700,7 @@ ValueObjectSP ValueObject::GetSyntheticBase(uint32_t offset, return synthetic_child_sp; if (!can_create) - return {}; + return ValueObjectSP(); const bool is_base_class = true; @@ -1708,7 +1708,7 @@ ValueObjectSP ValueObject::GetSyntheticBase(uint32_t offset, std::optional size = type.GetByteSize(exe_ctx.GetBestExecutionContextScope()); if (!size) - return {}; + return ValueObjectSP(); ValueObjectChild *synthetic_child = new ValueObjectChild(*this, type, name_const_str, *size, offset, 0, 0, is_base_class, false, eAddressTypeInvalid, 0); @@ -1737,30 +1737,30 @@ static const char *SkipLeadingExpressionPathSeparators(const char *expression) { ValueObjectSP ValueObject::GetSyntheticExpressionPathChild(const char *expression, bool can_create) { - ValueObjectSP synthetic_child_sp; ConstString name_const_string(expression); // Check if we have already created a synthetic array member in this valid // object. If we have we will re-use it. - synthetic_child_sp = GetSyntheticChild(name_const_string); - if (!synthetic_child_sp) { - // We haven't made a synthetic array member for expression yet, so lets - // make one and cache it for any future reference. - synthetic_child_sp = GetValueForExpressionPath( - expression, nullptr, nullptr, - GetValueForExpressionPathOptions().SetSyntheticChildrenTraversal( - GetValueForExpressionPathOptions::SyntheticChildrenTraversal:: - None)); + if (auto existing_synthetic_child = GetSyntheticChild(name_const_string)) + return existing_synthetic_child; - // Cache the value if we got one back... - if (synthetic_child_sp.get()) { - // FIXME: this causes a "real" child to end up with its name changed to - // the contents of expression - AddSyntheticChild(name_const_string, synthetic_child_sp.get()); - synthetic_child_sp->SetName( - ConstString(SkipLeadingExpressionPathSeparators(expression))); - } - } - return synthetic_child_sp; + // We haven't made a synthetic array member for expression yet, so lets + // make one and cache it for any future reference. + auto path_options = GetValueForExpressionPathOptions(); + path_options.SetSyntheticChildrenTraversal( + GetValueForExpressionPathOptions::SyntheticChildrenTraversal::None); + auto synthetic_child = + GetValueForExpressionPath(expression, nullptr, nullptr, path_options); + + if (!synthetic_child) + return ValueObjectSP(); + + // Cache the synthetic child's value because it's valid. + // FIXME: this causes a "real" child to end up with its name changed to + // the contents of expression + AddSyntheticChild(name_const_string, synthetic_child.get()); + synthetic_child->SetName( + ConstString(SkipLeadingExpressionPathSeparators(expression))); + return synthetic_child; } void ValueObject::CalculateSyntheticValue() { @@ -1957,66 +1957,55 @@ ValueObjectSP ValueObject::GetValueForExpressionPath( const GetValueForExpressionPathOptions &options, ExpressionPathAftermath *final_task_on_target) { - ExpressionPathScanEndReason dummy_reason_to_stop = - ValueObject::eExpressionPathScanEndReasonUnknown; - ExpressionPathEndResultType dummy_final_value_type = - ValueObject::eExpressionPathEndResultTypeInvalid; - ExpressionPathAftermath dummy_final_task_on_target = - ValueObject::eExpressionPathAftermathNothing; + auto dummy_stop_reason = eExpressionPathScanEndReasonUnknown; + auto dummy_value_type = eExpressionPathEndResultTypeInvalid; + auto dummy_final_task = eExpressionPathAftermathNothing; - ValueObjectSP ret_val = GetValueForExpressionPath_Impl( - expression, reason_to_stop ? reason_to_stop : &dummy_reason_to_stop, - final_value_type ? final_value_type : &dummy_final_value_type, options, - final_task_on_target ? final_task_on_target - : &dummy_final_task_on_target); + auto proxy_stop_reason = reason_to_stop ? reason_to_stop : &dummy_stop_reason; + auto proxy_value_type = + final_value_type ? final_value_type : &dummy_value_type; + auto proxy_final_task = + final_task_on_target ? final_task_on_target : &dummy_final_task; - if (!final_task_on_target || - *final_task_on_target == ValueObject::eExpressionPathAftermathNothing) - return ret_val; + auto ret_value = GetValueForExpressionPath_Impl(expression, proxy_stop_reason, + proxy_value_type, options, + proxy_final_task); - if (ret_val.get() && - ((final_value_type ? *final_value_type : dummy_final_value_type) == - eExpressionPathEndResultTypePlain)) // I can only deref and takeaddress - // of plain objects - { - if ((final_task_on_target ? *final_task_on_target - : dummy_final_task_on_target) == - ValueObject::eExpressionPathAftermathDereference) { - Status error; - ValueObjectSP final_value = ret_val->Dereference(error); - if (error.Fail() || !final_value.get()) { - if (reason_to_stop) - *reason_to_stop = - ValueObject::eExpressionPathScanEndReasonDereferencingFailed; - if (final_value_type) - *final_value_type = ValueObject::eExpressionPathEndResultTypeInvalid; - return ValueObjectSP(); - } else { - if (final_task_on_target) - *final_task_on_target = ValueObject::eExpressionPathAftermathNothing; - return final_value; - } - } - if (*final_task_on_target == - ValueObject::eExpressionPathAftermathTakeAddress) { - Status error; - ValueObjectSP final_value = ret_val->AddressOf(error); - if (error.Fail() || !final_value.get()) { - if (reason_to_stop) - *reason_to_stop = - ValueObject::eExpressionPathScanEndReasonTakingAddressFailed; - if (final_value_type) - *final_value_type = ValueObject::eExpressionPathEndResultTypeInvalid; - return ValueObjectSP(); - } else { - if (final_task_on_target) - *final_task_on_target = ValueObject::eExpressionPathAftermathNothing; - return final_value; - } - } + // The caller knows nothing happened if `final_task_on_target` doesn't change. + if (!ret_value || (*proxy_value_type) != eExpressionPathEndResultTypePlain || + !final_task_on_target) + return ValueObjectSP(); + + ExpressionPathAftermath &final_task_on_target_ref = (*final_task_on_target); + ExpressionPathScanEndReason stop_reason_for_error; + Status error; + // The method can only dereference and take the address of plain objects. + switch (final_task_on_target_ref) { + case eExpressionPathAftermathNothing: + return ret_value; + + case eExpressionPathAftermathDereference: + ret_value = ret_value->Dereference(error); + stop_reason_for_error = eExpressionPathScanEndReasonDereferencingFailed; + break; + + case eExpressionPathAftermathTakeAddress: + ret_value = ret_value->AddressOf(error); + stop_reason_for_error = eExpressionPathScanEndReasonTakingAddressFailed; + break; } - return ret_val; // final_task_on_target will still have its original value, so - // you know I did not do it + + if (ret_value && error.Success()) { + final_task_on_target_ref = eExpressionPathAftermathNothing; + return ret_value; + } + + if (reason_to_stop) + *reason_to_stop = stop_reason_for_error; + + if (final_value_type) + *final_value_type = eExpressionPathEndResultTypeInvalid; + return ValueObjectSP(); } ValueObjectSP ValueObject::GetValueForExpressionPath_Impl( @@ -2687,39 +2676,47 @@ ValueObjectSP ValueObject::AddressOf(Status &error) { const bool scalar_is_load_address = false; addr_t addr = GetAddressOf(scalar_is_load_address, &address_type); error.Clear(); - if (addr != LLDB_INVALID_ADDRESS && address_type != eAddressTypeHost) { - switch (address_type) { - case eAddressTypeInvalid: { - StreamString expr_path_strm; - GetExpressionPath(expr_path_strm); - error.SetErrorStringWithFormat("'%s' is not in memory", - expr_path_strm.GetData()); - } break; - case eAddressTypeFile: - case eAddressTypeLoad: { - CompilerType compiler_type = GetCompilerType(); - if (compiler_type) { - std::string name(1, '&'); - name.append(m_name.AsCString("")); - ExecutionContext exe_ctx(GetExecutionContextRef()); - m_addr_of_valobj_sp = ValueObjectConstResult::Create( - exe_ctx.GetBestExecutionContextScope(), - compiler_type.GetPointerType(), ConstString(name.c_str()), addr, - eAddressTypeInvalid, m_data.GetAddressByteSize()); - } - } break; - default: - break; - } - } else { - StreamString expr_path_strm; - GetExpressionPath(expr_path_strm); + StreamString expr_path_strm; + GetExpressionPath(expr_path_strm); + const char *expr_path_str = expr_path_strm.GetData(); + + ExecutionContext exe_ctx(GetExecutionContextRef()); + auto scope = exe_ctx.GetBestExecutionContextScope(); + + if (addr == LLDB_INVALID_ADDRESS) { error.SetErrorStringWithFormat("'%s' doesn't have a valid address", - expr_path_strm.GetData()); + expr_path_str); + return ValueObjectSP(); } - return m_addr_of_valobj_sp; + switch (address_type) { + case eAddressTypeInvalid: + error.SetErrorStringWithFormat("'%s' is not in memory", expr_path_str); + return ValueObjectSP(); + + case eAddressTypeHost: + error.SetErrorStringWithFormat("'%s' is in host process (LLDB) memory", + expr_path_str); + return ValueObjectSP(); + + case eAddressTypeFile: + case eAddressTypeLoad: { + CompilerType compiler_type = GetCompilerType(); + if (!compiler_type) { + error.SetErrorStringWithFormat("'%s' doesn't have a compiler type", + expr_path_str); + return ValueObjectSP(); + } + + std::string name(1, '&'); + name.append(m_name.AsCString("")); + m_addr_of_valobj_sp = ValueObjectConstResult::Create( + scope, compiler_type.GetPointerType(), ConstString(name.c_str()), addr, + eAddressTypeInvalid, m_data.GetAddressByteSize()); + return m_addr_of_valobj_sp; + } + } } ValueObjectSP ValueObject::DoCast(const CompilerType &compiler_type) { diff --git a/lldb/source/Expression/DiagnosticManager.cpp b/lldb/source/Expression/DiagnosticManager.cpp index 08977066e33..9a1100df78d 100644 --- a/lldb/source/Expression/DiagnosticManager.cpp +++ b/lldb/source/Expression/DiagnosticManager.cpp @@ -46,11 +46,20 @@ static const char *StringForSeverity(DiagnosticSeverity severity) { std::string DiagnosticManager::GetString(char separator) { std::string ret; + llvm::raw_string_ostream stream(ret); for (const auto &diagnostic : Diagnostics()) { - ret.append(StringForSeverity(diagnostic->GetSeverity())); - ret.append(std::string(diagnostic->GetMessage())); - ret.push_back(separator); + llvm::StringRef severity = StringForSeverity(diagnostic->GetSeverity()); + stream << severity; + + llvm::StringRef message = diagnostic->GetMessage(); + std::string searchable_message = message.lower(); + auto severity_pos = message.find(severity); + stream << message.take_front(severity_pos); + + if (severity_pos != llvm::StringRef::npos) + stream << message.drop_front(severity_pos + severity.size()); + stream << separator; } return ret; diff --git a/lldb/source/Plugins/Instruction/ARM/EmulateInstructionARM.cpp b/lldb/source/Plugins/Instruction/ARM/EmulateInstructionARM.cpp index ff5c79aa245..b652ede9b1f 100644 --- a/lldb/source/Plugins/Instruction/ARM/EmulateInstructionARM.cpp +++ b/lldb/source/Plugins/Instruction/ARM/EmulateInstructionARM.cpp @@ -830,6 +830,7 @@ uint32_t EmulateInstructionARM::GetFramePointerRegisterNumber() const { case llvm::Triple::IOS: case llvm::Triple::TvOS: case llvm::Triple::WatchOS: + case llvm::Triple::XROS: // NEED_BRIDGEOS_TRIPLE case llvm::Triple::BridgeOS: is_apple = true; break; diff --git a/lldb/source/Plugins/Language/CPlusPlus/CPlusPlusLanguage.cpp b/lldb/source/Plugins/Language/CPlusPlus/CPlusPlusLanguage.cpp index c6937ebca31..f0fe6c9e06d 100644 --- a/lldb/source/Plugins/Language/CPlusPlus/CPlusPlusLanguage.cpp +++ b/lldb/source/Plugins/Language/CPlusPlus/CPlusPlusLanguage.cpp @@ -1032,6 +1032,31 @@ static void LoadLibCxxFormatters(lldb::TypeCategoryImplSP cpp_category_sp) { TypeSummaryImplSP(new StringSummaryFormat( eTypeOptionHideChildren | eTypeOptionHideValue, "${var.__rep_} s"))); + // Chrono time point types + + AddCXXSummary(cpp_category_sp, + lldb_private::formatters::LibcxxChronoSysSecondsSummaryProvider, + "libc++ std::chrono::sys_seconds summary provider", + "^std::__[[:alnum:]]+::chrono::time_point<" + "std::__[[:alnum:]]+::chrono::system_clock, " + "std::__[[:alnum:]]+::chrono::duration " + "> >$", + eTypeOptionHideChildren | eTypeOptionHideValue | + eTypeOptionCascade, + true); + AddCXXSummary(cpp_category_sp, + lldb_private::formatters::LibcxxChronoSysDaysSummaryProvider, + "libc++ std::chrono::sys_seconds summary provider", + "^std::__[[:alnum:]]+::chrono::time_point<" + "std::__[[:alnum:]]+::chrono::system_clock, " + "std::__[[:alnum:]]+::chrono::duration " + "> >$", + eTypeOptionHideChildren | eTypeOptionHideValue | + eTypeOptionCascade, + true); + // Chrono calendar types cpp_category_sp->AddTypeSummary( @@ -1039,6 +1064,7 @@ static void LoadLibCxxFormatters(lldb::TypeCategoryImplSP cpp_category_sp) { TypeSummaryImplSP(new StringSummaryFormat(eTypeOptionHideChildren | eTypeOptionHideValue, "day=${var.__d_%u}"))); + AddCXXSummary(cpp_category_sp, lldb_private::formatters::LibcxxChronoMonthSummaryProvider, "libc++ std::chrono::month summary provider", @@ -1050,6 +1076,23 @@ static void LoadLibCxxFormatters(lldb::TypeCategoryImplSP cpp_category_sp) { TypeSummaryImplSP(new StringSummaryFormat( eTypeOptionHideChildren | eTypeOptionHideValue, "year=${var.__y_}"))); + AddCXXSummary(cpp_category_sp, + lldb_private::formatters::LibcxxChronoWeekdaySummaryProvider, + "libc++ std::chrono::weekday summary provider", + "^std::__[[:alnum:]]+::chrono::weekday$", + eTypeOptionHideChildren | eTypeOptionHideValue, true); + + cpp_category_sp->AddTypeSummary( + "^std::__[[:alnum:]]+::chrono::weekday_indexed$", eFormatterMatchRegex, + TypeSummaryImplSP(new StringSummaryFormat( + eTypeOptionHideChildren | eTypeOptionHideValue, + "${var.__wd_} index=${var.__idx_%u}"))); + + cpp_category_sp->AddTypeSummary( + "^std::__[[:alnum:]]+::chrono::weekday_last$", eFormatterMatchRegex, + TypeSummaryImplSP(new StringSummaryFormat(eTypeOptionHideChildren | + eTypeOptionHideValue, + "${var.__wd_} index=last"))); cpp_category_sp->AddTypeSummary( "^std::__[[:alnum:]]+::chrono::month_day$", eFormatterMatchRegex, TypeSummaryImplSP(new StringSummaryFormat(eTypeOptionHideChildren | @@ -1060,12 +1103,51 @@ static void LoadLibCxxFormatters(lldb::TypeCategoryImplSP cpp_category_sp) { TypeSummaryImplSP(new StringSummaryFormat(eTypeOptionHideChildren | eTypeOptionHideValue, "${var.__m_} day=last"))); + + cpp_category_sp->AddTypeSummary( + "^std::__[[:alnum:]]+::chrono::month_weekday$", eFormatterMatchRegex, + TypeSummaryImplSP(new StringSummaryFormat(eTypeOptionHideChildren | + eTypeOptionHideValue, + "${var.__m_} ${var.__wdi_}"))); + + cpp_category_sp->AddTypeSummary( + "^std::__[[:alnum:]]+::chrono::month_weekday_last$", eFormatterMatchRegex, + TypeSummaryImplSP(new StringSummaryFormat(eTypeOptionHideChildren | + eTypeOptionHideValue, + "${var.__m_} ${var.__wdl_}"))); + + cpp_category_sp->AddTypeSummary( + "^std::__[[:alnum:]]+::chrono::year_month$", eFormatterMatchRegex, + TypeSummaryImplSP(new StringSummaryFormat(eTypeOptionHideChildren | + eTypeOptionHideValue, + "${var.__y_} ${var.__m_}"))); + AddCXXSummary( cpp_category_sp, lldb_private::formatters::LibcxxChronoYearMonthDaySummaryProvider, "libc++ std::chrono::year_month_day summary provider", "^std::__[[:alnum:]]+::chrono::year_month_day$", eTypeOptionHideChildren | eTypeOptionHideValue, true); + + cpp_category_sp->AddTypeSummary( + "^std::__[[:alnum:]]+::chrono::year_month_day_last$", + eFormatterMatchRegex, + TypeSummaryImplSP(new StringSummaryFormat(eTypeOptionHideChildren | + eTypeOptionHideValue, + "${var.__y_} ${var.__mdl_}"))); + + cpp_category_sp->AddTypeSummary( + "^std::__[[:alnum:]]+::chrono::year_month_weekday$", eFormatterMatchRegex, + TypeSummaryImplSP(new StringSummaryFormat( + eTypeOptionHideChildren | eTypeOptionHideValue, + "${var.__y_} ${var.__m_} ${var.__wdi_}"))); + + cpp_category_sp->AddTypeSummary( + "^std::__[[:alnum:]]+::chrono::year_month_weekday_last$", + eFormatterMatchRegex, + TypeSummaryImplSP(new StringSummaryFormat( + eTypeOptionHideChildren | eTypeOptionHideValue, + "${var.__y_} ${var.__m_} ${var.__wdl_}"))); } static void LoadLibStdcppFormatters(lldb::TypeCategoryImplSP cpp_category_sp) { @@ -1589,7 +1671,7 @@ bool CPlusPlusLanguage::GetFunctionDisplayName( if (inline_block) { get_function_vars = false; - inline_info = sc->block->GetInlinedFunctionInfo(); + inline_info = inline_block->GetInlinedFunctionInfo(); if (inline_info) variable_list_sp = inline_block->GetBlockVariableList(true); } diff --git a/lldb/source/Plugins/Language/CPlusPlus/LibCxx.cpp b/lldb/source/Plugins/Language/CPlusPlus/LibCxx.cpp index f8be4f785dc..060324e2fcf 100644 --- a/lldb/source/Plugins/Language/CPlusPlus/LibCxx.cpp +++ b/lldb/source/Plugins/Language/CPlusPlus/LibCxx.cpp @@ -1073,18 +1073,87 @@ bool lldb_private::formatters::LibcxxWStringViewSummaryProvider( bool success; ValueObjectSP dataobj; size_t size; - std::tie( success, dataobj, size ) = LibcxxExtractStringViewData(valobj); + std::tie(success, dataobj, size) = LibcxxExtractStringViewData(valobj); if (!success) { stream << "Summary Unavailable"; return true; } - return ::LibcxxWStringSummaryProvider(valobj, stream, summary_options, dataobj, size); } +bool lldb_private::formatters::LibcxxChronoSysSecondsSummaryProvider( + ValueObject &valobj, Stream &stream, const TypeSummaryOptions &options) { + ValueObjectSP ptr_sp = valobj.GetChildMemberWithName("__d_"); + if (!ptr_sp) + return false; + ptr_sp = ptr_sp->GetChildMemberWithName("__rep_"); + if (!ptr_sp) + return false; + + // The date time in the chrono library is valid in the range + // [-32767-01-01T00:00:00Z, 32767-12-31T23:59:59Z]. A 64-bit time_t has a + // larger range, the function strftime is not able to format the entire range + // of time_t. The exact point has not been investigated; it's limited to + // chrono's range. + const std::time_t chrono_timestamp_min = + -1'096'193'779'200; // -32767-01-01T00:00:00Z + const std::time_t chrono_timestamp_max = + 971'890'963'199; // 32767-12-31T23:59:59Z + + const std::time_t seconds = ptr_sp->GetValueAsSigned(0); + if (seconds < chrono_timestamp_min || seconds > chrono_timestamp_max) + stream.Printf("timestamp=%ld s", seconds); + else { + std::array str; + std::size_t size = + std::strftime(str.data(), str.size(), "%FT%H:%M:%SZ", gmtime(&seconds)); + if (size == 0) + return false; + + stream.Printf("date/time=%s timestamp=%ld s", str.data(), seconds); + } + + return true; +} + +bool lldb_private::formatters::LibcxxChronoSysDaysSummaryProvider( + ValueObject &valobj, Stream &stream, const TypeSummaryOptions &options) { + ValueObjectSP ptr_sp = valobj.GetChildMemberWithName("__d_"); + if (!ptr_sp) + return false; + ptr_sp = ptr_sp->GetChildMemberWithName("__rep_"); + if (!ptr_sp) + return false; + + // The date time in the chrono library is valid in the range + // [-32767-01-01Z, 32767-12-31Z]. A 32-bit time_t has a larger range, the + // function strftime is not able to format the entire range of time_t. The + // exact point has not been investigated; it's limited to chrono's range. + const int chrono_timestamp_min = -12'687'428; // -32767-01-01Z + const int chrono_timestamp_max = 11'248'737; // 32767-12-31Z + + const int days = ptr_sp->GetValueAsSigned(0); + if (days < chrono_timestamp_min || days > chrono_timestamp_max) + stream.Printf("timestamp=%d days", days); + + else { + const std::time_t seconds = std::time_t(86400) * days; + + std::array str; + std::size_t size = + std::strftime(str.data(), str.size(), "%FZ", gmtime(&seconds)); + if (size == 0) + return false; + + stream.Printf("date=%s timestamp=%d days", str.data(), days); + } + + return true; +} + bool lldb_private::formatters::LibcxxChronoMonthSummaryProvider( ValueObject &valobj, Stream &stream, const TypeSummaryOptions &options) { // FIXME: These are the names used in the C++20 ostream operator. Since LLVM @@ -1106,6 +1175,27 @@ bool lldb_private::formatters::LibcxxChronoMonthSummaryProvider( return true; } +bool lldb_private::formatters::LibcxxChronoWeekdaySummaryProvider( + ValueObject &valobj, Stream &stream, const TypeSummaryOptions &options) { + // FIXME: These are the names used in the C++20 ostream operator. Since LLVM + // uses C++17 it's not possible to use the ostream operator directly. + static const std::array weekdays = { + "Sunday", "Monday", "Tuesday", "Wednesday", + "Thursday", "Friday", "Saturday"}; + + ValueObjectSP ptr_sp = valobj.GetChildMemberWithName("__wd_"); + if (!ptr_sp) + return false; + + const unsigned weekday = ptr_sp->GetValueAsUnsigned(0); + if (weekday >= 0 && weekday < 7) + stream << "weekday=" << weekdays[weekday]; + else + stream.Printf("weekday=%u", weekday); + + return true; +} + bool lldb_private::formatters::LibcxxChronoYearMonthDaySummaryProvider( ValueObject &valobj, Stream &stream, const TypeSummaryOptions &options) { ValueObjectSP ptr_sp = valobj.GetChildMemberWithName("__y_"); diff --git a/lldb/source/Plugins/Language/CPlusPlus/LibCxx.h b/lldb/source/Plugins/Language/CPlusPlus/LibCxx.h index c252ae382dd..72da6b2426e 100644 --- a/lldb/source/Plugins/Language/CPlusPlus/LibCxx.h +++ b/lldb/source/Plugins/Language/CPlusPlus/LibCxx.h @@ -261,10 +261,22 @@ SyntheticChildrenFrontEnd * LibcxxStdRangesRefViewSyntheticFrontEndCreator(CXXSyntheticChildren *, lldb::ValueObjectSP); +bool LibcxxChronoSysSecondsSummaryProvider( + ValueObject &valobj, Stream &stream, + const TypeSummaryOptions &options); // libc++ std::chrono::sys_seconds + +bool LibcxxChronoSysDaysSummaryProvider( + ValueObject &valobj, Stream &stream, + const TypeSummaryOptions &options); // libc++ std::chrono::sys_days + bool LibcxxChronoMonthSummaryProvider( ValueObject &valobj, Stream &stream, const TypeSummaryOptions &options); // libc++ std::chrono::month +bool LibcxxChronoWeekdaySummaryProvider( + ValueObject &valobj, Stream &stream, + const TypeSummaryOptions &options); // libc++ std::chrono::weekday + bool LibcxxChronoYearMonthDaySummaryProvider( ValueObject &valobj, Stream &stream, const TypeSummaryOptions &options); // libc++ std::chrono::year_month_day diff --git a/lldb/source/Plugins/LanguageRuntime/ObjC/AppleObjCRuntime/AppleObjCRuntimeV2.cpp b/lldb/source/Plugins/LanguageRuntime/ObjC/AppleObjCRuntime/AppleObjCRuntimeV2.cpp index dc492ac0f06..f380d6e7e67 100644 --- a/lldb/source/Plugins/LanguageRuntime/ObjC/AppleObjCRuntime/AppleObjCRuntimeV2.cpp +++ b/lldb/source/Plugins/LanguageRuntime/ObjC/AppleObjCRuntime/AppleObjCRuntimeV2.cpp @@ -1893,15 +1893,15 @@ AppleObjCRuntimeV2::DynamicClassInfoExtractor::ComputeHelper( if (loader->IsFullyInitialized()) { switch (exe_ctx.GetTargetRef().GetDynamicClassInfoHelper()) { case eDynamicClassInfoHelperAuto: - [[clang::fallthrough]]; + LLVM_FALLTHROUGH; case eDynamicClassInfoHelperGetRealizedClassList: if (m_runtime.m_has_objc_getRealizedClassList_trylock) return DynamicClassInfoExtractor::objc_getRealizedClassList_trylock; - [[clang::fallthrough]]; + LLVM_FALLTHROUGH; case eDynamicClassInfoHelperCopyRealizedClassList: if (m_runtime.m_has_objc_copyRealizedClassList) return DynamicClassInfoExtractor::objc_copyRealizedClassList; - [[clang::fallthrough]]; + LLVM_FALLTHROUGH; case eDynamicClassInfoHelperRealizedClassesStruct: return DynamicClassInfoExtractor::gdb_objc_realized_classes; } diff --git a/lldb/source/Plugins/ObjectFile/ELF/ObjectFileELF.cpp b/lldb/source/Plugins/ObjectFile/ELF/ObjectFileELF.cpp index 43ab87f08e1..0d95a1c12bd 100644 --- a/lldb/source/Plugins/ObjectFile/ELF/ObjectFileELF.cpp +++ b/lldb/source/Plugins/ObjectFile/ELF/ObjectFileELF.cpp @@ -2897,9 +2897,8 @@ void ObjectFileELF::ParseSymtab(Symtab &lldb_symtab) { if (!module_sp) return; - Progress progress( - llvm::formatv("Parsing symbol table for {0}", - m_file.GetFilename().AsCString(""))); + Progress progress("Parsing symbol table", + m_file.GetFilename().AsCString("")); ElapsedTime elapsed(module_sp->GetSymtabParseTime()); // We always want to use the main object file so we (hopefully) only have one diff --git a/lldb/source/Plugins/Process/Utility/RegisterContextPOSIX_mips64.cpp b/lldb/source/Plugins/Process/Utility/RegisterContextPOSIX_mips64.cpp index 9e05737d8e6..3685d6ac72a 100644 --- a/lldb/source/Plugins/Process/Utility/RegisterContextPOSIX_mips64.cpp +++ b/lldb/source/Plugins/Process/Utility/RegisterContextPOSIX_mips64.cpp @@ -98,26 +98,15 @@ RegisterContextPOSIX_mips64::GetRegisterInfoAtIndex(size_t reg) { } size_t RegisterContextPOSIX_mips64::GetRegisterSetCount() { - ArchSpec target_arch = m_register_info_up->GetTargetArchitecture(); - switch (target_arch.GetTriple().getOS()) { - default: { - const auto *context = static_cast( - m_register_info_up.get()); - return context->GetRegisterSetCount(); - } - - } + const auto *context = static_cast( + m_register_info_up.get()); + return context->GetRegisterSetCount(); } const RegisterSet *RegisterContextPOSIX_mips64::GetRegisterSet(size_t set) { - ArchSpec target_arch = m_register_info_up->GetTargetArchitecture(); - switch (target_arch.GetTriple().getOS()) { - default: { - const auto *context = static_cast( - m_register_info_up.get()); - return context->GetRegisterSet(set); - } - } + const auto *context = static_cast( + m_register_info_up.get()); + return context->GetRegisterSet(set); } const char *RegisterContextPOSIX_mips64::GetRegisterName(unsigned reg) { diff --git a/lldb/source/Plugins/Process/gdb-remote/GDBRemoteCommunicationClient.cpp b/lldb/source/Plugins/Process/gdb-remote/GDBRemoteCommunicationClient.cpp index ad72b3d121e..7bb44984185 100644 --- a/lldb/source/Plugins/Process/gdb-remote/GDBRemoteCommunicationClient.cpp +++ b/lldb/source/Plugins/Process/gdb-remote/GDBRemoteCommunicationClient.cpp @@ -1180,7 +1180,8 @@ bool GDBRemoteCommunicationClient::GetDefaultThreadId(lldb::tid_t &tid) { static void ParseOSType(llvm::StringRef value, std::string &os_name, std::string &environment) { if (value.equals("iossimulator") || value.equals("tvossimulator") || - value.equals("watchossimulator")) { + value.equals("watchossimulator") || value.equals("xrossimulator") || + value.equals("visionossimulator")) { environment = "simulator"; os_name = value.drop_back(environment.size()).str(); } else if (value.equals("maccatalyst")) { diff --git a/lldb/source/Plugins/Process/gdb-remote/ProcessGDBRemote.cpp b/lldb/source/Plugins/Process/gdb-remote/ProcessGDBRemote.cpp index 316be471df9..eb42b9eb6cb 100644 --- a/lldb/source/Plugins/Process/gdb-remote/ProcessGDBRemote.cpp +++ b/lldb/source/Plugins/Process/gdb-remote/ProcessGDBRemote.cpp @@ -1089,8 +1089,8 @@ Status ProcessGDBRemote::DoAttachToProcessWithID( const int packet_len = ::snprintf(packet, sizeof(packet), "vAttach;%" PRIx64, attach_pid); SetID(attach_pid); - m_async_broadcaster.BroadcastEvent( - eBroadcastBitAsyncContinue, new EventDataBytes(packet, packet_len)); + auto data_sp = std::make_shared(packet, packet_len); + m_async_broadcaster.BroadcastEvent(eBroadcastBitAsyncContinue, data_sp); } else SetExitStatus(-1, error.AsCString()); } @@ -1127,9 +1127,9 @@ Status ProcessGDBRemote::DoAttachToProcessWithName( endian::InlHostByteOrder(), endian::InlHostByteOrder()); - m_async_broadcaster.BroadcastEvent( - eBroadcastBitAsyncContinue, - new EventDataBytes(packet.GetString().data(), packet.GetSize())); + auto data_sp = std::make_shared(packet.GetString().data(), + packet.GetSize()); + m_async_broadcaster.BroadcastEvent(eBroadcastBitAsyncContinue, data_sp); } else SetExitStatus(-1, error.AsCString()); @@ -1374,10 +1374,9 @@ Status ProcessGDBRemote::DoResume() { return error; } - m_async_broadcaster.BroadcastEvent( - eBroadcastBitAsyncContinue, - new EventDataBytes(continue_packet.GetString().data(), - continue_packet.GetSize())); + auto data_sp = std::make_shared( + continue_packet.GetString().data(), continue_packet.GetSize()); + m_async_broadcaster.BroadcastEvent(eBroadcastBitAsyncContinue, data_sp); if (!listener_sp->GetEvent(event_sp, std::chrono::seconds(5))) { error.SetErrorString("Resume timed out."); @@ -4189,52 +4188,55 @@ static std::vector ParseFlagsFields(XMLNode flags_node, // Note that XML in general requires that each of these attributes only // appears once, so we don't have to handle that here. if (attr_name == "name") { - LLDB_LOG(log, - "ProcessGDBRemote::ParseFlags Found field node name \"{0}\"", - attr_value.data()); + LLDB_LOG( + log, + "ProcessGDBRemote::ParseFlagsFields Found field node name \"{0}\"", + attr_value.data()); name = attr_value; } else if (attr_name == "start") { unsigned parsed_start = 0; if (llvm::to_integer(attr_value, parsed_start)) { if (parsed_start > max_start_bit) { - LLDB_LOG( - log, - "ProcessGDBRemote::ParseFlags Invalid start {0} in field node, " - "cannot be > {1}", - parsed_start, max_start_bit); + LLDB_LOG(log, + "ProcessGDBRemote::ParseFlagsFields Invalid start {0} in " + "field node, " + "cannot be > {1}", + parsed_start, max_start_bit); } else start = parsed_start; } else { - LLDB_LOG(log, - "ProcessGDBRemote::ParseFlags Invalid start \"{0}\" in " - "field node", - attr_value.data()); + LLDB_LOG( + log, + "ProcessGDBRemote::ParseFlagsFields Invalid start \"{0}\" in " + "field node", + attr_value.data()); } } else if (attr_name == "end") { unsigned parsed_end = 0; if (llvm::to_integer(attr_value, parsed_end)) if (parsed_end > max_start_bit) { - LLDB_LOG( - log, - "ProcessGDBRemote::ParseFlags Invalid end {0} in field node, " - "cannot be > {1}", - parsed_end, max_start_bit); + LLDB_LOG(log, + "ProcessGDBRemote::ParseFlagsFields Invalid end {0} in " + "field node, " + "cannot be > {1}", + parsed_end, max_start_bit); } else end = parsed_end; else { - LLDB_LOG( - log, - "ProcessGDBRemote::ParseFlags Invalid end \"{0}\" in field node", - attr_value.data()); + LLDB_LOG(log, + "ProcessGDBRemote::ParseFlagsFields Invalid end \"{0}\" in " + "field node", + attr_value.data()); } } else if (attr_name == "type") { // Type is a known attribute but we do not currently use it and it is // not required. } else { - LLDB_LOG(log, - "ProcessGDBRemote::ParseFlags Ignoring unknown attribute " - "\"{0}\" in field node", - attr_name.data()); + LLDB_LOG( + log, + "ProcessGDBRemote::ParseFlagsFields Ignoring unknown attribute " + "\"{0}\" in field node", + attr_name.data()); } return true; // Walk all attributes of the field. @@ -4242,10 +4244,11 @@ static std::vector ParseFlagsFields(XMLNode flags_node, if (name && start && end) { if (*start > *end) { - LLDB_LOG(log, - "ProcessGDBRemote::ParseFlags Start {0} > end {1} in field " - "\"{2}\", ignoring", - *start, *end, name->data()); + LLDB_LOG( + log, + "ProcessGDBRemote::ParseFlagsFields Start {0} > end {1} in field " + "\"{2}\", ignoring", + *start, *end, name->data()); } else { fields.push_back(RegisterFlags::Field(name->str(), *start, *end)); } diff --git a/lldb/source/Plugins/SymbolFile/Breakpad/SymbolFileBreakpad.cpp b/lldb/source/Plugins/SymbolFile/Breakpad/SymbolFileBreakpad.cpp index 47c8074adc5..b1f7397d6b0 100644 --- a/lldb/source/Plugins/SymbolFile/Breakpad/SymbolFileBreakpad.cpp +++ b/lldb/source/Plugins/SymbolFile/Breakpad/SymbolFileBreakpad.cpp @@ -216,10 +216,11 @@ CompUnitSP SymbolFileBreakpad::ParseCompileUnitAtIndex(uint32_t index) { spec = (*m_files)[record->FileNum]; } - auto cu_sp = std::make_shared(m_objfile_sp->GetModule(), - /*user_data*/ nullptr, spec, index, - eLanguageTypeUnknown, - /*is_optimized*/ eLazyBoolNo); + auto cu_sp = std::make_shared( + m_objfile_sp->GetModule(), + /*user_data*/ nullptr, std::make_shared(spec), index, + eLanguageTypeUnknown, + /*is_optimized*/ eLazyBoolNo); SetCompileUnitAtIndex(index, cu_sp); return cu_sp; diff --git a/lldb/source/Plugins/SymbolFile/CTF/SymbolFileCTF.cpp b/lldb/source/Plugins/SymbolFile/CTF/SymbolFileCTF.cpp index d192944bb9d..65f5b1a5f1b 100644 --- a/lldb/source/Plugins/SymbolFile/CTF/SymbolFileCTF.cpp +++ b/lldb/source/Plugins/SymbolFile/CTF/SymbolFileCTF.cpp @@ -603,6 +603,7 @@ llvm::Expected SymbolFileCTF::CreateType(CTFType *ctf_type) { ctf_type->uid, ctf_type->name, ctf_type->kind), llvm::inconvertibleErrorCode()); } + llvm_unreachable("Unexpected CTF type kind"); } llvm::Expected> diff --git a/lldb/source/Plugins/SymbolFile/DWARF/DWARFDebugInfo.cpp b/lldb/source/Plugins/SymbolFile/DWARF/DWARFDebugInfo.cpp index 553b6a4c551..340b9acf80d 100644 --- a/lldb/source/Plugins/SymbolFile/DWARF/DWARFDebugInfo.cpp +++ b/lldb/source/Plugins/SymbolFile/DWARF/DWARFDebugInfo.cpp @@ -191,3 +191,9 @@ DWARFDebugInfo::GetDIE(const DIERef &die_ref) { return cu->GetNonSkeletonUnit().GetDIE(die_ref.die_offset()); return DWARFDIE(); // Not found } + +llvm::StringRef DWARFDebugInfo::PeekDIEName(const DIERef &die_ref) { + if (DWARFUnit *cu = GetUnit(die_ref)) + return cu->GetNonSkeletonUnit().PeekDIEName(die_ref.die_offset()); + return llvm::StringRef(); +} diff --git a/lldb/source/Plugins/SymbolFile/DWARF/DWARFDebugInfo.h b/lldb/source/Plugins/SymbolFile/DWARF/DWARFDebugInfo.h index d5e48f312ea..a8b5abc3bee 100644 --- a/lldb/source/Plugins/SymbolFile/DWARF/DWARFDebugInfo.h +++ b/lldb/source/Plugins/SymbolFile/DWARF/DWARFDebugInfo.h @@ -43,6 +43,11 @@ public: bool ContainsTypeUnits(); DWARFDIE GetDIE(const DIERef &die_ref); + /// Returns the AT_Name of this DIE, if it exists, without parsing the entire + /// compile unit. An empty is string is returned upon error or if the + /// attribute is not present. + llvm::StringRef PeekDIEName(const DIERef &die_ref); + enum { eDumpFlag_Verbose = (1 << 0), // Verbose dumping eDumpFlag_ShowForm = (1 << 1), // Show the DW_form type diff --git a/lldb/source/Plugins/SymbolFile/DWARF/DWARFFormValue.cpp b/lldb/source/Plugins/SymbolFile/DWARF/DWARFFormValue.cpp index 0a7029a55c0..e1f73f1997e 100644 --- a/lldb/source/Plugins/SymbolFile/DWARF/DWARFFormValue.cpp +++ b/lldb/source/Plugins/SymbolFile/DWARF/DWARFFormValue.cpp @@ -18,8 +18,6 @@ #include "DWARFFormValue.h" #include "DWARFUnit.h" -class DWARFUnit; - using namespace lldb_private; using namespace lldb_private::dwarf; using namespace lldb_private::plugin::dwarf; @@ -502,7 +500,8 @@ dw_addr_t DWARFFormValue::Address() const { &offset, index_size); } -DWARFDIE DWARFFormValue::Reference() const { +std::pair +DWARFFormValue::ReferencedUnitAndOffset() const { uint64_t value = m_value.value.uval; switch (m_form) { case DW_FORM_ref1: @@ -516,9 +515,9 @@ DWARFDIE DWARFFormValue::Reference() const { if (!m_unit->ContainsDIEOffset(value)) { m_unit->GetSymbolFileDWARF().GetObjectFile()->GetModule()->ReportError( "DW_FORM_ref* DIE reference {0:x16} is outside of its CU", value); - return {}; + return {nullptr, 0}; } - return const_cast(m_unit)->GetDIE(value); + return {const_cast(m_unit), value}; case DW_FORM_ref_addr: { DWARFUnit *ref_cu = @@ -527,24 +526,29 @@ DWARFDIE DWARFFormValue::Reference() const { if (!ref_cu) { m_unit->GetSymbolFileDWARF().GetObjectFile()->GetModule()->ReportError( "DW_FORM_ref_addr DIE reference {0:x16} has no matching CU", value); - return {}; + return {nullptr, 0}; } - return ref_cu->GetDIE(value); + return {ref_cu, value}; } case DW_FORM_ref_sig8: { DWARFTypeUnit *tu = m_unit->GetSymbolFileDWARF().DebugInfo().GetTypeUnitForHash(value); if (!tu) - return {}; - return tu->GetDIE(tu->GetTypeOffset()); + return {nullptr, 0}; + return {tu, tu->GetTypeOffset()}; } default: - return {}; + return {nullptr, 0}; } } +DWARFDIE DWARFFormValue::Reference() const { + auto [unit, offset] = ReferencedUnitAndOffset(); + return unit ? unit->GetDIE(offset) : DWARFDIE(); +} + uint64_t DWARFFormValue::Reference(dw_offset_t base_offset) const { uint64_t value = m_value.value.uval; switch (m_form) { diff --git a/lldb/source/Plugins/SymbolFile/DWARF/DWARFFormValue.h b/lldb/source/Plugins/SymbolFile/DWARF/DWARFFormValue.h index 445749a6aac..fdd5b3c278a 100644 --- a/lldb/source/Plugins/SymbolFile/DWARF/DWARFFormValue.h +++ b/lldb/source/Plugins/SymbolFile/DWARF/DWARFFormValue.h @@ -60,6 +60,12 @@ public: const DWARFUnit *u); std::optional GetFixedSize() const; DWARFDIE Reference() const; + + /// If this is a reference to another DIE, return the corresponding DWARFUnit + /// and DIE offset such that Unit->GetDIE(offset) produces the desired DIE. + /// Otherwise, a nullptr and unspecified offset are returned. + std::pair ReferencedUnitAndOffset() const; + uint64_t Reference(dw_offset_t offset) const; bool Boolean() const { return m_value.value.uval != 0; } uint64_t Unsigned() const { return m_value.value.uval; } diff --git a/lldb/source/Plugins/SymbolFile/DWARF/DWARFUnit.cpp b/lldb/source/Plugins/SymbolFile/DWARF/DWARFUnit.cpp index 0e2f4d45543..7a40361cded 100644 --- a/lldb/source/Plugins/SymbolFile/DWARF/DWARFUnit.cpp +++ b/lldb/source/Plugins/SymbolFile/DWARF/DWARFUnit.cpp @@ -663,6 +663,30 @@ DWARFUnit::GetDIE(dw_offset_t die_offset) { return DWARFDIE(); // Not found } +llvm::StringRef DWARFUnit::PeekDIEName(dw_offset_t die_offset) { + DWARFDebugInfoEntry die; + if (!die.Extract(GetData(), this, &die_offset)) + return llvm::StringRef(); + + // Does die contain a DW_AT_Name? + if (const char *name = + die.GetAttributeValueAsString(this, DW_AT_name, nullptr)) + return name; + + // Does its DW_AT_specification or DW_AT_abstract_origin contain an AT_Name? + for (auto attr : {DW_AT_specification, DW_AT_abstract_origin}) { + DWARFFormValue form_value; + if (!die.GetAttributeValue(this, attr, form_value)) + continue; + auto [unit, offset] = form_value.ReferencedUnitAndOffset(); + if (unit) + if (auto name = unit->PeekDIEName(offset); !name.empty()) + return name; + } + + return llvm::StringRef(); +} + DWARFUnit &DWARFUnit::GetNonSkeletonUnit() { ExtractUnitDIEIfNeeded(); if (m_dwo) diff --git a/lldb/source/Plugins/SymbolFile/DWARF/DWARFUnit.h b/lldb/source/Plugins/SymbolFile/DWARF/DWARFUnit.h index 3f528e913d8..bc225a52e1d 100644 --- a/lldb/source/Plugins/SymbolFile/DWARF/DWARFUnit.h +++ b/lldb/source/Plugins/SymbolFile/DWARF/DWARFUnit.h @@ -187,6 +187,11 @@ public: DWARFDIE GetDIE(dw_offset_t die_offset); + /// Returns the AT_Name of the DIE at `die_offset`, if it exists, without + /// parsing the entire compile unit. An empty is string is returned upon + /// error or if the attribute is not present. + llvm::StringRef PeekDIEName(dw_offset_t die_offset); + DWARFUnit &GetNonSkeletonUnit(); static uint8_t GetAddressByteSize(const DWARFUnit *cu); diff --git a/lldb/source/Plugins/SymbolFile/DWARF/ManualDWARFIndex.cpp b/lldb/source/Plugins/SymbolFile/DWARF/ManualDWARFIndex.cpp index 16ff5f7d484..92275600f99 100644 --- a/lldb/source/Plugins/SymbolFile/DWARF/ManualDWARFIndex.cpp +++ b/lldb/source/Plugins/SymbolFile/DWARF/ManualDWARFIndex.cpp @@ -75,9 +75,8 @@ void ManualDWARFIndex::Index() { // Include 2 passes per unit to index for extracting DIEs from the unit and // indexing the unit, and then 8 extra entries for finalizing each index set. const uint64_t total_progress = units_to_index.size() * 2 + 8; - Progress progress( - llvm::formatv("Manually indexing DWARF for {0}", module_desc.GetData()), - total_progress); + Progress progress("Manually indexing DWARF", module_desc.GetData(), + total_progress); std::vector sets(units_to_index.size()); diff --git a/lldb/source/Plugins/SymbolFile/DWARF/SymbolFileDWARF.cpp b/lldb/source/Plugins/SymbolFile/DWARF/SymbolFileDWARF.cpp index 1a16b70f42f..fed97858c83 100644 --- a/lldb/source/Plugins/SymbolFile/DWARF/SymbolFileDWARF.cpp +++ b/lldb/source/Plugins/SymbolFile/DWARF/SymbolFileDWARF.cpp @@ -294,7 +294,7 @@ static void ParseSupportFilesFromPrologue( } // Unconditionally add an entry, so the indices match up. - support_files.EmplaceBack(remapped_file, style, checksum); + support_files.EmplaceBack(FileSpec(remapped_file, style), checksum); } } @@ -519,8 +519,6 @@ void SymbolFileDWARF::InitializeObject() { if (apple_names.GetByteSize() > 0 || apple_namespaces.GetByteSize() > 0 || apple_types.GetByteSize() > 0 || apple_objc.GetByteSize() > 0) { - Progress progress(llvm::formatv("Loading Apple DWARF index for {0}", - module_desc.GetData())); m_index = AppleDWARFIndex::Create( *GetObjectFile()->GetModule(), apple_names, apple_namespaces, apple_types, apple_objc, m_context.getOrLoadStrData()); @@ -532,8 +530,7 @@ void SymbolFileDWARF::InitializeObject() { DWARFDataExtractor debug_names; LoadSectionData(eSectionTypeDWARFDebugNames, debug_names); if (debug_names.GetByteSize() > 0) { - Progress progress( - llvm::formatv("Loading DWARF5 index for {0}", module_desc.GetData())); + Progress progress("Loading DWARF5 index", module_desc.GetData()); llvm::Expected> index_or = DebugNamesDWARFIndex::Create(*GetObjectFile()->GetModule(), debug_names, @@ -786,12 +783,12 @@ lldb::CompUnitSP SymbolFileDWARF::ParseCompileUnit(DWARFCompileUnit &dwarf_cu) { } else { ModuleSP module_sp(m_objfile_sp->GetModule()); if (module_sp) { - auto initialize_cu = [&](const FileSpec &file_spec, + auto initialize_cu = [&](lldb::SupportFileSP support_file_sp, LanguageType cu_language, SupportFileList &&support_files = {}) { BuildCuTranslationTable(); cu_sp = std::make_shared( - module_sp, &dwarf_cu, file_spec, + module_sp, &dwarf_cu, support_file_sp, *GetDWARFUnitIndex(dwarf_cu.GetID()), cu_language, eLazyBoolCalculate, std::move(support_files)); @@ -824,7 +821,7 @@ lldb::CompUnitSP SymbolFileDWARF::ParseCompileUnit(DWARFCompileUnit &dwarf_cu) { return false; if (support_files.GetSize() == 0) return false; - initialize_cu(support_files.GetFileSpecAtIndex(0), + initialize_cu(support_files.GetSupportFileAtIndex(0), eLanguageTypeUnknown, std::move(support_files)); return true; }; @@ -843,7 +840,8 @@ lldb::CompUnitSP SymbolFileDWARF::ParseCompileUnit(DWARFCompileUnit &dwarf_cu) { // case ParseSupportFiles takes care of the remapping. MakeAbsoluteAndRemap(cu_file_spec, dwarf_cu, module_sp); - initialize_cu(cu_file_spec, cu_language); + initialize_cu(std::make_shared(cu_file_spec), + cu_language); } } } diff --git a/lldb/source/Plugins/SymbolFile/DWARF/SymbolFileDWARFDebugMap.cpp b/lldb/source/Plugins/SymbolFile/DWARF/SymbolFileDWARFDebugMap.cpp index 9094a5e21e6..6dd3eb3677b 100644 --- a/lldb/source/Plugins/SymbolFile/DWARF/SymbolFileDWARFDebugMap.cpp +++ b/lldb/source/Plugins/SymbolFile/DWARF/SymbolFileDWARFDebugMap.cpp @@ -598,10 +598,10 @@ CompUnitSP SymbolFileDWARFDebugMap::ParseCompileUnitAtIndex(uint32_t cu_idx) { // User zero as the ID to match the compile unit at offset zero in each // .o file. lldb::user_id_t cu_id = 0; - cu_info.compile_units_sps.push_back( - std::make_shared( - m_objfile_sp->GetModule(), nullptr, so_file_spec, cu_id, - eLanguageTypeUnknown, eLazyBoolCalculate)); + cu_info.compile_units_sps.push_back(std::make_shared( + m_objfile_sp->GetModule(), nullptr, + std::make_shared(so_file_spec), cu_id, + eLanguageTypeUnknown, eLazyBoolCalculate)); cu_info.id_to_index_map.insert({0, 0}); SetCompileUnitAtIndex(cu_idx, cu_info.compile_units_sps[0]); // If there's a symbol file also register all the extra compile units. @@ -615,7 +615,8 @@ CompUnitSP SymbolFileDWARFDebugMap::ParseCompileUnitAtIndex(uint32_t cu_idx) { if (dwarf_cu->GetID() == 0) continue; cu_info.compile_units_sps.push_back(std::make_shared( - m_objfile_sp->GetModule(), nullptr, so_file_spec, + m_objfile_sp->GetModule(), nullptr, + std::make_shared(so_file_spec), dwarf_cu->GetID(), eLanguageTypeUnknown, eLazyBoolCalculate)); cu_info.id_to_index_map.insert( {dwarf_cu->GetID(), cu_info.compile_units_sps.size() - 1}); diff --git a/lldb/source/Plugins/SymbolFile/NativePDB/SymbolFileNativePDB.cpp b/lldb/source/Plugins/SymbolFile/NativePDB/SymbolFileNativePDB.cpp index 9234768323e..745685a1b31 100644 --- a/lldb/source/Plugins/SymbolFile/NativePDB/SymbolFileNativePDB.cpp +++ b/lldb/source/Plugins/SymbolFile/NativePDB/SymbolFileNativePDB.cpp @@ -534,9 +534,9 @@ SymbolFileNativePDB::CreateCompileUnit(const CompilandIndexItem &cci) { FileSpec fs(llvm::sys::path::convert_to_slash( source_file_name, llvm::sys::path::Style::windows_backslash)); - CompUnitSP cu_sp = - std::make_shared(m_objfile_sp->GetModule(), nullptr, fs, - toOpaqueUid(cci.m_id), lang, optimized); + CompUnitSP cu_sp = std::make_shared( + m_objfile_sp->GetModule(), nullptr, std::make_shared(fs), + toOpaqueUid(cci.m_id), lang, optimized); SetCompileUnitAtIndex(cci.m_id.modi, cu_sp); return cu_sp; diff --git a/lldb/source/Plugins/SymbolLocator/Debuginfod/SymbolLocatorDebuginfod.cpp b/lldb/source/Plugins/SymbolLocator/Debuginfod/SymbolLocatorDebuginfod.cpp index 111be6be365..2cd7bbbb244 100644 --- a/lldb/source/Plugins/SymbolLocator/Debuginfod/SymbolLocatorDebuginfod.cpp +++ b/lldb/source/Plugins/SymbolLocator/Debuginfod/SymbolLocatorDebuginfod.cpp @@ -9,7 +9,10 @@ #include "SymbolLocatorDebuginfod.h" #include "lldb/Core/PluginManager.h" +#include "lldb/Interpreter/OptionValueString.h" #include "lldb/Utility/Args.h" +#include "lldb/Utility/LLDBLog.h" +#include "lldb/Utility/Log.h" #include "llvm/Debuginfod/Debuginfod.h" #include "llvm/Debuginfod/HTTPClient.h" @@ -54,6 +57,32 @@ public: return urls; } + llvm::Expected GetCachePath() { + OptionValueString *s = + m_collection_sp->GetPropertyAtIndexAsOptionValueString( + ePropertySymbolCachePath); + // If we don't have a valid cache location, use the default one. + if (!s || !s->GetCurrentValueAsRef().size()) { + llvm::Expected maybeCachePath = + llvm::getDefaultDebuginfodCacheDirectory(); + if (!maybeCachePath) + return maybeCachePath; + return *maybeCachePath; + } + return s->GetCurrentValue(); + } + + std::chrono::milliseconds GetTimeout() const { + std::optional seconds = + m_collection_sp->GetPropertyAtIndexAs(ePropertyTimeout); + if (seconds && *seconds != 0) { + return std::chrono::duration_cast( + std::chrono::seconds(*seconds)); + } else { + return llvm::getDefaultDebuginfodTimeout(); + } + } + private: void ServerURLsChangedCallback() { m_server_urls = GetDebugInfoDURLs(); @@ -112,31 +141,51 @@ SymbolLocator *SymbolLocatorDebuginfod::CreateInstance() { return new SymbolLocatorDebuginfod(); } -static std::optional GetFileForModule( - const ModuleSpec &module_spec, - std::function(llvm::object::BuildIDRef)> - PullFromServer) { - if (!ModuleList::GetGlobalModuleListProperties().GetEnableExternalLookup()) - return {}; +static std::optional +GetFileForModule(const ModuleSpec &module_spec, + std::function UrlBuilder) { const UUID &module_uuid = module_spec.GetUUID(); - if (module_uuid.IsValid() && llvm::canUseDebuginfod()) { - llvm::object::BuildID build_id(module_uuid.GetBytes()); - llvm::Expected result = PullFromServer(build_id); - if (result) - return FileSpec(*result); - // An error here should be logged as a failure in the Debuginfod library, - // so just consume it here - consumeError(result.takeError()); - } + // Don't bother if we don't have a valid UUID, Debuginfod isn't available, + // or if the 'symbols.enable-external-lookup' setting is false. + if (!module_uuid.IsValid() || !llvm::canUseDebuginfod() || + !ModuleList::GetGlobalModuleListProperties().GetEnableExternalLookup()) + return {}; + + // Grab LLDB's Debuginfod overrides from the + // plugin.symbol-locator.debuginfod.* settings. + PluginProperties &plugin_props = GetGlobalPluginProperties(); + llvm::Expected cache_path_or_err = plugin_props.GetCachePath(); + // A cache location is *required*. + if (!cache_path_or_err) + return {}; + std::string cache_path = *cache_path_or_err; + llvm::SmallVector debuginfod_urls = + llvm::getDefaultDebuginfodUrls(); + std::chrono::milliseconds timeout = plugin_props.GetTimeout(); + + // We're ready to ask the Debuginfod library to find our file. + llvm::object::BuildID build_id(module_uuid.GetBytes()); + std::string url_path = UrlBuilder(build_id); + std::string cache_key = llvm::getDebuginfodCacheKey(url_path); + llvm::Expected result = llvm::getCachedOrDownloadArtifact( + cache_key, url_path, cache_path, debuginfod_urls, timeout); + if (result) + return FileSpec(*result); + + Log *log = GetLog(LLDBLog::Symbols); + auto err_message = llvm::toString(result.takeError()); + LLDB_LOGV(log, + "Debuginfod failed to download symbol artifact {0} with error {1}", + url_path, err_message); return {}; } std::optional SymbolLocatorDebuginfod::LocateExecutableObjectFile( const ModuleSpec &module_spec) { - return GetFileForModule(module_spec, llvm::getCachedOrDownloadExecutable); + return GetFileForModule(module_spec, llvm::getDebuginfodExecutableUrlPath); } std::optional SymbolLocatorDebuginfod::LocateExecutableSymbolFile( const ModuleSpec &module_spec, const FileSpecList &default_search_paths) { - return GetFileForModule(module_spec, llvm::getCachedOrDownloadDebuginfo); + return GetFileForModule(module_spec, llvm::getDebuginfodDebuginfoUrlPath); } diff --git a/lldb/source/Plugins/SymbolLocator/Debuginfod/SymbolLocatorDebuginfodProperties.td b/lldb/source/Plugins/SymbolLocator/Debuginfod/SymbolLocatorDebuginfodProperties.td index 1c668b001a1..0ff02674b8e 100644 --- a/lldb/source/Plugins/SymbolLocator/Debuginfod/SymbolLocatorDebuginfodProperties.td +++ b/lldb/source/Plugins/SymbolLocator/Debuginfod/SymbolLocatorDebuginfodProperties.td @@ -1,7 +1,13 @@ include "../../../../include/lldb/Core/PropertiesBase.td" let Definition = "symbollocatordebuginfod" in { - def ServerURLs : Property<"server_urls", "Array">, + def ServerURLs : Property<"server-urls", "Array">, ElementType<"String">, Desc<"An ordered list of Debuginfod server URLs to query for symbols. This defaults to the contents of the DEBUGINFOD_URLS environment variable.">; + def SymbolCachePath: Property<"cache-path", "String">, + DefaultStringValue<"">, + Desc<"The path where symbol files should be cached. This defaults to LLDB's system cache location.">; + def Timeout : Property<"timeout", "UInt64">, + DefaultUnsignedValue<0>, + Desc<"Timeout (in seconds) for requests made to a DEBUGINFOD server. A value of zero means we use the debuginfod default timeout: DEBUGINFOD_TIMEOUT if the environment variable is set and 90 seconds otherwise.">; } diff --git a/lldb/source/Plugins/SymbolLocator/Default/SymbolLocatorDefault.cpp b/lldb/source/Plugins/SymbolLocator/Default/SymbolLocatorDefault.cpp index ed014f99fdb..6f0126b16cd 100644 --- a/lldb/source/Plugins/SymbolLocator/Default/SymbolLocatorDefault.cpp +++ b/lldb/source/Plugins/SymbolLocator/Default/SymbolLocatorDefault.cpp @@ -98,9 +98,9 @@ std::optional SymbolLocatorDefault::LocateExecutableSymbolFile( FileSystem::Instance().Exists(symbol_file_spec)) return symbol_file_spec; - Progress progress(llvm::formatv( - "Locating external symbol file for {0}", - module_spec.GetFileSpec().GetFilename().AsCString(""))); + Progress progress( + "Locating external symbol file", + module_spec.GetFileSpec().GetFilename().AsCString("")); FileSpecList debug_file_search_paths = default_search_paths; diff --git a/lldb/source/Plugins/TypeSystem/Clang/TypeSystemClang.cpp b/lldb/source/Plugins/TypeSystem/Clang/TypeSystemClang.cpp index 797df8c098a..6f5ff105477 100644 --- a/lldb/source/Plugins/TypeSystem/Clang/TypeSystemClang.cpp +++ b/lldb/source/Plugins/TypeSystem/Clang/TypeSystemClang.cpp @@ -7168,6 +7168,9 @@ TypeSystemClang::GetTemplateArgumentKind(lldb::opaque_compiler_type_t type, case clang::TemplateArgument::Pack: return eTemplateArgumentKindPack; + + case clang::TemplateArgument::StructuralValue: + return eTemplateArgumentKindStructuralValue; } llvm_unreachable("Unhandled clang::TemplateArgument::ArgKind"); } @@ -8353,7 +8356,7 @@ clang::EnumConstantDecl *TypeSystemClang::AddEnumerationValueToEnumerationType( if (name && name[0]) enumerator_decl->setDeclName(&getASTContext().Idents.get(name)); enumerator_decl->setType(clang::QualType(enutype, 0)); - enumerator_decl->setInitVal(value); + enumerator_decl->setInitVal(getASTContext(), value); SetMemberOwningModule(enumerator_decl, enutype->getDecl()); if (!enumerator_decl) diff --git a/lldb/source/Symbol/CompileUnit.cpp b/lldb/source/Symbol/CompileUnit.cpp index a6b6c8e57ee..1b3cd23d940 100644 --- a/lldb/source/Symbol/CompileUnit.cpp +++ b/lldb/source/Symbol/CompileUnit.cpp @@ -22,16 +22,19 @@ CompileUnit::CompileUnit(const lldb::ModuleSP &module_sp, void *user_data, const char *pathname, const lldb::user_id_t cu_sym_id, lldb::LanguageType language, lldb_private::LazyBool is_optimized) - : CompileUnit(module_sp, user_data, FileSpec(pathname), cu_sym_id, language, - is_optimized) {} + : CompileUnit(module_sp, user_data, + std::make_shared(FileSpec(pathname)), cu_sym_id, + language, is_optimized) {} CompileUnit::CompileUnit(const lldb::ModuleSP &module_sp, void *user_data, - const FileSpec &fspec, const lldb::user_id_t cu_sym_id, + lldb::SupportFileSP support_file_sp, + const lldb::user_id_t cu_sym_id, lldb::LanguageType language, lldb_private::LazyBool is_optimized, SupportFileList &&support_files) : ModuleChild(module_sp), UserID(cu_sym_id), m_user_data(user_data), - m_language(language), m_flags(0), m_file_spec(fspec), + m_language(language), m_flags(0), + m_primary_support_file_sp(support_file_sp), m_support_files(std::move(support_files)), m_is_optimized(is_optimized) { if (language != eLanguageTypeUnknown) m_flags.Set(flagsParsedLanguage); diff --git a/lldb/source/Symbol/LineEntry.cpp b/lldb/source/Symbol/LineEntry.cpp index 1b2801cd036..389f8dcb65d 100644 --- a/lldb/source/Symbol/LineEntry.cpp +++ b/lldb/source/Symbol/LineEntry.cpp @@ -17,23 +17,10 @@ LineEntry::LineEntry() : range(), file(), is_start_of_statement(0), is_start_of_basic_block(0), is_prologue_end(0), is_epilogue_begin(0), is_terminal_entry(0) {} -LineEntry::LineEntry(const lldb::SectionSP §ion_sp, - lldb::addr_t section_offset, lldb::addr_t byte_size, - const FileSpec &_file, uint32_t _line, uint16_t _column, - bool _is_start_of_statement, bool _is_start_of_basic_block, - bool _is_prologue_end, bool _is_epilogue_begin, - bool _is_terminal_entry) - : range(section_sp, section_offset, byte_size), file(_file), - original_file(_file), line(_line), column(_column), - is_start_of_statement(_is_start_of_statement), - is_start_of_basic_block(_is_start_of_basic_block), - is_prologue_end(_is_prologue_end), is_epilogue_begin(_is_epilogue_begin), - is_terminal_entry(_is_terminal_entry) {} - void LineEntry::Clear() { range.Clear(); file.Clear(); - original_file.Clear(); + original_file_sp = std::make_shared(); line = LLDB_INVALID_LINE_NUMBER; column = 0; is_start_of_statement = 0; @@ -195,7 +182,7 @@ AddressRange LineEntry::GetSameLineContiguousAddressRange( // different file / line number. AddressRange complete_line_range = range; auto symbol_context_scope = lldb::eSymbolContextLineEntry; - Declaration start_call_site(original_file, line); + Declaration start_call_site(original_file_sp->GetSpecOnly(), line); if (include_inlined_functions) symbol_context_scope |= lldb::eSymbolContextBlock; @@ -209,7 +196,7 @@ AddressRange LineEntry::GetSameLineContiguousAddressRange( next_line_sc.line_entry.range.GetByteSize() == 0) break; - if (original_file == next_line_sc.line_entry.original_file && + if (*original_file_sp == *next_line_sc.line_entry.original_file_sp && (next_line_sc.line_entry.line == 0 || line == next_line_sc.line_entry.line)) { // Include any line 0 entries - they indicate that this is compiler- @@ -253,8 +240,8 @@ AddressRange LineEntry::GetSameLineContiguousAddressRange( void LineEntry::ApplyFileMappings(lldb::TargetSP target_sp) { if (target_sp) { // Apply any file remappings to our file. - if (auto new_file_spec = - target_sp->GetSourcePathMap().FindFile(original_file)) + if (auto new_file_spec = target_sp->GetSourcePathMap().FindFile( + original_file_sp->GetSpecOnly())) file = *new_file_spec; } } diff --git a/lldb/source/Symbol/LineTable.cpp b/lldb/source/Symbol/LineTable.cpp index abe4c98d592..444135f63bc 100644 --- a/lldb/source/Symbol/LineTable.cpp +++ b/lldb/source/Symbol/LineTable.cpp @@ -290,8 +290,8 @@ bool LineTable::ConvertEntryAtIndexToLineEntry(uint32_t idx, line_entry.file = m_comp_unit->GetSupportFiles().GetFileSpecAtIndex(entry.file_idx); - line_entry.original_file = - m_comp_unit->GetSupportFiles().GetFileSpecAtIndex(entry.file_idx); + line_entry.original_file_sp = + m_comp_unit->GetSupportFiles().GetSupportFileAtIndex(entry.file_idx); line_entry.line = entry.line; line_entry.column = entry.column; line_entry.is_start_of_statement = entry.is_start_of_statement; @@ -357,13 +357,13 @@ void LineTable::Dump(Stream *s, Target *target, Address::DumpStyle style, Address::DumpStyle fallback_style, bool show_line_ranges) { const size_t count = m_entries.size(); LineEntry line_entry; - FileSpec prev_file; + SupportFileSP prev_file; for (size_t idx = 0; idx < count; ++idx) { ConvertEntryAtIndexToLineEntry(idx, line_entry); - line_entry.Dump(s, target, prev_file != line_entry.original_file, style, - fallback_style, show_line_ranges); + line_entry.Dump(s, target, *prev_file != *line_entry.original_file_sp, + style, fallback_style, show_line_ranges); s->EOL(); - prev_file = line_entry.original_file; + prev_file = line_entry.original_file_sp; } } diff --git a/lldb/source/Symbol/Symbol.cpp b/lldb/source/Symbol/Symbol.cpp index 08900a3ef34..1895f299cc0 100644 --- a/lldb/source/Symbol/Symbol.cpp +++ b/lldb/source/Symbol/Symbol.cpp @@ -226,8 +226,9 @@ bool Symbol::IsTrampoline() const { return m_type == eSymbolTypeTrampoline; } bool Symbol::IsIndirect() const { return m_type == eSymbolTypeResolver; } -void Symbol::GetDescription(Stream *s, lldb::DescriptionLevel level, - Target *target, llvm::StringRef pattern) const { +void Symbol::GetDescription( + Stream *s, lldb::DescriptionLevel level, Target *target, + std::optional settings) const { s->Printf("id = {0x%8.8x}", m_uid); if (m_addr_range.GetBaseAddress().GetSection()) { @@ -254,22 +255,14 @@ void Symbol::GetDescription(Stream *s, lldb::DescriptionLevel level, s->Printf(", value = 0x%16.16" PRIx64, m_addr_range.GetBaseAddress().GetOffset()); } - llvm::StringRef ansi_prefix; - llvm::StringRef ansi_suffix; - if (target) { - ansi_prefix = target->GetDebugger().GetRegexMatchAnsiPrefix(); - ansi_suffix = target->GetDebugger().GetRegexMatchAnsiSuffix(); - } if (ConstString demangled = m_mangled.GetDemangledName()) { s->PutCString(", name=\""); - s->PutCStringColorHighlighted(demangled.GetStringRef(), pattern, - ansi_prefix, ansi_suffix); + s->PutCStringColorHighlighted(demangled.GetStringRef(), settings); s->PutCString("\""); } if (ConstString mangled_name = m_mangled.GetMangledName()) { s->PutCString(", mangled=\""); - s->PutCStringColorHighlighted(mangled_name.GetStringRef(), pattern, - ansi_prefix, ansi_suffix); + s->PutCStringColorHighlighted(mangled_name.GetStringRef(), settings); s->PutCString("\""); } } diff --git a/lldb/source/Symbol/SymbolContext.cpp b/lldb/source/Symbol/SymbolContext.cpp index 9fd40b5ca56..3c70b8d8743 100644 --- a/lldb/source/Symbol/SymbolContext.cpp +++ b/lldb/source/Symbol/SymbolContext.cpp @@ -24,6 +24,7 @@ #include "lldb/Target/Target.h" #include "lldb/Utility/LLDBLog.h" #include "lldb/Utility/Log.h" +#include "lldb/Utility/Stream.h" #include "lldb/Utility/StreamString.h" #include "lldb/lldb-enumerations.h" @@ -68,12 +69,11 @@ void SymbolContext::Clear(bool clear_target) { variable = nullptr; } -bool SymbolContext::DumpStopContext(Stream *s, ExecutionContextScope *exe_scope, - const Address &addr, bool show_fullpaths, - bool show_module, bool show_inlined_frames, - bool show_function_arguments, - bool show_function_name, - llvm::StringRef pattern) const { +bool SymbolContext::DumpStopContext( + Stream *s, ExecutionContextScope *exe_scope, const Address &addr, + bool show_fullpaths, bool show_module, bool show_inlined_frames, + bool show_function_arguments, bool show_function_name, + std::optional settings) const { bool dumped_something = false; if (show_module && module_sp) { if (show_fullpaths) @@ -95,16 +95,8 @@ bool SymbolContext::DumpStopContext(Stream *s, ExecutionContextScope *exe_scope, name = function->GetNameNoArguments(); if (!name) name = function->GetName(); - if (name) { - llvm::StringRef ansi_prefix; - llvm::StringRef ansi_suffix; - if (target_sp) { - ansi_prefix = target_sp->GetDebugger().GetRegexMatchAnsiPrefix(); - ansi_suffix = target_sp->GetDebugger().GetRegexMatchAnsiSuffix(); - } - s->PutCStringColorHighlighted(name.GetStringRef(), pattern, ansi_prefix, - ansi_suffix); - } + if (name) + s->PutCStringColorHighlighted(name.GetStringRef(), settings); } if (addr.IsValid()) { @@ -172,14 +164,7 @@ bool SymbolContext::DumpStopContext(Stream *s, ExecutionContextScope *exe_scope, dumped_something = true; if (symbol->GetType() == eSymbolTypeTrampoline) s->PutCString("symbol stub for: "); - llvm::StringRef ansi_prefix; - llvm::StringRef ansi_suffix; - if (target_sp) { - ansi_prefix = target_sp->GetDebugger().GetRegexMatchAnsiPrefix(); - ansi_suffix = target_sp->GetDebugger().GetRegexMatchAnsiSuffix(); - } - s->PutCStringColorHighlighted(symbol->GetName().GetStringRef(), pattern, - ansi_prefix, ansi_suffix); + s->PutCStringColorHighlighted(symbol->GetName().GetStringRef(), settings); } if (addr.IsValid() && symbol->ValueIsAddress()) { @@ -201,9 +186,9 @@ bool SymbolContext::DumpStopContext(Stream *s, ExecutionContextScope *exe_scope, return dumped_something; } -void SymbolContext::GetDescription(Stream *s, lldb::DescriptionLevel level, - Target *target, - llvm::StringRef pattern) const { +void SymbolContext::GetDescription( + Stream *s, lldb::DescriptionLevel level, Target *target, + std::optional settings) const { if (module_sp) { s->Indent(" Module: file = \""); module_sp->GetFileSpec().Dump(s->AsRawOstream()); @@ -263,7 +248,7 @@ void SymbolContext::GetDescription(Stream *s, lldb::DescriptionLevel level, if (symbol != nullptr) { s->Indent(" Symbol: "); - symbol->GetDescription(s, level, target, pattern); + symbol->GetDescription(s, level, target, settings); s->EOL(); } @@ -489,8 +474,9 @@ bool SymbolContext::GetParentOfInlinedScope(const Address &curr_frame_pc, next_frame_sc.line_entry.range.GetBaseAddress() = next_frame_pc; next_frame_sc.line_entry.file = curr_inlined_block_inlined_info->GetCallSite().GetFile(); - next_frame_sc.line_entry.original_file = - curr_inlined_block_inlined_info->GetCallSite().GetFile(); + next_frame_sc.line_entry.original_file_sp = + std::make_shared( + curr_inlined_block_inlined_info->GetCallSite().GetFile()); next_frame_sc.line_entry.line = curr_inlined_block_inlined_info->GetCallSite().GetLine(); next_frame_sc.line_entry.column = diff --git a/lldb/source/Target/Process.cpp b/lldb/source/Target/Process.cpp index aa3b04c43cc..e1c16ca2164 100644 --- a/lldb/source/Target/Process.cpp +++ b/lldb/source/Target/Process.cpp @@ -4304,9 +4304,9 @@ void Process::BroadcastAsyncProfileData(const std::string &one_profile_data) { void Process::BroadcastStructuredData(const StructuredData::ObjectSP &object_sp, const StructuredDataPluginSP &plugin_sp) { - BroadcastEvent( - eBroadcastBitStructuredData, - new EventDataStructuredData(shared_from_this(), object_sp, plugin_sp)); + auto data_sp = std::make_shared( + shared_from_this(), object_sp, plugin_sp); + BroadcastEvent(eBroadcastBitStructuredData, data_sp); } StructuredDataPluginSP @@ -5694,12 +5694,16 @@ lldb::addr_t Process::GetDataAddressMask() { lldb::addr_t Process::GetHighmemCodeAddressMask() { if (uint32_t num_bits_setting = GetHighmemVirtualAddressableBits()) return ~((1ULL << num_bits_setting) - 1); + if (m_highmem_code_address_mask) + return m_highmem_code_address_mask; return GetCodeAddressMask(); } lldb::addr_t Process::GetHighmemDataAddressMask() { if (uint32_t num_bits_setting = GetHighmemVirtualAddressableBits()) return ~((1ULL << num_bits_setting) - 1); + if (m_highmem_data_address_mask) + return m_highmem_data_address_mask; return GetDataAddressMask(); } diff --git a/lldb/source/Target/Target.cpp b/lldb/source/Target/Target.cpp index 302c2bad702..e969340fdf1 100644 --- a/lldb/source/Target/Target.cpp +++ b/lldb/source/Target/Target.cpp @@ -1704,8 +1704,9 @@ void Target::ModulesDidLoad(ModuleList &module_list) { if (m_process_sp) { m_process_sp->ModulesDidLoad(module_list); } - BroadcastEvent(eBroadcastBitModulesLoaded, - new TargetEventData(this->shared_from_this(), module_list)); + auto data_sp = + std::make_shared(shared_from_this(), module_list); + BroadcastEvent(eBroadcastBitModulesLoaded, data_sp); } } @@ -1719,16 +1720,18 @@ void Target::SymbolsDidLoad(ModuleList &module_list) { m_breakpoint_list.UpdateBreakpoints(module_list, true, false); m_internal_breakpoint_list.UpdateBreakpoints(module_list, true, false); - BroadcastEvent(eBroadcastBitSymbolsLoaded, - new TargetEventData(this->shared_from_this(), module_list)); + auto data_sp = + std::make_shared(shared_from_this(), module_list); + BroadcastEvent(eBroadcastBitSymbolsLoaded, data_sp); } } void Target::ModulesDidUnload(ModuleList &module_list, bool delete_locations) { if (m_valid && module_list.GetSize()) { UnloadModuleSections(module_list); - BroadcastEvent(eBroadcastBitModulesUnloaded, - new TargetEventData(this->shared_from_this(), module_list)); + auto data_sp = + std::make_shared(shared_from_this(), module_list); + BroadcastEvent(eBroadcastBitModulesUnloaded, data_sp); m_breakpoint_list.UpdateBreakpoints(module_list, false, delete_locations); m_internal_breakpoint_list.UpdateBreakpoints(module_list, false, delete_locations); diff --git a/lldb/source/Target/TargetProperties.td b/lldb/source/Target/TargetProperties.td index 154a6e5919a..d2fccdb7b9b 100644 --- a/lldb/source/Target/TargetProperties.td +++ b/lldb/source/Target/TargetProperties.td @@ -95,7 +95,7 @@ let Definition = "target" in { def MaxChildrenDepth: Property<"max-children-depth", "UInt64">, DefaultUnsignedValue<0xFFFFFFFF>, Desc<"Maximum depth to expand children.">; - def MaxSummaryLength: Property<"max-string-summary-length", "SInt64">, + def MaxSummaryLength: Property<"max-string-summary-length", "UInt64">, DefaultUnsignedValue<1024>, Desc<"Maximum number of characters to show when using %s in summary strings.">; def MaxMemReadSize: Property<"max-memory-read-size", "SInt64">, diff --git a/lldb/source/Target/Thread.cpp b/lldb/source/Target/Thread.cpp index 865cee97e6d..8ae2179c128 100644 --- a/lldb/source/Target/Thread.cpp +++ b/lldb/source/Target/Thread.cpp @@ -253,9 +253,11 @@ void Thread::DestroyThread() { } void Thread::BroadcastSelectedFrameChange(StackID &new_frame_id) { - if (EventTypeHasListeners(eBroadcastBitSelectedFrameChanged)) - BroadcastEvent(eBroadcastBitSelectedFrameChanged, - new ThreadEventData(this->shared_from_this(), new_frame_id)); + if (EventTypeHasListeners(eBroadcastBitSelectedFrameChanged)) { + auto data_sp = + std::make_shared(shared_from_this(), new_frame_id); + BroadcastEvent(eBroadcastBitSelectedFrameChanged, data_sp); + } } lldb::StackFrameSP @@ -1507,9 +1509,10 @@ Status Thread::ReturnFromFrame(lldb::StackFrameSP frame_sp, if (copy_success) { thread->DiscardThreadPlans(true); thread->ClearStackFrames(); - if (broadcast && EventTypeHasListeners(eBroadcastBitStackChanged)) - BroadcastEvent(eBroadcastBitStackChanged, - new ThreadEventData(this->shared_from_this())); + if (broadcast && EventTypeHasListeners(eBroadcastBitStackChanged)) { + auto data_sp = std::make_shared(shared_from_this()); + BroadcastEvent(eBroadcastBitStackChanged, data_sp); + } } else { return_error.SetErrorString("Could not reset register values."); } diff --git a/lldb/source/Target/ThreadList.cpp b/lldb/source/Target/ThreadList.cpp index 1ba0c435b99..03e8daedff1 100644 --- a/lldb/source/Target/ThreadList.cpp +++ b/lldb/source/Target/ThreadList.cpp @@ -726,10 +726,12 @@ bool ThreadList::SetSelectedThreadByIndexID(uint32_t index_id, bool notify) { void ThreadList::NotifySelectedThreadChanged(lldb::tid_t tid) { ThreadSP selected_thread_sp(FindThreadByID(tid)); if (selected_thread_sp->EventTypeHasListeners( - Thread::eBroadcastBitThreadSelected)) - selected_thread_sp->BroadcastEvent( - Thread::eBroadcastBitThreadSelected, - new Thread::ThreadEventData(selected_thread_sp)); + Thread::eBroadcastBitThreadSelected)) { + auto data_sp = + std::make_shared(selected_thread_sp); + selected_thread_sp->BroadcastEvent(Thread::eBroadcastBitThreadSelected, + data_sp); + } } void ThreadList::Update(ThreadList &rhs) { diff --git a/lldb/source/Target/ThreadPlanStepOverRange.cpp b/lldb/source/Target/ThreadPlanStepOverRange.cpp index b1cb070e0a3..84f282f1de5 100644 --- a/lldb/source/Target/ThreadPlanStepOverRange.cpp +++ b/lldb/source/Target/ThreadPlanStepOverRange.cpp @@ -220,8 +220,8 @@ bool ThreadPlanStepOverRange::ShouldStop(Event *event_ptr) { StackFrameSP frame_sp = thread.GetStackFrameAtIndex(0); sc = frame_sp->GetSymbolContext(eSymbolContextEverything); if (sc.line_entry.IsValid()) { - if (sc.line_entry.original_file != - m_addr_context.line_entry.original_file && + if (*sc.line_entry.original_file_sp != + *m_addr_context.line_entry.original_file_sp && sc.comp_unit == m_addr_context.comp_unit && sc.function == m_addr_context.function) { // Okay, find the next occurrence of this file in the line table: @@ -244,8 +244,8 @@ bool ThreadPlanStepOverRange::ShouldStop(Event *event_ptr) { LineEntry prev_line_entry; if (line_table->GetLineEntryAtIndex(entry_idx - 1, prev_line_entry) && - prev_line_entry.original_file == - line_entry.original_file) { + *prev_line_entry.original_file_sp == + *line_entry.original_file_sp) { SymbolContext prev_sc; Address prev_address = prev_line_entry.range.GetBaseAddress(); @@ -279,8 +279,8 @@ bool ThreadPlanStepOverRange::ShouldStop(Event *event_ptr) { if (next_line_function != m_addr_context.function) break; - if (next_line_entry.original_file == - m_addr_context.line_entry.original_file) { + if (*next_line_entry.original_file_sp == + *m_addr_context.line_entry.original_file_sp) { const bool abort_other_plans = false; const RunMode stop_other_threads = RunMode::eAllThreads; lldb::addr_t cur_pc = thread.GetStackFrameAtIndex(0) diff --git a/lldb/source/Target/ThreadPlanStepRange.cpp b/lldb/source/Target/ThreadPlanStepRange.cpp index bb92adcae78..998e76cb65d 100644 --- a/lldb/source/Target/ThreadPlanStepRange.cpp +++ b/lldb/source/Target/ThreadPlanStepRange.cpp @@ -120,8 +120,8 @@ bool ThreadPlanStepRange::InRange() { frame->GetSymbolContext(eSymbolContextEverything)); if (m_addr_context.line_entry.IsValid() && new_context.line_entry.IsValid()) { - if (m_addr_context.line_entry.original_file == - new_context.line_entry.original_file) { + if (*m_addr_context.line_entry.original_file_sp == + *new_context.line_entry.original_file_sp) { if (m_addr_context.line_entry.line == new_context.line_entry.line) { m_addr_context = new_context; const bool include_inlined_functions = diff --git a/lldb/source/Utility/Broadcaster.cpp b/lldb/source/Utility/Broadcaster.cpp index 914812d7857..33cd49963e7 100644 --- a/lldb/source/Utility/Broadcaster.cpp +++ b/lldb/source/Utility/Broadcaster.cpp @@ -300,9 +300,8 @@ void Broadcaster::BroadcasterImpl::PrivateBroadcastEvent(EventSP &event_sp, } } -void Broadcaster::BroadcasterImpl::BroadcastEvent(uint32_t event_type, - EventData *event_data) { - auto event_sp = std::make_shared(event_type, event_data); +void Broadcaster::BroadcasterImpl::BroadcastEvent(uint32_t event_type) { + auto event_sp = std::make_shared(event_type, /*data = */ nullptr); PrivateBroadcastEvent(event_sp, false); } diff --git a/lldb/source/Utility/FileSpec.cpp b/lldb/source/Utility/FileSpec.cpp index 5387be9a681..4bebbc9ff17 100644 --- a/lldb/source/Utility/FileSpec.cpp +++ b/lldb/source/Utility/FileSpec.cpp @@ -68,9 +68,8 @@ void Denormalize(llvm::SmallVectorImpl &path, FileSpec::Style style) { FileSpec::FileSpec() : m_style(GetNativeStyle()) {} // Default constructor that can take an optional full path to a file on disk. -FileSpec::FileSpec(llvm::StringRef path, Style style, const Checksum &checksum) - : m_checksum(checksum), m_style(style) { - SetFile(path, style, checksum); +FileSpec::FileSpec(llvm::StringRef path, Style style) : m_style(style) { + SetFile(path, style); } FileSpec::FileSpec(llvm::StringRef path, const llvm::Triple &triple) @@ -172,11 +171,9 @@ void FileSpec::SetFile(llvm::StringRef pathname) { SetFile(pathname, m_style); } // Update the contents of this object with a new path. The path will be split // up into a directory and filename and stored as uniqued string values for // quick comparison and efficient memory usage. -void FileSpec::SetFile(llvm::StringRef pathname, Style style, - const Checksum &checksum) { +void FileSpec::SetFile(llvm::StringRef pathname, Style style) { Clear(); m_style = (style == Style::native) ? GetNativeStyle() : style; - m_checksum = checksum; if (pathname.empty()) return; diff --git a/lldb/source/Utility/FileSpecList.cpp b/lldb/source/Utility/FileSpecList.cpp index 8d2cf81efe5..7647e04a820 100644 --- a/lldb/source/Utility/FileSpecList.cpp +++ b/lldb/source/Utility/FileSpecList.cpp @@ -41,7 +41,7 @@ bool FileSpecList::AppendIfUnique(const FileSpec &file_spec) { bool SupportFileList::AppendIfUnique(const FileSpec &file_spec) { collection::iterator end = m_files.end(); if (find_if(m_files.begin(), end, - [&](const std::unique_ptr &support_file) { + [&](const std::shared_ptr &support_file) { return support_file->GetSpecOnly() == file_spec; }) == end) { Append(file_spec); @@ -176,6 +176,13 @@ const FileSpec &SupportFileList::GetFileSpecAtIndex(size_t idx) const { return g_empty_file_spec; } +std::shared_ptr +SupportFileList::GetSupportFileAtIndex(size_t idx) const { + if (idx < m_files.size()) + return m_files[idx]; + return {}; +} + // Return the size in bytes that this object takes in memory. This returns the // size in bytes of this object's member variables and any FileSpec objects its // member variables contain, the result doesn't not include the string values diff --git a/lldb/source/Utility/Stream.cpp b/lldb/source/Utility/Stream.cpp index 62e061e9d09..89dce9fb0e1 100644 --- a/lldb/source/Utility/Stream.cpp +++ b/lldb/source/Utility/Stream.cpp @@ -72,23 +72,20 @@ size_t Stream::PutCString(llvm::StringRef str) { return bytes_written; } -void Stream::PutCStringColorHighlighted(llvm::StringRef text, - llvm::StringRef pattern, - llvm::StringRef prefix, - llvm::StringRef suffix) { - // Only apply color formatting when a pattern is present and both prefix and - // suffix are specified. In the absence of these conditions, output the text - // without color formatting. - if (pattern.empty() || (prefix.empty() && suffix.empty())) { +void Stream::PutCStringColorHighlighted( + llvm::StringRef text, std::optional pattern_info) { + // Only apply color formatting when a pattern information is specified. + // Otherwise, output the text without color formatting. + if (!pattern_info.has_value()) { PutCString(text); return; } - llvm::Regex reg_pattern(pattern); + llvm::Regex reg_pattern(pattern_info->pattern); llvm::SmallVector matches; llvm::StringRef remaining = text; std::string format_str = lldb_private::ansi::FormatAnsiTerminalCodes( - prefix.str() + "%.*s" + suffix.str()); + pattern_info->prefix.str() + "%.*s" + pattern_info->suffix.str()); while (reg_pattern.match(remaining, &matches)) { llvm::StringRef match = matches[0]; size_t match_start_pos = match.data() - remaining.data(); diff --git a/lldb/source/Utility/XcodeSDK.cpp b/lldb/source/Utility/XcodeSDK.cpp index d744336373b..712d611db28 100644 --- a/lldb/source/Utility/XcodeSDK.cpp +++ b/lldb/source/Utility/XcodeSDK.cpp @@ -34,6 +34,10 @@ static llvm::StringRef GetName(XcodeSDK::Type type) { return "WatchSimulator"; case XcodeSDK::watchOS: return "WatchOS"; + case XcodeSDK::XRSimulator: + return "XRSimulator"; + case XcodeSDK::XROS: + return "XROS"; case XcodeSDK::bridgeOS: return "bridgeOS"; case XcodeSDK::Linux: @@ -75,6 +79,10 @@ static XcodeSDK::Type ParseSDKName(llvm::StringRef &name) { return XcodeSDK::WatchSimulator; if (name.consume_front("WatchOS")) return XcodeSDK::watchOS; + if (name.consume_front("XRSimulator")) + return XcodeSDK::XRSimulator; + if (name.consume_front("XROS")) + return XcodeSDK::XROS; if (name.consume_front("bridgeOS")) return XcodeSDK::bridgeOS; if (name.consume_front("Linux")) @@ -183,6 +191,12 @@ std::string XcodeSDK::GetCanonicalName(XcodeSDK::Info info) { case watchOS: name = "watchos"; break; + case XRSimulator: + name = "xrsimulator"; + break; + case XROS: + name = "xros"; + break; case bridgeOS: name = "bridgeos"; break; @@ -212,6 +226,9 @@ bool XcodeSDK::SDKSupportsModules(XcodeSDK::Type sdk_type, case Type::watchOS: case Type::WatchSimulator: return version >= llvm::VersionTuple(6); + case Type::XROS: + case Type::XRSimulator: + return true; default: return false; } @@ -233,6 +250,8 @@ bool XcodeSDK::SupportsSwift() const { case Type::WatchSimulator: case Type::watchOS: return info.version.empty() || info.version >= llvm::VersionTuple(2); + case Type::XROS: + case Type::XRSimulator: case Type::Linux: return true; default: @@ -276,6 +295,10 @@ XcodeSDK::Type XcodeSDK::GetSDKTypeForTriple(const llvm::Triple &triple) { if (triple.getEnvironment() == Triple::Simulator) return XcodeSDK::WatchSimulator; return XcodeSDK::watchOS; + case Triple::XROS: + if (triple.getEnvironment() == Triple::Simulator) + return XcodeSDK::XRSimulator; + return XcodeSDK::XROS; case Triple::Linux: return XcodeSDK::Linux; default: diff --git a/lldb/tools/driver/Driver.cpp b/lldb/tools/driver/Driver.cpp index f8058f868d5..c63ff0ff597 100644 --- a/lldb/tools/driver/Driver.cpp +++ b/lldb/tools/driver/Driver.cpp @@ -18,6 +18,7 @@ #include "lldb/API/SBStream.h" #include "lldb/API/SBStringList.h" #include "lldb/API/SBStructuredData.h" +#include "lldb/Host/Config.h" #include "llvm/ADT/StringRef.h" #include "llvm/Support/Format.h" @@ -746,6 +747,8 @@ int main(int argc, char const *argv[]) { // Setup LLVM signal handlers and make sure we call llvm_shutdown() on // destruction. llvm::InitLLVM IL(argc, argv, /*InstallPipeSignalExitHandler=*/false); + llvm::setBugReportMsg("PLEASE submit a bug report to " LLDB_BUG_REPORT_URL + " and include the crash backtrace.\n"); // Parse arguments. LLDBOptTable T; diff --git a/lldb/tools/lldb-server/lldb-server.cpp b/lldb/tools/lldb-server/lldb-server.cpp index 1808ffc0c97..e2e6bfcd864 100644 --- a/lldb/tools/lldb-server/lldb-server.cpp +++ b/lldb/tools/lldb-server/lldb-server.cpp @@ -7,6 +7,7 @@ //===----------------------------------------------------------------------===// #include "SystemInitializerLLGS.h" +#include "lldb/Host/Config.h" #include "lldb/Initialization/SystemLifetimeManager.h" #include "lldb/Version/Version.h" @@ -50,7 +51,8 @@ static void terminate_debugger() { g_debugger_lifetime->Terminate(); } // main int main(int argc, char *argv[]) { llvm::InitLLVM IL(argc, argv, /*InstallPipeSignalExitHandler=*/false); - llvm::PrettyStackTraceProgram X(argc, argv); + llvm::setBugReportMsg("PLEASE submit a bug report to " LLDB_BUG_REPORT_URL + " and include the crash backtrace.\n"); int option_error = 0; const char *progname = argv[0]; diff --git a/llvm/include/llvm/ADT/APFixedPoint.h b/llvm/include/llvm/ADT/APFixedPoint.h index 5442968d20e..b0c510865f4 100644 --- a/llvm/include/llvm/ADT/APFixedPoint.h +++ b/llvm/include/llvm/ADT/APFixedPoint.h @@ -235,7 +235,7 @@ public: std::string toString() const { SmallString<40> S; toString(S); - return std::string(S.str()); + return std::string(S); } void print(raw_ostream &) const; diff --git a/llvm/include/llvm/ADT/FunctionExtras.h b/llvm/include/llvm/ADT/FunctionExtras.h index 4cf1de488c7..c0bc30c7450 100644 --- a/llvm/include/llvm/ADT/FunctionExtras.h +++ b/llvm/include/llvm/ADT/FunctionExtras.h @@ -35,6 +35,7 @@ #include "llvm/ADT/PointerIntPair.h" #include "llvm/ADT/PointerUnion.h" #include "llvm/ADT/STLForwardCompat.h" +#include "llvm/Support/Compiler.h" #include "llvm/Support/MemAlloc.h" #include "llvm/Support/type_traits.h" #include @@ -317,8 +318,10 @@ protected: // Clear the old callback and inline flag to get back to as-if-null. RHS.CallbackAndInlineFlag = {}; -#ifndef NDEBUG - // In debug builds, we also scribble across the rest of the storage. +#if !defined(NDEBUG) && !LLVM_ADDRESS_SANITIZER_BUILD + // In debug builds without ASan, we also scribble across the rest of the + // storage. Scribbling under AddressSanitizer (ASan) is disabled to prevent + // overwriting poisoned objects (e.g., annotated short strings). memset(RHS.getInlineStorage(), 0xAD, InlineStorageSize); #endif } diff --git a/llvm/include/llvm/ADT/Hashing.h b/llvm/include/llvm/ADT/Hashing.h index 4e82ba9a6fb..a5477362a50 100644 --- a/llvm/include/llvm/ADT/Hashing.h +++ b/llvm/include/llvm/ADT/Hashing.h @@ -677,7 +677,9 @@ template hash_code hash_value(const std::optional &arg) { template <> struct DenseMapInfo { static inline hash_code getEmptyKey() { return hash_code(-1); } static inline hash_code getTombstoneKey() { return hash_code(-2); } - static unsigned getHashValue(hash_code val) { return val; } + static unsigned getHashValue(hash_code val) { + return static_cast(size_t(val)); + } static bool isEqual(hash_code LHS, hash_code RHS) { return LHS == RHS; } }; diff --git a/llvm/include/llvm/ADT/SetVector.h b/llvm/include/llvm/ADT/SetVector.h index ff083556cf1..69931e02953 100644 --- a/llvm/include/llvm/ADT/SetVector.h +++ b/llvm/include/llvm/ADT/SetVector.h @@ -162,7 +162,7 @@ public: bool insert(const value_type &X) { if constexpr (canBeSmall()) if (isSmall()) { - if (llvm::find(vector_, X) == vector_.end()) { + if (!llvm::is_contained(vector_, X)) { vector_.push_back(X); if (vector_.size() > N) makeBig(); diff --git a/llvm/include/llvm/ADT/SmallVector.h b/llvm/include/llvm/ADT/SmallVector.h index 2e6d2dc6ce9..09676d792df 100644 --- a/llvm/include/llvm/ADT/SmallVector.h +++ b/llvm/include/llvm/ADT/SmallVector.h @@ -61,7 +61,7 @@ protected: SmallVectorBase() = delete; SmallVectorBase(void *FirstEl, size_t TotalCapacity) - : BeginX(FirstEl), Capacity(TotalCapacity) {} + : BeginX(FirstEl), Capacity(static_cast(TotalCapacity)) {} /// This is a helper for \a grow() that's out of line to reduce code /// duplication. This function will report a fatal error if it can't grow at @@ -99,8 +99,18 @@ protected: /// /// This does not construct or destroy any elements in the vector. void set_size(size_t N) { - assert(N <= capacity()); - Size = N; + assert(N <= capacity()); // implies no overflow in assignment + Size = static_cast(N); + } + + /// Set the array data pointer to \p Begin and capacity to \p N. + /// + /// This does not construct or destroy any elements in the vector. + // This does not clean up any existing allocation. + void set_allocation_range(void *Begin, size_t N) { + assert(N <= SizeTypeMax()); + BeginX = Begin; + Capacity = static_cast(N); } }; @@ -467,8 +477,7 @@ void SmallVectorTemplateBase::takeAllocationForGrow( if (!this->isSmall()) free(this->begin()); - this->BeginX = NewElts; - this->Capacity = NewCapacity; + this->set_allocation_range(NewElts, NewCapacity); } /// SmallVectorTemplateBase - This is where we put diff --git a/llvm/include/llvm/ADT/StringExtras.h b/llvm/include/llvm/ADT/StringExtras.h index c6fb8b65280..a24368924bc 100644 --- a/llvm/include/llvm/ADT/StringExtras.h +++ b/llvm/include/llvm/ADT/StringExtras.h @@ -332,7 +332,7 @@ inline std::string toString(const APInt &I, unsigned Radix, bool Signed, bool formatAsCLiteral = false) { SmallString<40> S; I.toString(S, Radix, Signed, formatAsCLiteral); - return std::string(S.str()); + return std::string(S); } inline std::string toString(const APSInt &I, unsigned Radix) { diff --git a/llvm/include/llvm/Analysis/AliasAnalysis.h b/llvm/include/llvm/Analysis/AliasAnalysis.h index e1cfb025fb6..d6f732d35fd 100644 --- a/llvm/include/llvm/Analysis/AliasAnalysis.h +++ b/llvm/include/llvm/Analysis/AliasAnalysis.h @@ -154,6 +154,8 @@ struct CaptureInfo { /// Check whether Object is not captured before instruction I. If OrAt is /// true, captures by instruction I itself are also considered. + /// + /// If I is nullptr, then captures at any point will be considered. virtual bool isNotCapturedBefore(const Value *Object, const Instruction *I, bool OrAt) = 0; }; diff --git a/llvm/include/llvm/Analysis/AliasSetTracker.h b/llvm/include/llvm/Analysis/AliasSetTracker.h index 8afe455e2f0..3030cb30864 100644 --- a/llvm/include/llvm/Analysis/AliasSetTracker.h +++ b/llvm/include/llvm/Analysis/AliasSetTracker.h @@ -7,7 +7,7 @@ //===----------------------------------------------------------------------===// // // This file defines two classes: AliasSetTracker and AliasSet. These interfaces -// are used to classify a collection of pointer references into a maximal number +// are used to classify a collection of memory locations into a maximal number // of disjoint sets. Each AliasSet object constructed by the AliasSetTracker // object refers to memory disjoint from the other sets. // @@ -19,7 +19,7 @@ #define LLVM_ANALYSIS_ALIASSETTRACKER_H #include "llvm/ADT/DenseMap.h" -#include "llvm/ADT/DenseMapInfo.h" +#include "llvm/ADT/SmallVector.h" #include "llvm/ADT/ilist.h" #include "llvm/ADT/ilist_node.h" #include "llvm/Analysis/MemoryLocation.h" @@ -27,8 +27,6 @@ #include "llvm/IR/PassManager.h" #include "llvm/IR/ValueHandle.h" #include -#include -#include #include namespace llvm { @@ -49,99 +47,12 @@ class Value; class AliasSet : public ilist_node { friend class AliasSetTracker; - class PointerRec { - Value *Val; // The pointer this record corresponds to. - PointerRec **PrevInList = nullptr; - PointerRec *NextInList = nullptr; - AliasSet *AS = nullptr; - LocationSize Size = LocationSize::mapEmpty(); - AAMDNodes AAInfo; - - // Whether the size for this record has been set at all. This makes no - // guarantees about the size being known. - bool isSizeSet() const { return Size != LocationSize::mapEmpty(); } - - public: - PointerRec(Value *V) - : Val(V), AAInfo(DenseMapInfo::getEmptyKey()) {} - - Value *getValue() const { return Val; } - - PointerRec *getNext() const { return NextInList; } - bool hasAliasSet() const { return AS != nullptr; } - - PointerRec** setPrevInList(PointerRec **PIL) { - PrevInList = PIL; - return &NextInList; - } - - bool updateSizeAndAAInfo(LocationSize NewSize, const AAMDNodes &NewAAInfo) { - bool SizeChanged = false; - if (NewSize != Size) { - LocationSize OldSize = Size; - Size = isSizeSet() ? Size.unionWith(NewSize) : NewSize; - SizeChanged = OldSize != Size; - } - - if (AAInfo == DenseMapInfo::getEmptyKey()) - // We don't have a AAInfo yet. Set it to NewAAInfo. - AAInfo = NewAAInfo; - else { - AAMDNodes Intersection(AAInfo.intersect(NewAAInfo)); - SizeChanged |= Intersection != AAInfo; - AAInfo = Intersection; - } - return SizeChanged; - } - - LocationSize getSize() const { - assert(isSizeSet() && "Getting an unset size!"); - return Size; - } - - /// Return the AAInfo, or null if there is no information or conflicting - /// information. - AAMDNodes getAAInfo() const { - // If we have missing or conflicting AAInfo, return null. - if (AAInfo == DenseMapInfo::getEmptyKey() || - AAInfo == DenseMapInfo::getTombstoneKey()) - return AAMDNodes(); - return AAInfo; - } - - AliasSet *getAliasSet(AliasSetTracker &AST) { - assert(AS && "No AliasSet yet!"); - if (AS->Forward) { - AliasSet *OldAS = AS; - AS = OldAS->getForwardedTarget(AST); - AS->addRef(); - OldAS->dropRef(AST); - } - return AS; - } - - void setAliasSet(AliasSet *as) { - assert(!AS && "Already have an alias set!"); - AS = as; - } - - void eraseFromList() { - if (NextInList) NextInList->PrevInList = PrevInList; - *PrevInList = NextInList; - if (AS->PtrListEnd == &NextInList) { - AS->PtrListEnd = PrevInList; - assert(*AS->PtrListEnd == nullptr && "List not terminated right!"); - } - delete this; - } - }; - - // Doubly linked list of nodes. - PointerRec *PtrList = nullptr; - PointerRec **PtrListEnd; // Forwarding pointer. AliasSet *Forward = nullptr; + /// Memory locations in this alias set. + SmallVector MemoryLocs; + /// All instructions without a specific address in this alias set. std::vector> UnknownInsts; @@ -178,8 +89,6 @@ class AliasSet : public ilist_node { }; unsigned Alias : 1; - unsigned SetSize = 0; - void addRef() { ++RefCount; } void dropRef(AliasSetTracker &AST) { @@ -205,95 +114,40 @@ public: /// Merge the specified alias set into this alias set. void mergeSetIn(AliasSet &AS, AliasSetTracker &AST, BatchAAResults &BatchAA); - // Alias Set iteration - Allow access to all of the pointers which are part of - // this alias set. - class iterator; - iterator begin() const { return iterator(PtrList); } - iterator end() const { return iterator(); } - bool empty() const { return PtrList == nullptr; } + // Alias Set iteration - Allow access to all of the memory locations which are + // part of this alias set. + using iterator = SmallVectorImpl::const_iterator; + iterator begin() const { return MemoryLocs.begin(); } + iterator end() const { return MemoryLocs.end(); } - // Unfortunately, ilist::size() is linear, so we have to add code to keep - // track of the list's exact size. - unsigned size() { return SetSize; } + unsigned size() { return MemoryLocs.size(); } + + /// Retrieve the pointer values for the memory locations in this alias set. + /// The order matches that of the memory locations, but duplicate pointer + /// values are omitted. + using PointerVector = SmallVector; + PointerVector getPointers() const; void print(raw_ostream &OS) const; void dump() const; - /// Define an iterator for alias sets... this is just a forward iterator. - class iterator { - PointerRec *CurNode; - - public: - using iterator_category = std::forward_iterator_tag; - using value_type = PointerRec; - using difference_type = std::ptrdiff_t; - using pointer = value_type *; - using reference = value_type &; - - explicit iterator(PointerRec *CN = nullptr) : CurNode(CN) {} - - bool operator==(const iterator& x) const { - return CurNode == x.CurNode; - } - bool operator!=(const iterator& x) const { return !operator==(x); } - - value_type &operator*() const { - assert(CurNode && "Dereferencing AliasSet.end()!"); - return *CurNode; - } - value_type *operator->() const { return &operator*(); } - - Value *getPointer() const { return CurNode->getValue(); } - LocationSize getSize() const { return CurNode->getSize(); } - AAMDNodes getAAInfo() const { return CurNode->getAAInfo(); } - - iterator& operator++() { // Preincrement - assert(CurNode && "Advancing past AliasSet.end()!"); - CurNode = CurNode->getNext(); - return *this; - } - iterator operator++(int) { // Postincrement - iterator tmp = *this; ++*this; return tmp; - } - }; - private: // Can only be created by AliasSetTracker. AliasSet() - : PtrListEnd(&PtrList), RefCount(0), AliasAny(false), Access(NoAccess), - Alias(SetMustAlias) {} - - PointerRec *getSomePointer() const { - return PtrList; - } - - /// Return the real alias set this represents. If this has been merged with - /// another set and is forwarding, return the ultimate destination set. This - /// also implements the union-find collapsing as well. - AliasSet *getForwardedTarget(AliasSetTracker &AST) { - if (!Forward) return this; - - AliasSet *Dest = Forward->getForwardedTarget(AST); - if (Dest != Forward) { - Dest->addRef(); - Forward->dropRef(AST); - Forward = Dest; - } - return Dest; - } + : RefCount(0), AliasAny(false), Access(NoAccess), Alias(SetMustAlias) {} void removeFromTracker(AliasSetTracker &AST); - void addPointer(AliasSetTracker &AST, PointerRec &Entry, LocationSize Size, - const AAMDNodes &AAInfo, bool KnownMustAlias = false, - bool SkipSizeUpdate = false); + void addMemoryLocation(AliasSetTracker &AST, const MemoryLocation &MemLoc, + bool KnownMustAlias = false); void addUnknownInst(Instruction *I, BatchAAResults &AA); public: - /// If the specified pointer "may" (or must) alias one of the members in the - /// set return the appropriate AliasResult. Otherwise return NoAlias. - AliasResult aliasesPointer(const Value *Ptr, LocationSize Size, - const AAMDNodes &AAInfo, BatchAAResults &AA) const; + /// If the specified memory location "may" (or must) alias one of the members + /// in the set return the appropriate AliasResult. Otherwise return NoAlias. + AliasResult aliasesMemoryLocation(const MemoryLocation &MemLoc, + BatchAAResults &AA) const; + ModRefInfo aliasesUnknownInst(const Instruction *Inst, BatchAAResults &AA) const; }; @@ -307,9 +161,10 @@ class AliasSetTracker { BatchAAResults &AA; ilist AliasSets; - using PointerMapType = DenseMap, AliasSet::PointerRec *>; + using PointerMapType = DenseMap, AliasSet *>; - // Map from pointers to their node + // Map from pointer values to the alias set holding one or more memory + // locations with that pointer value. PointerMapType PointerMap; public: @@ -327,9 +182,6 @@ public: /// 3. If the instruction aliases multiple sets, merge the sets, and add /// the instruction to the result. /// - /// These methods return true if inserting the instruction resulted in the - /// addition of a new alias set (i.e., the pointer did not alias anything). - /// void add(const MemoryLocation &Loc); void add(LoadInst *LI); void add(StoreInst *SI); @@ -370,31 +222,39 @@ public: private: friend class AliasSet; - // The total number of pointers contained in all "may" alias sets. - unsigned TotalMayAliasSetSize = 0; + // The total number of memory locations contained in all alias sets. + unsigned TotalAliasSetSize = 0; // A non-null value signifies this AST is saturated. A saturated AST lumps - // all pointers into a single "May" set. + // all elements into a single "May" set. AliasSet *AliasAnyAS = nullptr; void removeAliasSet(AliasSet *AS); - /// Just like operator[] on the map, except that it creates an entry for the - /// pointer if it doesn't already exist. - AliasSet::PointerRec &getEntryFor(Value *V) { - AliasSet::PointerRec *&Entry = PointerMap[V]; - if (!Entry) - Entry = new AliasSet::PointerRec(V); - return *Entry; + // Update an alias set field to point to its real destination. If the field is + // pointing to a set that has been merged with another set and is forwarding, + // the field is updated to point to the set obtained by following the + // forwarding links. The Forward fields of intermediate alias sets are + // collapsed as well, and alias set reference counts are updated to reflect + // the new situation. + void collapseForwardingIn(AliasSet *&AS) { + if (AS->Forward) { + collapseForwardingIn(AS->Forward); + // Swap out AS for AS->Forward, while updating reference counts. + AliasSet *NewAS = AS->Forward; + NewAS->addRef(); + AS->dropRef(*this); + AS = NewAS; + } } - AliasSet &addPointer(MemoryLocation Loc, AliasSet::AccessLattice E); - AliasSet *mergeAliasSetsForPointer(const Value *Ptr, LocationSize Size, - const AAMDNodes &AAInfo, - bool &MustAliasAll); + AliasSet &addMemoryLocation(MemoryLocation Loc, AliasSet::AccessLattice E); + AliasSet *mergeAliasSetsForMemoryLocation(const MemoryLocation &MemLoc, + AliasSet *PtrAS, + bool &MustAliasAll); - /// Merge all alias sets into a single set that is considered to alias any - /// pointer. + /// Merge all alias sets into a single set that is considered to alias + /// any memory location or instruction. AliasSet &mergeAllAliasSets(); AliasSet *findAliasSetForUnknownInst(Instruction *Inst); diff --git a/llvm/include/llvm/Analysis/BlockFrequencyInfoImpl.h b/llvm/include/llvm/Analysis/BlockFrequencyInfoImpl.h index 0c05be0b9b8..8acb75e8725 100644 --- a/llvm/include/llvm/Analysis/BlockFrequencyInfoImpl.h +++ b/llvm/include/llvm/Analysis/BlockFrequencyInfoImpl.h @@ -1532,8 +1532,7 @@ void BlockFrequencyInfoImpl::findReachableBlocks( SmallPtrSet InverseReachable; for (const BlockT &BB : *F) { // An exit block is a block without any successors - bool HasSucc = GraphTraits::child_begin(&BB) != - GraphTraits::child_end(&BB); + bool HasSucc = !llvm::children(&BB).empty(); if (!HasSucc && Reachable.count(&BB)) { Queue.push(&BB); InverseReachable.insert(&BB); @@ -1542,7 +1541,7 @@ void BlockFrequencyInfoImpl::findReachableBlocks( while (!Queue.empty()) { const BlockT *SrcBB = Queue.front(); Queue.pop(); - for (const BlockT *DstBB : children>(SrcBB)) { + for (const BlockT *DstBB : inverse_children(SrcBB)) { auto EP = BPI->getEdgeProbability(DstBB, SrcBB); if (EP.isZero()) continue; diff --git a/llvm/include/llvm/Analysis/DOTGraphTraitsPass.h b/llvm/include/llvm/Analysis/DOTGraphTraitsPass.h index 07c08bc1cc3..da72fb511f8 100644 --- a/llvm/include/llvm/Analysis/DOTGraphTraitsPass.h +++ b/llvm/include/llvm/Analysis/DOTGraphTraitsPass.h @@ -16,6 +16,9 @@ #include "llvm/Analysis/CFGPrinter.h" #include "llvm/Support/FileSystem.h" #include "llvm/Support/GraphWriter.h" +#include + +static std::unordered_set nameObj; namespace llvm { @@ -83,10 +86,28 @@ private: StringRef Name; }; +static inline void shortenFileName(std::string &FN, unsigned char len = 250) { + + FN = FN.substr(0, len); + + auto strLen = FN.length(); + while (strLen > 0) { + if (auto it = nameObj.find(FN); it != nameObj.end()) { + FN = FN.substr(0, --len); + } else { + nameObj.insert(FN); + break; + } + strLen--; + } +} + template void printGraphForFunction(Function &F, GraphT Graph, StringRef Name, bool IsSimple) { - std::string Filename = Name.str() + "." + F.getName().str() + ".dot"; + std::string Filename = Name.str() + "." + F.getName().str(); + shortenFileName(Filename); + Filename = Filename + ".dot"; std::error_code EC; errs() << "Writing '" << Filename << "'..."; @@ -272,6 +293,7 @@ public: bool runOnModule(Module &M) override { GraphT Graph = AnalysisGraphTraitsT::getGraph(&getAnalysis()); + shortenFileName(Name); std::string Filename = Name + ".dot"; std::error_code EC; @@ -301,7 +323,9 @@ private: template void WriteDOTGraphToFile(Function &F, GraphT &&Graph, std::string FileNamePrefix, bool IsSimple) { - std::string Filename = FileNamePrefix + "." + F.getName().str() + ".dot"; + std::string Filename = FileNamePrefix + "." + F.getName().str(); + shortenFileName(Filename); + Filename = Filename + ".dot"; std::error_code EC; errs() << "Writing '" << Filename << "'..."; diff --git a/llvm/include/llvm/Analysis/RegionInfoImpl.h b/llvm/include/llvm/Analysis/RegionInfoImpl.h index ec79b35ae32..c5e8821858f 100644 --- a/llvm/include/llvm/Analysis/RegionInfoImpl.h +++ b/llvm/include/llvm/Analysis/RegionInfoImpl.h @@ -163,9 +163,7 @@ typename RegionBase::BlockT *RegionBase::getEnteringBlock() const { assert(!AllowRepeats && "Unexpected parameter value."); return DT->getNode(Pred) && !contains(Pred) ? Pred : nullptr; }; - BlockT *entry = getEntry(); - return find_singleton(make_range(InvBlockTraits::child_begin(entry), - InvBlockTraits::child_end(entry)), + return find_singleton(llvm::inverse_children(getEntry()), isEnteringBlock); } @@ -177,10 +175,7 @@ bool RegionBase::getExitingBlocks( if (!exit) return CoverAll; - for (PredIterTy PI = InvBlockTraits::child_begin(exit), - PE = InvBlockTraits::child_end(exit); - PI != PE; ++PI) { - BlockT *Pred = *PI; + for (BlockT *Pred : llvm::inverse_children(exit)) { if (contains(Pred)) { Exitings.push_back(Pred); continue; @@ -202,8 +197,7 @@ typename RegionBase::BlockT *RegionBase::getExitingBlock() const { assert(!AllowRepeats && "Unexpected parameter value."); return contains(Pred) ? Pred : nullptr; }; - return find_singleton(make_range(InvBlockTraits::child_begin(exit), - InvBlockTraits::child_end(exit)), + return find_singleton(llvm::inverse_children(exit), isContained); } @@ -244,16 +238,14 @@ void RegionBase::verifyBBInRegion(BlockT *BB) const { BlockT *entry = getEntry(), *exit = getExit(); - for (BlockT *Succ : - make_range(BlockTraits::child_begin(BB), BlockTraits::child_end(BB))) { + for (BlockT *Succ : llvm::children(BB)) { if (!contains(Succ) && exit != Succ) report_fatal_error("Broken region found: edges leaving the region must go " "to the exit node!"); } if (entry != BB) { - for (BlockT *Pred : make_range(InvBlockTraits::child_begin(BB), - InvBlockTraits::child_end(BB))) { + for (BlockT *Pred : llvm::inverse_children(BB)) { // Allow predecessors that are unreachable, as these are ignored during // region analysis. if (!contains(Pred) && DT->isReachableFromEntry(Pred)) @@ -271,8 +263,7 @@ void RegionBase::verifyWalk(BlockT *BB, std::set *visited) const { verifyBBInRegion(BB); - for (BlockT *Succ : - make_range(BlockTraits::child_begin(BB), BlockTraits::child_end(BB))) { + for (BlockT *Succ : llvm::children(BB)) { if (Succ != exit && visited->find(Succ) == visited->end()) verifyWalk(Succ, visited); } @@ -453,8 +444,7 @@ typename Tr::RegionT *RegionBase::getExpandedRegion() const { RegionT *R = RI->getRegionFor(exit); if (R->getEntry() != exit) { - for (BlockT *Pred : make_range(InvBlockTraits::child_begin(getExit()), - InvBlockTraits::child_end(getExit()))) + for (BlockT *Pred : llvm::inverse_children(getExit())) if (!contains(Pred)) return nullptr; if (Tr::getNumSuccessors(exit) == 1) @@ -465,8 +455,7 @@ typename Tr::RegionT *RegionBase::getExpandedRegion() const { while (R->getParent() && R->getParent()->getEntry() == exit) R = R->getParent(); - for (BlockT *Pred : make_range(InvBlockTraits::child_begin(getExit()), - InvBlockTraits::child_end(getExit()))) { + for (BlockT *Pred : llvm::inverse_children(getExit())) { if (!(contains(Pred) || R->contains(Pred))) return nullptr; } @@ -553,8 +542,7 @@ void RegionInfoBase::verifyBBMap(const RegionT *R) const { template bool RegionInfoBase::isCommonDomFrontier(BlockT *BB, BlockT *entry, BlockT *exit) const { - for (BlockT *P : make_range(InvBlockTraits::child_begin(BB), - InvBlockTraits::child_end(BB))) { + for (BlockT *P : llvm::inverse_children(BB)) { if (DT->dominates(entry, P) && !DT->dominates(exit, P)) return false; } @@ -837,8 +825,7 @@ RegionInfoBase::getMaxRegionExit(BlockT *BB) const { ExitR->getParent()->getEntry() == Exit) ExitR = ExitR->getParent(); - for (BlockT *Pred : make_range(InvBlockTraits::child_begin(Exit), - InvBlockTraits::child_end(Exit))) { + for (BlockT *Pred : llvm::inverse_children(Exit)) { if (!R->contains(Pred) && !ExitR->contains(Pred)) break; } diff --git a/llvm/include/llvm/Analysis/TargetTransformInfo.h b/llvm/include/llvm/Analysis/TargetTransformInfo.h index 9697278eaea..3b615bc700b 100644 --- a/llvm/include/llvm/Analysis/TargetTransformInfo.h +++ b/llvm/include/llvm/Analysis/TargetTransformInfo.h @@ -934,6 +934,12 @@ public: /// Should the Select Optimization pass be enabled and ran. bool enableSelectOptimize() const; + /// Should the Select Optimization pass treat the given instruction like a + /// select, potentially converting it to a conditional branch. This can + /// include select-like instructions like or(zext(c), x) that can be converted + /// to selects. + bool shouldTreatInstructionLikeSelect(const Instruction *I) const; + /// Enable matching of interleaved access groups. bool enableInterleavedAccessVectorization() const; @@ -1878,6 +1884,7 @@ public: virtual MemCmpExpansionOptions enableMemCmpExpansion(bool OptSize, bool IsZeroCmp) const = 0; virtual bool enableSelectOptimize() = 0; + virtual bool shouldTreatInstructionLikeSelect(const Instruction *I) = 0; virtual bool enableInterleavedAccessVectorization() = 0; virtual bool enableMaskedInterleavedAccessVectorization() = 0; virtual bool isFPVectorizationPotentiallyUnsafe() = 0; @@ -2415,6 +2422,9 @@ public: bool enableSelectOptimize() override { return Impl.enableSelectOptimize(); } + bool shouldTreatInstructionLikeSelect(const Instruction *I) override { + return Impl.shouldTreatInstructionLikeSelect(I); + } bool enableInterleavedAccessVectorization() override { return Impl.enableInterleavedAccessVectorization(); } diff --git a/llvm/include/llvm/Analysis/TargetTransformInfoImpl.h b/llvm/include/llvm/Analysis/TargetTransformInfoImpl.h index 60eab53fa2f..9958b4daa6e 100644 --- a/llvm/include/llvm/Analysis/TargetTransformInfoImpl.h +++ b/llvm/include/llvm/Analysis/TargetTransformInfoImpl.h @@ -378,6 +378,15 @@ public: bool enableSelectOptimize() const { return true; } + bool shouldTreatInstructionLikeSelect(const Instruction *I) { + // If the select is a logical-and/logical-or then it is better treated as a + // and/or by the backend. + using namespace llvm::PatternMatch; + return isa(I) && + !match(I, m_CombineOr(m_LogicalAnd(m_Value(), m_Value()), + m_LogicalOr(m_Value(), m_Value()))); + } + bool enableInterleavedAccessVectorization() const { return false; } bool enableMaskedInterleavedAccessVectorization() const { return false; } diff --git a/llvm/include/llvm/Analysis/VecFuncs.def b/llvm/include/llvm/Analysis/VecFuncs.def index b22bdd555cd..f09e12f3038 100644 --- a/llvm/include/llvm/Analysis/VecFuncs.def +++ b/llvm/include/llvm/Analysis/VecFuncs.def @@ -472,19 +472,33 @@ TLI_DEFINE_VECFUNC("__exp2f_finite", "__svml_exp2f16", FIXED(16), "_ZGV_LLVM_N16 TLI_DEFINE_VECFUNC("acos", "_ZGVnN2v_acos", FIXED(2), "_ZGV_LLVM_N2v") +TLI_DEFINE_VECFUNC("acosh", "_ZGVnN2v_acosh", FIXED(2), "_ZGV_LLVM_N2v") + TLI_DEFINE_VECFUNC("asin", "_ZGVnN2v_asin", FIXED(2), "_ZGV_LLVM_N2v") +TLI_DEFINE_VECFUNC("asinh", "_ZGVnN2v_asinh", FIXED(2), "_ZGV_LLVM_N2v") + TLI_DEFINE_VECFUNC("atan", "_ZGVnN2v_atan", FIXED(2), "_ZGV_LLVM_N2v") TLI_DEFINE_VECFUNC("atan2", "_ZGVnN2vv_atan2", FIXED(2), "_ZGV_LLVM_N2vv") TLI_DEFINE_VECFUNC("atanh", "_ZGVnN2v_atanh", FIXED(2), "_ZGV_LLVM_N2v") +TLI_DEFINE_VECFUNC("cbrt", "_ZGVnN2v_cbrt", FIXED(2), "_ZGV_LLVM_N2v") + +TLI_DEFINE_VECFUNC("copysign", "_ZGVnN2vv_copysign", FIXED(2), "_ZGV_LLVM_N2vv") + TLI_DEFINE_VECFUNC("cos", "_ZGVnN2v_cos", FIXED(2), "_ZGV_LLVM_N2v") TLI_DEFINE_VECFUNC("llvm.cos.f64", "_ZGVnN2v_cos", FIXED(2), "_ZGV_LLVM_N2v") TLI_DEFINE_VECFUNC("cosh", "_ZGVnN2v_cosh", FIXED(2), "_ZGV_LLVM_N2v") +TLI_DEFINE_VECFUNC("cospi", "_ZGVnN2v_cospi", FIXED(2), "_ZGV_LLVM_N2v") + +TLI_DEFINE_VECFUNC("erf", "_ZGVnN2v_erf", FIXED(2), "_ZGV_LLVM_N2v") + +TLI_DEFINE_VECFUNC("erfc", "_ZGVnN2v_erfc", FIXED(2), "_ZGV_LLVM_N2v") + TLI_DEFINE_VECFUNC("exp", "_ZGVnN2v_exp", FIXED(2), "_ZGV_LLVM_N2v") TLI_DEFINE_VECFUNC("llvm.exp.f64", "_ZGVnN2v_exp", FIXED(2), "_ZGV_LLVM_N2v") @@ -494,8 +508,24 @@ TLI_DEFINE_VECFUNC("llvm.exp10.f64", "_ZGVnN2v_exp10", FIXED(2), "_ZGV_LLVM_N2v" TLI_DEFINE_VECFUNC("exp2", "_ZGVnN2v_exp2", FIXED(2), "_ZGV_LLVM_N2v") TLI_DEFINE_VECFUNC("llvm.exp2.f64", "_ZGVnN2v_exp2", FIXED(2), "_ZGV_LLVM_N2v") +TLI_DEFINE_VECFUNC("expm1", "_ZGVnN2v_expm1", FIXED(2), "_ZGV_LLVM_N2v") + +TLI_DEFINE_VECFUNC("fdim", "_ZGVnN2vv_fdim", FIXED(2), "_ZGV_LLVM_N2vv") + +TLI_DEFINE_VECFUNC("fma", "_ZGVnN2vvv_fma", FIXED(2), "_ZGV_LLVM_N2vvv") + +TLI_DEFINE_VECFUNC("fmax", "_ZGVnN2vv_fmax", FIXED(2), "_ZGV_LLVM_N2vv") + +TLI_DEFINE_VECFUNC("fmin", "_ZGVnN2vv_fmin", FIXED(2), "_ZGV_LLVM_N2vv") + TLI_DEFINE_VECFUNC("fmod", "_ZGVnN2vv_fmod", FIXED(2), "_ZGV_LLVM_N2vv") +TLI_DEFINE_VECFUNC("hypot", "_ZGVnN2vv_hypot", FIXED(2), "_ZGV_LLVM_N2vv") + +TLI_DEFINE_VECFUNC("ilogb", "_ZGVnN2v_ilogb", FIXED(2), "_ZGV_LLVM_N2v") + +TLI_DEFINE_VECFUNC("ldexp", "_ZGVnN2vv_ldexp", FIXED(2), "_ZGV_LLVM_N2vv") + TLI_DEFINE_VECFUNC("lgamma", "_ZGVnN2v_lgamma", FIXED(2), "_ZGV_LLVM_N2v") TLI_DEFINE_VECFUNC("log", "_ZGVnN2v_log", FIXED(2), "_ZGV_LLVM_N2v") @@ -504,11 +534,15 @@ TLI_DEFINE_VECFUNC("llvm.log.f64", "_ZGVnN2v_log", FIXED(2), "_ZGV_LLVM_N2v") TLI_DEFINE_VECFUNC("log10", "_ZGVnN2v_log10", FIXED(2), "_ZGV_LLVM_N2v") TLI_DEFINE_VECFUNC("llvm.log10.f64", "_ZGVnN2v_log10", FIXED(2), "_ZGV_LLVM_N2v") +TLI_DEFINE_VECFUNC("log1p", "_ZGVnN2v_log1p", FIXED(2), "_ZGV_LLVM_N2v") + TLI_DEFINE_VECFUNC("log2", "_ZGVnN2v_log2", FIXED(2), "_ZGV_LLVM_N2v") TLI_DEFINE_VECFUNC("llvm.log2.f64", "_ZGVnN2v_log2", FIXED(2), "_ZGV_LLVM_N2v") TLI_DEFINE_VECFUNC("modf", "_ZGVnN2vl8_modf", FIXED(2), "_ZGV_LLVM_N2vl8") +TLI_DEFINE_VECFUNC("nextafter", "_ZGVnN2vv_nextafter", FIXED(2), "_ZGV_LLVM_N2vv") + TLI_DEFINE_VECFUNC("pow", "_ZGVnN2vv_pow", FIXED(2), "_ZGV_LLVM_N2vv") TLI_DEFINE_VECFUNC("llvm.pow.f64", "_ZGVnN2vv_pow", FIXED(2), "_ZGV_LLVM_N2vv") @@ -521,6 +555,8 @@ TLI_DEFINE_VECFUNC("sincospi", "_ZGVnN2vl8l8_sincospi", FIXED(2), "_ZGV_LLVM_N2v TLI_DEFINE_VECFUNC("sinh", "_ZGVnN2v_sinh", FIXED(2), "_ZGV_LLVM_N2v") +TLI_DEFINE_VECFUNC("sinpi", "_ZGVnN2v_sinpi", FIXED(2), "_ZGV_LLVM_N2v") + TLI_DEFINE_VECFUNC("sqrt", "_ZGVnN2v_sqrt", FIXED(2), "_ZGV_LLVM_N2v") TLI_DEFINE_VECFUNC("tan", "_ZGVnN2v_tan", FIXED(2), "_ZGV_LLVM_N2v") @@ -533,19 +569,33 @@ TLI_DEFINE_VECFUNC("tgamma", "_ZGVnN2v_tgamma", FIXED(2), "_ZGV_LLVM_N2v") TLI_DEFINE_VECFUNC("acosf", "_ZGVnN4v_acosf", FIXED(4), "_ZGV_LLVM_N4v") +TLI_DEFINE_VECFUNC("acoshf", "_ZGVnN4v_acoshf", FIXED(4), "_ZGV_LLVM_N4v") + TLI_DEFINE_VECFUNC("asinf", "_ZGVnN4v_asinf", FIXED(4), "_ZGV_LLVM_N4v") +TLI_DEFINE_VECFUNC("asinhf", "_ZGVnN4v_asinhf", FIXED(4), "_ZGV_LLVM_N4v") + TLI_DEFINE_VECFUNC("atanf", "_ZGVnN4v_atanf", FIXED(4), "_ZGV_LLVM_N4v") TLI_DEFINE_VECFUNC("atan2f", "_ZGVnN4vv_atan2f", FIXED(4), "_ZGV_LLVM_N4vv") TLI_DEFINE_VECFUNC("atanhf", "_ZGVnN4v_atanhf", FIXED(4), "_ZGV_LLVM_N4v") +TLI_DEFINE_VECFUNC("cbrtf", "_ZGVnN4v_cbrtf", FIXED(4), "_ZGV_LLVM_N4v") + +TLI_DEFINE_VECFUNC("copysignf", "_ZGVnN4vv_copysignf", FIXED(4), "_ZGV_LLVM_N4vv") + TLI_DEFINE_VECFUNC("cosf", "_ZGVnN4v_cosf", FIXED(4), "_ZGV_LLVM_N4v") TLI_DEFINE_VECFUNC("llvm.cos.f32", "_ZGVnN4v_cosf", FIXED(4), "_ZGV_LLVM_N4v") TLI_DEFINE_VECFUNC("coshf", "_ZGVnN4v_coshf", FIXED(4), "_ZGV_LLVM_N4v") +TLI_DEFINE_VECFUNC("cospif", "_ZGVnN4v_cospif", FIXED(4), "_ZGV_LLVM_N4v") + +TLI_DEFINE_VECFUNC("erff", "_ZGVnN4v_erff", FIXED(4), "_ZGV_LLVM_N4v") + +TLI_DEFINE_VECFUNC("erfcf", "_ZGVnN4v_erfcf", FIXED(4), "_ZGV_LLVM_N4v") + TLI_DEFINE_VECFUNC("expf", "_ZGVnN4v_expf", FIXED(4), "_ZGV_LLVM_N4v") TLI_DEFINE_VECFUNC("llvm.exp.f32", "_ZGVnN4v_expf", FIXED(4), "_ZGV_LLVM_N4v") @@ -555,8 +605,24 @@ TLI_DEFINE_VECFUNC("llvm.exp10.f32", "_ZGVnN4v_exp10f", FIXED(4), "_ZGV_LLVM_N4v TLI_DEFINE_VECFUNC("exp2f", "_ZGVnN4v_exp2f", FIXED(4), "_ZGV_LLVM_N4v") TLI_DEFINE_VECFUNC("llvm.exp2.f32", "_ZGVnN4v_exp2f", FIXED(4), "_ZGV_LLVM_N4v") +TLI_DEFINE_VECFUNC("expm1f", "_ZGVnN4v_expm1f", FIXED(4), "_ZGV_LLVM_N4v") + +TLI_DEFINE_VECFUNC("fdimf", "_ZGVnN4vv_fdimf", FIXED(4), "_ZGV_LLVM_N4vv") + +TLI_DEFINE_VECFUNC("fmaf", "_ZGVnN4vvv_fmaf", FIXED(4), "_ZGV_LLVM_N4vvv") + +TLI_DEFINE_VECFUNC("fmaxf", "_ZGVnN4vv_fmaxf", FIXED(4), "_ZGV_LLVM_N4vv") + +TLI_DEFINE_VECFUNC("fminf", "_ZGVnN4vv_fminf", FIXED(4), "_ZGV_LLVM_N4vv") + TLI_DEFINE_VECFUNC("fmodf", "_ZGVnN4vv_fmodf", FIXED(4), "_ZGV_LLVM_N4vv") +TLI_DEFINE_VECFUNC("hypotf", "_ZGVnN4vv_hypotf", FIXED(4), "_ZGV_LLVM_N4vv") + +TLI_DEFINE_VECFUNC("ilogbf", "_ZGVnN4v_ilogbf", FIXED(4), "_ZGV_LLVM_N4v") + +TLI_DEFINE_VECFUNC("ldexpf", "_ZGVnN4vv_ldexpf", FIXED(4), "_ZGV_LLVM_N4vv") + TLI_DEFINE_VECFUNC("lgammaf", "_ZGVnN4v_lgammaf", FIXED(4), "_ZGV_LLVM_N4v") TLI_DEFINE_VECFUNC("logf", "_ZGVnN4v_logf", FIXED(4), "_ZGV_LLVM_N4v") @@ -565,11 +631,15 @@ TLI_DEFINE_VECFUNC("llvm.log.f32", "_ZGVnN4v_logf", FIXED(4), "_ZGV_LLVM_N4v") TLI_DEFINE_VECFUNC("log10f", "_ZGVnN4v_log10f", FIXED(4), "_ZGV_LLVM_N4v") TLI_DEFINE_VECFUNC("llvm.log10.f32", "_ZGVnN4v_log10f", FIXED(4), "_ZGV_LLVM_N4v") +TLI_DEFINE_VECFUNC("log1pf", "_ZGVnN4v_log1pf", FIXED(4), "_ZGV_LLVM_N4v") + TLI_DEFINE_VECFUNC("log2f", "_ZGVnN4v_log2f", FIXED(4), "_ZGV_LLVM_N4v") TLI_DEFINE_VECFUNC("llvm.log2.f32", "_ZGVnN4v_log2f", FIXED(4), "_ZGV_LLVM_N4v") TLI_DEFINE_VECFUNC("modff", "_ZGVnN4vl4_modff", FIXED(4), "_ZGV_LLVM_N4vl4") +TLI_DEFINE_VECFUNC("nextafterf", "_ZGVnN4vv_nextafterf", FIXED(4), "_ZGV_LLVM_N4vv") + TLI_DEFINE_VECFUNC("powf", "_ZGVnN4vv_powf", FIXED(4), "_ZGV_LLVM_N4vv") TLI_DEFINE_VECFUNC("llvm.pow.f32", "_ZGVnN4vv_powf", FIXED(4), "_ZGV_LLVM_N4vv") @@ -582,6 +652,8 @@ TLI_DEFINE_VECFUNC("sincospif", "_ZGVnN4vl4l4_sincospif", FIXED(4), "_ZGV_LLVM_N TLI_DEFINE_VECFUNC("sinhf", "_ZGVnN4v_sinhf", FIXED(4), "_ZGV_LLVM_N4v") +TLI_DEFINE_VECFUNC("sinpif", "_ZGVnN4v_sinpif", FIXED(4), "_ZGV_LLVM_N4v") + TLI_DEFINE_VECFUNC("sqrtf", "_ZGVnN4v_sqrtf", FIXED(4), "_ZGV_LLVM_N4v") TLI_DEFINE_VECFUNC("tanf", "_ZGVnN4v_tanf", FIXED(4), "_ZGV_LLVM_N4v") @@ -595,9 +667,15 @@ TLI_DEFINE_VECFUNC("tgammaf", "_ZGVnN4v_tgammaf", FIXED(4), "_ZGV_LLVM_N4v") TLI_DEFINE_VECFUNC("acos", "_ZGVsMxv_acos", SCALABLE(2), MASKED, "_ZGVsMxv") TLI_DEFINE_VECFUNC("acosf", "_ZGVsMxv_acosf", SCALABLE(4), MASKED, "_ZGVsMxv") +TLI_DEFINE_VECFUNC("acosh", "_ZGVsMxv_acosh", SCALABLE(2), MASKED, "_ZGVsMxv") +TLI_DEFINE_VECFUNC("acoshf", "_ZGVsMxv_acoshf", SCALABLE(4), MASKED, "_ZGVsMxv") + TLI_DEFINE_VECFUNC("asin", "_ZGVsMxv_asin", SCALABLE(2), MASKED, "_ZGVsMxv") TLI_DEFINE_VECFUNC("asinf", "_ZGVsMxv_asinf", SCALABLE(4), MASKED, "_ZGVsMxv") +TLI_DEFINE_VECFUNC("asinh", "_ZGVsMxv_asinh", SCALABLE(2), MASKED, "_ZGVsMxv") +TLI_DEFINE_VECFUNC("asinhf", "_ZGVsMxv_asinhf", SCALABLE(4), MASKED, "_ZGVsMxv") + TLI_DEFINE_VECFUNC("atan", "_ZGVsMxv_atan", SCALABLE(2), MASKED, "_ZGVsMxv") TLI_DEFINE_VECFUNC("atanf", "_ZGVsMxv_atanf", SCALABLE(4), MASKED, "_ZGVsMxv") @@ -607,6 +685,12 @@ TLI_DEFINE_VECFUNC("atan2f", "_ZGVsMxvv_atan2f", SCALABLE(4), MASKED, "_ZGVsMxvv TLI_DEFINE_VECFUNC("atanh", "_ZGVsMxv_atanh", SCALABLE(2), MASKED, "_ZGVsMxv") TLI_DEFINE_VECFUNC("atanhf", "_ZGVsMxv_atanhf", SCALABLE(4), MASKED, "_ZGVsMxv") +TLI_DEFINE_VECFUNC("cbrt", "_ZGVsMxv_cbrt", SCALABLE(2), MASKED, "_ZGVsMxv") +TLI_DEFINE_VECFUNC("cbrtf", "_ZGVsMxv_cbrtf", SCALABLE(4), MASKED, "_ZGVsMxv") + +TLI_DEFINE_VECFUNC("copysign", "_ZGVsMxvv_copysign", SCALABLE(2), MASKED, "_ZGVsMxvv") +TLI_DEFINE_VECFUNC("copysignf", "_ZGVsMxvv_copysignf", SCALABLE(4), MASKED, "_ZGVsMxvv") + TLI_DEFINE_VECFUNC("cos", "_ZGVsMxv_cos", SCALABLE(2), MASKED, "_ZGVsMxv") TLI_DEFINE_VECFUNC("cosf", "_ZGVsMxv_cosf", SCALABLE(4), MASKED, "_ZGVsMxv") TLI_DEFINE_VECFUNC("llvm.cos.f64", "_ZGVsMxv_cos", SCALABLE(2), MASKED, "_ZGVsMxv") @@ -615,6 +699,15 @@ TLI_DEFINE_VECFUNC("llvm.cos.f32", "_ZGVsMxv_cosf", SCALABLE(4), MASKED, "_ZGVsM TLI_DEFINE_VECFUNC("cosh", "_ZGVsMxv_cosh", SCALABLE(2), MASKED, "_ZGVsMxv") TLI_DEFINE_VECFUNC("coshf", "_ZGVsMxv_coshf", SCALABLE(4), MASKED, "_ZGVsMxv") +TLI_DEFINE_VECFUNC("cospi", "_ZGVsMxv_cospi", SCALABLE(2), MASKED, "_ZGVsMxv") +TLI_DEFINE_VECFUNC("cospif", "_ZGVsMxv_cospif", SCALABLE(4), MASKED, "_ZGVsMxv") + +TLI_DEFINE_VECFUNC("erf", "_ZGVsMxv_erf", SCALABLE(2), MASKED, "_ZGVsMxv") +TLI_DEFINE_VECFUNC("erff", "_ZGVsMxv_erff", SCALABLE(4), MASKED, "_ZGVsMxv") + +TLI_DEFINE_VECFUNC("erfc", "_ZGVsMxv_erfc", SCALABLE(2), MASKED, "_ZGVsMxv") +TLI_DEFINE_VECFUNC("erfcf", "_ZGVsMxv_erfcf", SCALABLE(4), MASKED, "_ZGVsMxv") + TLI_DEFINE_VECFUNC("exp", "_ZGVsMxv_exp", SCALABLE(2), MASKED, "_ZGVsMxv") TLI_DEFINE_VECFUNC("expf", "_ZGVsMxv_expf", SCALABLE(4), MASKED, "_ZGVsMxv") TLI_DEFINE_VECFUNC("llvm.exp.f64", "_ZGVsMxv_exp", SCALABLE(2), MASKED, "_ZGVsMxv") @@ -630,9 +723,33 @@ TLI_DEFINE_VECFUNC("exp2f", "_ZGVsMxv_exp2f", SCALABLE(4), MASKED, "_ZGVsMxv") TLI_DEFINE_VECFUNC("llvm.exp2.f64", "_ZGVsMxv_exp2", SCALABLE(2), MASKED, "_ZGVsMxv") TLI_DEFINE_VECFUNC("llvm.exp2.f32", "_ZGVsMxv_exp2f", SCALABLE(4), MASKED, "_ZGVsMxv") +TLI_DEFINE_VECFUNC("expm1", "_ZGVsMxv_expm1", SCALABLE(2), MASKED, "_ZGVsMxv") +TLI_DEFINE_VECFUNC("expm1f", "_ZGVsMxv_expm1f", SCALABLE(4), MASKED, "_ZGVsMxv") + +TLI_DEFINE_VECFUNC("fdim", "_ZGVsMxvv_fdim", SCALABLE(2), MASKED, "_ZGVsMxvv") +TLI_DEFINE_VECFUNC("fdimf", "_ZGVsMxvv_fdimf", SCALABLE(4), MASKED, "_ZGVsMxvv") + +TLI_DEFINE_VECFUNC("fma", "_ZGVsMxvvv_fma", SCALABLE(2), MASKED, "_ZGVsMxvvv") +TLI_DEFINE_VECFUNC("fmaf", "_ZGVsMxvvv_fmaf", SCALABLE(4), MASKED, "_ZGVsMxvvv") + +TLI_DEFINE_VECFUNC("fmax", "_ZGVsMxvv_fmax", SCALABLE(2), MASKED, "_ZGVsMxvv") +TLI_DEFINE_VECFUNC("fmaxf", "_ZGVsMxvv_fmaxf", SCALABLE(4), MASKED, "_ZGVsMxvv") + +TLI_DEFINE_VECFUNC("fmin", "_ZGVsMxvv_fmin", SCALABLE(2), MASKED, "_ZGVsMxvv") +TLI_DEFINE_VECFUNC("fminf", "_ZGVsMxvv_fminf", SCALABLE(4), MASKED, "_ZGVsMxvv") + TLI_DEFINE_VECFUNC("fmod", "_ZGVsMxvv_fmod", SCALABLE(2), MASKED, "_ZGVsMxvv") TLI_DEFINE_VECFUNC("fmodf", "_ZGVsMxvv_fmodf", SCALABLE(4), MASKED, "_ZGVsMxvv") +TLI_DEFINE_VECFUNC("hypot", "_ZGVsMxvv_hypot", SCALABLE(2), MASKED, "_ZGVsMxvv") +TLI_DEFINE_VECFUNC("hypotf", "_ZGVsMxvv_hypotf", SCALABLE(4), MASKED, "_ZGVsMxvv") + +TLI_DEFINE_VECFUNC("ilogb", "_ZGVsMxv_ilogb", SCALABLE(2), MASKED, "_ZGVsMxv") +TLI_DEFINE_VECFUNC("ilogbf", "_ZGVsMxv_ilogbf", SCALABLE(4), MASKED, "_ZGVsMxv") + +TLI_DEFINE_VECFUNC("ldexp", "_ZGVsMxvv_ldexp", SCALABLE(2), MASKED, "_ZGVsMxvv") +TLI_DEFINE_VECFUNC("ldexpf", "_ZGVsMxvv_ldexpf", SCALABLE(4), MASKED, "_ZGVsMxvv") + TLI_DEFINE_VECFUNC("lgamma", "_ZGVsMxv_lgamma", SCALABLE(2), MASKED, "_ZGVsMxv") TLI_DEFINE_VECFUNC("lgammaf", "_ZGVsMxv_lgammaf", SCALABLE(4), MASKED, "_ZGVsMxv") @@ -646,6 +763,9 @@ TLI_DEFINE_VECFUNC("log10f", "_ZGVsMxv_log10f", SCALABLE(4), MASKED, "_ZGVsMxv") TLI_DEFINE_VECFUNC("llvm.log10.f64", "_ZGVsMxv_log10", SCALABLE(2), MASKED, "_ZGVsMxv") TLI_DEFINE_VECFUNC("llvm.log10.f32", "_ZGVsMxv_log10f", SCALABLE(4), MASKED, "_ZGVsMxv") +TLI_DEFINE_VECFUNC("log1p", "_ZGVsMxv_log1p", SCALABLE(2), MASKED, "_ZGVsMxv") +TLI_DEFINE_VECFUNC("log1pf", "_ZGVsMxv_log1pf", SCALABLE(4), MASKED, "_ZGVsMxv") + TLI_DEFINE_VECFUNC("log2", "_ZGVsMxv_log2", SCALABLE(2), MASKED, "_ZGVsMxv") TLI_DEFINE_VECFUNC("log2f", "_ZGVsMxv_log2f", SCALABLE(4), MASKED, "_ZGVsMxv") TLI_DEFINE_VECFUNC("llvm.log2.f64", "_ZGVsMxv_log2", SCALABLE(2), MASKED, "_ZGVsMxv") @@ -654,6 +774,9 @@ TLI_DEFINE_VECFUNC("llvm.log2.f32", "_ZGVsMxv_log2f", SCALABLE(4), MASKED, "_ZGV TLI_DEFINE_VECFUNC("modf", "_ZGVsMxvl8_modf", SCALABLE(2), MASKED, "_ZGVsMxvl8") TLI_DEFINE_VECFUNC("modff", "_ZGVsMxvl4_modff", SCALABLE(4), MASKED, "_ZGVsMxvl4") +TLI_DEFINE_VECFUNC("nextafter", "_ZGVsMxvv_nextafter", SCALABLE(2), MASKED, "_ZGVsMxvv") +TLI_DEFINE_VECFUNC("nextafterf", "_ZGVsMxvv_nextafterf", SCALABLE(4), MASKED, "_ZGVsMxvv") + TLI_DEFINE_VECFUNC("pow", "_ZGVsMxvv_pow", SCALABLE(2), MASKED, "_ZGVsMxvv") TLI_DEFINE_VECFUNC("powf", "_ZGVsMxvv_powf", SCALABLE(4), MASKED, "_ZGVsMxvv") TLI_DEFINE_VECFUNC("llvm.pow.f64", "_ZGVsMxvv_pow", SCALABLE(2), MASKED, "_ZGVsMxvv") @@ -673,6 +796,9 @@ TLI_DEFINE_VECFUNC("sincospif", "_ZGVsMxvl4l4_sincospif", SCALABLE(4), MASKED, " TLI_DEFINE_VECFUNC("sinh", "_ZGVsMxv_sinh", SCALABLE(2), MASKED, "_ZGVsMxv") TLI_DEFINE_VECFUNC("sinhf", "_ZGVsMxv_sinhf", SCALABLE(4), MASKED, "_ZGVsMxv") +TLI_DEFINE_VECFUNC("sinpi", "_ZGVsMxv_sinpi", SCALABLE(2), MASKED, "_ZGVsMxv") +TLI_DEFINE_VECFUNC("sinpif", "_ZGVsMxv_sinpif", SCALABLE(4), MASKED, "_ZGVsMxv") + TLI_DEFINE_VECFUNC("sqrt", "_ZGVsMxv_sqrt", SCALABLE(2), MASKED, "_ZGVsMxv") TLI_DEFINE_VECFUNC("sqrtf", "_ZGVsMxv_sqrtf", SCALABLE(4), MASKED, "_ZGVsMxv") @@ -747,6 +873,11 @@ TLI_DEFINE_VECFUNC("coshf", "armpl_vcoshq_f32", FIXED(4), NOMASK, "_ZGV_LLVM_N4v TLI_DEFINE_VECFUNC("cosh", "armpl_svcosh_f64_x", SCALABLE(2), MASKED, "_ZGVsMxv") TLI_DEFINE_VECFUNC("coshf", "armpl_svcosh_f32_x", SCALABLE(4), MASKED, "_ZGVsMxv") +TLI_DEFINE_VECFUNC("cospi", "armpl_vcospiq_f64", FIXED(2), NOMASK, "_ZGV_LLVM_N2v") +TLI_DEFINE_VECFUNC("cospif", "armpl_vcospiq_f32", FIXED(4), NOMASK, "_ZGV_LLVM_N4v") +TLI_DEFINE_VECFUNC("cospi", "armpl_svcospi_f64_x", SCALABLE(2), MASKED, "_ZGVsMxv") +TLI_DEFINE_VECFUNC("cospif", "armpl_svcospi_f32_x", SCALABLE(4), MASKED, "_ZGVsMxv") + TLI_DEFINE_VECFUNC("erf", "armpl_verfq_f64", FIXED(2), NOMASK, "_ZGV_LLVM_N2v") TLI_DEFINE_VECFUNC("erff", "armpl_verfq_f32", FIXED(4), NOMASK, "_ZGV_LLVM_N4v") TLI_DEFINE_VECFUNC("erf", "armpl_sverf_f64_x", SCALABLE(2), MASKED, "_ZGVsMxv") @@ -802,6 +933,11 @@ TLI_DEFINE_VECFUNC("fmaf", "armpl_vfmaq_f32", FIXED(4), NOMASK, "_ZGV_LLVM_N4vvv TLI_DEFINE_VECFUNC("fma", "armpl_svfma_f64_x", SCALABLE(2), MASKED, "_ZGVsMxvvv") TLI_DEFINE_VECFUNC("fmaf", "armpl_svfma_f32_x", SCALABLE(4), MASKED, "_ZGVsMxvvv") +TLI_DEFINE_VECFUNC("fmax", "armpl_vfmaxq_f64", FIXED(2), NOMASK, "_ZGV_LLVM_N2vv") +TLI_DEFINE_VECFUNC("fmaxf", "armpl_vfmaxq_f32", FIXED(4), NOMASK, "_ZGV_LLVM_N4vv") +TLI_DEFINE_VECFUNC("fmax", "armpl_svfmax_f64_x", SCALABLE(2), MASKED, "_ZGVsMxvv") +TLI_DEFINE_VECFUNC("fmaxf", "armpl_svfmax_f32_x", SCALABLE(4), MASKED, "_ZGVsMxvv") + TLI_DEFINE_VECFUNC("fmin", "armpl_vfminq_f64", FIXED(2), NOMASK, "_ZGV_LLVM_N2vv") TLI_DEFINE_VECFUNC("fminf", "armpl_vfminq_f32", FIXED(4), NOMASK, "_ZGV_LLVM_N4vv") TLI_DEFINE_VECFUNC("fmin", "armpl_svfmin_f64_x", SCALABLE(2), MASKED, "_ZGVsMxvv") @@ -817,6 +953,16 @@ TLI_DEFINE_VECFUNC("hypotf", "armpl_vhypotq_f32", FIXED(4), NOMASK, "_ZGV_LLVM_N TLI_DEFINE_VECFUNC("hypot", "armpl_svhypot_f64_x", SCALABLE(2), MASKED, "_ZGVsMxvv") TLI_DEFINE_VECFUNC("hypotf", "armpl_svhypot_f32_x", SCALABLE(4), MASKED, "_ZGVsMxvv") +TLI_DEFINE_VECFUNC("ilogb", "armpl_vilogbq_f64", FIXED(2), NOMASK, "_ZGV_LLVM_N2v") +TLI_DEFINE_VECFUNC("ilogbf", "armpl_vilogbq_f32", FIXED(4), NOMASK, "_ZGV_LLVM_N4v") +TLI_DEFINE_VECFUNC("ilogb", "armpl_svilogb_f64_x", SCALABLE(2), MASKED, "_ZGVsMxv") +TLI_DEFINE_VECFUNC("ilogbf", "armpl_svilogb_f32_x", SCALABLE(4), MASKED, "_ZGVsMxv") + +TLI_DEFINE_VECFUNC("ldexp", "armpl_vldexpq_f64", FIXED(2), NOMASK, "_ZGV_LLVM_N2vv") +TLI_DEFINE_VECFUNC("ldexpf", "armpl_vldexpq_f32", FIXED(4), NOMASK, "_ZGV_LLVM_N4vv") +TLI_DEFINE_VECFUNC("ldexp", "armpl_svldexp_f64_x", SCALABLE(2), MASKED, "_ZGVsMxvv") +TLI_DEFINE_VECFUNC("ldexpf", "armpl_svldexp_f32_x", SCALABLE(4), MASKED, "_ZGVsMxvv") + TLI_DEFINE_VECFUNC("lgamma", "armpl_vlgammaq_f64", FIXED(2), NOMASK, "_ZGV_LLVM_N2v") TLI_DEFINE_VECFUNC("lgammaf", "armpl_vlgammaq_f32", FIXED(4), NOMASK, "_ZGV_LLVM_N4v") TLI_DEFINE_VECFUNC("lgamma", "armpl_svlgamma_f64_x", SCALABLE(2), MASKED, "_ZGVsMxv") diff --git a/llvm/include/llvm/Analysis/VectorUtils.h b/llvm/include/llvm/Analysis/VectorUtils.h index b1ecc8777c1..7a92e62b53c 100644 --- a/llvm/include/llvm/Analysis/VectorUtils.h +++ b/llvm/include/llvm/Analysis/VectorUtils.h @@ -16,197 +16,12 @@ #include "llvm/ADT/MapVector.h" #include "llvm/ADT/SmallVector.h" #include "llvm/Analysis/LoopAccessAnalysis.h" +#include "llvm/IR/VFABIDemangler.h" #include "llvm/Support/CheckedArithmetic.h" namespace llvm { class TargetLibraryInfo; -/// Describes the type of Parameters -enum class VFParamKind { - Vector, // No semantic information. - OMP_Linear, // declare simd linear(i) - OMP_LinearRef, // declare simd linear(ref(i)) - OMP_LinearVal, // declare simd linear(val(i)) - OMP_LinearUVal, // declare simd linear(uval(i)) - OMP_LinearPos, // declare simd linear(i:c) uniform(c) - OMP_LinearValPos, // declare simd linear(val(i:c)) uniform(c) - OMP_LinearRefPos, // declare simd linear(ref(i:c)) uniform(c) - OMP_LinearUValPos, // declare simd linear(uval(i:c)) uniform(c) - OMP_Uniform, // declare simd uniform(i) - GlobalPredicate, // Global logical predicate that acts on all lanes - // of the input and output mask concurrently. For - // example, it is implied by the `M` token in the - // Vector Function ABI mangled name. - Unknown -}; - -/// Describes the type of Instruction Set Architecture -enum class VFISAKind { - AdvancedSIMD, // AArch64 Advanced SIMD (NEON) - SVE, // AArch64 Scalable Vector Extension - SSE, // x86 SSE - AVX, // x86 AVX - AVX2, // x86 AVX2 - AVX512, // x86 AVX512 - LLVM, // LLVM internal ISA for functions that are not - // attached to an existing ABI via name mangling. - Unknown // Unknown ISA -}; - -/// Encapsulates information needed to describe a parameter. -/// -/// The description of the parameter is not linked directly to -/// OpenMP or any other vector function description. This structure -/// is extendible to handle other paradigms that describe vector -/// functions and their parameters. -struct VFParameter { - unsigned ParamPos; // Parameter Position in Scalar Function. - VFParamKind ParamKind; // Kind of Parameter. - int LinearStepOrPos = 0; // Step or Position of the Parameter. - Align Alignment = Align(); // Optional alignment in bytes, defaulted to 1. - - // Comparison operator. - bool operator==(const VFParameter &Other) const { - return std::tie(ParamPos, ParamKind, LinearStepOrPos, Alignment) == - std::tie(Other.ParamPos, Other.ParamKind, Other.LinearStepOrPos, - Other.Alignment); - } -}; - -/// Contains the information about the kind of vectorization -/// available. -/// -/// This object in independent on the paradigm used to -/// represent vector functions. in particular, it is not attached to -/// any target-specific ABI. -struct VFShape { - ElementCount VF; // Vectorization factor. - SmallVector Parameters; // List of parameter information. - // Comparison operator. - bool operator==(const VFShape &Other) const { - return std::tie(VF, Parameters) == std::tie(Other.VF, Other.Parameters); - } - - /// Update the parameter in position P.ParamPos to P. - void updateParam(VFParameter P) { - assert(P.ParamPos < Parameters.size() && "Invalid parameter position."); - Parameters[P.ParamPos] = P; - assert(hasValidParameterList() && "Invalid parameter list"); - } - - /// Retrieve the VFShape that can be used to map a scalar function to itself, - /// with VF = 1. - static VFShape getScalarShape(const FunctionType *FTy) { - return VFShape::get(FTy, ElementCount::getFixed(1), - /*HasGlobalPredicate*/ false); - } - - /// Retrieve the basic vectorization shape of the function, where all - /// parameters are mapped to VFParamKind::Vector with \p EC lanes. Specifies - /// whether the function has a Global Predicate argument via \p HasGlobalPred. - static VFShape get(const FunctionType *FTy, ElementCount EC, - bool HasGlobalPred) { - SmallVector Parameters; - for (unsigned I = 0; I < FTy->getNumParams(); ++I) - Parameters.push_back(VFParameter({I, VFParamKind::Vector})); - if (HasGlobalPred) - Parameters.push_back( - VFParameter({FTy->getNumParams(), VFParamKind::GlobalPredicate})); - - return {EC, Parameters}; - } - /// Validation check on the Parameters in the VFShape. - bool hasValidParameterList() const; -}; - -/// Holds the VFShape for a specific scalar to vector function mapping. -struct VFInfo { - VFShape Shape; /// Classification of the vector function. - std::string ScalarName; /// Scalar Function Name. - std::string VectorName; /// Vector Function Name associated to this VFInfo. - VFISAKind ISA; /// Instruction Set Architecture. - - /// Returns the index of the first parameter with the kind 'GlobalPredicate', - /// if any exist. - std::optional getParamIndexForOptionalMask() const { - unsigned ParamCount = Shape.Parameters.size(); - for (unsigned i = 0; i < ParamCount; ++i) - if (Shape.Parameters[i].ParamKind == VFParamKind::GlobalPredicate) - return i; - - return std::nullopt; - } - - /// Returns true if at least one of the operands to the vectorized function - /// has the kind 'GlobalPredicate'. - bool isMasked() const { return getParamIndexForOptionalMask().has_value(); } -}; - -namespace VFABI { -/// LLVM Internal VFABI ISA token for vector functions. -static constexpr char const *_LLVM_ = "_LLVM_"; -/// Prefix for internal name redirection for vector function that -/// tells the compiler to scalarize the call using the scalar name -/// of the function. For example, a mangled name like -/// `_ZGV_LLVM_N2v_foo(_LLVM_Scalarize_foo)` would tell the -/// vectorizer to vectorize the scalar call `foo`, and to scalarize -/// it once vectorization is done. -static constexpr char const *_LLVM_Scalarize_ = "_LLVM_Scalarize_"; - -/// Function to construct a VFInfo out of a mangled names in the -/// following format: -/// -/// {()} -/// -/// where is the name of the vector function, mangled according -/// to the rules described in the Vector Function ABI of the target vector -/// extension (or from now on). The is in the following -/// format: -/// -/// _ZGV_[()] -/// -/// This methods support demangling rules for the following : -/// -/// * AArch64: https://developer.arm.com/docs/101129/latest -/// -/// * x86 (libmvec): https://sourceware.org/glibc/wiki/libmvec and -/// https://sourceware.org/glibc/wiki/libmvec?action=AttachFile&do=view&target=VectorABI.txt -/// -/// \param MangledName -> input string in the format -/// _ZGV_[()]. -/// \param FTy -> FunctionType of the scalar function which we're trying to find -/// a vectorized variant for. This is required to determine the vectorization -/// factor for scalable vectors, since the mangled name doesn't encode that; -/// it needs to be derived from the widest element types of vector arguments -/// or return values. -std::optional tryDemangleForVFABI(StringRef MangledName, - const FunctionType *FTy); - -/// Retrieve the `VFParamKind` from a string token. -VFParamKind getVFParamKindFromString(const StringRef Token); - -// Name of the attribute where the variant mappings are stored. -static constexpr char const *MappingsAttrName = "vector-function-abi-variant"; - -/// Populates a set of strings representing the Vector Function ABI variants -/// associated to the CallInst CI. If the CI does not contain the -/// vector-function-abi-variant attribute, we return without populating -/// VariantMappings, i.e. callers of getVectorVariantNames need not check for -/// the presence of the attribute (see InjectTLIMappings). -void getVectorVariantNames(const CallInst &CI, - SmallVectorImpl &VariantMappings); - -/// Constructs a FunctionType by applying vector function information to the -/// type of a matching scalar function. -/// \param Info gets the vectorization factor (VF) and the VFParamKind of the -/// parameters. -/// \param ScalarFTy gets the Type information of parameters, as it is not -/// stored in \p Info. -/// \returns a pointer to a newly created vector FunctionType -FunctionType *createFunctionType(const VFInfo &Info, - const FunctionType *ScalarFTy); -} // end namespace VFABI - /// The Vector Function Database. /// /// Helper class used to find the vector functions associated to a diff --git a/llvm/include/llvm/AsmParser/LLParser.h b/llvm/include/llvm/AsmParser/LLParser.h index 54bc3e582e0..cf358c384f5 100644 --- a/llvm/include/llvm/AsmParser/LLParser.h +++ b/llvm/include/llvm/AsmParser/LLParser.h @@ -203,6 +203,9 @@ namespace llvm { bool error(LocTy L, const Twine &Msg) const { return Lex.Error(L, Msg); } bool tokError(const Twine &Msg) const { return error(Lex.getLoc(), Msg); } + bool checkValueID(LocTy L, StringRef Kind, StringRef Prefix, + unsigned NextID, unsigned ID) const; + /// Restore the internal name and slot mappings using the mappings that /// were created at an earlier parsing stage. void restoreParsingState(const SlotMapping *Slots); @@ -328,6 +331,7 @@ namespace llvm { // Top-Level Entities bool parseTopLevelEntities(); + void dropUnknownMetadataReferences(); bool validateEndOfModule(bool UpgradeDebugInfo); bool validateEndOfIndex(); bool parseTargetDefinitions(DataLayoutCallbackTy DataLayoutCallback); @@ -448,19 +452,35 @@ namespace llvm { bool parseFunctionType(Type *&Result); bool parseTargetExtType(Type *&Result); + class NumberedValues { + DenseMap Vals; + unsigned NextUnusedID = 0; + + public: + unsigned getNext() const { return NextUnusedID; } + Value *get(unsigned ID) const { return Vals.lookup(ID); } + void add(unsigned ID, Value *V) { + assert(ID >= NextUnusedID && "Invalid value ID"); + Vals.insert({ID, V}); + NextUnusedID = ID + 1; + } + }; + // Function Semantic Analysis. class PerFunctionState { LLParser &P; Function &F; std::map > ForwardRefVals; std::map > ForwardRefValIDs; - std::vector NumberedVals; + NumberedValues NumberedVals; /// FunctionNumber - If this is an unnamed function, this is the slot /// number of it, otherwise it is -1. int FunctionNumber; + public: - PerFunctionState(LLParser &p, Function &f, int functionNumber); + PerFunctionState(LLParser &p, Function &f, int functionNumber, + ArrayRef UnnamedArgNums); ~PerFunctionState(); Function &getFunction() const { return F; } @@ -590,9 +610,12 @@ namespace llvm { ArgInfo(LocTy L, Type *ty, AttributeSet Attr, const std::string &N) : Loc(L), Ty(ty), Attrs(Attr), Name(N) {} }; - bool parseArgumentList(SmallVectorImpl &ArgList, bool &IsVarArg); - bool parseFunctionHeader(Function *&Fn, bool IsDefine); - bool parseFunctionBody(Function &Fn); + bool parseArgumentList(SmallVectorImpl &ArgList, + SmallVectorImpl &UnnamedArgNums, + bool &IsVarArg); + bool parseFunctionHeader(Function *&Fn, bool IsDefine, + SmallVectorImpl &UnnamedArgNums); + bool parseFunctionBody(Function &Fn, ArrayRef UnnamedArgNums); bool parseBasicBlock(PerFunctionState &PFS); enum TailCallType { TCT_None, TCT_Tail, TCT_MustTail }; diff --git a/llvm/include/llvm/BinaryFormat/ELF.h b/llvm/include/llvm/BinaryFormat/ELF.h index 9b8128a9ec4..81cdd39afc6 100644 --- a/llvm/include/llvm/BinaryFormat/ELF.h +++ b/llvm/include/llvm/BinaryFormat/ELF.h @@ -787,6 +787,8 @@ enum : unsigned { EF_AMDGPU_MACH_AMDGCN_GFX942 = 0x04c, EF_AMDGPU_MACH_AMDGCN_RESERVED_0X4D = 0x04d, EF_AMDGPU_MACH_AMDGCN_GFX1201 = 0x04e, + EF_AMDGPU_MACH_AMDGCN_RESERVED_0X4F = 0x04f, + EF_AMDGPU_MACH_AMDGCN_RESERVED_0X50 = 0x050, // clang-format on // First/last AMDGCN-based processors. diff --git a/llvm/include/llvm/BinaryFormat/ELFRelocs/RISCV.def b/llvm/include/llvm/BinaryFormat/ELFRelocs/RISCV.def index b478799c91f..d4be34e3b37 100644 --- a/llvm/include/llvm/BinaryFormat/ELFRelocs/RISCV.def +++ b/llvm/include/llvm/BinaryFormat/ELFRelocs/RISCV.def @@ -15,6 +15,7 @@ ELF_RELOC(R_RISCV_TLS_DTPREL32, 8) ELF_RELOC(R_RISCV_TLS_DTPREL64, 9) ELF_RELOC(R_RISCV_TLS_TPREL32, 10) ELF_RELOC(R_RISCV_TLS_TPREL64, 11) +ELF_RELOC(R_RISCV_TLSDESC, 12) ELF_RELOC(R_RISCV_BRANCH, 16) ELF_RELOC(R_RISCV_JAL, 17) ELF_RELOC(R_RISCV_CALL, 18) @@ -56,3 +57,7 @@ ELF_RELOC(R_RISCV_IRELATIVE, 58) ELF_RELOC(R_RISCV_PLT32, 59) ELF_RELOC(R_RISCV_SET_ULEB128, 60) ELF_RELOC(R_RISCV_SUB_ULEB128, 61) +ELF_RELOC(R_RISCV_TLSDESC_HI20, 62) +ELF_RELOC(R_RISCV_TLSDESC_LOAD_LO12, 63) +ELF_RELOC(R_RISCV_TLSDESC_ADD_LO12, 64) +ELF_RELOC(R_RISCV_TLSDESC_CALL, 65) diff --git a/llvm/include/llvm/BinaryFormat/MachO.def b/llvm/include/llvm/BinaryFormat/MachO.def index df527b4a8ab..4124c723ec0 100644 --- a/llvm/include/llvm/BinaryFormat/MachO.def +++ b/llvm/include/llvm/BinaryFormat/MachO.def @@ -133,6 +133,8 @@ PLATFORM(IOSSIMULATOR, 7, iossimulator, iossimulator, ios-simulator, ios-simulat PLATFORM(TVOSSIMULATOR, 8, tvossimulator, tvossimulator, tvos-simulator, tvos-simulator, tvOS Simulator) PLATFORM(WATCHOSSIMULATOR, 9, watchossimulator, watchossimulator, watchos-simulator, watchos-simulator, watchOS Simulator) PLATFORM(DRIVERKIT, 10, driverkit, driverkit, driverkit, driverkit, DriverKit) +PLATFORM(XROS, 11, xros, xros, xros, xros, xrOS) +PLATFORM(XROS_SIMULATOR, 12, xrsimulator, xrsimulator, xrsimulator, xros-simulator, xrOS Simulator) #endif #undef HANDLE_LOAD_COMMAND diff --git a/llvm/include/llvm/BinaryFormat/Magic.h b/llvm/include/llvm/BinaryFormat/Magic.h index c635a269576..6978c066bda 100644 --- a/llvm/include/llvm/BinaryFormat/Magic.h +++ b/llvm/include/llvm/BinaryFormat/Magic.h @@ -21,6 +21,7 @@ struct file_magic { enum Impl { unknown = 0, ///< Unrecognized file bitcode, ///< Bitcode file + clang_ast, ///< Clang PCH or PCM archive, ///< ar style archive file elf, ///< ELF Unknown type elf_relocatable, ///< ELF Relocatable object file diff --git a/llvm/include/llvm/BinaryFormat/Wasm.h b/llvm/include/llvm/BinaryFormat/Wasm.h index c7658cc7b74..c6f83753136 100644 --- a/llvm/include/llvm/BinaryFormat/Wasm.h +++ b/llvm/include/llvm/BinaryFormat/Wasm.h @@ -31,213 +31,6 @@ const uint32_t WasmMetadataVersion = 0x2; // Wasm uses a 64k page size const uint32_t WasmPageSize = 65536; -struct WasmObjectHeader { - StringRef Magic; - uint32_t Version; -}; - -struct WasmDylinkImportInfo { - StringRef Module; - StringRef Field; - uint32_t Flags; -}; - -struct WasmDylinkExportInfo { - StringRef Name; - uint32_t Flags; -}; - -struct WasmDylinkInfo { - uint32_t MemorySize; // Memory size in bytes - uint32_t MemoryAlignment; // P2 alignment of memory - uint32_t TableSize; // Table size in elements - uint32_t TableAlignment; // P2 alignment of table - std::vector Needed; // Shared library dependencies - std::vector ImportInfo; - std::vector ExportInfo; -}; - -struct WasmProducerInfo { - std::vector> Languages; - std::vector> Tools; - std::vector> SDKs; -}; - -struct WasmFeatureEntry { - uint8_t Prefix; - std::string Name; -}; - -struct WasmExport { - StringRef Name; - uint8_t Kind; - uint32_t Index; -}; - -struct WasmLimits { - uint8_t Flags; - uint64_t Minimum; - uint64_t Maximum; -}; - -struct WasmTableType { - uint8_t ElemType; - WasmLimits Limits; -}; - -struct WasmTable { - uint32_t Index; - WasmTableType Type; - StringRef SymbolName; // from the "linking" section -}; - -struct WasmInitExprMVP { - uint8_t Opcode; - union { - int32_t Int32; - int64_t Int64; - uint32_t Float32; - uint64_t Float64; - uint32_t Global; - } Value; -}; - -struct WasmInitExpr { - uint8_t Extended; // Set to non-zero if extended const is used (i.e. more than - // one instruction) - WasmInitExprMVP Inst; - ArrayRef Body; -}; - -struct WasmGlobalType { - uint8_t Type; - bool Mutable; -}; - -struct WasmGlobal { - uint32_t Index; - WasmGlobalType Type; - WasmInitExpr InitExpr; - StringRef SymbolName; // from the "linking" section -}; - -struct WasmTag { - uint32_t Index; - uint32_t SigIndex; - StringRef SymbolName; // from the "linking" section -}; - -struct WasmImport { - StringRef Module; - StringRef Field; - uint8_t Kind; - union { - uint32_t SigIndex; - WasmGlobalType Global; - WasmTableType Table; - WasmLimits Memory; - }; -}; - -struct WasmLocalDecl { - uint8_t Type; - uint32_t Count; -}; - -struct WasmFunction { - uint32_t Index; - uint32_t SigIndex; - std::vector Locals; - ArrayRef Body; - uint32_t CodeSectionOffset; - uint32_t Size; - uint32_t CodeOffset; // start of Locals and Body - std::optional ExportName; // from the "export" section - StringRef SymbolName; // from the "linking" section - StringRef DebugName; // from the "name" section - uint32_t Comdat; // from the "comdat info" section -}; - -struct WasmDataSegment { - uint32_t InitFlags; - // Present if InitFlags & WASM_DATA_SEGMENT_HAS_MEMINDEX. - uint32_t MemoryIndex; - // Present if InitFlags & WASM_DATA_SEGMENT_IS_PASSIVE == 0. - WasmInitExpr Offset; - - ArrayRef Content; - StringRef Name; // from the "segment info" section - uint32_t Alignment; - uint32_t LinkingFlags; - uint32_t Comdat; // from the "comdat info" section -}; - -struct WasmElemSegment { - uint32_t Flags; - uint32_t TableNumber; - uint8_t ElemKind; - WasmInitExpr Offset; - std::vector Functions; -}; - -// Represents the location of a Wasm data symbol within a WasmDataSegment, as -// the index of the segment, and the offset and size within the segment. -struct WasmDataReference { - uint32_t Segment; - uint64_t Offset; - uint64_t Size; -}; - -struct WasmRelocation { - uint8_t Type; // The type of the relocation. - uint32_t Index; // Index into either symbol or type index space. - uint64_t Offset; // Offset from the start of the section. - int64_t Addend; // A value to add to the symbol. -}; - -struct WasmInitFunc { - uint32_t Priority; - uint32_t Symbol; -}; - -struct WasmSymbolInfo { - StringRef Name; - uint8_t Kind; - uint32_t Flags; - // For undefined symbols the module of the import - std::optional ImportModule; - // For undefined symbols the name of the import - std::optional ImportName; - // For symbols to be exported from the final module - std::optional ExportName; - union { - // For function, table, or global symbols, the index in function, table, or - // global index space. - uint32_t ElementIndex; - // For a data symbols, the address of the data relative to segment. - WasmDataReference DataRef; - }; -}; - -enum class NameType { - FUNCTION, - GLOBAL, - DATA_SEGMENT, -}; - -struct WasmDebugName { - NameType Type; - uint32_t Index; - StringRef Name; -}; - -struct WasmLinkingData { - uint32_t Version; - std::vector InitFunctions; - std::vector Comdats; - std::vector SymbolTable; -}; - enum : unsigned { WASM_SEC_CUSTOM = 0, // Custom / User-defined section WASM_SEC_TYPE = 1, // Function signature declarations @@ -422,6 +215,11 @@ enum : unsigned { #undef WASM_RELOC +struct WasmObjectHeader { + StringRef Magic; + uint32_t Version; +}; + // Subset of types that a value can have enum class ValType { I32 = WASM_TYPE_I32, @@ -433,6 +231,208 @@ enum class ValType { EXTERNREF = WASM_TYPE_EXTERNREF, }; +struct WasmDylinkImportInfo { + StringRef Module; + StringRef Field; + uint32_t Flags; +}; + +struct WasmDylinkExportInfo { + StringRef Name; + uint32_t Flags; +}; + +struct WasmDylinkInfo { + uint32_t MemorySize; // Memory size in bytes + uint32_t MemoryAlignment; // P2 alignment of memory + uint32_t TableSize; // Table size in elements + uint32_t TableAlignment; // P2 alignment of table + std::vector Needed; // Shared library dependencies + std::vector ImportInfo; + std::vector ExportInfo; +}; + +struct WasmProducerInfo { + std::vector> Languages; + std::vector> Tools; + std::vector> SDKs; +}; + +struct WasmFeatureEntry { + uint8_t Prefix; + std::string Name; +}; + +struct WasmExport { + StringRef Name; + uint8_t Kind; + uint32_t Index; +}; + +struct WasmLimits { + uint8_t Flags; + uint64_t Minimum; + uint64_t Maximum; +}; + +struct WasmTableType { + ValType ElemType; + WasmLimits Limits; +}; + +struct WasmTable { + uint32_t Index; + WasmTableType Type; + StringRef SymbolName; // from the "linking" section +}; + +struct WasmInitExprMVP { + uint8_t Opcode; + union { + int32_t Int32; + int64_t Int64; + uint32_t Float32; + uint64_t Float64; + uint32_t Global; + } Value; +}; + +struct WasmInitExpr { + uint8_t Extended; // Set to non-zero if extended const is used (i.e. more than + // one instruction) + WasmInitExprMVP Inst; + ArrayRef Body; +}; + +struct WasmGlobalType { + uint8_t Type; // TODO: make this a ValType? + bool Mutable; +}; + +struct WasmGlobal { + uint32_t Index; + WasmGlobalType Type; + WasmInitExpr InitExpr; + StringRef SymbolName; // from the "linking" section +}; + +struct WasmTag { + uint32_t Index; + uint32_t SigIndex; + StringRef SymbolName; // from the "linking" section +}; + +struct WasmImport { + StringRef Module; + StringRef Field; + uint8_t Kind; + union { + uint32_t SigIndex; + WasmGlobalType Global; + WasmTableType Table; + WasmLimits Memory; + }; +}; + +struct WasmLocalDecl { + uint8_t Type; + uint32_t Count; +}; + +struct WasmFunction { + uint32_t Index; + uint32_t SigIndex; + std::vector Locals; + ArrayRef Body; + uint32_t CodeSectionOffset; + uint32_t Size; + uint32_t CodeOffset; // start of Locals and Body + std::optional ExportName; // from the "export" section + StringRef SymbolName; // from the "linking" section + StringRef DebugName; // from the "name" section + uint32_t Comdat; // from the "comdat info" section +}; + +struct WasmDataSegment { + uint32_t InitFlags; + // Present if InitFlags & WASM_DATA_SEGMENT_HAS_MEMINDEX. + uint32_t MemoryIndex; + // Present if InitFlags & WASM_DATA_SEGMENT_IS_PASSIVE == 0. + WasmInitExpr Offset; + + ArrayRef Content; + StringRef Name; // from the "segment info" section + uint32_t Alignment; + uint32_t LinkingFlags; + uint32_t Comdat; // from the "comdat info" section +}; + +struct WasmElemSegment { + uint32_t Flags; + uint32_t TableNumber; + ValType ElemKind; + WasmInitExpr Offset; + std::vector Functions; +}; + +// Represents the location of a Wasm data symbol within a WasmDataSegment, as +// the index of the segment, and the offset and size within the segment. +struct WasmDataReference { + uint32_t Segment; + uint64_t Offset; + uint64_t Size; +}; + +struct WasmRelocation { + uint8_t Type; // The type of the relocation. + uint32_t Index; // Index into either symbol or type index space. + uint64_t Offset; // Offset from the start of the section. + int64_t Addend; // A value to add to the symbol. +}; + +struct WasmInitFunc { + uint32_t Priority; + uint32_t Symbol; +}; + +struct WasmSymbolInfo { + StringRef Name; + uint8_t Kind; + uint32_t Flags; + // For undefined symbols the module of the import + std::optional ImportModule; + // For undefined symbols the name of the import + std::optional ImportName; + // For symbols to be exported from the final module + std::optional ExportName; + union { + // For function, table, or global symbols, the index in function, table, or + // global index space. + uint32_t ElementIndex; + // For a data symbols, the address of the data relative to segment. + WasmDataReference DataRef; + }; +}; + +enum class NameType { + FUNCTION, + GLOBAL, + DATA_SEGMENT, +}; + +struct WasmDebugName { + NameType Type; + uint32_t Index; + StringRef Name; +}; + +struct WasmLinkingData { + uint32_t Version; + std::vector InitFunctions; + std::vector Comdats; + std::vector SymbolTable; +}; + struct WasmSignature { SmallVector Returns; SmallVector Params; diff --git a/llvm/include/llvm/BinaryFormat/WasmTraits.h b/llvm/include/llvm/BinaryFormat/WasmTraits.h index bef9dd3291c..8167dab01c1 100644 --- a/llvm/include/llvm/BinaryFormat/WasmTraits.h +++ b/llvm/include/llvm/BinaryFormat/WasmTraits.h @@ -87,11 +87,12 @@ template <> struct DenseMapInfo { template <> struct DenseMapInfo { static wasm::WasmTableType getEmptyKey() { return wasm::WasmTableType{ - 0, DenseMapInfo::getEmptyKey()}; + wasm::ValType(0), DenseMapInfo::getEmptyKey()}; } static wasm::WasmTableType getTombstoneKey() { return wasm::WasmTableType{ - 1, DenseMapInfo::getTombstoneKey()}; + wasm::ValType(1), + DenseMapInfo::getTombstoneKey()}; } static unsigned getHashValue(const wasm::WasmTableType &TableType) { return hash_combine( diff --git a/llvm/include/llvm/Bitcode/BitcodeWriterPass.h b/llvm/include/llvm/Bitcode/BitcodeWriterPass.h index 3c247123753..4035c00b679 100644 --- a/llvm/include/llvm/Bitcode/BitcodeWriterPass.h +++ b/llvm/include/llvm/Bitcode/BitcodeWriterPass.h @@ -28,16 +28,8 @@ class raw_ostream; /// /// If \c ShouldPreserveUseListOrder, encode use-list order so it can be /// reproduced when deserialized. -/// -/// If \c EmitSummaryIndex, emit the summary index (currently for use in ThinLTO -/// optimization). -/// -/// If \c EmitModuleHash, compute and emit the module hash in the bitcode -/// (currently for use in ThinLTO incremental build). ModulePass *createBitcodeWriterPass(raw_ostream &Str, - bool ShouldPreserveUseListOrder = false, - bool EmitSummaryIndex = false, - bool EmitModuleHash = false); + bool ShouldPreserveUseListOrder = false); /// Check whether a pass is a BitcodeWriterPass. bool isBitcodeWriterPass(Pass *P); diff --git a/llvm/include/llvm/CodeGen/AccelTable.h b/llvm/include/llvm/CodeGen/AccelTable.h index 0638fbffda4..e6a66169635 100644 --- a/llvm/include/llvm/CodeGen/AccelTable.h +++ b/llvm/include/llvm/CodeGen/AccelTable.h @@ -255,6 +255,20 @@ public: static uint32_t hash(StringRef Buffer) { return djbHash(Buffer); } }; +/// Helper class to identify an entry in DWARF5AccelTable based on their DIE +/// offset and UnitID. +struct OffsetAndUnitID : std::pair { + using Base = std::pair; + OffsetAndUnitID(Base B) : Base(B) {} + + OffsetAndUnitID(uint64_t Offset, uint32_t UnitID) : Base(Offset, UnitID) {} + uint64_t offset() const { return first; }; + uint32_t unitID() const { return second; }; +}; + +template <> +struct DenseMapInfo : DenseMapInfo {}; + /// The Data class implementation for DWARF v5 accelerator table. Unlike the /// Apple Data classes, this class is just a DIE wrapper, and does not know to /// serialize itself. The complete serialization logic is in the @@ -270,9 +284,12 @@ public: DWARF5AccelTableData(const DIE &Die, const uint32_t UnitID, const bool IsTU = false); - DWARF5AccelTableData(const uint64_t DieOffset, const unsigned DieTag, - const unsigned UnitID, const bool IsTU = false) - : OffsetVal(DieOffset), DieTag(DieTag), UnitID(UnitID), IsTU(IsTU) {} + DWARF5AccelTableData(const uint64_t DieOffset, + const std::optional DefiningParentOffset, + const unsigned DieTag, const unsigned UnitID, + const bool IsTU = false) + : OffsetVal(DieOffset), ParentOffset(DefiningParentOffset), + DieTag(DieTag), UnitID(UnitID), IsTU(IsTU) {} #ifndef NDEBUG void print(raw_ostream &OS) const override; @@ -282,19 +299,44 @@ public: assert(isNormalized() && "Accessing DIE Offset before normalizing."); return std::get(OffsetVal); } + + OffsetAndUnitID getDieOffsetAndUnitID() const { + return {getDieOffset(), UnitID}; + } + unsigned getDieTag() const { return DieTag; } unsigned getUnitID() const { return UnitID; } bool isTU() const { return IsTU; } void normalizeDIEToOffset() { assert(!isNormalized() && "Accessing offset after normalizing."); - OffsetVal = std::get(OffsetVal)->getOffset(); + const DIE *Entry = std::get(OffsetVal); + ParentOffset = getDefiningParentDieOffset(*Entry); + OffsetVal = Entry->getOffset(); } bool isNormalized() const { return std::holds_alternative(OffsetVal); } + std::optional getParentDieOffset() const { + if (auto OffsetAndId = getParentDieOffsetAndUnitID()) + return OffsetAndId->offset(); + return {}; + } + + std::optional getParentDieOffsetAndUnitID() const { + assert(isNormalized() && "Accessing DIE Offset before normalizing."); + if (!ParentOffset) + return std::nullopt; + return OffsetAndUnitID(*ParentOffset, getUnitID()); + } + + /// If `Die` has a non-null parent and the parent is not a declaration, + /// return its offset. + static std::optional getDefiningParentDieOffset(const DIE &Die); + protected: std::variant OffsetVal; + std::optional ParentOffset; uint32_t DieTag : 16; uint32_t UnitID : 15; uint32_t IsTU : 1; @@ -341,7 +383,8 @@ public: void addTypeEntries(DWARF5AccelTable &Table) { for (auto &Entry : Table.getEntries()) { for (auto *Data : Entry.second.getValues()) { - addName(Entry.second.Name, Data->getDieOffset(), Data->getDieTag(), + addName(Entry.second.Name, Data->getDieOffset(), + Data->getParentDieOffset(), Data->getDieTag(), Data->getUnitID(), true); } } diff --git a/llvm/include/llvm/CodeGen/AsmPrinter.h b/llvm/include/llvm/CodeGen/AsmPrinter.h index 5ec246ee701..fbd198a75a2 100644 --- a/llvm/include/llvm/CodeGen/AsmPrinter.h +++ b/llvm/include/llvm/CodeGen/AsmPrinter.h @@ -236,10 +236,6 @@ private: /// split stack prologue. bool HasNoSplitStack = false; - /// Raw FDOstream for outputting machine basic block frequncies if the - /// --mbb-profile-dump flag is set for downstream cost modelling applications - std::unique_ptr MBBProfileDumpFileOutput; - protected: explicit AsmPrinter(TargetMachine &TM, std::unique_ptr Streamer); diff --git a/llvm/include/llvm/CodeGen/CodeGenPassBuilder.h b/llvm/include/llvm/CodeGen/CodeGenPassBuilder.h index f540f3774c4..96d6f891af4 100644 --- a/llvm/include/llvm/CodeGen/CodeGenPassBuilder.h +++ b/llvm/include/llvm/CodeGen/CodeGenPassBuilder.h @@ -30,6 +30,7 @@ #include "llvm/CodeGen/ExpandMemCmp.h" #include "llvm/CodeGen/ExpandReductions.h" #include "llvm/CodeGen/GCMetadata.h" +#include "llvm/CodeGen/GlobalMerge.h" #include "llvm/CodeGen/IndirectBrExpand.h" #include "llvm/CodeGen/InterleavedAccess.h" #include "llvm/CodeGen/InterleavedLoadCombine.h" @@ -43,6 +44,7 @@ #include "llvm/CodeGen/ShadowStackGCLowering.h" #include "llvm/CodeGen/SjLjEHPrepare.h" #include "llvm/CodeGen/StackProtector.h" +#include "llvm/CodeGen/TargetPassConfig.h" #include "llvm/CodeGen/UnreachableBlockElim.h" #include "llvm/CodeGen/WasmEHPrepare.h" #include "llvm/CodeGen/WinEHPrepare.h" @@ -175,85 +177,80 @@ protected: // Function object to maintain state while adding codegen IR passes. class AddIRPass { public: - AddIRPass(ModulePassManager &MPM, bool DebugPM, bool Check = true) - : MPM(MPM) { - if (Check) - AddingFunctionPasses = false; - } + AddIRPass(ModulePassManager &MPM, const DerivedT &PB) : MPM(MPM), PB(PB) {} ~AddIRPass() { - MPM.addPass(createModuleToFunctionPassAdaptor(std::move(FPM))); + if (!FPM.isEmpty()) + MPM.addPass(createModuleToFunctionPassAdaptor(std::move(FPM))); } - // Add Function Pass template - std::enable_if_t::value> - operator()(PassT &&Pass) { - if (AddingFunctionPasses && !*AddingFunctionPasses) - AddingFunctionPasses = true; - FPM.addPass(std::forward(Pass)); - } + void operator()(PassT &&Pass, StringRef Name = PassT::name()) { + static_assert((is_detected::value || + is_detected::value) && + "Only module pass and function pass are supported."); - // Add Module Pass - template - std::enable_if_t::value && - !is_detected::value> - operator()(PassT &&Pass) { - assert((!AddingFunctionPasses || !*AddingFunctionPasses) && - "could not add module pass after adding function pass"); - MPM.addPass(std::forward(Pass)); + if (!PB.runBeforeAdding(Name)) + return; + + // Add Function Pass + if constexpr (is_detected::value) { + FPM.addPass(std::forward(Pass)); + + for (auto &C : PB.AfterCallbacks) + C(Name); + } else { + // Add Module Pass + if (!FPM.isEmpty()) { + MPM.addPass(createModuleToFunctionPassAdaptor(std::move(FPM))); + FPM = FunctionPassManager(); + } + + MPM.addPass(std::forward(Pass)); + + for (auto &C : PB.AfterCallbacks) + C(Name); + } } private: ModulePassManager &MPM; FunctionPassManager FPM; - // The codegen IR pipeline are mostly function passes with the exceptions of - // a few loop and module passes. `AddingFunctionPasses` make sures that - // we could only add module passes at the beginning of the pipeline. Once - // we begin adding function passes, we could no longer add module passes. - // This special-casing introduces less adaptor passes. If we have the need - // of adding module passes after function passes, we could change the - // implementation to accommodate that. - std::optional AddingFunctionPasses; + const DerivedT &PB; }; // Function object to maintain state while adding codegen machine passes. class AddMachinePass { public: - AddMachinePass(MachineFunctionPassManager &PM) : PM(PM) {} + AddMachinePass(MachineFunctionPassManager &PM, const DerivedT &PB) + : PM(PM), PB(PB) {} template void operator()(PassT &&Pass) { static_assert( is_detected::value, "Machine function pass must define a static member variable `Key`."); - for (auto &C : BeforeCallbacks) - if (!C(&PassT::Key)) - return; + + if (!PB.runBeforeAdding(PassT::name())) + return; + PM.addPass(std::forward(Pass)); - for (auto &C : AfterCallbacks) - C(&PassT::Key); + + for (auto &C : PB.AfterCallbacks) + C(PassT::name()); } template void insertPass(MachinePassKey *ID, PassT Pass) { - AfterCallbacks.emplace_back( + PB.AfterCallbacks.emplace_back( [this, ID, Pass = std::move(Pass)](MachinePassKey *PassID) { if (PassID == ID) this->PM.addPass(std::move(Pass)); }); } - void disablePass(MachinePassKey *ID) { - BeforeCallbacks.emplace_back( - [ID](MachinePassKey *PassID) { return PassID != ID; }); - } - MachineFunctionPassManager releasePM() { return std::move(PM); } private: MachineFunctionPassManager &PM; - SmallVector, 4> - BeforeCallbacks; - SmallVector, 4> - AfterCallbacks; + const DerivedT &PB; }; LLVMTargetMachine &TM; @@ -292,6 +289,9 @@ protected: inconvertibleErrorCode()); } + /// Target can override this to add GlobalMergePass before all IR passes. + void addGlobalMergePass(AddIRPass &) const {} + /// Add passes that optimize instruction level parallelism for out-of-order /// targets. These passes are run while the machine code is still in SSA /// form, so they can use MachineTraceMetrics to control their heuristics. @@ -481,6 +481,25 @@ private: const DerivedT &derived() const { return static_cast(*this); } + + bool runBeforeAdding(StringRef Name) const { + bool ShouldAdd = true; + for (auto &C : BeforeCallbacks) + ShouldAdd &= C(Name); + return ShouldAdd; + } + + void setStartStopPasses(const TargetPassConfig::StartStopInfo &Info) const; + + Error verifyStartStop(const TargetPassConfig::StartStopInfo &Info) const; + + mutable SmallVector, 4> + BeforeCallbacks; + mutable SmallVector, 4> AfterCallbacks; + + /// Helper variable for `-start-before/-start-after/-stop-before/-stop-after` + mutable bool Started = true; + mutable bool Stopped = true; }; template @@ -488,13 +507,17 @@ Error CodeGenPassBuilder::buildPipeline( ModulePassManager &MPM, MachineFunctionPassManager &MFPM, raw_pwrite_stream &Out, raw_pwrite_stream *DwoOut, CodeGenFileType FileType) const { - AddIRPass addIRPass(MPM, Opt.DebugPM); + auto StartStopInfo = TargetPassConfig::getStartStopInfo(*PIC); + if (!StartStopInfo) + return StartStopInfo.takeError(); + setStartStopPasses(*StartStopInfo); + AddIRPass addIRPass(MPM, derived()); // `ProfileSummaryInfo` is always valid. addIRPass(RequireAnalysisPass()); addIRPass(RequireAnalysisPass()); addISelPasses(addIRPass); - AddMachinePass addPass(MFPM); + AddMachinePass addPass(MFPM, derived()); if (auto Err = addCoreISelPasses(addPass)) return std::move(Err); @@ -507,6 +530,68 @@ Error CodeGenPassBuilder::buildPipeline( }); addPass(FreeMachineFunctionPass()); + return verifyStartStop(*StartStopInfo); +} + +template +void CodeGenPassBuilder::setStartStopPasses( + const TargetPassConfig::StartStopInfo &Info) const { + if (!Info.StartPass.empty()) { + Started = false; + BeforeCallbacks.emplace_back([this, &Info, AfterFlag = Info.StartAfter, + Count = 0u](StringRef ClassName) mutable { + if (Count == Info.StartInstanceNum) { + if (AfterFlag) { + AfterFlag = false; + Started = true; + } + return Started; + } + + auto PassName = PIC->getPassNameForClassName(ClassName); + if (Info.StartPass == PassName && ++Count == Info.StartInstanceNum) + Started = !Info.StartAfter; + + return Started; + }); + } + + if (!Info.StopPass.empty()) { + Stopped = false; + BeforeCallbacks.emplace_back([this, &Info, AfterFlag = Info.StopAfter, + Count = 0u](StringRef ClassName) mutable { + if (Count == Info.StopInstanceNum) { + if (AfterFlag) { + AfterFlag = false; + Stopped = true; + } + return !Stopped; + } + + auto PassName = PIC->getPassNameForClassName(ClassName); + if (Info.StopPass == PassName && ++Count == Info.StopInstanceNum) + Stopped = !Info.StopAfter; + return !Stopped; + }); + } +} + +template +Error CodeGenPassBuilder::verifyStartStop( + const TargetPassConfig::StartStopInfo &Info) const { + if (Started && Stopped) + return Error::success(); + + if (!Started) + return make_error( + "Can't find start pass \"" + + PIC->getPassNameForClassName(Info.StartPass) + "\".", + std::make_error_code(std::errc::invalid_argument)); + if (!Stopped) + return make_error( + "Can't find stop pass \"" + + PIC->getPassNameForClassName(Info.StopPass) + "\".", + std::make_error_code(std::errc::invalid_argument)); return Error::success(); } @@ -605,6 +690,7 @@ CodeGenPassBuilder::getPassNameFromLegacyName(StringRef Name) const { template void CodeGenPassBuilder::addISelPasses(AddIRPass &addPass) const { + derived().addGlobalMergePass(addPass); if (TM.useEmulatedTLS()) addPass(LowerEmuTLSPass()); @@ -627,8 +713,8 @@ void CodeGenPassBuilder::addIRPasses(AddIRPass &addPass) const { // Run loop strength reduction before anything else. if (getOptLevel() != CodeGenOptLevel::None && !Opt.DisableLSR) { - addPass(createFunctionToLoopPassAdaptor( - LoopStrengthReducePass(), /*UseMemorySSA*/ true, Opt.DebugPM)); + addPass(createFunctionToLoopPassAdaptor(LoopStrengthReducePass(), + /*UseMemorySSA=*/true)); // FIXME: use -stop-after so we could remove PrintLSR if (Opt.PrintLSR) addPass(PrintFunctionPass(dbgs(), "\n\n*** Code after LSR ***\n")); @@ -647,9 +733,6 @@ void CodeGenPassBuilder::addIRPasses(AddIRPass &addPass) const { // Run GC lowering passes for builtin collectors // TODO: add a pass insertion point here addPass(GCLoweringPass()); - // FIXME: `ShadowStackGCLoweringPass` now is a - // module pass, so it will trigger assertion. - // See comment of `AddingFunctionPasses` addPass(ShadowStackGCLoweringPass()); addPass(LowerConstantIntrinsicsPass()); @@ -1030,30 +1113,13 @@ void CodeGenPassBuilder::addTargetRegisterAllocator( template void CodeGenPassBuilder::addRegAllocPass(AddMachinePass &addPass, bool Optimized) const { - if (Opt.RegAlloc == RegAllocType::Default) - // With no -regalloc= override, ask the target for a regalloc pass. - derived().addTargetRegisterAllocator(addPass, Optimized); - else if (Opt.RegAlloc == RegAllocType::Basic) - addPass(RABasicPass()); - else if (Opt.RegAlloc == RegAllocType::Fast) - addPass(RAFastPass()); - else if (Opt.RegAlloc == RegAllocType::Greedy) - addPass(RAGreedyPass()); - else if (Opt.RegAlloc == RegAllocType::PBQP) - addPass(RAPBQPPass()); - else - llvm_unreachable("unknonwn register allocator type"); + // TODO: Parse Opt.RegAlloc to add register allocator. } template Error CodeGenPassBuilder::addRegAssignmentFast( AddMachinePass &addPass) const { - if (Opt.RegAlloc != RegAllocType::Default && - Opt.RegAlloc != RegAllocType::Fast) - return make_error( - "Must use fast (default) register allocator for unoptimized regalloc.", - inconvertibleErrorCode()); - + // TODO: Ensure allocator is default or fast. addRegAllocPass(addPass, false); return Error::success(); } diff --git a/llvm/include/llvm/CodeGen/CommandFlags.h b/llvm/include/llvm/CodeGen/CommandFlags.h index 6407dde5bcd..bf166a63edb 100644 --- a/llvm/include/llvm/CodeGen/CommandFlags.h +++ b/llvm/include/llvm/CodeGen/CommandFlags.h @@ -117,6 +117,9 @@ unsigned getTLSSize(); bool getEmulatedTLS(); std::optional getExplicitEmulatedTLS(); +bool getEnableTLSDESC(); +std::optional getExplicitEnableTLSDESC(); + bool getUniqueSectionNames(); bool getUniqueBasicBlockSectionNames(); diff --git a/llvm/include/llvm/CodeGen/GlobalISel/CallLowering.h b/llvm/include/llvm/CodeGen/GlobalISel/CallLowering.h index ec0b3363f51..d123ab7d8e4 100644 --- a/llvm/include/llvm/CodeGen/GlobalISel/CallLowering.h +++ b/llvm/include/llvm/CodeGen/GlobalISel/CallLowering.h @@ -291,8 +291,8 @@ public: /// \p If the handler wants the assignments to be delayed until after /// mem loc assignments, then it sets \p Thunk to the thunk to do the /// assignment. - /// \return The number of \p VAs that have been assigned after the first - /// one, and which should therefore be skipped from further + /// \return The number of \p VAs that have been assigned including the + /// first one, and which should therefore be skipped from further /// processing. virtual unsigned assignCustomValue(ArgInfo &Arg, ArrayRef VAs, std::function *Thunk = nullptr) { diff --git a/llvm/include/llvm/CodeGen/GlobalISel/GenericMachineInstrs.h b/llvm/include/llvm/CodeGen/GlobalISel/GenericMachineInstrs.h index 14885d5f9d0..eabbe688a1c 100644 --- a/llvm/include/llvm/CodeGen/GlobalISel/GenericMachineInstrs.h +++ b/llvm/include/llvm/CodeGen/GlobalISel/GenericMachineInstrs.h @@ -114,6 +114,21 @@ public: } }; +/// Represents either G_INDEXED_LOAD, G_INDEXED_ZEXTLOAD or G_INDEXED_SEXTLOAD. +class GIndexedAnyExtLoad : public GIndexedLoad { +public: + static bool classof(const MachineInstr *MI) { + switch (MI->getOpcode()) { + case TargetOpcode::G_INDEXED_LOAD: + case TargetOpcode::G_INDEXED_ZEXTLOAD: + case TargetOpcode::G_INDEXED_SEXTLOAD: + return true; + default: + return false; + } + } +}; + /// Represents a G_ZEXTLOAD. class GIndexedZExtLoad : GIndexedExtLoad { public: @@ -564,11 +579,11 @@ public: /// Returns the number of incoming values. unsigned getNumIncomingValues() const { return (getNumOperands() - 1) / 2; } /// Returns the I'th incoming vreg. - Register getIncomingValue(unsigned I) { + Register getIncomingValue(unsigned I) const { return getOperand(I * 2 + 1).getReg(); } /// Returns the I'th incoming basic block. - MachineBasicBlock *getIncomingBlock(unsigned I) { + MachineBasicBlock *getIncomingBlock(unsigned I) const { return getOperand(I * 2 + 2).getMBB(); } diff --git a/llvm/include/llvm/CodeGen/GlobalISel/IRTranslator.h b/llvm/include/llvm/CodeGen/GlobalISel/IRTranslator.h index 1b094d9d9fe..5454df02914 100644 --- a/llvm/include/llvm/CodeGen/GlobalISel/IRTranslator.h +++ b/llvm/include/llvm/CodeGen/GlobalISel/IRTranslator.h @@ -204,6 +204,27 @@ private: /// \return true if the materialization succeeded. bool translate(const Constant &C, Register Reg); + /// Examine any debug-info attached to the instruction (in the form of + /// DPValues) and translate it. + void translateDbgInfo(const Instruction &Inst, + MachineIRBuilder &MIRBuilder); + + /// Translate a debug-info record of a dbg.value into a DBG_* instruction. + /// Pass in all the contents of the record, rather than relying on how it's + /// stored. + void translateDbgValueRecord(Value *V, bool HasArgList, + const DILocalVariable *Variable, + const DIExpression *Expression, const DebugLoc &DL, + MachineIRBuilder &MIRBuilder); + + /// Translate a debug-info record of a dbg.declare into an indirect DBG_* + /// instruction. Pass in all the contents of the record, rather than relying + /// on how it's stored. + void translateDbgDeclareRecord(Value *Address, bool HasArgList, + const DILocalVariable *Variable, + const DIExpression *Expression, const DebugLoc &DL, + MachineIRBuilder &MIRBuilder); + // Translate U as a copy of V. bool translateCopy(const User &U, const Value &V, MachineIRBuilder &MIRBuilder); @@ -250,14 +271,14 @@ private: /// possible. std::optional getArgPhysReg(Argument &Arg); - /// If DebugInst targets an Argument and its expression is an EntryValue, - /// lower it as an entry in the MF debug table. - bool translateIfEntryValueArgument(const DbgDeclareInst &DebugInst); - - /// If DebugInst targets an Argument and its expression is an EntryValue, - /// lower as a DBG_VALUE targeting the corresponding livein register for that - /// Argument. - bool translateIfEntryValueArgument(const DbgValueInst &DebugInst, + /// If debug-info targets an Argument and its expression is an EntryValue, + /// lower it as either an entry in the MF debug table (dbg.declare), or a + /// DBG_VALUE targeting the corresponding livein register for that Argument + /// (dbg.value). + bool translateIfEntryValueArgument(bool isDeclare, Value *Arg, + const DILocalVariable *Var, + const DIExpression *Expr, + const DebugLoc &DL, MachineIRBuilder &MIRBuilder); bool translateInlineAsm(const CallBase &CB, MachineIRBuilder &MIRBuilder); diff --git a/llvm/include/llvm/CodeGen/GlobalISel/LegalizerHelper.h b/llvm/include/llvm/CodeGen/GlobalISel/LegalizerHelper.h index 586679fa295..a7ecf0dc1ba 100644 --- a/llvm/include/llvm/CodeGen/GlobalISel/LegalizerHelper.h +++ b/llvm/include/llvm/CodeGen/GlobalISel/LegalizerHelper.h @@ -187,22 +187,6 @@ private: LegalizeResult widenScalarMulo(MachineInstr &MI, unsigned TypeIdx, LLT WideTy); - /// Helper function to split a wide generic register into bitwise blocks with - /// the given Type (which implies the number of blocks needed). The generic - /// registers created are appended to Ops, starting at bit 0 of Reg. - void extractParts(Register Reg, LLT Ty, int NumParts, - SmallVectorImpl &VRegs); - - /// Version which handles irregular splits. - bool extractParts(Register Reg, LLT RegTy, LLT MainTy, - LLT &LeftoverTy, - SmallVectorImpl &VRegs, - SmallVectorImpl &LeftoverVRegs); - - /// Version which handles irregular sub-vector splits. - void extractVectorParts(Register Reg, unsigned NumElst, - SmallVectorImpl &VRegs); - /// Helper function to build a wide generic register \p DstReg of type \p /// RegTy from smaller parts. This will produce a G_MERGE_VALUES, /// G_BUILD_VECTOR, G_CONCAT_VECTORS, or sequence of G_INSERT as appropriate diff --git a/llvm/include/llvm/CodeGen/GlobalISel/Utils.h b/llvm/include/llvm/CodeGen/GlobalISel/Utils.h index ffb6e53a036..57c037b5518 100644 --- a/llvm/include/llvm/CodeGen/GlobalISel/Utils.h +++ b/llvm/include/llvm/CodeGen/GlobalISel/Utils.h @@ -33,6 +33,7 @@ class BlockFrequencyInfo; class GISelKnownBits; class MachineFunction; class MachineInstr; +class MachineIRBuilder; class MachineOperand; class MachineOptimizationRemarkEmitter; class MachineOptimizationRemarkMissed; @@ -247,6 +248,24 @@ MachineInstr *getDefIgnoringCopies(Register Reg, /// Also walks through hints such as G_ASSERT_ZEXT. Register getSrcRegIgnoringCopies(Register Reg, const MachineRegisterInfo &MRI); +/// Helper function to split a wide generic register into bitwise blocks with +/// the given Type (which implies the number of blocks needed). The generic +/// registers created are appended to Ops, starting at bit 0 of Reg. +void extractParts(Register Reg, LLT Ty, int NumParts, + SmallVectorImpl &VRegs, + MachineIRBuilder &MIRBuilder, MachineRegisterInfo &MRI); + +/// Version which handles irregular splits. +bool extractParts(Register Reg, LLT RegTy, LLT MainTy, LLT &LeftoverTy, + SmallVectorImpl &VRegs, + SmallVectorImpl &LeftoverVRegs, + MachineIRBuilder &MIRBuilder, MachineRegisterInfo &MRI); + +/// Version which handles irregular sub-vector splits. +void extractVectorParts(Register Reg, unsigned NumElts, + SmallVectorImpl &VRegs, + MachineIRBuilder &MIRBuilder, MachineRegisterInfo &MRI); + // Templated variant of getOpcodeDef returning a MachineInstr derived T. /// See if Reg is defined by an single def instruction of type T /// Also try to do trivial folding if it's a COPY with diff --git a/llvm/include/llvm/CodeGen/GlobalMerge.h b/llvm/include/llvm/CodeGen/GlobalMerge.h new file mode 100644 index 00000000000..6b3766ab9e0 --- /dev/null +++ b/llvm/include/llvm/CodeGen/GlobalMerge.h @@ -0,0 +1,50 @@ +//===- llvm/CodeGen/GlobalMerge.h -------------------------------*- C++ -*-===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +#ifndef LLVM_CODEGEN_GLOBALMERGE_H +#define LLVM_CODEGEN_GLOBALMERGE_H + +#include "llvm/IR/PassManager.h" + +namespace llvm { + +class TargetMachine; + +struct GlobalMergeOptions { + // FIXME: Infer the maximum possible offset depending on the actual users + // (these max offsets are different for the users inside Thumb or ARM + // functions), see the code that passes in the offset in the ARM backend + // for more information. + unsigned MaxOffset = 0; + bool GroupByUse = true; + bool IgnoreSingleUse = true; + bool MergeConst = false; + /// Whether we should merge global variables that have external linkage. + bool MergeExternal = true; + /// Whether we should try to optimize for size only. + /// Currently, this applies a dead simple heuristic: only consider globals + /// used in minsize functions for merging. + /// FIXME: This could learn about optsize, and be used in the cost model. + bool SizeOnly = false; +}; + +// FIXME: This pass must run before AsmPrinterPass::doInitialization! +class GlobalMergePass : public PassInfoMixin { + const TargetMachine *TM; + GlobalMergeOptions Options; + +public: + GlobalMergePass(const TargetMachine *TM, GlobalMergeOptions Options) + : TM(TM), Options(Options) {} + + PreservedAnalyses run(Module &M, ModuleAnalysisManager &MAM); +}; + +} // namespace llvm + +#endif // LLVM_CODEGEN_GLOBALMERGE_H diff --git a/llvm/include/llvm/CodeGen/MachineBasicBlock.h b/llvm/include/llvm/CodeGen/MachineBasicBlock.h index 5812295f73b..c84fd281c6a 100644 --- a/llvm/include/llvm/CodeGen/MachineBasicBlock.h +++ b/llvm/include/llvm/CodeGen/MachineBasicBlock.h @@ -74,10 +74,10 @@ private: MBBSectionID(SectionType T) : Type(T), Number(0) {} }; -// This structure represents the information for a basic block. +// This structure represents the information for a basic block pertaining to +// the basic block sections profile. struct UniqueBBID { unsigned BaseID; - // sections profile). unsigned CloneID; }; diff --git a/llvm/include/llvm/CodeGen/MachineOperand.h b/llvm/include/llvm/CodeGen/MachineOperand.h index 1f3b7feedd1..63a17213453 100644 --- a/llvm/include/llvm/CodeGen/MachineOperand.h +++ b/llvm/include/llvm/CodeGen/MachineOperand.h @@ -782,6 +782,10 @@ public: void ChangeToGA(const GlobalValue *GV, int64_t Offset, unsigned TargetFlags = 0); + /// ChangeToBA - Replace this operand with a new block address operand. + void ChangeToBA(const BlockAddress *BA, int64_t Offset, + unsigned TargetFlags = 0); + /// ChangeToMCSymbol - Replace this operand with a new MC symbol operand. void ChangeToMCSymbol(MCSymbol *Sym, unsigned TargetFlags = 0); diff --git a/llvm/include/llvm/CodeGen/MachineOutliner.h b/llvm/include/llvm/CodeGen/MachineOutliner.h index d0ff02fea4f..eaba6c9b18f 100644 --- a/llvm/include/llvm/CodeGen/MachineOutliner.h +++ b/llvm/include/llvm/CodeGen/MachineOutliner.h @@ -87,7 +87,7 @@ private: // Compute liveness from the end of the block up to the beginning of the // outlining candidate. for (auto &MI : make_range(MBB->rbegin(), - (MachineBasicBlock::reverse_iterator)front())) + (MachineBasicBlock::reverse_iterator)begin())) FromEndOfBlockToStartOfSeq.stepBackward(MI); } @@ -100,7 +100,7 @@ private: return; InSeqWasSet = true; InSeq.init(TRI); - for (auto &MI : make_range(front(), std::next(back()))) + for (auto &MI : *this) InSeq.accumulate(MI); } @@ -135,8 +135,11 @@ public: /// Returns the call overhead of this candidate if it is in the list. unsigned getCallOverhead() const { return CallOverhead; } - MachineBasicBlock::iterator &front() { return FirstInst; } - MachineBasicBlock::iterator &back() { return LastInst; } + MachineBasicBlock::iterator begin() { return FirstInst; } + MachineBasicBlock::iterator end() { return std::next(LastInst); } + + MachineInstr &front() { return *FirstInst; } + MachineInstr &back() { return *LastInst; } MachineFunction *getMF() const { return MBB->getParent(); } MachineBasicBlock *getMBB() const { return MBB; } diff --git a/llvm/include/llvm/CodeGen/MachinePassRegistry.def b/llvm/include/llvm/CodeGen/MachinePassRegistry.def index e789747036e..082e2e37c83 100644 --- a/llvm/include/llvm/CodeGen/MachinePassRegistry.def +++ b/llvm/include/llvm/CodeGen/MachinePassRegistry.def @@ -23,9 +23,10 @@ MODULE_ANALYSIS("pass-instrumentation", PassInstrumentationAnalysis, (PIC)) #ifndef MODULE_PASS #define MODULE_PASS(NAME, PASS_NAME, CONSTRUCTOR) #endif -MODULE_PASS("pre-isel-intrinsic-lowering", PreISelIntrinsicLoweringPass, ()) +MODULE_PASS("global-merge", GlobalMergePass, (TM, GlobalMergeOptions())) MODULE_PASS("jmc-instrumenter", JMCInstrumenterPass, ()) MODULE_PASS("lower-emutls", LowerEmuTLSPass, ()) +MODULE_PASS("pre-isel-intrinsic-lowering", PreISelIntrinsicLoweringPass, ()) MODULE_PASS("shadow-stack-gc-lowering", ShadowStackGCLoweringPass, ()) #undef MODULE_PASS diff --git a/llvm/include/llvm/CodeGen/MachinePipeliner.h b/llvm/include/llvm/CodeGen/MachinePipeliner.h index 04055ba9732..8f0a17cf999 100644 --- a/llvm/include/llvm/CodeGen/MachinePipeliner.h +++ b/llvm/include/llvm/CodeGen/MachinePipeliner.h @@ -273,8 +273,8 @@ public: /// Return the new base register that was stored away for the changed /// instruction. - unsigned getInstrBaseReg(SUnit *SU) { - DenseMap>::iterator It = + unsigned getInstrBaseReg(SUnit *SU) const { + DenseMap>::const_iterator It = InstrChanges.find(SU); if (It != InstrChanges.end()) return It->second.first; @@ -639,16 +639,20 @@ public: computeUnpipelineableNodes(SwingSchedulerDAG *SSD, TargetInstrInfo::PipelinerLoopInfo *PLI); + std::deque + reorderInstructions(const SwingSchedulerDAG *SSD, + const std::deque &Instrs) const; + bool normalizeNonPipelinedInstructions(SwingSchedulerDAG *SSD, TargetInstrInfo::PipelinerLoopInfo *PLI); bool isValidSchedule(SwingSchedulerDAG *SSD); void finalizeSchedule(SwingSchedulerDAG *SSD); - void orderDependence(SwingSchedulerDAG *SSD, SUnit *SU, - std::deque &Insts); - bool isLoopCarried(SwingSchedulerDAG *SSD, MachineInstr &Phi); - bool isLoopCarriedDefOfUse(SwingSchedulerDAG *SSD, MachineInstr *Def, - MachineOperand &MO); + void orderDependence(const SwingSchedulerDAG *SSD, SUnit *SU, + std::deque &Insts) const; + bool isLoopCarried(const SwingSchedulerDAG *SSD, MachineInstr &Phi) const; + bool isLoopCarriedDefOfUse(const SwingSchedulerDAG *SSD, MachineInstr *Def, + MachineOperand &MO) const; void print(raw_ostream &os) const; void dump() const; }; diff --git a/llvm/include/llvm/CodeGen/MachineScheduler.h b/llvm/include/llvm/CodeGen/MachineScheduler.h index 9f16cf5d5bc..47127a6c296 100644 --- a/llvm/include/llvm/CodeGen/MachineScheduler.h +++ b/llvm/include/llvm/CodeGen/MachineScheduler.h @@ -1347,13 +1347,19 @@ ScheduleDAGMILive *createGenericSchedLive(MachineSchedContext *C); /// Create a generic scheduler with no vreg liveness or DAG mutation passes. ScheduleDAGMI *createGenericSchedPostRA(MachineSchedContext *C); +/// If ReorderWhileClustering is set to true, no attempt will be made to +/// reduce reordering due to store clustering. std::unique_ptr createLoadClusterDAGMutation(const TargetInstrInfo *TII, - const TargetRegisterInfo *TRI); + const TargetRegisterInfo *TRI, + bool ReorderWhileClustering = false); +/// If ReorderWhileClustering is set to true, no attempt will be made to +/// reduce reordering due to store clustering. std::unique_ptr createStoreClusterDAGMutation(const TargetInstrInfo *TII, - const TargetRegisterInfo *TRI); + const TargetRegisterInfo *TRI, + bool ReorderWhileClustering = false); std::unique_ptr createCopyConstrainDAGMutation(const TargetInstrInfo *TII, diff --git a/llvm/include/llvm/CodeGen/SelectionDAGISel.h b/llvm/include/llvm/CodeGen/SelectionDAGISel.h index e4d90f6e898..dbd9b391f4a 100644 --- a/llvm/include/llvm/CodeGen/SelectionDAGISel.h +++ b/llvm/include/llvm/CodeGen/SelectionDAGISel.h @@ -169,6 +169,14 @@ public: OPC_CheckPatternPredicate7, OPC_CheckPatternPredicateTwoByte, OPC_CheckPredicate, + OPC_CheckPredicate0, + OPC_CheckPredicate1, + OPC_CheckPredicate2, + OPC_CheckPredicate3, + OPC_CheckPredicate4, + OPC_CheckPredicate5, + OPC_CheckPredicate6, + OPC_CheckPredicate7, OPC_CheckPredicateWithOperands, OPC_CheckOpcode, OPC_SwitchOpcode, diff --git a/llvm/include/llvm/CodeGen/StackMaps.h b/llvm/include/llvm/CodeGen/StackMaps.h index 467e31f17bc..578020ca550 100644 --- a/llvm/include/llvm/CodeGen/StackMaps.h +++ b/llvm/include/llvm/CodeGen/StackMaps.h @@ -259,7 +259,7 @@ private: class StackMaps { public: struct Location { - enum LocationType { + enum LocationType : uint16_t { Unprocessed, Register, Direct, @@ -268,23 +268,22 @@ public: ConstantIndex }; LocationType Type = Unprocessed; - unsigned Size = 0; - unsigned Reg = 0; - int64_t Offset = 0; + uint16_t Size = 0; + uint16_t Reg = 0; + int32_t Offset = 0; Location() = default; - Location(LocationType Type, unsigned Size, unsigned Reg, int64_t Offset) + Location(LocationType Type, uint16_t Size, uint16_t Reg, int32_t Offset) : Type(Type), Size(Size), Reg(Reg), Offset(Offset) {} }; struct LiveOutReg { - unsigned short Reg = 0; - unsigned short DwarfRegNum = 0; - unsigned short Size = 0; + uint16_t Reg = 0; + uint16_t DwarfRegNum = 0; + uint16_t Size = 0; LiveOutReg() = default; - LiveOutReg(unsigned short Reg, unsigned short DwarfRegNum, - unsigned short Size) + LiveOutReg(uint16_t Reg, uint16_t DwarfRegNum, uint16_t Size) : Reg(Reg), DwarfRegNum(DwarfRegNum), Size(Size) {} }; @@ -369,7 +368,7 @@ private: MachineInstr::const_mop_iterator parseOperand(MachineInstr::const_mop_iterator MOI, MachineInstr::const_mop_iterator MOE, LocationVec &Locs, - LiveOutVec &LiveOuts) const; + LiveOutVec &LiveOuts); /// Specialized parser of statepoint operands. /// They do not directly correspond to StackMap record entries. diff --git a/llvm/include/llvm/CodeGen/TargetLowering.h b/llvm/include/llvm/CodeGen/TargetLowering.h index ed2b513be96..c9492b4cf77 100644 --- a/llvm/include/llvm/CodeGen/TargetLowering.h +++ b/llvm/include/llvm/CodeGen/TargetLowering.h @@ -2166,27 +2166,13 @@ public: /// This function should either return a nullptr, or a pointer to an IR-level /// Instruction*. Even complex fence sequences can be represented by a /// single Instruction* through an intrinsic to be lowered later. - /// Backends should override this method to produce target-specific intrinsic - /// for their fences. - /// FIXME: Please note that the default implementation here in terms of - /// IR-level fences exists for historical/compatibility reasons and is - /// *unsound* ! Fences cannot, in general, be used to restore sequential - /// consistency. For example, consider the following example: - /// atomic x = y = 0; - /// int r1, r2, r3, r4; - /// Thread 0: - /// x.store(1); - /// Thread 1: - /// y.store(1); - /// Thread 2: - /// r1 = x.load(); - /// r2 = y.load(); - /// Thread 3: - /// r3 = y.load(); - /// r4 = x.load(); - /// r1 = r3 = 1 and r2 = r4 = 0 is impossible as long as the accesses are all - /// seq_cst. But if they are lowered to monotonic accesses, no amount of - /// IR-level fences can prevent it. + /// + /// The default implementation emits an IR fence before any release (or + /// stronger) operation that stores, and after any acquire (or stronger) + /// operation. This is generally a correct implementation, but backends may + /// override if they wish to use alternative schemes (e.g. the PowerPC + /// standard ABI uses a fence before a seq_cst load instead of after a + /// seq_cst store). /// @{ virtual Instruction *emitLeadingFence(IRBuilderBase &Builder, Instruction *Inst, diff --git a/llvm/include/llvm/CodeGen/TargetPassConfig.h b/llvm/include/llvm/CodeGen/TargetPassConfig.h index 66365419aa3..d00e0bed91a 100644 --- a/llvm/include/llvm/CodeGen/TargetPassConfig.h +++ b/llvm/include/llvm/CodeGen/TargetPassConfig.h @@ -15,6 +15,7 @@ #include "llvm/Pass.h" #include "llvm/Support/CodeGen.h" +#include "llvm/Support/Error.h" #include #include @@ -170,11 +171,24 @@ public: /// set. static bool willCompleteCodeGenPipeline(); - /// If hasLimitedCodeGenPipeline is true, this method - /// returns a string with the name of the options, separated - /// by \p Separator that caused this pipeline to be limited. - static std::string - getLimitedCodeGenPipelineReason(const char *Separator = "/"); + /// If hasLimitedCodeGenPipeline is true, this method returns + /// a string with the name of the options that caused this + /// pipeline to be limited. + static std::string getLimitedCodeGenPipelineReason(); + + struct StartStopInfo { + bool StartAfter; + bool StopAfter; + unsigned StartInstanceNum; + unsigned StopInstanceNum; + StringRef StartPass; + StringRef StopPass; + }; + + /// Returns pass name in `-stop-before` or `-stop-after` + /// NOTE: New pass manager migration only + static Expected + getStartStopInfo(PassInstrumentationCallbacks &PIC); void setDisableVerify(bool Disable) { setOpt(DisableVerify, Disable); } diff --git a/llvm/include/llvm/CodeGen/TargetSubtargetInfo.h b/llvm/include/llvm/CodeGen/TargetSubtargetInfo.h index 55ef95c2854..a064dec7d8a 100644 --- a/llvm/include/llvm/CodeGen/TargetSubtargetInfo.h +++ b/llvm/include/llvm/CodeGen/TargetSubtargetInfo.h @@ -16,6 +16,7 @@ #include "llvm/ADT/ArrayRef.h" #include "llvm/ADT/SmallVector.h" #include "llvm/ADT/StringRef.h" +#include "llvm/CodeGen/MacroFusion.h" #include "llvm/CodeGen/PBQPRAConstraint.h" #include "llvm/CodeGen/SchedulerRegistry.h" #include "llvm/IR/GlobalValue.h" @@ -323,6 +324,9 @@ public: /// helps removing redundant copies generated by register allocator when /// handling complex eviction chains. virtual bool enableSpillageCopyElimination() const { return false; } + + /// Get the list of MacroFusion predicates. + virtual std::vector getMacroFusions() const { return {}; }; }; } // end namespace llvm diff --git a/llvm/include/llvm/DWARFLinker/AddressesMap.h b/llvm/include/llvm/DWARFLinker/AddressesMap.h index d8b3b440747..a232aafadc5 100644 --- a/llvm/include/llvm/DWARFLinker/AddressesMap.h +++ b/llvm/include/llvm/DWARFLinker/AddressesMap.h @@ -38,22 +38,22 @@ public: /// Checks that the specified DWARF expression operand \p Op references live /// code section and returns the relocation adjustment value (to get the /// linked address this value might be added to the source expression operand - /// address). + /// address). Print debug output if \p Verbose is true. /// \returns relocation adjustment value or std::nullopt if there is no /// corresponding live address. - virtual std::optional - getExprOpAddressRelocAdjustment(DWARFUnit &U, - const DWARFExpression::Operation &Op, - uint64_t StartOffset, uint64_t EndOffset) = 0; + virtual std::optional getExprOpAddressRelocAdjustment( + DWARFUnit &U, const DWARFExpression::Operation &Op, uint64_t StartOffset, + uint64_t EndOffset, bool Verbose) = 0; /// Checks that the specified subprogram \p DIE references the live code /// section and returns the relocation adjustment value (to get the linked /// address this value might be added to the source subprogram address). /// Allowed kinds of input DIE: DW_TAG_subprogram, DW_TAG_label. + /// Print debug output if \p Verbose is true. /// \returns relocation adjustment value or std::nullopt if there is no /// corresponding live address. virtual std::optional - getSubprogramRelocAdjustment(const DWARFDie &DIE) = 0; + getSubprogramRelocAdjustment(const DWARFDie &DIE, bool Verbose) = 0; // Returns the library install name associated to the AddessesMap. virtual std::optional getLibraryInstallName() = 0; @@ -90,7 +90,7 @@ public: /// second is the relocation adjustment value if the live address is /// referenced. std::pair> - getVariableRelocAdjustment(const DWARFDie &DIE) { + getVariableRelocAdjustment(const DWARFDie &DIE, bool Verbose) { assert((DIE.getTag() == dwarf::DW_TAG_variable || DIE.getTag() == dwarf::DW_TAG_constant) && "Wrong type of input die"); @@ -149,9 +149,9 @@ public: HasLocationAddress = true; // Check relocation for the address. if (std::optional RelocAdjustment = - getExprOpAddressRelocAdjustment(*U, Op, - AttrOffset + CurExprOffset, - AttrOffset + Op.getEndOffset())) + getExprOpAddressRelocAdjustment( + *U, Op, AttrOffset + CurExprOffset, + AttrOffset + Op.getEndOffset(), Verbose)) return std::make_pair(HasLocationAddress, *RelocAdjustment); } break; case dwarf::DW_OP_constx: @@ -164,8 +164,8 @@ public: if (std::optional RelocAdjustment = getExprOpAddressRelocAdjustment( *U, Op, *AddressOffset, - *AddressOffset + - DIE.getDwarfUnit()->getAddressByteSize())) + *AddressOffset + DIE.getDwarfUnit()->getAddressByteSize(), + Verbose)) return std::make_pair(HasLocationAddress, *RelocAdjustment); } } break; diff --git a/llvm/include/llvm/DWARFLinker/Classic/DWARFLinker.h b/llvm/include/llvm/DWARFLinker/Classic/DWARFLinker.h index d3aaa3baadc..b1d3f03394f 100644 --- a/llvm/include/llvm/DWARFLinker/Classic/DWARFLinker.h +++ b/llvm/include/llvm/DWARFLinker/Classic/DWARFLinker.h @@ -15,6 +15,7 @@ #include "llvm/CodeGen/NonRelocatableStringpool.h" #include "llvm/DWARFLinker/Classic/DWARFLinkerCompileUnit.h" #include "llvm/DWARFLinker/DWARFLinkerBase.h" +#include "llvm/DWARFLinker/IndexedValuesMap.h" #include "llvm/DebugInfo/DWARF/DWARFContext.h" #include "llvm/DebugInfo/DWARF/DWARFDebugLine.h" #include "llvm/DebugInfo/DWARF/DWARFDebugRangeList.h" @@ -33,25 +34,7 @@ namespace classic { class DeclContextTree; using Offset2UnitMap = DenseMap; - -struct DebugDieValuePool { - DenseMap DieValueMap; - SmallVector DieValues; - - uint64_t getValueIndex(uint64_t Value) { - DenseMap::iterator It = DieValueMap.find(Value); - if (It == DieValueMap.end()) { - It = DieValueMap.insert(std::make_pair(Value, DieValues.size())).first; - DieValues.push_back(Value); - } - return It->second; - } - - void clear() { - DieValueMap.clear(); - DieValues.clear(); - } -}; +using DebugDieValuePool = IndexedValuesMap; /// DwarfEmitter presents interface to generate all debug info tables. class DwarfEmitter { @@ -59,7 +42,8 @@ public: virtual ~DwarfEmitter() = default; /// Emit section named SecName with data SecData. - virtual void emitSectionContents(StringRef SecData, StringRef SecName) = 0; + virtual void emitSectionContents(StringRef SecData, + DebugSectionKind SecKind) = 0; /// Emit the abbreviation table \p Abbrevs to the .debug_abbrev section. virtual void @@ -205,17 +189,6 @@ public: /// Dump the file to the disk. virtual void finish() = 0; - - /// Emit the swift_ast section stored in \p Buffer. - virtual void emitSwiftAST(StringRef Buffer) = 0; - - /// Emit the swift reflection section stored in \p Buffer. - virtual void emitSwiftReflectionSection( - llvm::binaryformat::Swift5ReflectionSectionKind ReflSectionKind, - StringRef Buffer, uint32_t Alignment, uint32_t Size) = 0; - - /// Returns underlying AsmPrinter. - virtual AsmPrinter &getAsmPrinter() const = 0; }; class DwarfStreamer; @@ -249,10 +222,10 @@ public: StringsTranslator); } - Error createEmitter(const Triple &TheTriple, OutputFileType FileType, - raw_pwrite_stream &OutFile); - - DwarfEmitter *getEmitter(); + /// Set output DWARF emitter. + void setOutputDWARFEmitter(DwarfEmitter *Emitter) { + TheDwarfEmitter = Emitter; + } /// Add object file to be linked. Pre-load compile unit die. Call /// \p OnCUDieLoaded for each compile unit die. If specified \p File @@ -779,7 +752,7 @@ private: BumpPtrAllocator DIEAlloc; /// @} - std::unique_ptr TheDwarfEmitter; + DwarfEmitter *TheDwarfEmitter = nullptr; std::vector ObjectContexts; /// The CIEs that have been emitted in the output section. The actual CIE diff --git a/llvm/include/llvm/DWARFLinker/Classic/DWARFStreamer.h b/llvm/include/llvm/DWARFLinker/Classic/DWARFStreamer.h index f010c348f12..bebdfd5e602 100644 --- a/llvm/include/llvm/DWARFLinker/Classic/DWARFStreamer.h +++ b/llvm/include/llvm/DWARFLinker/Classic/DWARFStreamer.h @@ -45,18 +45,23 @@ class DwarfStreamer : public DwarfEmitter { public: DwarfStreamer(DWARFLinkerBase::OutputFileType OutFileType, raw_pwrite_stream &OutFile, - std::function Translator, + DWARFLinkerBase::TranslatorFuncTy Translator, DWARFLinkerBase::MessageHandlerTy Warning) : OutFile(OutFile), OutFileType(OutFileType), Translator(Translator), WarningHandler(Warning) {} virtual ~DwarfStreamer() = default; + static Expected> createStreamer( + const Triple &TheTriple, DWARFLinkerBase::OutputFileType FileType, + raw_pwrite_stream &OutFile, DWARFLinkerBase::TranslatorFuncTy Translator, + DWARFLinkerBase::MessageHandlerTy Warning); + Error init(Triple TheTriple, StringRef Swift5ReflectionSegmentName); /// Dump the file to the disk. void finish() override; - AsmPrinter &getAsmPrinter() const override { return *Asm; } + AsmPrinter &getAsmPrinter() const { return *Asm; } /// Set the current output section to debug_info and change /// the MC Dwarf version to \p DwarfVersion. @@ -77,7 +82,8 @@ public: unsigned DwarfVersion) override; /// Emit contents of section SecName From Obj. - void emitSectionContents(StringRef SecData, StringRef SecName) override; + void emitSectionContents(StringRef SecData, + DebugSectionKind SecKind) override; /// Emit the string table described by \p Pool into .debug_str table. void emitStrings(const NonRelocatableStringpool &Pool) override; @@ -91,12 +97,12 @@ public: void emitLineStrings(const NonRelocatableStringpool &Pool) override; /// Emit the swift_ast section stored in \p Buffer. - void emitSwiftAST(StringRef Buffer) override; + void emitSwiftAST(StringRef Buffer); /// Emit the swift reflection section stored in \p Buffer. void emitSwiftReflectionSection( llvm::binaryformat::Swift5ReflectionSectionKind ReflSectionKind, - StringRef Buffer, uint32_t Alignment, uint32_t Size) override; + StringRef Buffer, uint32_t Alignment, uint32_t Size); /// Emit debug ranges(.debug_ranges, .debug_rnglists) header. MCSymbol *emitDwarfDebugRangeListHeader(const CompileUnit &Unit) override; @@ -215,6 +221,8 @@ private: WarningHandler(Warning, Context, nullptr); } + MCSection *getMCSection(DebugSectionKind SecKind); + void emitMacroTableImpl(const DWARFDebugMacro *MacroTable, const Offset2UnitMap &UnitMacroMap, OffsetsStringPool &StringPool, uint64_t &OutOffset); diff --git a/llvm/include/llvm/DWARFLinker/DWARFLinkerBase.h b/llvm/include/llvm/DWARFLinker/DWARFLinkerBase.h index 626fb53d90f..5c811b668f0 100644 --- a/llvm/include/llvm/DWARFLinker/DWARFLinkerBase.h +++ b/llvm/include/llvm/DWARFLinker/DWARFLinkerBase.h @@ -23,6 +23,53 @@ class DWARFUnit; namespace dwarf_linker { +/// List of tracked debug tables. +enum class DebugSectionKind : uint8_t { + DebugInfo = 0, + DebugLine, + DebugFrame, + DebugRange, + DebugRngLists, + DebugLoc, + DebugLocLists, + DebugARanges, + DebugAbbrev, + DebugMacinfo, + DebugMacro, + DebugAddr, + DebugStr, + DebugLineStr, + DebugStrOffsets, + DebugPubNames, + DebugPubTypes, + DebugNames, + AppleNames, + AppleNamespaces, + AppleObjC, + AppleTypes, + NumberOfEnumEntries // must be last +}; + +static constexpr size_t SectionKindsNum = + static_cast(DebugSectionKind::NumberOfEnumEntries); + +static constexpr StringLiteral SectionNames[SectionKindsNum] = { + "debug_info", "debug_line", "debug_frame", "debug_ranges", + "debug_rnglists", "debug_loc", "debug_loclists", "debug_aranges", + "debug_abbrev", "debug_macinfo", "debug_macro", "debug_addr", + "debug_str", "debug_line_str", "debug_str_offsets", "debug_pubnames", + "debug_pubtypes", "debug_names", "apple_names", "apple_namespac", + "apple_objc", "apple_types"}; + +/// Return the name of the section. +static constexpr const StringLiteral & +getSectionName(DebugSectionKind SectionKind) { + return SectionNames[static_cast(SectionKind)]; +} + +/// Recognise the table name and match it with the DebugSectionKind. +std::optional parseDebugTableName(StringRef Name); + /// The base interface for DWARFLinker implementations. class DWARFLinkerBase { public: diff --git a/llvm/lib/DWARFLinker/Parallel/IndexedValuesMap.h b/llvm/include/llvm/DWARFLinker/IndexedValuesMap.h similarity index 80% rename from llvm/lib/DWARFLinker/Parallel/IndexedValuesMap.h rename to llvm/include/llvm/DWARFLinker/IndexedValuesMap.h index b592ce37937..fadbeb168b5 100644 --- a/llvm/lib/DWARFLinker/Parallel/IndexedValuesMap.h +++ b/llvm/include/llvm/DWARFLinker/IndexedValuesMap.h @@ -6,8 +6,8 @@ // //===----------------------------------------------------------------------===// -#ifndef LLVM_LIB_DWARFLINKER_PARALLEL_INDEXEDVALUESMAP_H -#define LLVM_LIB_DWARFLINKER_PARALLEL_INDEXEDVALUESMAP_H +#ifndef LLVM_DWARFLINKER_INDEXEDVALUESMAP_H +#define LLVM_DWARFLINKER_INDEXEDVALUESMAP_H #include "llvm/ADT/DenseMap.h" #include "llvm/ADT/SmallVector.h" @@ -16,8 +16,8 @@ namespace llvm { namespace dwarf_linker { -namespace parallel { +/// This class stores values sequentually and assigns index to the each value. template class IndexedValuesMap { public: uint64_t getValueIndex(T Value) { @@ -29,7 +29,7 @@ public: return It->second; } - const SmallVector &getValues() { return Values; } + const SmallVector &getValues() const { return Values; } void clear() { ValueToIndexMap.clear(); @@ -44,8 +44,7 @@ protected: SmallVector Values; }; -} // end of namespace parallel } // end of namespace dwarf_linker } // end of namespace llvm -#endif // LLVM_LIB_DWARFLINKER_PARALLEL_INDEXEDVALUESMAP_H +#endif // LLVM_DWARFLINKER_INDEXEDVALUESMAP_H diff --git a/llvm/include/llvm/DWARFLinker/Parallel/DWARFLinker.h b/llvm/include/llvm/DWARFLinker/Parallel/DWARFLinker.h index c38a9906940..5312712a4a5 100644 --- a/llvm/include/llvm/DWARFLinker/Parallel/DWARFLinker.h +++ b/llvm/include/llvm/DWARFLinker/Parallel/DWARFLinker.h @@ -89,30 +89,34 @@ namespace llvm { namespace dwarf_linker { namespace parallel { -/// ExtraDwarfEmitter allows adding extra data to the DWARFLinker output. -/// The finish() method should be called after all extra data are emitted. -class ExtraDwarfEmitter { -public: - virtual ~ExtraDwarfEmitter() = default; +/// This structure keeps data of the concrete section. +struct SectionDescriptorBase { + SectionDescriptorBase(DebugSectionKind SectionKind, dwarf::FormParams Format, + llvm::endianness Endianess) + : SectionKind(SectionKind), Format(Format), Endianess(Endianess) {} + virtual ~SectionDescriptorBase() = default; + /// Returns section content. + virtual StringRef getContents() = 0; + /// Returns section kind. + DebugSectionKind getKind() { return SectionKind; } + /// Returns section name. + const StringLiteral &getName() const { return getSectionName(SectionKind); } + /// Returns endianess used by section. + llvm::endianness getEndianess() const { return Endianess; } + /// Returns FormParams used by section. + dwarf::FormParams getFormParams() const { return Format; } - /// Dump the file to the disk. - virtual void finish() = 0; - - /// Emit section named SecName with data SecData. - virtual void emitSectionContents(StringRef SecData, StringRef SecName) = 0; - - /// Emit the swift_ast section stored in \p Buffer. - virtual void emitSwiftAST(StringRef Buffer) = 0; - - /// Emit the swift reflection section stored in \p Buffer. - virtual void emitSwiftReflectionSection( - llvm::binaryformat::Swift5ReflectionSectionKind ReflSectionKind, - StringRef Buffer, uint32_t Alignment, uint32_t Size) = 0; - - /// Returns underlying AsmPrinter. - virtual AsmPrinter &getAsmPrinter() const = 0; +protected: + /// The section kind. + DebugSectionKind SectionKind = DebugSectionKind::NumberOfEnumEntries; + /// Output format. + dwarf::FormParams Format = {4, 4, dwarf::DWARF32}; + llvm::endianness Endianess = llvm::endianness::little; }; +using SectionHandlerTy = + std::function Section)>; + class DWARFLinker : public DWARFLinkerBase { public: virtual ~DWARFLinker() = default; @@ -122,12 +126,11 @@ public: createLinker(MessageHandlerTy ErrorHandler, MessageHandlerTy WarningHandler, TranslatorFuncTy StringsTranslator = nullptr); - /// Creates emitter for output dwarf. - virtual Error createEmitter(const Triple &TheTriple, OutputFileType FileType, - raw_pwrite_stream &OutFile) = 0; - - /// Returns previously created dwarf emitter. May be nullptr. - virtual ExtraDwarfEmitter *getEmitter() = 0; + /// Set output DWARF handler. Result of linking DWARF is set of sections + /// containing final debug info. DWARFLinkerBase::link() pass generated + /// sections using specified \p SectionHandler. + virtual void setOutputDWARFHandler(const Triple &TargetTriple, + SectionHandlerTy SectionHandler) = 0; }; } // end of namespace parallel diff --git a/llvm/include/llvm/DebugInfo/DIContext.h b/llvm/include/llvm/DebugInfo/DIContext.h index 9ad27033ec1..78ac34e5f0d 100644 --- a/llvm/include/llvm/DebugInfo/DIContext.h +++ b/llvm/include/llvm/DebugInfo/DIContext.h @@ -204,6 +204,7 @@ struct DIDumpOptions { bool Verbose = false; bool DisplayRawContents = false; bool IsEH = false; + bool DumpNonSkeleton = false; std::function GetNameForDWARFReg; diff --git a/llvm/include/llvm/DebugInfo/DWARF/DWARFContext.h b/llvm/include/llvm/DebugInfo/DWARF/DWARFContext.h index fa98cbcfc4d..7be65a8b45e 100644 --- a/llvm/include/llvm/DebugInfo/DWARF/DWARFContext.h +++ b/llvm/include/llvm/DebugInfo/DWARF/DWARFContext.h @@ -372,7 +372,13 @@ public: /// given address where applicable. /// TODO: change input parameter from "uint64_t Address" /// into "SectionedAddress Address" - DIEsForAddress getDIEsForAddress(uint64_t Address); + /// \param[in] CheckDWO If this is false then only search for address matches + /// in the current context's DIEs. If this is true, then each + /// DWARFUnit that has a DWO file will have the debug info in the + /// DWO file searched as well. This allows for lookups to succeed + /// by searching the split DWARF debug info when using the main + /// executable's debug info. + DIEsForAddress getDIEsForAddress(uint64_t Address, bool CheckDWO = false); DILineInfo getLineInfoForAddress( object::SectionedAddress Address, diff --git a/llvm/include/llvm/Debuginfod/Debuginfod.h b/llvm/include/llvm/Debuginfod/Debuginfod.h index 251fd700530..ef03948a706 100644 --- a/llvm/include/llvm/Debuginfod/Debuginfod.h +++ b/llvm/include/llvm/Debuginfod/Debuginfod.h @@ -46,6 +46,9 @@ bool canUseDebuginfod(); /// environment variable. SmallVector getDefaultDebuginfodUrls(); +/// Returns the cache key for a given debuginfod URL path. +std::string getDebuginfodCacheKey(StringRef UrlPath); + /// Sets the list of debuginfod server URLs to query. This overrides the /// environment variable DEBUGINFOD_URLS. void setDefaultDebuginfodUrls(const SmallVector &URLs); @@ -58,15 +61,26 @@ Expected getDefaultDebuginfodCacheDirectory(); /// DEBUGINFOD_TIMEOUT environment variable, default is 90 seconds (90000 ms). std::chrono::milliseconds getDefaultDebuginfodTimeout(); +/// Get the full URL path for a source request of a given BuildID and file +/// path. +std::string getDebuginfodSourceUrlPath(object::BuildIDRef ID, + StringRef SourceFilePath); + /// Fetches a specified source file by searching the default local cache /// directory and server URLs. Expected getCachedOrDownloadSource(object::BuildIDRef ID, StringRef SourceFilePath); +/// Get the full URL path for an executable request of a given BuildID. +std::string getDebuginfodExecutableUrlPath(object::BuildIDRef ID); + /// Fetches an executable by searching the default local cache directory and /// server URLs. Expected getCachedOrDownloadExecutable(object::BuildIDRef ID); +/// Get the full URL path for a debug binary request of a given BuildID. +std::string getDebuginfodDebuginfoUrlPath(object::BuildIDRef ID); + /// Fetches a debug binary by searching the default local cache directory and /// server URLs. Expected getCachedOrDownloadDebuginfo(object::BuildIDRef ID); diff --git a/llvm/include/llvm/ExecutionEngine/JITLink/aarch32.h b/llvm/include/llvm/ExecutionEngine/JITLink/aarch32.h index f346cfb2a93..eda6feb441e 100644 --- a/llvm/include/llvm/ExecutionEngine/JITLink/aarch32.h +++ b/llvm/include/llvm/ExecutionEngine/JITLink/aarch32.h @@ -41,7 +41,13 @@ enum EdgeKind_aarch32 : Edge::Kind { /// Absolute 32-bit value relocation Data_Pointer32, - LastDataRelocation = Data_Pointer32, + /// Relative 31-bit value relocation that preserves the most-significant bit + Data_PRel31, + + /// Create GOT entry and store offset + Data_RequestGOTAndTransformToDelta32, + + LastDataRelocation = Data_RequestGOTAndTransformToDelta32, /// /// Relocations of class Arm (covers fixed-width 4-byte instruction subset) @@ -98,7 +104,11 @@ enum EdgeKind_aarch32 : Edge::Kind { Thumb_MovtPrel, LastThumbRelocation = Thumb_MovtPrel, - LastRelocation = LastThumbRelocation, + + /// No-op relocation + None, + + LastRelocation = None, }; /// Flags enum for AArch32-specific symbol properties @@ -123,32 +133,29 @@ const char *getEdgeKindName(Edge::Kind K); /// /// Stubs are often called "veneers" in the official docs and online. /// -enum StubsFlavor { - Unsupported = 0, - Thumbv7, +enum class StubsFlavor { + Undefined = 0, + pre_v7, + v7, }; /// JITLink sub-arch configuration for Arm CPU models struct ArmConfig { bool J1J2BranchEncoding = false; - StubsFlavor Stubs = Unsupported; + StubsFlavor Stubs = StubsFlavor::Undefined; + // In the long term, we might want a linker switch like --target1-rel + bool Target1Rel = false; }; /// Obtain the sub-arch configuration for a given Arm CPU model. inline ArmConfig getArmConfigForCPUArch(ARMBuildAttrs::CPUArch CPUArch) { ArmConfig ArmCfg; - switch (CPUArch) { - case ARMBuildAttrs::v7: - case ARMBuildAttrs::v8_A: + if (CPUArch == ARMBuildAttrs::v7 || CPUArch >= ARMBuildAttrs::v7E_M) { ArmCfg.J1J2BranchEncoding = true; - ArmCfg.Stubs = Thumbv7; - break; - default: - DEBUG_WITH_TYPE("jitlink", { - dbgs() << " Warning: ARM config not defined for CPU architecture " - << getCPUArchName(CPUArch); - }); - break; + ArmCfg.Stubs = StubsFlavor::v7; + } else { + ArmCfg.J1J2BranchEncoding = false; + ArmCfg.Stubs = StubsFlavor::pre_v7; } return ArmCfg; } @@ -288,7 +295,8 @@ inline Expected readAddend(LinkGraph &G, Block &B, if (Kind <= LastThumbRelocation) return readAddendThumb(G, B, Offset, Kind, ArmCfg); - llvm_unreachable("Relocation must be of class Data, Arm or Thumb"); + assert(Kind == None && "Not associated with a relocation class"); + return 0; } /// Helper function to apply the fixup for Data-class relocations. @@ -315,76 +323,86 @@ inline Error applyFixup(LinkGraph &G, Block &B, const Edge &E, if (Kind <= LastThumbRelocation) return applyFixupThumb(G, B, E, ArmCfg); - llvm_unreachable("Relocation must be of class Data, Arm or Thumb"); + assert(Kind == None && "Not associated with a relocation class"); + return Error::success(); } -/// Stubs builder for a specific StubsFlavor -/// -/// Right now we only have one default stub kind, but we want to extend this -/// and allow creation of specific kinds in the future (e.g. branch range -/// extension or interworking). -/// -/// Let's keep it simple for the moment and not wire this through a GOT. -/// -template -class StubsManager : public TableManager> { +/// Populate a Global Offset Table from edges that request it. +class GOTBuilder : public TableManager { public: - StubsManager() = default; + static StringRef getSectionName() { return "$__GOT"; } - /// Name of the object file section that will contain all our stubs. - static StringRef getSectionName(); - - /// Implements link-graph traversal via visitExistingEdges(). - bool visitEdge(LinkGraph &G, Block *B, Edge &E) { - if (E.getTarget().isDefined()) - return false; - - switch (E.getKind()) { - case Thumb_Call: - case Thumb_Jump24: { - DEBUG_WITH_TYPE("jitlink", { - dbgs() << " Fixing " << G.getEdgeKindName(E.getKind()) << " edge at " - << B->getFixupAddress(E) << " (" << B->getAddress() << " + " - << formatv("{0:x}", E.getOffset()) << ")\n"; - }); - E.setTarget(this->getEntryForTarget(G, E.getTarget())); - return true; - } - } - return false; - } - - /// Create a branch range extension stub for the class's flavor. + bool visitEdge(LinkGraph &G, Block *B, Edge &E); Symbol &createEntry(LinkGraph &G, Symbol &Target); private: - /// Create a new node in the link-graph for the given stub template. - template - Block &addStub(LinkGraph &G, const uint8_t (&Code)[Size], - uint64_t Alignment) { - ArrayRef Template(reinterpret_cast(Code), Size); - return G.createContentBlock(getStubsSection(G), Template, - orc::ExecutorAddr(), Alignment, 0); + Section *GOTSection = nullptr; +}; + +/// Stubs builder emits non-position-independent Arm stubs for pre-v7 CPUs. +/// These architectures have no MovT/MovW instructions and don't support Thumb2. +/// BL is the only Thumb instruction that can generate stubs and they can always +/// be transformed into BLX. +class StubsManager_prev7 { +public: + StubsManager_prev7() = default; + + /// Name of the object file section that will contain all our stubs. + static StringRef getSectionName() { + return "__llvm_jitlink_aarch32_STUBS_prev7"; } - /// Get or create the object file section that will contain all our stubs. - Section &getStubsSection(LinkGraph &G) { - if (!StubsSection) - StubsSection = &G.createSection(getSectionName(), - orc::MemProt::Read | orc::MemProt::Exec); - return *StubsSection; + /// Implements link-graph traversal via visitExistingEdges() + bool visitEdge(LinkGraph &G, Block *B, Edge &E); + +private: + // Each stub uses a single block that can have 2 entryponts, one for Arm and + // one for Thumb + struct StubMapEntry { + Block *B = nullptr; + Symbol *ArmEntry = nullptr; + Symbol *ThumbEntry = nullptr; + }; + + std::pair getStubMapSlot(StringRef Name) { + auto &&[Stubs, NewStub] = StubMap.try_emplace(Name); + return std::make_pair(&Stubs->second, NewStub); } + Symbol *getOrCreateSlotEntrypoint(LinkGraph &G, StubMapEntry &Slot, + bool Thumb); + + DenseMap StubMap; Section *StubsSection = nullptr; }; -/// Create a branch range extension stub with Thumb encoding for v7 CPUs. -template <> -Symbol &StubsManager::createEntry(LinkGraph &G, Symbol &Target); +/// Stubs builder for v7 emits non-position-independent Arm and Thumb stubs. +class StubsManager_v7 { +public: + StubsManager_v7() = default; -template <> inline StringRef StubsManager::getSectionName() { - return "__llvm_jitlink_aarch32_STUBS_Thumbv7"; -} + /// Name of the object file section that will contain all our stubs. + static StringRef getSectionName() { + return "__llvm_jitlink_aarch32_STUBS_v7"; + } + + /// Implements link-graph traversal via visitExistingEdges(). + bool visitEdge(LinkGraph &G, Block *B, Edge &E); + +private: + // Two slots per external: Arm and Thumb + using StubMapEntry = std::tuple; + + Symbol *&getStubSymbolSlot(StringRef Name, bool Thumb) { + StubMapEntry &Stubs = StubMap.try_emplace(Name).first->second; + if (Thumb) + return std::get<1>(Stubs); + return std::get<0>(Stubs); + } + + DenseMap StubMap; + Section *StubsSection = nullptr; +}; } // namespace aarch32 } // namespace jitlink diff --git a/llvm/include/llvm/ExecutionEngine/Orc/MachOBuilder.h b/llvm/include/llvm/ExecutionEngine/Orc/MachOBuilder.h index 2bc66b11e27..45dd5fcbebd 100644 --- a/llvm/include/llvm/ExecutionEngine/Orc/MachOBuilder.h +++ b/llvm/include/llvm/ExecutionEngine/Orc/MachOBuilder.h @@ -43,20 +43,20 @@ struct MachOBuilderLoadCommandBase { }; /// MachOBuilder load command wrapper type. -template struct MachOBuilderLoadCommand; +template struct MachOBuilderLoadCommandImplBase; #define HANDLE_LOAD_COMMAND(Name, Value, LCStruct) \ template <> \ - struct MachOBuilderLoadCommand \ + struct MachOBuilderLoadCommandImplBase \ : public MachO::LCStruct, public MachOBuilderLoadCommandBase { \ using CmdStruct = LCStruct; \ - MachOBuilderLoadCommand() { \ + MachOBuilderLoadCommandImplBase() { \ memset(&rawStruct(), 0, sizeof(CmdStruct)); \ cmd = Value; \ cmdsize = sizeof(CmdStruct); \ } \ template \ - MachOBuilderLoadCommand(ArgTs &&...Args) \ + MachOBuilderLoadCommandImplBase(ArgTs &&...Args) \ : CmdStruct{Value, sizeof(CmdStruct), std::forward(Args)...} {} \ CmdStruct &rawStruct() { return static_cast(*this); } \ size_t size() const override { return cmdsize; } \ @@ -70,6 +70,81 @@ template struct MachOBuilderLoadCommand; #undef HANDLE_LOAD_COMMAND +template +struct MachOBuilderLoadCommand + : public MachOBuilderLoadCommandImplBase { +public: + MachOBuilderLoadCommand() = default; + + template + MachOBuilderLoadCommand(ArgTs &&...Args) + : MachOBuilderLoadCommand(std::forward(Args)...) {} +}; + +template <> +struct MachOBuilderLoadCommand + : public MachOBuilderLoadCommandImplBase { + + MachOBuilderLoadCommand(std::string Name, uint32_t Timestamp, + uint32_t CurrentVersion, + uint32_t CompatibilityVersion) + : MachOBuilderLoadCommandImplBase( + MachO::dylib{24, Timestamp, CurrentVersion, CompatibilityVersion}), + Name(std::move(Name)) { + cmdsize += (this->Name.size() + 1 + 3) & ~0x3; + } + + size_t write(MutableArrayRef Buf, size_t Offset, + bool SwapStruct) override { + Offset = writeMachOStruct(Buf, Offset, rawStruct(), SwapStruct); + strcpy(Buf.data() + Offset, Name.data()); + return Offset + ((Name.size() + 1 + 3) & ~0x3); + } + + std::string Name; +}; + +template <> +struct MachOBuilderLoadCommand + : public MachOBuilderLoadCommandImplBase { + + MachOBuilderLoadCommand(std::string Name, uint32_t Timestamp, + uint32_t CurrentVersion, + uint32_t CompatibilityVersion) + : MachOBuilderLoadCommandImplBase( + MachO::dylib{24, Timestamp, CurrentVersion, CompatibilityVersion}), + Name(std::move(Name)) { + cmdsize += (this->Name.size() + 1 + 3) & ~0x3; + } + + size_t write(MutableArrayRef Buf, size_t Offset, + bool SwapStruct) override { + Offset = writeMachOStruct(Buf, Offset, rawStruct(), SwapStruct); + strcpy(Buf.data() + Offset, Name.data()); + return Offset + ((Name.size() + 1 + 3) & ~0x3); + } + + std::string Name; +}; + +template <> +struct MachOBuilderLoadCommand + : public MachOBuilderLoadCommandImplBase { + MachOBuilderLoadCommand(std::string Path) + : MachOBuilderLoadCommandImplBase(12u), Path(std::move(Path)) { + cmdsize += (this->Path.size() + 1 + 3) & ~0x3; + } + + size_t write(MutableArrayRef Buf, size_t Offset, + bool SwapStruct) override { + Offset = writeMachOStruct(Buf, Offset, rawStruct(), SwapStruct); + strcpy(Buf.data() + Offset, Path.data()); + return Offset + ((Path.size() + 1 + 3) & ~0x3); + } + + std::string Path; +}; + // Builds MachO objects. template class MachOBuilder { private: diff --git a/llvm/include/llvm/ExecutionEngine/Orc/MachOPlatform.h b/llvm/include/llvm/ExecutionEngine/Orc/MachOPlatform.h index d9b809ab5b1..ff1c420d047 100644 --- a/llvm/include/llvm/ExecutionEngine/Orc/MachOPlatform.h +++ b/llvm/include/llvm/ExecutionEngine/Orc/MachOPlatform.h @@ -47,14 +47,38 @@ public: LLVM_MARK_AS_BITMASK_ENUM(/* LargestValue = */ Callable) }; + /// Configuration for the mach-o header of a JITDylib. Specify common load + /// commands that should be added to the header. + struct HeaderOptions { + /// A dylib for use with a dylib command (e.g. LC_ID_DYLIB, LC_LOAD_DYLIB). + struct Dylib { + std::string Name; + uint32_t Timestamp; + uint32_t CurrentVersion; + uint32_t CompatibilityVersion; + }; + + /// Override for LC_IC_DYLIB. If this is nullopt, {JD.getName(), 0, 0, 0} + /// will be used. + std::optional IDDylib; + /// List of LC_LOAD_DYLIBs. + std::vector LoadDylibs; + /// List of LC_RPATHs. + std::vector RPaths; + + HeaderOptions() = default; + HeaderOptions(Dylib D) : IDDylib(std::move(D)) {} + }; + /// Used by setupJITDylib to create MachO header MaterializationUnits for /// JITDylibs. using MachOHeaderMUBuilder = - unique_function(MachOPlatform &MOP)>; + unique_function(MachOPlatform &MOP, + HeaderOptions Opts)>; /// Simple MachO header graph builder. static inline std::unique_ptr - buildSimpleMachOHeaderMU(MachOPlatform &MOP); + buildSimpleMachOHeaderMU(MachOPlatform &MOP, HeaderOptions Opts); /// Try to create a MachOPlatform instance, adding the ORC runtime to the /// given JITDylib. @@ -97,6 +121,7 @@ public: static Expected> Create(ExecutionSession &ES, ObjectLinkingLayer &ObjLinkingLayer, JITDylib &PlatformJD, std::unique_ptr OrcRuntime, + HeaderOptions PlatformJDOpts = {}, MachOHeaderMUBuilder BuildMachOHeaderMU = buildSimpleMachOHeaderMU, std::optional RuntimeAliases = std::nullopt); @@ -104,6 +129,7 @@ public: static Expected> Create(ExecutionSession &ES, ObjectLinkingLayer &ObjLinkingLayer, JITDylib &PlatformJD, const char *OrcRuntimePath, + HeaderOptions PlatformJDOpts = {}, MachOHeaderMUBuilder BuildMachOHeaderMU = buildSimpleMachOHeaderMU, std::optional RuntimeAliases = std::nullopt); @@ -115,6 +141,11 @@ public: } Error setupJITDylib(JITDylib &JD) override; + + /// Install any platform-specific symbols (e.g. `__dso_handle`) and create a + /// mach-o header based on the given options. + Error setupJITDylib(JITDylib &JD, HeaderOptions Opts); + Error teardownJITDylib(JITDylib &JD) override; Error notifyAdding(ResourceTracker &RT, const MaterializationUnit &MU) override; @@ -258,6 +289,7 @@ private: MachOPlatform(ExecutionSession &ES, ObjectLinkingLayer &ObjLinkingLayer, JITDylib &PlatformJD, std::unique_ptr OrcRuntimeGenerator, + HeaderOptions PlatformJDOpts, MachOHeaderMUBuilder BuildMachOHeaderMU, Error &Err); // Associate MachOPlatform JIT-side runtime support functions with handlers. @@ -336,7 +368,8 @@ private: // Generates a MachO header. class SimpleMachOHeaderMU : public MaterializationUnit { public: - SimpleMachOHeaderMU(MachOPlatform &MOP, SymbolStringPtr HeaderStartSymbol); + SimpleMachOHeaderMU(MachOPlatform &MOP, SymbolStringPtr HeaderStartSymbol, + MachOPlatform::HeaderOptions Opts); StringRef getName() const override { return "MachOHeaderMU"; } void materialize(std::unique_ptr R) override; void discard(const JITDylib &JD, const SymbolStringPtr &Sym) override; @@ -346,6 +379,7 @@ protected: jitlink::Section &HeaderSection); MachOPlatform &MOP; + MachOPlatform::HeaderOptions Opts; private: struct HeaderSymbol { @@ -365,8 +399,10 @@ private: /// Simple MachO header graph builder. inline std::unique_ptr -MachOPlatform::buildSimpleMachOHeaderMU(MachOPlatform &MOP) { - return std::make_unique(MOP, MOP.MachOHeaderStartSymbol); +MachOPlatform::buildSimpleMachOHeaderMU(MachOPlatform &MOP, + HeaderOptions Opts) { + return std::make_unique(MOP, MOP.MachOHeaderStartSymbol, + std::move(Opts)); } struct MachOHeaderInfo { diff --git a/llvm/include/llvm/ExecutionEngine/RuntimeDyldChecker.h b/llvm/include/llvm/ExecutionEngine/RuntimeDyldChecker.h index 80e4bbf4943..034c134a137 100644 --- a/llvm/include/llvm/ExecutionEngine/RuntimeDyldChecker.h +++ b/llvm/include/llvm/ExecutionEngine/RuntimeDyldChecker.h @@ -154,7 +154,7 @@ public: using GetSectionInfoFunction = std::function( StringRef FileName, StringRef SectionName)>; using GetStubInfoFunction = std::function( - StringRef StubContainer, StringRef TargetName)>; + StringRef StubContainer, StringRef TargetName, StringRef StubKindFilter)>; using GetGOTInfoFunction = std::function( StringRef GOTContainer, StringRef TargetName)>; diff --git a/llvm/include/llvm/Frontend/Offloading/OffloadWrapper.h b/llvm/include/llvm/Frontend/Offloading/OffloadWrapper.h new file mode 100644 index 00000000000..e3ded00b573 --- /dev/null +++ b/llvm/include/llvm/Frontend/Offloading/OffloadWrapper.h @@ -0,0 +1,52 @@ +//===- OffloadWrapper.h --r-------------------------------------*- C++ -*-===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +#ifndef LLVM_FRONTEND_OFFLOADING_OFFLOADWRAPPER_H +#define LLVM_FRONTEND_OFFLOADING_OFFLOADWRAPPER_H + +#include "llvm/ADT/ArrayRef.h" +#include "llvm/IR/Module.h" + +namespace llvm { +namespace offloading { +using EntryArrayTy = std::pair; +/// Wraps the input device images into the module \p M as global symbols and +/// registers the images with the OpenMP Offloading runtime libomptarget. +/// \param EntryArray Optional pair pointing to the `__start` and `__stop` +/// symbols holding the `__tgt_offload_entry` array. +/// \param Suffix An optional suffix appended to the emitted symbols. +llvm::Error wrapOpenMPBinaries(llvm::Module &M, + llvm::ArrayRef> Images, + EntryArrayTy EntryArray, + llvm::StringRef Suffix = ""); + +/// Wraps the input fatbinary image into the module \p M as global symbols and +/// registers the images with the CUDA runtime. +/// \param EntryArray Optional pair pointing to the `__start` and `__stop` +/// symbols holding the `__tgt_offload_entry` array. +/// \param Suffix An optional suffix appended to the emitted symbols. +/// \param EmitSurfacesAndTextures Whether to emit surface and textures +/// registration code. It defaults to false. +llvm::Error wrapCudaBinary(llvm::Module &M, llvm::ArrayRef Images, + EntryArrayTy EntryArray, llvm::StringRef Suffix = "", + bool EmitSurfacesAndTextures = true); + +/// Wraps the input bundled image into the module \p M as global symbols and +/// registers the images with the HIP runtime. +/// \param EntryArray Optional pair pointing to the `__start` and `__stop` +/// symbols holding the `__tgt_offload_entry` array. +/// \param Suffix An optional suffix appended to the emitted symbols. +/// \param EmitSurfacesAndTextures Whether to emit surface and textures +/// registration code. It defaults to false. +llvm::Error wrapHIPBinary(llvm::Module &M, llvm::ArrayRef Images, + EntryArrayTy EntryArray, llvm::StringRef Suffix = "", + bool EmitSurfacesAndTextures = true); +} // namespace offloading +} // namespace llvm + +#endif // LLVM_FRONTEND_OFFLOADING_OFFLOADWRAPPER_H diff --git a/llvm/include/llvm/Frontend/Offloading/Utility.h b/llvm/include/llvm/Frontend/Offloading/Utility.h index 520c192996a..f54dd7ba7ab 100644 --- a/llvm/include/llvm/Frontend/Offloading/Utility.h +++ b/llvm/include/llvm/Frontend/Offloading/Utility.h @@ -61,6 +61,12 @@ StructType *getEntryTy(Module &M); void emitOffloadingEntry(Module &M, Constant *Addr, StringRef Name, uint64_t Size, int32_t Flags, int32_t Data, StringRef SectionName); +/// Create a constant struct initializer used to register this global at +/// runtime. +/// \return the constant struct and the global variable holding the symbol name. +std::pair +getOffloadingEntryInitializer(Module &M, Constant *Addr, StringRef Name, + uint64_t Size, int32_t Flags, int32_t Data); /// Creates a pair of globals used to iterate the array of offloading entries by /// accessing the section variables provided by the linker. diff --git a/llvm/include/llvm/IR/Attributes.h b/llvm/include/llvm/IR/Attributes.h index db33b540047..a4ebe5d732f 100644 --- a/llvm/include/llvm/IR/Attributes.h +++ b/llvm/include/llvm/IR/Attributes.h @@ -86,7 +86,7 @@ public: None, ///< No attributes have been set #define GET_ATTR_ENUM #include "llvm/IR/Attributes.inc" - EndAttrKinds, ///< Sentinal value useful for loops + EndAttrKinds, ///< Sentinel value useful for loops EmptyKey, ///< Use as Empty key for DenseMap of AttrKind TombstoneKey, ///< Use as Tombstone key for DenseMap of AttrKind }; diff --git a/llvm/include/llvm/IR/CallingConv.h b/llvm/include/llvm/IR/CallingConv.h index 3a522c239ad..bca31b2572e 100644 --- a/llvm/include/llvm/IR/CallingConv.h +++ b/llvm/include/llvm/IR/CallingConv.h @@ -251,6 +251,16 @@ namespace CallingConv { /// Used by GraalVM. Two additional registers are reserved. GRAAL = 107, + /// Calling convention used in the ARM64EC ABI to implement calls between + /// x64 code and thunks. This is basically the x64 calling convention using + /// ARM64 register names. The first parameter is mapped to x9. + ARM64EC_Thunk_X64 = 108, + + /// Calling convention used in the ARM64EC ABI to implement calls between + /// ARM64 code and thunks. This is just the ARM64 calling convention, + /// except that the first parameter is mapped to x9. + ARM64EC_Thunk_Native = 109, + /// The highest possible ID. Must be some 2^k - 1. MaxID = 1023 }; diff --git a/llvm/include/llvm/IR/DebugInfo.h b/llvm/include/llvm/IR/DebugInfo.h index 36ef77f9505..b2f07939340 100644 --- a/llvm/include/llvm/IR/DebugInfo.h +++ b/llvm/include/llvm/IR/DebugInfo.h @@ -40,8 +40,9 @@ class Module; /// Finds dbg.declare intrinsics declaring local variables as living in the /// memory that 'V' points to. -void findDbgDeclares(SmallVectorImpl &DbgUsers, Value *V, - SmallVectorImpl *DPValues = nullptr); +TinyPtrVector findDbgDeclares(Value *V); +/// As above, for DPVDeclares. +TinyPtrVector findDPVDeclares(Value *V); /// Finds the llvm.dbg.value intrinsics describing a value. void findDbgValues(SmallVectorImpl &DbgValues, @@ -57,6 +58,7 @@ DISubprogram *getDISubprogram(const MDNode *Scope); /// Produce a DebugLoc to use for each dbg.declare that is promoted to a /// dbg.value. DebugLoc getDebugValueLoc(DbgVariableIntrinsic *DII); +DebugLoc getDebugValueLoc(DPValue *DPV); /// Strip debug info in the module if it exists. /// @@ -191,6 +193,12 @@ inline AssignmentInstRange getAssignmentInsts(const DbgAssignIntrinsic *DAI) { return getAssignmentInsts(DAI->getAssignID()); } +inline AssignmentInstRange getAssignmentInsts(const DPValue *DPV) { + assert(DPV->isDbgAssign() && + "Can't get assignment instructions for non-assign DPV!"); + return getAssignmentInsts(DPV->getAssignID()); +} + // // Utilities for enumerating llvm.dbg.assign intrinsic from an assignment ID. // @@ -223,6 +231,12 @@ inline AssignmentMarkerRange getAssignmentMarkers(const Instruction *Inst) { return make_range(Value::user_iterator(), Value::user_iterator()); } +inline SmallVector getDPVAssignmentMarkers(const Instruction *Inst) { + if (auto *ID = Inst->getMetadata(LLVMContext::MD_DIAssignID)) + return cast(ID)->getAllDPValueUsers(); + return {}; +} + /// Delete the llvm.dbg.assign intrinsics linked to \p Inst. void deleteAssignmentMarkers(const Instruction *Inst); @@ -243,7 +257,11 @@ void deleteAll(Function *F); /// Result contains a zero-sized fragment if there's no intersect. bool calculateFragmentIntersect( const DataLayout &DL, const Value *Dest, uint64_t SliceOffsetInBits, - uint64_t SliceSizeInBits, const DbgAssignIntrinsic *DAI, + uint64_t SliceSizeInBits, const DbgAssignIntrinsic *DbgAssign, + std::optional &Result); +bool calculateFragmentIntersect( + const DataLayout &DL, const Value *Dest, uint64_t SliceOffsetInBits, + uint64_t SliceSizeInBits, const DPValue *DPVAssign, std::optional &Result); /// Helper struct for trackAssignments, below. We don't use the similar @@ -258,6 +276,8 @@ struct VarRecord { VarRecord(DbgVariableIntrinsic *DVI) : Var(DVI->getVariable()), DL(getDebugValueLoc(DVI)) {} + VarRecord(DPValue *DPV) + : Var(DPV->getVariable()), DL(getDebugValueLoc(DPV)) {} VarRecord(DILocalVariable *Var, DILocation *DL) : Var(Var), DL(DL) {} friend bool operator<(const VarRecord &LHS, const VarRecord &RHS) { return std::tie(LHS.Var, LHS.DL) < std::tie(RHS.Var, RHS.DL); diff --git a/llvm/include/llvm/IR/DebugInfoMetadata.h b/llvm/include/llvm/IR/DebugInfoMetadata.h index f521862b1a5..156f6eb4925 100644 --- a/llvm/include/llvm/IR/DebugInfoMetadata.h +++ b/llvm/include/llvm/IR/DebugInfoMetadata.h @@ -323,6 +323,10 @@ public: // This node has no operands to replace. void replaceOperandWith(unsigned I, Metadata *New) = delete; + SmallVector getAllDPValueUsers() { + return Context.getReplaceableUses()->getAllDPValueUsers(); + } + static DIAssignID *getDistinct(LLVMContext &Context) { return getImpl(Context, Distinct); } diff --git a/llvm/include/llvm/IR/DebugProgramInstruction.h b/llvm/include/llvm/IR/DebugProgramInstruction.h index 8230070343e..737417fb9b9 100644 --- a/llvm/include/llvm/IR/DebugProgramInstruction.h +++ b/llvm/include/llvm/IR/DebugProgramInstruction.h @@ -47,10 +47,12 @@ #ifndef LLVM_IR_DEBUGPROGRAMINSTRUCTION_H #define LLVM_IR_DEBUGPROGRAMINSTRUCTION_H -#include "llvm/ADT/ilist_node.h" #include "llvm/ADT/ilist.h" +#include "llvm/ADT/ilist_node.h" #include "llvm/ADT/iterator.h" #include "llvm/IR/DebugLoc.h" +#include "llvm/IR/Instruction.h" +#include "llvm/IR/SymbolTableListTraits.h" namespace llvm { @@ -59,6 +61,7 @@ class BasicBlock; class MDNode; class Module; class DbgVariableIntrinsic; +class DIAssignID; class DPMarker; class DPValue; class raw_ostream; @@ -81,6 +84,7 @@ class DPValue : public ilist_node, private DebugValueUser { DILocalVariable *Variable; DIExpression *Expression; DebugLoc DbgLoc; + DIExpression *AddressExpression; public: void deleteInstr(); @@ -91,12 +95,16 @@ public: void removeFromParent(); void eraseFromParent(); + DPValue *getNextNode() { return &*std::next(getIterator()); } + DPValue *getPrevNode() { return &*std::prev(getIterator()); } + using self_iterator = simple_ilist::iterator; using const_self_iterator = simple_ilist::const_iterator; enum class LocationType { Declare, Value, + Assign, End, ///< Marks the end of the concrete types. Any, ///< To indicate all LocationTypes in searches. @@ -117,6 +125,32 @@ public: /// assigning \p Location to the DV / Expr / DI variable. DPValue(Metadata *Location, DILocalVariable *DV, DIExpression *Expr, const DILocation *DI, LocationType Type = LocationType::Value); + DPValue(Metadata *Value, DILocalVariable *Variable, DIExpression *Expression, + DIAssignID *AssignID, Metadata *Address, + DIExpression *AddressExpression, const DILocation *DI); + + static DPValue *createDPVAssign(Value *Val, DILocalVariable *Variable, + DIExpression *Expression, + DIAssignID *AssignID, Value *Address, + DIExpression *AddressExpression, + const DILocation *DI); + static DPValue *createLinkedDPVAssign(Instruction *LinkedInstr, Value *Val, + DILocalVariable *Variable, + DIExpression *Expression, + Value *Address, + DIExpression *AddressExpression, + const DILocation *DI); + + static DPValue *createDPValue(Value *Location, DILocalVariable *DV, + DIExpression *Expr, const DILocation *DI); + static DPValue *createDPValue(Value *Location, DILocalVariable *DV, + DIExpression *Expr, const DILocation *DI, + DPValue &InsertBefore); + static DPValue *createDPVDeclare(Value *Address, DILocalVariable *DV, + DIExpression *Expr, const DILocation *DI); + static DPValue *createDPVDeclare(Value *Address, DILocalVariable *DV, + DIExpression *Expr, const DILocation *DI, + DPValue &InsertBefore); /// Iterator for ValueAsMetadata that internally uses direct pointer iteration /// over either a ValueAsMetadata* or a ValueAsMetadata**, dereferencing to the @@ -166,6 +200,9 @@ public: } }; + bool isDbgDeclare() { return Type == LocationType::Declare; } + bool isDbgValue() { return Type == LocationType::Value; } + /// Get the locations corresponding to the variable referenced by the debug /// info intrinsic. Depending on the intrinsic, this could be the /// variable's value or its address. @@ -194,7 +231,7 @@ public: /// Does this describe the address of a local variable. True for dbg.addr /// and dbg.declare, but not dbg.value, which describes its value. - bool isAddressOfVariable() const { return Type != LocationType::Value; } + bool isAddressOfVariable() const { return Type == LocationType::Declare; } LocationType getType() const { return Type; } DebugLoc getDebugLoc() const { return DbgLoc; } @@ -207,7 +244,15 @@ public: DIExpression *getExpression() const { return Expression; } - Metadata *getRawLocation() const { return DebugValue; } + /// Returns the metadata operand for the first location description. i.e., + /// dbg intrinsic dbg.value,declare operand and dbg.assign 1st location + /// operand (the "value componenet"). Note the operand (singular) may be + /// a DIArgList which is a list of values. + Metadata *getRawLocation() const { return DebugValues[0]; } + + Value *getValue(unsigned OpIdx = 0) const { + return getVariableLocationOp(OpIdx); + } /// Use of this should generally be avoided; instead, /// replaceVariableLocationOp and addVariableLocationOps should be used where @@ -217,23 +262,58 @@ public: (isa(NewLocation) || isa(NewLocation) || isa(NewLocation)) && "Location for a DPValue must be either ValueAsMetadata or DIArgList"); - resetDebugValue(NewLocation); + resetDebugValue(0, NewLocation); } /// Get the size (in bits) of the variable, or fragment of the variable that /// is described. std::optional getFragmentSizeInBits() const; + bool isEquivalentTo(const DPValue &Other) { + return std::tie(Type, DebugValues, Variable, Expression, DbgLoc) == + std::tie(Other.Type, Other.DebugValues, Other.Variable, + Other.Expression, Other.DbgLoc); + } + // Matches the definition of the Instruction version, equivalent to above but + // without checking DbgLoc. + bool isIdenticalToWhenDefined(const DPValue &Other) { + return std::tie(Type, DebugValues, Variable, Expression) == + std::tie(Other.Type, Other.DebugValues, Other.Variable, + Other.Expression); + } + + /// @name DbgAssign Methods + /// @{ + bool isDbgAssign() const { return getType() == LocationType::Assign; } + + Value *getAddress() const; + Metadata *getRawAddress() const { + return isDbgAssign() ? DebugValues[1] : DebugValues[0]; + } + Metadata *getRawAssignID() const { return DebugValues[2]; } + DIAssignID *getAssignID() const; + DIExpression *getAddressExpression() const { return AddressExpression; } + void setAddressExpression(DIExpression *NewExpr) { + AddressExpression = NewExpr; + } + void setAssignId(DIAssignID *New); + void setAddress(Value *V) { resetDebugValue(1, ValueAsMetadata::get(V)); } + /// Kill the address component. + void setKillAddress(); + /// Check whether this kills the address component. This doesn't take into + /// account the position of the intrinsic, therefore a returned value of false + /// does not guarentee the address is a valid location for the variable at the + /// intrinsic's position in IR. + bool isKillAddress() const; + + /// @} + DPValue *clone() const; /// Convert this DPValue back into a dbg.value intrinsic. /// \p InsertBefore Optional position to insert this intrinsic. /// \returns A new dbg.value intrinsic representiung this DPValue. DbgVariableIntrinsic *createDebugIntrinsic(Module *M, Instruction *InsertBefore) const; - /// Handle changes to the location of the Value(s) that we refer to happening - /// "under our feet". - void handleChangedLocation(Metadata *NewLocation); - void setMarker(DPMarker *M) { Marker = M; } DPMarker *getMarker() { return Marker; } @@ -251,6 +331,13 @@ public: LLVMContext &getContext(); const LLVMContext &getContext() const; + /// Insert this DPValue prior to \p InsertBefore. Must not be called if this + /// is already contained in a DPMarker. + void insertBefore(DPValue *InsertBefore); + void insertAfter(DPValue *InsertAfter); + void moveBefore(DPValue *MoveBefore); + void moveAfter(DPValue *MoveAfter); + void print(raw_ostream &O, bool IsForDebug = false) const; void print(raw_ostream &ROS, ModuleSlotTracker &MST, bool IsForDebug) const; }; @@ -309,6 +396,8 @@ public: /// Produce a range over all the DPValues in this Marker. iterator_range::iterator> getDbgValueRange(); + iterator_range::const_iterator> + getDbgValueRange() const; /// Transfer any DPValues from \p Src into this DPMarker. If \p InsertAtHead /// is true, place them before existing DPValues, otherwise afterwards. void absorbDebugValues(DPMarker &Src, bool InsertAtHead); @@ -320,6 +409,10 @@ public: /// Insert a DPValue into this DPMarker, at the end of the list. If /// \p InsertAtHead is true, at the start. void insertDPValue(DPValue *New, bool InsertAtHead); + /// Insert a DPValue prior to a DPValue contained within this marker. + void insertDPValue(DPValue *New, DPValue *InsertBefore); + /// Insert a DPValue after a DPValue contained within this marker. + void insertDPValueAfter(DPValue *New, DPValue *InsertAfter); /// Clone all DPMarkers from \p From into this marker. There are numerous /// options to customise the source/destination, due to gnarliness, see class /// comment. diff --git a/llvm/include/llvm/IR/Function.h b/llvm/include/llvm/IR/Function.h index 6ac768b5139..cb87a449803 100644 --- a/llvm/include/llvm/IR/Function.h +++ b/llvm/include/llvm/IR/Function.h @@ -722,8 +722,9 @@ public: /// Insert \p BB in the basic block list at \p Position. \Returns an iterator /// to the newly inserted BB. Function::iterator insert(Function::iterator Position, BasicBlock *BB) { + Function::iterator FIt = BasicBlocks.insert(Position, BB); BB->setIsNewDbgInfoFormat(IsNewDbgInfoFormat); - return BasicBlocks.insert(Position, BB); + return FIt; } /// Transfer all blocks from \p FromF to this function at \p ToIt. diff --git a/llvm/include/llvm/IR/GlobalObject.h b/llvm/include/llvm/IR/GlobalObject.h index ae8e6168244..b6a974d8bb9 100644 --- a/llvm/include/llvm/IR/GlobalObject.h +++ b/llvm/include/llvm/IR/GlobalObject.h @@ -133,6 +133,7 @@ public: using Value::addMetadata; using Value::clearMetadata; using Value::eraseMetadata; + using Value::eraseMetadataIf; using Value::getAllMetadata; using Value::getMetadata; using Value::hasMetadata; diff --git a/llvm/include/llvm/IR/GlobalValue.h b/llvm/include/llvm/IR/GlobalValue.h index e97a7f2b963..aa8188cd99f 100644 --- a/llvm/include/llvm/IR/GlobalValue.h +++ b/llvm/include/llvm/IR/GlobalValue.h @@ -564,8 +564,7 @@ public: /// arbitrary GlobalValue, this is not the function you're looking for; see /// Mangler.h. static StringRef dropLLVMManglingEscape(StringRef Name) { - if (!Name.empty() && Name[0] == '\1') - return Name.substr(1); + Name.consume_front("\1"); return Name; } diff --git a/llvm/include/llvm/IR/IRBuilder.h b/llvm/include/llvm/IR/IRBuilder.h index 8863ca8eba4..f2922311097 100644 --- a/llvm/include/llvm/IR/IRBuilder.h +++ b/llvm/include/llvm/IR/IRBuilder.h @@ -1974,6 +1974,16 @@ public: return CreateConstInBoundsGEP2_32(Ty, Ptr, 0, Idx, Name); } + Value *CreatePtrAdd(Value *Ptr, Value *Offset, const Twine &Name = "", + bool IsInBounds = false) { + return CreateGEP(getInt8Ty(), Ptr, Offset, Name, IsInBounds); + } + + Value *CreateInBoundsPtrAdd(Value *Ptr, Value *Offset, + const Twine &Name = "") { + return CreateGEP(getInt8Ty(), Ptr, Offset, Name, /*IsInBounds*/ true); + } + /// Same as CreateGlobalString, but return a pointer with "i8*" type /// instead of a pointer to array of i8. /// diff --git a/llvm/include/llvm/IR/Instruction.h b/llvm/include/llvm/IR/Instruction.h index 0211b507613..fcd2ba838e7 100644 --- a/llvm/include/llvm/IR/Instruction.h +++ b/llvm/include/llvm/IR/Instruction.h @@ -384,6 +384,9 @@ public: void copyMetadata(const Instruction &SrcInst, ArrayRef WL = ArrayRef()); + /// Erase all metadata that matches the predicate. + void eraseMetadataIf(function_ref Pred); + /// If the instruction has "branch_weights" MD_prof metadata and the MDNode /// has three operands (including name string), swap the order of the /// metadata. diff --git a/llvm/include/llvm/IR/Intrinsics.td b/llvm/include/llvm/IR/Intrinsics.td index b54c697296b..3c19c7b0636 100644 --- a/llvm/include/llvm/IR/Intrinsics.td +++ b/llvm/include/llvm/IR/Intrinsics.td @@ -1991,6 +1991,16 @@ let IntrProperties = [IntrNoMem, IntrNoSync, IntrWillReturn] in { LLVMMatchType<0>, LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>, llvm_i32_ty]>; + def int_vp_minimum : DefaultAttrsIntrinsic<[ llvm_anyvector_ty ], + [ LLVMMatchType<0>, + LLVMMatchType<0>, + LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>, + llvm_i32_ty]>; + def int_vp_maximum : DefaultAttrsIntrinsic<[ llvm_anyvector_ty ], + [ LLVMMatchType<0>, + LLVMMatchType<0>, + LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>, + llvm_i32_ty]>; def int_vp_copysign : DefaultAttrsIntrinsic<[ llvm_anyvector_ty ], [ LLVMMatchType<0>, LLVMMatchType<0>, diff --git a/llvm/include/llvm/IR/IntrinsicsAArch64.td b/llvm/include/llvm/IR/IntrinsicsAArch64.td index acff5c20b1b..921e5b95ae0 100644 --- a/llvm/include/llvm/IR/IntrinsicsAArch64.td +++ b/llvm/include/llvm/IR/IntrinsicsAArch64.td @@ -3095,26 +3095,14 @@ let TargetPrefix = "aarch64" in { [llvm_anyvector_ty, LLVMMatchType<0>, LLVMMatchType<0>, LLVMMatchType<0>], [IntrNoMem]>; - class SME2_CVT_FtoI_VG2_Intrinsic + class SME2_CVT_X2_Intrinsic : DefaultAttrsIntrinsic<[llvm_anyvector_ty, LLVMMatchType<0>], - [LLVMVectorOfBitcastsToInt<0>, LLVMVectorOfBitcastsToInt<0>], + [llvm_anyvector_ty, LLVMMatchType<1>], [IntrNoMem]>; - class SME2_CVT_ItoF_VG2_Intrinsic - : DefaultAttrsIntrinsic<[LLVMVectorOfBitcastsToInt<0>, LLVMVectorOfBitcastsToInt<0>], - [llvm_anyvector_ty, LLVMMatchType<0>], - [IntrNoMem]>; - - class SME2_CVT_FtoI_VG4_Intrinsic + class SME2_CVT_X4_Intrinsic : DefaultAttrsIntrinsic<[llvm_anyvector_ty, LLVMMatchType<0>, LLVMMatchType<0>, LLVMMatchType<0>], - [LLVMVectorOfBitcastsToInt<0>, LLVMVectorOfBitcastsToInt<0>, - LLVMVectorOfBitcastsToInt<0>, LLVMVectorOfBitcastsToInt<0>], - [IntrNoMem]>; - - class SME2_CVT_ItoF_VG4_Intrinsic - : DefaultAttrsIntrinsic<[LLVMVectorOfBitcastsToInt<0>, LLVMVectorOfBitcastsToInt<0>, - LLVMVectorOfBitcastsToInt<0>, LLVMVectorOfBitcastsToInt<0>], - [llvm_anyvector_ty, LLVMMatchType<0>, LLVMMatchType<0>, LLVMMatchType<0>], + [llvm_anyvector_ty, LLVMMatchType<1>, LLVMMatchType<1>, LLVMMatchType<1>], [IntrNoMem]>; class SME2_BFMLS_Intrinsic @@ -3403,14 +3391,14 @@ let TargetPrefix = "aarch64" in { // def int_aarch64_sve_fcvt_x2 : SME2_CVT_VG2_SINGLE_Intrinsic; def int_aarch64_sve_bfcvt_x2 : SME2_CVT_VG2_SINGLE_BF16_Intrinsic; - def int_aarch64_sve_fcvts_x2 : SME2_CVT_FtoI_VG2_Intrinsic; - def int_aarch64_sve_fcvtu_x2 : SME2_CVT_FtoI_VG2_Intrinsic; - def int_aarch64_sve_scvtf_x2 : SME2_CVT_ItoF_VG2_Intrinsic; - def int_aarch64_sve_ucvtf_x2 : SME2_CVT_ItoF_VG2_Intrinsic; - def int_aarch64_sve_fcvts_x4 : SME2_CVT_FtoI_VG4_Intrinsic; - def int_aarch64_sve_fcvtu_x4 : SME2_CVT_FtoI_VG4_Intrinsic; - def int_aarch64_sve_scvtf_x4 : SME2_CVT_ItoF_VG4_Intrinsic; - def int_aarch64_sve_ucvtf_x4 : SME2_CVT_ItoF_VG4_Intrinsic; + def int_aarch64_sve_fcvtzs_x2 : SME2_CVT_X2_Intrinsic; + def int_aarch64_sve_fcvtzu_x2 : SME2_CVT_X2_Intrinsic; + def int_aarch64_sve_scvtf_x2 : SME2_CVT_X2_Intrinsic; + def int_aarch64_sve_ucvtf_x2 : SME2_CVT_X2_Intrinsic; + def int_aarch64_sve_fcvtzs_x4 : SME2_CVT_X4_Intrinsic; + def int_aarch64_sve_fcvtzu_x4 : SME2_CVT_X4_Intrinsic; + def int_aarch64_sve_scvtf_x4 : SME2_CVT_X4_Intrinsic; + def int_aarch64_sve_ucvtf_x4 : SME2_CVT_X4_Intrinsic; // // Multi-vector saturating extract narrow diff --git a/llvm/include/llvm/IR/IntrinsicsAMDGPU.td b/llvm/include/llvm/IR/IntrinsicsAMDGPU.td index e5596258847..e6db9da5526 100644 --- a/llvm/include/llvm/IR/IntrinsicsAMDGPU.td +++ b/llvm/include/llvm/IR/IntrinsicsAMDGPU.td @@ -311,6 +311,17 @@ def int_amdgcn_iglp_opt : ClangBuiltin<"__builtin_amdgcn_iglp_opt">, def int_amdgcn_s_waitcnt : ClangBuiltin<"__builtin_amdgcn_s_waitcnt">, Intrinsic<[], [llvm_i32_ty], [ImmArg>, IntrNoMem, IntrHasSideEffects, IntrWillReturn, IntrNoCallback, IntrNoFree]>; +// GFX12 intrinsics +class AMDGPUWaitIntrinsic : + Intrinsic<[], [llvm_i16_ty], [ImmArg>, IntrNoMem, IntrHasSideEffects, IntrWillReturn, IntrNoCallback, IntrNoFree]>; +def int_amdgcn_s_wait_bvhcnt : AMDGPUWaitIntrinsic; +def int_amdgcn_s_wait_dscnt : AMDGPUWaitIntrinsic; +def int_amdgcn_s_wait_expcnt : AMDGPUWaitIntrinsic; +def int_amdgcn_s_wait_kmcnt : AMDGPUWaitIntrinsic; +def int_amdgcn_s_wait_loadcnt : AMDGPUWaitIntrinsic; +def int_amdgcn_s_wait_samplecnt : AMDGPUWaitIntrinsic; +def int_amdgcn_s_wait_storecnt : AMDGPUWaitIntrinsic; + def int_amdgcn_div_scale : DefaultAttrsIntrinsic< // 1st parameter: Numerator // 2nd parameter: Denominator @@ -849,7 +860,6 @@ class AMDGPUImageDimIntrinsic.DmaskArgIndex>>]), @@ -1025,10 +1035,16 @@ defset list AMDGPUImageDimAtomicIntrinsics = { defm int_amdgcn_image_atomic_xor : AMDGPUImageDimAtomic<"ATOMIC_XOR">; defm int_amdgcn_image_atomic_inc : AMDGPUImageDimAtomic<"ATOMIC_INC">; defm int_amdgcn_image_atomic_dec : AMDGPUImageDimAtomic<"ATOMIC_DEC">; + defm int_amdgcn_image_atomic_add_flt : AMDGPUImageDimFloatAtomic<"ATOMIC_ADD_FLT">; + defm int_amdgcn_image_atomic_min_flt : AMDGPUImageDimFloatAtomic<"ATOMIC_MIN_FLT">; + defm int_amdgcn_image_atomic_max_flt : AMDGPUImageDimFloatAtomic<"ATOMIC_MAX_FLT">; defm int_amdgcn_image_atomic_cmpswap : AMDGPUImageDimAtomicX<"ATOMIC_CMPSWAP", [AMDGPUArg, "src">, AMDGPUArg, "cmp">]>; + + defm int_amdgcn_image_atomic_pk_add_f16 : AMDGPUImageDimFloatAtomic<"ATOMIC_PK_ADD_F16">; + defm int_amdgcn_image_atomic_pk_add_bf16 : AMDGPUImageDimFloatAtomic<"ATOMIC_PK_ADD_BF16">; } ////////////////////////////////////////////////////////////////////////// @@ -1071,7 +1087,9 @@ def int_amdgcn_s_buffer_load : DefaultAttrsIntrinsic < [llvm_any_ty], [llvm_v4i32_ty, // rsrc(SGPR) llvm_i32_ty, // byte offset - llvm_i32_ty], // cachepolicy(imm; bit 0 = glc, bit 2 = dlc) + llvm_i32_ty], // cachepolicy(imm; bit 0 = glc, bit 1 = slc, bit 2 = dlc; + // gfx12+ imm: bits [0-2] = th, bits [3-4] = scope) + // Note: volatile bit is **not** permitted here. [IntrNoMem, ImmArg>]>, AMDGPURsrcIntrinsic<0>; @@ -1099,6 +1117,10 @@ def int_amdgcn_buffer_store : AMDGPUBufferStore; // The versions of these intrinsics that take <4 x i32> arguments are deprecated // in favor of their .ptr.buffer variants that take ptr addrspace(8) arguments, // which allow for improved reasoning about memory accesses. +// +// Note that in the cachepolicy for all these intrinsics, bit 31 is not preserved +// through to final assembly selection and is used to signal that the buffer +// operation is volatile. class AMDGPURawBufferLoad : DefaultAttrsIntrinsic < [data_ty], [llvm_v4i32_ty, // rsrc(SGPR) @@ -1106,8 +1128,14 @@ class AMDGPURawBufferLoad : DefaultAttrsIntrinsi llvm_i32_ty, // soffset(SGPR/imm, excluded from bounds checking and swizzling) llvm_i32_ty], // auxiliary data (imm, cachepolicy (bit 0 = glc, // bit 1 = slc, - // bit 2 = dlc on gfx10+), - // swizzled buffer (bit 3 = swz)) + // bit 2 = dlc on gfx10/gfx11), + // swizzled buffer (bit 3 = swz), + // gfx12+: + // cachepolicy (bits [0-2] = th, + // bits [3-4] = scope) + // swizzled buffer (bit 6 = swz), + // all: + // volatile op (bit 31, stripped at lowering)) [IntrReadMem, ImmArg>], "", [SDNPMemOperand]>, AMDGPURsrcIntrinsic<0>; def int_amdgcn_raw_buffer_load_format : AMDGPURawBufferLoad; @@ -1120,8 +1148,15 @@ class AMDGPURawPtrBufferLoad : DefaultAttrsIntri llvm_i32_ty, // soffset(SGPR/imm, excluded from bounds checking and swizzling) llvm_i32_ty], // auxiliary data (imm, cachepolicy (bit 0 = glc, // bit 1 = slc, - // bit 2 = dlc on gfx10+), - // swizzled buffer (bit 3 = swz)) + // bit 2 = dlc on gfx10/gfx11), + // swizzled buffer (bit 3 = swz), + // gfx12+: + // cachepolicy (bits [0-2] = th, + // bits [3-4] = scope) + // swizzled buffer (bit 6 = swz), + // all: + // volatile op (bit 31, stripped at lowering)) + [IntrArgMemOnly, IntrReadMem, ReadOnly>, NoCapture>, ImmArg>], "", [SDNPMemOperand]>, AMDGPURsrcIntrinsic<0>; @@ -1136,8 +1171,14 @@ class AMDGPUStructBufferLoad : DefaultAttrsIntri llvm_i32_ty, // soffset(SGPR/imm, excluded from bounds checking and swizzling) llvm_i32_ty], // auxiliary data (imm, cachepolicy (bit 0 = glc, // bit 1 = slc, - // bit 2 = dlc on gfx10+), - // swizzled buffer (bit 3 = swz)) + // bit 2 = dlc on gfx10/gfx11), + // swizzled buffer (bit 3 = swz), + // gfx12+: + // cachepolicy (bits [0-2] = th, + // bits [3-4] = scope) + // swizzled buffer (bit 6 = swz), + // all: + // volatile op (bit 31, stripped at lowering)) [IntrReadMem, ImmArg>], "", [SDNPMemOperand]>, AMDGPURsrcIntrinsic<0>; def int_amdgcn_struct_buffer_load_format : AMDGPUStructBufferLoad; @@ -1151,8 +1192,14 @@ class AMDGPUStructPtrBufferLoad : DefaultAttrsIn llvm_i32_ty, // soffset(SGPR/imm, excluded from bounds checking and swizzling) llvm_i32_ty], // auxiliary data (imm, cachepolicy (bit 0 = glc, // bit 1 = slc, - // bit 2 = dlc on gfx10+), - // swizzled buffer (bit 3 = swz)) + // bit 2 = dlc on gfx10/gfx11), + // swizzled buffer (bit 3 = swz), + // gfx12+: + // cachepolicy (bits [0-2] = th, + // bits [3-4] = scope) + // swizzled buffer (bit 6 = swz), + // all: + // volatile op (bit 31, stripped at lowering)) [IntrArgMemOnly, IntrReadMem, ReadOnly>, NoCapture>, ImmArg>], "", [SDNPMemOperand]>, AMDGPURsrcIntrinsic<0>; @@ -1167,8 +1214,14 @@ class AMDGPURawBufferStore : DefaultAttrsIntrins llvm_i32_ty, // soffset(SGPR/imm, excluded from bounds checking and swizzling) llvm_i32_ty], // auxiliary data (imm, cachepolicy (bit 0 = glc, // bit 1 = slc, - // bit 2 = dlc on gfx10+), - // swizzled buffer (bit 3 = swz)) + // bit 2 = dlc on gfx10/gfx11), + // swizzled buffer (bit 3 = swz), + // gfx12+: + // cachepolicy (bits [0-2] = th, + // bits [3-4] = scope) + // swizzled buffer (bit 6 = swz), + // all: + // volatile op (bit 31, stripped at lowering)) [IntrWriteMem, ImmArg>], "", [SDNPMemOperand]>, AMDGPURsrcIntrinsic<1>; def int_amdgcn_raw_buffer_store_format : AMDGPURawBufferStore; @@ -1182,8 +1235,14 @@ class AMDGPURawPtrBufferStore : DefaultAttrsIntr llvm_i32_ty, // soffset(SGPR/imm, excluded from bounds checking and swizzling) llvm_i32_ty], // auxiliary data (imm, cachepolicy (bit 0 = glc, // bit 1 = slc, - // bit 2 = dlc on gfx10+), - // swizzled buffer (bit 3 = swz)) + // bit 2 = dlc on gfx10/gfx11), + // swizzled buffer (bit 3 = swz), + // gfx12+: + // cachepolicy (bits [0-2] = th, + // bits [3-4] = scope) + // swizzled buffer (bit 6 = swz), + // all: + // volatile op (bit 31, stripped at lowering)) [IntrArgMemOnly, IntrWriteMem, WriteOnly>, NoCapture>, ImmArg>], "", [SDNPMemOperand]>, AMDGPURsrcIntrinsic<1>; @@ -1199,8 +1258,14 @@ class AMDGPUStructBufferStore : DefaultAttrsIntr llvm_i32_ty, // soffset(SGPR/imm, excluded from bounds checking and swizzling) llvm_i32_ty], // auxiliary data (imm, cachepolicy (bit 0 = glc, // bit 1 = slc, - // bit 2 = dlc on gfx10+), - // swizzled buffer (bit 3 = swz)) + // bit 2 = dlc on gfx10/gfx11), + // swizzled buffer (bit 3 = swz), + // gfx12+: + // cachepolicy (bits [0-2] = th, + // bits [3-4] = scope) + // swizzled buffer (bit 6 = swz), + // all: + // volatile op (bit 31, stripped at lowering)) [IntrWriteMem, ImmArg>], "", [SDNPMemOperand]>, AMDGPURsrcIntrinsic<1>; def int_amdgcn_struct_buffer_store_format : AMDGPUStructBufferStore; @@ -1215,8 +1280,14 @@ class AMDGPUStructPtrBufferStore : DefaultAttrsI llvm_i32_ty, // soffset(SGPR/imm, excluded from bounds checking and swizzling) llvm_i32_ty], // auxiliary data (imm, cachepolicy (bit 0 = glc, // bit 1 = slc, - // bit 2 = dlc on gfx10+), - // swizzled buffer (bit 3 = swz)) + // bit 2 = dlc on gfx10/gfx11), + // swizzled buffer (bit 3 = swz), + // gfx12+: + // cachepolicy (bits [0-2] = th, + // bits [3-4] = scope) + // swizzled buffer (bit 6 = swz), + // all: + // volatile op (bit 31, stripped at lowering)) [IntrArgMemOnly, IntrWriteMem, WriteOnly>, NoCapture>, ImmArg>], "", [SDNPMemOperand]>, AMDGPURsrcIntrinsic<1>; @@ -1229,7 +1300,7 @@ class AMDGPURawBufferAtomic : Intrinsic < llvm_v4i32_ty, // rsrc(SGPR) llvm_i32_ty, // offset(VGPR/imm, included in bounds checking and swizzling) llvm_i32_ty, // soffset(SGPR/imm, excluded from bounds checking and swizzling) - llvm_i32_ty], // cachepolicy(imm; bit 1 = slc) + llvm_i32_ty], // cachepolicy(imm; bit 1 = slc, ..., bit 31 = volatile) [ImmArg>, IntrWillReturn, IntrNoCallback, IntrNoFree], "", [SDNPMemOperand]>, AMDGPURsrcIntrinsic<1, 0>; def int_amdgcn_raw_buffer_atomic_swap : AMDGPURawBufferAtomic; @@ -1246,6 +1317,7 @@ def int_amdgcn_raw_buffer_atomic_or : AMDGPURawBufferAtomic; def int_amdgcn_raw_buffer_atomic_xor : AMDGPURawBufferAtomic; def int_amdgcn_raw_buffer_atomic_inc : AMDGPURawBufferAtomic; def int_amdgcn_raw_buffer_atomic_dec : AMDGPURawBufferAtomic; +def int_amdgcn_raw_buffer_atomic_cond_sub_u32 : AMDGPURawBufferAtomic; def int_amdgcn_raw_buffer_atomic_cmpswap : Intrinsic< [llvm_anyint_ty], [LLVMMatchType<0>, // src(VGPR) @@ -1253,7 +1325,7 @@ def int_amdgcn_raw_buffer_atomic_cmpswap : Intrinsic< llvm_v4i32_ty, // rsrc(SGPR) llvm_i32_ty, // offset(VGPR/imm, included in bounds checking and swizzling) llvm_i32_ty, // soffset(SGPR/imm, excluded from bounds checking and swizzling) - llvm_i32_ty], // cachepolicy(imm; bit 1 = slc) + llvm_i32_ty], // cachepolicy(imm; bit 1 = slc, ..., bit 31 = volatile) [ImmArg>, IntrWillReturn, IntrNoCallback, IntrNoFree], "", [SDNPMemOperand]>, AMDGPURsrcIntrinsic<2, 0>; @@ -1263,7 +1335,7 @@ class AMDGPURawPtrBufferAtomic : Intrinsic < AMDGPUBufferRsrcTy, // rsrc(SGPR) llvm_i32_ty, // offset(VGPR/imm, included in bounds checking and swizzling) llvm_i32_ty, // soffset(SGPR/imm, excluded from bounds checking and swizzling) - llvm_i32_ty], // cachepolicy(imm; bit 1 = slc) + llvm_i32_ty], // cachepolicy(imm; bit 1 = slc, ..., bit 31 = volatile) [IntrArgMemOnly, NoCapture>, ImmArg>, IntrWillReturn, IntrNoCallback, IntrNoFree], "", [SDNPMemOperand]>, AMDGPURsrcIntrinsic<1, 0>; @@ -1282,6 +1354,7 @@ def int_amdgcn_raw_ptr_buffer_atomic_or : AMDGPURawPtrBufferAtomic; def int_amdgcn_raw_ptr_buffer_atomic_xor : AMDGPURawPtrBufferAtomic; def int_amdgcn_raw_ptr_buffer_atomic_inc : AMDGPURawPtrBufferAtomic; def int_amdgcn_raw_ptr_buffer_atomic_dec : AMDGPURawPtrBufferAtomic; +def int_amdgcn_raw_ptr_buffer_atomic_cond_sub_u32 : AMDGPURawPtrBufferAtomic; def int_amdgcn_raw_ptr_buffer_atomic_cmpswap : Intrinsic< [llvm_anyint_ty], [LLVMMatchType<0>, // src(VGPR) @@ -1289,7 +1362,7 @@ def int_amdgcn_raw_ptr_buffer_atomic_cmpswap : Intrinsic< AMDGPUBufferRsrcTy, // rsrc(SGPR) llvm_i32_ty, // offset(VGPR/imm, included in bounds checking and swizzling) llvm_i32_ty, // soffset(SGPR/imm, excluded from bounds checking and swizzling) - llvm_i32_ty], // cachepolicy(imm; bit 1 = slc) + llvm_i32_ty], // cachepolicy(imm; bit 1 = slc, ..., bit 31 = volatile) [IntrArgMemOnly, NoCapture>, ImmArg>, IntrWillReturn, IntrNoCallback, IntrNoFree], "", [SDNPMemOperand]>, AMDGPURsrcIntrinsic<2, 0>; @@ -1297,6 +1370,26 @@ def int_amdgcn_raw_ptr_buffer_atomic_cmpswap : Intrinsic< // gfx908 intrinsic def int_amdgcn_raw_buffer_atomic_fadd : AMDGPURawBufferAtomic; def int_amdgcn_raw_ptr_buffer_atomic_fadd : AMDGPURawPtrBufferAtomic; +// gfx12+ intrinsic +def int_amdgcn_raw_buffer_atomic_fadd_v2bf16 : Intrinsic < + [llvm_v2bf16_ty], + [llvm_v2bf16_ty, + llvm_v4i32_ty, + llvm_i32_ty, + llvm_i32_ty, + llvm_i32_ty], + [ImmArg>, IntrWillReturn, IntrNoCallback, IntrNoFree], "", [SDNPMemOperand]>, + AMDGPURsrcIntrinsic<1, 0>; +def int_amdgcn_raw_ptr_buffer_atomic_fadd_v2bf16 : Intrinsic < + [llvm_v2bf16_ty], + [llvm_v2bf16_ty, + AMDGPUBufferRsrcTy, + llvm_i32_ty, + llvm_i32_ty, + llvm_i32_ty], + [IntrArgMemOnly, NoCapture>, + ImmArg>, IntrWillReturn, IntrNoCallback, IntrNoFree], "", [SDNPMemOperand]>, + AMDGPURsrcIntrinsic<1, 0>; class AMDGPUStructBufferAtomic : Intrinsic < [data_ty], @@ -1305,7 +1398,7 @@ class AMDGPUStructBufferAtomic : Intrinsic < llvm_i32_ty, // vindex(VGPR) llvm_i32_ty, // offset(VGPR/imm, included in bounds checking and swizzling) llvm_i32_ty, // soffset(SGPR/imm, excluded from bounds checking and swizzling) - llvm_i32_ty], // cachepolicy(imm; bit 1 = slc) + llvm_i32_ty], // cachepolicy(imm; bit 1 = slc, ..., bit 31 = volatile) [ImmArg>, IntrWillReturn, IntrNoCallback, IntrNoFree], "", [SDNPMemOperand]>, AMDGPURsrcIntrinsic<1, 0>; def int_amdgcn_struct_buffer_atomic_swap : AMDGPUStructBufferAtomic; @@ -1320,6 +1413,7 @@ def int_amdgcn_struct_buffer_atomic_or : AMDGPUStructBufferAtomic; def int_amdgcn_struct_buffer_atomic_xor : AMDGPUStructBufferAtomic; def int_amdgcn_struct_buffer_atomic_inc : AMDGPUStructBufferAtomic; def int_amdgcn_struct_buffer_atomic_dec : AMDGPUStructBufferAtomic; +def int_amdgcn_struct_buffer_atomic_cond_sub_u32 : AMDGPUStructBufferAtomic; def int_amdgcn_struct_buffer_atomic_cmpswap : Intrinsic< [llvm_anyint_ty], [LLVMMatchType<0>, // src(VGPR) @@ -1328,7 +1422,7 @@ def int_amdgcn_struct_buffer_atomic_cmpswap : Intrinsic< llvm_i32_ty, // vindex(VGPR) llvm_i32_ty, // offset(VGPR/imm, included in bounds checking and swizzling) llvm_i32_ty, // soffset(SGPR/imm, excluded from bounds checking and swizzling) - llvm_i32_ty], // cachepolicy(imm; bit 1 = slc) + llvm_i32_ty], // cachepolicy(imm; bit 1 = slc, ..., bit 31 = volatile) [ImmArg>, IntrWillReturn, IntrNoCallback, IntrNoFree], "", [SDNPMemOperand]>, AMDGPURsrcIntrinsic<2, 0>; @@ -1339,7 +1433,7 @@ class AMDGPUStructPtrBufferAtomic : Intrinsic < llvm_i32_ty, // vindex(VGPR) llvm_i32_ty, // offset(VGPR/imm, included in bounds checking and swizzling) llvm_i32_ty, // soffset(SGPR/imm, excluded from bounds checking and swizzling) - llvm_i32_ty], // cachepolicy(imm; bit 1 = slc) + llvm_i32_ty], // cachepolicy(imm; bit 1 = slc, ..., bit 31 = volatile) [IntrArgMemOnly, NoCapture>, ImmArg>, IntrWillReturn, IntrNoCallback, IntrNoFree], "", [SDNPMemOperand]>, AMDGPURsrcIntrinsic<1, 0>; @@ -1355,6 +1449,7 @@ def int_amdgcn_struct_ptr_buffer_atomic_or : AMDGPUStructPtrBufferAtomic; def int_amdgcn_struct_ptr_buffer_atomic_xor : AMDGPUStructPtrBufferAtomic; def int_amdgcn_struct_ptr_buffer_atomic_inc : AMDGPUStructPtrBufferAtomic; def int_amdgcn_struct_ptr_buffer_atomic_dec : AMDGPUStructPtrBufferAtomic; +def int_amdgcn_struct_ptr_buffer_atomic_cond_sub_u32 : AMDGPUStructPtrBufferAtomic; def int_amdgcn_struct_ptr_buffer_atomic_cmpswap : Intrinsic< [llvm_anyint_ty], [LLVMMatchType<0>, // src(VGPR) @@ -1363,7 +1458,7 @@ def int_amdgcn_struct_ptr_buffer_atomic_cmpswap : Intrinsic< llvm_i32_ty, // vindex(VGPR) llvm_i32_ty, // offset(VGPR/imm, included in bounds checking and swizzling) llvm_i32_ty, // soffset(SGPR/imm, excluded from bounds checking and swizzling) - llvm_i32_ty], // cachepolicy(imm; bit 1 = slc) + llvm_i32_ty], // cachepolicy(imm; bit 1 = slc, ..., bit 31 = volatile) [IntrArgMemOnly, NoCapture>, ImmArg>, IntrWillReturn, IntrNoCallback, IntrNoFree], "", [SDNPMemOperand]>, AMDGPURsrcIntrinsic<2, 0>; @@ -1371,6 +1466,28 @@ def int_amdgcn_struct_ptr_buffer_atomic_cmpswap : Intrinsic< // gfx908 intrinsic def int_amdgcn_struct_buffer_atomic_fadd : AMDGPUStructBufferAtomic; def int_amdgcn_struct_ptr_buffer_atomic_fadd : AMDGPUStructPtrBufferAtomic; +// gfx12 intrinsic +def int_amdgcn_struct_buffer_atomic_fadd_v2bf16 : Intrinsic < + [llvm_v2bf16_ty], + [llvm_v2bf16_ty, + llvm_v4i32_ty, + llvm_i32_ty, + llvm_i32_ty, + llvm_i32_ty, + llvm_i32_ty], + [ImmArg>, IntrWillReturn, IntrNoCallback, IntrNoFree], "", [SDNPMemOperand]>, + AMDGPURsrcIntrinsic<1, 0>; +def int_amdgcn_struct_ptr_buffer_atomic_fadd_v2bf16 : Intrinsic < + [llvm_v2bf16_ty], + [llvm_v2bf16_ty, + AMDGPUBufferRsrcTy, + llvm_i32_ty, + llvm_i32_ty, + llvm_i32_ty, + llvm_i32_ty], + [IntrArgMemOnly, NoCapture>, + ImmArg>, IntrWillReturn, IntrNoCallback, IntrNoFree], "", [SDNPMemOperand]>, + AMDGPURsrcIntrinsic<1, 0>; // gfx90a intrinsics def int_amdgcn_struct_buffer_atomic_fmin : AMDGPUStructBufferAtomic; @@ -1425,8 +1542,12 @@ def int_amdgcn_raw_tbuffer_load : DefaultAttrsIntrinsic < llvm_i32_ty, // format(imm; bits 3..0 = dfmt, bits 6..4 = nfmt) llvm_i32_ty], // auxiliary data (imm, cachepolicy (bit 0 = glc, // bit 1 = slc, - // bit 2 = dlc on gfx10+), + // bit 2 = dlc on gfx10/gfx11), // swizzled buffer (bit 3 = swz)) + // gfx12+: + // cachepolicy (bits [0-2] = th, + // bits [3-4] = scope) + // swizzled buffer (bit 6 = swz) [IntrReadMem, ImmArg>, ImmArg>], "", [SDNPMemOperand]>, AMDGPURsrcIntrinsic<0>; @@ -1439,8 +1560,13 @@ def int_amdgcn_raw_ptr_tbuffer_load : DefaultAttrsIntrinsic < llvm_i32_ty, // format(imm; bits 3..0 = dfmt, bits 6..4 = nfmt) llvm_i32_ty], // auxiliary data (imm, cachepolicy (bit 0 = glc, // bit 1 = slc, - // bit 2 = dlc on gfx10+), - // swizzled buffer (bit 3 = swz)) + // bit 2 = dlc on gfx10/gfx11), + // swizzled buffer (bit 3 = swz), + // gfx12+: + // cachepolicy (bits [0-2] = th, + // bits [3-4] = scope) + // swizzled buffer (bit 6 = swz) + // volatile op (bit 31, stripped at lowering)) [IntrArgMemOnly, IntrReadMem, ReadOnly>, NoCapture>, ImmArg>, ImmArg>], "", [SDNPMemOperand]>, AMDGPURsrcIntrinsic<0>; @@ -1454,8 +1580,14 @@ def int_amdgcn_raw_tbuffer_store : DefaultAttrsIntrinsic < llvm_i32_ty, // format(imm; bits 3..0 = dfmt, bits 6..4 = nfmt) llvm_i32_ty], // auxiliary data (imm, cachepolicy (bit 0 = glc, // bit 1 = slc, - // bit 2 = dlc on gfx10+), - // swizzled buffer (bit 3 = swz)) + // bit 2 = dlc on gfx10/gfx11), + // swizzled buffer (bit 3 = swz), + // gfx12+: + // cachepolicy (bits [0-2] = th, + // bits [3-4] = scope) + // swizzled buffer (bit 6 = swz), + // all: + // volatile op (bit 31, stripped at lowering)) [IntrWriteMem, ImmArg>, ImmArg>], "", [SDNPMemOperand]>, AMDGPURsrcIntrinsic<1>; @@ -1469,8 +1601,14 @@ def int_amdgcn_raw_ptr_tbuffer_store : DefaultAttrsIntrinsic < llvm_i32_ty, // format(imm; bits 3..0 = dfmt, bits 6..4 = nfmt) llvm_i32_ty], // auxiliary data (imm, cachepolicy (bit 0 = glc, // bit 1 = slc, - // bit 2 = dlc on gfx10+), - // swizzled buffer (bit 3 = swz)) + // bit 2 = dlc on gfx10/gfx11), + // swizzled buffer (bit 3 = swz), + // gfx12+: + // cachepolicy (bits [0-2] = th, + // bits [3-4] = scope) + // swizzled buffer (bit 6 = swz), + // all: + // volatile op (bit 31, stripped at lowering)) [IntrArgMemOnly, IntrWriteMem, WriteOnly>, NoCapture>, ImmArg>, ImmArg>], "", [SDNPMemOperand]>, AMDGPURsrcIntrinsic<1>; @@ -1484,8 +1622,14 @@ def int_amdgcn_struct_tbuffer_load : DefaultAttrsIntrinsic < llvm_i32_ty, // format(imm; bits 3..0 = dfmt, bits 6..4 = nfmt) llvm_i32_ty], // auxiliary data (imm, cachepolicy (bit 0 = glc, // bit 1 = slc, - // bit 2 = dlc on gfx10+), - // swizzled buffer (bit 3 = swz)) + // bit 2 = dlc on gfx10/gfx11), + // swizzled buffer (bit 3 = swz), + // gfx12+: + // cachepolicy (bits [0-2] = th, + // bits [3-4] = scope) + // swizzled buffer (bit 6 = swz), + // all: + // volatile op (bit 31, stripped at lowering)) [IntrReadMem, ImmArg>, ImmArg>], "", [SDNPMemOperand]>, AMDGPURsrcIntrinsic<0>; @@ -1499,8 +1643,14 @@ def int_amdgcn_struct_ptr_tbuffer_load : DefaultAttrsIntrinsic < llvm_i32_ty, // format(imm; bits 3..0 = dfmt, bits 6..4 = nfmt) llvm_i32_ty], // auxiliary data (imm, cachepolicy (bit 0 = glc, // bit 1 = slc, - // bit 2 = dlc on gfx10+), - // swizzled buffer (bit 3 = swz)) + // bit 2 = dlc on gfx10/gfx11), + // swizzled buffer (bit 3 = swz), + // gfx12+: + // cachepolicy (bits [0-2] = th, + // bits [3-4] = scope) + // swizzled buffer (bit 6 = swz), + // all: + // volatile op (bit 31, stripped at lowering)) [IntrArgMemOnly, IntrReadMem, ReadOnly>, NoCapture>, ImmArg>, ImmArg>], "", [SDNPMemOperand]>, AMDGPURsrcIntrinsic<0>; @@ -1515,8 +1665,14 @@ def int_amdgcn_struct_ptr_tbuffer_store : DefaultAttrsIntrinsic < llvm_i32_ty, // format(imm; bits 3..0 = dfmt, bits 6..4 = nfmt) llvm_i32_ty], // auxiliary data (imm, cachepolicy (bit 0 = glc, // bit 1 = slc, - // bit 2 = dlc on gfx10+), - // swizzled buffer (bit 3 = swz)) + // bit 2 = dlc on gfx10/gfx11), + // swizzled buffer (bit 3 = swz), + // gfx12+: + // cachepolicy (bits [0-2] = th, + // bits [3-4] = scope) + // swizzled buffer (bit 6 = swz), + // all: + // volatile op (bit 31, stripped at lowering)) [IntrArgMemOnly, IntrWriteMem, WriteOnly>, NoCapture>, ImmArg>, ImmArg>], "", [SDNPMemOperand]>, AMDGPURsrcIntrinsic<1>; @@ -1531,8 +1687,14 @@ def int_amdgcn_struct_tbuffer_store : DefaultAttrsIntrinsic < llvm_i32_ty, // format(imm; bits 3..0 = dfmt, bits 6..4 = nfmt) llvm_i32_ty], // auxiliary data (imm, cachepolicy (bit 0 = glc, // bit 1 = slc, - // bit 2 = dlc on gfx10+), - // swizzled buffer (bit 3 = swz)) + // bit 2 = dlc on gfx10/gfx11), + // swizzled buffer (bit 3 = swz), + // gfx12+: + // cachepolicy (bits [0-2] = th, + // bits [3-4] = scope) + // swizzled buffer (bit 6 = swz), + // all: + // volatile op (bit 31, stripped at lowering)) [IntrWriteMem, ImmArg>, ImmArg>], "", [SDNPMemOperand]>, AMDGPURsrcIntrinsic<1>; @@ -1592,8 +1754,14 @@ class AMDGPURawBufferLoadLDS : Intrinsic < llvm_i32_ty, // imm offset(imm, included in bounds checking and swizzling) llvm_i32_ty], // auxiliary data (imm, cachepolicy (bit 0 = glc, // bit 1 = slc, - // bit 2 = dlc on gfx10+)) - // swizzled buffer (bit 3 = swz)) + // bit 2 = dlc on gfx10/gfx11)) + // swizzled buffer (bit 3 = swz), + // gfx12+: + // cachepolicy (bits [0-2] = th, + // bits [3-4] = scope) + // swizzled buffer (bit 6 = swz), + // all: + // volatile op (bit 31, stripped at lowering)) [IntrWillReturn, NoCapture>, ImmArg>, ImmArg>, ImmArg>, IntrNoCallback, IntrNoFree], "", [SDNPMemOperand]>, AMDGPURsrcIntrinsic<0>; def int_amdgcn_raw_buffer_load_lds : AMDGPURawBufferLoadLDS; @@ -1608,8 +1776,14 @@ class AMDGPURawPtrBufferLoadLDS : Intrinsic < llvm_i32_ty, // imm offset(imm, included in bounds checking and swizzling) llvm_i32_ty], // auxiliary data (imm, cachepolicy (bit 0 = glc, // bit 1 = slc, - // bit 2 = dlc on gfx10+)) - // swizzled buffer (bit 3 = swz)) + // bit 2 = dlc on gfx10/gfx11)) + // swizzled buffer (bit 3 = swz), + // gfx12+: + // cachepolicy (bits [0-2] = th, + // bits [3-4] = scope) + // swizzled buffer (bit 6 = swz), + // all: + // volatile op (bit 31, stripped at lowering)) [IntrWillReturn, IntrArgMemOnly, ReadOnly>, NoCapture>, WriteOnly>, NoCapture>, @@ -1628,8 +1802,14 @@ class AMDGPUStructBufferLoadLDS : Intrinsic < llvm_i32_ty, // imm offset(imm, included in bounds checking and swizzling) llvm_i32_ty], // auxiliary data (imm, cachepolicy (bit 0 = glc, // bit 1 = slc, - // bit 2 = dlc on gfx10+)) - // swizzled buffer (bit 3 = swz)) + // bit 2 = dlc on gfx10/gfx11)) + // swizzled buffer (bit 3 = swz), + // gfx12+: + // cachepolicy (bits [0-2] = th, + // bits [3-4] = scope) + // swizzled buffer (bit 6 = swz), + // all: + // volatile op (bit 31, stripped at lowering)) [IntrWillReturn, NoCapture>, ImmArg>, ImmArg>, ImmArg>, IntrNoCallback, IntrNoFree], "", [SDNPMemOperand]>, AMDGPURsrcIntrinsic<0>; def int_amdgcn_struct_buffer_load_lds : AMDGPUStructBufferLoadLDS; @@ -1645,8 +1825,14 @@ class AMDGPUStructPtrBufferLoadLDS : Intrinsic < llvm_i32_ty, // imm offset(imm, included in bounds checking and swizzling) llvm_i32_ty], // auxiliary data (imm, cachepolicy (bit 0 = glc, // bit 1 = slc, - // bit 2 = dlc on gfx10+)) - // swizzled buffer (bit 3 = swz)) + // bit 2 = dlc on gfx10/gfx11)) + // swizzled buffer (bit 3 = swz), + // gfx12+: + // cachepolicy (bits [0-2] = th, + // bits [3-4] = scope) + // swizzled buffer (bit 6 = swz), + // all: + // volatile op (bit 31, stripped at lowering)) [IntrWillReturn, IntrArgMemOnly, ReadOnly>, NoCapture>, WriteOnly>, NoCapture>, @@ -1782,6 +1968,8 @@ def int_amdgcn_s_setreg : // not cross a 4Gb address boundary. Use for any other purpose may not // produce the desired results as optimizations may cause code movement, // especially as we explicitly use IntrNoMem to allow optimizations. +// This intrinsic always returns PC sign-extended from 48 bits even if the +// s_getpc_b64 instruction returns a zero-extended value. def int_amdgcn_s_getpc : ClangBuiltin<"__builtin_amdgcn_s_getpc">, DefaultAttrsIntrinsic<[llvm_i64_ty], [], [IntrNoMem, IntrSpeculatable, @@ -2317,8 +2505,12 @@ class AMDGPUGlobalLoadLDS : Intrinsic < llvm_i32_ty, // imm offset (applied to both global and LDS address) llvm_i32_ty], // auxiliary data (imm, cachepolicy (bit 0 = glc/sc0, // bit 1 = slc/sc1, - // bit 2 = dlc on gfx10+)) + // bit 2 = dlc on gfx10/gfx11)) // bit 4 = scc/nt on gfx90a+)) + // gfx12+: + // cachepolicy (bits [0-2] = th, + // bits [3-4] = scope) + // swizzled buffer (bit 6 = swz), [IntrWillReturn, NoCapture>, NoCapture>, ImmArg>, ImmArg>, ImmArg>, IntrNoCallback, IntrNoFree], "", [SDNPMemOperand]>; @@ -2496,6 +2688,30 @@ def int_amdgcn_flat_atomic_fmax_num : AMDGPUAtomicRtn; def int_amdgcn_global_atomic_fmin_num : AMDGPUAtomicRtn; def int_amdgcn_global_atomic_fmax_num : AMDGPUAtomicRtn; +def int_amdgcn_atomic_cond_sub_u32 : AMDGPUAtomicRtn; + +class AMDGPULoadTr: + Intrinsic< + [llvm_any_ty], + [ptr_ty], + [IntrReadMem, IntrWillReturn, IntrConvergent, NoCapture>, IntrNoCallback, IntrNoFree], + "", + [SDNPMemOperand] + >; + +// Wave32 +// <2 x i32> @llvm.amdgcn.global.load.tr.v2i32(ptr addrspace(1)) -> global_load_tr_b64 +// <8 x i16> @llvm.amdgcn.global.load.tr.v8i16(ptr addrspace(1)) -> global_load_tr_b128 +// <8 x half> @llvm.amdgcn.global.load.tr.v8f16(ptr addrspace(1)) -> global_load_tr_b128 +// <8 x bfloat> @llvm.amdgcn.global.load.tr.v8bf16(ptr addrspace(1)) -> global_load_tr_b128 +// Wave64 +// i32 @llvm.amdgcn.global.load.tr.i32(ptr addrspace(1)) -> global_load_tr_b64 +// <4 x i16> @llvm.amdgcn.global.load.tr.v4i16(ptr addrspace(1)) -> global_load_tr_b128 +// <4 x half> @llvm.amdgcn.global.load.tr.v4f16(ptr addrspace(1)) -> global_load_tr_b128 +// <4 x bfloat> @llvm.amdgcn.global.load.tr.v4bf16(ptr addrspace(1)) -> global_load_tr_b128 + +def int_amdgcn_global_load_tr : AMDGPULoadTr; + //===----------------------------------------------------------------------===// // Deep learning intrinsics. //===----------------------------------------------------------------------===// @@ -2693,6 +2909,25 @@ def int_amdgcn_udot8 : ImmArg>, ImmArg>, ImmArg>] >; +// f32 %r = llvm.amdgcn.dot4.f32.type_a.type_b (v4type_a (as i32) %a, v4type_b (as i32) %b, f32 %c) +// %r = %a[0] * %b[0] + %a[1] * %b[1] + %a[2] * %b[2] + %a[3] * %b[3] + %c +class AMDGPU8bitFloatDot4Intrinsic : + ClangBuiltin, + DefaultAttrsIntrinsic< + [llvm_float_ty], // %r + [ + llvm_i32_ty, // %a + llvm_i32_ty, // %b + llvm_float_ty, // %c + ], + [IntrNoMem, IntrSpeculatable] + >; + +def int_amdgcn_dot4_f32_fp8_bf8 : AMDGPU8bitFloatDot4Intrinsic; +def int_amdgcn_dot4_f32_bf8_fp8 : AMDGPU8bitFloatDot4Intrinsic; +def int_amdgcn_dot4_f32_fp8_fp8 : AMDGPU8bitFloatDot4Intrinsic; +def int_amdgcn_dot4_f32_bf8_bf8 : AMDGPU8bitFloatDot4Intrinsic; + //===----------------------------------------------------------------------===// // gfx908 intrinsics // ===----------------------------------------------------------------------===// diff --git a/llvm/include/llvm/IR/IntrinsicsLoongArch.td b/llvm/include/llvm/IR/IntrinsicsLoongArch.td index 685deaec770..9002076e7ae 100644 --- a/llvm/include/llvm/IR/IntrinsicsLoongArch.td +++ b/llvm/include/llvm/IR/IntrinsicsLoongArch.td @@ -122,6 +122,15 @@ def int_loongarch_lddir_d : BaseInt<[llvm_i64_ty], [llvm_i64_ty, llvm_i64_ty], [ImmArg>]>; def int_loongarch_ldpte_d : BaseInt<[], [llvm_i64_ty, llvm_i64_ty], [ImmArg>]>; + +def int_loongarch_frecipe_s : BaseInt<[llvm_float_ty], [llvm_float_ty], + [IntrNoMem]>; +def int_loongarch_frecipe_d : BaseInt<[llvm_double_ty], [llvm_double_ty], + [IntrNoMem]>; +def int_loongarch_frsqrte_s : BaseInt<[llvm_float_ty], [llvm_float_ty], + [IntrNoMem]>; +def int_loongarch_frsqrte_d : BaseInt<[llvm_double_ty], [llvm_double_ty], + [IntrNoMem]>; } // TargetPrefix = "loongarch" /// Vector intrinsic @@ -527,10 +536,12 @@ foreach inst = ["vfmadd_d", "vfmsub_d", "vfnmadd_d", "vfnmsub_d"] in [IntrNoMem]>; foreach inst = ["vflogb_s", "vfsqrt_s", "vfrecip_s", "vfrsqrt_s", "vfrint_s", + "vfrecipe_s", "vfrsqrte_s", "vfrintrne_s", "vfrintrz_s", "vfrintrp_s", "vfrintrm_s"] in def int_loongarch_lsx_#inst : VecInt<[llvm_v4f32_ty], [llvm_v4f32_ty], [IntrNoMem]>; foreach inst = ["vflogb_d", "vfsqrt_d", "vfrecip_d", "vfrsqrt_d", "vfrint_d", + "vfrecipe_d", "vfrsqrte_d", "vfrintrne_d", "vfrintrz_d", "vfrintrp_d", "vfrintrm_d"] in def int_loongarch_lsx_#inst : VecInt<[llvm_v2f64_ty], [llvm_v2f64_ty], [IntrNoMem]>; @@ -1044,10 +1055,12 @@ foreach inst = ["xvfmadd_d", "xvfmsub_d", "xvfnmadd_d", "xvfnmsub_d"] in [IntrNoMem]>; foreach inst = ["xvflogb_s", "xvfsqrt_s", "xvfrecip_s", "xvfrsqrt_s", "xvfrint_s", + "xvfrecipe_s", "xvfrsqrte_s", "xvfrintrne_s", "xvfrintrz_s", "xvfrintrp_s", "xvfrintrm_s"] in def int_loongarch_lasx_#inst : VecInt<[llvm_v8f32_ty], [llvm_v8f32_ty], [IntrNoMem]>; foreach inst = ["xvflogb_d", "xvfsqrt_d", "xvfrecip_d", "xvfrsqrt_d", "xvfrint_d", + "xvfrecipe_d", "xvfrsqrte_d", "xvfrintrne_d", "xvfrintrz_d", "xvfrintrp_d", "xvfrintrm_d"] in def int_loongarch_lasx_#inst : VecInt<[llvm_v4f64_ty], [llvm_v4f64_ty], [IntrNoMem]>; diff --git a/llvm/include/llvm/IR/IntrinsicsNVVM.td b/llvm/include/llvm/IR/IntrinsicsNVVM.td index cf50f2a59f6..5a5ba2592e1 100644 --- a/llvm/include/llvm/IR/IntrinsicsNVVM.td +++ b/llvm/include/llvm/IR/IntrinsicsNVVM.td @@ -615,6 +615,13 @@ let TargetPrefix = "nvvm" in { // Multiplication // + def int_nvvm_mulhi_s : ClangBuiltin<"__nvvm_mulhi_s">, + DefaultAttrsIntrinsic<[llvm_i16_ty], [llvm_i16_ty, llvm_i16_ty], + [IntrNoMem, IntrSpeculatable, Commutative]>; + def int_nvvm_mulhi_us : ClangBuiltin<"__nvvm_mulhi_us">, + DefaultAttrsIntrinsic<[llvm_i16_ty], [llvm_i16_ty, llvm_i16_ty], + [IntrNoMem, IntrSpeculatable, Commutative]>; + def int_nvvm_mulhi_i : ClangBuiltin<"__nvvm_mulhi_i">, DefaultAttrsIntrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], [IntrNoMem, IntrSpeculatable, Commutative]>; @@ -730,12 +737,27 @@ let TargetPrefix = "nvvm" in { // Sad // + def int_nvvm_sad_s : ClangBuiltin<"__nvvm_sad_s">, + DefaultAttrsIntrinsic<[llvm_i16_ty], [llvm_i16_ty, llvm_i16_ty, llvm_i16_ty], + [IntrNoMem, Commutative, IntrSpeculatable]>; + def int_nvvm_sad_us : ClangBuiltin<"__nvvm_sad_us">, + DefaultAttrsIntrinsic<[llvm_i16_ty], [llvm_i16_ty, llvm_i16_ty, llvm_i16_ty], + [IntrNoMem, Commutative, IntrSpeculatable]>; + def int_nvvm_sad_i : ClangBuiltin<"__nvvm_sad_i">, DefaultAttrsIntrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], - [IntrNoMem, Commutative]>; + [IntrNoMem, Commutative, IntrSpeculatable]>; def int_nvvm_sad_ui : ClangBuiltin<"__nvvm_sad_ui">, DefaultAttrsIntrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], - [IntrNoMem, Commutative]>; + [IntrNoMem, Commutative, IntrSpeculatable]>; + + def int_nvvm_sad_ll : ClangBuiltin<"__nvvm_sad_ll">, + DefaultAttrsIntrinsic<[llvm_i64_ty], [llvm_i64_ty, llvm_i64_ty, llvm_i64_ty], + [IntrNoMem, Commutative, IntrSpeculatable]>; + def int_nvvm_sad_ull : ClangBuiltin<"__nvvm_sad_ull">, + DefaultAttrsIntrinsic<[llvm_i64_ty], [llvm_i64_ty, llvm_i64_ty, llvm_i64_ty], + [IntrNoMem, Commutative, IntrSpeculatable]>; + // // Floor Ceil @@ -1372,6 +1394,14 @@ let TargetPrefix = "nvvm" in { def int_nvvm_barrier_cluster_wait : Intrinsic<[], [], [IntrConvergent, IntrNoCallback]>; + // 'aligned' versions of the above barrier.cluster.* intrinsics + def int_nvvm_barrier_cluster_arrive_aligned : + Intrinsic<[], [], [IntrConvergent, IntrNoCallback]>; + def int_nvvm_barrier_cluster_arrive_relaxed_aligned : + Intrinsic<[], [], [IntrConvergent, IntrNoCallback]>; + def int_nvvm_barrier_cluster_wait_aligned : + Intrinsic<[], [], [IntrConvergent, IntrNoCallback]>; + // Membar def int_nvvm_membar_cta : ClangBuiltin<"__nvvm_membar_cta">, Intrinsic<[], [], [IntrNoCallback]>; @@ -1424,6 +1454,16 @@ def int_nvvm_cp_async_wait_all : ClangBuiltin<"__nvvm_cp_async_wait_all">, Intrinsic<[],[],[]>; +// cp.async.bulk variants of the commit/wait group +def int_nvvm_cp_async_bulk_commit_group : + Intrinsic<[],[],[]>; + +def int_nvvm_cp_async_bulk_wait_group : + Intrinsic<[],[llvm_i32_ty],[ImmArg>]>; + +def int_nvvm_cp_async_bulk_wait_group_read : + Intrinsic<[],[llvm_i32_ty],[ImmArg>]>; + // mbarrier def int_nvvm_mbarrier_init : ClangBuiltin<"__nvvm_mbarrier_init">, Intrinsic<[],[llvm_ptr_ty, llvm_i32_ty],[IntrConvergent, IntrNoCallback]>; @@ -2491,6 +2531,47 @@ def int_nvvm_tex_unified_cube_array_level_v4u32_f32 llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty], [], "llvm.nvvm.tex.unified.cube.array.level.v4u32.f32">; +def int_nvvm_tex_unified_cube_grad_v4f32_f32 + : Intrinsic<[llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty], + [llvm_i64_ty, llvm_float_ty, llvm_float_ty, + llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, + llvm_float_ty, llvm_float_ty, llvm_float_ty], [], + "llvm.nvvm.tex.unified.cube.grad.v4f32.f32">; +def int_nvvm_tex_unified_cube_grad_v4s32_f32 + : Intrinsic<[llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], + [llvm_i64_ty, llvm_float_ty, llvm_float_ty, + llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, + llvm_float_ty, llvm_float_ty, llvm_float_ty], [], + "llvm.nvvm.tex.unified.cube.grad.v4s32.f32">; +def int_nvvm_tex_unified_cube_grad_v4u32_f32 + : Intrinsic<[llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], + [llvm_i64_ty, llvm_float_ty, llvm_float_ty, + llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, + llvm_float_ty, llvm_float_ty, llvm_float_ty], [], + "llvm.nvvm.tex.unified.cube.grad.v4u32.f32">; + +def int_nvvm_tex_unified_cube_array_grad_v4f32_f32 + : Intrinsic<[llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty], + [llvm_i64_ty, llvm_i32_ty, + llvm_float_ty, llvm_float_ty, + llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, + llvm_float_ty, llvm_float_ty, llvm_float_ty], [], + "llvm.nvvm.tex.unified.cube.array.grad.v4f32.f32">; +def int_nvvm_tex_unified_cube_array_grad_v4s32_f32 + : Intrinsic<[llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], + [llvm_i64_ty, llvm_i32_ty, + llvm_float_ty, llvm_float_ty, + llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, + llvm_float_ty, llvm_float_ty, llvm_float_ty], [], + "llvm.nvvm.tex.unified.cube.array.grad.v4s32.f32">; +def int_nvvm_tex_unified_cube_array_grad_v4u32_f32 + : Intrinsic<[llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], + [llvm_i64_ty, llvm_i32_ty, + llvm_float_ty, llvm_float_ty, + llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, + llvm_float_ty, llvm_float_ty, llvm_float_ty], [], + "llvm.nvvm.tex.unified.cube.array.grad.v4u32.f32">; + def int_nvvm_tld4_unified_r_2d_v4f32_f32 : Intrinsic<[llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty], [llvm_i64_ty, llvm_float_ty, llvm_float_ty], [], diff --git a/llvm/include/llvm/IR/IntrinsicsPowerPC.td b/llvm/include/llvm/IR/IntrinsicsPowerPC.td index 3ede2a3736b..6d1e8eb4740 100644 --- a/llvm/include/llvm/IR/IntrinsicsPowerPC.td +++ b/llvm/include/llvm/IR/IntrinsicsPowerPC.td @@ -29,6 +29,11 @@ let TargetPrefix = "ppc" in { // All intrinsics start with "llvm.ppc.". [IntrArgMemOnly, NoCapture>, ImmArg>]>; def int_ppc_dcbzl : Intrinsic<[], [llvm_ptr_ty], []>; + // Emit pseudo instruction as fence of instruction motion + def int_ppc_fence : ClangBuiltin<"__builtin_ppc_fence">, + DefaultAttrsIntrinsic<[], [], + [IntrNoMerge, IntrHasSideEffects]>; + // Get content from current FPSCR register def int_ppc_readflm : ClangBuiltin<"__builtin_readflm">, DefaultAttrsIntrinsic<[llvm_double_ty], [], diff --git a/llvm/include/llvm/IR/IntrinsicsRISCV.td b/llvm/include/llvm/IR/IntrinsicsRISCV.td index a391bc53cdb..9a63d14b0ef 100644 --- a/llvm/include/llvm/IR/IntrinsicsRISCV.td +++ b/llvm/include/llvm/IR/IntrinsicsRISCV.td @@ -147,7 +147,8 @@ let TargetPrefix = "riscv" in { class RISCVUSMLoad : DefaultAttrsIntrinsic<[llvm_anyvector_ty], [llvm_ptr_ty, llvm_anyint_ty], - [NoCapture>, IntrReadMem]>, RISCVVIntrinsic { + [NoCapture>, IntrReadMem, IntrArgMemOnly]>, + RISCVVIntrinsic { let VLOperand = 1; } // For unit stride load @@ -155,7 +156,8 @@ let TargetPrefix = "riscv" in { class RISCVUSLoad : DefaultAttrsIntrinsic<[llvm_anyvector_ty], [LLVMMatchType<0>, llvm_ptr_ty, llvm_anyint_ty], - [NoCapture>, IntrReadMem]>, RISCVVIntrinsic { + [NoCapture>, IntrReadMem, IntrArgMemOnly]>, + RISCVVIntrinsic { let VLOperand = 2; } // For unit stride fault-only-first load @@ -177,7 +179,8 @@ let TargetPrefix = "riscv" in { [LLVMMatchType<0>, llvm_ptr_ty, LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>, llvm_anyint_ty, LLVMMatchType<1>], - [NoCapture>, ImmArg>, IntrReadMem]>, + [NoCapture>, ImmArg>, IntrReadMem, + IntrArgMemOnly]>, RISCVVIntrinsic { let VLOperand = 3; } @@ -239,7 +242,8 @@ let TargetPrefix = "riscv" in { class RISCVUSStore : DefaultAttrsIntrinsic<[], [llvm_anyvector_ty, llvm_ptr_ty, llvm_anyint_ty], - [NoCapture>, IntrWriteMem]>, RISCVVIntrinsic { + [NoCapture>, IntrWriteMem, IntrArgMemOnly]>, + RISCVVIntrinsic { let VLOperand = 2; } // For unit stride store with mask @@ -249,7 +253,8 @@ let TargetPrefix = "riscv" in { [llvm_anyvector_ty, llvm_ptr_ty, LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>, llvm_anyint_ty], - [NoCapture>, IntrWriteMem]>, RISCVVIntrinsic { + [NoCapture>, IntrWriteMem, IntrArgMemOnly]>, + RISCVVIntrinsic { let VLOperand = 3; } // For strided store @@ -992,7 +997,8 @@ let TargetPrefix = "riscv" in { !add(nf, -1))), !listconcat(!listsplat(LLVMMatchType<0>, nf), [llvm_ptr_ty, llvm_anyint_ty]), - [NoCapture>, IntrReadMem]>, RISCVVIntrinsic { + [NoCapture>, IntrReadMem, IntrArgMemOnly]>, + RISCVVIntrinsic { let VLOperand = !add(nf, 1); } // For unit stride segment load with mask @@ -1004,8 +1010,9 @@ let TargetPrefix = "riscv" in { [llvm_ptr_ty, LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>, llvm_anyint_ty, LLVMMatchType<1>]), - [ImmArg>, NoCapture>, IntrReadMem]>, - RISCVVIntrinsic { + [ImmArg>, NoCapture>, + IntrReadMem, IntrArgMemOnly]>, + RISCVVIntrinsic { let VLOperand = !add(nf, 2); } @@ -1096,7 +1103,8 @@ let TargetPrefix = "riscv" in { !listconcat([llvm_anyvector_ty], !listsplat(LLVMMatchType<0>, !add(nf, -1)), [llvm_ptr_ty, llvm_anyint_ty]), - [NoCapture>, IntrWriteMem]>, RISCVVIntrinsic { + [NoCapture>, IntrWriteMem, IntrArgMemOnly]>, + RISCVVIntrinsic { let VLOperand = !add(nf, 1); } // For unit stride segment store with mask @@ -1108,7 +1116,8 @@ let TargetPrefix = "riscv" in { [llvm_ptr_ty, LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>, llvm_anyint_ty]), - [NoCapture>, IntrWriteMem]>, RISCVVIntrinsic { + [NoCapture>, IntrWriteMem, IntrArgMemOnly]>, + RISCVVIntrinsic { let VLOperand = !add(nf, 2); } diff --git a/llvm/include/llvm/IR/Metadata.h b/llvm/include/llvm/IR/Metadata.h index 4498423c4c4..db1f44fea3b 100644 --- a/llvm/include/llvm/IR/Metadata.h +++ b/llvm/include/llvm/IR/Metadata.h @@ -211,31 +211,45 @@ private: /// lookup and callback handling. class DebugValueUser { protected: - Metadata *DebugValue; + // Capacity to store 3 debug values. + // TODO: Not all DebugValueUser instances need all 3 elements, if we + // restructure the DPValue class then we can template parameterize this array + // size. + std::array DebugValues; + + ArrayRef getDebugValues() const { return DebugValues; } public: DPValue *getUser(); const DPValue *getUser() const; - void handleChangedValue(Metadata *NewDebugValue); + /// To be called by ReplaceableMetadataImpl::replaceAllUsesWith, where `Old` + /// is a pointer to one of the pointers in `DebugValues` (so should be type + /// Metadata**), and `NewDebugValue` is the new Metadata* that is replacing + /// *Old. + /// For manually replacing elements of DebugValues, + /// `resetDebugValue(Idx, NewDebugValue)` should be used instead. + void handleChangedValue(void *Old, Metadata *NewDebugValue); DebugValueUser() = default; - explicit DebugValueUser(Metadata *DebugValue) : DebugValue(DebugValue) { - trackDebugValue(); + explicit DebugValueUser(std::array DebugValues) + : DebugValues(DebugValues) { + trackDebugValues(); } - - DebugValueUser(DebugValueUser &&X) : DebugValue(X.DebugValue) { - retrackDebugValue(X); + DebugValueUser(DebugValueUser &&X) { + DebugValues = X.DebugValues; + retrackDebugValues(X); } - DebugValueUser(const DebugValueUser &X) : DebugValue(X.DebugValue) { - trackDebugValue(); + DebugValueUser(const DebugValueUser &X) { + DebugValues = X.DebugValues; + trackDebugValues(); } DebugValueUser &operator=(DebugValueUser &&X) { if (&X == this) return *this; - untrackDebugValue(); - DebugValue = X.DebugValue; - retrackDebugValue(X); + untrackDebugValues(); + DebugValues = X.DebugValues; + retrackDebugValues(X); return *this; } @@ -243,35 +257,41 @@ public: if (&X == this) return *this; - untrackDebugValue(); - DebugValue = X.DebugValue; - trackDebugValue(); + untrackDebugValues(); + DebugValues = X.DebugValues; + trackDebugValues(); return *this; } - ~DebugValueUser() { untrackDebugValue(); } + ~DebugValueUser() { untrackDebugValues(); } - void resetDebugValue() { - untrackDebugValue(); - DebugValue = nullptr; + void resetDebugValues() { + untrackDebugValues(); + DebugValues.fill(nullptr); } - void resetDebugValue(Metadata *DebugValue) { - untrackDebugValue(); - this->DebugValue = DebugValue; - trackDebugValue(); + + void resetDebugValue(size_t Idx, Metadata *DebugValue) { + assert(Idx < 3 && "Invalid debug value index."); + untrackDebugValue(Idx); + DebugValues[Idx] = DebugValue; + trackDebugValue(Idx); } bool operator==(const DebugValueUser &X) const { - return DebugValue == X.DebugValue; + return DebugValues == X.DebugValues; } bool operator!=(const DebugValueUser &X) const { - return DebugValue != X.DebugValue; + return DebugValues != X.DebugValues; } private: - void trackDebugValue(); - void untrackDebugValue(); - void retrackDebugValue(DebugValueUser &X); + void trackDebugValue(size_t Idx); + void trackDebugValues(); + + void untrackDebugValue(size_t Idx); + void untrackDebugValues(); + + void retrackDebugValues(DebugValueUser &X); }; /// API for tracking metadata references through RAUW and deletion. @@ -397,6 +417,8 @@ public: /// is resolved. void resolveAllUses(bool ResolveUsers = true); + unsigned getNumUses() const { return UseMap.size(); } + private: void addRef(void *Ref, OwnerTy Owner); void dropRef(void *Ref); @@ -1037,6 +1059,7 @@ struct TempMDNodeDeleter { class MDNode : public Metadata { friend class ReplaceableMetadataImpl; friend class LLVMContextImpl; + friend class DIAssignID; /// The header that is coallocated with an MDNode along with its "small" /// operands. It is located immediately before the main body of the node. @@ -1219,7 +1242,13 @@ public: bool isDistinct() const { return Storage == Distinct; } bool isTemporary() const { return Storage == Temporary; } - bool isReplaceable() const { return isTemporary(); } + bool isReplaceable() const { return isTemporary() || isAlwaysReplaceable(); } + bool isAlwaysReplaceable() const { return getMetadataID() == DIAssignIDKind; } + + unsigned getNumTemporaryUses() const { + assert(isTemporary() && "Only for temporaries"); + return Context.getReplaceableUses()->getNumUses(); + } /// RAUW a temporary. /// diff --git a/llvm/include/llvm/IR/ModuleSummaryIndex.h b/llvm/include/llvm/IR/ModuleSummaryIndex.h index 66c7d10d823..395c9e332eb 100644 --- a/llvm/include/llvm/IR/ModuleSummaryIndex.h +++ b/llvm/include/llvm/IR/ModuleSummaryIndex.h @@ -1715,7 +1715,7 @@ public: SmallString<256> NewName(Name); NewName += ".llvm."; NewName += Suffix; - return std::string(NewName.str()); + return std::string(NewName); } /// Helper to obtain the unpromoted name for a global value (or the original diff --git a/llvm/include/llvm/IR/ProfileSummary.h b/llvm/include/llvm/IR/ProfileSummary.h index 4bb6bb8d4a4..b23d5a30846 100644 --- a/llvm/include/llvm/IR/ProfileSummary.h +++ b/llvm/include/llvm/IR/ProfileSummary.h @@ -73,10 +73,10 @@ public: uint64_t MaxInternalCount, uint64_t MaxFunctionCount, uint32_t NumCounts, uint32_t NumFunctions, bool Partial = false, double PartialProfileRatio = 0) - : PSK(K), DetailedSummary(std::move(DetailedSummary)), - TotalCount(TotalCount), MaxCount(MaxCount), - MaxInternalCount(MaxInternalCount), MaxFunctionCount(MaxFunctionCount), - NumCounts(NumCounts), NumFunctions(NumFunctions), Partial(Partial), + : PSK(K), DetailedSummary(DetailedSummary), TotalCount(TotalCount), + MaxCount(MaxCount), MaxInternalCount(MaxInternalCount), + MaxFunctionCount(MaxFunctionCount), NumCounts(NumCounts), + NumFunctions(NumFunctions), Partial(Partial), PartialProfileRatio(PartialProfileRatio) {} Kind getKind() const { return PSK; } diff --git a/llvm/include/llvm/IR/VFABIDemangler.h b/llvm/include/llvm/IR/VFABIDemangler.h new file mode 100644 index 00000000000..8450d4ce541 --- /dev/null +++ b/llvm/include/llvm/IR/VFABIDemangler.h @@ -0,0 +1,217 @@ +//===- VFABIDemangler.h - Vector Function ABI demangler ------- -*- C++ -*-===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// +// +// This file defines the VFABI demangling utility. +// +//===----------------------------------------------------------------------===// + +#ifndef LLVM_IR_VFABIDEMANGLER_H +#define LLVM_IR_VFABIDEMANGLER_H + +#include "llvm/ADT/SmallVector.h" +#include "llvm/IR/DerivedTypes.h" +#include "llvm/IR/Instructions.h" +#include "llvm/Support/Alignment.h" +#include "llvm/Support/TypeSize.h" + +namespace llvm { + +/// Describes the type of Parameters +enum class VFParamKind { + Vector, // No semantic information. + OMP_Linear, // declare simd linear(i) + OMP_LinearRef, // declare simd linear(ref(i)) + OMP_LinearVal, // declare simd linear(val(i)) + OMP_LinearUVal, // declare simd linear(uval(i)) + OMP_LinearPos, // declare simd linear(i:c) uniform(c) + OMP_LinearValPos, // declare simd linear(val(i:c)) uniform(c) + OMP_LinearRefPos, // declare simd linear(ref(i:c)) uniform(c) + OMP_LinearUValPos, // declare simd linear(uval(i:c)) uniform(c) + OMP_Uniform, // declare simd uniform(i) + GlobalPredicate, // Global logical predicate that acts on all lanes + // of the input and output mask concurrently. For + // example, it is implied by the `M` token in the + // Vector Function ABI mangled name. + Unknown +}; + +/// Describes the type of Instruction Set Architecture +enum class VFISAKind { + AdvancedSIMD, // AArch64 Advanced SIMD (NEON) + SVE, // AArch64 Scalable Vector Extension + SSE, // x86 SSE + AVX, // x86 AVX + AVX2, // x86 AVX2 + AVX512, // x86 AVX512 + LLVM, // LLVM internal ISA for functions that are not + // attached to an existing ABI via name mangling. + Unknown // Unknown ISA +}; + +/// Encapsulates information needed to describe a parameter. +/// +/// The description of the parameter is not linked directly to +/// OpenMP or any other vector function description. This structure +/// is extendible to handle other paradigms that describe vector +/// functions and their parameters. +struct VFParameter { + unsigned ParamPos; // Parameter Position in Scalar Function. + VFParamKind ParamKind; // Kind of Parameter. + int LinearStepOrPos = 0; // Step or Position of the Parameter. + Align Alignment = Align(); // Optional alignment in bytes, defaulted to 1. + + // Comparison operator. + bool operator==(const VFParameter &Other) const { + return std::tie(ParamPos, ParamKind, LinearStepOrPos, Alignment) == + std::tie(Other.ParamPos, Other.ParamKind, Other.LinearStepOrPos, + Other.Alignment); + } +}; + +/// Contains the information about the kind of vectorization +/// available. +/// +/// This object in independent on the paradigm used to +/// represent vector functions. in particular, it is not attached to +/// any target-specific ABI. +struct VFShape { + ElementCount VF; // Vectorization factor. + SmallVector Parameters; // List of parameter information. + // Comparison operator. + bool operator==(const VFShape &Other) const { + return std::tie(VF, Parameters) == std::tie(Other.VF, Other.Parameters); + } + + /// Update the parameter in position P.ParamPos to P. + void updateParam(VFParameter P) { + assert(P.ParamPos < Parameters.size() && "Invalid parameter position."); + Parameters[P.ParamPos] = P; + assert(hasValidParameterList() && "Invalid parameter list"); + } + + /// Retrieve the VFShape that can be used to map a scalar function to itself, + /// with VF = 1. + static VFShape getScalarShape(const FunctionType *FTy) { + return VFShape::get(FTy, ElementCount::getFixed(1), + /*HasGlobalPredicate*/ false); + } + + /// Retrieve the basic vectorization shape of the function, where all + /// parameters are mapped to VFParamKind::Vector with \p EC lanes. Specifies + /// whether the function has a Global Predicate argument via \p HasGlobalPred. + static VFShape get(const FunctionType *FTy, ElementCount EC, + bool HasGlobalPred) { + SmallVector Parameters; + for (unsigned I = 0; I < FTy->getNumParams(); ++I) + Parameters.push_back(VFParameter({I, VFParamKind::Vector})); + if (HasGlobalPred) + Parameters.push_back( + VFParameter({FTy->getNumParams(), VFParamKind::GlobalPredicate})); + + return {EC, Parameters}; + } + /// Validation check on the Parameters in the VFShape. + bool hasValidParameterList() const; +}; + +/// Holds the VFShape for a specific scalar to vector function mapping. +struct VFInfo { + VFShape Shape; /// Classification of the vector function. + std::string ScalarName; /// Scalar Function Name. + std::string VectorName; /// Vector Function Name associated to this VFInfo. + VFISAKind ISA; /// Instruction Set Architecture. + + /// Returns the index of the first parameter with the kind 'GlobalPredicate', + /// if any exist. + std::optional getParamIndexForOptionalMask() const { + unsigned ParamCount = Shape.Parameters.size(); + for (unsigned i = 0; i < ParamCount; ++i) + if (Shape.Parameters[i].ParamKind == VFParamKind::GlobalPredicate) + return i; + + return std::nullopt; + } + + /// Returns true if at least one of the operands to the vectorized function + /// has the kind 'GlobalPredicate'. + bool isMasked() const { return getParamIndexForOptionalMask().has_value(); } +}; + +namespace VFABI { +/// LLVM Internal VFABI ISA token for vector functions. +static constexpr char const *_LLVM_ = "_LLVM_"; +/// Prefix for internal name redirection for vector function that +/// tells the compiler to scalarize the call using the scalar name +/// of the function. For example, a mangled name like +/// `_ZGV_LLVM_N2v_foo(_LLVM_Scalarize_foo)` would tell the +/// vectorizer to vectorize the scalar call `foo`, and to scalarize +/// it once vectorization is done. +static constexpr char const *_LLVM_Scalarize_ = "_LLVM_Scalarize_"; + +/// Function to construct a VFInfo out of a mangled names in the +/// following format: +/// +/// {()} +/// +/// where is the name of the vector function, mangled according +/// to the rules described in the Vector Function ABI of the target vector +/// extension (or from now on). The is in the following +/// format: +/// +/// _ZGV_[()] +/// +/// This methods support demangling rules for the following : +/// +/// * AArch64: https://developer.arm.com/docs/101129/latest +/// +/// * x86 (libmvec): https://sourceware.org/glibc/wiki/libmvec and +/// https://sourceware.org/glibc/wiki/libmvec?action=AttachFile&do=view&target=VectorABI.txt +/// +/// \param MangledName -> input string in the format +/// _ZGV_[()]. +/// \param FTy -> FunctionType of the scalar function which we're trying to find +/// a vectorized variant for. This is required to determine the vectorization +/// factor for scalable vectors, since the mangled name doesn't encode that; +/// it needs to be derived from the widest element types of vector arguments +/// or return values. +std::optional tryDemangleForVFABI(StringRef MangledName, + const FunctionType *FTy); + +/// Retrieve the `VFParamKind` from a string token. +VFParamKind getVFParamKindFromString(const StringRef Token); + +// Name of the attribute where the variant mappings are stored. +static constexpr char const *MappingsAttrName = "vector-function-abi-variant"; + +/// Populates a set of strings representing the Vector Function ABI variants +/// associated to the CallInst CI. If the CI does not contain the +/// vector-function-abi-variant attribute, we return without populating +/// VariantMappings, i.e. callers of getVectorVariantNames need not check for +/// the presence of the attribute (see InjectTLIMappings). +void getVectorVariantNames(const CallInst &CI, + SmallVectorImpl &VariantMappings); + +/// Constructs a FunctionType by applying vector function information to the +/// type of a matching scalar function. +/// \param Info gets the vectorization factor (VF) and the VFParamKind of the +/// parameters. +/// \param ScalarFTy gets the Type information of parameters, as it is not +/// stored in \p Info. +/// \returns a pointer to a newly created vector FunctionType +FunctionType *createFunctionType(const VFInfo &Info, + const FunctionType *ScalarFTy); + +/// Overwrite the Vector Function ABI variants attribute with the names provide +/// in \p VariantMappings. +void setVectorVariantNames(CallInst *CI, ArrayRef VariantMappings); + +} // end namespace VFABI + +} // namespace llvm + +#endif // LLVM_IR_VFABIDEMANGLER_H diff --git a/llvm/include/llvm/IR/VPIntrinsics.def b/llvm/include/llvm/IR/VPIntrinsics.def index 671dc39db26..3b32b60609f 100644 --- a/llvm/include/llvm/IR/VPIntrinsics.def +++ b/llvm/include/llvm/IR/VPIntrinsics.def @@ -367,20 +367,34 @@ VP_PROPERTY_FUNCTIONAL_SDOPC(FCOPYSIGN) VP_PROPERTY_FUNCTIONAL_INTRINSIC(copysign) END_REGISTER_VP(vp_copysign, VP_FCOPYSIGN) -// llvm.vp.minnum(x, y, mask,vlen) +// llvm.vp.minnum(x,y,mask,vlen) BEGIN_REGISTER_VP(vp_minnum, 2, 3, VP_FMINNUM, -1) VP_PROPERTY_BINARYOP VP_PROPERTY_FUNCTIONAL_SDOPC(FMINNUM) VP_PROPERTY_FUNCTIONAL_INTRINSIC(minnum) END_REGISTER_VP(vp_minnum, VP_FMINNUM) -// llvm.vp.maxnum(x, y, mask,vlen) +// llvm.vp.maxnum(x,y,mask,vlen) BEGIN_REGISTER_VP(vp_maxnum, 2, 3, VP_FMAXNUM, -1) VP_PROPERTY_BINARYOP VP_PROPERTY_FUNCTIONAL_SDOPC(FMAXNUM) VP_PROPERTY_FUNCTIONAL_INTRINSIC(maxnum) END_REGISTER_VP(vp_maxnum, VP_FMAXNUM) +// llvm.vp.minimum(x,y,mask,vlen) +BEGIN_REGISTER_VP(vp_minimum, 2, 3, VP_FMINIMUM, -1) +VP_PROPERTY_BINARYOP +VP_PROPERTY_FUNCTIONAL_SDOPC(FMINIMUM) +VP_PROPERTY_FUNCTIONAL_INTRINSIC(minimum) +END_REGISTER_VP(vp_minimum, VP_FMINIMUM) + +// llvm.vp.maximum(x,y,mask,vlen) +BEGIN_REGISTER_VP(vp_maximum, 2, 3, VP_FMAXIMUM, -1) +VP_PROPERTY_BINARYOP +VP_PROPERTY_FUNCTIONAL_SDOPC(FMAXIMUM) +VP_PROPERTY_FUNCTIONAL_INTRINSIC(maximum) +END_REGISTER_VP(vp_maximum, VP_FMAXIMUM) + // llvm.vp.ceil(x,mask,vlen) BEGIN_REGISTER_VP(vp_ceil, 1, 2, VP_FCEIL, -1) VP_PROPERTY_FUNCTIONAL_INTRINSIC(ceil) diff --git a/llvm/include/llvm/IR/Value.h b/llvm/include/llvm/IR/Value.h index 8fce56e12c5..945081b77e9 100644 --- a/llvm/include/llvm/IR/Value.h +++ b/llvm/include/llvm/IR/Value.h @@ -72,12 +72,6 @@ using ValueName = StringMapEntry; /// objects that watch it and listen to RAUW and Destroy events. See /// llvm/IR/ValueHandle.h for details. class Value { - Type *VTy; - Use *UseList; - - friend class ValueAsMetadata; // Allow access to IsUsedByMD. - friend class ValueHandleBase; - const unsigned char SubclassID; // Subclass identifier (for isa/dyn_cast) unsigned char HasValueHandle : 1; // Has a ValueHandle pointing to this? @@ -121,6 +115,12 @@ protected: unsigned HasDescriptor : 1; private: + Type *VTy; + Use *UseList; + + friend class ValueAsMetadata; // Allow access to IsUsedByMD. + friend class ValueHandleBase; // Allow access to HasValueHandle. + template // UseT == 'Use' or 'const Use' class use_iterator_impl { friend class Value; @@ -618,6 +618,9 @@ protected: /// \returns true if any metadata was removed. bool eraseMetadata(unsigned KindID); + /// Erase all metadata attachments matching the given predicate. + void eraseMetadataIf(function_ref Pred); + /// Erase all metadata attached to this Value. void clearMetadata(); diff --git a/llvm/include/llvm/MC/MCObjectWriter.h b/llvm/include/llvm/MC/MCObjectWriter.h index 8c104523739..e66bb2c932d 100644 --- a/llvm/include/llvm/MC/MCObjectWriter.h +++ b/llvm/include/llvm/MC/MCObjectWriter.h @@ -92,6 +92,9 @@ public: /// ELF only. Mark that we have seen GNU ABI usage (e.g. SHF_GNU_RETAIN). virtual void markGnuAbi() {} + /// ELF only, override the default ABIVersion in the ELF header. + virtual void setOverrideABIVersion(uint8_t ABIVersion) {} + /// Tell the object writer to emit an address-significance table during /// writeObject(). If this function is not called, all symbols are treated as /// address-significant. diff --git a/llvm/include/llvm/MC/MCSymbol.h b/llvm/include/llvm/MC/MCSymbol.h index 7be31223280..a53e53179e4 100644 --- a/llvm/include/llvm/MC/MCSymbol.h +++ b/llvm/include/llvm/MC/MCSymbol.h @@ -61,7 +61,7 @@ protected: SymContentsTargetCommon, // Index stores the section index }; - // Special sentinal value for the absolute pseudo fragment. + // Special sentinel value for the absolute pseudo fragment. static MCFragment *AbsolutePseudoFragment; /// If a symbol has a Fragment, the section is implied, so we only need diff --git a/llvm/include/llvm/MC/MCSymbolWasm.h b/llvm/include/llvm/MC/MCSymbolWasm.h index c67bd64e7cb..0ce95c72a73 100644 --- a/llvm/include/llvm/MC/MCSymbolWasm.h +++ b/llvm/include/llvm/MC/MCSymbolWasm.h @@ -112,7 +112,7 @@ public: bool isFunctionTable() const { return isTable() && hasTableType() && - getTableType().ElemType == wasm::WASM_TYPE_FUNCREF; + getTableType().ElemType == wasm::ValType::FUNCREF; } void setFunctionTable() { setType(wasm::WASM_SYMBOL_TYPE_TABLE); @@ -144,7 +144,7 @@ public: // Declare a table with element type VT and no limits (min size 0, no max // size). wasm::WasmLimits Limits = {wasm::WASM_LIMITS_FLAG_NONE, 0, 0}; - setTableType({uint8_t(VT), Limits}); + setTableType({VT, Limits}); } }; diff --git a/llvm/include/llvm/Object/COFFImportFile.h b/llvm/include/llvm/Object/COFFImportFile.h index 0fb65fabdbc..edc836ff034 100644 --- a/llvm/include/llvm/Object/COFFImportFile.h +++ b/llvm/include/llvm/Object/COFFImportFile.h @@ -65,6 +65,8 @@ public: uint16_t getMachine() const { return getCOFFImportHeader()->Machine; } + StringRef getFileFormatName() const; + private: bool isData() const { return getCOFFImportHeader()->getType() == COFF::IMPORT_DATA; diff --git a/llvm/include/llvm/Object/ELFObjectFile.h b/llvm/include/llvm/Object/ELFObjectFile.h index 86f42654f8a..7124df50b56 100644 --- a/llvm/include/llvm/Object/ELFObjectFile.h +++ b/llvm/include/llvm/Object/ELFObjectFile.h @@ -110,11 +110,12 @@ public: Expected> readDynsymVersions() const; /// Returns a vector of all BB address maps in the object file. When - // `TextSectionIndex` is specified, only returns the BB address maps - // corresponding to the section with that index. When `PGOAnalyses`is - // specified, the vector is cleared then filled with extra PGO data. - // `PGOAnalyses` will always be the same length as the return value on - // success, otherwise it is empty. + /// `TextSectionIndex` is specified, only returns the BB address maps + /// corresponding to the section with that index. When `PGOAnalyses`is + /// specified (PGOAnalyses is not nullptr), the vector is cleared then filled + /// with extra PGO data. `PGOAnalyses` will always be the same length as the + /// return value when it is requested assuming no error occurs. Upon failure, + /// `PGOAnalyses` will be emptied. Expected> readBBAddrMap(std::optional TextSectionIndex = std::nullopt, std::vector *PGOAnalyses = nullptr) const; diff --git a/llvm/include/llvm/Object/MachO.h b/llvm/include/llvm/Object/MachO.h index f91f21d837c..24f9954584e 100644 --- a/llvm/include/llvm/Object/MachO.h +++ b/llvm/include/llvm/Object/MachO.h @@ -826,7 +826,7 @@ public: Version = utostr(major) + "." + utostr(minor); if (update != 0) Version += "." + utostr(update); - return std::string(std::string(Version.str())); + return std::string(std::string(Version)); } /// If the input path is a .dSYM bundle (as created by the dsymutil tool), diff --git a/llvm/include/llvm/Object/OffloadBinary.h b/llvm/include/llvm/Object/OffloadBinary.h index dda1e7f1eaf..13383d5f07b 100644 --- a/llvm/include/llvm/Object/OffloadBinary.h +++ b/llvm/include/llvm/Object/OffloadBinary.h @@ -162,6 +162,19 @@ public: std::unique_ptr Buffer) : OwningBinary(std::move(Binary), std::move(Buffer)) {} + /// Make a deep copy of this offloading file. + OffloadFile copy() const { + std::unique_ptr Buffer = MemoryBuffer::getMemBufferCopy( + getBinary()->getMemoryBufferRef().getBuffer()); + + // This parsing should never fail because it has already been parsed. + auto NewBinaryOrErr = OffloadBinary::create(*Buffer); + assert(NewBinaryOrErr && "Failed to parse a copy of the binary?"); + if (!NewBinaryOrErr) + llvm::consumeError(NewBinaryOrErr.takeError()); + return OffloadFile(std::move(*NewBinaryOrErr), std::move(Buffer)); + } + /// We use the Triple and Architecture pair to group linker inputs together. /// This conversion function lets us use these inputs in a hash-map. operator TargetID() const { @@ -186,6 +199,18 @@ OffloadKind getOffloadKind(StringRef Name); /// Convert an offload kind to its string representation. StringRef getOffloadKindName(OffloadKind Name); +/// If the target is AMD we check the target IDs for mutual compatibility. A +/// target id is a string conforming to the folowing BNF syntax: +/// +/// target-id ::= ' ( : ( '+' | '-' ) )*' +/// +/// The features 'xnack' and 'sramecc' are currently supported. These can be in +/// the state of on, off, and any when unspecified. A target marked as any can +/// bind with either on or off. This is used to link mutually compatible +/// architectures together. Returns false in the case of an exact match. +bool areTargetsCompatible(const OffloadFile::TargetID &LHS, + const OffloadFile::TargetID &RHS); + } // namespace object } // namespace llvm diff --git a/llvm/include/llvm/Passes/PassBuilder.h b/llvm/include/llvm/Passes/PassBuilder.h index 61417431f8a..7339b8a9882 100644 --- a/llvm/include/llvm/Passes/PassBuilder.h +++ b/llvm/include/llvm/Passes/PassBuilder.h @@ -16,6 +16,7 @@ #define LLVM_PASSES_PASSBUILDER_H #include "llvm/Analysis/CGSCCPassManager.h" +#include "llvm/CodeGen/MachinePassManager.h" #include "llvm/IR/PassManager.h" #include "llvm/Passes/OptimizationLevel.h" #include "llvm/Support/Error.h" @@ -165,6 +166,14 @@ public: /// additional analyses. void registerLoopAnalyses(LoopAnalysisManager &LAM); + /// Registers all available machine function analysis passes. + /// + /// This is an interface that can be used to populate a \c + /// MachineFunctionAnalysisManager with all registered function analyses. + /// Callers can still manually register any additional analyses. Callers can + /// also pre-register analyses and this will not override those. + void registerMachineFunctionAnalyses(MachineFunctionAnalysisManager &MFAM); + /// Construct the core LLVM function canonicalization and simplification /// pipeline. /// @@ -241,12 +250,9 @@ public: /// /// This builds a pipeline that runs the LTO/ThinLTO pre-link pipeline, and /// emits a section containing the pre-link bitcode along side the object code - /// generated by running the PerModuleDefaultPipeline, used when compiling - /// without LTO. It clones the module and runs the LTO/non-LTO pipelines - /// separately to avoid any inconsistencies with an ad-hoc pipeline that tries - /// to approximate the PerModuleDefaultPipeline from the pre-link LTO - /// pipelines. - ModulePassManager buildFatLTODefaultPipeline(OptimizationLevel Level); + /// generated in non-LTO compilation. + ModulePassManager buildFatLTODefaultPipeline(OptimizationLevel Level, + bool ThinLTO, bool EmitSummary); /// Build a pre-link, ThinLTO-targeting default optimization pipeline to /// a pass manager. @@ -352,6 +358,18 @@ public: Error parsePassPipeline(LoopPassManager &LPM, StringRef PipelineText); /// @}} + /// Parse a textual MIR pipeline into the provided \c MachineFunctionPass + /// manager. + /// The format of the textual machine pipeline is a comma separated list of + /// machine pass names: + /// + /// machine-funciton-pass,machine-module-pass,... + /// + /// There is no need to specify the pass nesting, and this function + /// currently cannot handle the pass nesting. + Error parsePassPipeline(MachineFunctionPassManager &MFPM, + StringRef PipelineText); + /// Parse a textual alias analysis pipeline into the provided AA manager. /// /// The format of the textual AA pipeline is a comma separated list of AA @@ -520,6 +538,10 @@ public: const std::function &C) { ModuleAnalysisRegistrationCallbacks.push_back(C); } + void registerAnalysisRegistrationCallback( + const std::function &C) { + MachineFunctionAnalysisRegistrationCallbacks.push_back(C); + } /// @}} /// {{@ Register pipeline parsing callbacks with this pass builder instance. @@ -546,6 +568,11 @@ public: ArrayRef)> &C) { ModulePipelineParsingCallbacks.push_back(C); } + void registerPipelineParsingCallback( + const std::function + &C) { + MachinePipelineParsingCallbacks.push_back(C); + } /// @}} /// Register a callback for a top-level pipeline entry. @@ -616,8 +643,12 @@ private: Error parseCGSCCPass(CGSCCPassManager &CGPM, const PipelineElement &E); Error parseFunctionPass(FunctionPassManager &FPM, const PipelineElement &E); Error parseLoopPass(LoopPassManager &LPM, const PipelineElement &E); + Error parseMachinePass(MachineFunctionPassManager &MFPM, + const PipelineElement &E); bool parseAAPassName(AAManager &AA, StringRef Name); + Error parseMachinePassPipeline(MachineFunctionPassManager &MFPM, + ArrayRef Pipeline); Error parseLoopPassPipeline(LoopPassManager &LPM, ArrayRef Pipeline); Error parseFunctionPassPipeline(FunctionPassManager &FPM, @@ -699,6 +730,11 @@ private: // AA callbacks SmallVector, 2> AAParsingCallbacks; + // Machine pass callbackcs + SmallVector, 2> + MachineFunctionAnalysisRegistrationCallbacks; + SmallVector, 2> + MachinePipelineParsingCallbacks; }; /// This utility template takes care of adding require<> and invalidate<> @@ -743,6 +779,90 @@ bool parseAnalysisUtilityPasses( return false; } + +// These are special since they are only for testing purposes. + +/// No-op module pass which does nothing. +struct NoOpModulePass : PassInfoMixin { + PreservedAnalyses run(Module &M, ModuleAnalysisManager &) { + return PreservedAnalyses::all(); + } +}; + +/// No-op module analysis. +class NoOpModuleAnalysis : public AnalysisInfoMixin { + friend AnalysisInfoMixin; + static AnalysisKey Key; + +public: + struct Result {}; + Result run(Module &, ModuleAnalysisManager &) { return Result(); } +}; + +/// No-op CGSCC pass which does nothing. +struct NoOpCGSCCPass : PassInfoMixin { + PreservedAnalyses run(LazyCallGraph::SCC &C, CGSCCAnalysisManager &, + LazyCallGraph &, CGSCCUpdateResult &UR) { + return PreservedAnalyses::all(); + } +}; + +/// No-op CGSCC analysis. +class NoOpCGSCCAnalysis : public AnalysisInfoMixin { + friend AnalysisInfoMixin; + static AnalysisKey Key; + +public: + struct Result {}; + Result run(LazyCallGraph::SCC &, CGSCCAnalysisManager &, LazyCallGraph &G) { + return Result(); + } +}; + +/// No-op function pass which does nothing. +struct NoOpFunctionPass : PassInfoMixin { + PreservedAnalyses run(Function &F, FunctionAnalysisManager &) { + return PreservedAnalyses::all(); + } +}; + +/// No-op function analysis. +class NoOpFunctionAnalysis : public AnalysisInfoMixin { + friend AnalysisInfoMixin; + static AnalysisKey Key; + +public: + struct Result {}; + Result run(Function &, FunctionAnalysisManager &) { return Result(); } +}; + +/// No-op loop nest pass which does nothing. +struct NoOpLoopNestPass : PassInfoMixin { + PreservedAnalyses run(LoopNest &L, LoopAnalysisManager &, + LoopStandardAnalysisResults &, LPMUpdater &) { + return PreservedAnalyses::all(); + } +}; + +/// No-op loop pass which does nothing. +struct NoOpLoopPass : PassInfoMixin { + PreservedAnalyses run(Loop &L, LoopAnalysisManager &, + LoopStandardAnalysisResults &, LPMUpdater &) { + return PreservedAnalyses::all(); + } +}; + +/// No-op loop analysis. +class NoOpLoopAnalysis : public AnalysisInfoMixin { + friend AnalysisInfoMixin; + static AnalysisKey Key; + +public: + struct Result {}; + Result run(Loop &, LoopAnalysisManager &, LoopStandardAnalysisResults &) { + return Result(); + } +}; } #endif diff --git a/llvm/include/llvm/ProfileData/Coverage/CoverageMapping.h b/llvm/include/llvm/ProfileData/Coverage/CoverageMapping.h index 2757b8cd54a..33fa17ba811 100644 --- a/llvm/include/llvm/ProfileData/Coverage/CoverageMapping.h +++ b/llvm/include/llvm/ProfileData/Coverage/CoverageMapping.h @@ -295,12 +295,11 @@ struct CounterMappingRegion { Kind(Kind) {} CounterMappingRegion(MCDCParameters MCDCParams, unsigned FileID, - unsigned ExpandedFileID, unsigned LineStart, - unsigned ColumnStart, unsigned LineEnd, - unsigned ColumnEnd, RegionKind Kind) - : MCDCParams(MCDCParams), ExpandedFileID(ExpandedFileID), - LineStart(LineStart), ColumnStart(ColumnStart), LineEnd(LineEnd), - ColumnEnd(ColumnEnd), Kind(Kind) {} + unsigned LineStart, unsigned ColumnStart, + unsigned LineEnd, unsigned ColumnEnd, RegionKind Kind) + : MCDCParams(MCDCParams), FileID(FileID), LineStart(LineStart), + ColumnStart(ColumnStart), LineEnd(LineEnd), ColumnEnd(ColumnEnd), + Kind(Kind) {} static CounterMappingRegion makeRegion(Counter Count, unsigned FileID, unsigned LineStart, @@ -354,7 +353,7 @@ struct CounterMappingRegion { makeDecisionRegion(MCDCParameters MCDCParams, unsigned FileID, unsigned LineStart, unsigned ColumnStart, unsigned LineEnd, unsigned ColumnEnd) { - return CounterMappingRegion(MCDCParams, FileID, 0, LineStart, ColumnStart, + return CounterMappingRegion(MCDCParams, FileID, LineStart, ColumnStart, LineEnd, ColumnEnd, MCDCDecisionRegion); } @@ -588,8 +587,9 @@ public: /// Return an MCDC record that indicates executed test vectors and condition /// pairs. Expected - evaluateMCDCRegion(CounterMappingRegion Region, BitVector Bitmap, - ArrayRef Branches); + evaluateMCDCRegion(const CounterMappingRegion &Region, + const BitVector &Bitmap, + ArrayRef Branches); unsigned getMaxCounterID(const Counter &C) const; }; diff --git a/llvm/include/llvm/ProfileData/SampleProf.h b/llvm/include/llvm/ProfileData/SampleProf.h index 66aaf602d0e..8ac84d4b933 100644 --- a/llvm/include/llvm/ProfileData/SampleProf.h +++ b/llvm/include/llvm/ProfileData/SampleProf.h @@ -1330,6 +1330,8 @@ public: } size_t erase(const key_type &Key) { return base_type::erase(Key); } + + iterator erase(iterator It) { return base_type::erase(It); } }; using NameFunctionSamples = std::pair; diff --git a/llvm/include/llvm/Support/AMDGPUMetadata.h b/llvm/include/llvm/Support/AMDGPUMetadata.h index e0838a1f425..2dae6feac08 100644 --- a/llvm/include/llvm/Support/AMDGPUMetadata.h +++ b/llvm/include/llvm/Support/AMDGPUMetadata.h @@ -29,11 +29,6 @@ namespace AMDGPU { //===----------------------------------------------------------------------===// namespace HSAMD { -/// HSA metadata major version for code object V2. -constexpr uint32_t VersionMajorV2 = 1; -/// HSA metadata minor version for code object V2. -constexpr uint32_t VersionMinorV2 = 0; - /// HSA metadata major version for code object V3. constexpr uint32_t VersionMajorV3 = 1; /// HSA metadata minor version for code object V3. @@ -49,10 +44,9 @@ constexpr uint32_t VersionMajorV5 = 1; /// HSA metadata minor version for code object V5. constexpr uint32_t VersionMinorV5 = 2; -/// HSA metadata beginning assembler directive. +/// Old HSA metadata beginning assembler directive for V2. This is only used for +/// diagnostics now. constexpr char AssemblerDirectiveBegin[] = ".amd_amdgpu_hsa_metadata"; -/// HSA metadata ending assembler directive. -constexpr char AssemblerDirectiveEnd[] = ".end_amd_amdgpu_hsa_metadata"; /// Access qualifiers. enum class AccessQualifier : uint8_t { diff --git a/llvm/include/llvm/Support/FormatCommon.h b/llvm/include/llvm/Support/FormatCommon.h index 3c119d12529..24a40c325e1 100644 --- a/llvm/include/llvm/Support/FormatCommon.h +++ b/llvm/include/llvm/Support/FormatCommon.h @@ -66,8 +66,8 @@ struct FmtAlign { } private: - void fill(llvm::raw_ostream &S, uint32_t Count) { - for (uint32_t I = 0; I < Count; ++I) + void fill(llvm::raw_ostream &S, size_t Count) { + for (size_t I = 0; I < Count; ++I) S << Fill; } }; diff --git a/llvm/include/llvm/Support/GenericDomTree.h b/llvm/include/llvm/Support/GenericDomTree.h index 62186a368e9..4fce9d8bfb2 100644 --- a/llvm/include/llvm/Support/GenericDomTree.h +++ b/llvm/include/llvm/Support/GenericDomTree.h @@ -850,17 +850,16 @@ protected: void Split(typename GraphTraits::NodeRef NewBB) { using GraphT = GraphTraits; using NodeRef = typename GraphT::NodeRef; - assert(std::distance(GraphT::child_begin(NewBB), - GraphT::child_end(NewBB)) == 1 && + assert(llvm::hasSingleElement(children(NewBB)) && "NewBB should have a single successor!"); NodeRef NewBBSucc = *GraphT::child_begin(NewBB); - SmallVector PredBlocks(children>(NewBB)); + SmallVector PredBlocks(inverse_children(NewBB)); assert(!PredBlocks.empty() && "No predblocks?"); bool NewBBDominatesNewBBSucc = true; - for (auto *Pred : children>(NewBBSucc)) { + for (auto *Pred : inverse_children(NewBBSucc)) { if (Pred != NewBB && !dominates(NewBBSucc, Pred) && isReachableFromEntry(Pred)) { NewBBDominatesNewBBSucc = false; diff --git a/llvm/include/llvm/Support/GenericLoopInfo.h b/llvm/include/llvm/Support/GenericLoopInfo.h index ac4f2d7010b..d560ca64813 100644 --- a/llvm/include/llvm/Support/GenericLoopInfo.h +++ b/llvm/include/llvm/Support/GenericLoopInfo.h @@ -241,24 +241,14 @@ public: bool isLoopLatch(const BlockT *BB) const { assert(!isInvalid() && "Loop not in a valid state!"); assert(contains(BB) && "block does not belong to the loop"); - - BlockT *Header = getHeader(); - auto PredBegin = GraphTraits>::child_begin(Header); - auto PredEnd = GraphTraits>::child_end(Header); - return std::find(PredBegin, PredEnd, BB) != PredEnd; + return llvm::is_contained(inverse_children(getHeader()), BB); } /// Calculate the number of back edges to the loop header. unsigned getNumBackEdges() const { assert(!isInvalid() && "Loop not in a valid state!"); - unsigned NumBackEdges = 0; - BlockT *H = getHeader(); - - for (const auto Pred : children>(H)) - if (contains(Pred)) - ++NumBackEdges; - - return NumBackEdges; + return llvm::count_if(inverse_children(getHeader()), + [&](BlockT *Pred) { return contains(Pred); }); } //===--------------------------------------------------------------------===// @@ -336,7 +326,7 @@ public: void getLoopLatches(SmallVectorImpl &LoopLatches) const { assert(!isInvalid() && "Loop not in a valid state!"); BlockT *H = getHeader(); - for (const auto Pred : children>(H)) + for (const auto Pred : inverse_children(H)) if (contains(Pred)) LoopLatches.push_back(Pred); } diff --git a/llvm/include/llvm/Support/GenericLoopInfoImpl.h b/llvm/include/llvm/Support/GenericLoopInfoImpl.h index 15af9cd794e..1e0d0ee446f 100644 --- a/llvm/include/llvm/Support/GenericLoopInfoImpl.h +++ b/llvm/include/llvm/Support/GenericLoopInfoImpl.h @@ -115,7 +115,7 @@ bool LoopBase::hasDedicatedExits() const { SmallVector UniqueExitBlocks; getUniqueExitBlocks(UniqueExitBlocks); for (BlockT *EB : UniqueExitBlocks) - for (BlockT *Predecessor : children>(EB)) + for (BlockT *Predecessor : inverse_children(EB)) if (!contains(Predecessor)) return false; // All the requirements are met. @@ -208,10 +208,7 @@ BlockT *LoopBase::getLoopPreheader() const { return nullptr; // Make sure there is only one exit out of the preheader. - typedef GraphTraits BlockTraits; - typename BlockTraits::ChildIteratorType SI = BlockTraits::child_begin(Out); - ++SI; - if (SI != BlockTraits::child_end(Out)) + if (llvm::size(llvm::children(Out)) != 1) return nullptr; // Multiple exits from the block, must not be a preheader. // The predecessor has exactly one successor, so it is a preheader. @@ -231,7 +228,7 @@ BlockT *LoopBase::getLoopPredecessor() const { // Loop over the predecessors of the header node... BlockT *Header = getHeader(); - for (const auto Pred : children>(Header)) { + for (const auto Pred : inverse_children(Header)) { if (!contains(Pred)) { // If the block is not in the loop... if (Out && Out != Pred) return nullptr; // Multiple predecessors outside the loop @@ -249,7 +246,7 @@ BlockT *LoopBase::getLoopLatch() const { assert(!isInvalid() && "Loop not in a valid state!"); BlockT *Header = getHeader(); BlockT *Latch = nullptr; - for (const auto Pred : children>(Header)) { + for (const auto Pred : inverse_children(Header)) { if (contains(Pred)) { if (Latch) return nullptr; @@ -331,20 +328,16 @@ void LoopBase::verifyLoop() const { // Check the individual blocks. for (BlockT *BB : depth_first_ext(getHeader(), VisitSet)) { - assert(std::any_of(GraphTraits::child_begin(BB), - GraphTraits::child_end(BB), - [&](BlockT *B) { return contains(B); }) && + assert(llvm::any_of(children(BB), + [&](BlockT *B) { return contains(B); }) && "Loop block has no in-loop successors!"); - assert(std::any_of(GraphTraits>::child_begin(BB), - GraphTraits>::child_end(BB), - [&](BlockT *B) { return contains(B); }) && + assert(llvm::any_of(inverse_children(BB), + [&](BlockT *B) { return contains(B); }) && "Loop block has no in-loop predecessors!"); SmallVector OutsideLoopPreds; - for (BlockT *B : - llvm::make_range(GraphTraits>::child_begin(BB), - GraphTraits>::child_end(BB))) + for (BlockT *B : inverse_children(BB)) if (!contains(B)) OutsideLoopPreds.push_back(B); @@ -496,7 +489,7 @@ static void discoverAndMapSubloop(LoopT *L, ArrayRef Backedges, // within this subloop tree itself. Note that a predecessor may directly // reach another subloop that is not yet discovered to be a subloop of // this loop, which we must traverse. - for (const auto Pred : children>(PredBB)) { + for (const auto Pred : inverse_children(PredBB)) { if (LI->getLoopFor(Pred) != Subloop) ReverseCFGWorklist.push_back(Pred); } @@ -579,7 +572,7 @@ void LoopInfoBase::analyze(const DomTreeBase &DomTree) { SmallVector Backedges; // Check each predecessor of the potential loop header. - for (const auto Backedge : children>(Header)) { + for (const auto Backedge : inverse_children(Header)) { // If Header dominates predBB, this is a new loop. Collect the backedges. const DomTreeNodeBase *BackedgeNode = DomTree.getNode(Backedge); if (BackedgeNode && DomTree.dominates(DomNode, BackedgeNode)) diff --git a/llvm/include/llvm/Support/JSON.h b/llvm/include/llvm/Support/JSON.h index a81881c52d6..8b437bbabd9 100644 --- a/llvm/include/llvm/Support/JSON.h +++ b/llvm/include/llvm/Support/JSON.h @@ -47,9 +47,10 @@ #define LLVM_SUPPORT_JSON_H #include "llvm/ADT/DenseMap.h" +#include "llvm/ADT/STLFunctionalExtras.h" #include "llvm/ADT/SmallVector.h" #include "llvm/ADT/StringRef.h" -#include "llvm/ADT/STLFunctionalExtras.h" +#include "llvm/Support/Compiler.h" #include "llvm/Support/Error.h" #include "llvm/Support/FormatVariadic.h" #include "llvm/Support/raw_ostream.h" @@ -482,6 +483,18 @@ private: friend class Object; template void create(U &&... V) { +#if LLVM_ADDRESS_SANITIZER_BUILD + // Unpoisoning to prevent overwriting poisoned object (e.g., annotated short + // string). Objects that have had their memory poisoned may cause an ASan + // error if their memory is reused without calling their destructor. + // Unpoisoning the memory prevents this error from occurring. + // FIXME: This is a temporary solution to prevent buildbots from failing. + // The more appropriate approach would be to call the object's destructor + // to unpoison memory. This would prevent any potential memory leaks (long + // strings). Read for details: + // https://github.com/llvm/llvm-project/pull/79065#discussion_r1462621761 + __asan_unpoison_memory_region(&Union, sizeof(T)); +#endif new (reinterpret_cast(&Union)) T(std::forward(V)...); } template T &as() const { diff --git a/llvm/include/llvm/Support/MathExtras.h b/llvm/include/llvm/Support/MathExtras.h index 7278c4eb769..aa4f4d2ed42 100644 --- a/llvm/include/llvm/Support/MathExtras.h +++ b/llvm/include/llvm/Support/MathExtras.h @@ -359,9 +359,9 @@ constexpr inline uint64_t NextPowerOf2(uint64_t A) { /// Returns the power of two which is greater than or equal to the given value. /// Essentially, it is a ceil operation across the domain of powers of two. inline uint64_t PowerOf2Ceil(uint64_t A) { - if (!A) + if (!A || A > UINT64_MAX / 2) return 0; - return NextPowerOf2(A - 1); + return UINT64_C(1) << Log2_64_Ceil(A); } /// Returns the next integer (mod 2**64) that is greater than or equal to diff --git a/llvm/include/llvm/Support/RISCVAttributes.h b/llvm/include/llvm/Support/RISCVAttributes.h index a8ce8f4d8da..8643debb78e 100644 --- a/llvm/include/llvm/Support/RISCVAttributes.h +++ b/llvm/include/llvm/Support/RISCVAttributes.h @@ -34,7 +34,7 @@ enum AttrType : unsigned { PRIV_SPEC_REVISION = 12, }; -enum StackAlign { ALIGN_4 = 4, ALIGN_16 = 16 }; +enum StackAlign { ALIGN_4 = 4, ALIGN_8 = 8, ALIGN_16 = 16 }; enum { NOT_ALLOWED = 0, ALLOWED = 1 }; diff --git a/llvm/include/llvm/Support/TargetOpcodes.def b/llvm/include/llvm/Support/TargetOpcodes.def index c005218c80f..abb237083d2 100644 --- a/llvm/include/llvm/Support/TargetOpcodes.def +++ b/llvm/include/llvm/Support/TargetOpcodes.def @@ -170,15 +170,10 @@ HANDLE_TARGET_OPCODE(LOCAL_ESCAPE) /// comparisons into existing memory operations. HANDLE_TARGET_OPCODE(FAULTING_OP) -/// Wraps a machine instruction to add patchability constraints. An -/// instruction wrapped in PATCHABLE_OP has to either have a minimum +/// Precedes a machine instruction to add patchability constraints. An +/// instruction after PATCHABLE_OP has to either have a minimum /// size or be preceded with a nop of that size. The first operand is -/// an immediate denoting the minimum size of the instruction, the -/// second operand is an immediate denoting the opcode of the original -/// instruction. The rest of the operands are the operands of the -/// original instruction. -/// PATCHABLE_OP can be used as second operand to only insert a nop of -/// required size. +/// an immediate denoting the minimum size of the following instruction. HANDLE_TARGET_OPCODE(PATCHABLE_OP) /// This is a marker instruction which gets translated into a nop sled, useful diff --git a/llvm/include/llvm/TableGen/StringToOffsetTable.h b/llvm/include/llvm/TableGen/StringToOffsetTable.h index 7fcf20abed6..66bcc81c94b 100644 --- a/llvm/include/llvm/TableGen/StringToOffsetTable.h +++ b/llvm/include/llvm/TableGen/StringToOffsetTable.h @@ -45,7 +45,7 @@ public: // Escape the string. SmallString<256> Str; raw_svector_ostream(Str).write_escaped(AggregateString); - AggregateString = std::string(Str.str()); + AggregateString = std::string(Str); O << " \""; unsigned CharsPrinted = 0; diff --git a/llvm/include/llvm/Target/CGPassBuilderOption.h b/llvm/include/llvm/Target/CGPassBuilderOption.h index 6b5c023a9b6..8ab6d63a000 100644 --- a/llvm/include/llvm/Target/CGPassBuilderOption.h +++ b/llvm/include/llvm/Target/CGPassBuilderOption.h @@ -52,7 +52,7 @@ struct CGPassBuilderOption { bool RequiresCodeGenSCCOrder = false; RunOutliner EnableMachineOutliner = RunOutliner::TargetDefault; - RegAllocType RegAlloc = RegAllocType::Default; + StringRef RegAlloc = "default"; std::optional EnableGlobalISelAbort; std::string FSProfileFile; std::string FSRemappingFile; diff --git a/llvm/include/llvm/Target/Target.td b/llvm/include/llvm/Target/Target.td index 3b1d2f45267..0d97a47190b 100644 --- a/llvm/include/llvm/Target/Target.td +++ b/llvm/include/llvm/Target/Target.td @@ -459,6 +459,52 @@ class DwarfRegAlias { Register DwarfAlias = reg; } +//===----------------------------------------------------------------------===// +// SubtargetFeature - A characteristic of the chip set. +// +class SubtargetFeature i = []> { + // Name - Feature name. Used by command line (-mattr=) to determine the + // appropriate target chip. + // + string Name = n; + + // FieldName - Field in XXXSubtarget to be set by feature. + // + string FieldName = f; + + // Value - Value the XXXSubtarget field to be set to by feature. + // + // A value of "true" or "false" implies the field is a bool. Otherwise, + // it is assumed to be an integer. the integer value may be the name of an + // enum constant. If multiple features use the same integer field, the + // field will be set to the maximum value of all enabled features that + // share the field. + // + string Value = v; + + // Desc - Feature description. Used by command line (-mattr=) to display help + // information. + // + string Desc = d; + + // Implies - Features that this feature implies are present. If one of those + // features isn't set, then this one shouldn't be set either. + // + list Implies = i; +} + +/// Specifies a Subtarget feature that this instruction is deprecated on. +class Deprecated { + SubtargetFeature DeprecatedFeatureMask = dep; +} + +/// A custom predicate used to determine if an instruction is +/// deprecated or not. +class ComplexDeprecationPredicate { + string ComplexDeprecationPredicate = dep; +} + //===----------------------------------------------------------------------===// // Pull in the common support for MCPredicate (portable scheduling predicates). // @@ -1680,52 +1726,6 @@ class Target { int AllowRegisterRenaming = 0; } -//===----------------------------------------------------------------------===// -// SubtargetFeature - A characteristic of the chip set. -// -class SubtargetFeature i = []> { - // Name - Feature name. Used by command line (-mattr=) to determine the - // appropriate target chip. - // - string Name = n; - - // FieldName - Field in XXXSubtarget to be set by feature. - // - string FieldName = f; - - // Value - Value the XXXSubtarget field to be set to by feature. - // - // A value of "true" or "false" implies the field is a bool. Otherwise, - // it is assumed to be an integer. the integer value may be the name of an - // enum constant. If multiple features use the same integer field, the - // field will be set to the maximum value of all enabled features that - // share the field. - // - string Value = v; - - // Desc - Feature description. Used by command line (-mattr=) to display help - // information. - // - string Desc = d; - - // Implies - Features that this feature implies are present. If one of those - // features isn't set, then this one shouldn't be set either. - // - list Implies = i; -} - -/// Specifies a Subtarget feature that this instruction is deprecated on. -class Deprecated { - SubtargetFeature DeprecatedFeatureMask = dep; -} - -/// A custom predicate used to determine if an instruction is -/// deprecated or not. -class ComplexDeprecationPredicate { - string ComplexDeprecationPredicate = dep; -} - //===----------------------------------------------------------------------===// // Processor chip sets - These values represent each of the chip sets supported // by the scheduler. Each Processor definition requires corresponding diff --git a/llvm/include/llvm/Target/TargetMachine.h b/llvm/include/llvm/Target/TargetMachine.h index 1fe47dec70b..a522a12299b 100644 --- a/llvm/include/llvm/Target/TargetMachine.h +++ b/llvm/include/llvm/Target/TargetMachine.h @@ -248,6 +248,9 @@ public: /// Returns true if this target uses emulated TLS. bool useEmulatedTLS() const; + /// Returns true if this target uses TLS Descriptors. + bool useTLSDESC() const; + /// Returns the TLS model which should be used for the given global variable. TLSModel::Model getTLSModel(const GlobalValue *GV) const; diff --git a/llvm/include/llvm/Target/TargetOptions.h b/llvm/include/llvm/Target/TargetOptions.h index 4df897c047a..d02d1699813 100644 --- a/llvm/include/llvm/Target/TargetOptions.h +++ b/llvm/include/llvm/Target/TargetOptions.h @@ -145,13 +145,13 @@ namespace llvm { IgnoreXCOFFVisibility(false), XCOFFTracebackTable(true), UniqueSectionNames(true), UniqueBasicBlockSectionNames(false), TrapUnreachable(false), NoTrapAfterNoreturn(false), TLSSize(0), - EmulatedTLS(false), EnableIPRA(false), EmitStackSizeSection(false), - EnableMachineOutliner(false), EnableMachineFunctionSplitter(false), - SupportsDefaultOutlining(false), EmitAddrsig(false), - EmitCallSiteInfo(false), SupportsDebugEntryValues(false), - EnableDebugEntryValues(false), ValueTrackingVariableLocations(false), - ForceDwarfFrameSection(false), XRayFunctionIndex(true), - DebugStrictDwarf(false), Hotpatch(false), + EmulatedTLS(false), EnableTLSDESC(false), EnableIPRA(false), + EmitStackSizeSection(false), EnableMachineOutliner(false), + EnableMachineFunctionSplitter(false), SupportsDefaultOutlining(false), + EmitAddrsig(false), EmitCallSiteInfo(false), + SupportsDebugEntryValues(false), EnableDebugEntryValues(false), + ValueTrackingVariableLocations(false), ForceDwarfFrameSection(false), + XRayFunctionIndex(true), DebugStrictDwarf(false), Hotpatch(false), PPCGenScalarMASSEntries(false), JMCInstrument(false), EnableCFIFixup(false), MisExpect(false), XCOFFReadOnlyPointers(false), FPDenormalMode(DenormalMode::IEEE, DenormalMode::IEEE) {} @@ -295,6 +295,9 @@ namespace llvm { /// function in the runtime library.. unsigned EmulatedTLS : 1; + /// EnableTLSDESC - This flag enables TLS Descriptors. + unsigned EnableTLSDESC : 1; + /// This flag enables InterProcedural Register Allocation (IPRA). unsigned EnableIPRA : 1; diff --git a/llvm/include/llvm/Target/TargetPfmCounters.td b/llvm/include/llvm/Target/TargetPfmCounters.td index 33dff741fa2..c56f388fbd9 100644 --- a/llvm/include/llvm/Target/TargetPfmCounters.td +++ b/llvm/include/llvm/Target/TargetPfmCounters.td @@ -36,6 +36,13 @@ class ValidationEvent { } def InstructionRetired : ValidationEvent<0>; +def L1DCacheLoadMiss : ValidationEvent<1>; +def L1DCacheStoreMiss : ValidationEvent<2>; +def L1ICacheLoadMiss : ValidationEvent<3>; +def DataTLBLoadMiss : ValidationEvent<4>; +def DataTLBStoreMiss : ValidationEvent<5>; +def InstructionTLBLoadMiss : ValidationEvent<6>; + // PfmValidationCounter provides a mapping between the events that are // are interesting in regards to the snippet execution environment and diff --git a/llvm/include/llvm/Target/TargetSchedule.td b/llvm/include/llvm/Target/TargetSchedule.td index 2016d452afb..032de728517 100644 --- a/llvm/include/llvm/Target/TargetSchedule.td +++ b/llvm/include/llvm/Target/TargetSchedule.td @@ -658,7 +658,8 @@ def OneUse : OneUsePred; // return true; // } // ``` -class Fusion predicates> { +class Fusion predicates> + : SubtargetFeature { list Predicates = predicates; } @@ -679,21 +680,23 @@ class Fusion predicates> { // return true; // } // ``` -class SimpleFusion prolog = [], list epilog = []> - : Fusion, - WildcardTrue, - FirstFusionPredicateWithMCInstPredicate, - SecondFusionPredicateWithMCInstPredicate< - CheckAny<[ - CheckIsVRegOperand<0>, - CheckSameRegOperand<0, 1> - ]>>, - OneUse, - TieReg<0, 1>, - ], - epilog)>; + : Fusion, + WildcardTrue, + FirstFusionPredicateWithMCInstPredicate, + SecondFusionPredicateWithMCInstPredicate< + CheckAny<[ + CheckIsVRegOperand<0>, + CheckSameRegOperand<0, 1> + ]>>, + OneUse, + TieReg<0, 1>, + ], + epilog)>; diff --git a/llvm/include/llvm/TargetParser/AArch64TargetParser.h b/llvm/include/llvm/TargetParser/AArch64TargetParser.h index 2fe4d5eeb74..623fdc21ba6 100644 --- a/llvm/include/llvm/TargetParser/AArch64TargetParser.h +++ b/llvm/include/llvm/TargetParser/AArch64TargetParser.h @@ -27,6 +27,10 @@ namespace llvm { class Triple; namespace AArch64 { + +struct ArchInfo; +struct CpuInfo; + // Function Multi Versioning CPU features. They must be kept in sync with // compiler-rt enum CPUFeatures in lib/builtins/cpu_model.c with FEAT_MAX as // sentinel. @@ -90,6 +94,7 @@ enum CPUFeatures { FEAT_SME_I64, FEAT_SME2, FEAT_RCPC3, + FEAT_MOPS, FEAT_MAX, FEAT_EXT = 62, FEAT_INIT @@ -176,6 +181,8 @@ enum ArchExtKind : unsigned { AEK_CPA = 72, // FEAT_CPA AEK_PAUTHLR = 73, // FEAT_PAuth_LR AEK_TLBIW = 74, // FEAT_TLBIW + AEK_JSCVT = 75, // FEAT_JSCVT + AEK_FCMA = 76, // FEAT_FCMA AEK_NUM_EXTENSIONS }; using ExtensionBitset = Bitset; @@ -221,7 +228,7 @@ inline constexpr ExtensionInfo Extensions[] = { {"ebf16", AArch64::AEK_NONE, {}, {}, FEAT_EBF16, "+bf16", 290}, {"f32mm", AArch64::AEK_F32MM, "+f32mm", "-f32mm", FEAT_SVE_F32MM, "+sve,+f32mm,+fullfp16,+fp-armv8,+neon", 350}, {"f64mm", AArch64::AEK_F64MM, "+f64mm", "-f64mm", FEAT_SVE_F64MM, "+sve,+f64mm,+fullfp16,+fp-armv8,+neon", 360}, - {"fcma", AArch64::AEK_NONE, {}, {}, FEAT_FCMA, "+fp-armv8,+neon,+complxnum", 220}, + {"fcma", AArch64::AEK_FCMA, "+complxnum", "-complxnum", FEAT_FCMA, "+fp-armv8,+neon,+complxnum", 220}, {"flagm", AArch64::AEK_FLAGM, "+flagm", "-flagm", FEAT_FLAGM, "+flagm", 20}, {"flagm2", AArch64::AEK_NONE, {}, {}, FEAT_FLAGM2, "+flagm,+altnzcv", 30}, {"fp", AArch64::AEK_FP, "+fp-armv8", "-fp-armv8", FEAT_FP, "+fp-armv8,+neon", 90}, @@ -231,7 +238,7 @@ inline constexpr ExtensionInfo Extensions[] = { {"hbc", AArch64::AEK_HBC, "+hbc", "-hbc", FEAT_INIT, "", 0}, {"i8mm", AArch64::AEK_I8MM, "+i8mm", "-i8mm", FEAT_I8MM, "+i8mm", 270}, {"ite", AArch64::AEK_ITE, "+ite", "-ite", FEAT_INIT, "", 0}, - {"jscvt", AArch64::AEK_NONE, {}, {}, FEAT_JSCVT, "+fp-armv8,+neon,+jsconv", 210}, + {"jscvt", AArch64::AEK_JSCVT, "+jsconv", "-jsconv", FEAT_JSCVT, "+fp-armv8,+neon,+jsconv", 210}, {"ls64_accdata", AArch64::AEK_NONE, {}, {}, FEAT_LS64_ACCDATA, "+ls64", 540}, {"ls64_v", AArch64::AEK_NONE, {}, {}, FEAT_LS64_V, "", 530}, {"ls64", AArch64::AEK_LS64, "+ls64", "-ls64", FEAT_LS64, "", 520}, @@ -240,7 +247,7 @@ inline constexpr ExtensionInfo Extensions[] = { {"memtag", AArch64::AEK_MTE, "+mte", "-mte", FEAT_MEMTAG, "", 440}, {"memtag2", AArch64::AEK_NONE, {}, {}, FEAT_MEMTAG2, "+mte", 450}, {"memtag3", AArch64::AEK_NONE, {}, {}, FEAT_MEMTAG3, "+mte", 460}, - {"mops", AArch64::AEK_MOPS, "+mops", "-mops", FEAT_INIT, "", 0}, + {"mops", AArch64::AEK_MOPS, "+mops", "-mops", FEAT_MOPS, "+mops", 650}, {"pauth", AArch64::AEK_PAUTH, "+pauth", "-pauth", FEAT_INIT, "", 0}, {"pmull", AArch64::AEK_NONE, {}, {}, FEAT_PMULL, "+aes,+fp-armv8,+neon", 160}, {"pmuv3", AArch64::AEK_PERFMON, "+perfmon", "-perfmon", FEAT_INIT, "", 0}, @@ -306,6 +313,107 @@ inline constexpr ExtensionInfo Extensions[] = { }; // clang-format on +struct ExtensionSet { + // Set of extensions which are currently enabled. + ExtensionBitset Enabled; + // Set of extensions which have been enabled or disabled at any point. Used + // to avoid cluttering the cc1 command-line with lots of unneeded features. + ExtensionBitset Touched; + // Base architecture version, which we need to know because some feature + // dependencies change depending on this. + const ArchInfo *BaseArch; + + ExtensionSet() : Enabled(), Touched(), BaseArch(nullptr) {} + + // Enable the given architecture extension, and any other extensions it + // depends on. Does not change the base architecture, or follow dependencies + // between features which are only related by required arcitecture versions. + void enable(ArchExtKind E); + + // Disable the given architecture extension, and any other extensions which + // depend on it. Does not change the base architecture, or follow + // dependencies between features which are only related by required + // arcitecture versions. + void disable(ArchExtKind E); + + // Add default extensions for the given CPU. Records the base architecture, + // to later resolve dependencies which depend on it. + void addCPUDefaults(const CpuInfo &CPU); + + // Add default extensions for the given architecture version. Records the + // base architecture, to later resolve dependencies which depend on it. + void addArchDefaults(const ArchInfo &Arch); + + // Add or remove a feature based on a modifier string. The string must be of + // the form "" to enable a feature or "no" to disable it. This + // will also enable or disable any features as required by the dependencies + // between them. + bool parseModifier(StringRef Modifier); + + // Convert the set of enabled extension to an LLVM feature list, appending + // them to Features. + void toLLVMFeatureList(std::vector &Features) const; +}; + +// Represents a dependency between two architecture extensions. Later is the +// feature which was added to the architecture after Earlier, and expands the +// functionality provided by it. If Later is enabled, then Earlier will also be +// enabled. If Earlier is disabled, then Later will also be disabled. +struct ExtensionDependency { + ArchExtKind Earlier; + ArchExtKind Later; +}; + +// clang-format off +// Each entry here is a link in the dependency chain starting from the +// extension that was added to the architecture first. +inline constexpr ExtensionDependency ExtensionDependencies[] = { + {AEK_FP, AEK_FP16}, + {AEK_FP, AEK_SIMD}, + {AEK_FP, AEK_JSCVT}, + {AEK_FP, AEK_FP8}, + {AEK_SIMD, AEK_CRYPTO}, + {AEK_SIMD, AEK_AES}, + {AEK_SIMD, AEK_SHA2}, + {AEK_SIMD, AEK_SHA3}, + {AEK_SIMD, AEK_SM4}, + {AEK_SIMD, AEK_RDM}, + {AEK_SIMD, AEK_DOTPROD}, + {AEK_SIMD, AEK_FCMA}, + {AEK_FP16, AEK_FP16FML}, + {AEK_FP16, AEK_SVE}, + {AEK_BF16, AEK_SME}, + {AEK_BF16, AEK_B16B16}, + {AEK_SVE, AEK_SVE2}, + {AEK_SVE, AEK_F32MM}, + {AEK_SVE, AEK_F64MM}, + {AEK_SVE2, AEK_SVE2p1}, + {AEK_SVE2, AEK_SVE2BITPERM}, + {AEK_SVE2, AEK_SVE2AES}, + {AEK_SVE2, AEK_SVE2SHA3}, + {AEK_SVE2, AEK_SVE2SM4}, + {AEK_SVE2, AEK_SMEFA64}, + {AEK_SVE2, AEK_SMEFA64}, + {AEK_SME, AEK_SME2}, + {AEK_SME, AEK_SMEF16F16}, + {AEK_SME, AEK_SMEF64F64}, + {AEK_SME, AEK_SMEI16I64}, + {AEK_SME, AEK_SMEFA64}, + {AEK_SME2, AEK_SME2p1}, + {AEK_SME2, AEK_SSVE_FP8FMA}, + {AEK_SME2, AEK_SSVE_FP8DOT2}, + {AEK_SME2, AEK_SSVE_FP8DOT4}, + {AEK_SME2, AEK_SMEF8F16}, + {AEK_SME2, AEK_SMEF8F32}, + {AEK_FP8, AEK_SMEF8F16}, + {AEK_FP8, AEK_SMEF8F32}, + {AEK_LSE, AEK_LSE128}, + {AEK_PREDRES, AEK_SPECRES2}, + {AEK_RAS, AEK_RASv2}, + {AEK_RCPC, AEK_RCPC3}, +}; +// clang-format on + enum ArchProfile { AProfile = 'A', RProfile = 'R', InvalidProfile = '?' }; // Information about a specific architecture, e.g. V8.1-A @@ -327,9 +435,9 @@ struct ArchInfo { // Defines the following partial order, indicating when an architecture is // a superset of another: // - // v9.4a > v9.3a > v9.3a > v9.3a > v9a; - // v v v v v - // v8.9a > v8.8a > v8.7a > v8.6a > v8.5a > v8.4a > ... > v8a; + // v9.5a > v9.4a > v9.3a > v9.2a > v9.1a > v9a; + // v v v v v + // v8.9a > v8.8a > v8.7a > v8.6a > v8.5a > v8.4a > ... > v8a; // // v8r has no relation to anything. This is used to determine which // features to enable for a given architecture. See @@ -349,6 +457,12 @@ struct ArchInfo { return false; } + // True if this architecture is a superset of Other (including being equal to + // it). + bool is_superset(const ArchInfo &Other) const { + return (*this == Other) || implies(Other); + } + // Return ArchFeature without the leading "+". StringRef getSubArch() const { return ArchFeature.substr(1); } @@ -364,7 +478,7 @@ inline constexpr ArchInfo ARMV8_1A = { VersionTuple{8, 1}, AProfile, "armv8.1-a inline constexpr ArchInfo ARMV8_2A = { VersionTuple{8, 2}, AProfile, "armv8.2-a", "+v8.2a", (ARMV8_1A.DefaultExts | AArch64::ExtensionBitset({AArch64::AEK_RAS}))}; inline constexpr ArchInfo ARMV8_3A = { VersionTuple{8, 3}, AProfile, "armv8.3-a", "+v8.3a", (ARMV8_2A.DefaultExts | - AArch64::ExtensionBitset({AArch64::AEK_RCPC}))}; + AArch64::ExtensionBitset({AArch64::AEK_RCPC, AArch64::AEK_JSCVT, AArch64::AEK_FCMA}))}; inline constexpr ArchInfo ARMV8_4A = { VersionTuple{8, 4}, AProfile, "armv8.4-a", "+v8.4a", (ARMV8_3A.DefaultExts | AArch64::ExtensionBitset({AArch64::AEK_DOTPROD}))}; inline constexpr ArchInfo ARMV8_5A = { VersionTuple{8, 5}, AProfile, "armv8.5-a", "+v8.5a", (ARMV8_4A.DefaultExts)}; @@ -672,7 +786,8 @@ inline constexpr CpuInfo CpuInfos[] = { {"tsv110", ARMV8_2A, (AArch64::ExtensionBitset( {AArch64::AEK_AES, AArch64::AEK_SHA2, AArch64::AEK_DOTPROD, - AArch64::AEK_FP16, AArch64::AEK_FP16FML, AArch64::AEK_PROFILE}))}, + AArch64::AEK_FP16, AArch64::AEK_FP16FML, AArch64::AEK_PROFILE, + AArch64::AEK_JSCVT, AArch64::AEK_FCMA}))}, {"a64fx", ARMV8_2A, (AArch64::ExtensionBitset({AArch64::AEK_AES, AArch64::AEK_SHA2, AArch64::AEK_FP16, @@ -708,10 +823,10 @@ StringRef getArchExtFeature(StringRef ArchExt); StringRef resolveCPUAlias(StringRef CPU); // Information by Name -std::optional getArchForCpu(StringRef CPU); +const ArchInfo *getArchForCpu(StringRef CPU); // Parser -std::optional parseArch(StringRef Arch); +const ArchInfo *parseArch(StringRef Arch); std::optional parseArchExtension(StringRef Extension); // Given the name of a CPU or alias, return the correponding CpuInfo. std::optional parseCpu(StringRef Name); diff --git a/llvm/include/llvm/TargetParser/ARMTargetParser.def b/llvm/include/llvm/TargetParser/ARMTargetParser.def index c520ab898cb..1797a1b238d 100644 --- a/llvm/include/llvm/TargetParser/ARMTargetParser.def +++ b/llvm/include/llvm/TargetParser/ARMTargetParser.def @@ -151,6 +151,11 @@ ARM_ARCH("armv9.4-a", ARMV9_4A, "9.4-A", "+v9.4a", (ARM::AEK_SEC | ARM::AEK_MP | ARM::AEK_VIRT | ARM::AEK_HWDIVARM | ARM::AEK_HWDIVTHUMB | ARM::AEK_DSP | ARM::AEK_CRC | ARM::AEK_RAS | ARM::AEK_DOTPROD | ARM::AEK_BF16 | ARM::AEK_I8MM)) +ARM_ARCH("armv9.5-a", ARMV9_5A, "9.5-A", "+v9.5a", + ARMBuildAttrs::CPUArch::v9_A, FK_NEON_FP_ARMV8, + (ARM::AEK_SEC | ARM::AEK_MP | ARM::AEK_VIRT | ARM::AEK_HWDIVARM | + ARM::AEK_HWDIVTHUMB | ARM::AEK_DSP | ARM::AEK_CRC | ARM::AEK_RAS | + ARM::AEK_DOTPROD | ARM::AEK_BF16 | ARM::AEK_I8MM)) ARM_ARCH("armv8-r", ARMV8R, "8-R", "+v8r", ARMBuildAttrs::CPUArch::v8_R, FK_NEON_FP_ARMV8, (ARM::AEK_MP | ARM::AEK_VIRT | ARM::AEK_HWDIVARM | ARM::AEK_HWDIVTHUMB | diff --git a/llvm/include/llvm/TargetParser/Triple.h b/llvm/include/llvm/TargetParser/Triple.h index 95014a546f7..870dc75b1c1 100644 --- a/llvm/include/llvm/TargetParser/Triple.h +++ b/llvm/include/llvm/TargetParser/Triple.h @@ -164,6 +164,7 @@ public: SPIRVSubArch_v13, SPIRVSubArch_v14, SPIRVSubArch_v15, + SPIRVSubArch_v16, }; enum VendorType { UnknownVendor, @@ -214,6 +215,7 @@ public: TvOS, // Apple tvOS WatchOS, // Apple watchOS DriverKit, // Apple DriverKit + XROS, // Apple XROS Mesa3D, AMDPAL, // AMD PAL Runtime HermitCore, // HermitCore Unikernel/Multikernel @@ -223,7 +225,8 @@ public: ShaderModel, // DirectX ShaderModel LiteOS, Serenity, - LastOSType = Serenity + Vulkan, // Vulkan SPIR-V + LastOSType = Vulkan }; enum EnvironmentType { UnknownEnvironment, @@ -409,6 +412,10 @@ public: /// Parse the version number as with getOSVersion. VersionTuple getDriverKitVersion() const; + /// Parse the Vulkan version number from the OSVersion and SPIR-V version + /// (SubArch). This should only be called with Vulkan SPIR-V triples. + VersionTuple getVulkanVersion() const; + /// @} /// @name Direct Component Access /// @{ @@ -514,14 +521,17 @@ public: return getSubArch() == Triple::ARMSubArch_v7k; } + /// Is this an Apple XROS triple. + bool isXROS() const { return getOS() == Triple::XROS; } + /// Is this an Apple DriverKit triple. bool isDriverKit() const { return getOS() == Triple::DriverKit; } bool isOSzOS() const { return getOS() == Triple::ZOS; } - /// Is this a "Darwin" OS (macOS, iOS, tvOS, watchOS, or DriverKit). + /// Is this a "Darwin" OS (macOS, iOS, tvOS, watchOS, XROS, or DriverKit). bool isOSDarwin() const { - return isMacOSX() || isiOS() || isWatchOS() || isDriverKit(); + return isMacOSX() || isiOS() || isWatchOS() || isDriverKit() || isXROS(); } bool isSimulatorEnvironment() const { @@ -771,6 +781,8 @@ public: return getOS() == Triple::ShaderModel; } + bool isVulkanOS() const { return getOS() == Triple::Vulkan; } + bool isShaderStageEnvironment() const { EnvironmentType Env = getEnvironment(); return Env == Triple::Pixel || Env == Triple::Vertex || @@ -1021,6 +1033,13 @@ public: isWindowsCygwinEnvironment() || isOHOSFamily(); } + /// Tests whether the target uses TLS Descriptor by default. + bool hasDefaultTLSDESC() const { + // TODO: Improve check for other platforms, like Android, and RISC-V + // Note: This is currently only used on RISC-V. + return isOSBinFormatELF() && isAArch64(); + } + /// Tests whether the target uses -data-sections as default. bool hasDefaultDataSections() const { return isOSBinFormatXCOFF() || isWasm(); diff --git a/llvm/include/llvm/TargetParser/X86TargetParser.def b/llvm/include/llvm/TargetParser/X86TargetParser.def index b58feafe4e8..43162f2b52e 100644 --- a/llvm/include/llvm/TargetParser/X86TargetParser.def +++ b/llvm/include/llvm/TargetParser/X86TargetParser.def @@ -122,6 +122,7 @@ X86_CPU_SUBTYPE_ALIAS(INTEL_COREI7_ALDERLAKE, "gracemont") // // We cannot just re-sort the list though because its order is dictated by the // order of bits in CodeGenFunction::GetX86CpuSupportsMask. +// We cannot re-adjust the position of X86_FEATURE_COMPAT at the whole list. #ifndef X86_FEATURE_COMPAT #define X86_FEATURE_COMPAT(ENUM, STR, PRIORITY) X86_FEATURE(ENUM, STR) #endif @@ -184,12 +185,12 @@ X86_FEATURE (AMX_TILE, "amx-tile") X86_FEATURE (CLDEMOTE, "cldemote") X86_FEATURE (CLFLUSHOPT, "clflushopt") X86_FEATURE (CLWB, "clwb") +X86_FEATURE_COMPAT(F16C, "f16c", 38) X86_FEATURE (CLZERO, "clzero") X86_FEATURE (CMPXCHG16B, "cx16") X86_FEATURE (CMPXCHG8B, "cx8") X86_FEATURE (CRC32, "crc32") X86_FEATURE (ENQCMD, "enqcmd") -X86_FEATURE (F16C, "f16c") X86_FEATURE (FSGSBASE, "fsgsbase") X86_FEATURE (FXSR, "fxsr") X86_FEATURE (INVPCID, "invpcid") @@ -229,9 +230,9 @@ X86_FEATURE (XSAVE, "xsave") X86_FEATURE (XSAVEC, "xsavec") X86_FEATURE (XSAVEOPT, "xsaveopt") X86_FEATURE (XSAVES, "xsaves") +X86_FEATURE_COMPAT(AVX512FP16, "avx512fp16", 39) X86_FEATURE (HRESET, "hreset") X86_FEATURE (RAOINT, "raoint") -X86_FEATURE (AVX512FP16, "avx512fp16") X86_FEATURE (AMX_FP16, "amx-fp16") X86_FEATURE (CMPCCXADD, "cmpccxadd") X86_FEATURE (AVXNECONVERT, "avxneconvert") diff --git a/llvm/include/llvm/Transforms/IPO/EmbedBitcodePass.h b/llvm/include/llvm/Transforms/IPO/EmbedBitcodePass.h index 2bb7d5f1fcf..12bf0dd6581 100644 --- a/llvm/include/llvm/Transforms/IPO/EmbedBitcodePass.h +++ b/llvm/include/llvm/Transforms/IPO/EmbedBitcodePass.h @@ -24,13 +24,25 @@ namespace llvm { class Module; class Pass; +struct EmbedBitcodeOptions { + EmbedBitcodeOptions() : EmbedBitcodeOptions(false, false) {} + EmbedBitcodeOptions(bool IsThinLTO, bool EmitLTOSummary) + : IsThinLTO(IsThinLTO), EmitLTOSummary(EmitLTOSummary) {} + bool IsThinLTO; + bool EmitLTOSummary; +}; + /// Pass embeds a copy of the module optimized with the provided pass pipeline /// into a global variable. class EmbedBitcodePass : public PassInfoMixin { - ModulePassManager MPM; + bool IsThinLTO; + bool EmitLTOSummary; public: - EmbedBitcodePass() {} + EmbedBitcodePass(EmbedBitcodeOptions Opts) + : EmbedBitcodePass(Opts.IsThinLTO, Opts.EmitLTOSummary) {} + EmbedBitcodePass(bool IsThinLTO, bool EmitLTOSummary) + : IsThinLTO(IsThinLTO), EmitLTOSummary(EmitLTOSummary) {} PreservedAnalyses run(Module &M, ModuleAnalysisManager &); diff --git a/llvm/include/llvm/Transforms/Instrumentation/CGProfile.h b/llvm/include/llvm/Transforms/Instrumentation/CGProfile.h index 9f9ce42277a..0011b7b8b36 100644 --- a/llvm/include/llvm/Transforms/Instrumentation/CGProfile.h +++ b/llvm/include/llvm/Transforms/Instrumentation/CGProfile.h @@ -18,7 +18,11 @@ namespace llvm { class Module; class CGProfilePass : public PassInfoMixin { public: + CGProfilePass(bool InLTO) : InLTO(InLTO) {} PreservedAnalyses run(Module &M, ModuleAnalysisManager &AM); + +private: + bool InLTO = false; }; } // end namespace llvm diff --git a/llvm/include/llvm/Transforms/Scalar/ConstantHoisting.h b/llvm/include/llvm/Transforms/Scalar/ConstantHoisting.h index fa13ed73d50..a4d1653fdf4 100644 --- a/llvm/include/llvm/Transforms/Scalar/ConstantHoisting.h +++ b/llvm/include/llvm/Transforms/Scalar/ConstantHoisting.h @@ -153,6 +153,7 @@ private: const DataLayout *DL; BasicBlock *Entry; ProfileSummaryInfo *PSI; + bool OptForSize; /// Keeps track of constant candidates found in the function. using ConstCandVecType = std::vector; diff --git a/llvm/include/llvm/Transforms/Utils/ModuleUtils.h b/llvm/include/llvm/Transforms/Utils/ModuleUtils.h index e37547cb4ef..1ec87505544 100644 --- a/llvm/include/llvm/Transforms/Utils/ModuleUtils.h +++ b/llvm/include/llvm/Transforms/Utils/ModuleUtils.h @@ -143,12 +143,6 @@ void embedBufferInModule(Module &M, MemoryBufferRef Buf, StringRef SectionName, bool lowerGlobalIFuncUsersAsGlobalCtor( Module &M, ArrayRef IFuncsToLower = {}); -class CallInst; -namespace VFABI { -/// Overwrite the Vector Function ABI variants attribute with the names provide -/// in \p VariantMappings. -void setVectorVariantNames(CallInst *CI, ArrayRef VariantMappings); -} // End VFABI namespace } // End llvm namespace #endif // LLVM_TRANSFORMS_UTILS_MODULEUTILS_H diff --git a/llvm/include/llvm/Transforms/Utils/NameAnonGlobals.h b/llvm/include/llvm/Transforms/Utils/NameAnonGlobals.h index a59f9bc3ebf..b1c181c1211 100644 --- a/llvm/include/llvm/Transforms/Utils/NameAnonGlobals.h +++ b/llvm/include/llvm/Transforms/Utils/NameAnonGlobals.h @@ -24,6 +24,8 @@ public: NameAnonGlobalPass() = default; PreservedAnalyses run(Module &M, ModuleAnalysisManager &AM); + + static bool isRequired() { return true; } }; } // end namespace llvm diff --git a/llvm/lib/Analysis/AliasAnalysis.cpp b/llvm/lib/Analysis/AliasAnalysis.cpp index da18279ae9b..6eaaad5f332 100644 --- a/llvm/lib/Analysis/AliasAnalysis.cpp +++ b/llvm/lib/Analysis/AliasAnalysis.cpp @@ -883,6 +883,11 @@ bool llvm::isEscapeSource(const Value *V) { if (isa(V)) return true; + // Same for inttoptr constant expressions. + if (auto *CE = dyn_cast(V)) + if (CE->getOpcode() == Instruction::IntToPtr) + return true; + return false; } diff --git a/llvm/lib/Analysis/AliasSetTracker.cpp b/llvm/lib/Analysis/AliasSetTracker.cpp index 99d20c7bef3..59bb40cdba6 100644 --- a/llvm/lib/Analysis/AliasSetTracker.cpp +++ b/llvm/lib/Analysis/AliasSetTracker.cpp @@ -11,6 +11,7 @@ //===----------------------------------------------------------------------===// #include "llvm/Analysis/AliasSetTracker.h" +#include "llvm/ADT/SetVector.h" #include "llvm/ADT/StringExtras.h" #include "llvm/Analysis/AliasAnalysis.h" #include "llvm/Analysis/GuardUtils.h" @@ -34,11 +35,10 @@ using namespace llvm; -static cl::opt - SaturationThreshold("alias-set-saturation-threshold", cl::Hidden, - cl::init(250), - cl::desc("The maximum number of pointers may-alias " - "sets may contain before degradation")); +static cl::opt SaturationThreshold( + "alias-set-saturation-threshold", cl::Hidden, cl::init(250), + cl::desc("The maximum total number of memory locations alias " + "sets may contain before degradation")); /// mergeSetIn - Merge the specified alias set into this alias set. void AliasSet::mergeSetIn(AliasSet &AS, AliasSetTracker &AST, @@ -46,30 +46,27 @@ void AliasSet::mergeSetIn(AliasSet &AS, AliasSetTracker &AST, assert(!AS.Forward && "Alias set is already forwarding!"); assert(!Forward && "This set is a forwarding set!!"); - bool WasMustAlias = (Alias == SetMustAlias); // Update the alias and access types of this set... Access |= AS.Access; Alias |= AS.Alias; if (Alias == SetMustAlias) { - // Check that these two merged sets really are must aliases. Since both - // used to be must-alias sets, we can just check any pointer from each set - // for aliasing. - PointerRec *L = getSomePointer(); - PointerRec *R = AS.getSomePointer(); - - // If the pointers are not a must-alias pair, this set becomes a may alias. - if (!BatchAA.isMustAlias( - MemoryLocation(L->getValue(), L->getSize(), L->getAAInfo()), - MemoryLocation(R->getValue(), R->getSize(), R->getAAInfo()))) + // Check that these two merged sets really are must aliases. If we cannot + // find a must-alias pair between them, this set becomes a may alias. + if (!any_of(MemoryLocs, [&](const MemoryLocation &MemLoc) { + return any_of(AS.MemoryLocs, [&](const MemoryLocation &ASMemLoc) { + return BatchAA.isMustAlias(MemLoc, ASMemLoc); + }); + })) Alias = SetMayAlias; } - if (Alias == SetMayAlias) { - if (WasMustAlias) - AST.TotalMayAliasSetSize += size(); - if (AS.Alias == SetMustAlias) - AST.TotalMayAliasSetSize += AS.size(); + // Merge the list of constituent memory locations... + if (MemoryLocs.empty()) { + std::swap(MemoryLocs, AS.MemoryLocs); + } else { + append_range(MemoryLocs, AS.MemoryLocs); + AS.MemoryLocs.clear(); } bool ASHadUnknownInsts = !AS.UnknownInsts.empty(); @@ -86,18 +83,6 @@ void AliasSet::mergeSetIn(AliasSet &AS, AliasSetTracker &AST, AS.Forward = this; // Forward across AS now... addRef(); // AS is now pointing to us... - // Merge the list of constituent pointers... - if (AS.PtrList) { - SetSize += AS.size(); - AS.SetSize = 0; - *PtrListEnd = AS.PtrList; - AS.PtrList->setPrevInList(PtrListEnd); - PtrListEnd = AS.PtrListEnd; - - AS.PtrList = nullptr; - AS.PtrListEnd = &AS.PtrList; - assert(*AS.PtrListEnd == nullptr && "End of list is not null?"); - } if (ASHadUnknownInsts) AS.dropRef(AST); } @@ -106,9 +91,8 @@ void AliasSetTracker::removeAliasSet(AliasSet *AS) { if (AliasSet *Fwd = AS->Forward) { Fwd->dropRef(*this); AS->Forward = nullptr; - } else // Update TotalMayAliasSetSize only if not forwarding. - if (AS->Alias == AliasSet::SetMayAlias) - TotalMayAliasSetSize -= AS->size(); + } else // Update TotalAliasSetSize only if not forwarding. + TotalAliasSetSize -= AS->size(); AliasSets.erase(AS); // If we've removed the saturated alias set, set saturated marker back to @@ -124,42 +108,22 @@ void AliasSet::removeFromTracker(AliasSetTracker &AST) { AST.removeAliasSet(this); } -void AliasSet::addPointer(AliasSetTracker &AST, PointerRec &Entry, - LocationSize Size, const AAMDNodes &AAInfo, - bool KnownMustAlias, bool SkipSizeUpdate) { - assert(!Entry.hasAliasSet() && "Entry already in set!"); - - // Check to see if we have to downgrade to _may_ alias. - if (isMustAlias()) - if (PointerRec *P = getSomePointer()) { - if (!KnownMustAlias) { - BatchAAResults &AA = AST.getAliasAnalysis(); - AliasResult Result = AA.alias( - MemoryLocation(P->getValue(), P->getSize(), P->getAAInfo()), - MemoryLocation(Entry.getValue(), Size, AAInfo)); - if (Result != AliasResult::MustAlias) { - Alias = SetMayAlias; - AST.TotalMayAliasSetSize += size(); - } - assert(Result != AliasResult::NoAlias && "Cannot be part of must set!"); - } else if (!SkipSizeUpdate) - P->updateSizeAndAAInfo(Size, AAInfo); - } - - Entry.setAliasSet(this); - Entry.updateSizeAndAAInfo(Size, AAInfo); +void AliasSet::addMemoryLocation(AliasSetTracker &AST, + const MemoryLocation &MemLoc, + bool KnownMustAlias) { + if (isMustAlias() && !KnownMustAlias) { + // If we cannot find a must-alias with any of the existing MemoryLocs, we + // must downgrade to may-alias. + if (!any_of(MemoryLocs, [&](const MemoryLocation &ASMemLoc) { + return AST.getAliasAnalysis().isMustAlias(MemLoc, ASMemLoc); + })) + Alias = SetMayAlias; + } // Add it to the end of the list... - ++SetSize; - assert(*PtrListEnd == nullptr && "End of list is not null?"); - *PtrListEnd = &Entry; - PtrListEnd = Entry.setPrevInList(PtrListEnd); - assert(*PtrListEnd == nullptr && "End of list is not null?"); - // Entry points to alias set. - addRef(); + MemoryLocs.push_back(MemLoc); - if (Alias == SetMayAlias) - AST.TotalMayAliasSetSize++; + AST.TotalAliasSetSize++; } void AliasSet::addUnknownInst(Instruction *I, BatchAAResults &AA) { @@ -183,45 +147,26 @@ void AliasSet::addUnknownInst(Instruction *I, BatchAAResults &AA) { Access = ModRefAccess; } -/// aliasesPointer - If the specified pointer "may" (or must) alias one of the -/// members in the set return the appropriate AliasResult. Otherwise return -/// NoAlias. +/// aliasesMemoryLocation - If the specified memory location "may" (or must) +/// alias one of the members in the set return the appropriate AliasResult. +/// Otherwise return NoAlias. /// -AliasResult AliasSet::aliasesPointer(const Value *Ptr, LocationSize Size, - const AAMDNodes &AAInfo, - BatchAAResults &AA) const { +AliasResult AliasSet::aliasesMemoryLocation(const MemoryLocation &MemLoc, + BatchAAResults &AA) const { if (AliasAny) return AliasResult::MayAlias; - if (Alias == SetMustAlias) { - assert(UnknownInsts.empty() && "Illegal must alias set!"); - - // If this is a set of MustAliases, only check to see if the pointer aliases - // SOME value in the set. - PointerRec *SomePtr = getSomePointer(); - assert(SomePtr && "Empty must-alias set??"); - return AA.alias(MemoryLocation(SomePtr->getValue(), SomePtr->getSize(), - SomePtr->getAAInfo()), - MemoryLocation(Ptr, Size, AAInfo)); - } - - // If this is a may-alias set, we have to check all of the pointers in the set - // to be sure it doesn't alias the set... - for (iterator I = begin(), E = end(); I != E; ++I) { - AliasResult AR = - AA.alias(MemoryLocation(Ptr, Size, AAInfo), - MemoryLocation(I.getPointer(), I.getSize(), I.getAAInfo())); + // Check all of the memory locations in the set... + for (const auto &ASMemLoc : MemoryLocs) { + AliasResult AR = AA.alias(MemLoc, ASMemLoc); if (AR != AliasResult::NoAlias) return AR; } // Check the unknown instructions... - if (!UnknownInsts.empty()) { - for (Instruction *Inst : UnknownInsts) - if (isModOrRefSet( - AA.getModRefInfo(Inst, MemoryLocation(Ptr, Size, AAInfo)))) - return AliasResult::MayAlias; - } + for (Instruction *Inst : UnknownInsts) + if (isModOrRefSet(AA.getModRefInfo(Inst, MemLoc))) + return AliasResult::MayAlias; return AliasResult::NoAlias; } @@ -246,9 +191,8 @@ ModRefInfo AliasSet::aliasesUnknownInst(const Instruction *Inst, } ModRefInfo MR = ModRefInfo::NoModRef; - for (iterator I = begin(), E = end(); I != E; ++I) { - MR |= AA.getModRefInfo( - Inst, MemoryLocation(I.getPointer(), I.getSize(), I.getAAInfo())); + for (const auto &ASMemLoc : MemoryLocs) { + MR |= AA.getModRefInfo(Inst, ASMemLoc); if (isModAndRefSet(MR)) return MR; } @@ -256,37 +200,46 @@ ModRefInfo AliasSet::aliasesUnknownInst(const Instruction *Inst, return MR; } +AliasSet::PointerVector AliasSet::getPointers() const { + SmallSetVector Pointers; + for (const MemoryLocation &MemLoc : MemoryLocs) + Pointers.insert(MemLoc.Ptr); + return Pointers.takeVector(); +} + void AliasSetTracker::clear() { - // Delete all the PointerRec entries. - for (auto &I : PointerMap) - I.second->eraseFromList(); - PointerMap.clear(); - - // The alias sets should all be clear now. AliasSets.clear(); } -/// mergeAliasSetsForPointer - Given a pointer, merge all alias sets that may -/// alias the pointer. Return the unified set, or nullptr if no set that aliases -/// the pointer was found. MustAliasAll is updated to true/false if the pointer -/// is found to MustAlias all the sets it merged. -AliasSet *AliasSetTracker::mergeAliasSetsForPointer(const Value *Ptr, - LocationSize Size, - const AAMDNodes &AAInfo, - bool &MustAliasAll) { +/// mergeAliasSetsForMemoryLocation - Given a memory location, merge all alias +/// sets that may alias it. Return the unified set, or nullptr if no aliasing +/// set was found. A known existing alias set for the pointer value of the +/// memory location can be passed in (or nullptr if not available). MustAliasAll +/// is updated to true/false if the memory location is found to MustAlias all +/// the sets it merged. +AliasSet *AliasSetTracker::mergeAliasSetsForMemoryLocation( + const MemoryLocation &MemLoc, AliasSet *PtrAS, bool &MustAliasAll) { AliasSet *FoundSet = nullptr; MustAliasAll = true; for (AliasSet &AS : llvm::make_early_inc_range(*this)) { if (AS.Forward) continue; - AliasResult AR = AS.aliasesPointer(Ptr, Size, AAInfo, AA); - if (AR == AliasResult::NoAlias) - continue; + // An alias set that already contains a memory location with the same + // pointer value is directly assumed to MustAlias; we bypass the AA query in + // this case. + // Note: it is not guaranteed that AA would always provide the same result; + // a known exception are undef pointer values, where alias(undef, undef) is + // NoAlias, while we treat it as MustAlias. + if (&AS != PtrAS) { + AliasResult AR = AS.aliasesMemoryLocation(MemLoc, AA); + if (AR == AliasResult::NoAlias) + continue; - if (AR != AliasResult::MustAlias) - MustAliasAll = false; + if (AR != AliasResult::MustAlias) + MustAliasAll = false; + } if (!FoundSet) { // If this is the first alias set ptr can go into, remember it. @@ -317,91 +270,77 @@ AliasSet *AliasSetTracker::findAliasSetForUnknownInst(Instruction *Inst) { } AliasSet &AliasSetTracker::getAliasSetFor(const MemoryLocation &MemLoc) { + // The alias sets are indexed with a map from the memory locations' pointer + // values. If the memory location is already registered, we can find it in the + // alias set associated with its pointer. + AliasSet *&MapEntry = PointerMap[MemLoc.Ptr]; + if (MapEntry) { + collapseForwardingIn(MapEntry); + if (is_contained(MapEntry->MemoryLocs, MemLoc)) + return *MapEntry; + } - Value * const Pointer = const_cast(MemLoc.Ptr); - const LocationSize Size = MemLoc.Size; - const AAMDNodes &AAInfo = MemLoc.AATags; - - AliasSet::PointerRec &Entry = getEntryFor(Pointer); - + AliasSet *AS; + bool MustAliasAll = false; if (AliasAnyAS) { // At this point, the AST is saturated, so we only have one active alias // set. That means we already know which alias set we want to return, and - // just need to add the pointer to that set to keep the data structure - // consistent. + // just need to add the memory location to that set to keep the data + // structure consistent. // This, of course, means that we will never need a merge here. - if (Entry.hasAliasSet()) { - Entry.updateSizeAndAAInfo(Size, AAInfo); - assert(Entry.getAliasSet(*this) == AliasAnyAS && - "Entry in saturated AST must belong to only alias set"); - } else { - AliasAnyAS->addPointer(*this, Entry, Size, AAInfo); - } - return *AliasAnyAS; - } - - bool MustAliasAll = false; - // Check to see if the pointer is already known. - if (Entry.hasAliasSet()) { - // If the size changed, we may need to merge several alias sets. - // Note that we can *not* return the result of mergeAliasSetsForPointer - // due to a quirk of alias analysis behavior. Since alias(undef, undef) - // is NoAlias, mergeAliasSetsForPointer(undef, ...) will not find the - // the right set for undef, even if it exists. - if (Entry.updateSizeAndAAInfo(Size, AAInfo)) { - mergeAliasSetsForPointer(Pointer, Size, AAInfo, MustAliasAll); - - // For MustAlias sets, also update Size/AAInfo of the representative - // pointer. - AliasSet &AS = *Entry.getAliasSet(*this); - if (AS.isMustAlias()) - if (AliasSet::PointerRec *P = AS.getSomePointer()) - P->updateSizeAndAAInfo(Size, AAInfo); - } - // Return the set! - return *Entry.getAliasSet(*this)->getForwardedTarget(*this); - } - - if (AliasSet *AS = - mergeAliasSetsForPointer(Pointer, Size, AAInfo, MustAliasAll)) { + AS = AliasAnyAS; + } else if (AliasSet *AliasAS = mergeAliasSetsForMemoryLocation( + MemLoc, MapEntry, MustAliasAll)) { // Add it to the alias set it aliases. - AS->addPointer(*this, Entry, Size, AAInfo, MustAliasAll); - return *AS; + AS = AliasAS; + } else { + // Otherwise create a new alias set to hold the new memory location. + AliasSets.push_back(AS = new AliasSet()); + MustAliasAll = true; } - // Otherwise create a new alias set to hold the loaded pointer. - AliasSets.push_back(new AliasSet()); - AliasSets.back().addPointer(*this, Entry, Size, AAInfo, true); - return AliasSets.back(); + // Register memory location in selected alias set. + AS->addMemoryLocation(*this, MemLoc, MustAliasAll); + // Register selected alias set in pointer map (or ensure it is consistent with + // earlier map entry after taking into account new merging). + if (MapEntry) { + collapseForwardingIn(MapEntry); + assert(MapEntry == AS && "Memory locations with same pointer value cannot " + "be in different alias sets"); + } else { + AS->addRef(); + MapEntry = AS; + } + return *AS; } void AliasSetTracker::add(const MemoryLocation &Loc) { - addPointer(Loc, AliasSet::NoAccess); + addMemoryLocation(Loc, AliasSet::NoAccess); } void AliasSetTracker::add(LoadInst *LI) { if (isStrongerThanMonotonic(LI->getOrdering())) return addUnknown(LI); - addPointer(MemoryLocation::get(LI), AliasSet::RefAccess); + addMemoryLocation(MemoryLocation::get(LI), AliasSet::RefAccess); } void AliasSetTracker::add(StoreInst *SI) { if (isStrongerThanMonotonic(SI->getOrdering())) return addUnknown(SI); - addPointer(MemoryLocation::get(SI), AliasSet::ModAccess); + addMemoryLocation(MemoryLocation::get(SI), AliasSet::ModAccess); } void AliasSetTracker::add(VAArgInst *VAAI) { - addPointer(MemoryLocation::get(VAAI), AliasSet::ModRefAccess); + addMemoryLocation(MemoryLocation::get(VAAI), AliasSet::ModRefAccess); } void AliasSetTracker::add(AnyMemSetInst *MSI) { - addPointer(MemoryLocation::getForDest(MSI), AliasSet::ModAccess); + addMemoryLocation(MemoryLocation::getForDest(MSI), AliasSet::ModAccess); } void AliasSetTracker::add(AnyMemTransferInst *MTI) { - addPointer(MemoryLocation::getForDest(MTI), AliasSet::ModAccess); - addPointer(MemoryLocation::getForSource(MTI), AliasSet::RefAccess); + addMemoryLocation(MemoryLocation::getForDest(MTI), AliasSet::ModAccess); + addMemoryLocation(MemoryLocation::getForSource(MTI), AliasSet::RefAccess); } void AliasSetTracker::addUnknown(Instruction *Inst) { @@ -480,7 +419,7 @@ void AliasSetTracker::add(Instruction *I) { ModRefInfo ArgMask = AA.getArgModRefInfo(Call, ArgIdx); ArgMask &= CallMask; if (!isNoModRef(ArgMask)) - addPointer(ArgLoc, getAccessFromModRef(ArgMask)); + addMemoryLocation(ArgLoc, getAccessFromModRef(ArgMask)); } return; } @@ -497,7 +436,7 @@ void AliasSetTracker::add(const AliasSetTracker &AST) { assert(&AA == &AST.AA && "Merging AliasSetTracker objects with different Alias Analyses!"); - // Loop over all of the alias sets in AST, adding the pointers contained + // Loop over all of the alias sets in AST, adding the members contained // therein into the current alias sets. This can cause alias sets to be // merged together in the current AST. for (const AliasSet &AS : AST) { @@ -508,16 +447,14 @@ void AliasSetTracker::add(const AliasSetTracker &AST) { for (Instruction *Inst : AS.UnknownInsts) add(Inst); - // Loop over all of the pointers in this alias set. - for (AliasSet::iterator ASI = AS.begin(), E = AS.end(); ASI != E; ++ASI) - addPointer( - MemoryLocation(ASI.getPointer(), ASI.getSize(), ASI.getAAInfo()), - (AliasSet::AccessLattice)AS.Access); + // Loop over all of the memory locations in this alias set. + for (const MemoryLocation &ASMemLoc : AS.MemoryLocs) + addMemoryLocation(ASMemLoc, (AliasSet::AccessLattice)AS.Access); } } AliasSet &AliasSetTracker::mergeAllAliasSets() { - assert(!AliasAnyAS && (TotalMayAliasSetSize > SaturationThreshold) && + assert(!AliasAnyAS && (TotalAliasSetSize > SaturationThreshold) && "Full merge should happen once, when the saturation threshold is " "reached"); @@ -528,8 +465,8 @@ AliasSet &AliasSetTracker::mergeAllAliasSets() { for (AliasSet &AS : *this) ASVector.push_back(&AS); - // Copy all instructions and pointers into a new set, and forward all other - // sets to it. + // Copy all instructions and memory locations into a new set, and forward all + // other sets to it. AliasSets.push_back(new AliasSet()); AliasAnyAS = &AliasSets.back(); AliasAnyAS->Alias = AliasSet::SetMayAlias; @@ -553,14 +490,14 @@ AliasSet &AliasSetTracker::mergeAllAliasSets() { return *AliasAnyAS; } -AliasSet &AliasSetTracker::addPointer(MemoryLocation Loc, - AliasSet::AccessLattice E) { +AliasSet &AliasSetTracker::addMemoryLocation(MemoryLocation Loc, + AliasSet::AccessLattice E) { AliasSet &AS = getAliasSetFor(Loc); AS.Access |= E; - if (!AliasAnyAS && (TotalMayAliasSetSize > SaturationThreshold)) { + if (!AliasAnyAS && (TotalAliasSetSize > SaturationThreshold)) { // The AST is now saturated. From here on, we conservatively consider all - // pointers to alias each-other. + // elements to alias each-other. return mergeAllAliasSets(); } @@ -584,17 +521,18 @@ void AliasSet::print(raw_ostream &OS) const { if (Forward) OS << " forwarding to " << (void*)Forward; - if (!empty()) { - OS << "Pointers: "; - for (iterator I = begin(), E = end(); I != E; ++I) { - if (I != begin()) OS << ", "; - I.getPointer()->printAsOperand(OS << "("); - if (I.getSize() == LocationSize::afterPointer()) + if (!MemoryLocs.empty()) { + ListSeparator LS; + OS << "Memory locations: "; + for (const MemoryLocation &MemLoc : MemoryLocs) { + OS << LS; + MemLoc.Ptr->printAsOperand(OS << "("); + if (MemLoc.Size == LocationSize::afterPointer()) OS << ", unknown after)"; - else if (I.getSize() == LocationSize::beforeOrAfterPointer()) + else if (MemLoc.Size == LocationSize::beforeOrAfterPointer()) OS << ", unknown before-or-after)"; else - OS << ", " << I.getSize() << ")"; + OS << ", " << MemLoc.Size << ")"; } } if (!UnknownInsts.empty()) { diff --git a/llvm/lib/Analysis/BasicAliasAnalysis.cpp b/llvm/lib/Analysis/BasicAliasAnalysis.cpp index a4a0846df7a..3178e2d2781 100644 --- a/llvm/lib/Analysis/BasicAliasAnalysis.cpp +++ b/llvm/lib/Analysis/BasicAliasAnalysis.cpp @@ -215,7 +215,7 @@ bool EarliestEscapeInfo::isNotCapturedBefore(const Value *Object, auto Iter = EarliestEscapes.insert({Object, nullptr}); if (Iter.second) { Instruction *EarliestCapture = FindEarliestCapture( - Object, *const_cast(I->getFunction()), + Object, *const_cast(DT.getRoot()->getParent()), /*ReturnCaptures=*/false, /*StoreCaptures=*/true, DT); if (EarliestCapture) { auto Ins = Inst2Obj.insert({EarliestCapture, {}}); @@ -228,6 +228,10 @@ bool EarliestEscapeInfo::isNotCapturedBefore(const Value *Object, if (!Iter.first->second) return true; + // No context instruction means any use is capturing. + if (!I) + return false; + if (I == Iter.first->second) { if (OrAt) return false; @@ -393,10 +397,8 @@ static LinearExpression GetLinearExpression( // further. return Val; case Instruction::Or: - // X|C == X+C if all the bits in C are unset in X. Otherwise we can't - // analyze it. - if (!MaskedValueIsZero(BOp->getOperand(0), RHSC->getValue(), - SimplifyQuery(DL, DT, AC, BOp))) + // X|C == X+C if it is disjoint. Otherwise we can't analyze it. + if (!cast(BOp)->isDisjoint()) return Val; [[fallthrough]]; @@ -1504,11 +1506,6 @@ AliasResult BasicAAResult::aliasCheck(const Value *V1, LocationSize V1Size, if (isIdentifiedObject(O1) && isIdentifiedObject(O2)) return AliasResult::NoAlias; - // Constant pointers can't alias with non-const isIdentifiedObject objects. - if ((isa(O1) && isIdentifiedObject(O2) && !isa(O2)) || - (isa(O2) && isIdentifiedObject(O1) && !isa(O1))) - return AliasResult::NoAlias; - // Function arguments can't alias with things that are known to be // unambigously identified at the function level. if ((isa(O1) && isIdentifiedFunctionLocal(O2)) || @@ -1524,11 +1521,11 @@ AliasResult BasicAAResult::aliasCheck(const Value *V1, LocationSize V1Size, // temporary store the nocapture argument's value in a temporary memory // location if that memory location doesn't escape. Or it may pass a // nocapture value to other functions as long as they don't capture it. - if (isEscapeSource(O1) && - AAQI.CI->isNotCapturedBefore(O2, cast(O1), /*OrAt*/ true)) + if (isEscapeSource(O1) && AAQI.CI->isNotCapturedBefore( + O2, dyn_cast(O1), /*OrAt*/ true)) return AliasResult::NoAlias; - if (isEscapeSource(O2) && - AAQI.CI->isNotCapturedBefore(O1, cast(O2), /*OrAt*/ true)) + if (isEscapeSource(O2) && AAQI.CI->isNotCapturedBefore( + O1, dyn_cast(O2), /*OrAt*/ true)) return AliasResult::NoAlias; } diff --git a/llvm/lib/Analysis/InlineOrder.cpp b/llvm/lib/Analysis/InlineOrder.cpp index d6acafdc6ab..09fc4f9a00f 100644 --- a/llvm/lib/Analysis/InlineOrder.cpp +++ b/llvm/lib/Analysis/InlineOrder.cpp @@ -262,7 +262,7 @@ public: void erase_if(function_ref Pred) override { auto PredWrapper = [=](CallBase *CB) -> bool { - return Pred(std::make_pair(CB, 0)); + return Pred(std::make_pair(CB, InlineHistoryMap[CB])); }; llvm::erase_if(Heap, PredWrapper); std::make_heap(Heap.begin(), Heap.end(), isLess); diff --git a/llvm/lib/Analysis/LoopAccessAnalysis.cpp b/llvm/lib/Analysis/LoopAccessAnalysis.cpp index aed60cc5a3f..7e67c901528 100644 --- a/llvm/lib/Analysis/LoopAccessAnalysis.cpp +++ b/llvm/lib/Analysis/LoopAccessAnalysis.cpp @@ -1115,6 +1115,7 @@ bool AccessAnalysis::canCheckPtrAtRT(RuntimePointerChecking &RtCheck, int NumWritePtrChecks = 0; bool CanDoAliasSetRT = true; ++ASId; + auto ASPointers = AS.getPointers(); // We assign consecutive id to access from different dependence sets. // Accesses within the same set don't need a runtime check. @@ -1126,8 +1127,8 @@ bool AccessAnalysis::canCheckPtrAtRT(RuntimePointerChecking &RtCheck, // First, count how many write and read accesses are in the alias set. Also // collect MemAccessInfos for later. SmallVector AccessInfos; - for (const auto &A : AS) { - Value *Ptr = A.getValue(); + for (const Value *Ptr_ : ASPointers) { + Value *Ptr = const_cast(Ptr_); bool IsWrite = Accesses.count(MemAccessInfo(Ptr, true)); if (IsWrite) ++NumWritePtrChecks; @@ -1140,10 +1141,11 @@ bool AccessAnalysis::canCheckPtrAtRT(RuntimePointerChecking &RtCheck, // or a single write and no reads. if (NumWritePtrChecks == 0 || (NumWritePtrChecks == 1 && NumReadPtrChecks == 0)) { - assert((AS.size() <= 1 || - all_of(AS, - [this](auto AC) { - MemAccessInfo AccessWrite(AC.getValue(), true); + assert((ASPointers.size() <= 1 || + all_of(ASPointers, + [this](const Value *Ptr) { + MemAccessInfo AccessWrite(const_cast(Ptr), + true); return DepCands.findValue(AccessWrite) == DepCands.end(); })) && "Can only skip updating CanDoRT below, if all entries in AS " @@ -1271,8 +1273,9 @@ void AccessAnalysis::processMemAccesses() { // set. for (const auto &AS : AST) { // Note that both the alias-set tracker and the alias sets themselves used - // linked lists internally and so the iteration order here is deterministic - // (matching the original instruction order within each set). + // ordered collections internally and so the iteration order here is + // deterministic. + auto ASPointers = AS.getPointers(); bool SetHasWrite = false; @@ -1289,8 +1292,8 @@ void AccessAnalysis::processMemAccesses() { bool UseDeferred = SetIteration > 0; PtrAccessMap &S = UseDeferred ? DeferredAccesses : Accesses; - for (const auto &AV : AS) { - Value *Ptr = AV.getValue(); + for (const Value *Ptr_ : ASPointers) { + Value *Ptr = const_cast(Ptr_); // For a single memory access in AliasSetTracker, Accesses may contain // both read and write, and they both need to be handled for CheckDeps. diff --git a/llvm/lib/Analysis/ScalarEvolution.cpp b/llvm/lib/Analysis/ScalarEvolution.cpp index 623814c038a..2acb45837c4 100644 --- a/llvm/lib/Analysis/ScalarEvolution.cpp +++ b/llvm/lib/Analysis/ScalarEvolution.cpp @@ -10721,6 +10721,10 @@ bool ScalarEvolution::isKnownNonPositive(const SCEV *S) { } bool ScalarEvolution::isKnownNonZero(const SCEV *S) { + // Query push down for cases where the unsigned range is + // less than sufficient. + if (const auto *SExt = dyn_cast(S)) + return isKnownNonZero(SExt->getOperand(0)); return getUnsignedRangeMin(S) != 0; } diff --git a/llvm/lib/Analysis/StackSafetyAnalysis.cpp b/llvm/lib/Analysis/StackSafetyAnalysis.cpp index da21e3f28e7..19991c1a7ba 100644 --- a/llvm/lib/Analysis/StackSafetyAnalysis.cpp +++ b/llvm/lib/Analysis/StackSafetyAnalysis.cpp @@ -331,7 +331,7 @@ ConstantRange StackSafetyLocalAnalysis::getMemIntrinsicAccessRange( const SCEV *Expr = SE.getTruncateOrZeroExtend(SE.getSCEV(MI->getLength()), CalculationTy); ConstantRange Sizes = SE.getSignedRange(Expr); - if (Sizes.getUpper().isNegative() || isUnsafe(Sizes)) + if (!Sizes.getUpper().isStrictlyPositive() || isUnsafe(Sizes)) return UnknownRange; Sizes = Sizes.sextOrTrunc(PointerSize); ConstantRange SizeRange(APInt::getZero(PointerSize), Sizes.getUpper() - 1); diff --git a/llvm/lib/Analysis/TargetLibraryInfo.cpp b/llvm/lib/Analysis/TargetLibraryInfo.cpp index bbb7c86d218..25951d2a7fe 100644 --- a/llvm/lib/Analysis/TargetLibraryInfo.cpp +++ b/llvm/lib/Analysis/TargetLibraryInfo.cpp @@ -163,12 +163,6 @@ bool TargetLibraryInfoImpl::isCallingConvCCompatible(Function *F) { /// triple gets a sane set of defaults. static void initialize(TargetLibraryInfoImpl &TLI, const Triple &T, ArrayRef StandardNames) { - // Verify that the StandardNames array is in alphabetical order. - assert( - llvm::is_sorted(StandardNames, - [](StringRef LHS, StringRef RHS) { return LHS < RHS; }) && - "TargetLibraryInfoImpl function names must be sorted"); - // Set IO unlocked variants as unavailable // Set them as available per system below TLI.setUnavailable(LibFunc_getc_unlocked); @@ -546,6 +540,7 @@ static void initialize(TargetLibraryInfoImpl &TLI, const Triple &T, case Triple::IOS: case Triple::TvOS: case Triple::WatchOS: + case Triple::XROS: TLI.setUnavailable(LibFunc_exp10l); if (!T.isWatchOS() && (T.isOSVersionLT(7, 0) || (T.isOSVersionLT(9, 0) && T.isX86()))) { @@ -581,6 +576,7 @@ static void initialize(TargetLibraryInfoImpl &TLI, const Triple &T, case Triple::IOS: case Triple::TvOS: case Triple::WatchOS: + case Triple::XROS: case Triple::FreeBSD: case Triple::Linux: break; @@ -597,6 +593,7 @@ static void initialize(TargetLibraryInfoImpl &TLI, const Triple &T, case Triple::IOS: case Triple::TvOS: case Triple::WatchOS: + case Triple::XROS: case Triple::FreeBSD: case Triple::Linux: break; diff --git a/llvm/lib/Analysis/TargetTransformInfo.cpp b/llvm/lib/Analysis/TargetTransformInfo.cpp index a5a18a538d7..8902dde37cb 100644 --- a/llvm/lib/Analysis/TargetTransformInfo.cpp +++ b/llvm/lib/Analysis/TargetTransformInfo.cpp @@ -604,6 +604,11 @@ bool TargetTransformInfo::enableSelectOptimize() const { return TTIImpl->enableSelectOptimize(); } +bool TargetTransformInfo::shouldTreatInstructionLikeSelect( + const Instruction *I) const { + return TTIImpl->shouldTreatInstructionLikeSelect(I); +} + bool TargetTransformInfo::enableInterleavedAccessVectorization() const { return TTIImpl->enableInterleavedAccessVectorization(); } diff --git a/llvm/lib/Analysis/ValueTracking.cpp b/llvm/lib/Analysis/ValueTracking.cpp index 940ae9eb7ee..5d6c3465a0c 100644 --- a/llvm/lib/Analysis/ValueTracking.cpp +++ b/llvm/lib/Analysis/ValueTracking.cpp @@ -4019,6 +4019,12 @@ llvm::fcmpToClassTest(FCmpInst::Predicate Pred, const Function &F, Value *LHS, if (Pred == FCmpInst::FCMP_UNO && !ConstRHS->isNaN()) return {LHS, fcNan}; + if (Pred == FCmpInst::FCMP_TRUE) + return {LHS, fcAllFlags}; + + if (Pred == FCmpInst::FCMP_FALSE) + return {LHS, fcNone}; + if (ConstRHS->isZero()) { // Compares with fcNone are only exactly equal to fcZero if input denormals // are not flushed. @@ -4059,7 +4065,7 @@ llvm::fcmpToClassTest(FCmpInst::Predicate Pred, const Function &F, Value *LHS, case FCmpInst::FCMP_ULE: // isnan(x) || x <= 0 return {LHS, fcNegative | fcPosZero | fcNan}; default: - break; + llvm_unreachable("all compare types are handled"); } return {nullptr, fcAllFlags}; @@ -4178,8 +4184,22 @@ llvm::fcmpToClassTest(FCmpInst::Predicate Pred, const Function &F, Value *LHS, Mask = fcNone; break; } + case FCmpInst::FCMP_OLE: + case FCmpInst::FCMP_UGT: { + if (ConstRHS->isNegative()) { + Mask = IsFabs ? fcNone : fcNegInf; + break; + } + + // fcmp ole x, +inf -> fcmp ord x, x + // fcmp ole fabs(x), +inf -> fcmp ord x, x + // fcmp ole x, -inf -> fcmp oeq x, -inf + // fcmp ole fabs(x), -inf -> false + Mask = ~fcNan; + break; + } default: - return {nullptr, fcAllFlags}; + llvm_unreachable("all compare types are handled"); } } else if (ConstRHS->isSmallestNormalized() && !ConstRHS->isNegative()) { // Match pattern that's used in __builtin_isnormal. diff --git a/llvm/lib/Analysis/VectorUtils.cpp b/llvm/lib/Analysis/VectorUtils.cpp index 5b57f0a25ce..73facc76a92 100644 --- a/llvm/lib/Analysis/VectorUtils.cpp +++ b/llvm/lib/Analysis/VectorUtils.cpp @@ -1458,95 +1458,4 @@ void InterleaveGroup::addMetadata(Instruction *NewInst) const { [](std::pair p) { return p.second; }); propagateMetadata(NewInst, VL); } -} - -void VFABI::getVectorVariantNames( - const CallInst &CI, SmallVectorImpl &VariantMappings) { - const StringRef S = CI.getFnAttr(VFABI::MappingsAttrName).getValueAsString(); - if (S.empty()) - return; - - SmallVector ListAttr; - S.split(ListAttr, ","); - - for (const auto &S : SetVector(ListAttr.begin(), ListAttr.end())) { - std::optional Info = - VFABI::tryDemangleForVFABI(S, CI.getFunctionType()); - if (Info && CI.getModule()->getFunction(Info->VectorName)) { - LLVM_DEBUG(dbgs() << "VFABI: Adding mapping '" << S << "' for " << CI - << "\n"); - VariantMappings.push_back(std::string(S)); - } else - LLVM_DEBUG(dbgs() << "VFABI: Invalid mapping '" << S << "'\n"); - } -} - -FunctionType *VFABI::createFunctionType(const VFInfo &Info, - const FunctionType *ScalarFTy) { - // Create vector parameter types - SmallVector VecTypes; - ElementCount VF = Info.Shape.VF; - int ScalarParamIndex = 0; - for (auto VFParam : Info.Shape.Parameters) { - if (VFParam.ParamKind == VFParamKind::GlobalPredicate) { - VectorType *MaskTy = - VectorType::get(Type::getInt1Ty(ScalarFTy->getContext()), VF); - VecTypes.push_back(MaskTy); - continue; - } - - Type *OperandTy = ScalarFTy->getParamType(ScalarParamIndex++); - if (VFParam.ParamKind == VFParamKind::Vector) - OperandTy = VectorType::get(OperandTy, VF); - VecTypes.push_back(OperandTy); - } - - auto *RetTy = ScalarFTy->getReturnType(); - if (!RetTy->isVoidTy()) - RetTy = VectorType::get(RetTy, VF); - return FunctionType::get(RetTy, VecTypes, false); -} - -bool VFShape::hasValidParameterList() const { - for (unsigned Pos = 0, NumParams = Parameters.size(); Pos < NumParams; - ++Pos) { - assert(Parameters[Pos].ParamPos == Pos && "Broken parameter list."); - - switch (Parameters[Pos].ParamKind) { - default: // Nothing to check. - break; - case VFParamKind::OMP_Linear: - case VFParamKind::OMP_LinearRef: - case VFParamKind::OMP_LinearVal: - case VFParamKind::OMP_LinearUVal: - // Compile time linear steps must be non-zero. - if (Parameters[Pos].LinearStepOrPos == 0) - return false; - break; - case VFParamKind::OMP_LinearPos: - case VFParamKind::OMP_LinearRefPos: - case VFParamKind::OMP_LinearValPos: - case VFParamKind::OMP_LinearUValPos: - // The runtime linear step must be referring to some other - // parameters in the signature. - if (Parameters[Pos].LinearStepOrPos >= int(NumParams)) - return false; - // The linear step parameter must be marked as uniform. - if (Parameters[Parameters[Pos].LinearStepOrPos].ParamKind != - VFParamKind::OMP_Uniform) - return false; - // The linear step parameter can't point at itself. - if (Parameters[Pos].LinearStepOrPos == int(Pos)) - return false; - break; - case VFParamKind::GlobalPredicate: - // The global predicate must be the unique. Can be placed anywhere in the - // signature. - for (unsigned NextPos = Pos + 1; NextPos < NumParams; ++NextPos) - if (Parameters[NextPos].ParamKind == VFParamKind::GlobalPredicate) - return false; - break; - } - } - return true; -} +} // namespace llvm diff --git a/llvm/lib/AsmParser/LLParser.cpp b/llvm/lib/AsmParser/LLParser.cpp index fb9e1ba875e..d6c5993797d 100644 --- a/llvm/lib/AsmParser/LLParser.cpp +++ b/llvm/lib/AsmParser/LLParser.cpp @@ -13,8 +13,8 @@ #include "llvm/AsmParser/LLParser.h" #include "llvm/ADT/APSInt.h" #include "llvm/ADT/DenseMap.h" -#include "llvm/ADT/ScopeExit.h" #include "llvm/ADT/STLExtras.h" +#include "llvm/ADT/ScopeExit.h" #include "llvm/ADT/SmallPtrSet.h" #include "llvm/AsmParser/LLToken.h" #include "llvm/AsmParser/SlotMapping.h" @@ -32,7 +32,9 @@ #include "llvm/IR/GlobalIFunc.h" #include "llvm/IR/GlobalObject.h" #include "llvm/IR/InlineAsm.h" +#include "llvm/IR/InstIterator.h" #include "llvm/IR/Instructions.h" +#include "llvm/IR/IntrinsicInst.h" #include "llvm/IR/Intrinsics.h" #include "llvm/IR/LLVMContext.h" #include "llvm/IR/Metadata.h" @@ -54,6 +56,12 @@ using namespace llvm; +static cl::opt AllowIncompleteIR( + "allow-incomplete-ir", cl::init(false), cl::Hidden, + cl::desc( + "Allow incomplete IR on a best effort basis (references to unknown " + "metadata will be dropped)")); + static std::string getTypeString(Type *T) { std::string Result; raw_string_ostream Tmp(Result); @@ -123,6 +131,55 @@ void LLParser::restoreParsingState(const SlotMapping *Slots) { std::make_pair(I.first, std::make_pair(I.second, LocTy()))); } +static void dropIntrinsicWithUnknownMetadataArgument(IntrinsicInst *II) { + // White-list intrinsics that are safe to drop. + if (!isa(II) && + II->getIntrinsicID() != Intrinsic::experimental_noalias_scope_decl) + return; + + SmallVector MVs; + for (Value *V : II->args()) + if (auto *MV = dyn_cast(V)) + if (auto *MD = dyn_cast(MV->getMetadata())) + if (MD->isTemporary()) + MVs.push_back(MV); + + if (!MVs.empty()) { + assert(II->use_empty() && "Cannot have uses"); + II->eraseFromParent(); + + // Also remove no longer used MetadataAsValue wrappers. + for (MetadataAsValue *MV : MVs) + if (MV->use_empty()) + delete MV; + } +} + +void LLParser::dropUnknownMetadataReferences() { + auto Pred = [](unsigned MDKind, MDNode *Node) { return Node->isTemporary(); }; + for (Function &F : *M) { + F.eraseMetadataIf(Pred); + for (Instruction &I : make_early_inc_range(instructions(F))) { + I.eraseMetadataIf(Pred); + + if (auto *II = dyn_cast(&I)) + dropIntrinsicWithUnknownMetadataArgument(II); + } + } + + for (GlobalVariable &GV : M->globals()) + GV.eraseMetadataIf(Pred); + + for (const auto &[ID, Info] : make_early_inc_range(ForwardRefMDNodes)) { + // Check whether there is only a single use left, which would be in our + // own NumberedMetadata. + if (Info.first->getNumTemporaryUses() == 1) { + NumberedMetadata.erase(ID); + ForwardRefMDNodes.erase(ID); + } + } +} + /// validateEndOfModule - Do final validity and basic correctness checks at the /// end of the module. bool LLParser::validateEndOfModule(bool UpgradeDebugInfo) { @@ -246,6 +303,34 @@ bool LLParser::validateEndOfModule(bool UpgradeDebugInfo) { "use of undefined comdat '$" + ForwardRefComdats.begin()->first + "'"); + // Automatically create declarations for intrinsics. Intrinsics can only be + // called directly, so the call function type directly determines the + // declaration function type. + for (const auto &[Name, Info] : make_early_inc_range(ForwardRefVals)) { + if (!StringRef(Name).starts_with("llvm.")) + continue; + + // Don't do anything if the intrinsic is called with different function + // types. This would result in a verifier error anyway. + auto GetCommonFunctionType = [](Value *V) -> FunctionType * { + FunctionType *FTy = nullptr; + for (User *U : V->users()) { + auto *CB = dyn_cast(U); + if (!CB || (FTy && FTy != CB->getFunctionType())) + return nullptr; + FTy = CB->getFunctionType(); + } + return FTy; + }; + if (FunctionType *FTy = GetCommonFunctionType(Info.first)) { + Function *Fn = + Function::Create(FTy, GlobalValue::ExternalLinkage, Name, M); + Info.first->replaceAllUsesWith(Fn); + Info.first->eraseFromParent(); + ForwardRefVals.erase(Name); + } + } + if (!ForwardRefVals.empty()) return error(ForwardRefVals.begin()->second.second, "use of undefined value '@" + ForwardRefVals.begin()->first + @@ -256,6 +341,9 @@ bool LLParser::validateEndOfModule(bool UpgradeDebugInfo) { "use of undefined value '@" + Twine(ForwardRefValIDs.begin()->first) + "'"); + if (AllowIncompleteIR && !ForwardRefMDNodes.empty()) + dropUnknownMetadataReferences(); + if (!ForwardRefMDNodes.empty()) return error(ForwardRefMDNodes.begin()->second.second, "use of undefined metadata '!" + @@ -269,10 +357,14 @@ bool LLParser::validateEndOfModule(bool UpgradeDebugInfo) { for (auto *Inst : InstsWithTBAATag) { MDNode *MD = Inst->getMetadata(LLVMContext::MD_tbaa); - assert(MD && "UpgradeInstWithTBAATag should have a TBAA tag"); - auto *UpgradedMD = UpgradeTBAANode(*MD); - if (MD != UpgradedMD) - Inst->setMetadata(LLVMContext::MD_tbaa, UpgradedMD); + // With incomplete IR, the tbaa metadata may have been dropped. + if (!AllowIncompleteIR) + assert(MD && "UpgradeInstWithTBAATag should have a TBAA tag"); + if (MD) { + auto *UpgradedMD = UpgradeTBAANode(*MD); + if (MD != UpgradedMD) + Inst->setMetadata(LLVMContext::MD_tbaa, UpgradedMD); + } } // Look for intrinsic functions and CallInst that need to be upgraded. We use @@ -572,7 +664,8 @@ bool LLParser::parseDeclare() { } Function *F; - if (parseFunctionHeader(F, false)) + SmallVector UnnamedArgNums; + if (parseFunctionHeader(F, false, UnnamedArgNums)) return true; for (auto &MD : MDs) F->addMetadata(MD.first, *MD.second); @@ -586,8 +679,10 @@ bool LLParser::parseDefine() { Lex.Lex(); Function *F; - return parseFunctionHeader(F, true) || parseOptionalFunctionMetadata(*F) || - parseFunctionBody(*F); + SmallVector UnnamedArgNums; + return parseFunctionHeader(F, true, UnnamedArgNums) || + parseOptionalFunctionMetadata(*F) || + parseFunctionBody(*F, UnnamedArgNums); } /// parseGlobalType @@ -2925,6 +3020,15 @@ bool LLParser::parseOptionalOperandBundles( return false; } +bool LLParser::checkValueID(LocTy Loc, StringRef Kind, StringRef Prefix, + unsigned NextID, unsigned ID) const { + if (ID < NextID) + return error(Loc, Kind + " expected to be numbered '" + Prefix + + Twine(NextID) + "' or greater"); + + return false; +} + /// parseArgumentList - parse the argument list for a function type or function /// prototype. /// ::= '(' ArgTypeListI ')' @@ -2935,48 +3039,15 @@ bool LLParser::parseOptionalOperandBundles( /// ::= ArgType (',' ArgType)* /// bool LLParser::parseArgumentList(SmallVectorImpl &ArgList, + SmallVectorImpl &UnnamedArgNums, bool &IsVarArg) { unsigned CurValID = 0; IsVarArg = false; assert(Lex.getKind() == lltok::lparen); Lex.Lex(); // eat the (. - if (Lex.getKind() == lltok::rparen) { - // empty - } else if (Lex.getKind() == lltok::dotdotdot) { - IsVarArg = true; - Lex.Lex(); - } else { - LocTy TypeLoc = Lex.getLoc(); - Type *ArgTy = nullptr; - AttrBuilder Attrs(M->getContext()); - std::string Name; - - if (parseType(ArgTy) || parseOptionalParamAttrs(Attrs)) - return true; - - if (ArgTy->isVoidTy()) - return error(TypeLoc, "argument can not have void type"); - - if (Lex.getKind() == lltok::LocalVar) { - Name = Lex.getStrVal(); - Lex.Lex(); - } else if (Lex.getKind() == lltok::LocalVarID) { - if (Lex.getUIntVal() != CurValID) - return error(TypeLoc, "argument expected to be numbered '%" + - Twine(CurValID) + "'"); - ++CurValID; - Lex.Lex(); - } - - if (!FunctionType::isValidArgumentType(ArgTy)) - return error(TypeLoc, "invalid type for function argument"); - - ArgList.emplace_back(TypeLoc, ArgTy, - AttributeSet::get(ArgTy->getContext(), Attrs), - std::move(Name)); - - while (EatIfPresent(lltok::comma)) { + if (Lex.getKind() != lltok::rparen) { + do { // Handle ... at end of arg list. if (EatIfPresent(lltok::dotdotdot)) { IsVarArg = true; @@ -2984,25 +3055,31 @@ bool LLParser::parseArgumentList(SmallVectorImpl &ArgList, } // Otherwise must be an argument type. - TypeLoc = Lex.getLoc(); + LocTy TypeLoc = Lex.getLoc(); + Type *ArgTy = nullptr; + AttrBuilder Attrs(M->getContext()); if (parseType(ArgTy) || parseOptionalParamAttrs(Attrs)) return true; if (ArgTy->isVoidTy()) return error(TypeLoc, "argument can not have void type"); + std::string Name; if (Lex.getKind() == lltok::LocalVar) { Name = Lex.getStrVal(); Lex.Lex(); } else { + unsigned ArgID; if (Lex.getKind() == lltok::LocalVarID) { - if (Lex.getUIntVal() != CurValID) - return error(TypeLoc, "argument expected to be numbered '%" + - Twine(CurValID) + "'"); + ArgID = Lex.getUIntVal(); + if (checkValueID(TypeLoc, "argument", "%", CurValID, ArgID)) + return true; Lex.Lex(); + } else { + ArgID = CurValID; } - ++CurValID; - Name = ""; + UnnamedArgNums.push_back(ArgID); + CurValID = ArgID + 1; } if (!ArgTy->isFirstClassType()) @@ -3011,7 +3088,7 @@ bool LLParser::parseArgumentList(SmallVectorImpl &ArgList, ArgList.emplace_back(TypeLoc, ArgTy, AttributeSet::get(ArgTy->getContext(), Attrs), std::move(Name)); - } + } while (EatIfPresent(lltok::comma)); } return parseToken(lltok::rparen, "expected ')' at end of argument list"); @@ -3027,7 +3104,8 @@ bool LLParser::parseFunctionType(Type *&Result) { SmallVector ArgList; bool IsVarArg; - if (parseArgumentList(ArgList, IsVarArg)) + SmallVector UnnamedArgNums; + if (parseArgumentList(ArgList, UnnamedArgNums, IsVarArg)) return true; // Reject names on the arguments lists. @@ -3263,13 +3341,18 @@ bool LLParser::parseTargetExtType(Type *&Result) { //===----------------------------------------------------------------------===// LLParser::PerFunctionState::PerFunctionState(LLParser &p, Function &f, - int functionNumber) + int functionNumber, + ArrayRef UnnamedArgNums) : P(p), F(f), FunctionNumber(functionNumber) { // Insert unnamed arguments into the NumberedVals list. - for (Argument &A : F.args()) - if (!A.hasName()) - NumberedVals.push_back(&A); + auto It = UnnamedArgNums.begin(); + for (Argument &A : F.args()) { + if (!A.hasName()) { + unsigned ArgNum = *It++; + NumberedVals.add(ArgNum, &A); + } + } } LLParser::PerFunctionState::~PerFunctionState() { @@ -3350,7 +3433,7 @@ Value *LLParser::PerFunctionState::getVal(const std::string &Name, Type *Ty, Value *LLParser::PerFunctionState::getVal(unsigned ID, Type *Ty, LocTy Loc) { // Look this name up in the normal function symbol table. - Value *Val = ID < NumberedVals.size() ? NumberedVals[ID] : nullptr; + Value *Val = NumberedVals.get(ID); // If this is a forward reference for the value, see if we already created a // forward ref record. @@ -3398,11 +3481,11 @@ bool LLParser::PerFunctionState::setInstName(int NameID, if (NameStr.empty()) { // If neither a name nor an ID was specified, just use the next ID. if (NameID == -1) - NameID = NumberedVals.size(); + NameID = NumberedVals.getNext(); - if (unsigned(NameID) != NumberedVals.size()) - return P.error(NameLoc, "instruction expected to be numbered '%" + - Twine(NumberedVals.size()) + "'"); + if (P.checkValueID(NameLoc, "instruction", "%", NumberedVals.getNext(), + NameID)) + return true; auto FI = ForwardRefValIDs.find(NameID); if (FI != ForwardRefValIDs.end()) { @@ -3417,7 +3500,7 @@ bool LLParser::PerFunctionState::setInstName(int NameID, ForwardRefValIDs.erase(FI); } - NumberedVals.push_back(Inst); + NumberedVals.add(NameID, Inst); return false; } @@ -3464,15 +3547,15 @@ BasicBlock *LLParser::PerFunctionState::defineBB(const std::string &Name, int NameID, LocTy Loc) { BasicBlock *BB; if (Name.empty()) { - if (NameID != -1 && unsigned(NameID) != NumberedVals.size()) { - P.error(Loc, "label expected to be numbered '" + - Twine(NumberedVals.size()) + "'"); - return nullptr; + if (NameID != -1) { + if (P.checkValueID(Loc, "label", "", NumberedVals.getNext(), NameID)) + return nullptr; + } else { + NameID = NumberedVals.getNext(); } - BB = getBB(NumberedVals.size(), Loc); + BB = getBB(NameID, Loc); if (!BB) { - P.error(Loc, "unable to create block numbered '" + - Twine(NumberedVals.size()) + "'"); + P.error(Loc, "unable to create block numbered '" + Twine(NameID) + "'"); return nullptr; } } else { @@ -3489,8 +3572,8 @@ BasicBlock *LLParser::PerFunctionState::defineBB(const std::string &Name, // Remove the block from forward ref sets. if (Name.empty()) { - ForwardRefValIDs.erase(NumberedVals.size()); - NumberedVals.push_back(BB); + ForwardRefValIDs.erase(NameID); + NumberedVals.add(NameID, BB); } else { // BB forward references are already in the function symbol table. ForwardRefVals.erase(Name); @@ -5934,7 +6017,8 @@ bool LLParser::parseTypeAndBasicBlock(BasicBlock *&BB, LocTy &Loc, /// OptionalCallingConv OptRetAttrs OptUnnamedAddr Type GlobalName /// '(' ArgList ')' OptAddrSpace OptFuncAttrs OptSection OptionalAlign /// OptGC OptionalPrefix OptionalPrologue OptPersonalityFn -bool LLParser::parseFunctionHeader(Function *&Fn, bool IsDefine) { +bool LLParser::parseFunctionHeader(Function *&Fn, bool IsDefine, + SmallVectorImpl &UnnamedArgNums) { // parse the linkage. LocTy LinkageLoc = Lex.getLoc(); unsigned Linkage; @@ -6022,7 +6106,7 @@ bool LLParser::parseFunctionHeader(Function *&Fn, bool IsDefine) { Constant *PersonalityFn = nullptr; Comdat *C; - if (parseArgumentList(ArgList, IsVarArg) || + if (parseArgumentList(ArgList, UnnamedArgNums, IsVarArg) || parseOptionalUnnamedAddr(UnnamedAddr) || parseOptionalProgramAddrSpace(AddrSpace) || parseFnAttributeValuePairs(FuncAttrs, FwdRefAttrGrps, false, @@ -6217,7 +6301,8 @@ bool LLParser::PerFunctionState::resolveForwardRefBlockAddresses() { /// parseFunctionBody /// ::= '{' BasicBlock+ UseListOrderDirective* '}' -bool LLParser::parseFunctionBody(Function &Fn) { +bool LLParser::parseFunctionBody(Function &Fn, + ArrayRef UnnamedArgNums) { if (Lex.getKind() != lltok::lbrace) return tokError("expected '{' in function body"); Lex.Lex(); // eat the {. @@ -6225,7 +6310,7 @@ bool LLParser::parseFunctionBody(Function &Fn) { int FunctionNumber = -1; if (!Fn.hasName()) FunctionNumber = NumberedVals.size()-1; - PerFunctionState PFS(*this, Fn, FunctionNumber); + PerFunctionState PFS(*this, Fn, FunctionNumber, UnnamedArgNums); // Resolve block addresses and allow basic blocks to be forward-declared // within this function. diff --git a/llvm/lib/BinaryFormat/Magic.cpp b/llvm/lib/BinaryFormat/Magic.cpp index 45a0b7e1145..bd378337ed3 100644 --- a/llvm/lib/BinaryFormat/Magic.cpp +++ b/llvm/lib/BinaryFormat/Magic.cpp @@ -98,6 +98,8 @@ file_magic llvm::identify_magic(StringRef Magic) { case 'C': if (startswith(Magic, "CCOB")) return file_magic::offload_bundle_compressed; + if (startswith(Magic, "CPCH")) + return file_magic::clang_ast; break; case '!': if (startswith(Magic, "!\n") || startswith(Magic, "!\n")) diff --git a/llvm/lib/Bitcode/Reader/MetadataLoader.cpp b/llvm/lib/Bitcode/Reader/MetadataLoader.cpp index 910e97489db..770eb83af17 100644 --- a/llvm/lib/Bitcode/Reader/MetadataLoader.cpp +++ b/llvm/lib/Bitcode/Reader/MetadataLoader.cpp @@ -1615,27 +1615,32 @@ Error MetadataLoader::MetadataLoaderImpl::parseOneMetadata( Metadata *Annotations = nullptr; auto *Identifier = getMDString(Record[15]); // If this module is being parsed so that it can be ThinLTO imported - // into another module, composite types only need to be imported - // as type declarations (unless full type definitions requested). - // Create type declarations up front to save memory. Also, buildODRType - // handles the case where this is type ODRed with a definition needed - // by the importing module, in which case the existing definition is - // used. - if (IsImporting && !ImportFullTypeDefinitions && Identifier && + // into another module, composite types only need to be imported as + // type declarations (unless full type definitions are requested). + // Create type declarations up front to save memory. This is only + // done for types which have an Identifier, and are therefore + // subject to the ODR. + // + // buildODRType handles the case where this is type ODRed with a + // definition needed by the importing module, in which case the + // existing definition is used. + // + // We always import full definitions for anonymous composite types, + // as without a name, debuggers cannot easily resolve a declaration + // to its definition. + if (IsImporting && !ImportFullTypeDefinitions && Identifier && Name && (Tag == dwarf::DW_TAG_enumeration_type || Tag == dwarf::DW_TAG_class_type || Tag == dwarf::DW_TAG_structure_type || Tag == dwarf::DW_TAG_union_type)) { Flags = Flags | DINode::FlagFwdDecl; - if (Name) { - // This is a hack around preserving template parameters for simplified - // template names - it should probably be replaced with a - // DICompositeType flag specifying whether template parameters are - // required on declarations of this type. - StringRef NameStr = Name->getString(); - if (!NameStr.contains('<') || NameStr.starts_with("_STN|")) - TemplateParams = getMDOrNull(Record[14]); - } + // This is a hack around preserving template parameters for simplified + // template names - it should probably be replaced with a + // DICompositeType flag specifying whether template parameters are + // required on declarations of this type. + StringRef NameStr = Name->getString(); + if (!NameStr.contains('<') || NameStr.starts_with("_STN|")) + TemplateParams = getMDOrNull(Record[14]); } else { BaseType = getDITypeRefOrNull(Record[6]); OffsetInBits = Record[9]; diff --git a/llvm/lib/Bitcode/Writer/BitcodeWriterPass.cpp b/llvm/lib/Bitcode/Writer/BitcodeWriterPass.cpp index 28941d6c41c..93fb2a821de 100644 --- a/llvm/lib/Bitcode/Writer/BitcodeWriterPass.cpp +++ b/llvm/lib/Bitcode/Writer/BitcodeWriterPass.cpp @@ -40,8 +40,6 @@ namespace { class WriteBitcodePass : public ModulePass { raw_ostream &OS; // raw_ostream to print on bool ShouldPreserveUseListOrder; - bool EmitSummaryIndex; - bool EmitModuleHash; public: static char ID; // Pass identification, replacement for typeid @@ -49,29 +47,23 @@ namespace { initializeWriteBitcodePassPass(*PassRegistry::getPassRegistry()); } - explicit WriteBitcodePass(raw_ostream &o, bool ShouldPreserveUseListOrder, - bool EmitSummaryIndex, bool EmitModuleHash) + explicit WriteBitcodePass(raw_ostream &o, bool ShouldPreserveUseListOrder) : ModulePass(ID), OS(o), - ShouldPreserveUseListOrder(ShouldPreserveUseListOrder), - EmitSummaryIndex(EmitSummaryIndex), EmitModuleHash(EmitModuleHash) { + ShouldPreserveUseListOrder(ShouldPreserveUseListOrder) { initializeWriteBitcodePassPass(*PassRegistry::getPassRegistry()); } StringRef getPassName() const override { return "Bitcode Writer"; } bool runOnModule(Module &M) override { - const ModuleSummaryIndex *Index = - EmitSummaryIndex - ? &(getAnalysis().getIndex()) - : nullptr; // RemoveDIs: there's no bitcode representation of the DPValue debug-info, // convert to dbg.values before writing out. bool IsNewDbgInfoFormat = M.IsNewDbgInfoFormat; if (IsNewDbgInfoFormat) M.convertFromNewDbgValues(); - WriteBitcodeToFile(M, OS, ShouldPreserveUseListOrder, Index, - EmitModuleHash); + WriteBitcodeToFile(M, OS, ShouldPreserveUseListOrder, /*Index=*/nullptr, + /*EmitModuleHash=*/false); if (IsNewDbgInfoFormat) M.convertToNewDbgValues(); @@ -79,8 +71,6 @@ namespace { } void getAnalysisUsage(AnalysisUsage &AU) const override { AU.setPreservesAll(); - if (EmitSummaryIndex) - AU.addRequired(); } }; } @@ -93,10 +83,8 @@ INITIALIZE_PASS_END(WriteBitcodePass, "write-bitcode", "Write Bitcode", false, true) ModulePass *llvm::createBitcodeWriterPass(raw_ostream &Str, - bool ShouldPreserveUseListOrder, - bool EmitSummaryIndex, bool EmitModuleHash) { - return new WriteBitcodePass(Str, ShouldPreserveUseListOrder, - EmitSummaryIndex, EmitModuleHash); + bool ShouldPreserveUseListOrder) { + return new WriteBitcodePass(Str, ShouldPreserveUseListOrder); } bool llvm::isBitcodeWriterPass(Pass *P) { diff --git a/llvm/lib/Bitcode/Writer/ValueEnumerator.cpp b/llvm/lib/Bitcode/Writer/ValueEnumerator.cpp index 998f629aaa4..fccb2a606f7 100644 --- a/llvm/lib/Bitcode/Writer/ValueEnumerator.cpp +++ b/llvm/lib/Bitcode/Writer/ValueEnumerator.cpp @@ -1108,8 +1108,8 @@ void ValueEnumerator::purgeFunction() { /// Remove purged values from the ValueMap. for (unsigned i = NumModuleValues, e = Values.size(); i != e; ++i) ValueMap.erase(Values[i].first); - for (unsigned i = NumModuleMDs, e = MDs.size(); i != e; ++i) - MetadataMap.erase(MDs[i]); + for (const Metadata *MD : llvm::drop_begin(MDs, NumModuleMDs)) + MetadataMap.erase(MD); for (const BasicBlock *BB : BasicBlocks) ValueMap.erase(BB); diff --git a/llvm/lib/CodeGen/AsmPrinter/AccelTable.cpp b/llvm/lib/CodeGen/AsmPrinter/AccelTable.cpp index b72c17aa6f5..1024aabf2ab 100644 --- a/llvm/lib/CodeGen/AsmPrinter/AccelTable.cpp +++ b/llvm/lib/CodeGen/AsmPrinter/AccelTable.cpp @@ -13,6 +13,7 @@ #include "llvm/CodeGen/AccelTable.h" #include "DwarfCompileUnit.h" #include "DwarfUnit.h" +#include "llvm/ADT/DenseSet.h" #include "llvm/ADT/STLExtras.h" #include "llvm/ADT/Twine.h" #include "llvm/BinaryFormat/Dwarf.h" @@ -207,7 +208,7 @@ class Dwarf5AccelTableWriter : public AccelTableWriter { }; Header Header; - DenseMap> + DenseMap> Abbreviations; ArrayRef> CompUnits; ArrayRef> TypeUnits; @@ -220,6 +221,8 @@ class Dwarf5AccelTableWriter : public AccelTableWriter { MCSymbol *EntryPool = Asm->createTempSymbol("names_entries"); // Indicates if this module is built with Split Dwarf enabled. bool IsSplitDwarf = false; + /// Stores the DIE offsets which are indexed by this table. + DenseSet IndexedOffsets; void populateAbbrevsMap(); @@ -228,8 +231,11 @@ class Dwarf5AccelTableWriter : public AccelTableWriter { void emitBuckets() const; void emitStringOffsets() const; void emitAbbrevs() const; - void emitEntry(const DWARF5AccelTableData &Entry) const; - void emitData() const; + void emitEntry( + const DWARF5AccelTableData &Entry, + const DenseMap &DIEOffsetToAccelEntryLabel, + DenseSet &EmittedAccelEntrySymbols) const; + void emitData(); public: Dwarf5AccelTableWriter( @@ -395,23 +401,72 @@ void Dwarf5AccelTableWriter::Header::emit(Dwarf5AccelTableWriter &Ctx) { Asm->OutStreamer->emitBytes({AugmentationString, AugmentationStringSize}); } -static uint32_t constexpr LowerBitSize = dwarf::DW_IDX_type_hash; +std::optional +DWARF5AccelTableData::getDefiningParentDieOffset(const DIE &Die) { + if (auto *Parent = Die.getParent(); + Parent && !Parent->findAttribute(dwarf::Attribute::DW_AT_declaration)) + return Parent->getOffset(); + return {}; +} + +enum IdxParentEncoding : uint8_t { + NoIndexedParent = 0, /// Parent information present but parent isn't indexed. + Ref4 = 1, /// Parent information present and parent is indexed. + NoParent = 2, /// Parent information missing. +}; + +static uint32_t constexpr NumBitsIdxParent = 2; + +uint8_t encodeIdxParent(const std::optional MaybeParentForm) { + if (!MaybeParentForm) + return NoParent; + switch (*MaybeParentForm) { + case dwarf::Form::DW_FORM_flag_present: + return NoIndexedParent; + case dwarf::Form::DW_FORM_ref4: + return Ref4; + default: + // This is not crashing on bad input: we should only reach this if the + // internal compiler logic is faulty; see getFormForIdxParent. + llvm_unreachable("Bad form for IDX_parent"); + } +} + +static uint32_t constexpr ParentBitOffset = dwarf::DW_IDX_type_hash; +static uint32_t constexpr TagBitOffset = ParentBitOffset + NumBitsIdxParent; static uint32_t getTagFromAbbreviationTag(const uint32_t AbbrvTag) { - return AbbrvTag >> LowerBitSize; + return AbbrvTag >> TagBitOffset; } /// Constructs a unique AbbrevTag that captures what a DIE accesses. /// Using this tag we can emit a unique abbreviation for each DIE. static uint32_t constructAbbreviationTag( const unsigned Tag, - const std::optional &EntryRet) { + const std::optional &EntryRet, + std::optional MaybeParentForm) { uint32_t AbbrvTag = 0; if (EntryRet) AbbrvTag |= 1 << EntryRet->Encoding.Index; AbbrvTag |= 1 << dwarf::DW_IDX_die_offset; - AbbrvTag |= Tag << LowerBitSize; + AbbrvTag |= 1 << dwarf::DW_IDX_parent; + AbbrvTag |= encodeIdxParent(MaybeParentForm) << ParentBitOffset; + AbbrvTag |= Tag << TagBitOffset; return AbbrvTag; } + +static std::optional +getFormForIdxParent(const DenseSet &IndexedOffsets, + std::optional ParentOffset) { + // No parent information + if (!ParentOffset) + return std::nullopt; + // Parent is indexed by this table. + if (IndexedOffsets.contains(*ParentOffset)) + return dwarf::Form::DW_FORM_ref4; + // Parent is not indexed by this table. + return dwarf::Form::DW_FORM_flag_present; +} + void Dwarf5AccelTableWriter::populateAbbrevsMap() { for (auto &Bucket : Contents.getBuckets()) { for (auto *Hash : Bucket) { @@ -419,12 +474,17 @@ void Dwarf5AccelTableWriter::populateAbbrevsMap() { std::optional EntryRet = getIndexForEntry(*Value); unsigned Tag = Value->getDieTag(); - uint32_t AbbrvTag = constructAbbreviationTag(Tag, EntryRet); + std::optional MaybeParentForm = getFormForIdxParent( + IndexedOffsets, Value->getParentDieOffsetAndUnitID()); + uint32_t AbbrvTag = + constructAbbreviationTag(Tag, EntryRet, MaybeParentForm); if (Abbreviations.count(AbbrvTag) == 0) { - SmallVector UA; + SmallVector UA; if (EntryRet) UA.push_back(EntryRet->Encoding); UA.push_back({dwarf::DW_IDX_die_offset, dwarf::DW_FORM_ref4}); + if (MaybeParentForm) + UA.push_back({dwarf::DW_IDX_parent, *MaybeParentForm}); Abbreviations.try_emplace(AbbrvTag, UA); } } @@ -496,15 +556,34 @@ void Dwarf5AccelTableWriter::emitAbbrevs() const { } void Dwarf5AccelTableWriter::emitEntry( - const DWARF5AccelTableData &Entry) const { + const DWARF5AccelTableData &Entry, + const DenseMap &DIEOffsetToAccelEntryLabel, + DenseSet &EmittedAccelEntrySymbols) const { std::optional EntryRet = getIndexForEntry(Entry); - uint32_t AbbrvTag = constructAbbreviationTag(Entry.getDieTag(), EntryRet); + std::optional MaybeParentOffset = + Entry.getParentDieOffsetAndUnitID(); + std::optional MaybeParentForm = + getFormForIdxParent(IndexedOffsets, MaybeParentOffset); + uint32_t AbbrvTag = + constructAbbreviationTag(Entry.getDieTag(), EntryRet, MaybeParentForm); auto AbbrevIt = Abbreviations.find(AbbrvTag); assert(AbbrevIt != Abbreviations.end() && "Why wasn't this abbrev generated?"); assert(getTagFromAbbreviationTag(AbbrevIt->first) == Entry.getDieTag() && "Invalid Tag"); + + auto EntrySymbolIt = + DIEOffsetToAccelEntryLabel.find(Entry.getDieOffsetAndUnitID()); + assert(EntrySymbolIt != DIEOffsetToAccelEntryLabel.end()); + MCSymbol *EntrySymbol = EntrySymbolIt->getSecond(); + + // Emit the label for this Entry, so that IDX_parents may refer to it. + // Note: a DIE may have multiple accelerator Entries; this check avoids + // creating/emitting multiple labels for the same DIE. + if (EmittedAccelEntrySymbols.insert(EntrySymbol).second) + Asm->OutStreamer->emitLabel(EntrySymbol); + Asm->emitULEB128(AbbrevIt->first, "Abbreviation code"); for (const auto &AttrEnc : AbbrevIt->second) { @@ -520,20 +599,34 @@ void Dwarf5AccelTableWriter::emitEntry( assert(AttrEnc.Form == dwarf::DW_FORM_ref4); Asm->emitInt32(Entry.getDieOffset()); break; + case dwarf::DW_IDX_parent: { + if (AttrEnc.Form == dwarf::Form::DW_FORM_flag_present) + break; + auto ParentSymbolIt = DIEOffsetToAccelEntryLabel.find(*MaybeParentOffset); + assert(ParentSymbolIt != DIEOffsetToAccelEntryLabel.end()); + Asm->emitLabelDifference(ParentSymbolIt->getSecond(), EntryPool, 4); + break; + } default: llvm_unreachable("Unexpected index attribute!"); } } } -void Dwarf5AccelTableWriter::emitData() const { +void Dwarf5AccelTableWriter::emitData() { + DenseMap DIEOffsetToAccelEntryLabel; + + for (OffsetAndUnitID Offset : IndexedOffsets) + DIEOffsetToAccelEntryLabel.insert({Offset, Asm->createTempSymbol("")}); + Asm->OutStreamer->emitLabel(EntryPool); + DenseSet EmittedAccelEntrySymbols; for (auto &Bucket : Contents.getBuckets()) { for (auto *Hash : Bucket) { // Remember to emit the label for our offset. Asm->OutStreamer->emitLabel(Hash->Sym); - for (const auto *Value : Hash->Values) - emitEntry(*static_cast(Value)); + for (const auto *Value : Hash->getValues()) + emitEntry(*Value, DIEOffsetToAccelEntryLabel, EmittedAccelEntrySymbols); Asm->OutStreamer->AddComment("End of list: " + Hash->Name.getString()); Asm->emitInt8(0); } @@ -555,6 +648,12 @@ Dwarf5AccelTableWriter::Dwarf5AccelTableWriter( CompUnits(CompUnits), TypeUnits(TypeUnits), getIndexForEntry(std::move(getIndexForEntry)), IsSplitDwarf(IsSplitDwarf) { + + for (auto &Bucket : Contents.getBuckets()) + for (auto *Hash : Bucket) + for (auto *Value : Hash->getValues()) + IndexedOffsets.insert(Value->getDieOffsetAndUnitID()); + populateAbbrevsMap(); } diff --git a/llvm/lib/CodeGen/AsmPrinter/AsmPrinter.cpp b/llvm/lib/CodeGen/AsmPrinter/AsmPrinter.cpp index 7df1c82bf35..0d573562de9 100644 --- a/llvm/lib/CodeGen/AsmPrinter/AsmPrinter.cpp +++ b/llvm/lib/CodeGen/AsmPrinter/AsmPrinter.cpp @@ -134,13 +134,6 @@ using namespace llvm; #define DEBUG_TYPE "asm-printer" -static cl::opt BasicBlockProfileDump( - "mbb-profile-dump", cl::Hidden, - cl::desc("Basic block profile dump for external cost modelling. If " - "matching up BBs with afterwards, the compilation must be " - "performed with -basic-block-sections=labels. Enabling this " - "flag during in-process ThinLTO is not supported.")); - // This is a replication of fields of object::PGOAnalysisMap::Features. It // should match the order of the fields so that // `object::PGOAnalysisMap::Features::decode(PgoAnalysisMapFeatures.getBits())` @@ -646,16 +639,6 @@ bool AsmPrinter::doInitialization(Module &M) { HI.Handler->beginModule(&M); } - if (!BasicBlockProfileDump.empty()) { - std::error_code PossibleFileError; - MBBProfileDumpFileOutput = std::make_unique( - BasicBlockProfileDump, PossibleFileError); - if (PossibleFileError) { - M.getContext().emitError("Failed to open file for MBB Profile Dump: " + - PossibleFileError.message() + "\n"); - } - } - return false; } @@ -2026,40 +2009,6 @@ void AsmPrinter::emitFunctionBody() { OutStreamer->getCommentOS() << "-- End function\n"; OutStreamer->addBlankLine(); - - // Output MBB ids, function names, and frequencies if the flag to dump - // MBB profile information has been set - if (MBBProfileDumpFileOutput && !MF->empty() && - MF->getFunction().getEntryCount()) { - if (!MF->hasBBLabels()) { - MF->getContext().reportError( - SMLoc(), - "Unable to find BB labels for MBB profile dump. -mbb-profile-dump " - "must be called with -basic-block-sections=labels"); - } else { - MachineBlockFrequencyInfo &MBFI = - getAnalysis().getBFI(); - // The entry count and the entry basic block frequency aren't the same. We - // want to capture "absolute" frequencies, i.e. the frequency with which a - // MBB is executed when the program is executed. From there, we can derive - // Function-relative frequencies (divide by the value for the first MBB). - // We also have the information about frequency with which functions - // were called. This helps, for example, in a type of integration tests - // where we want to cross-validate the compiler's profile with a real - // profile. - // Using double precision because uint64 values used to encode mbb - // "frequencies" may be quite large. - const double EntryCount = - static_cast(MF->getFunction().getEntryCount()->getCount()); - for (const auto &MBB : *MF) { - const double MBBRelFreq = MBFI.getBlockFreqRelativeToEntryBlock(&MBB); - const double AbsMBBFreq = MBBRelFreq * EntryCount; - *MBBProfileDumpFileOutput.get() - << MF->getName() << "," << MBB.getBBID()->BaseID << "," - << AbsMBBFreq << "\n"; - } - } - } } /// Compute the number of Global Variables that uses a Constant. @@ -2892,6 +2841,39 @@ bool AsmPrinter::emitSpecialLLVMGlobal(const GlobalVariable *GV) { GV->hasAvailableExternallyLinkage()) return true; + if (GV->getName() == "llvm.arm64ec.symbolmap") { + // For ARM64EC, print the table that maps between symbols and the + // corresponding thunks to translate between x64 and AArch64 code. + // This table is generated by AArch64Arm64ECCallLowering. + OutStreamer->switchSection(OutContext.getCOFFSection( + ".hybmp$x", COFF::IMAGE_SCN_LNK_INFO, SectionKind::getMetadata())); + auto *Arr = cast(GV->getInitializer()); + for (auto &U : Arr->operands()) { + auto *C = cast(U); + auto *Src = cast(C->getOperand(0)->stripPointerCasts()); + auto *Dst = cast(C->getOperand(1)->stripPointerCasts()); + int Kind = cast(C->getOperand(2))->getZExtValue(); + + if (Src->hasDLLImportStorageClass()) { + // For now, we assume dllimport functions aren't directly called. + // (We might change this later to match MSVC.) + OutStreamer->emitCOFFSymbolIndex( + OutContext.getOrCreateSymbol("__imp_" + Src->getName())); + OutStreamer->emitCOFFSymbolIndex(getSymbol(Dst)); + OutStreamer->emitInt32(Kind); + } else { + // FIXME: For non-dllimport functions, MSVC emits the same entry + // twice, for reasons I don't understand. I have to assume the linker + // ignores the redundant entry; there aren't any reasonable semantics + // to attach to it. + OutStreamer->emitCOFFSymbolIndex(getSymbol(Src)); + OutStreamer->emitCOFFSymbolIndex(getSymbol(Dst)); + OutStreamer->emitInt32(Kind); + } + } + return true; + } + if (!GV->hasAppendingLinkage()) return false; assert(GV->hasInitializer() && "Not a special LLVM global!"); diff --git a/llvm/lib/CodeGen/AsmPrinter/DwarfDebug.cpp b/llvm/lib/CodeGen/AsmPrinter/DwarfDebug.cpp index 41afbea4561..6b5ad62e083 100644 --- a/llvm/lib/CodeGen/AsmPrinter/DwarfDebug.cpp +++ b/llvm/lib/CodeGen/AsmPrinter/DwarfDebug.cpp @@ -3448,7 +3448,6 @@ uint64_t DwarfDebug::makeTypeSignature(StringRef Identifier) { void DwarfDebug::addDwarfTypeUnitType(DwarfCompileUnit &CU, StringRef Identifier, DIE &RefDie, const DICompositeType *CTy) { - setCurrentDWARF5AccelTable(DWARF5AccelTableKind::TU); // Fast path if we're building some type units and one has already used the // address pool we know we're going to throw away all this work anyway, so // don't bother building dependent types. @@ -3461,6 +3460,7 @@ void DwarfDebug::addDwarfTypeUnitType(DwarfCompileUnit &CU, return; } + setCurrentDWARF5AccelTable(DWARF5AccelTableKind::TU); bool TopLevelType = TypeUnitsUnderConstruction.empty(); AddrPool.resetUsedFlag(); @@ -3549,9 +3549,9 @@ void DwarfDebug::addDwarfTypeUnitType(DwarfCompileUnit &CU, AccelTypeUnitsDebugNames.convertDieToOffset(); AccelDebugNames.addTypeEntries(AccelTypeUnitsDebugNames); AccelTypeUnitsDebugNames.clear(); + setCurrentDWARF5AccelTable(DWARF5AccelTableKind::CU); } CU.addDIETypeSignature(RefDie, Signature); - setCurrentDWARF5AccelTable(DWARF5AccelTableKind::CU); } // Add the Name along with its companion DIE to the appropriate accelerator @@ -3580,6 +3580,14 @@ void DwarfDebug::addAccelNameImpl( break; case AccelTableKind::Dwarf: { DWARF5AccelTable &Current = getCurrentDWARF5AccelTable(); + assert(((&Current == &AccelTypeUnitsDebugNames) || + ((&Current == &AccelDebugNames) && + (Unit.getUnitDie().getTag() != dwarf::DW_TAG_type_unit))) && + "Kind is CU but TU is being processed."); + assert(((&Current == &AccelDebugNames) || + ((&Current == &AccelTypeUnitsDebugNames) && + (Unit.getUnitDie().getTag() == dwarf::DW_TAG_type_unit))) && + "Kind is TU but CU is being processed."); // The type unit can be discarded, so need to add references to final // acceleration table once we know it's complete and we emit it. Current.addName(Ref, Die, Unit.getUniqueID()); diff --git a/llvm/lib/CodeGen/AssignmentTrackingAnalysis.cpp b/llvm/lib/CodeGen/AssignmentTrackingAnalysis.cpp index eb372655e5f..f8ce8f98864 100644 --- a/llvm/lib/CodeGen/AssignmentTrackingAnalysis.cpp +++ b/llvm/lib/CodeGen/AssignmentTrackingAnalysis.cpp @@ -20,6 +20,7 @@ #include "llvm/IR/BasicBlock.h" #include "llvm/IR/DataLayout.h" #include "llvm/IR/DebugInfo.h" +#include "llvm/IR/DebugProgramInstruction.h" #include "llvm/IR/Function.h" #include "llvm/IR/Instruction.h" #include "llvm/IR/IntrinsicInst.h" @@ -81,6 +82,19 @@ template <> struct llvm::DenseMapInfo { } }; +using VarLocInsertPt = PointerUnion; + +namespace std { +template <> struct hash { + using argument_type = VarLocInsertPt; + using result_type = std::size_t; + + result_type operator()(const argument_type &Arg) const { + return std::hash()(Arg.getOpaqueValue()); + } +}; +} // namespace std + /// Helper class to build FunctionVarLocs, since that class isn't easy to /// modify. TODO: There's not a great deal of value in the split, it could be /// worth merging the two classes. @@ -89,8 +103,7 @@ class FunctionVarLocsBuilder { UniqueVector Variables; // Use an unordered_map so we don't invalidate iterators after // insert/modifications. - std::unordered_map> - VarLocsBeforeInst; + std::unordered_map> VarLocsBeforeInst; SmallVector SingleLocVars; @@ -109,7 +122,7 @@ public: /// Return ptr to wedge of defs or nullptr if no defs come just before /p /// Before. - const SmallVectorImpl *getWedge(const Instruction *Before) const { + const SmallVectorImpl *getWedge(VarLocInsertPt Before) const { auto R = VarLocsBeforeInst.find(Before); if (R == VarLocsBeforeInst.end()) return nullptr; @@ -117,7 +130,7 @@ public: } /// Replace the defs that come just before /p Before with /p Wedge. - void setWedge(const Instruction *Before, SmallVector &&Wedge) { + void setWedge(VarLocInsertPt Before, SmallVector &&Wedge) { VarLocsBeforeInst[Before] = std::move(Wedge); } @@ -133,7 +146,7 @@ public: } /// Add a def to the wedge of defs just before /p Before. - void addVarLoc(Instruction *Before, DebugVariable Var, DIExpression *Expr, + void addVarLoc(VarLocInsertPt Before, DebugVariable Var, DIExpression *Expr, DebugLoc DL, RawLocationWrapper R) { VarLocInfo VarLoc; VarLoc.VariableID = insertVariable(Var); @@ -201,15 +214,31 @@ void FunctionVarLocs::init(FunctionVarLocsBuilder &Builder) { SingleVarLocEnd = VarLocRecords.size(); // Insert a contiguous block of VarLocInfos for each instruction, mapping it - // to the start and end position in the vector with VarLocsBeforeInst. + // to the start and end position in the vector with VarLocsBeforeInst. This + // block includes VarLocs for any DPValues attached to that instruction. for (auto &P : Builder.VarLocsBeforeInst) { + // Process VarLocs attached to a DPValue alongside their marker Instruction. + if (isa(P.first)) + continue; + const Instruction *I = cast(P.first); unsigned BlockStart = VarLocRecords.size(); + // Any VarLocInfos attached to a DPValue should now be remapped to their + // marker Instruction, in order of DPValue appearance and prior to any + // VarLocInfos attached directly to that instruction. + for (const DPValue &DPV : I->getDbgValueRange()) { + // Even though DPV defines a variable location, VarLocsBeforeInst can + // still be empty if that VarLoc was redundant. + if (!Builder.VarLocsBeforeInst.count(&DPV)) + continue; + for (const VarLocInfo &VarLoc : Builder.VarLocsBeforeInst[&DPV]) + VarLocRecords.emplace_back(VarLoc); + } for (const VarLocInfo &VarLoc : P.second) VarLocRecords.emplace_back(VarLoc); unsigned BlockEnd = VarLocRecords.size(); // Record the start and end indices. if (BlockEnd != BlockStart) - VarLocsBeforeInst[P.first] = {BlockStart, BlockEnd}; + VarLocsBeforeInst[I] = {BlockStart, BlockEnd}; } // Copy the Variables vector from the builder's UniqueVector. @@ -370,7 +399,7 @@ class MemLocFragmentFill { unsigned SizeInBits; DebugLoc DL; }; - using InsertMap = MapVector>; + using InsertMap = MapVector>; /// BBInsertBeforeMap holds a description for the set of location defs to be /// inserted after the analysis is complete. It is updated during the dataflow @@ -590,7 +619,7 @@ class MemLocFragmentFill { return /*Changed=*/false; } - void insertMemLoc(BasicBlock &BB, Instruction &Before, unsigned Var, + void insertMemLoc(BasicBlock &BB, VarLocInsertPt Before, unsigned Var, unsigned StartBit, unsigned EndBit, unsigned Base, DebugLoc DL) { assert(StartBit < EndBit && "Cannot create fragment of size <= 0"); @@ -603,7 +632,7 @@ class MemLocFragmentFill { assert(Base && "Expected a non-zero ID for Base address"); Loc.Base = Base; Loc.DL = DL; - BBInsertBeforeMap[&BB][&Before].push_back(Loc); + BBInsertBeforeMap[&BB][Before].push_back(Loc); LLVM_DEBUG(dbgs() << "Add mem def for " << Aggregates[Var].first->getName() << " bits [" << StartBit << ", " << EndBit << ")\n"); } @@ -612,7 +641,7 @@ class MemLocFragmentFill { /// in \p FragMap starts before \p StartBit or ends after \p EndBit (which /// indicates - assuming StartBit->EndBit has just been inserted - that the /// slice has been coalesced in the map). - void coalesceFragments(BasicBlock &BB, Instruction &Before, unsigned Var, + void coalesceFragments(BasicBlock &BB, VarLocInsertPt Before, unsigned Var, unsigned StartBit, unsigned EndBit, unsigned Base, DebugLoc DL, const FragsInMemMap &FragMap) { if (!CoalesceAdjacentFragments) @@ -633,7 +662,7 @@ class MemLocFragmentFill { Base, DL); } - void addDef(const VarLocInfo &VarLoc, Instruction &Before, BasicBlock &BB, + void addDef(const VarLocInfo &VarLoc, VarLocInsertPt Before, BasicBlock &BB, VarFragMap &LiveSet) { DebugVariable DbgVar = FnVarLocs->getVariable(VarLoc.VariableID); if (skipVariable(DbgVar.getVariable())) @@ -800,9 +829,16 @@ class MemLocFragmentFill { void process(BasicBlock &BB, VarFragMap &LiveSet) { BBInsertBeforeMap[&BB].clear(); for (auto &I : BB) { + for (auto &DPV : I.getDbgValueRange()) { + if (const auto *Locs = FnVarLocs->getWedge(&DPV)) { + for (const VarLocInfo &Loc : *Locs) { + addDef(Loc, &DPV, *I.getParent(), LiveSet); + } + } + } if (const auto *Locs = FnVarLocs->getWedge(&I)) { for (const VarLocInfo &Loc : *Locs) { - addDef(Loc, I, *I.getParent(), LiveSet); + addDef(Loc, &I, *I.getParent(), LiveSet); } } } @@ -923,7 +959,7 @@ public: for (auto &Pair : BBInsertBeforeMap) { InsertMap &Map = Pair.second; for (auto &Pair : Map) { - Instruction *InsertBefore = Pair.first; + auto InsertBefore = Pair.first; assert(InsertBefore && "should never be null"); auto FragMemLocs = Pair.second; auto &Ctx = Fn.getContext(); @@ -990,13 +1026,14 @@ public: /// i.e. for all values x and y where x != y: /// join(x, x) = x /// join(x, y) = NoneOrPhi + using AssignRecord = PointerUnion; struct Assignment { enum S { Known, NoneOrPhi } Status; /// ID of the assignment. nullptr if Status is not Known. DIAssignID *ID; /// The dbg.assign that marks this dbg-def. Mem-defs don't use this field. /// May be nullptr. - DbgAssignIntrinsic *Source; + AssignRecord Source; bool isSameSourceAssignment(const Assignment &Other) const { // Don't include Source in the equality check. Assignments are @@ -1011,31 +1048,51 @@ public: else OS << "null"; OS << ", s="; - if (Source) - OS << *Source; - else + if (Source.isNull()) OS << "null"; + else if (isa(Source)) + OS << Source.get(); + else + OS << Source.get(); OS << ")"; } static Assignment make(DIAssignID *ID, DbgAssignIntrinsic *Source) { return Assignment(Known, ID, Source); } + static Assignment make(DIAssignID *ID, DPValue *Source) { + assert(Source->isDbgAssign() && + "Cannot make an assignment from a non-assign DPValue"); + return Assignment(Known, ID, Source); + } + static Assignment make(DIAssignID *ID, AssignRecord Source) { + return Assignment(Known, ID, Source); + } static Assignment makeFromMemDef(DIAssignID *ID) { - return Assignment(Known, ID, nullptr); - } - static Assignment makeNoneOrPhi() { - return Assignment(NoneOrPhi, nullptr, nullptr); + return Assignment(Known, ID); } + static Assignment makeNoneOrPhi() { return Assignment(NoneOrPhi, nullptr); } // Again, need a Top value? - Assignment() - : Status(NoneOrPhi), ID(nullptr), Source(nullptr) { - } // Can we delete this? + Assignment() : Status(NoneOrPhi), ID(nullptr) {} // Can we delete this? + Assignment(S Status, DIAssignID *ID) : Status(Status), ID(ID) { + // If the Status is Known then we expect there to be an assignment ID. + assert(Status == NoneOrPhi || ID); + } Assignment(S Status, DIAssignID *ID, DbgAssignIntrinsic *Source) : Status(Status), ID(ID), Source(Source) { // If the Status is Known then we expect there to be an assignment ID. assert(Status == NoneOrPhi || ID); } + Assignment(S Status, DIAssignID *ID, DPValue *Source) + : Status(Status), ID(ID), Source(Source) { + // If the Status is Known then we expect there to be an assignment ID. + assert(Status == NoneOrPhi || ID); + } + Assignment(S Status, DIAssignID *ID, AssignRecord Source) + : Status(Status), ID(ID), Source(Source) { + // If the Status is Known then we expect there to be an assignment ID. + assert(Status == NoneOrPhi || ID); + } }; using AssignmentMap = SmallVector; @@ -1056,13 +1113,22 @@ private: UntaggedStoreAssignmentMap UntaggedStoreVars; // Machinery to defer inserting dbg.values. - using InsertMap = MapVector>; - InsertMap InsertBeforeMap; + using InstInsertMap = MapVector>; + InstInsertMap InsertBeforeMap; /// Clear the location definitions currently cached for insertion after /p /// After. void resetInsertionPoint(Instruction &After); - void emitDbgValue(LocKind Kind, const DbgVariableIntrinsic *Source, - Instruction *After); + void resetInsertionPoint(DPValue &After); + + // emitDbgValue can be called with: + // Source=[AssignRecord|DbgValueInst*|DbgAssignIntrinsic*|DPValue*] + // Since AssignRecord can be cast to one of the latter two types, and all + // other types have a shared interface, we use a template to handle the latter + // three types, and an explicit overload for AssignRecord that forwards to + // the template version with the right type. + void emitDbgValue(LocKind Kind, AssignRecord Source, VarLocInsertPt After); + template + void emitDbgValue(LocKind Kind, const T Source, VarLocInsertPt After); static bool mapsAreEqual(const BitVector &Mask, const AssignmentMap &A, const AssignmentMap &B) { @@ -1287,8 +1353,10 @@ private: /// Update \p LiveSet after encountering an instruciton without a DIAssignID /// attachment, \p I. void processUntaggedInstruction(Instruction &I, BlockInfo *LiveSet); - void processDbgAssign(DbgAssignIntrinsic &DAI, BlockInfo *LiveSet); - void processDbgValue(DbgValueInst &DVI, BlockInfo *LiveSet); + void processDbgAssign(AssignRecord Assign, BlockInfo *LiveSet); + void processDPValue(DPValue &DPV, BlockInfo *LiveSet); + void processDbgValue(PointerUnion DbgValueRecord, + BlockInfo *LiveSet); /// Add an assignment to memory for the variable /p Var. void addMemDef(BlockInfo *LiveSet, VariableID Var, const Assignment &AV); /// Add an assignment to the variable /p Var. @@ -1388,6 +1456,12 @@ static DIAssignID *getIDFromMarker(const DbgAssignIntrinsic &DAI) { return cast(DAI.getAssignID()); } +static DIAssignID *getIDFromMarker(const DPValue &DPV) { + assert(DPV.isDbgAssign() && + "Cannot get a DIAssignID from a non-assign DPValue!"); + return DPV.getAssignID(); +} + /// Return true if \p Var has an assignment in \p M matching \p AV. bool AssignmentTrackingLowering::hasVarWithAssignment( BlockInfo *LiveSet, BlockInfo::AssignmentKind Kind, VariableID Var, @@ -1418,9 +1492,46 @@ const char *locStr(AssignmentTrackingLowering::LocKind Loc) { } #endif +VarLocInsertPt getNextNode(const DPValue *DPV) { + auto NextIt = ++(DPV->getIterator()); + if (NextIt == DPV->getMarker()->getDbgValueRange().end()) + return DPV->getMarker()->MarkedInstr; + return &*NextIt; +} +VarLocInsertPt getNextNode(const Instruction *Inst) { + const Instruction *Next = Inst->getNextNode(); + if (!Next->hasDbgValues()) + return Next; + return &*Next->getDbgValueRange().begin(); +} +VarLocInsertPt getNextNode(VarLocInsertPt InsertPt) { + if (isa(InsertPt)) + return getNextNode(cast(InsertPt)); + return getNextNode(cast(InsertPt)); +} + +DbgAssignIntrinsic *CastToDbgAssign(DbgVariableIntrinsic *DVI) { + return cast(DVI); +} + +DPValue *CastToDbgAssign(DPValue *DPV) { + assert(DPV->isDbgAssign() && + "Attempted to cast non-assign DPValue to DPVAssign."); + return DPV; +} + void AssignmentTrackingLowering::emitDbgValue( AssignmentTrackingLowering::LocKind Kind, - const DbgVariableIntrinsic *Source, Instruction *After) { + AssignmentTrackingLowering::AssignRecord Source, VarLocInsertPt After) { + if (isa(Source)) + emitDbgValue(Kind, cast(Source), After); + else + emitDbgValue(Kind, cast(Source), After); +} +template +void AssignmentTrackingLowering::emitDbgValue( + AssignmentTrackingLowering::LocKind Kind, const T Source, + VarLocInsertPt After) { DILocation *DL = Source->getDebugLoc(); auto Emit = [this, Source, After, DL](Metadata *Val, DIExpression *Expr) { @@ -1430,7 +1541,7 @@ void AssignmentTrackingLowering::emitDbgValue( PoisonValue::get(Type::getInt1Ty(Source->getContext()))); // Find a suitable insert point. - Instruction *InsertBefore = After->getNextNode(); + auto InsertBefore = getNextNode(After); assert(InsertBefore && "Shouldn't be inserting after a terminator"); VariableID Var = getVariableID(DebugVariable(Source)); @@ -1445,15 +1556,15 @@ void AssignmentTrackingLowering::emitDbgValue( // NOTE: This block can mutate Kind. if (Kind == LocKind::Mem) { - const auto *DAI = cast(Source); + const auto *Assign = CastToDbgAssign(Source); // Check the address hasn't been dropped (e.g. the debug uses may not have // been replaced before deleting a Value). - if (DAI->isKillAddress()) { + if (Assign->isKillAddress()) { // The address isn't valid so treat this as a non-memory def. Kind = LocKind::Val; } else { - Value *Val = DAI->getAddress(); - DIExpression *Expr = DAI->getAddressExpression(); + Value *Val = Assign->getAddress(); + DIExpression *Expr = Assign->getAddressExpression(); assert(!Expr->getFragmentInfo() && "fragment info should be stored in value-expression only"); // Copy the fragment info over from the value-expression to the new @@ -1538,8 +1649,9 @@ void AssignmentTrackingLowering::processUntaggedInstruction( Ops.push_back(dwarf::DW_OP_deref); DIE = DIExpression::prependOpcodes(DIE, Ops, /*StackValue=*/false, /*EntryValue=*/false); - // Find a suitable insert point. - Instruction *InsertBefore = I.getNextNode(); + // Find a suitable insert point, before the next instruction or DPValue + // after I. + auto InsertBefore = getNextNode(&I); assert(InsertBefore && "Shouldn't be inserting after a terminator"); // Get DILocation for this unrecorded assignment. @@ -1561,25 +1673,26 @@ void AssignmentTrackingLowering::processUntaggedInstruction( void AssignmentTrackingLowering::processTaggedInstruction( Instruction &I, AssignmentTrackingLowering::BlockInfo *LiveSet) { auto Linked = at::getAssignmentMarkers(&I); + auto LinkedDPAssigns = at::getDPVAssignmentMarkers(&I); // No dbg.assign intrinsics linked. // FIXME: All vars that have a stack slot this store modifies that don't have // a dbg.assign linked to it should probably treat this like an untagged // store. - if (Linked.empty()) + if (Linked.empty() && LinkedDPAssigns.empty()) return; LLVM_DEBUG(dbgs() << "processTaggedInstruction on " << I << "\n"); - for (DbgAssignIntrinsic *DAI : Linked) { - VariableID Var = getVariableID(DebugVariable(DAI)); + auto ProcessLinkedAssign = [&](auto *Assign) { + VariableID Var = getVariableID(DebugVariable(Assign)); // Something has gone wrong if VarsWithStackSlot doesn't contain a variable // that is linked to a store. - assert(VarsWithStackSlot->count(getAggregate(DAI)) && - "expected DAI's variable to have stack slot"); + assert(VarsWithStackSlot->count(getAggregate(Assign)) && + "expected Assign's variable to have stack slot"); Assignment AV = Assignment::makeFromMemDef(getIDFromInst(I)); addMemDef(LiveSet, Var, AV); - LLVM_DEBUG(dbgs() << " linked to " << *DAI << "\n"); + LLVM_DEBUG(dbgs() << " linked to " << *Assign << "\n"); LLVM_DEBUG(dbgs() << " LiveLoc " << locStr(getLocKind(LiveSet, Var)) << " -> "); @@ -1594,8 +1707,8 @@ void AssignmentTrackingLowering::processTaggedInstruction( LiveSet->DebugValue[static_cast(Var)].dump(dbgs()); dbgs() << "\n"); setLocKind(LiveSet, Var, LocKind::Mem); - emitDbgValue(LocKind::Mem, DAI, &I); - continue; + emitDbgValue(LocKind::Mem, Assign, &I); + return; } // The StackHomeValue and DebugValue for this variable do not match. I.e. @@ -1620,7 +1733,7 @@ void AssignmentTrackingLowering::processTaggedInstruction( // We need to terminate any previously open location now. LLVM_DEBUG(dbgs() << "None, No Debug value available\n";); setLocKind(LiveSet, Var, LocKind::None); - emitDbgValue(LocKind::None, DAI, &I); + emitDbgValue(LocKind::None, Assign, &I); } else { // The previous DebugValue Value can be used here. LLVM_DEBUG(dbgs() << "Val, Debug value is Known\n";); @@ -1629,7 +1742,7 @@ void AssignmentTrackingLowering::processTaggedInstruction( emitDbgValue(LocKind::Val, DbgAV.Source, &I); } else { // PrevAV.Source is nullptr so we must emit undef here. - emitDbgValue(LocKind::None, DAI, &I); + emitDbgValue(LocKind::None, Assign, &I); } } } break; @@ -1640,78 +1753,93 @@ void AssignmentTrackingLowering::processTaggedInstruction( setLocKind(LiveSet, Var, LocKind::None); } break; } - } + }; + for (DbgAssignIntrinsic *DAI : Linked) + ProcessLinkedAssign(DAI); + for (DPValue *DPV : LinkedDPAssigns) + ProcessLinkedAssign(DPV); } -void AssignmentTrackingLowering::processDbgAssign(DbgAssignIntrinsic &DAI, +void AssignmentTrackingLowering::processDbgAssign(AssignRecord Assign, BlockInfo *LiveSet) { - // Only bother tracking variables that are at some point stack homed. Other - // variables can be dealt with trivially later. - if (!VarsWithStackSlot->count(getAggregate(&DAI))) - return; + auto ProcessDbgAssignImpl = [&](auto *DbgAssign) { + // Only bother tracking variables that are at some point stack homed. Other + // variables can be dealt with trivially later. + if (!VarsWithStackSlot->count(getAggregate(DbgAssign))) + return; - VariableID Var = getVariableID(DebugVariable(&DAI)); - Assignment AV = Assignment::make(getIDFromMarker(DAI), &DAI); - addDbgDef(LiveSet, Var, AV); + VariableID Var = getVariableID(DebugVariable(DbgAssign)); + Assignment AV = Assignment::make(getIDFromMarker(*DbgAssign), DbgAssign); + addDbgDef(LiveSet, Var, AV); - LLVM_DEBUG(dbgs() << "processDbgAssign on " << DAI << "\n";); - LLVM_DEBUG(dbgs() << " LiveLoc " << locStr(getLocKind(LiveSet, Var)) - << " -> "); + LLVM_DEBUG(dbgs() << "processDbgAssign on " << *DbgAssign << "\n";); + LLVM_DEBUG(dbgs() << " LiveLoc " << locStr(getLocKind(LiveSet, Var)) + << " -> "); - // Check if the DebugValue and StackHomeValue both hold the same - // Assignment. - if (hasVarWithAssignment(LiveSet, BlockInfo::Stack, Var, AV)) { - // They match. We can use the stack home because the debug intrinsics state - // that an assignment happened here, and we know that specific assignment - // was the last one to take place in memory for this variable. - LocKind Kind; - if (DAI.isKillAddress()) { - LLVM_DEBUG( - dbgs() - << "Val, Stack matches Debug program but address is killed\n";); - Kind = LocKind::Val; + // Check if the DebugValue and StackHomeValue both hold the same + // Assignment. + if (hasVarWithAssignment(LiveSet, BlockInfo::Stack, Var, AV)) { + // They match. We can use the stack home because the debug intrinsics + // state that an assignment happened here, and we know that specific + // assignment was the last one to take place in memory for this variable. + LocKind Kind; + if (DbgAssign->isKillAddress()) { + LLVM_DEBUG( + dbgs() + << "Val, Stack matches Debug program but address is killed\n";); + Kind = LocKind::Val; + } else { + LLVM_DEBUG(dbgs() << "Mem, Stack matches Debug program\n";); + Kind = LocKind::Mem; + }; + setLocKind(LiveSet, Var, Kind); + emitDbgValue(Kind, DbgAssign, DbgAssign); } else { - LLVM_DEBUG(dbgs() << "Mem, Stack matches Debug program\n";); - Kind = LocKind::Mem; - }; - setLocKind(LiveSet, Var, Kind); - emitDbgValue(Kind, &DAI, &DAI); - } else { - // The last assignment to the memory location isn't the one that we want to - // show to the user so emit a dbg.value(Value). Value may be undef. - LLVM_DEBUG(dbgs() << "Val, Stack contents is unknown\n";); + // The last assignment to the memory location isn't the one that we want + // to show to the user so emit a dbg.value(Value). Value may be undef. + LLVM_DEBUG(dbgs() << "Val, Stack contents is unknown\n";); + setLocKind(LiveSet, Var, LocKind::Val); + emitDbgValue(LocKind::Val, DbgAssign, DbgAssign); + } + }; + if (isa(Assign)) + return ProcessDbgAssignImpl(cast(Assign)); + return ProcessDbgAssignImpl(cast(Assign)); +} + +void AssignmentTrackingLowering::processDbgValue( + PointerUnion DbgValueRecord, + BlockInfo *LiveSet) { + auto ProcessDbgValueImpl = [&](auto *DbgValue) { + // Only other tracking variables that are at some point stack homed. + // Other variables can be dealt with trivally later. + if (!VarsWithStackSlot->count(getAggregate(DbgValue))) + return; + + VariableID Var = getVariableID(DebugVariable(DbgValue)); + // We have no ID to create an Assignment with so we mark this assignment as + // NoneOrPhi. Note that the dbg.value still exists, we just cannot determine + // the assignment responsible for setting this value. + // This is fine; dbg.values are essentially interchangable with unlinked + // dbg.assigns, and some passes such as mem2reg and instcombine add them to + // PHIs for promoted variables. + Assignment AV = Assignment::makeNoneOrPhi(); + addDbgDef(LiveSet, Var, AV); + + LLVM_DEBUG(dbgs() << "processDbgValue on " << *DbgValue << "\n";); + LLVM_DEBUG(dbgs() << " LiveLoc " << locStr(getLocKind(LiveSet, Var)) + << " -> Val, dbg.value override"); + setLocKind(LiveSet, Var, LocKind::Val); - emitDbgValue(LocKind::Val, &DAI, &DAI); - } + emitDbgValue(LocKind::Val, DbgValue, DbgValue); + }; + if (isa(DbgValueRecord)) + return ProcessDbgValueImpl(cast(DbgValueRecord)); + return ProcessDbgValueImpl(cast(DbgValueRecord)); } -void AssignmentTrackingLowering::processDbgValue(DbgValueInst &DVI, - BlockInfo *LiveSet) { - // Only other tracking variables that are at some point stack homed. - // Other variables can be dealt with trivally later. - if (!VarsWithStackSlot->count(getAggregate(&DVI))) - return; - - VariableID Var = getVariableID(DebugVariable(&DVI)); - // We have no ID to create an Assignment with so we mark this assignment as - // NoneOrPhi. Note that the dbg.value still exists, we just cannot determine - // the assignment responsible for setting this value. - // This is fine; dbg.values are essentially interchangable with unlinked - // dbg.assigns, and some passes such as mem2reg and instcombine add them to - // PHIs for promoted variables. - Assignment AV = Assignment::makeNoneOrPhi(); - addDbgDef(LiveSet, Var, AV); - - LLVM_DEBUG(dbgs() << "processDbgValue on " << DVI << "\n";); - LLVM_DEBUG(dbgs() << " LiveLoc " << locStr(getLocKind(LiveSet, Var)) - << " -> Val, dbg.value override"); - - setLocKind(LiveSet, Var, LocKind::Val); - emitDbgValue(LocKind::Val, &DVI, &DVI); -} - -static bool hasZeroSizedFragment(DbgVariableIntrinsic &DVI) { - if (auto F = DVI.getExpression()->getFragmentInfo()) +template static bool hasZeroSizedFragment(T &DbgValue) { + if (auto F = DbgValue.getExpression()->getFragmentInfo()) return F->SizeInBits == 0; return false; } @@ -1727,33 +1855,73 @@ void AssignmentTrackingLowering::processDbgInstruction( return; if (auto *DAI = dyn_cast(&I)) - processDbgAssign(*DAI, LiveSet); + processDbgAssign(DAI, LiveSet); else if (auto *DVI = dyn_cast(&I)) - processDbgValue(*DVI, LiveSet); + processDbgValue(DVI, LiveSet); +} +void AssignmentTrackingLowering::processDPValue( + DPValue &DPV, AssignmentTrackingLowering::BlockInfo *LiveSet) { + // Ignore assignments to zero bits of the variable. + if (hasZeroSizedFragment(DPV)) + return; + + if (DPV.isDbgAssign()) + processDbgAssign(&DPV, LiveSet); + else if (DPV.isDbgValue()) + processDbgValue(&DPV, LiveSet); } void AssignmentTrackingLowering::resetInsertionPoint(Instruction &After) { assert(!After.isTerminator() && "Can't insert after a terminator"); - auto R = InsertBeforeMap.find(After.getNextNode()); + auto *R = InsertBeforeMap.find(getNextNode(&After)); + if (R == InsertBeforeMap.end()) + return; + R->second.clear(); +} +void AssignmentTrackingLowering::resetInsertionPoint(DPValue &After) { + auto *R = InsertBeforeMap.find(getNextNode(&After)); if (R == InsertBeforeMap.end()) return; R->second.clear(); } void AssignmentTrackingLowering::process(BasicBlock &BB, BlockInfo *LiveSet) { + // If the block starts with DPValues, we need to process those DPValues as + // their own frame without processing any instructions first. + bool ProcessedLeadingDPValues = !BB.begin()->hasDbgValues(); for (auto II = BB.begin(), EI = BB.end(); II != EI;) { assert(VarsTouchedThisFrame.empty()); // Process the instructions in "frames". A "frame" includes a single // non-debug instruction followed any debug instructions before the // next non-debug instruction. - if (!isa(&*II)) { - if (II->isTerminator()) - break; - resetInsertionPoint(*II); - processNonDbgInstruction(*II, LiveSet); - assert(LiveSet->isValid()); - ++II; + + // Skip the current instruction if it has unprocessed DPValues attached (see + // comment above `ProcessedLeadingDPValues`). + if (ProcessedLeadingDPValues) { + // II is now either a debug intrinsic, a non-debug instruction with no + // attached DPValues, or a non-debug instruction with attached processed + // DPValues. + // II has not been processed. + if (!isa(&*II)) { + if (II->isTerminator()) + break; + resetInsertionPoint(*II); + processNonDbgInstruction(*II, LiveSet); + assert(LiveSet->isValid()); + ++II; + } } + // II is now either a debug intrinsic, a non-debug instruction with no + // attached DPValues, or a non-debug instruction with attached unprocessed + // DPValues. + if (II != EI && II->hasDbgValues()) { + for (DPValue &DPV : II->getDbgValueRange()) { + resetInsertionPoint(DPV); + processDPValue(DPV, LiveSet); + assert(LiveSet->isValid()); + } + } + ProcessedLeadingDPValues = true; while (II != EI) { auto *Dbg = dyn_cast(&*II); if (!Dbg) @@ -1763,6 +1931,10 @@ void AssignmentTrackingLowering::process(BasicBlock &BB, BlockInfo *LiveSet) { assert(LiveSet->isValid()); ++II; } + // II is now a non-debug instruction either with no attached DPValues, or + // with attached processed DPValues. II has not been processed, and all + // debug instructions or DPValues in the frame preceding II have been + // processed. // We've processed everything in the "frame". Now determine which variables // cannot be represented by a dbg.declare. @@ -1819,16 +1991,22 @@ AssignmentTrackingLowering::joinAssignment(const Assignment &A, // Here the same assignment (!1) was performed in both preds in the source, // but we can't use either one unless they are identical (e.g. .we don't // want to arbitrarily pick between constant values). - auto JoinSource = [&]() -> DbgAssignIntrinsic * { + auto JoinSource = [&]() -> AssignRecord { if (A.Source == B.Source) return A.Source; - if (A.Source == nullptr || B.Source == nullptr) - return nullptr; - if (A.Source->isIdenticalTo(B.Source)) + if (!A.Source || !B.Source) + return AssignRecord(); + assert(isa(A.Source) == isa(B.Source)); + if (isa(A.Source) && + cast(A.Source)->isEquivalentTo(*cast(B.Source))) return A.Source; - return nullptr; + if (isa(A.Source) && + cast(A.Source)->isIdenticalTo( + cast(B.Source))) + return A.Source; + return AssignRecord(); }; - DbgAssignIntrinsic *Source = JoinSource(); + AssignRecord Source = JoinSource(); assert(A.Status == B.Status && A.Status == Assignment::Known); assert(A.ID == B.ID); return Assignment::make(A.ID, Source); @@ -1851,8 +2029,7 @@ bool AssignmentTrackingLowering::join( // invalidated later, we will remove it when we revisit this block. This // is essentially the same as initialising all LocKinds and Assignments to // an implicit ⊥ value which is the identity value for the join operation. - for (auto I = pred_begin(&BB), E = pred_end(&BB); I != E; I++) { - const BasicBlock *Pred = *I; + for (const BasicBlock *Pred : predecessors(&BB)) { if (Visited.count(Pred)) VisitedPreds.push_back(Pred); } @@ -1938,6 +2115,14 @@ getUntaggedStoreAssignmentInfo(const Instruction &I, const DataLayout &Layout) { return std::nullopt; } +DbgDeclareInst *DynCastToDbgDeclare(DbgVariableIntrinsic *DVI) { + return dyn_cast(DVI); +} + +DPValue *DynCastToDbgDeclare(DPValue *DPV) { + return DPV->isDbgDeclare() ? DPV : nullptr; +} + /// Build a map of {Variable x: Variables y} where all variable fragments /// contained within the variable fragment x are in set y. This means that /// y does not contain all overlaps because partial overlaps are excluded. @@ -1971,31 +2156,39 @@ static AssignmentTrackingLowering::OverlapMap buildOverlapMapAndRecordDeclares( // UntaggedStoreVars. // We need to add fragments for untagged stores too so that we can correctly // clobber overlapped fragment locations later. - SmallVector Declares; + SmallVector InstDeclares; + SmallVector DPDeclares; + auto ProcessDbgRecord = [&](auto *Record, auto &DeclareList) { + if (auto *Declare = DynCastToDbgDeclare(Record)) { + DeclareList.push_back(Declare); + return; + } + DebugVariable DV = DebugVariable(Record); + DebugAggregate DA = {DV.getVariable(), DV.getInlinedAt()}; + if (!VarsWithStackSlot.contains(DA)) + return; + if (Seen.insert(DV).second) + FragmentMap[DA].push_back(DV); + }; for (auto &BB : Fn) { for (auto &I : BB) { - if (auto *DDI = dyn_cast(&I)) { - Declares.push_back(DDI); - } else if (auto *DII = dyn_cast(&I)) { - DebugVariable DV = DebugVariable(DII); - DebugAggregate DA = {DV.getVariable(), DV.getInlinedAt()}; - if (!VarsWithStackSlot.contains(DA)) - continue; - if (Seen.insert(DV).second) - FragmentMap[DA].push_back(DV); + for (auto &DPV : I.getDbgValueRange()) + ProcessDbgRecord(&DPV, DPDeclares); + if (auto *DII = dyn_cast(&I)) { + ProcessDbgRecord(DII, InstDeclares); } else if (auto Info = getUntaggedStoreAssignmentInfo( I, Fn.getParent()->getDataLayout())) { // Find markers linked to this alloca. - for (DbgAssignIntrinsic *DAI : at::getAssignmentMarkers(Info->Base)) { + auto HandleDbgAssignForStore = [&](auto *Assign) { std::optional FragInfo; // Skip this assignment if the affected bits are outside of the // variable fragment. if (!at::calculateFragmentIntersect( I.getModule()->getDataLayout(), Info->Base, - Info->OffsetInBits, Info->SizeInBits, DAI, FragInfo) || + Info->OffsetInBits, Info->SizeInBits, Assign, FragInfo) || (FragInfo && FragInfo->SizeInBits == 0)) - continue; + return; // FragInfo from calculateFragmentIntersect is nullopt if the // resultant fragment matches DAI's fragment or entire variable - in @@ -2003,13 +2196,14 @@ static AssignmentTrackingLowering::OverlapMap buildOverlapMapAndRecordDeclares( // nullopt after the copy it means "no fragment info" instead, which // is how it is usually interpreted. if (!FragInfo) - FragInfo = DAI->getExpression()->getFragmentInfo(); + FragInfo = Assign->getExpression()->getFragmentInfo(); - DebugVariable DV = DebugVariable(DAI->getVariable(), FragInfo, - DAI->getDebugLoc().getInlinedAt()); + DebugVariable DV = + DebugVariable(Assign->getVariable(), FragInfo, + Assign->getDebugLoc().getInlinedAt()); DebugAggregate DA = {DV.getVariable(), DV.getInlinedAt()}; if (!VarsWithStackSlot.contains(DA)) - continue; + return; // Cache this info for later. UntaggedStoreVars[&I].push_back( @@ -2017,7 +2211,11 @@ static AssignmentTrackingLowering::OverlapMap buildOverlapMapAndRecordDeclares( if (Seen.insert(DV).second) FragmentMap[DA].push_back(DV); - } + }; + for (DbgAssignIntrinsic *DAI : at::getAssignmentMarkers(Info->Base)) + HandleDbgAssignForStore(DAI); + for (DPValue *DPV : at::getDPVAssignmentMarkers(Info->Base)) + HandleDbgAssignForStore(DPV); } } } @@ -2064,9 +2262,13 @@ static AssignmentTrackingLowering::OverlapMap buildOverlapMapAndRecordDeclares( // Finally, insert the declares afterwards, so the first IDs are all // partially stack homed vars. - for (auto *DDI : Declares) + for (auto *DDI : InstDeclares) FnVarLocs->addSingleLocVar(DebugVariable(DDI), DDI->getExpression(), DDI->getDebugLoc(), DDI->getWrappedLocation()); + for (auto *DPV : DPDeclares) + FnVarLocs->addSingleLocVar(DebugVariable(DPV), DPV->getExpression(), + DPV->getDebugLoc(), + RawLocationWrapper(DPV->getRawLocation())); return Map; } @@ -2179,7 +2381,7 @@ bool AssignmentTrackingLowering::run(FunctionVarLocsBuilder *FnVarLocsBuilder) { // we can identify those uneeded defs later. DenseSet AlwaysStackHomed; for (const auto &Pair : InsertBeforeMap) { - const auto &Vec = Pair.second; + auto &Vec = Pair.second; for (VarLocInfo VarLoc : Vec) { DebugVariable Var = FnVarLocs->getVariable(VarLoc.VariableID); DebugAggregate Aggr{Var.getVariable(), Var.getInlinedAt()}; @@ -2245,22 +2447,27 @@ bool AssignmentTrackingLowering::emitPromotedVarLocs( bool InsertedAnyIntrinsics = false; // Go through every block, translating debug intrinsics for fully promoted // variables into FnVarLocs location defs. No analysis required for these. + auto TranslateDbgRecord = [&](auto *Record) { + // Skip variables that haven't been promoted - we've dealt with those + // already. + if (VarsWithStackSlot->contains(getAggregate(Record))) + return; + auto InsertBefore = getNextNode(Record); + assert(InsertBefore && "Unexpected: debug intrinsics after a terminator"); + FnVarLocs->addVarLoc(InsertBefore, DebugVariable(Record), + Record->getExpression(), Record->getDebugLoc(), + RawLocationWrapper(Record->getRawLocation())); + InsertedAnyIntrinsics = true; + }; for (auto &BB : Fn) { for (auto &I : BB) { // Skip instructions other than dbg.values and dbg.assigns. + for (DPValue &DPV : I.getDbgValueRange()) + if (DPV.isDbgValue() || DPV.isDbgAssign()) + TranslateDbgRecord(&DPV); auto *DVI = dyn_cast(&I); - if (!DVI) - continue; - // Skip variables that haven't been promoted - we've dealt with those - // already. - if (VarsWithStackSlot->contains(getAggregate(DVI))) - continue; - Instruction *InsertBefore = I.getNextNode(); - assert(InsertBefore && "Unexpected: debug intrinsics after a terminator"); - FnVarLocs->addVarLoc(InsertBefore, DebugVariable(DVI), - DVI->getExpression(), DVI->getDebugLoc(), - DVI->getWrappedLocation()); - InsertedAnyIntrinsics = true; + if (DVI) + TranslateDbgRecord(DVI); } } return InsertedAnyIntrinsics; @@ -2287,73 +2494,78 @@ removeRedundantDbgLocsUsingBackwardScan(const BasicBlock *BB, VariableDefinedBytes.clear(); } - // Get the location defs that start just before this instruction. - const auto *Locs = FnVarLocs.getWedge(&I); - if (!Locs) - continue; + auto HandleLocsForWedge = [&](auto *WedgePosition) { + // Get the location defs that start just before this instruction. + const auto *Locs = FnVarLocs.getWedge(WedgePosition); + if (!Locs) + return; - NumWedgesScanned++; - bool ChangedThisWedge = false; - // The new pruned set of defs, reversed because we're scanning backwards. - SmallVector NewDefsReversed; + NumWedgesScanned++; + bool ChangedThisWedge = false; + // The new pruned set of defs, reversed because we're scanning backwards. + SmallVector NewDefsReversed; - // Iterate over the existing defs in reverse. - for (auto RIt = Locs->rbegin(), REnd = Locs->rend(); RIt != REnd; ++RIt) { - NumDefsScanned++; - DebugAggregate Aggr = - getAggregate(FnVarLocs.getVariable(RIt->VariableID)); - uint64_t SizeInBits = Aggr.first->getSizeInBits().value_or(0); - uint64_t SizeInBytes = divideCeil(SizeInBits, 8); + // Iterate over the existing defs in reverse. + for (auto RIt = Locs->rbegin(), REnd = Locs->rend(); RIt != REnd; ++RIt) { + NumDefsScanned++; + DebugAggregate Aggr = + getAggregate(FnVarLocs.getVariable(RIt->VariableID)); + uint64_t SizeInBits = Aggr.first->getSizeInBits().value_or(0); + uint64_t SizeInBytes = divideCeil(SizeInBits, 8); - // Cutoff for large variables to prevent expensive bitvector operations. - const uint64_t MaxSizeBytes = 2048; + // Cutoff for large variables to prevent expensive bitvector operations. + const uint64_t MaxSizeBytes = 2048; - if (SizeInBytes == 0 || SizeInBytes > MaxSizeBytes) { - // If the size is unknown (0) then keep this location def to be safe. - // Do the same for defs of large variables, which would be expensive - // to represent with a BitVector. - NewDefsReversed.push_back(*RIt); - continue; + if (SizeInBytes == 0 || SizeInBytes > MaxSizeBytes) { + // If the size is unknown (0) then keep this location def to be safe. + // Do the same for defs of large variables, which would be expensive + // to represent with a BitVector. + NewDefsReversed.push_back(*RIt); + continue; + } + + // Only keep this location definition if it is not fully eclipsed by + // other definitions in this wedge that come after it + + // Inert the bytes the location definition defines. + auto InsertResult = + VariableDefinedBytes.try_emplace(Aggr, BitVector(SizeInBytes)); + bool FirstDefinition = InsertResult.second; + BitVector &DefinedBytes = InsertResult.first->second; + + DIExpression::FragmentInfo Fragment = + RIt->Expr->getFragmentInfo().value_or( + DIExpression::FragmentInfo(SizeInBits, 0)); + bool InvalidFragment = Fragment.endInBits() > SizeInBits; + uint64_t StartInBytes = Fragment.startInBits() / 8; + uint64_t EndInBytes = divideCeil(Fragment.endInBits(), 8); + + // If this defines any previously undefined bytes, keep it. + if (FirstDefinition || InvalidFragment || + DefinedBytes.find_first_unset_in(StartInBytes, EndInBytes) != -1) { + if (!InvalidFragment) + DefinedBytes.set(StartInBytes, EndInBytes); + NewDefsReversed.push_back(*RIt); + continue; + } + + // Redundant def found: throw it away. Since the wedge of defs is being + // rebuilt, doing nothing is the same as deleting an entry. + ChangedThisWedge = true; + NumDefsRemoved++; } - // Only keep this location definition if it is not fully eclipsed by - // other definitions in this wedge that come after it - - // Inert the bytes the location definition defines. - auto InsertResult = - VariableDefinedBytes.try_emplace(Aggr, BitVector(SizeInBytes)); - bool FirstDefinition = InsertResult.second; - BitVector &DefinedBytes = InsertResult.first->second; - - DIExpression::FragmentInfo Fragment = - RIt->Expr->getFragmentInfo().value_or( - DIExpression::FragmentInfo(SizeInBits, 0)); - bool InvalidFragment = Fragment.endInBits() > SizeInBits; - uint64_t StartInBytes = Fragment.startInBits() / 8; - uint64_t EndInBytes = divideCeil(Fragment.endInBits(), 8); - - // If this defines any previously undefined bytes, keep it. - if (FirstDefinition || InvalidFragment || - DefinedBytes.find_first_unset_in(StartInBytes, EndInBytes) != -1) { - if (!InvalidFragment) - DefinedBytes.set(StartInBytes, EndInBytes); - NewDefsReversed.push_back(*RIt); - continue; + // Un-reverse the defs and replace the wedge with the pruned version. + if (ChangedThisWedge) { + std::reverse(NewDefsReversed.begin(), NewDefsReversed.end()); + FnVarLocs.setWedge(WedgePosition, std::move(NewDefsReversed)); + NumWedgesChanged++; + Changed = true; } - - // Redundant def found: throw it away. Since the wedge of defs is being - // rebuilt, doing nothing is the same as deleting an entry. - ChangedThisWedge = true; - NumDefsRemoved++; - } - - // Un-reverse the defs and replace the wedge with the pruned version. - if (ChangedThisWedge) { - std::reverse(NewDefsReversed.begin(), NewDefsReversed.end()); - FnVarLocs.setWedge(&I, std::move(NewDefsReversed)); - NumWedgesChanged++; - Changed = true; - } + }; + HandleLocsForWedge(&I); + for (DPValue &DPV : reverse(I.getDbgValueRange())) + HandleLocsForWedge(&DPV); } return Changed; @@ -2378,42 +2590,48 @@ removeRedundantDbgLocsUsingForwardScan(const BasicBlock *BB, // instructions. for (const Instruction &I : *BB) { // Get the defs that come just before this instruction. - const auto *Locs = FnVarLocs.getWedge(&I); - if (!Locs) - continue; + auto HandleLocsForWedge = [&](auto *WedgePosition) { + const auto *Locs = FnVarLocs.getWedge(WedgePosition); + if (!Locs) + return; - NumWedgesScanned++; - bool ChangedThisWedge = false; - // The new pruned set of defs. - SmallVector NewDefs; + NumWedgesScanned++; + bool ChangedThisWedge = false; + // The new pruned set of defs. + SmallVector NewDefs; - // Iterate over the existing defs. - for (const VarLocInfo &Loc : *Locs) { - NumDefsScanned++; - DebugVariable Key(FnVarLocs.getVariable(Loc.VariableID).getVariable(), - std::nullopt, Loc.DL.getInlinedAt()); - auto VMI = VariableMap.find(Key); + // Iterate over the existing defs. + for (const VarLocInfo &Loc : *Locs) { + NumDefsScanned++; + DebugVariable Key(FnVarLocs.getVariable(Loc.VariableID).getVariable(), + std::nullopt, Loc.DL.getInlinedAt()); + auto VMI = VariableMap.find(Key); - // Update the map if we found a new value/expression describing the - // variable, or if the variable wasn't mapped already. - if (VMI == VariableMap.end() || VMI->second.first != Loc.Values || - VMI->second.second != Loc.Expr) { - VariableMap[Key] = {Loc.Values, Loc.Expr}; - NewDefs.push_back(Loc); - continue; + // Update the map if we found a new value/expression describing the + // variable, or if the variable wasn't mapped already. + if (VMI == VariableMap.end() || VMI->second.first != Loc.Values || + VMI->second.second != Loc.Expr) { + VariableMap[Key] = {Loc.Values, Loc.Expr}; + NewDefs.push_back(Loc); + continue; + } + + // Did not insert this Loc, which is the same as removing it. + ChangedThisWedge = true; + NumDefsRemoved++; } - // Did not insert this Loc, which is the same as removing it. - ChangedThisWedge = true; - NumDefsRemoved++; - } + // Replace the existing wedge with the pruned version. + if (ChangedThisWedge) { + FnVarLocs.setWedge(WedgePosition, std::move(NewDefs)); + NumWedgesChanged++; + Changed = true; + } + }; - // Replace the existing wedge with the pruned version. - if (ChangedThisWedge) { - FnVarLocs.setWedge(&I, std::move(NewDefs)); - NumWedgesChanged++; - Changed = true; - } + for (DPValue &DPV : I.getDbgValueRange()) + HandleLocsForWedge(&DPV); + HandleLocsForWedge(&I); } return Changed; @@ -2460,41 +2678,46 @@ removeUndefDbgLocsFromEntryBlock(const BasicBlock *BB, // instructions. for (const Instruction &I : *BB) { // Get the defs that come just before this instruction. - const auto *Locs = FnVarLocs.getWedge(&I); - if (!Locs) - continue; + auto HandleLocsForWedge = [&](auto *WedgePosition) { + const auto *Locs = FnVarLocs.getWedge(WedgePosition); + if (!Locs) + return; - NumWedgesScanned++; - bool ChangedThisWedge = false; - // The new pruned set of defs. - SmallVector NewDefs; + NumWedgesScanned++; + bool ChangedThisWedge = false; + // The new pruned set of defs. + SmallVector NewDefs; - // Iterate over the existing defs. - for (const VarLocInfo &Loc : *Locs) { - NumDefsScanned++; - DebugAggregate Aggr{FnVarLocs.getVariable(Loc.VariableID).getVariable(), - Loc.DL.getInlinedAt()}; - DebugVariable Var = FnVarLocs.getVariable(Loc.VariableID); + // Iterate over the existing defs. + for (const VarLocInfo &Loc : *Locs) { + NumDefsScanned++; + DebugAggregate Aggr{FnVarLocs.getVariable(Loc.VariableID).getVariable(), + Loc.DL.getInlinedAt()}; + DebugVariable Var = FnVarLocs.getVariable(Loc.VariableID); - // Remove undef entries that are encountered before any non-undef - // intrinsics from the entry block. - if (Loc.Values.isKillLocation(Loc.Expr) && !HasDefinedBits(Aggr, Var)) { - // Did not insert this Loc, which is the same as removing it. - NumDefsRemoved++; - ChangedThisWedge = true; - continue; + // Remove undef entries that are encountered before any non-undef + // intrinsics from the entry block. + if (Loc.Values.isKillLocation(Loc.Expr) && !HasDefinedBits(Aggr, Var)) { + // Did not insert this Loc, which is the same as removing it. + NumDefsRemoved++; + ChangedThisWedge = true; + continue; + } + + DefineBits(Aggr, Var); + NewDefs.push_back(Loc); } - DefineBits(Aggr, Var); - NewDefs.push_back(Loc); - } - - // Replace the existing wedge with the pruned version. - if (ChangedThisWedge) { - FnVarLocs.setWedge(&I, std::move(NewDefs)); - NumWedgesChanged++; - Changed = true; - } + // Replace the existing wedge with the pruned version. + if (ChangedThisWedge) { + FnVarLocs.setWedge(WedgePosition, std::move(NewDefs)); + NumWedgesChanged++; + Changed = true; + } + }; + for (DPValue &DPV : I.getDbgValueRange()) + HandleLocsForWedge(&DPV); + HandleLocsForWedge(&I); } return Changed; @@ -2526,6 +2749,9 @@ static DenseSet findVarsWithStackSlot(Function &Fn) { for (DbgAssignIntrinsic *DAI : at::getAssignmentMarkers(&I)) { Result.insert({DAI->getVariable(), DAI->getDebugLoc().getInlinedAt()}); } + for (DPValue *DPV : at::getDPVAssignmentMarkers(&I)) { + Result.insert({DPV->getVariable(), DPV->getDebugLoc().getInlinedAt()}); + } } } return Result; diff --git a/llvm/lib/CodeGen/BasicBlockSections.cpp b/llvm/lib/CodeGen/BasicBlockSections.cpp index 94b5a503fbd..dbb6ebb3d7e 100644 --- a/llvm/lib/CodeGen/BasicBlockSections.cpp +++ b/llvm/lib/CodeGen/BasicBlockSections.cpp @@ -318,9 +318,8 @@ bool BasicBlockSections::runOnMachineFunction(MachineFunction &MF) { MF.setBBSectionsType(BBSectionsType); assignSections(MF, FuncClusterInfo); - // We make sure that the cluster including the entry basic block precedes all - // other clusters. - auto EntryBBSectionID = MF.front().getSectionID(); + const MachineBasicBlock &EntryBB = MF.front(); + auto EntryBBSectionID = EntryBB.getSectionID(); // Helper function for ordering BB sections as follows: // * Entry section (section including the entry block). @@ -341,12 +340,17 @@ bool BasicBlockSections::runOnMachineFunction(MachineFunction &MF) { // contiguous and ordered accordingly. Furthermore, clusters are ordered in // increasing order of their section IDs, with the exception and the // cold section placed at the end of the function. + // Also, we force the entry block of the function to be placed at the + // beginning of the function, regardless of the requested order. auto Comparator = [&](const MachineBasicBlock &X, const MachineBasicBlock &Y) { auto XSectionID = X.getSectionID(); auto YSectionID = Y.getSectionID(); if (XSectionID != YSectionID) return MBBSectionOrder(XSectionID, YSectionID); + // Make sure that the entry block is placed at the beginning. + if (&X == &EntryBB || &Y == &EntryBB) + return &X == &EntryBB; // If the two basic block are in the same section, the order is decided by // their position within the section. if (XSectionID.Type == MBBSectionID::SectionType::Default) diff --git a/llvm/lib/CodeGen/BasicBlockSectionsProfileReader.cpp b/llvm/lib/CodeGen/BasicBlockSectionsProfileReader.cpp index 79e42d9304d..6eef5d2c50a 100644 --- a/llvm/lib/CodeGen/BasicBlockSectionsProfileReader.cpp +++ b/llvm/lib/CodeGen/BasicBlockSectionsProfileReader.cpp @@ -214,10 +214,6 @@ Error BasicBlockSectionsProfileReader::ReadV1Profile() { Twine("duplicate basic block id found '") + BasicBlockIDStr + "'"); - if (!BasicBlockID->BaseID && CurrentPosition) - return createProfileParseError( - "entry BB (0) does not begin a cluster."); - FI->second.ClusterInfo.emplace_back(BBClusterInfo{ *std::move(BasicBlockID), CurrentCluster, CurrentPosition++}); } @@ -288,9 +284,6 @@ Error BasicBlockSectionsProfileReader::ReadV0Profile() { if (!FuncBBIDs.insert(BBID).second) return createProfileParseError( Twine("duplicate basic block id found '") + BBIDStr + "'"); - if (BBID == 0 && CurrentPosition) - return createProfileParseError( - "entry BB (0) does not begin a cluster"); FI->second.ClusterInfo.emplace_back( BBClusterInfo({{static_cast(BBID), 0}, diff --git a/llvm/lib/CodeGen/BranchFolding.cpp b/llvm/lib/CodeGen/BranchFolding.cpp index 599b7c72b2f..a9f78358e57 100644 --- a/llvm/lib/CodeGen/BranchFolding.cpp +++ b/llvm/lib/CodeGen/BranchFolding.cpp @@ -1411,7 +1411,7 @@ ReoptimizeBlock: // This has to check PrevBB->succ_size() because EH edges are ignored by // analyzeBranch. if (PriorCond.empty() && !PriorTBB && MBB->pred_size() == 1 && - PrevBB.succ_size() == 1 && + PrevBB.succ_size() == 1 && PrevBB.isSuccessor(MBB) && !MBB->hasAddressTaken() && !MBB->isEHPad()) { LLVM_DEBUG(dbgs() << "\nMerging into block: " << PrevBB << "From MBB: " << *MBB); diff --git a/llvm/lib/CodeGen/CodeGenPrepare.cpp b/llvm/lib/CodeGen/CodeGenPrepare.cpp index b8bfb9742bf..8ee1f19e083 100644 --- a/llvm/lib/CodeGen/CodeGenPrepare.cpp +++ b/llvm/lib/CodeGen/CodeGenPrepare.cpp @@ -5553,7 +5553,6 @@ bool CodeGenPrepare::optimizeMemoryInst(Instruction *MemoryInst, Value *Addr, } else { Type *I8PtrTy = Builder.getPtrTy(Addr->getType()->getPointerAddressSpace()); - Type *I8Ty = Builder.getInt8Ty(); // Start with the base register. Do this first so that subsequent address // matching finds it last, which will prevent it from trying to match it @@ -5597,8 +5596,8 @@ bool CodeGenPrepare::optimizeMemoryInst(Instruction *MemoryInst, Value *Addr, // SDAG consecutive load/store merging. if (ResultPtr->getType() != I8PtrTy) ResultPtr = Builder.CreatePointerCast(ResultPtr, I8PtrTy); - ResultPtr = Builder.CreateGEP(I8Ty, ResultPtr, ResultIndex, - "sunkaddr", AddrMode.InBounds); + ResultPtr = Builder.CreatePtrAdd(ResultPtr, ResultIndex, "sunkaddr", + AddrMode.InBounds); } ResultIndex = V; @@ -5609,8 +5608,8 @@ bool CodeGenPrepare::optimizeMemoryInst(Instruction *MemoryInst, Value *Addr, } else { if (ResultPtr->getType() != I8PtrTy) ResultPtr = Builder.CreatePointerCast(ResultPtr, I8PtrTy); - SunkAddr = Builder.CreateGEP(I8Ty, ResultPtr, ResultIndex, "sunkaddr", - AddrMode.InBounds); + SunkAddr = Builder.CreatePtrAdd(ResultPtr, ResultIndex, "sunkaddr", + AddrMode.InBounds); } if (SunkAddr->getType() != Addr->getType()) { @@ -6014,7 +6013,9 @@ bool CodeGenPrepare::tryToPromoteExts( // cut this search path, because it means we degrade the code quality. // With exactly 2, the transformation is neutral, because we will merge // one extension but leave one. However, we optimistically keep going, - // because the new extension may be removed too. + // because the new extension may be removed too. Also avoid replacing a + // single free extension with multiple extensions, as this increases the + // number of IR instructions while not providing any savings. long long TotalCreatedInstsCost = CreatedInstsCost + NewCreatedInstsCost; // FIXME: It would be possible to propagate a negative value instead of // conservatively ceiling it to 0. @@ -6022,7 +6023,8 @@ bool CodeGenPrepare::tryToPromoteExts( std::max((long long)0, (TotalCreatedInstsCost - ExtCost)); if (!StressExtLdPromotion && (TotalCreatedInstsCost > 1 || - !isPromotedInstructionLegal(*TLI, *DL, PromotedVal))) { + !isPromotedInstructionLegal(*TLI, *DL, PromotedVal) || + (ExtCost == 0 && NewExts.size() > 1))) { // This promotion is not profitable, rollback to the previous state, and // save the current extension in ProfitablyMovedExts as the latest // speculative promotion turned out to be unprofitable. @@ -6169,7 +6171,6 @@ bool CodeGenPrepare::splitLargeGEPOffsets() { Type *PtrIdxTy = DL->getIndexType(GEP->getType()); Type *I8PtrTy = PointerType::get(Ctx, GEP->getType()->getPointerAddressSpace()); - Type *I8Ty = Type::getInt8Ty(Ctx); BasicBlock::iterator NewBaseInsertPt; BasicBlock *NewBaseInsertBB; @@ -6198,7 +6199,7 @@ bool CodeGenPrepare::splitLargeGEPOffsets() { if (NewBaseGEP->getType() != I8PtrTy) NewBaseGEP = NewBaseBuilder.CreatePointerCast(NewBaseGEP, I8PtrTy); NewBaseGEP = - NewBaseBuilder.CreateGEP(I8Ty, NewBaseGEP, BaseIndex, "splitgep"); + NewBaseBuilder.CreatePtrAdd(NewBaseGEP, BaseIndex, "splitgep"); NewGEPBases.insert(NewBaseGEP); return; }; @@ -6235,9 +6236,7 @@ bool CodeGenPrepare::splitLargeGEPOffsets() { } // Generate a new GEP to replace the current one. - LLVMContext &Ctx = GEP->getContext(); Type *PtrIdxTy = DL->getIndexType(GEP->getType()); - Type *I8Ty = Type::getInt8Ty(Ctx); if (!NewBaseGEP) { // Create a new base if we don't have one yet. Find the insertion @@ -6250,7 +6249,7 @@ bool CodeGenPrepare::splitLargeGEPOffsets() { if (Offset != BaseOffset) { // Calculate the new offset for the new GEP. Value *Index = ConstantInt::get(PtrIdxTy, Offset - BaseOffset); - NewGEP = Builder.CreateGEP(I8Ty, NewBaseGEP, Index); + NewGEP = Builder.CreatePtrAdd(NewBaseGEP, Index); } replaceAllUsesWith(GEP, NewGEP, FreshBBs, IsHugeFunc); LargeOffsetGEPID.erase(GEP); diff --git a/llvm/lib/CodeGen/CommandFlags.cpp b/llvm/lib/CodeGen/CommandFlags.cpp index c6d7827f36d..51406fb287e 100644 --- a/llvm/lib/CodeGen/CommandFlags.cpp +++ b/llvm/lib/CodeGen/CommandFlags.cpp @@ -93,6 +93,7 @@ CGOPT(bool, XCOFFTracebackTable) CGOPT(std::string, BBSections) CGOPT(unsigned, TLSSize) CGOPT_EXP(bool, EmulatedTLS) +CGOPT_EXP(bool, EnableTLSDESC) CGOPT(bool, UniqueSectionNames) CGOPT(bool, UniqueBasicBlockSectionNames) CGOPT(EABI, EABIVersion) @@ -404,6 +405,11 @@ codegen::RegisterCodeGenFlags::RegisterCodeGenFlags() { "emulated-tls", cl::desc("Use emulated TLS model"), cl::init(false)); CGBINDOPT(EmulatedTLS); + static cl::opt EnableTLSDESC( + "enable-tlsdesc", cl::desc("Enable the use of TLS Descriptors"), + cl::init(false)); + CGBINDOPT(EnableTLSDESC); + static cl::opt UniqueSectionNames( "unique-section-names", cl::desc("Give unique names to every section"), cl::init(true)); @@ -568,6 +574,8 @@ codegen::InitTargetOptionsFromCodeGenFlags(const Triple &TheTriple) { Options.TLSSize = getTLSSize(); Options.EmulatedTLS = getExplicitEmulatedTLS().value_or(TheTriple.hasDefaultEmulatedTLS()); + Options.EnableTLSDESC = + getExplicitEnableTLSDESC().value_or(TheTriple.hasDefaultTLSDESC()); Options.ExceptionModel = getExceptionModel(); Options.EmitStackSizeSection = getEnableStackSizeSection(); Options.EnableMachineFunctionSplitter = getEnableMachineFunctionSplitter(); diff --git a/llvm/lib/CodeGen/ExpandVectorPredication.cpp b/llvm/lib/CodeGen/ExpandVectorPredication.cpp index 6c873a9aee2..0fe4cfefdb1 100644 --- a/llvm/lib/CodeGen/ExpandVectorPredication.cpp +++ b/llvm/lib/CodeGen/ExpandVectorPredication.cpp @@ -729,6 +729,8 @@ Value *CachingVPExpander::expandPredication(VPIntrinsic &VPI) { case Intrinsic::vp_sqrt: case Intrinsic::vp_maxnum: case Intrinsic::vp_minnum: + case Intrinsic::vp_maximum: + case Intrinsic::vp_minimum: return expandPredicationToFPCall(Builder, VPI, VPI.getFunctionalIntrinsicID().value()); case Intrinsic::vp_load: diff --git a/llvm/lib/CodeGen/GlobalISel/CallLowering.cpp b/llvm/lib/CodeGen/GlobalISel/CallLowering.cpp index 6858e030c2c..ccd9b13d730 100644 --- a/llvm/lib/CodeGen/GlobalISel/CallLowering.cpp +++ b/llvm/lib/CodeGen/GlobalISel/CallLowering.cpp @@ -478,9 +478,43 @@ static void buildCopyFromRegs(MachineIRBuilder &B, ArrayRef OrigRegs, } else { // Vector was split, and elements promoted to a wider type. // FIXME: Should handle floating point promotions. - LLT BVType = LLT::fixed_vector(LLTy.getNumElements(), PartLLT); - auto BV = B.buildBuildVector(BVType, Regs); - B.buildTrunc(OrigRegs[0], BV); + unsigned NumElts = LLTy.getNumElements(); + LLT BVType = LLT::fixed_vector(NumElts, PartLLT); + + Register BuildVec; + if (NumElts == Regs.size()) + BuildVec = B.buildBuildVector(BVType, Regs).getReg(0); + else { + // Vector elements are packed in the inputs. + // e.g. we have a <4 x s16> but 2 x s32 in regs. + assert(NumElts > Regs.size()); + LLT SrcEltTy = MRI.getType(Regs[0]); + + LLT OriginalEltTy = MRI.getType(OrigRegs[0]).getElementType(); + + // Input registers contain packed elements. + // Determine how many elements per reg. + assert((SrcEltTy.getSizeInBits() % OriginalEltTy.getSizeInBits()) == 0); + unsigned EltPerReg = + (SrcEltTy.getSizeInBits() / OriginalEltTy.getSizeInBits()); + + SmallVector BVRegs; + BVRegs.reserve(Regs.size() * EltPerReg); + for (Register R : Regs) { + auto Unmerge = B.buildUnmerge(OriginalEltTy, R); + for (unsigned K = 0; K < EltPerReg; ++K) + BVRegs.push_back(B.buildAnyExt(PartLLT, Unmerge.getReg(K)).getReg(0)); + } + + // We may have some more elements in BVRegs, e.g. if we have 2 s32 pieces + // for a <3 x s16> vector. We should have less than EltPerReg extra items. + if (BVRegs.size() > NumElts) { + assert((BVRegs.size() - NumElts) < EltPerReg); + BVRegs.truncate(NumElts); + } + BuildVec = B.buildBuildVector(BVType, BVRegs).getReg(0); + } + B.buildTrunc(OrigRegs[0], BuildVec); } } @@ -694,7 +728,7 @@ bool CallLowering::handleAssignments(ValueHandler &Handler, DelayedOutgoingRegAssignments.emplace_back(Thunk); if (!NumArgRegs) return false; - j += NumArgRegs; + j += (NumArgRegs - 1); continue; } diff --git a/llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp b/llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp index fc2793bd7a1..772229215e7 100644 --- a/llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp +++ b/llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp @@ -2374,6 +2374,9 @@ bool CombinerHelper::matchCombineAnyExtTrunc(MachineInstr &MI, Register &Reg) { assert(MI.getOpcode() == TargetOpcode::G_ANYEXT && "Expected a G_ANYEXT"); Register DstReg = MI.getOperand(0).getReg(); Register SrcReg = MI.getOperand(1).getReg(); + Register OriginalSrcReg = getSrcRegIgnoringCopies(SrcReg, MRI); + if (OriginalSrcReg.isValid()) + SrcReg = OriginalSrcReg; LLT DstTy = MRI.getType(DstReg); return mi_match(SrcReg, MRI, m_GTrunc(m_all_of(m_Reg(Reg), m_SpecificType(DstTy)))); @@ -2400,6 +2403,9 @@ bool CombinerHelper::matchCombineExtOfExt( MI.getOpcode() == TargetOpcode::G_ZEXT) && "Expected a G_[ASZ]EXT"); Register SrcReg = MI.getOperand(1).getReg(); + Register OriginalSrcReg = getSrcRegIgnoringCopies(SrcReg, MRI); + if (OriginalSrcReg.isValid()) + SrcReg = OriginalSrcReg; MachineInstr *SrcMI = MRI.getVRegDef(SrcReg); // Match exts with the same opcode, anyext([sz]ext) and sext(zext). unsigned Opc = MI.getOpcode(); @@ -3874,9 +3880,8 @@ bool CombinerHelper::matchLoadOrCombine( bool CombinerHelper::matchExtendThroughPhis(MachineInstr &MI, MachineInstr *&ExtMI) { - assert(MI.getOpcode() == TargetOpcode::G_PHI); - - Register DstReg = MI.getOperand(0).getReg(); + auto &PHI = cast(MI); + Register DstReg = PHI.getReg(0); // TODO: Extending a vector may be expensive, don't do this until heuristics // are better. @@ -3905,8 +3910,8 @@ bool CombinerHelper::matchExtendThroughPhis(MachineInstr &MI, // they'll be optimized in some way. // Collect the unique incoming values. SmallPtrSet InSrcs; - for (unsigned Idx = 1; Idx < MI.getNumOperands(); Idx += 2) { - auto *DefMI = getDefIgnoringCopies(MI.getOperand(Idx).getReg(), MRI); + for (unsigned I = 0; I < PHI.getNumIncomingValues(); ++I) { + auto *DefMI = getDefIgnoringCopies(PHI.getIncomingValue(I), MRI); switch (DefMI->getOpcode()) { case TargetOpcode::G_LOAD: case TargetOpcode::G_TRUNC: @@ -3914,7 +3919,7 @@ bool CombinerHelper::matchExtendThroughPhis(MachineInstr &MI, case TargetOpcode::G_ZEXT: case TargetOpcode::G_ANYEXT: case TargetOpcode::G_CONSTANT: - InSrcs.insert(getDefIgnoringCopies(MI.getOperand(Idx).getReg(), MRI)); + InSrcs.insert(DefMI); // Don't try to propagate if there are too many places to create new // extends, chances are it'll increase code size. if (InSrcs.size() > 2) @@ -3929,7 +3934,7 @@ bool CombinerHelper::matchExtendThroughPhis(MachineInstr &MI, void CombinerHelper::applyExtendThroughPhis(MachineInstr &MI, MachineInstr *&ExtMI) { - assert(MI.getOpcode() == TargetOpcode::G_PHI); + auto &PHI = cast(MI); Register DstReg = ExtMI->getOperand(0).getReg(); LLT ExtTy = MRI.getType(DstReg); @@ -3938,8 +3943,9 @@ void CombinerHelper::applyExtendThroughPhis(MachineInstr &MI, // deterministic iteration order. SmallSetVector SrcMIs; SmallDenseMap OldToNewSrcMap; - for (unsigned SrcIdx = 1; SrcIdx < MI.getNumOperands(); SrcIdx += 2) { - auto *SrcMI = MRI.getVRegDef(MI.getOperand(SrcIdx).getReg()); + for (unsigned I = 0; I < PHI.getNumIncomingValues(); ++I) { + auto SrcReg = PHI.getIncomingValue(I); + auto *SrcMI = MRI.getVRegDef(SrcReg); if (!SrcMIs.insert(SrcMI)) continue; @@ -3951,8 +3957,7 @@ void CombinerHelper::applyExtendThroughPhis(MachineInstr &MI, Builder.setInsertPt(*SrcMI->getParent(), InsertPt); Builder.setDebugLoc(MI.getDebugLoc()); - auto NewExt = Builder.buildExtOrTrunc(ExtMI->getOpcode(), ExtTy, - SrcMI->getOperand(0).getReg()); + auto NewExt = Builder.buildExtOrTrunc(ExtMI->getOpcode(), ExtTy, SrcReg); OldToNewSrcMap[SrcMI] = NewExt; } @@ -6556,6 +6561,9 @@ bool CombinerHelper::tryFoldSelectToIntMinMax(GSelect *Select, Register False = Select->getFalseReg(); LLT DstTy = MRI.getType(DstReg); + if (DstTy.isPointer()) + return false; + // We need an G_ICMP on the condition register. GICmp *Cmp = getOpcodeDef(Cond, MRI); if (!Cmp) diff --git a/llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp b/llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp index 8a6bfdc5ee6..1a71c1232c7 100644 --- a/llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp +++ b/llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp @@ -162,7 +162,8 @@ public: // they could have originated from constants, and we don't want a jumpy // debug experience. assert((CurrInst->getDebugLoc() == MI.getDebugLoc() || - (MI.getParent()->isEntryBlock() && !MI.getDebugLoc())) && + (MI.getParent()->isEntryBlock() && !MI.getDebugLoc()) || + (MI.isDebugInstr())) && "Line info was not transferred to all instructions"); } }; @@ -2006,47 +2007,35 @@ std::optional IRTranslator::getArgPhysReg(Argument &Arg) { return VRegDef->getOperand(1).getReg().asMCReg(); } -bool IRTranslator::translateIfEntryValueArgument(const DbgValueInst &DebugInst, +bool IRTranslator::translateIfEntryValueArgument(bool isDeclare, Value *Val, + const DILocalVariable *Var, + const DIExpression *Expr, + const DebugLoc &DL, MachineIRBuilder &MIRBuilder) { - auto *Arg = dyn_cast(DebugInst.getValue()); + auto *Arg = dyn_cast(Val); if (!Arg) return false; - const DIExpression *Expr = DebugInst.getExpression(); if (!Expr->isEntryValue()) return false; std::optional PhysReg = getArgPhysReg(*Arg); if (!PhysReg) { - LLVM_DEBUG(dbgs() << "Dropping dbg.value: expression is entry_value but " - "couldn't find a physical register\n" - << DebugInst << "\n"); + LLVM_DEBUG(dbgs() << "Dropping dbg." << (isDeclare ? "declare" : "value") + << ": expression is entry_value but " + << "couldn't find a physical register\n"); + LLVM_DEBUG(dbgs() << *Var << "\n"); return true; } - MIRBuilder.buildDirectDbgValue(*PhysReg, DebugInst.getVariable(), - DebugInst.getExpression()); - return true; -} + if (isDeclare) { + // Append an op deref to account for the fact that this is a dbg_declare. + Expr = DIExpression::append(Expr, dwarf::DW_OP_deref); + MF->setVariableDbgInfo(Var, Expr, *PhysReg, DL); + } else { + MIRBuilder.buildDirectDbgValue(*PhysReg, Var, Expr); + } -bool IRTranslator::translateIfEntryValueArgument( - const DbgDeclareInst &DebugInst) { - auto *Arg = dyn_cast(DebugInst.getAddress()); - if (!Arg) - return false; - - const DIExpression *Expr = DebugInst.getExpression(); - if (!Expr->isEntryValue()) - return false; - - std::optional PhysReg = getArgPhysReg(*Arg); - if (!PhysReg) - return false; - - // Append an op deref to account for the fact that this is a dbg_declare. - Expr = DIExpression::append(Expr, dwarf::DW_OP_deref); - MF->setVariableDbgInfo(DebugInst.getVariable(), Expr, *PhysReg, - DebugInst.getDebugLoc()); return true; } @@ -2100,32 +2089,8 @@ bool IRTranslator::translateKnownIntrinsic(const CallInst &CI, Intrinsic::ID ID, case Intrinsic::dbg_declare: { const DbgDeclareInst &DI = cast(CI); assert(DI.getVariable() && "Missing variable"); - - const Value *Address = DI.getAddress(); - if (!Address || isa(Address)) { - LLVM_DEBUG(dbgs() << "Dropping debug info for " << DI << "\n"); - return true; - } - - assert(DI.getVariable()->isValidLocationForIntrinsic( - MIRBuilder.getDebugLoc()) && - "Expected inlined-at fields to agree"); - auto AI = dyn_cast(Address); - if (AI && AI->isStaticAlloca()) { - // Static allocas are tracked at the MF level, no need for DBG_VALUE - // instructions (in fact, they get ignored if they *do* exist). - MF->setVariableDbgInfo(DI.getVariable(), DI.getExpression(), - getOrCreateFrameIndex(*AI), DI.getDebugLoc()); - return true; - } - - if (translateIfEntryValueArgument(DI)) - return true; - - // A dbg.declare describes the address of a source variable, so lower it - // into an indirect DBG_VALUE. - MIRBuilder.buildIndirectDbgValue(getOrCreateVReg(*Address), - DI.getVariable(), DI.getExpression()); + translateDbgDeclareRecord(DI.getAddress(), DI.hasArgList(), DI.getVariable(), + DI.getExpression(), DI.getDebugLoc(), MIRBuilder); return true; } case Intrinsic::dbg_label: { @@ -2158,41 +2123,8 @@ bool IRTranslator::translateKnownIntrinsic(const CallInst &CI, Intrinsic::ID ID, case Intrinsic::dbg_value: { // This form of DBG_VALUE is target-independent. const DbgValueInst &DI = cast(CI); - const Value *V = DI.getValue(); - assert(DI.getVariable()->isValidLocationForIntrinsic( - MIRBuilder.getDebugLoc()) && - "Expected inlined-at fields to agree"); - if (!V || DI.hasArgList()) { - // DI cannot produce a valid DBG_VALUE, so produce an undef DBG_VALUE to - // terminate any prior location. - MIRBuilder.buildIndirectDbgValue(0, DI.getVariable(), DI.getExpression()); - return true; - } - if (const auto *CI = dyn_cast(V)) { - MIRBuilder.buildConstDbgValue(*CI, DI.getVariable(), DI.getExpression()); - return true; - } - if (auto *AI = dyn_cast(V); - AI && AI->isStaticAlloca() && DI.getExpression()->startsWithDeref()) { - // If the value is an alloca and the expression starts with a - // dereference, track a stack slot instead of a register, as registers - // may be clobbered. - auto ExprOperands = DI.getExpression()->getElements(); - auto *ExprDerefRemoved = - DIExpression::get(AI->getContext(), ExprOperands.drop_front()); - MIRBuilder.buildFIDbgValue(getOrCreateFrameIndex(*AI), DI.getVariable(), - ExprDerefRemoved); - return true; - } - if (translateIfEntryValueArgument(DI, MIRBuilder)) - return true; - for (Register Reg : getOrCreateVRegs(*V)) { - // FIXME: This does not handle register-indirect values at offset 0. The - // direct/indirect thing shouldn't really be handled by something as - // implicit as reg+noreg vs reg+imm in the first place, but it seems - // pretty baked in right now. - MIRBuilder.buildDirectDbgValue(Reg, DI.getVariable(), DI.getExpression()); - } + translateDbgValueRecord(DI.getValue(), DI.hasArgList(), DI.getVariable(), + DI.getExpression(), DI.getDebugLoc(), MIRBuilder); return true; } case Intrinsic::uadd_with_overflow: @@ -3223,6 +3155,8 @@ void IRTranslator::finishPendingPhis() { #endif // ifndef NDEBUG for (auto &Phi : PendingPHIs) { const PHINode *PI = Phi.first; + if (PI->getType()->isEmptyTy()) + continue; ArrayRef ComponentPHIs = Phi.second; MachineBasicBlock *PhiMBB = ComponentPHIs[0]->getParent(); EntryBuilder->setDebugLoc(PI->getDebugLoc()); @@ -3248,6 +3182,102 @@ void IRTranslator::finishPendingPhis() { } } +void IRTranslator::translateDbgValueRecord(Value *V, bool HasArgList, + const DILocalVariable *Variable, + const DIExpression *Expression, + const DebugLoc &DL, + MachineIRBuilder &MIRBuilder) { + assert(Variable->isValidLocationForIntrinsic(DL) && + "Expected inlined-at fields to agree"); + // Act as if we're handling a debug intrinsic. + MIRBuilder.setDebugLoc(DL); + + if (!V || HasArgList) { + // DI cannot produce a valid DBG_VALUE, so produce an undef DBG_VALUE to + // terminate any prior location. + MIRBuilder.buildIndirectDbgValue(0, Variable, Expression); + return; + } + + if (const auto *CI = dyn_cast(V)) { + MIRBuilder.buildConstDbgValue(*CI, Variable, Expression); + return; + } + + if (auto *AI = dyn_cast(V); + AI && AI->isStaticAlloca() && Expression->startsWithDeref()) { + // If the value is an alloca and the expression starts with a + // dereference, track a stack slot instead of a register, as registers + // may be clobbered. + auto ExprOperands = Expression->getElements(); + auto *ExprDerefRemoved = + DIExpression::get(AI->getContext(), ExprOperands.drop_front()); + MIRBuilder.buildFIDbgValue(getOrCreateFrameIndex(*AI), Variable, + ExprDerefRemoved); + return; + } + if (translateIfEntryValueArgument(false, V, Variable, Expression, DL, + MIRBuilder)) + return; + for (Register Reg : getOrCreateVRegs(*V)) { + // FIXME: This does not handle register-indirect values at offset 0. The + // direct/indirect thing shouldn't really be handled by something as + // implicit as reg+noreg vs reg+imm in the first place, but it seems + // pretty baked in right now. + MIRBuilder.buildDirectDbgValue(Reg, Variable, Expression); + } + return; +} + +void IRTranslator::translateDbgDeclareRecord(Value *Address, bool HasArgList, + const DILocalVariable *Variable, + const DIExpression *Expression, + const DebugLoc &DL, + MachineIRBuilder &MIRBuilder) { + if (!Address || isa(Address)) { + LLVM_DEBUG(dbgs() << "Dropping debug info for " << *Variable << "\n"); + return; + } + + assert(Variable->isValidLocationForIntrinsic(DL) && + "Expected inlined-at fields to agree"); + auto AI = dyn_cast(Address); + if (AI && AI->isStaticAlloca()) { + // Static allocas are tracked at the MF level, no need for DBG_VALUE + // instructions (in fact, they get ignored if they *do* exist). + MF->setVariableDbgInfo(Variable, Expression, + getOrCreateFrameIndex(*AI), DL); + return; + } + + if (translateIfEntryValueArgument(true, Address, Variable, + Expression, DL, + MIRBuilder)) + return; + + // A dbg.declare describes the address of a source variable, so lower it + // into an indirect DBG_VALUE. + MIRBuilder.setDebugLoc(DL); + MIRBuilder.buildIndirectDbgValue(getOrCreateVReg(*Address), + Variable, Expression); + return; +} + +void IRTranslator::translateDbgInfo(const Instruction &Inst, + MachineIRBuilder &MIRBuilder) { + for (DPValue &DPV : Inst.getDbgValueRange()) { + const DILocalVariable *Variable = DPV.getVariable(); + const DIExpression *Expression = DPV.getExpression(); + Value *V = DPV.getVariableLocationOp(0); + if (DPV.isDbgDeclare()) + translateDbgDeclareRecord(V, DPV.hasArgList(), Variable, + Expression, DPV.getDebugLoc(), MIRBuilder); + else + translateDbgValueRecord(V, DPV.hasArgList(), Variable, + Expression, DPV.getDebugLoc(), MIRBuilder); + } +} + bool IRTranslator::translate(const Instruction &Inst) { CurBuilder->setDebugLoc(Inst.getDebugLoc()); CurBuilder->setPCSections(Inst.getMetadata(LLVMContext::MD_pcsections)); @@ -3758,6 +3788,10 @@ bool IRTranslator::runOnMachineFunction(MachineFunction &CurMF) { #ifndef NDEBUG Verifier.setCurrentInst(&Inst); #endif // ifndef NDEBUG + + // Translate any debug-info attached to the instruction. + translateDbgInfo(Inst, *CurBuilder.get()); + if (translate(Inst)) continue; diff --git a/llvm/lib/CodeGen/GlobalISel/InstructionSelect.cpp b/llvm/lib/CodeGen/GlobalISel/InstructionSelect.cpp index baea773cf52..30b2430249d 100644 --- a/llvm/lib/CodeGen/GlobalISel/InstructionSelect.cpp +++ b/llvm/lib/CodeGen/GlobalISel/InstructionSelect.cpp @@ -31,12 +31,16 @@ #include "llvm/Support/CodeGenCoverage.h" #include "llvm/Support/CommandLine.h" #include "llvm/Support/Debug.h" +#include "llvm/Support/DebugCounter.h" #include "llvm/Target/TargetMachine.h" #define DEBUG_TYPE "instruction-select" using namespace llvm; +DEBUG_COUNTER(GlobalISelCounter, "globalisel", + "Controls whether to select function with GlobalISel"); + #ifdef LLVM_GISEL_COV_PREFIX static cl::opt CoveragePrefix("gisel-coverage-prefix", cl::init(LLVM_GISEL_COV_PREFIX), @@ -294,6 +298,13 @@ bool InstructionSelect::runOnMachineFunction(MachineFunction &MF) { return false; } #endif + + if (!DebugCounter::shouldExecute(GlobalISelCounter)) { + dbgs() << "Falling back for function " << MF.getName() << "\n"; + MF.getProperties().set(MachineFunctionProperties::Property::FailedISel); + return false; + } + // Determine if there are any calls in this machine function. Ported from // SelectionDAG. MachineFrameInfo &MFI = MF.getFrameInfo(); diff --git a/llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp b/llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp index 21947a55874..3b2cf319109 100644 --- a/llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp +++ b/llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp @@ -158,100 +158,6 @@ LegalizerHelper::legalizeInstrStep(MachineInstr &MI, } } -void LegalizerHelper::extractParts(Register Reg, LLT Ty, int NumParts, - SmallVectorImpl &VRegs) { - for (int i = 0; i < NumParts; ++i) - VRegs.push_back(MRI.createGenericVirtualRegister(Ty)); - MIRBuilder.buildUnmerge(VRegs, Reg); -} - -bool LegalizerHelper::extractParts(Register Reg, LLT RegTy, - LLT MainTy, LLT &LeftoverTy, - SmallVectorImpl &VRegs, - SmallVectorImpl &LeftoverRegs) { - assert(!LeftoverTy.isValid() && "this is an out argument"); - - unsigned RegSize = RegTy.getSizeInBits(); - unsigned MainSize = MainTy.getSizeInBits(); - unsigned NumParts = RegSize / MainSize; - unsigned LeftoverSize = RegSize - NumParts * MainSize; - - // Use an unmerge when possible. - if (LeftoverSize == 0) { - for (unsigned I = 0; I < NumParts; ++I) - VRegs.push_back(MRI.createGenericVirtualRegister(MainTy)); - MIRBuilder.buildUnmerge(VRegs, Reg); - return true; - } - - // Perform irregular split. Leftover is last element of RegPieces. - if (MainTy.isVector()) { - SmallVector RegPieces; - extractVectorParts(Reg, MainTy.getNumElements(), RegPieces); - for (unsigned i = 0; i < RegPieces.size() - 1; ++i) - VRegs.push_back(RegPieces[i]); - LeftoverRegs.push_back(RegPieces[RegPieces.size() - 1]); - LeftoverTy = MRI.getType(LeftoverRegs[0]); - return true; - } - - LeftoverTy = LLT::scalar(LeftoverSize); - // For irregular sizes, extract the individual parts. - for (unsigned I = 0; I != NumParts; ++I) { - Register NewReg = MRI.createGenericVirtualRegister(MainTy); - VRegs.push_back(NewReg); - MIRBuilder.buildExtract(NewReg, Reg, MainSize * I); - } - - for (unsigned Offset = MainSize * NumParts; Offset < RegSize; - Offset += LeftoverSize) { - Register NewReg = MRI.createGenericVirtualRegister(LeftoverTy); - LeftoverRegs.push_back(NewReg); - MIRBuilder.buildExtract(NewReg, Reg, Offset); - } - - return true; -} - -void LegalizerHelper::extractVectorParts(Register Reg, unsigned NumElts, - SmallVectorImpl &VRegs) { - LLT RegTy = MRI.getType(Reg); - assert(RegTy.isVector() && "Expected a vector type"); - - LLT EltTy = RegTy.getElementType(); - LLT NarrowTy = (NumElts == 1) ? EltTy : LLT::fixed_vector(NumElts, EltTy); - unsigned RegNumElts = RegTy.getNumElements(); - unsigned LeftoverNumElts = RegNumElts % NumElts; - unsigned NumNarrowTyPieces = RegNumElts / NumElts; - - // Perfect split without leftover - if (LeftoverNumElts == 0) - return extractParts(Reg, NarrowTy, NumNarrowTyPieces, VRegs); - - // Irregular split. Provide direct access to all elements for artifact - // combiner using unmerge to elements. Then build vectors with NumElts - // elements. Remaining element(s) will be (used to build vector) Leftover. - SmallVector Elts; - extractParts(Reg, EltTy, RegNumElts, Elts); - - unsigned Offset = 0; - // Requested sub-vectors of NarrowTy. - for (unsigned i = 0; i < NumNarrowTyPieces; ++i, Offset += NumElts) { - ArrayRef Pieces(&Elts[Offset], NumElts); - VRegs.push_back(MIRBuilder.buildMergeLikeInstr(NarrowTy, Pieces).getReg(0)); - } - - // Leftover element(s). - if (LeftoverNumElts == 1) { - VRegs.push_back(Elts[Offset]); - } else { - LLT LeftoverTy = LLT::fixed_vector(LeftoverNumElts, EltTy); - ArrayRef Pieces(&Elts[Offset], LeftoverNumElts); - VRegs.push_back( - MIRBuilder.buildMergeLikeInstr(LeftoverTy, Pieces).getReg(0)); - } -} - void LegalizerHelper::insertParts(Register DstReg, LLT ResultTy, LLT PartTy, ArrayRef PartRegs, @@ -293,7 +199,8 @@ void LegalizerHelper::appendVectorElts(SmallVectorImpl &Elts, Register Reg) { LLT Ty = MRI.getType(Reg); SmallVector RegElts; - extractParts(Reg, Ty.getScalarType(), Ty.getNumElements(), RegElts); + extractParts(Reg, Ty.getScalarType(), Ty.getNumElements(), RegElts, + MIRBuilder, MRI); Elts.append(RegElts); } @@ -1542,7 +1449,7 @@ LegalizerHelper::LegalizeResult LegalizerHelper::narrowScalar(MachineInstr &MI, MachineBasicBlock &OpMBB = *MI.getOperand(i + 1).getMBB(); MIRBuilder.setInsertPt(OpMBB, OpMBB.getFirstTerminatorForward()); extractParts(MI.getOperand(i).getReg(), NarrowTy, NumParts, - SrcRegs[i / 2]); + SrcRegs[i / 2], MIRBuilder, MRI); } MachineBasicBlock &MBB = *MI.getParent(); MIRBuilder.setInsertPt(MBB, MI); @@ -1584,13 +1491,13 @@ LegalizerHelper::LegalizeResult LegalizerHelper::narrowScalar(MachineInstr &MI, LLT LeftoverTy; // Example: s88 -> s64 (NarrowTy) + s24 (leftover) SmallVector LHSPartRegs, LHSLeftoverRegs; if (!extractParts(LHS, SrcTy, NarrowTy, LeftoverTy, LHSPartRegs, - LHSLeftoverRegs)) + LHSLeftoverRegs, MIRBuilder, MRI)) return UnableToLegalize; LLT Unused; // Matches LeftoverTy; G_ICMP LHS and RHS are the same type. SmallVector RHSPartRegs, RHSLeftoverRegs; if (!extractParts(MI.getOperand(3).getReg(), SrcTy, NarrowTy, Unused, - RHSPartRegs, RHSLeftoverRegs)) + RHSPartRegs, RHSLeftoverRegs, MIRBuilder, MRI)) return UnableToLegalize; // We now have the LHS and RHS of the compare split into narrow-type @@ -1744,7 +1651,8 @@ LegalizerHelper::LegalizeResult LegalizerHelper::narrowScalar(MachineInstr &MI, Observer.changingInstr(MI); SmallVector SrcRegs, DstRegs; unsigned NumParts = SizeOp0 / NarrowSize; - extractParts(MI.getOperand(1).getReg(), NarrowTy, NumParts, SrcRegs); + extractParts(MI.getOperand(1).getReg(), NarrowTy, NumParts, SrcRegs, + MIRBuilder, MRI); for (unsigned i = 0; i < NumParts; ++i) { auto DstPart = MIRBuilder.buildInstr(MI.getOpcode(), {NarrowTy}, @@ -4194,7 +4102,8 @@ LegalizerHelper::fewerElementsVectorMultiEltType( MI.getOperand(UseIdx)); } else { SmallVector SplitPieces; - extractVectorParts(MI.getReg(UseIdx), NumElts, SplitPieces); + extractVectorParts(MI.getReg(UseIdx), NumElts, SplitPieces, MIRBuilder, + MRI); for (auto Reg : SplitPieces) InputOpsPieces[UseNo].push_back(Reg); } @@ -4250,7 +4159,8 @@ LegalizerHelper::fewerElementsVectorPhi(GenericMachineInstr &MI, UseIdx += 2, ++UseNo) { MachineBasicBlock &OpMBB = *MI.getOperand(UseIdx + 1).getMBB(); MIRBuilder.setInsertPt(OpMBB, OpMBB.getFirstTerminatorForward()); - extractVectorParts(MI.getReg(UseIdx), NumElts, InputOpsPieces[UseNo]); + extractVectorParts(MI.getReg(UseIdx), NumElts, InputOpsPieces[UseNo], + MIRBuilder, MRI); } // Build PHIs with fewer elements. @@ -4519,7 +4429,7 @@ LegalizerHelper::reduceLoadStoreWidth(GLoadStore &LdStMI, unsigned TypeIdx, std::tie(NumParts, NumLeftover) = getNarrowTypeBreakDown(ValTy, NarrowTy, LeftoverTy); } else { if (extractParts(ValReg, ValTy, NarrowTy, LeftoverTy, NarrowRegs, - NarrowLeftoverRegs)) { + NarrowLeftoverRegs, MIRBuilder, MRI)) { NumParts = NarrowRegs.size(); NumLeftover = NarrowLeftoverRegs.size(); } @@ -4765,8 +4675,8 @@ LegalizerHelper::LegalizeResult LegalizerHelper::fewerElementsVectorShuffle( unsigned NewElts = NarrowTy.getNumElements(); SmallVector SplitSrc1Regs, SplitSrc2Regs; - extractParts(Src1Reg, NarrowTy, 2, SplitSrc1Regs); - extractParts(Src2Reg, NarrowTy, 2, SplitSrc2Regs); + extractParts(Src1Reg, NarrowTy, 2, SplitSrc1Regs, MIRBuilder, MRI); + extractParts(Src2Reg, NarrowTy, 2, SplitSrc2Regs, MIRBuilder, MRI); Register Inputs[4] = {SplitSrc1Regs[0], SplitSrc1Regs[1], SplitSrc2Regs[0], SplitSrc2Regs[1]}; @@ -4900,7 +4810,7 @@ LegalizerHelper::LegalizeResult LegalizerHelper::fewerElementsVectorReductions( NarrowTy.isVector() ? SrcTy.getNumElements() / NarrowTy.getNumElements() : SrcTy.getNumElements(); - extractParts(SrcReg, NarrowTy, NumParts, SplitSrcs); + extractParts(SrcReg, NarrowTy, NumParts, SplitSrcs, MIRBuilder, MRI); if (NarrowTy.isScalar()) { if (DstTy != NarrowTy) return UnableToLegalize; // FIXME: handle implicit extensions. @@ -4983,7 +4893,7 @@ LegalizerHelper::fewerElementsVectorSeqReductions(MachineInstr &MI, SmallVector SplitSrcs; unsigned NumParts = SrcTy.getNumElements(); - extractParts(SrcReg, NarrowTy, NumParts, SplitSrcs); + extractParts(SrcReg, NarrowTy, NumParts, SplitSrcs, MIRBuilder, MRI); Register Acc = ScalarReg; for (unsigned i = 0; i < NumParts; i++) Acc = MIRBuilder.buildInstr(ScalarOpc, {NarrowTy}, {Acc, SplitSrcs[i]}) @@ -5001,7 +4911,8 @@ LegalizerHelper::tryNarrowPow2Reduction(MachineInstr &MI, Register SrcReg, SmallVector SplitSrcs; // Split the sources into NarrowTy size pieces. extractParts(SrcReg, NarrowTy, - SrcTy.getNumElements() / NarrowTy.getNumElements(), SplitSrcs); + SrcTy.getNumElements() / NarrowTy.getNumElements(), SplitSrcs, + MIRBuilder, MRI); // We're going to do a tree reduction using vector operations until we have // one NarrowTy size value left. while (SplitSrcs.size() > 1) { @@ -5287,7 +5198,10 @@ LegalizerHelper::moreElementsVector(MachineInstr &MI, unsigned TypeIdx, case TargetOpcode::G_FMAXIMUM: case TargetOpcode::G_STRICT_FADD: case TargetOpcode::G_STRICT_FSUB: - case TargetOpcode::G_STRICT_FMUL: { + case TargetOpcode::G_STRICT_FMUL: + case TargetOpcode::G_SHL: + case TargetOpcode::G_ASHR: + case TargetOpcode::G_LSHR: { Observer.changingInstr(MI); moreElementsVectorSrc(MI, MoreTy, 1); moreElementsVectorSrc(MI, MoreTy, 2); @@ -5403,6 +5317,17 @@ LegalizerHelper::moreElementsVector(MachineInstr &MI, unsigned TypeIdx, Observer.changedInstr(MI); return Legalized; } + case TargetOpcode::G_ICMP: { + // TODO: the symmetric MoreTy works for targets like, e.g. NEON. + // For targets, like e.g. MVE, the result is a predicated vector (i1). + // This will need some refactoring. + Observer.changingInstr(MI); + moreElementsVectorSrc(MI, MoreTy, 2); + moreElementsVectorSrc(MI, MoreTy, 3); + moreElementsVectorDst(MI, MoreTy, 0); + Observer.changedInstr(MI); + return Legalized; + } default: return UnableToLegalize; } @@ -5640,8 +5565,10 @@ LegalizerHelper::narrowScalarAddSub(MachineInstr &MI, unsigned TypeIdx, LLT RegTy = MRI.getType(MI.getOperand(0).getReg()); LLT LeftoverTy, DummyTy; SmallVector Src1Regs, Src2Regs, Src1Left, Src2Left, DstRegs; - extractParts(Src1, RegTy, NarrowTy, LeftoverTy, Src1Regs, Src1Left); - extractParts(Src2, RegTy, NarrowTy, DummyTy, Src2Regs, Src2Left); + extractParts(Src1, RegTy, NarrowTy, LeftoverTy, Src1Regs, Src1Left, + MIRBuilder, MRI); + extractParts(Src2, RegTy, NarrowTy, DummyTy, Src2Regs, Src2Left, MIRBuilder, + MRI); int NarrowParts = Src1Regs.size(); for (int I = 0, E = Src1Left.size(); I != E; ++I) { @@ -5699,8 +5626,8 @@ LegalizerHelper::narrowScalarMul(MachineInstr &MI, LLT NarrowTy) { SmallVector Src1Parts, Src2Parts; SmallVector DstTmpRegs(DstTmpParts); - extractParts(Src1, NarrowTy, NumParts, Src1Parts); - extractParts(Src2, NarrowTy, NumParts, Src2Parts); + extractParts(Src1, NarrowTy, NumParts, Src1Parts, MIRBuilder, MRI); + extractParts(Src2, NarrowTy, NumParts, Src2Parts, MIRBuilder, MRI); multiplyRegisters(DstTmpRegs, Src1Parts, Src2Parts, NarrowTy); // Take only high half of registers if this is high mul. @@ -5752,7 +5679,8 @@ LegalizerHelper::narrowScalarExtract(MachineInstr &MI, unsigned TypeIdx, SmallVector SrcRegs, DstRegs; SmallVector Indexes; - extractParts(MI.getOperand(1).getReg(), NarrowTy, NumParts, SrcRegs); + extractParts(MI.getOperand(1).getReg(), NarrowTy, NumParts, SrcRegs, + MIRBuilder, MRI); Register OpReg = MI.getOperand(0).getReg(); uint64_t OpStart = MI.getOperand(2).getImm(); @@ -5814,7 +5742,7 @@ LegalizerHelper::narrowScalarInsert(MachineInstr &MI, unsigned TypeIdx, LLT RegTy = MRI.getType(MI.getOperand(0).getReg()); LLT LeftoverTy; extractParts(MI.getOperand(1).getReg(), RegTy, NarrowTy, LeftoverTy, SrcRegs, - LeftoverRegs); + LeftoverRegs, MIRBuilder, MRI); for (Register Reg : LeftoverRegs) SrcRegs.push_back(Reg); @@ -5899,12 +5827,12 @@ LegalizerHelper::narrowScalarBasic(MachineInstr &MI, unsigned TypeIdx, SmallVector Src1Regs, Src1LeftoverRegs; LLT LeftoverTy; if (!extractParts(MI.getOperand(1).getReg(), DstTy, NarrowTy, LeftoverTy, - Src0Regs, Src0LeftoverRegs)) + Src0Regs, Src0LeftoverRegs, MIRBuilder, MRI)) return UnableToLegalize; LLT Unused; if (!extractParts(MI.getOperand(2).getReg(), DstTy, NarrowTy, Unused, - Src1Regs, Src1LeftoverRegs)) + Src1Regs, Src1LeftoverRegs, MIRBuilder, MRI)) llvm_unreachable("inconsistent extractParts result"); for (unsigned I = 0, E = Src1Regs.size(); I != E; ++I) { @@ -5967,12 +5895,12 @@ LegalizerHelper::narrowScalarSelect(MachineInstr &MI, unsigned TypeIdx, SmallVector Src2Regs, Src2LeftoverRegs; LLT LeftoverTy; if (!extractParts(MI.getOperand(2).getReg(), DstTy, NarrowTy, LeftoverTy, - Src1Regs, Src1LeftoverRegs)) + Src1Regs, Src1LeftoverRegs, MIRBuilder, MRI)) return UnableToLegalize; LLT Unused; if (!extractParts(MI.getOperand(3).getReg(), DstTy, NarrowTy, Unused, - Src2Regs, Src2LeftoverRegs)) + Src2Regs, Src2LeftoverRegs, MIRBuilder, MRI)) llvm_unreachable("inconsistent extractParts result"); for (unsigned I = 0, E = Src1Regs.size(); I != E; ++I) { @@ -6468,7 +6396,7 @@ LegalizerHelper::LegalizeResult LegalizerHelper::lowerTRUNC(MachineInstr &MI) { // First, split the source into two smaller vectors. SmallVector SplitSrcs; - extractParts(SrcReg, SplitSrcTy, 2, SplitSrcs); + extractParts(SrcReg, SplitSrcTy, 2, SplitSrcs, MIRBuilder, MRI); // Truncate the splits into intermediate narrower elements. LLT InterTy; @@ -7208,7 +7136,7 @@ LegalizerHelper::lowerExtractInsertVectorElt(MachineInstr &MI) { int64_t IdxVal; if (mi_match(Idx, MRI, m_ICst(IdxVal)) && IdxVal <= NumElts) { SmallVector SrcRegs; - extractParts(SrcVec, EltTy, NumElts, SrcRegs); + extractParts(SrcVec, EltTy, NumElts, SrcRegs, MIRBuilder, MRI); if (InsertVal) { SrcRegs[IdxVal] = MI.getOperand(2).getReg(); diff --git a/llvm/lib/CodeGen/GlobalISel/Utils.cpp b/llvm/lib/CodeGen/GlobalISel/Utils.cpp index eaf829f562b..aed826a9cbc 100644 --- a/llvm/lib/CodeGen/GlobalISel/Utils.cpp +++ b/llvm/lib/CodeGen/GlobalISel/Utils.cpp @@ -18,6 +18,7 @@ #include "llvm/CodeGen/GlobalISel/GenericMachineInstrs.h" #include "llvm/CodeGen/GlobalISel/LostDebugLocObserver.h" #include "llvm/CodeGen/GlobalISel/MIPatternMatch.h" +#include "llvm/CodeGen/GlobalISel/MachineIRBuilder.h" #include "llvm/CodeGen/MachineInstr.h" #include "llvm/CodeGen/MachineInstrBuilder.h" #include "llvm/CodeGen/MachineOptimizationRemarkEmitter.h" @@ -476,6 +477,152 @@ Register llvm::getSrcRegIgnoringCopies(Register Reg, return DefSrcReg ? DefSrcReg->Reg : Register(); } +void llvm::extractParts(Register Reg, LLT Ty, int NumParts, + SmallVectorImpl &VRegs, + MachineIRBuilder &MIRBuilder, + MachineRegisterInfo &MRI) { + for (int i = 0; i < NumParts; ++i) + VRegs.push_back(MRI.createGenericVirtualRegister(Ty)); + MIRBuilder.buildUnmerge(VRegs, Reg); +} + +bool llvm::extractParts(Register Reg, LLT RegTy, LLT MainTy, LLT &LeftoverTy, + SmallVectorImpl &VRegs, + SmallVectorImpl &LeftoverRegs, + MachineIRBuilder &MIRBuilder, + MachineRegisterInfo &MRI) { + assert(!LeftoverTy.isValid() && "this is an out argument"); + + unsigned RegSize = RegTy.getSizeInBits(); + unsigned MainSize = MainTy.getSizeInBits(); + unsigned NumParts = RegSize / MainSize; + unsigned LeftoverSize = RegSize - NumParts * MainSize; + + // Use an unmerge when possible. + if (LeftoverSize == 0) { + for (unsigned I = 0; I < NumParts; ++I) + VRegs.push_back(MRI.createGenericVirtualRegister(MainTy)); + MIRBuilder.buildUnmerge(VRegs, Reg); + return true; + } + + // Try to use unmerge for irregular vector split where possible + // For example when splitting a <6 x i32> into <4 x i32> with <2 x i32> + // leftover, it becomes: + // <2 x i32> %2, <2 x i32>%3, <2 x i32> %4 = G_UNMERGE_VALUE <6 x i32> %1 + // <4 x i32> %5 = G_CONCAT_VECTOR <2 x i32> %2, <2 x i32> %3 + if (RegTy.isVector() && MainTy.isVector()) { + unsigned RegNumElts = RegTy.getNumElements(); + unsigned MainNumElts = MainTy.getNumElements(); + unsigned LeftoverNumElts = RegNumElts % MainNumElts; + // If can unmerge to LeftoverTy, do it + if (MainNumElts % LeftoverNumElts == 0 && + RegNumElts % LeftoverNumElts == 0 && + RegTy.getScalarSizeInBits() == MainTy.getScalarSizeInBits() && + LeftoverNumElts > 1) { + LeftoverTy = + LLT::fixed_vector(LeftoverNumElts, RegTy.getScalarSizeInBits()); + + // Unmerge the SrcReg to LeftoverTy vectors + SmallVector UnmergeValues; + extractParts(Reg, LeftoverTy, RegNumElts / LeftoverNumElts, UnmergeValues, + MIRBuilder, MRI); + + // Find how many LeftoverTy makes one MainTy + unsigned LeftoverPerMain = MainNumElts / LeftoverNumElts; + unsigned NumOfLeftoverVal = + ((RegNumElts % MainNumElts) / LeftoverNumElts); + + // Create as many MainTy as possible using unmerged value + SmallVector MergeValues; + for (unsigned I = 0; I < UnmergeValues.size() - NumOfLeftoverVal; I++) { + MergeValues.push_back(UnmergeValues[I]); + if (MergeValues.size() == LeftoverPerMain) { + VRegs.push_back( + MIRBuilder.buildMergeLikeInstr(MainTy, MergeValues).getReg(0)); + MergeValues.clear(); + } + } + // Populate LeftoverRegs with the leftovers + for (unsigned I = UnmergeValues.size() - NumOfLeftoverVal; + I < UnmergeValues.size(); I++) { + LeftoverRegs.push_back(UnmergeValues[I]); + } + return true; + } + } + // Perform irregular split. Leftover is last element of RegPieces. + if (MainTy.isVector()) { + SmallVector RegPieces; + extractVectorParts(Reg, MainTy.getNumElements(), RegPieces, MIRBuilder, + MRI); + for (unsigned i = 0; i < RegPieces.size() - 1; ++i) + VRegs.push_back(RegPieces[i]); + LeftoverRegs.push_back(RegPieces[RegPieces.size() - 1]); + LeftoverTy = MRI.getType(LeftoverRegs[0]); + return true; + } + + LeftoverTy = LLT::scalar(LeftoverSize); + // For irregular sizes, extract the individual parts. + for (unsigned I = 0; I != NumParts; ++I) { + Register NewReg = MRI.createGenericVirtualRegister(MainTy); + VRegs.push_back(NewReg); + MIRBuilder.buildExtract(NewReg, Reg, MainSize * I); + } + + for (unsigned Offset = MainSize * NumParts; Offset < RegSize; + Offset += LeftoverSize) { + Register NewReg = MRI.createGenericVirtualRegister(LeftoverTy); + LeftoverRegs.push_back(NewReg); + MIRBuilder.buildExtract(NewReg, Reg, Offset); + } + + return true; +} + +void llvm::extractVectorParts(Register Reg, unsigned NumElts, + SmallVectorImpl &VRegs, + MachineIRBuilder &MIRBuilder, + MachineRegisterInfo &MRI) { + LLT RegTy = MRI.getType(Reg); + assert(RegTy.isVector() && "Expected a vector type"); + + LLT EltTy = RegTy.getElementType(); + LLT NarrowTy = (NumElts == 1) ? EltTy : LLT::fixed_vector(NumElts, EltTy); + unsigned RegNumElts = RegTy.getNumElements(); + unsigned LeftoverNumElts = RegNumElts % NumElts; + unsigned NumNarrowTyPieces = RegNumElts / NumElts; + + // Perfect split without leftover + if (LeftoverNumElts == 0) + return extractParts(Reg, NarrowTy, NumNarrowTyPieces, VRegs, MIRBuilder, + MRI); + + // Irregular split. Provide direct access to all elements for artifact + // combiner using unmerge to elements. Then build vectors with NumElts + // elements. Remaining element(s) will be (used to build vector) Leftover. + SmallVector Elts; + extractParts(Reg, EltTy, RegNumElts, Elts, MIRBuilder, MRI); + + unsigned Offset = 0; + // Requested sub-vectors of NarrowTy. + for (unsigned i = 0; i < NumNarrowTyPieces; ++i, Offset += NumElts) { + ArrayRef Pieces(&Elts[Offset], NumElts); + VRegs.push_back(MIRBuilder.buildMergeLikeInstr(NarrowTy, Pieces).getReg(0)); + } + + // Leftover element(s). + if (LeftoverNumElts == 1) { + VRegs.push_back(Elts[Offset]); + } else { + LLT LeftoverTy = LLT::fixed_vector(LeftoverNumElts, EltTy); + ArrayRef Pieces(&Elts[Offset], LeftoverNumElts); + VRegs.push_back( + MIRBuilder.buildMergeLikeInstr(LeftoverTy, Pieces).getReg(0)); + } +} + MachineInstr *llvm::getOpcodeDef(unsigned Opcode, Register Reg, const MachineRegisterInfo &MRI) { MachineInstr *DefMI = getDefIgnoringCopies(Reg, MRI); diff --git a/llvm/lib/CodeGen/GlobalMerge.cpp b/llvm/lib/CodeGen/GlobalMerge.cpp index 22b6d31d063..a2b5cbf7bad 100644 --- a/llvm/lib/CodeGen/GlobalMerge.cpp +++ b/llvm/lib/CodeGen/GlobalMerge.cpp @@ -60,6 +60,7 @@ // // ===---------------------------------------------------------------------===// +#include "llvm/CodeGen/GlobalMerge.h" #include "llvm/ADT/BitVector.h" #include "llvm/ADT/DenseMap.h" #include "llvm/ADT/SetVector.h" @@ -137,88 +138,99 @@ STATISTIC(NumMerged, "Number of globals merged"); namespace { - class GlobalMerge : public FunctionPass { - const TargetMachine *TM = nullptr; +class GlobalMergeImpl { + const TargetMachine *TM = nullptr; + GlobalMergeOptions Opt; + bool IsMachO = false; - // FIXME: Infer the maximum possible offset depending on the actual users - // (these max offsets are different for the users inside Thumb or ARM - // functions), see the code that passes in the offset in the ARM backend - // for more information. - unsigned MaxOffset; +private: + bool doMerge(SmallVectorImpl &Globals, Module &M, + bool isConst, unsigned AddrSpace) const; - /// Whether we should try to optimize for size only. - /// Currently, this applies a dead simple heuristic: only consider globals - /// used in minsize functions for merging. - /// FIXME: This could learn about optsize, and be used in the cost model. - bool OnlyOptimizeForSize = false; + /// Merge everything in \p Globals for which the corresponding bit + /// in \p GlobalSet is set. + bool doMerge(const SmallVectorImpl &Globals, + const BitVector &GlobalSet, Module &M, bool isConst, + unsigned AddrSpace) const; - /// Whether we should merge global variables that have external linkage. - bool MergeExternalGlobals = false; + /// Check if the given variable has been identified as must keep + /// \pre setMustKeepGlobalVariables must have been called on the Module that + /// contains GV + bool isMustKeepGlobalVariable(const GlobalVariable *GV) const { + return MustKeepGlobalVariables.count(GV); + } - bool IsMachO = false; + /// Collect every variables marked as "used" or used in a landing pad + /// instruction for this Module. + void setMustKeepGlobalVariables(Module &M); - bool doMerge(SmallVectorImpl &Globals, - Module &M, bool isConst, unsigned AddrSpace) const; + /// Collect every variables marked as "used" + void collectUsedGlobalVariables(Module &M, StringRef Name); - /// Merge everything in \p Globals for which the corresponding bit - /// in \p GlobalSet is set. - bool doMerge(const SmallVectorImpl &Globals, - const BitVector &GlobalSet, Module &M, bool isConst, - unsigned AddrSpace) const; + /// Keep track of the GlobalVariable that must not be merged away + SmallSetVector MustKeepGlobalVariables; - /// Check if the given variable has been identified as must keep - /// \pre setMustKeepGlobalVariables must have been called on the Module that - /// contains GV - bool isMustKeepGlobalVariable(const GlobalVariable *GV) const { - return MustKeepGlobalVariables.count(GV); - } +public: + GlobalMergeImpl(const TargetMachine *TM, GlobalMergeOptions Opt) + : TM(TM), Opt(Opt) {} + bool run(Module &M); +}; - /// Collect every variables marked as "used" or used in a landing pad - /// instruction for this Module. - void setMustKeepGlobalVariables(Module &M); +class GlobalMerge : public FunctionPass { + const TargetMachine *TM = nullptr; + GlobalMergeOptions Opt; - /// Collect every variables marked as "used" - void collectUsedGlobalVariables(Module &M, StringRef Name); +public: + static char ID; // Pass identification, replacement for typeid. - /// Keep track of the GlobalVariable that must not be merged away - SmallSetVector MustKeepGlobalVariables; + explicit GlobalMerge() : FunctionPass(ID) { + Opt.MaxOffset = GlobalMergeMaxOffset; + initializeGlobalMergePass(*PassRegistry::getPassRegistry()); + } - public: - static char ID; // Pass identification, replacement for typeid. + explicit GlobalMerge(const TargetMachine *TM, unsigned MaximalOffset, + bool OnlyOptimizeForSize, bool MergeExternalGlobals) + : FunctionPass(ID), TM(TM) { + Opt.MaxOffset = MaximalOffset; + Opt.SizeOnly = OnlyOptimizeForSize; + Opt.MergeExternal = MergeExternalGlobals; + initializeGlobalMergePass(*PassRegistry::getPassRegistry()); + } - explicit GlobalMerge() - : FunctionPass(ID), MaxOffset(GlobalMergeMaxOffset) { - initializeGlobalMergePass(*PassRegistry::getPassRegistry()); - } + bool doInitialization(Module &M) override { + GlobalMergeImpl P(TM, Opt); + return P.run(M); + } + bool runOnFunction(Function &F) override { return false; } - explicit GlobalMerge(const TargetMachine *TM, unsigned MaximalOffset, - bool OnlyOptimizeForSize, bool MergeExternalGlobals) - : FunctionPass(ID), TM(TM), MaxOffset(MaximalOffset), - OnlyOptimizeForSize(OnlyOptimizeForSize), - MergeExternalGlobals(MergeExternalGlobals) { - initializeGlobalMergePass(*PassRegistry::getPassRegistry()); - } + StringRef getPassName() const override { return "Merge internal globals"; } - bool doInitialization(Module &M) override; - bool runOnFunction(Function &F) override; - bool doFinalization(Module &M) override; - - StringRef getPassName() const override { return "Merge internal globals"; } - - void getAnalysisUsage(AnalysisUsage &AU) const override { - AU.setPreservesCFG(); - FunctionPass::getAnalysisUsage(AU); - } - }; + void getAnalysisUsage(AnalysisUsage &AU) const override { + AU.setPreservesCFG(); + FunctionPass::getAnalysisUsage(AU); + } +}; } // end anonymous namespace +PreservedAnalyses GlobalMergePass::run(Module &M, ModuleAnalysisManager &) { + GlobalMergeImpl P(TM, Options); + bool Changed = P.run(M); + if (!Changed) + return PreservedAnalyses::all(); + + PreservedAnalyses PA; + PA.preserveSet(); + return PA; +} + char GlobalMerge::ID = 0; INITIALIZE_PASS(GlobalMerge, DEBUG_TYPE, "Merge global variables", false, false) -bool GlobalMerge::doMerge(SmallVectorImpl &Globals, - Module &M, bool isConst, unsigned AddrSpace) const { +bool GlobalMergeImpl::doMerge(SmallVectorImpl &Globals, + Module &M, bool isConst, + unsigned AddrSpace) const { auto &DL = M.getDataLayout(); // FIXME: Find better heuristics llvm::stable_sort( @@ -333,7 +345,7 @@ bool GlobalMerge::doMerge(SmallVectorImpl &Globals, Function *ParentFn = I->getParent()->getParent(); // If we're only optimizing for size, ignore non-minsize functions. - if (OnlyOptimizeForSize && !ParentFn->hasMinSize()) + if (Opt.SizeOnly && !ParentFn->hasMinSize()) continue; size_t UGSIdx = GlobalUsesByFunction[ParentFn]; @@ -434,9 +446,9 @@ bool GlobalMerge::doMerge(SmallVectorImpl &Globals, return Changed; } -bool GlobalMerge::doMerge(const SmallVectorImpl &Globals, - const BitVector &GlobalSet, Module &M, bool isConst, - unsigned AddrSpace) const { +bool GlobalMergeImpl::doMerge(const SmallVectorImpl &Globals, + const BitVector &GlobalSet, Module &M, + bool isConst, unsigned AddrSpace) const { assert(Globals.size() > 1); Type *Int32Ty = Type::getInt32Ty(M.getContext()); @@ -467,7 +479,7 @@ bool GlobalMerge::doMerge(const SmallVectorImpl &Globals, unsigned Padding = alignTo(MergedSize, Alignment) - MergedSize; MergedSize += Padding; MergedSize += DL.getTypeAllocSize(Ty); - if (MergedSize > MaxOffset) { + if (MergedSize > Opt.MaxOffset) { break; } if (Padding) { @@ -563,7 +575,7 @@ bool GlobalMerge::doMerge(const SmallVectorImpl &Globals, return Changed; } -void GlobalMerge::collectUsedGlobalVariables(Module &M, StringRef Name) { +void GlobalMergeImpl::collectUsedGlobalVariables(Module &M, StringRef Name) { // Extract global variables from llvm.used array const GlobalVariable *GV = M.getGlobalVariable(Name); if (!GV || !GV->hasInitializer()) return; @@ -577,7 +589,7 @@ void GlobalMerge::collectUsedGlobalVariables(Module &M, StringRef Name) { MustKeepGlobalVariables.insert(G); } -void GlobalMerge::setMustKeepGlobalVariables(Module &M) { +void GlobalMergeImpl::setMustKeepGlobalVariables(Module &M) { collectUsedGlobalVariables(M, "llvm.used"); collectUsedGlobalVariables(M, "llvm.compiler.used"); @@ -604,7 +616,7 @@ void GlobalMerge::setMustKeepGlobalVariables(Module &M) { } } -bool GlobalMerge::doInitialization(Module &M) { +bool GlobalMergeImpl::run(Module &M) { if (!EnableGlobalMerge) return false; @@ -632,7 +644,7 @@ bool GlobalMerge::doInitialization(Module &M) { if (TM && !TM->shouldAssumeDSOLocal(M, &GV)) continue; - if (!(MergeExternalGlobals && GV.hasExternalLinkage()) && + if (!(Opt.MergeExternal && GV.hasExternalLinkage()) && !GV.hasInternalLinkage()) continue; @@ -659,7 +671,7 @@ bool GlobalMerge::doInitialization(Module &M) { continue; Type *Ty = GV.getValueType(); - if (DL.getTypeAllocSize(Ty) < MaxOffset) { + if (DL.getTypeAllocSize(Ty) < Opt.MaxOffset) { if (TM && TargetLoweringObjectFile::getKindForGlobal(&GV, *TM).isBSS()) BSSGlobals[{AddressSpace, Section}].push_back(&GV); @@ -686,15 +698,6 @@ bool GlobalMerge::doInitialization(Module &M) { return Changed; } -bool GlobalMerge::runOnFunction(Function &F) { - return false; -} - -bool GlobalMerge::doFinalization(Module &M) { - MustKeepGlobalVariables.clear(); - return false; -} - Pass *llvm::createGlobalMergePass(const TargetMachine *TM, unsigned Offset, bool OnlyOptimizeForSize, bool MergeExternalByDefault) { diff --git a/llvm/lib/CodeGen/LiveDebugValues/InstrRefBasedImpl.h b/llvm/lib/CodeGen/LiveDebugValues/InstrRefBasedImpl.h index ccc284b6233..6d77a6972f0 100644 --- a/llvm/lib/CodeGen/LiveDebugValues/InstrRefBasedImpl.h +++ b/llvm/lib/CodeGen/LiveDebugValues/InstrRefBasedImpl.h @@ -924,7 +924,7 @@ public: LocIdx getRegMLoc(Register R) { unsigned ID = getLocID(R); assert(ID < LocIDToLocIdx.size()); - assert(LocIDToLocIdx[ID] != UINT_MAX); // Sentinal for IndexedMap. + assert(LocIDToLocIdx[ID] != UINT_MAX); // Sentinel for IndexedMap. return LocIDToLocIdx[ID]; } @@ -940,7 +940,7 @@ public: // Get LocIdx of a spill ID. LocIdx getSpillMLoc(unsigned SpillID) { - assert(LocIDToLocIdx[SpillID] != UINT_MAX); // Sentinal for IndexedMap. + assert(LocIDToLocIdx[SpillID] != UINT_MAX); // Sentinel for IndexedMap. return LocIDToLocIdx[SpillID]; } diff --git a/llvm/lib/CodeGen/MachineCopyPropagation.cpp b/llvm/lib/CodeGen/MachineCopyPropagation.cpp index 51e944d0279..9a0ab300b21 100644 --- a/llvm/lib/CodeGen/MachineCopyPropagation.cpp +++ b/llvm/lib/CodeGen/MachineCopyPropagation.cpp @@ -853,7 +853,7 @@ void MachineCopyPropagation::ForwardCopyPropagateBlock(MachineBasicBlock &MBB) { forwardUses(MI); // Not a copy. - SmallVector Defs; + SmallVector Defs; const MachineOperand *RegMask = nullptr; for (const MachineOperand &MO : MI.operands()) { if (MO.isRegMask()) diff --git a/llvm/lib/CodeGen/MachineOperand.cpp b/llvm/lib/CodeGen/MachineOperand.cpp index 12d6b79f735..c7c0a1c20d5 100644 --- a/llvm/lib/CodeGen/MachineOperand.cpp +++ b/llvm/lib/CodeGen/MachineOperand.cpp @@ -206,6 +206,19 @@ void MachineOperand::ChangeToGA(const GlobalValue *GV, int64_t Offset, setTargetFlags(TargetFlags); } +void MachineOperand::ChangeToBA(const BlockAddress *BA, int64_t Offset, + unsigned TargetFlags) { + assert((!isReg() || !isTied()) && + "Cannot change a tied operand into a block address"); + + removeRegFromUses(); + + OpKind = MO_BlockAddress; + Contents.OffsetedInfo.Val.BA = BA; + setOffset(Offset); + setTargetFlags(TargetFlags); +} + void MachineOperand::ChangeToMCSymbol(MCSymbol *Sym, unsigned TargetFlags) { assert((!isReg() || !isTied()) && "Cannot change a tied operand into an MCSymbol"); diff --git a/llvm/lib/CodeGen/MachineOutliner.cpp b/llvm/lib/CodeGen/MachineOutliner.cpp index a0769105c92..b8d3b2e30e6 100644 --- a/llvm/lib/CodeGen/MachineOutliner.cpp +++ b/llvm/lib/CodeGen/MachineOutliner.cpp @@ -525,7 +525,7 @@ void MachineOutliner::emitNotOutliningCheaperRemark( MachineOptimizationRemarkEmitter MORE(*(C.getMF()), nullptr); MORE.emit([&]() { MachineOptimizationRemarkMissed R(DEBUG_TYPE, "NotOutliningCheaper", - C.front()->getDebugLoc(), C.getMBB()); + C.front().getDebugLoc(), C.getMBB()); R << "Did not outline " << NV("Length", StringLen) << " instructions" << " from " << NV("NumOccurrences", CandidatesForRepeatedSeq.size()) << " locations." @@ -538,7 +538,7 @@ void MachineOutliner::emitNotOutliningCheaperRemark( // Tell the user the other places the candidate was found. for (unsigned i = 1, e = CandidatesForRepeatedSeq.size(); i < e; i++) { R << NV((Twine("OtherStartLoc") + Twine(i)).str(), - CandidatesForRepeatedSeq[i].front()->getDebugLoc()); + CandidatesForRepeatedSeq[i].front().getDebugLoc()); if (i != e - 1) R << ", "; } @@ -563,7 +563,7 @@ void MachineOutliner::emitOutlinedFunctionRemark(OutlinedFunction &OF) { for (size_t i = 0, e = OF.Candidates.size(); i < e; i++) { R << NV((Twine("StartLoc") + Twine(i)).str(), - OF.Candidates[i].front()->getDebugLoc()); + OF.Candidates[i].front().getDebugLoc()); if (i != e - 1) R << ", "; } @@ -732,23 +732,22 @@ MachineFunction *MachineOutliner::createOutlinedFunction( // Insert the new function into the module. MF.insert(MF.begin(), &MBB); - MachineFunction *OriginalMF = FirstCand.front()->getMF(); + MachineFunction *OriginalMF = FirstCand.front().getMF(); const std::vector &Instrs = OriginalMF->getFrameInstructions(); - for (auto I = FirstCand.front(), E = std::next(FirstCand.back()); I != E; - ++I) { - if (I->isDebugInstr()) + for (auto &MI : FirstCand) { + if (MI.isDebugInstr()) continue; // Don't keep debug information for outlined instructions. auto DL = DebugLoc(); - if (I->isCFIInstruction()) { - unsigned CFIIndex = I->getOperand(0).getCFIIndex(); + if (MI.isCFIInstruction()) { + unsigned CFIIndex = MI.getOperand(0).getCFIIndex(); MCCFIInstruction CFI = Instrs[CFIIndex]; BuildMI(MBB, MBB.end(), DL, TII.get(TargetOpcode::CFI_INSTRUCTION)) .addCFIIndex(MF.addFrameInst(CFI)); } else { - MachineInstr *NewMI = MF.CloneMachineInstr(&*I); + MachineInstr *NewMI = MF.CloneMachineInstr(&MI); NewMI->dropMemRefs(MF); NewMI->setDebugLoc(DL); MBB.insert(MBB.end(), NewMI); @@ -768,11 +767,11 @@ MachineFunction *MachineOutliner::createOutlinedFunction( LivePhysRegs LiveIns(TRI); for (auto &Cand : OF.Candidates) { // Figure out live-ins at the first instruction. - MachineBasicBlock &OutlineBB = *Cand.front()->getParent(); + MachineBasicBlock &OutlineBB = *Cand.front().getParent(); LivePhysRegs CandLiveIns(TRI); CandLiveIns.addLiveOuts(OutlineBB); for (const MachineInstr &MI : - reverse(make_range(Cand.front(), OutlineBB.end()))) + reverse(make_range(Cand.begin(), OutlineBB.end()))) CandLiveIns.stepBackward(MI); // The live-in set for the outlined function is the union of the live-ins @@ -884,8 +883,8 @@ bool MachineOutliner::outline(Module &M, LLVM_DEBUG(dbgs() << "CREATE OUTLINED CALLS\n"); for (Candidate &C : OF.Candidates) { MachineBasicBlock &MBB = *C.getMBB(); - MachineBasicBlock::iterator StartIt = C.front(); - MachineBasicBlock::iterator EndIt = C.back(); + MachineBasicBlock::iterator StartIt = C.begin(); + MachineBasicBlock::iterator EndIt = std::prev(C.end()); // Insert the call. auto CallInst = TII.insertOutlinedCall(M, MBB, StartIt, *MF, C); diff --git a/llvm/lib/CodeGen/MachinePipeliner.cpp b/llvm/lib/CodeGen/MachinePipeliner.cpp index 8cd7f4ebe88..2d2d0bffe21 100644 --- a/llvm/lib/CodeGen/MachinePipeliner.cpp +++ b/llvm/lib/CodeGen/MachinePipeliner.cpp @@ -35,6 +35,7 @@ #include "llvm/ADT/DenseMap.h" #include "llvm/ADT/MapVector.h" #include "llvm/ADT/PriorityQueue.h" +#include "llvm/ADT/STLExtras.h" #include "llvm/ADT/SetOperations.h" #include "llvm/ADT/SetVector.h" #include "llvm/ADT/SmallPtrSet.h" @@ -60,9 +61,12 @@ #include "llvm/CodeGen/MachineOperand.h" #include "llvm/CodeGen/MachineRegisterInfo.h" #include "llvm/CodeGen/ModuloSchedule.h" +#include "llvm/CodeGen/Register.h" +#include "llvm/CodeGen/RegisterClassInfo.h" #include "llvm/CodeGen/RegisterPressure.h" #include "llvm/CodeGen/ScheduleDAG.h" #include "llvm/CodeGen/ScheduleDAGMutation.h" +#include "llvm/CodeGen/TargetInstrInfo.h" #include "llvm/CodeGen/TargetOpcodes.h" #include "llvm/CodeGen/TargetRegisterInfo.h" #include "llvm/CodeGen/TargetSubtargetInfo.h" @@ -174,6 +178,20 @@ static cl::opt ExperimentalCodeGen( cl::desc( "Use the experimental peeling code generator for software pipelining")); +static cl::opt SwpIISearchRange("pipeliner-ii-search-range", + cl::desc("Range to search for II"), + cl::Hidden, cl::init(10)); + +static cl::opt + LimitRegPressure("pipeliner-register-pressure", cl::Hidden, cl::init(false), + cl::desc("Limit register pressure of scheduled loop")); + +static cl::opt + RegPressureMargin("pipeliner-register-pressure-margin", cl::Hidden, + cl::init(5), + cl::desc("Margin representing the unused percentage of " + "the register pressure limit")); + namespace llvm { // A command line option to enable the CopyToPhi DAG mutation. @@ -484,7 +502,7 @@ void SwingSchedulerDAG::setMAX_II() { else if (II_setByPragma > 0) MAX_II = II_setByPragma; else - MAX_II = MII + 10; + MAX_II = MII + SwpIISearchRange; } /// We override the schedule function in ScheduleDAGInstrs to implement the @@ -695,7 +713,8 @@ static void getPhiRegs(MachineInstr &Phi, MachineBasicBlock *Loop, } /// Return the Phi register value that comes the loop block. -static unsigned getLoopPhiReg(MachineInstr &Phi, MachineBasicBlock *LoopBB) { +static unsigned getLoopPhiReg(const MachineInstr &Phi, + const MachineBasicBlock *LoopBB) { for (unsigned i = 1, e = Phi.getNumOperands(); i != e; i += 2) if (Phi.getOperand(i + 1).getMBB() == LoopBB) return Phi.getOperand(i).getReg(); @@ -996,6 +1015,41 @@ void SwingSchedulerDAG::changeDependences() { } } +/// Create an instruction stream that represents a single iteration and stage of +/// each instruction. This function differs from SMSchedule::finalizeSchedule in +/// that this doesn't have any side-effect to SwingSchedulerDAG. That is, this +/// function is an approximation of SMSchedule::finalizeSchedule with all +/// non-const operations removed. +static void computeScheduledInsts(const SwingSchedulerDAG *SSD, + SMSchedule &Schedule, + std::vector &OrderedInsts, + DenseMap &Stages) { + DenseMap> Instrs; + + // Move all instructions to the first stage from the later stages. + for (int Cycle = Schedule.getFirstCycle(); Cycle <= Schedule.getFinalCycle(); + ++Cycle) { + for (int Stage = 0, LastStage = Schedule.getMaxStageCount(); + Stage <= LastStage; ++Stage) { + for (SUnit *SU : llvm::reverse(Schedule.getInstructions( + Cycle + Stage * Schedule.getInitiationInterval()))) { + Instrs[Cycle].push_front(SU); + } + } + } + + for (int Cycle = Schedule.getFirstCycle(); Cycle <= Schedule.getFinalCycle(); + ++Cycle) { + std::deque &CycleInstrs = Instrs[Cycle]; + CycleInstrs = Schedule.reorderInstructions(SSD, CycleInstrs); + for (SUnit *SU : CycleInstrs) { + MachineInstr *MI = SU->getInstr(); + OrderedInsts.push_back(MI); + Stages[MI] = Schedule.stageScheduled(SU); + } + } +} + namespace { // FuncUnitSorter - Comparison operator used to sort instructions by @@ -1102,6 +1156,375 @@ struct FuncUnitSorter { } }; +/// Calculate the maximum register pressure of the scheduled instructions stream +class HighRegisterPressureDetector { + MachineBasicBlock *OrigMBB; + const MachineFunction &MF; + const MachineRegisterInfo &MRI; + const TargetRegisterInfo *TRI; + + const unsigned PSetNum; + + // Indexed by PSet ID + // InitSetPressure takes into account the register pressure of live-in + // registers. It's not depend on how the loop is scheduled, so it's enough to + // calculate them once at the beginning. + std::vector InitSetPressure; + + // Indexed by PSet ID + // Upper limit for each register pressure set + std::vector PressureSetLimit; + + DenseMap ROMap; + + using Instr2LastUsesTy = DenseMap>; + +public: + using OrderedInstsTy = std::vector; + using Instr2StageTy = DenseMap; + +private: + static void dumpRegisterPressures(const std::vector &Pressures) { + if (Pressures.size() == 0) { + dbgs() << "[]"; + } else { + char Prefix = '['; + for (unsigned P : Pressures) { + dbgs() << Prefix << P; + Prefix = ' '; + } + dbgs() << ']'; + } + } + + void dumpPSet(Register Reg) const { + dbgs() << "Reg=" << printReg(Reg, TRI, 0, &MRI) << " PSet="; + for (auto PSetIter = MRI.getPressureSets(Reg); PSetIter.isValid(); + ++PSetIter) { + dbgs() << *PSetIter << ' '; + } + dbgs() << '\n'; + } + + void increaseRegisterPressure(std::vector &Pressure, + Register Reg) const { + auto PSetIter = MRI.getPressureSets(Reg); + unsigned Weight = PSetIter.getWeight(); + for (; PSetIter.isValid(); ++PSetIter) + Pressure[*PSetIter] += Weight; + } + + void decreaseRegisterPressure(std::vector &Pressure, + Register Reg) const { + auto PSetIter = MRI.getPressureSets(Reg); + unsigned Weight = PSetIter.getWeight(); + for (; PSetIter.isValid(); ++PSetIter) { + auto &P = Pressure[*PSetIter]; + assert(P >= Weight && + "register pressure must be greater than or equal weight"); + P -= Weight; + } + } + + // Return true if Reg is fixed one, for example, stack pointer + bool isFixedRegister(Register Reg) const { + return Reg.isPhysical() && TRI->isFixedRegister(MF, Reg.asMCReg()); + } + + bool isDefinedInThisLoop(Register Reg) const { + return Reg.isVirtual() && MRI.getVRegDef(Reg)->getParent() == OrigMBB; + } + + // Search for live-in variables. They are factored into the register pressure + // from the begining. Live-in variables used by every iteration should be + // considered as alive throughout the loop. For example, the variable `c` in + // following code. \code + // int c = ...; + // for (int i = 0; i < n; i++) + // a[i] += b[i] + c; + // \endcode + void computeLiveIn() { + DenseSet Used; + for (auto &MI : *OrigMBB) { + if (MI.isDebugInstr()) + continue; + for (auto Use : ROMap[&MI].Uses) { + auto Reg = Use.RegUnit; + // Ignore the variable that appears only on one side of phi instruction + // because it's used only at the first iteration. + if (MI.isPHI() && Reg != getLoopPhiReg(MI, OrigMBB)) + continue; + if (isFixedRegister(Reg)) + continue; + if (isDefinedInThisLoop(Reg)) + continue; + Used.insert(Reg); + } + } + + for (auto LiveIn : Used) + increaseRegisterPressure(InitSetPressure, LiveIn); + } + + // Calculate the upper limit of each pressure set + void computePressureSetLimit(const RegisterClassInfo &RCI) { + for (unsigned PSet = 0; PSet < PSetNum; PSet++) + PressureSetLimit[PSet] = RCI.getRegPressureSetLimit(PSet); + + // We assume fixed registers, such as stack pointer, are already in use. + // Therefore subtracting the weight of the fixed registers from the limit of + // each pressure set in advance. + SmallDenseSet FixedRegs; + for (const TargetRegisterClass *TRC : TRI->regclasses()) { + for (const MCPhysReg Reg : *TRC) + if (isFixedRegister(Reg)) + FixedRegs.insert(Reg); + } + + LLVM_DEBUG({ + for (auto Reg : FixedRegs) { + dbgs() << printReg(Reg, TRI, 0, &MRI) << ": ["; + const int *Sets = TRI->getRegUnitPressureSets(Reg); + for (; *Sets != -1; Sets++) { + dbgs() << TRI->getRegPressureSetName(*Sets) << ", "; + } + dbgs() << "]\n"; + } + }); + + for (auto Reg : FixedRegs) { + LLVM_DEBUG(dbgs() << "fixed register: " << printReg(Reg, TRI, 0, &MRI) + << "\n"); + auto PSetIter = MRI.getPressureSets(Reg); + unsigned Weight = PSetIter.getWeight(); + for (; PSetIter.isValid(); ++PSetIter) { + unsigned &Limit = PressureSetLimit[*PSetIter]; + assert(Limit >= Weight && + "register pressure limit must be greater than or equal weight"); + Limit -= Weight; + LLVM_DEBUG(dbgs() << "PSet=" << *PSetIter << " Limit=" << Limit + << " (decreased by " << Weight << ")\n"); + } + } + } + + // There are two patterns of last-use. + // - by an instruction of the current iteration + // - by a phi instruction of the next iteration (loop carried value) + // + // Furthermore, following two groups of instructions are executed + // simultaneously + // - next iteration's phi instructions in i-th stage + // - current iteration's instructions in i+1-th stage + // + // This function calculates the last-use of each register while taking into + // account the above two patterns. + Instr2LastUsesTy computeLastUses(const OrderedInstsTy &OrderedInsts, + Instr2StageTy &Stages) const { + // We treat virtual registers that are defined and used in this loop. + // Following virtual register will be ignored + // - live-in one + // - defined but not used in the loop (potentially live-out) + DenseSet TargetRegs; + const auto UpdateTargetRegs = [this, &TargetRegs](Register Reg) { + if (isDefinedInThisLoop(Reg)) + TargetRegs.insert(Reg); + }; + for (MachineInstr *MI : OrderedInsts) { + if (MI->isPHI()) { + Register Reg = getLoopPhiReg(*MI, OrigMBB); + UpdateTargetRegs(Reg); + } else { + for (auto Use : ROMap.find(MI)->getSecond().Uses) + UpdateTargetRegs(Use.RegUnit); + } + } + + const auto InstrScore = [&Stages](MachineInstr *MI) { + return Stages[MI] + MI->isPHI(); + }; + + DenseMap LastUseMI; + for (MachineInstr *MI : llvm::reverse(OrderedInsts)) { + for (auto Use : ROMap.find(MI)->getSecond().Uses) { + auto Reg = Use.RegUnit; + if (!TargetRegs.contains(Reg)) + continue; + auto Ite = LastUseMI.find(Reg); + if (Ite == LastUseMI.end()) { + LastUseMI[Reg] = MI; + } else { + MachineInstr *Orig = Ite->second; + MachineInstr *New = MI; + if (InstrScore(Orig) < InstrScore(New)) + LastUseMI[Reg] = New; + } + } + } + + Instr2LastUsesTy LastUses; + for (auto &Entry : LastUseMI) + LastUses[Entry.second].insert(Entry.first); + return LastUses; + } + + // Compute the maximum register pressure of the kernel. We'll simulate #Stage + // iterations and check the register pressure at the point where all stages + // overlapping. + // + // An example of unrolled loop where #Stage is 4.. + // Iter i+0 i+1 i+2 i+3 + // ------------------------ + // Stage 0 + // Stage 1 0 + // Stage 2 1 0 + // Stage 3 2 1 0 <- All stages overlap + // + std::vector + computeMaxSetPressure(const OrderedInstsTy &OrderedInsts, + Instr2StageTy &Stages, + const unsigned StageCount) const { + using RegSetTy = SmallDenseSet; + + // Indexed by #Iter. To treat "local" variables of each stage separately, we + // manage the liveness of the registers independently by iterations. + SmallVector LiveRegSets(StageCount); + + auto CurSetPressure = InitSetPressure; + auto MaxSetPressure = InitSetPressure; + auto LastUses = computeLastUses(OrderedInsts, Stages); + + LLVM_DEBUG({ + dbgs() << "Ordered instructions:\n"; + for (MachineInstr *MI : OrderedInsts) { + dbgs() << "Stage " << Stages[MI] << ": "; + MI->dump(); + } + }); + + const auto InsertReg = [this, &CurSetPressure](RegSetTy &RegSet, + Register Reg) { + if (!Reg.isValid() || isFixedRegister(Reg)) + return; + + bool Inserted = RegSet.insert(Reg).second; + if (!Inserted) + return; + + LLVM_DEBUG(dbgs() << "insert " << printReg(Reg, TRI, 0, &MRI) << "\n"); + increaseRegisterPressure(CurSetPressure, Reg); + LLVM_DEBUG(dumpPSet(Reg)); + }; + + const auto EraseReg = [this, &CurSetPressure](RegSetTy &RegSet, + Register Reg) { + if (!Reg.isValid() || isFixedRegister(Reg)) + return; + + // live-in register + if (!RegSet.contains(Reg)) + return; + + LLVM_DEBUG(dbgs() << "erase " << printReg(Reg, TRI, 0, &MRI) << "\n"); + RegSet.erase(Reg); + decreaseRegisterPressure(CurSetPressure, Reg); + LLVM_DEBUG(dumpPSet(Reg)); + }; + + for (unsigned I = 0; I < StageCount; I++) { + for (MachineInstr *MI : OrderedInsts) { + const auto Stage = Stages[MI]; + if (I < Stage) + continue; + + const unsigned Iter = I - Stage; + + for (auto Def : ROMap.find(MI)->getSecond().Defs) + InsertReg(LiveRegSets[Iter], Def.RegUnit); + + for (auto LastUse : LastUses[MI]) { + if (MI->isPHI()) { + if (Iter != 0) + EraseReg(LiveRegSets[Iter - 1], LastUse); + } else { + EraseReg(LiveRegSets[Iter], LastUse); + } + } + + for (unsigned PSet = 0; PSet < PSetNum; PSet++) + MaxSetPressure[PSet] = + std::max(MaxSetPressure[PSet], CurSetPressure[PSet]); + + LLVM_DEBUG({ + dbgs() << "CurSetPressure="; + dumpRegisterPressures(CurSetPressure); + dbgs() << " iter=" << Iter << " stage=" << Stage << ":"; + MI->dump(); + }); + } + } + + return MaxSetPressure; + } + +public: + HighRegisterPressureDetector(MachineBasicBlock *OrigMBB, + const MachineFunction &MF) + : OrigMBB(OrigMBB), MF(MF), MRI(MF.getRegInfo()), + TRI(MF.getSubtarget().getRegisterInfo()), + PSetNum(TRI->getNumRegPressureSets()), InitSetPressure(PSetNum, 0), + PressureSetLimit(PSetNum, 0) {} + + // Used to calculate register pressure, which is independent of loop + // scheduling. + void init(const RegisterClassInfo &RCI) { + for (MachineInstr &MI : *OrigMBB) { + if (MI.isDebugInstr()) + continue; + ROMap[&MI].collect(MI, *TRI, MRI, false, true); + } + + computeLiveIn(); + computePressureSetLimit(RCI); + } + + // Calculate the maximum register pressures of the loop and check if they + // exceed the limit + bool detect(const SwingSchedulerDAG *SSD, SMSchedule &Schedule, + const unsigned MaxStage) const { + assert(0 <= RegPressureMargin && RegPressureMargin <= 100 && + "the percentage of the margin must be between 0 to 100"); + + OrderedInstsTy OrderedInsts; + Instr2StageTy Stages; + computeScheduledInsts(SSD, Schedule, OrderedInsts, Stages); + const auto MaxSetPressure = + computeMaxSetPressure(OrderedInsts, Stages, MaxStage + 1); + + LLVM_DEBUG({ + dbgs() << "Dump MaxSetPressure:\n"; + for (unsigned I = 0; I < MaxSetPressure.size(); I++) { + dbgs() << format("MaxSetPressure[%d]=%d\n", I, MaxSetPressure[I]); + } + dbgs() << '\n'; + }); + + for (unsigned PSet = 0; PSet < PSetNum; PSet++) { + unsigned Limit = PressureSetLimit[PSet]; + unsigned Margin = Limit * RegPressureMargin / 100; + LLVM_DEBUG(dbgs() << "PSet=" << PSet << " Limit=" << Limit + << " Margin=" << Margin << "\n"); + if (Limit < MaxSetPressure[PSet] + Margin) { + LLVM_DEBUG( + dbgs() + << "Rejected the schedule because of too high register pressure\n"); + return true; + } + } + return false; + } +}; + } // end anonymous namespace /// Calculate the resource constrained minimum initiation interval for the @@ -1967,6 +2390,12 @@ bool SwingSchedulerDAG::schedulePipeline(SMSchedule &Schedule) { } bool scheduleFound = false; + std::unique_ptr HRPDetector; + if (LimitRegPressure) { + HRPDetector = + std::make_unique(Loop.getHeader(), MF); + HRPDetector->init(RegClassInfo); + } // Keep increasing II until a valid schedule is found. for (unsigned II = MII; II <= MAX_II && !scheduleFound; ++II) { Schedule.reset(); @@ -2044,6 +2473,12 @@ bool SwingSchedulerDAG::schedulePipeline(SMSchedule &Schedule) { // If a schedule is found, check if it is a valid schedule too. if (scheduleFound) scheduleFound = Schedule.isValidSchedule(this); + + // If a schedule was found and the option is enabled, check if the schedule + // might generate additional register spills/fills. + if (scheduleFound && LimitRegPressure) + scheduleFound = + !HRPDetector->detect(this, Schedule, Schedule.getMaxStageCount()); } LLVM_DEBUG(dbgs() << "Schedule Found? " << scheduleFound @@ -2483,8 +2918,8 @@ void SMSchedule::computeStart(SUnit *SU, int *MaxEarlyStart, int *MinLateStart, /// Order the instructions within a cycle so that the definitions occur /// before the uses. Returns true if the instruction is added to the start /// of the list, or false if added to the end. -void SMSchedule::orderDependence(SwingSchedulerDAG *SSD, SUnit *SU, - std::deque &Insts) { +void SMSchedule::orderDependence(const SwingSchedulerDAG *SSD, SUnit *SU, + std::deque &Insts) const { MachineInstr *MI = SU->getInstr(); bool OrderBeforeUse = false; bool OrderAfterDef = false; @@ -2611,7 +3046,8 @@ void SMSchedule::orderDependence(SwingSchedulerDAG *SSD, SUnit *SU, } /// Return true if the scheduled Phi has a loop carried operand. -bool SMSchedule::isLoopCarried(SwingSchedulerDAG *SSD, MachineInstr &Phi) { +bool SMSchedule::isLoopCarried(const SwingSchedulerDAG *SSD, + MachineInstr &Phi) const { if (!Phi.isPHI()) return false; assert(Phi.isPHI() && "Expecting a Phi."); @@ -2639,8 +3075,9 @@ bool SMSchedule::isLoopCarried(SwingSchedulerDAG *SSD, MachineInstr &Phi) { /// (MO) = v1 /// If MO appears before Def, then v1 and v3 may get assigned to the same /// register. -bool SMSchedule::isLoopCarriedDefOfUse(SwingSchedulerDAG *SSD, - MachineInstr *Def, MachineOperand &MO) { +bool SMSchedule::isLoopCarriedDefOfUse(const SwingSchedulerDAG *SSD, + MachineInstr *Def, + MachineOperand &MO) const { if (!MO.isReg()) return false; if (Def->isPHI()) @@ -2895,6 +3332,23 @@ void SwingSchedulerDAG::fixupRegisterOverlaps(std::deque &Instrs) { } } +std::deque +SMSchedule::reorderInstructions(const SwingSchedulerDAG *SSD, + const std::deque &Instrs) const { + std::deque NewOrderPhi; + for (SUnit *SU : Instrs) { + if (SU->getInstr()->isPHI()) + NewOrderPhi.push_back(SU); + } + std::deque NewOrderI; + for (SUnit *SU : Instrs) { + if (!SU->getInstr()->isPHI()) + orderDependence(SSD, SU, NewOrderI); + } + llvm::append_range(NewOrderPhi, NewOrderI); + return NewOrderPhi; +} + /// After the schedule has been formed, call this function to combine /// the instructions from the different stages/cycles. That is, this /// function creates a schedule that represents a single iteration. @@ -2924,19 +3378,7 @@ void SMSchedule::finalizeSchedule(SwingSchedulerDAG *SSD) { // generated code. for (int Cycle = getFirstCycle(), E = getFinalCycle(); Cycle <= E; ++Cycle) { std::deque &cycleInstrs = ScheduledInstrs[Cycle]; - std::deque newOrderPhi; - for (SUnit *SU : cycleInstrs) { - if (SU->getInstr()->isPHI()) - newOrderPhi.push_back(SU); - } - std::deque newOrderI; - for (SUnit *SU : cycleInstrs) { - if (!SU->getInstr()->isPHI()) - orderDependence(SSD, SU, newOrderI); - } - // Replace the old order with the new order. - cycleInstrs.swap(newOrderPhi); - llvm::append_range(cycleInstrs, newOrderI); + cycleInstrs = reorderInstructions(SSD, cycleInstrs); SSD->fixupRegisterOverlaps(cycleInstrs); } diff --git a/llvm/lib/CodeGen/MachineScheduler.cpp b/llvm/lib/CodeGen/MachineScheduler.cpp index 886137d86f8..f40e91819a4 100644 --- a/llvm/lib/CodeGen/MachineScheduler.cpp +++ b/llvm/lib/CodeGen/MachineScheduler.cpp @@ -1743,11 +1743,14 @@ class BaseMemOpClusterMutation : public ScheduleDAGMutation { const TargetInstrInfo *TII; const TargetRegisterInfo *TRI; bool IsLoad; + bool ReorderWhileClustering; public: BaseMemOpClusterMutation(const TargetInstrInfo *tii, - const TargetRegisterInfo *tri, bool IsLoad) - : TII(tii), TRI(tri), IsLoad(IsLoad) {} + const TargetRegisterInfo *tri, bool IsLoad, + bool ReorderWhileClustering) + : TII(tii), TRI(tri), IsLoad(IsLoad), + ReorderWhileClustering(ReorderWhileClustering) {} void apply(ScheduleDAGInstrs *DAGInstrs) override; @@ -1763,14 +1766,16 @@ protected: class StoreClusterMutation : public BaseMemOpClusterMutation { public: StoreClusterMutation(const TargetInstrInfo *tii, - const TargetRegisterInfo *tri) - : BaseMemOpClusterMutation(tii, tri, false) {} + const TargetRegisterInfo *tri, + bool ReorderWhileClustering) + : BaseMemOpClusterMutation(tii, tri, false, ReorderWhileClustering) {} }; class LoadClusterMutation : public BaseMemOpClusterMutation { public: - LoadClusterMutation(const TargetInstrInfo *tii, const TargetRegisterInfo *tri) - : BaseMemOpClusterMutation(tii, tri, true) {} + LoadClusterMutation(const TargetInstrInfo *tii, const TargetRegisterInfo *tri, + bool ReorderWhileClustering) + : BaseMemOpClusterMutation(tii, tri, true, ReorderWhileClustering) {} }; } // end anonymous namespace @@ -1779,15 +1784,19 @@ namespace llvm { std::unique_ptr createLoadClusterDAGMutation(const TargetInstrInfo *TII, - const TargetRegisterInfo *TRI) { - return EnableMemOpCluster ? std::make_unique(TII, TRI) + const TargetRegisterInfo *TRI, + bool ReorderWhileClustering) { + return EnableMemOpCluster ? std::make_unique( + TII, TRI, ReorderWhileClustering) : nullptr; } std::unique_ptr createStoreClusterDAGMutation(const TargetInstrInfo *TII, - const TargetRegisterInfo *TRI) { - return EnableMemOpCluster ? std::make_unique(TII, TRI) + const TargetRegisterInfo *TRI, + bool ReorderWhileClustering) { + return EnableMemOpCluster ? std::make_unique( + TII, TRI, ReorderWhileClustering) : nullptr; } @@ -1840,7 +1849,7 @@ void BaseMemOpClusterMutation::clusterNeighboringMemOps( SUnit *SUa = MemOpa.SU; SUnit *SUb = MemOpb.SU; - if (SUa->NodeNum > SUb->NodeNum) + if (!ReorderWhileClustering && SUa->NodeNum > SUb->NodeNum) std::swap(SUa, SUb); // FIXME: Is this check really required? @@ -4260,7 +4269,7 @@ static bool sortIntervals(const ResourceSegments::IntervalTy &A, } unsigned ResourceSegments::getFirstAvailableAt( - unsigned CurrCycle, unsigned AcquireAtCycle, unsigned Cycle, + unsigned CurrCycle, unsigned AcquireAtCycle, unsigned ReleaseAtCycle, std::function IntervalBuilder) const { assert(std::is_sorted(std::begin(_Intervals), std::end(_Intervals), @@ -4268,7 +4277,7 @@ unsigned ResourceSegments::getFirstAvailableAt( "Cannot execute on an un-sorted set of intervals."); unsigned RetCycle = CurrCycle; ResourceSegments::IntervalTy NewInterval = - IntervalBuilder(RetCycle, AcquireAtCycle, Cycle); + IntervalBuilder(RetCycle, AcquireAtCycle, ReleaseAtCycle); for (auto &Interval : _Intervals) { if (!intersects(NewInterval, Interval)) continue; @@ -4278,7 +4287,7 @@ unsigned ResourceSegments::getFirstAvailableAt( assert(Interval.second > NewInterval.first && "Invalid intervals configuration."); RetCycle += (unsigned)Interval.second - (unsigned)NewInterval.first; - NewInterval = IntervalBuilder(RetCycle, AcquireAtCycle, Cycle); + NewInterval = IntervalBuilder(RetCycle, AcquireAtCycle, ReleaseAtCycle); } return RetCycle; } diff --git a/llvm/lib/CodeGen/PatchableFunction.cpp b/llvm/lib/CodeGen/PatchableFunction.cpp index 9449f143366..75c2dfeca58 100644 --- a/llvm/lib/CodeGen/PatchableFunction.cpp +++ b/llvm/lib/CodeGen/PatchableFunction.cpp @@ -38,58 +38,28 @@ struct PatchableFunction : public MachineFunctionPass { } bool PatchableFunction::runOnMachineFunction(MachineFunction &MF) { + MachineBasicBlock &FirstMBB = *MF.begin(); + if (MF.getFunction().hasFnAttribute("patchable-function-entry")) { - MachineBasicBlock &FirstMBB = *MF.begin(); const TargetInstrInfo *TII = MF.getSubtarget().getInstrInfo(); // The initial .loc covers PATCHABLE_FUNCTION_ENTER. BuildMI(FirstMBB, FirstMBB.begin(), DebugLoc(), TII->get(TargetOpcode::PATCHABLE_FUNCTION_ENTER)); return true; - } - - if (!MF.getFunction().hasFnAttribute("patchable-function")) - return false; - + } else if (MF.getFunction().hasFnAttribute("patchable-function")) { #ifndef NDEBUG - Attribute PatchAttr = MF.getFunction().getFnAttribute("patchable-function"); - StringRef PatchType = PatchAttr.getValueAsString(); - assert(PatchType == "prologue-short-redirect" && "Only possibility today!"); + Attribute PatchAttr = MF.getFunction().getFnAttribute("patchable-function"); + StringRef PatchType = PatchAttr.getValueAsString(); + assert(PatchType == "prologue-short-redirect" && "Only possibility today!"); #endif - - auto &FirstMBB = *MF.begin(); - auto *TII = MF.getSubtarget().getInstrInfo(); - - MachineBasicBlock::iterator FirstActualI = llvm::find_if( - FirstMBB, [](const MachineInstr &MI) { return !MI.isMetaInstruction(); }); - - if (FirstActualI == FirstMBB.end()) { - // As of Microsoft documentation on /hotpatch feature, we must ensure that - // "the first instruction of each function is at least two bytes, and no - // jump within the function goes to the first instruction" - - // When the first MBB is empty, insert a patchable no-op. This ensures the - // first instruction is patchable in two special cases: - // - the function is empty (e.g. unreachable) - // - the function jumps back to the first instruction, which is in a - // successor MBB. - BuildMI(&FirstMBB, DebugLoc(), TII->get(TargetOpcode::PATCHABLE_OP)) - .addImm(2) - .addImm(TargetOpcode::PATCHABLE_OP); + auto *TII = MF.getSubtarget().getInstrInfo(); + BuildMI(FirstMBB, FirstMBB.begin(), DebugLoc(), + TII->get(TargetOpcode::PATCHABLE_OP)) + .addImm(2); MF.ensureAlignment(Align(16)); return true; } - - auto MIB = BuildMI(FirstMBB, FirstActualI, FirstActualI->getDebugLoc(), - TII->get(TargetOpcode::PATCHABLE_OP)) - .addImm(2) - .addImm(FirstActualI->getOpcode()); - - for (auto &MO : FirstActualI->operands()) - MIB.add(MO); - - FirstActualI->eraseFromParent(); - MF.ensureAlignment(Align(16)); - return true; + return false; } char PatchableFunction::ID = 0; diff --git a/llvm/lib/CodeGen/PreISelIntrinsicLowering.cpp b/llvm/lib/CodeGen/PreISelIntrinsicLowering.cpp index 93183067797..0777acf6331 100644 --- a/llvm/lib/CodeGen/PreISelIntrinsicLowering.cpp +++ b/llvm/lib/CodeGen/PreISelIntrinsicLowering.cpp @@ -72,7 +72,6 @@ static bool lowerLoadRelative(Function &F) { bool Changed = false; Type *Int32Ty = Type::getInt32Ty(F.getContext()); - Type *Int8Ty = Type::getInt8Ty(F.getContext()); for (Use &U : llvm::make_early_inc_range(F.uses())) { auto CI = dyn_cast(U.getUser()); @@ -81,10 +80,10 @@ static bool lowerLoadRelative(Function &F) { IRBuilder<> B(CI); Value *OffsetPtr = - B.CreateGEP(Int8Ty, CI->getArgOperand(0), CI->getArgOperand(1)); + B.CreatePtrAdd(CI->getArgOperand(0), CI->getArgOperand(1)); Value *OffsetI32 = B.CreateAlignedLoad(Int32Ty, OffsetPtr, Align(4)); - Value *ResultPtr = B.CreateGEP(Int8Ty, CI->getArgOperand(0), OffsetI32); + Value *ResultPtr = B.CreatePtrAdd(CI->getArgOperand(0), OffsetI32); CI->replaceAllUsesWith(ResultPtr); CI->eraseFromParent(); diff --git a/llvm/lib/CodeGen/RDFGraph.cpp b/llvm/lib/CodeGen/RDFGraph.cpp index abf3b1e6fbb..6b2e69da76f 100644 --- a/llvm/lib/CodeGen/RDFGraph.cpp +++ b/llvm/lib/CodeGen/RDFGraph.cpp @@ -1790,7 +1790,7 @@ bool DataFlowGraph::hasUntrackedRef(Stmt S, bool IgnoreReserved) const { for (const MachineOperand &Op : S.Addr->getCode()->operands()) { if (!Op.isReg() && !Op.isRegMask()) continue; - if (llvm::find(Ops, &Op) == Ops.end()) + if (!llvm::is_contained(Ops, &Op)) return true; } return false; diff --git a/llvm/lib/CodeGen/ReplaceWithVeclib.cpp b/llvm/lib/CodeGen/ReplaceWithVeclib.cpp index 56025aa5c45..432c63fb65f 100644 --- a/llvm/lib/CodeGen/ReplaceWithVeclib.cpp +++ b/llvm/lib/CodeGen/ReplaceWithVeclib.cpp @@ -25,6 +25,7 @@ #include "llvm/IR/DerivedTypes.h" #include "llvm/IR/IRBuilder.h" #include "llvm/IR/InstIterator.h" +#include "llvm/IR/VFABIDemangler.h" #include "llvm/Support/TypeSize.h" #include "llvm/Transforms/Utils/ModuleUtils.h" @@ -111,7 +112,8 @@ static bool replaceWithCallToVeclib(const TargetLibraryInfo &TLI, SmallVector ScalarArgTypes; std::string ScalarName; Function *FuncToReplace = nullptr; - if (auto *CI = dyn_cast(&I)) { + auto *CI = dyn_cast(&I); + if (CI) { FuncToReplace = CI->getCalledFunction(); Intrinsic::ID IID = FuncToReplace->getIntrinsicID(); assert(IID != Intrinsic::not_intrinsic && "Not an intrinsic"); @@ -168,12 +170,36 @@ static bool replaceWithCallToVeclib(const TargetLibraryInfo &TLI, if (!OptInfo) return false; + // There is no guarantee that the vectorized instructions followed the VFABI + // specification when being created, this is why we need to add extra check to + // make sure that the operands of the vector function obtained via VFABI match + // the operands of the original vector instruction. + if (CI) { + for (auto VFParam : OptInfo->Shape.Parameters) { + if (VFParam.ParamKind == VFParamKind::GlobalPredicate) + continue; + + // tryDemangleForVFABI must return valid ParamPos, otherwise it could be + // a bug in the VFABI parser. + assert(VFParam.ParamPos < CI->arg_size() && + "ParamPos has invalid range."); + Type *OrigTy = CI->getArgOperand(VFParam.ParamPos)->getType(); + if (OrigTy->isVectorTy() != (VFParam.ParamKind == VFParamKind::Vector)) { + LLVM_DEBUG(dbgs() << DEBUG_TYPE << ": Will not replace: " << ScalarName + << ". Wrong type at index " << VFParam.ParamPos + << ": " << *OrigTy << "\n"); + return false; + } + } + } + FunctionType *VectorFTy = VFABI::createFunctionType(*OptInfo, ScalarFTy); if (!VectorFTy) return false; Function *TLIFunc = getTLIFunction(I.getModule(), VectorFTy, VD->getVectorFnName(), FuncToReplace); + replaceWithTLIFunction(I, *OptInfo, TLIFunc); LLVM_DEBUG(dbgs() << DEBUG_TYPE << ": Replaced call to `" << ScalarName << "` with call to `" << TLIFunc->getName() << "`.\n"); @@ -220,6 +246,9 @@ PreservedAnalyses ReplaceWithVeclib::run(Function &F, const TargetLibraryInfo &TLI = AM.getResult(F); auto Changed = runImpl(TLI, F); if (Changed) { + LLVM_DEBUG(dbgs() << "Instructions replaced with vector libraries: " + << NumCallsReplaced << "\n"); + PreservedAnalyses PA; PA.preserveSet(); PA.preserve(); diff --git a/llvm/lib/CodeGen/SafeStack.cpp b/llvm/lib/CodeGen/SafeStack.cpp index 88db57ad46b..0a26247a4d1 100644 --- a/llvm/lib/CodeGen/SafeStack.cpp +++ b/llvm/lib/CodeGen/SafeStack.cpp @@ -119,7 +119,6 @@ class SafeStack { Type *StackPtrTy; Type *IntPtrTy; Type *Int32Ty; - Type *Int8Ty; Value *UnsafeStackPtr = nullptr; @@ -195,8 +194,7 @@ public: : F(F), TL(TL), DL(DL), DTU(DTU), SE(SE), StackPtrTy(PointerType::getUnqual(F.getContext())), IntPtrTy(DL.getIntPtrType(F.getContext())), - Int32Ty(Type::getInt32Ty(F.getContext())), - Int8Ty(Type::getInt8Ty(F.getContext())) {} + Int32Ty(Type::getInt32Ty(F.getContext())) {} // Run the transformation on the associated function. // Returns whether the function was changed. @@ -562,8 +560,8 @@ Value *SafeStack::moveStaticAllocasToUnsafeStack( if (StackGuardSlot) { unsigned Offset = SSL.getObjectOffset(StackGuardSlot); - Value *Off = IRB.CreateGEP(Int8Ty, BasePointer, // BasePointer is i8* - ConstantInt::get(Int32Ty, -Offset)); + Value *Off = + IRB.CreatePtrAdd(BasePointer, ConstantInt::get(Int32Ty, -Offset)); Value *NewAI = IRB.CreateBitCast(Off, StackGuardSlot->getType(), "StackGuardSlot"); @@ -581,10 +579,10 @@ Value *SafeStack::moveStaticAllocasToUnsafeStack( if (Size == 0) Size = 1; // Don't create zero-sized stack objects. - Value *Off = IRB.CreateGEP(Int8Ty, BasePointer, // BasePointer is i8* - ConstantInt::get(Int32Ty, -Offset)); + Value *Off = + IRB.CreatePtrAdd(BasePointer, ConstantInt::get(Int32Ty, -Offset)); Value *NewArg = IRB.CreateBitCast(Off, Arg->getType(), - Arg->getName() + ".unsafe-byval"); + Arg->getName() + ".unsafe-byval"); // Replace alloc with the new location. replaceDbgDeclare(Arg, BasePointer, DIB, DIExpression::ApplyOffset, @@ -616,8 +614,8 @@ Value *SafeStack::moveStaticAllocasToUnsafeStack( InsertBefore = User; IRBuilder<> IRBUser(InsertBefore); - Value *Off = IRBUser.CreateGEP(Int8Ty, BasePointer, // BasePointer is i8* - ConstantInt::get(Int32Ty, -Offset)); + Value *Off = + IRBUser.CreatePtrAdd(BasePointer, ConstantInt::get(Int32Ty, -Offset)); Value *Replacement = IRBUser.CreateBitCast(Off, AI->getType(), Name); if (auto *PHI = dyn_cast(User)) @@ -647,8 +645,8 @@ Value *SafeStack::moveStaticAllocasToUnsafeStack( IRB.SetInsertPoint(BasePointer->getNextNode()); Value *StaticTop = - IRB.CreateGEP(Int8Ty, BasePointer, ConstantInt::get(Int32Ty, -FrameSize), - "unsafe_stack_static_top"); + IRB.CreatePtrAdd(BasePointer, ConstantInt::get(Int32Ty, -FrameSize), + "unsafe_stack_static_top"); IRB.CreateStore(StaticTop, UnsafeStackPtr); return StaticTop; } diff --git a/llvm/lib/CodeGen/SelectOptimize.cpp b/llvm/lib/CodeGen/SelectOptimize.cpp index 1316919e65d..9c720864358 100644 --- a/llvm/lib/CodeGen/SelectOptimize.cpp +++ b/llvm/lib/CodeGen/SelectOptimize.cpp @@ -42,6 +42,7 @@ #include using namespace llvm; +using namespace llvm::PatternMatch; #define DEBUG_TYPE "select-optimize" @@ -114,12 +115,6 @@ public: PreservedAnalyses run(Function &F, FunctionAnalysisManager &FAM); bool runOnFunction(Function &F, Pass &P); -private: - // Select groups consist of consecutive select instructions with the same - // condition. - using SelectGroup = SmallVector; - using SelectGroups = SmallVector; - using Scaled64 = ScaledNumber; struct CostInfo { @@ -129,6 +124,145 @@ private: Scaled64 NonPredCost; }; + /// SelectLike is an abstraction over SelectInst and other operations that can + /// act like selects. For example Or(Zext(icmp), X) can be treated like + /// select(icmp, X|1, X). + class SelectLike { + SelectLike(Instruction *I) : I(I) {} + + Instruction *I; + + public: + /// Match a select or select-like instruction, returning a SelectLike. + static SelectLike match(Instruction *I) { + // Select instruction are what we are usually looking for. + if (isa(I)) + return SelectLike(I); + + // An Or(zext(i1 X), Y) can also be treated like a select, with condition + // C and values Y|1 and Y. + Value *X; + if (PatternMatch::match( + I, m_c_Or(m_OneUse(m_ZExt(m_Value(X))), m_Value())) && + X->getType()->isIntegerTy(1)) + return SelectLike(I); + + return SelectLike(nullptr); + } + + bool isValid() { return I; } + operator bool() { return isValid(); } + + Instruction *getI() { return I; } + const Instruction *getI() const { return I; } + + Type *getType() const { return I->getType(); } + + /// Return the condition for the SelectLike instruction. For example the + /// condition of a select or c in `or(zext(c), x)` + Value *getCondition() const { + if (auto *Sel = dyn_cast(I)) + return Sel->getCondition(); + // Or(zext) case + if (auto *BO = dyn_cast(I)) { + Value *X; + if (PatternMatch::match(BO->getOperand(0), + m_OneUse(m_ZExt(m_Value(X))))) + return X; + if (PatternMatch::match(BO->getOperand(1), + m_OneUse(m_ZExt(m_Value(X))))) + return X; + } + + llvm_unreachable("Unhandled case in getCondition"); + } + + /// Return the true value for the SelectLike instruction. Note this may not + /// exist for all SelectLike instructions. For example, for `or(zext(c), x)` + /// the true value would be `or(x,1)`. As this value does not exist, nullptr + /// is returned. + Value *getTrueValue() const { + if (auto *Sel = dyn_cast(I)) + return Sel->getTrueValue(); + // Or(zext) case - The true value is Or(X), so return nullptr as the value + // does not yet exist. + if (isa(I)) + return nullptr; + + llvm_unreachable("Unhandled case in getTrueValue"); + } + + /// Return the false value for the SelectLike instruction. For example the + /// getFalseValue of a select or `x` in `or(zext(c), x)` (which is + /// `select(c, x|1, x)`) + Value *getFalseValue() const { + if (auto *Sel = dyn_cast(I)) + return Sel->getFalseValue(); + // Or(zext) case - return the operand which is not the zext. + if (auto *BO = dyn_cast(I)) { + Value *X; + if (PatternMatch::match(BO->getOperand(0), + m_OneUse(m_ZExt(m_Value(X))))) + return BO->getOperand(1); + if (PatternMatch::match(BO->getOperand(1), + m_OneUse(m_ZExt(m_Value(X))))) + return BO->getOperand(0); + } + + llvm_unreachable("Unhandled case in getFalseValue"); + } + + /// Return the NonPredCost cost of the true op, given the costs in + /// InstCostMap. This may need to be generated for select-like instructions. + Scaled64 getTrueOpCost(DenseMap &InstCostMap, + const TargetTransformInfo *TTI) { + if (auto *Sel = dyn_cast(I)) + if (auto *I = dyn_cast(Sel->getTrueValue())) + return InstCostMap.contains(I) ? InstCostMap[I].NonPredCost + : Scaled64::getZero(); + + // Or case - add the cost of an extra Or to the cost of the False case. + if (isa(I)) + if (auto I = dyn_cast(getFalseValue())) + if (InstCostMap.contains(I)) { + InstructionCost OrCost = TTI->getArithmeticInstrCost( + Instruction::Or, I->getType(), TargetTransformInfo::TCK_Latency, + {TargetTransformInfo::OK_AnyValue, + TargetTransformInfo::OP_None}, + {TTI::OK_UniformConstantValue, TTI::OP_PowerOf2}); + return InstCostMap[I].NonPredCost + + Scaled64::get(*OrCost.getValue()); + } + + return Scaled64::getZero(); + } + + /// Return the NonPredCost cost of the false op, given the costs in + /// InstCostMap. This may need to be generated for select-like instructions. + Scaled64 + getFalseOpCost(DenseMap &InstCostMap, + const TargetTransformInfo *TTI) { + if (auto *Sel = dyn_cast(I)) + if (auto *I = dyn_cast(Sel->getFalseValue())) + return InstCostMap.contains(I) ? InstCostMap[I].NonPredCost + : Scaled64::getZero(); + + // Or case - return the cost of the false case + if (isa(I)) + if (auto I = dyn_cast(getFalseValue())) + if (InstCostMap.contains(I)) + return InstCostMap[I].NonPredCost; + + return Scaled64::getZero(); + } + }; + +private: + // Select groups consist of consecutive select instructions with the same + // condition. + using SelectGroup = SmallVector; + using SelectGroups = SmallVector; + // Converts select instructions of a function to conditional jumps when deemed // profitable. Returns true if at least one select was converted. bool optimizeSelects(Function &F); @@ -156,12 +290,12 @@ private: // Determines if a select group should be converted to a branch (base // heuristics). - bool isConvertToBranchProfitableBase(const SmallVector &ASI); + bool isConvertToBranchProfitableBase(const SelectGroup &ASI); // Returns true if there are expensive instructions in the cold value // operand's (if any) dependence slice of any of the selects of the given // group. - bool hasExpensiveColdOperand(const SmallVector &ASI); + bool hasExpensiveColdOperand(const SelectGroup &ASI); // For a given source instruction, collect its backwards dependence slice // consisting of instructions exclusively computed for producing the operands @@ -170,7 +304,7 @@ private: Instruction *SI, bool ForSinking = false); // Returns true if the condition of the select is highly predictable. - bool isSelectHighlyPredictable(const SelectInst *SI); + bool isSelectHighlyPredictable(const SelectLike SI); // Loop-level checks to determine if a non-predicated version (with branches) // of the given loop is more profitable than its predicated version. @@ -183,20 +317,21 @@ private: CostInfo *LoopCost); // Returns a set of all the select instructions in the given select groups. - SmallPtrSet getSIset(const SelectGroups &SIGroups); + SmallDenseMap + getSImap(const SelectGroups &SIGroups); // Returns the latency cost of a given instruction. std::optional computeInstCost(const Instruction *I); // Returns the misprediction cost of a given select when converted to branch. - Scaled64 getMispredictionCost(const SelectInst *SI, const Scaled64 CondCost); + Scaled64 getMispredictionCost(const SelectLike SI, const Scaled64 CondCost); // Returns the cost of a branch when the prediction is correct. Scaled64 getPredictedPathCost(Scaled64 TrueCost, Scaled64 FalseCost, - const SelectInst *SI); + const SelectLike SI); // Returns true if the target architecture supports lowering a given select. - bool isSelectKindSupported(SelectInst *SI); + bool isSelectKindSupported(const SelectLike SI); }; class SelectOptimize : public FunctionPass { @@ -368,15 +503,26 @@ void SelectOptimizeImpl::optimizeSelectsInnerLoops(Function &F, /// select instructions in \p Selects, look through the defining select /// instruction until the true/false value is not defined in \p Selects. static Value * -getTrueOrFalseValue(SelectInst *SI, bool isTrue, - const SmallPtrSet &Selects) { +getTrueOrFalseValue(SelectOptimizeImpl::SelectLike SI, bool isTrue, + const SmallPtrSet &Selects, + IRBuilder<> &IB) { Value *V = nullptr; - for (SelectInst *DefSI = SI; DefSI != nullptr && Selects.count(DefSI); + for (SelectInst *DefSI = dyn_cast(SI.getI()); + DefSI != nullptr && Selects.count(DefSI); DefSI = dyn_cast(V)) { - assert(DefSI->getCondition() == SI->getCondition() && + assert(DefSI->getCondition() == SI.getCondition() && "The condition of DefSI does not match with SI"); V = (isTrue ? DefSI->getTrueValue() : DefSI->getFalseValue()); } + + if (isa(SI.getI())) { + assert(SI.getI()->getOpcode() == Instruction::Or && + "Only currently handling Or instructions."); + V = SI.getFalseValue(); + if (isTrue) + V = IB.CreateOr(V, ConstantInt::get(V->getType(), 1)); + } + assert(V && "Failed to get select true/false value"); return V; } @@ -424,20 +570,22 @@ void SelectOptimizeImpl::convertProfitableSIGroups(SelectGroups &ProfSIGroups) { SmallVector, 2> TrueSlices, FalseSlices; typedef std::stack::size_type StackSizeType; StackSizeType maxTrueSliceLen = 0, maxFalseSliceLen = 0; - for (SelectInst *SI : ASI) { + for (SelectLike SI : ASI) { // For each select, compute the sinkable dependence chains of the true and // false operands. - if (auto *TI = dyn_cast(SI->getTrueValue())) { + if (auto *TI = dyn_cast_or_null(SI.getTrueValue())) { std::stack TrueSlice; - getExclBackwardsSlice(TI, TrueSlice, SI, true); + getExclBackwardsSlice(TI, TrueSlice, SI.getI(), true); maxTrueSliceLen = std::max(maxTrueSliceLen, TrueSlice.size()); TrueSlices.push_back(TrueSlice); } - if (auto *FI = dyn_cast(SI->getFalseValue())) { - std::stack FalseSlice; - getExclBackwardsSlice(FI, FalseSlice, SI, true); - maxFalseSliceLen = std::max(maxFalseSliceLen, FalseSlice.size()); - FalseSlices.push_back(FalseSlice); + if (auto *FI = dyn_cast_or_null(SI.getFalseValue())) { + if (isa(SI.getI()) || !FI->hasOneUse()) { + std::stack FalseSlice; + getExclBackwardsSlice(FI, FalseSlice, SI.getI(), true); + maxFalseSliceLen = std::max(maxFalseSliceLen, FalseSlice.size()); + FalseSlices.push_back(FalseSlice); + } } } // In the case of multiple select instructions in the same group, the order @@ -469,10 +617,10 @@ void SelectOptimizeImpl::convertProfitableSIGroups(SelectGroups &ProfSIGroups) { } // We split the block containing the select(s) into two blocks. - SelectInst *SI = ASI.front(); - SelectInst *LastSI = ASI.back(); - BasicBlock *StartBlock = SI->getParent(); - BasicBlock::iterator SplitPt = ++(BasicBlock::iterator(LastSI)); + SelectLike SI = ASI.front(); + SelectLike LastSI = ASI.back(); + BasicBlock *StartBlock = SI.getI()->getParent(); + BasicBlock::iterator SplitPt = ++(BasicBlock::iterator(LastSI.getI())); BasicBlock *EndBlock = StartBlock->splitBasicBlock(SplitPt, "select.end"); BFI->setBlockFreq(EndBlock, BFI->getBlockFreq(StartBlock)); // Delete the unconditional branch that was just created by the split. @@ -481,8 +629,8 @@ void SelectOptimizeImpl::convertProfitableSIGroups(SelectGroups &ProfSIGroups) { // Move any debug/pseudo instructions that were in-between the select // group to the newly-created end block. SmallVector DebugPseudoINS; - auto DIt = SI->getIterator(); - while (&*DIt != LastSI) { + auto DIt = SI.getI()->getIterator(); + while (&*DIt != LastSI.getI()) { if (DIt->isDebugOrPseudoInst()) DebugPseudoINS.push_back(&*DIt); DIt++; @@ -491,23 +639,41 @@ void SelectOptimizeImpl::convertProfitableSIGroups(SelectGroups &ProfSIGroups) { DI->moveBeforePreserving(&*EndBlock->getFirstInsertionPt()); } + // Duplicate implementation for DPValues, the non-instruction debug-info + // record. Helper lambda for moving DPValues to the end block. + auto TransferDPValues = [&](Instruction &I) { + for (auto &DPValue : llvm::make_early_inc_range(I.getDbgValueRange())) { + DPValue.removeFromParent(); + EndBlock->insertDPValueBefore(&DPValue, + EndBlock->getFirstInsertionPt()); + } + }; + + // Iterate over all instructions in between SI and LastSI, not including + // SI itself. These are all the variable assignments that happen "in the + // middle" of the select group. + auto R = make_range(std::next(SI.getI()->getIterator()), + std::next(LastSI.getI()->getIterator())); + llvm::for_each(R, TransferDPValues); + // These are the new basic blocks for the conditional branch. // At least one will become an actual new basic block. BasicBlock *TrueBlock = nullptr, *FalseBlock = nullptr; BranchInst *TrueBranch = nullptr, *FalseBranch = nullptr; if (!TrueSlicesInterleaved.empty()) { - TrueBlock = BasicBlock::Create(LastSI->getContext(), "select.true.sink", + TrueBlock = BasicBlock::Create(EndBlock->getContext(), "select.true.sink", EndBlock->getParent(), EndBlock); TrueBranch = BranchInst::Create(EndBlock, TrueBlock); - TrueBranch->setDebugLoc(LastSI->getDebugLoc()); + TrueBranch->setDebugLoc(LastSI.getI()->getDebugLoc()); for (Instruction *TrueInst : TrueSlicesInterleaved) TrueInst->moveBefore(TrueBranch); } if (!FalseSlicesInterleaved.empty()) { - FalseBlock = BasicBlock::Create(LastSI->getContext(), "select.false.sink", - EndBlock->getParent(), EndBlock); + FalseBlock = + BasicBlock::Create(EndBlock->getContext(), "select.false.sink", + EndBlock->getParent(), EndBlock); FalseBranch = BranchInst::Create(EndBlock, FalseBlock); - FalseBranch->setDebugLoc(LastSI->getDebugLoc()); + FalseBranch->setDebugLoc(LastSI.getI()->getDebugLoc()); for (Instruction *FalseInst : FalseSlicesInterleaved) FalseInst->moveBefore(FalseBranch); } @@ -517,10 +683,10 @@ void SelectOptimizeImpl::convertProfitableSIGroups(SelectGroups &ProfSIGroups) { assert(TrueBlock == nullptr && "Unexpected basic block transform while optimizing select"); - FalseBlock = BasicBlock::Create(SI->getContext(), "select.false", + FalseBlock = BasicBlock::Create(StartBlock->getContext(), "select.false", EndBlock->getParent(), EndBlock); auto *FalseBranch = BranchInst::Create(EndBlock, FalseBlock); - FalseBranch->setDebugLoc(SI->getDebugLoc()); + FalseBranch->setDebugLoc(SI.getI()->getDebugLoc()); } // Insert the real conditional branch based on the original condition. @@ -541,67 +707,67 @@ void SelectOptimizeImpl::convertProfitableSIGroups(SelectGroups &ProfSIGroups) { TT = TrueBlock; FT = FalseBlock; } - IRBuilder<> IB(SI); - auto *CondFr = - IB.CreateFreeze(SI->getCondition(), SI->getName() + ".frozen"); - IB.CreateCondBr(CondFr, TT, FT, SI); + IRBuilder<> IB(SI.getI()); + auto *CondFr = IB.CreateFreeze(SI.getCondition(), + SI.getCondition()->getName() + ".frozen"); SmallPtrSet INS; - INS.insert(ASI.begin(), ASI.end()); + for (auto SI : ASI) + INS.insert(SI.getI()); + // Use reverse iterator because later select may use the value of the // earlier select, and we need to propagate value through earlier select // to get the PHI operand. for (auto It = ASI.rbegin(); It != ASI.rend(); ++It) { - SelectInst *SI = *It; + SelectLike SI = *It; // The select itself is replaced with a PHI Node. - PHINode *PN = PHINode::Create(SI->getType(), 2, ""); + PHINode *PN = PHINode::Create(SI.getType(), 2, ""); PN->insertBefore(EndBlock->begin()); - PN->takeName(SI); - PN->addIncoming(getTrueOrFalseValue(SI, true, INS), TrueBlock); - PN->addIncoming(getTrueOrFalseValue(SI, false, INS), FalseBlock); - PN->setDebugLoc(SI->getDebugLoc()); - - SI->replaceAllUsesWith(PN); - SI->eraseFromParent(); - INS.erase(SI); + PN->takeName(SI.getI()); + PN->addIncoming(getTrueOrFalseValue(SI, true, INS, IB), TrueBlock); + PN->addIncoming(getTrueOrFalseValue(SI, false, INS, IB), FalseBlock); + PN->setDebugLoc(SI.getI()->getDebugLoc()); + SI.getI()->replaceAllUsesWith(PN); + INS.erase(SI.getI()); ++NumSelectsConverted; } + IB.CreateCondBr(CondFr, TT, FT, SI.getI()); + + // Remove the old select instructions, now that they are not longer used. + for (auto SI : ASI) + SI.getI()->eraseFromParent(); } } -static bool isSpecialSelect(SelectInst *SI) { - using namespace llvm::PatternMatch; - - // If the select is a logical-and/logical-or then it is better treated as a - // and/or by the backend. - if (match(SI, m_CombineOr(m_LogicalAnd(m_Value(), m_Value()), - m_LogicalOr(m_Value(), m_Value())))) - return true; - - return false; -} - void SelectOptimizeImpl::collectSelectGroups(BasicBlock &BB, SelectGroups &SIGroups) { BasicBlock::iterator BBIt = BB.begin(); while (BBIt != BB.end()) { Instruction *I = &*BBIt++; - if (SelectInst *SI = dyn_cast(I)) { - if (isSpecialSelect(SI)) + if (SelectLike SI = SelectLike::match(I)) { + if (!TTI->shouldTreatInstructionLikeSelect(I)) continue; SelectGroup SIGroup; SIGroup.push_back(SI); while (BBIt != BB.end()) { Instruction *NI = &*BBIt; - SelectInst *NSI = dyn_cast(NI); - if (NSI && SI->getCondition() == NSI->getCondition()) { - SIGroup.push_back(NSI); - } else if (!NI->isDebugOrPseudoInst()) { - // Debug/pseudo instructions should be skipped and not prevent the - // formation of a select group. - break; + // Debug/pseudo instructions should be skipped and not prevent the + // formation of a select group. + if (NI->isDebugOrPseudoInst()) { + ++BBIt; + continue; } + // We only allow selects in the same group, not other select-like + // instructions. + if (!isa(NI)) + break; + + SelectLike NSI = SelectLike::match(NI); + if (NSI && SI.getCondition() == NSI.getCondition()) { + SIGroup.push_back(NSI); + } else + break; ++BBIt; } @@ -655,12 +821,12 @@ void SelectOptimizeImpl::findProfitableSIGroupsInnerLoops( // Assuming infinite resources, the cost of a group of instructions is the // cost of the most expensive instruction of the group. Scaled64 SelectCost = Scaled64::getZero(), BranchCost = Scaled64::getZero(); - for (SelectInst *SI : ASI) { - SelectCost = std::max(SelectCost, InstCostMap[SI].PredCost); - BranchCost = std::max(BranchCost, InstCostMap[SI].NonPredCost); + for (SelectLike SI : ASI) { + SelectCost = std::max(SelectCost, InstCostMap[SI.getI()].PredCost); + BranchCost = std::max(BranchCost, InstCostMap[SI.getI()].NonPredCost); } if (BranchCost < SelectCost) { - OptimizationRemark OR(DEBUG_TYPE, "SelectOpti", ASI.front()); + OptimizationRemark OR(DEBUG_TYPE, "SelectOpti", ASI.front().getI()); OR << "Profitable to convert to branch (loop analysis). BranchCost=" << BranchCost.toString() << ", SelectCost=" << SelectCost.toString() << ". "; @@ -668,7 +834,8 @@ void SelectOptimizeImpl::findProfitableSIGroupsInnerLoops( ++NumSelectConvertedLoop; ProfSIGroups.push_back(ASI); } else { - OptimizationRemarkMissed ORmiss(DEBUG_TYPE, "SelectOpti", ASI.front()); + OptimizationRemarkMissed ORmiss(DEBUG_TYPE, "SelectOpti", + ASI.front().getI()); ORmiss << "Select is more profitable (loop analysis). BranchCost=" << BranchCost.toString() << ", SelectCost=" << SelectCost.toString() << ". "; @@ -678,14 +845,15 @@ void SelectOptimizeImpl::findProfitableSIGroupsInnerLoops( } bool SelectOptimizeImpl::isConvertToBranchProfitableBase( - const SmallVector &ASI) { - SelectInst *SI = ASI.front(); - LLVM_DEBUG(dbgs() << "Analyzing select group containing " << *SI << "\n"); - OptimizationRemark OR(DEBUG_TYPE, "SelectOpti", SI); - OptimizationRemarkMissed ORmiss(DEBUG_TYPE, "SelectOpti", SI); + const SelectGroup &ASI) { + SelectLike SI = ASI.front(); + LLVM_DEBUG(dbgs() << "Analyzing select group containing " << SI.getI() + << "\n"); + OptimizationRemark OR(DEBUG_TYPE, "SelectOpti", SI.getI()); + OptimizationRemarkMissed ORmiss(DEBUG_TYPE, "SelectOpti", SI.getI()); // Skip cold basic blocks. Better to optimize for size for cold blocks. - if (PSI->isColdBlock(SI->getParent(), BFI)) { + if (PSI->isColdBlock(SI.getI()->getParent(), BFI)) { ++NumSelectColdBB; ORmiss << "Not converted to branch because of cold basic block. "; EmitAndPrintRemark(ORE, ORmiss); @@ -693,7 +861,7 @@ bool SelectOptimizeImpl::isConvertToBranchProfitableBase( } // If unpredictable, branch form is less profitable. - if (SI->getMetadata(LLVMContext::MD_unpredictable)) { + if (SI.getI()->getMetadata(LLVMContext::MD_unpredictable)) { ++NumSelectUnPred; ORmiss << "Not converted to branch because of unpredictable branch. "; EmitAndPrintRemark(ORE, ORmiss); @@ -728,17 +896,24 @@ static InstructionCost divideNearest(InstructionCost Numerator, return (Numerator + (Denominator / 2)) / Denominator; } -bool SelectOptimizeImpl::hasExpensiveColdOperand( - const SmallVector &ASI) { +static bool extractBranchWeights(const SelectOptimizeImpl::SelectLike SI, + uint64_t &TrueVal, uint64_t &FalseVal) { + if (isa(SI.getI())) + return extractBranchWeights(*SI.getI(), TrueVal, FalseVal); + return false; +} + +bool SelectOptimizeImpl::hasExpensiveColdOperand(const SelectGroup &ASI) { bool ColdOperand = false; uint64_t TrueWeight, FalseWeight, TotalWeight; - if (extractBranchWeights(*ASI.front(), TrueWeight, FalseWeight)) { + if (extractBranchWeights(ASI.front(), TrueWeight, FalseWeight)) { uint64_t MinWeight = std::min(TrueWeight, FalseWeight); TotalWeight = TrueWeight + FalseWeight; // Is there a path with frequency 100 * MinWeight; } else if (PSI->hasProfileSummary()) { - OptimizationRemarkMissed ORmiss(DEBUG_TYPE, "SelectOpti", ASI.front()); + OptimizationRemarkMissed ORmiss(DEBUG_TYPE, "SelectOpti", + ASI.front().getI()); ORmiss << "Profile data available but missing branch-weights metadata for " "select instruction. "; EmitAndPrintRemark(ORE, ORmiss); @@ -747,19 +922,19 @@ bool SelectOptimizeImpl::hasExpensiveColdOperand( return false; // Check if the cold path's dependence slice is expensive for any of the // selects of the group. - for (SelectInst *SI : ASI) { + for (SelectLike SI : ASI) { Instruction *ColdI = nullptr; uint64_t HotWeight; if (TrueWeight < FalseWeight) { - ColdI = dyn_cast(SI->getTrueValue()); + ColdI = dyn_cast_or_null(SI.getTrueValue()); HotWeight = FalseWeight; } else { - ColdI = dyn_cast(SI->getFalseValue()); + ColdI = dyn_cast_or_null(SI.getFalseValue()); HotWeight = TrueWeight; } if (ColdI) { std::stack ColdSlice; - getExclBackwardsSlice(ColdI, ColdSlice, SI); + getExclBackwardsSlice(ColdI, ColdSlice, SI.getI()); InstructionCost SliceCost = 0; while (!ColdSlice.empty()) { SliceCost += TTI->getInstructionCost(ColdSlice.top(), @@ -849,9 +1024,9 @@ void SelectOptimizeImpl::getExclBackwardsSlice(Instruction *I, } } -bool SelectOptimizeImpl::isSelectHighlyPredictable(const SelectInst *SI) { +bool SelectOptimizeImpl::isSelectHighlyPredictable(const SelectLike SI) { uint64_t TrueWeight, FalseWeight; - if (extractBranchWeights(*SI, TrueWeight, FalseWeight)) { + if (extractBranchWeights(SI, TrueWeight, FalseWeight)) { uint64_t Max = std::max(TrueWeight, FalseWeight); uint64_t Sum = TrueWeight + FalseWeight; if (Sum != 0) { @@ -937,7 +1112,7 @@ bool SelectOptimizeImpl::computeLoopCosts( DenseMap &InstCostMap, CostInfo *LoopCost) { LLVM_DEBUG(dbgs() << "Calculating Latency / IPredCost / INonPredCost of loop " << L->getHeader()->getName() << "\n"); - const auto &SIset = getSIset(SIGroups); + const auto &SImap = getSImap(SIGroups); // Compute instruction and loop-critical-path costs across two iterations for // both predicated and non-predicated version. const unsigned Iterations = 2; @@ -982,22 +1157,15 @@ bool SelectOptimizeImpl::computeLoopCosts( // BranchCost = PredictedPathCost + MispredictCost // PredictedPathCost = TrueOpCost * TrueProb + FalseOpCost * FalseProb // MispredictCost = max(MispredictPenalty, CondCost) * MispredictRate - if (SIset.contains(&I)) { - auto SI = cast(&I); - - Scaled64 TrueOpCost = Scaled64::getZero(), - FalseOpCost = Scaled64::getZero(); - if (auto *TI = dyn_cast(SI->getTrueValue())) - if (InstCostMap.count(TI)) - TrueOpCost = InstCostMap[TI].NonPredCost; - if (auto *FI = dyn_cast(SI->getFalseValue())) - if (InstCostMap.count(FI)) - FalseOpCost = InstCostMap[FI].NonPredCost; + if (SImap.contains(&I)) { + auto SI = SImap.at(&I); + Scaled64 TrueOpCost = SI.getTrueOpCost(InstCostMap, TTI); + Scaled64 FalseOpCost = SI.getFalseOpCost(InstCostMap, TTI); Scaled64 PredictedPathCost = getPredictedPathCost(TrueOpCost, FalseOpCost, SI); Scaled64 CondCost = Scaled64::getZero(); - if (auto *CI = dyn_cast(SI->getCondition())) + if (auto *CI = dyn_cast(SI.getCondition())) if (InstCostMap.count(CI)) CondCost = InstCostMap[CI].NonPredCost; Scaled64 MispredictCost = getMispredictionCost(SI, CondCost); @@ -1019,13 +1187,13 @@ bool SelectOptimizeImpl::computeLoopCosts( return true; } -SmallPtrSet -SelectOptimizeImpl::getSIset(const SelectGroups &SIGroups) { - SmallPtrSet SIset; +SmallDenseMap +SelectOptimizeImpl::getSImap(const SelectGroups &SIGroups) { + SmallDenseMap SImap; for (const SelectGroup &ASI : SIGroups) - for (const SelectInst *SI : ASI) - SIset.insert(SI); - return SIset; + for (SelectLike SI : ASI) + SImap.try_emplace(SI.getI(), SI); + return SImap; } std::optional @@ -1038,7 +1206,7 @@ SelectOptimizeImpl::computeInstCost(const Instruction *I) { } ScaledNumber -SelectOptimizeImpl::getMispredictionCost(const SelectInst *SI, +SelectOptimizeImpl::getMispredictionCost(const SelectLike SI, const Scaled64 CondCost) { uint64_t MispredictPenalty = TSchedModel.getMCSchedModel()->MispredictPenalty; @@ -1065,10 +1233,10 @@ SelectOptimizeImpl::getMispredictionCost(const SelectInst *SI, // TrueCost * TrueProbability + FalseCost * FalseProbability. ScaledNumber SelectOptimizeImpl::getPredictedPathCost(Scaled64 TrueCost, Scaled64 FalseCost, - const SelectInst *SI) { + const SelectLike SI) { Scaled64 PredPathCost; uint64_t TrueWeight, FalseWeight; - if (extractBranchWeights(*SI, TrueWeight, FalseWeight)) { + if (extractBranchWeights(SI, TrueWeight, FalseWeight)) { uint64_t SumWeight = TrueWeight + FalseWeight; if (SumWeight != 0) { PredPathCost = TrueCost * Scaled64::get(TrueWeight) + @@ -1085,12 +1253,12 @@ SelectOptimizeImpl::getPredictedPathCost(Scaled64 TrueCost, Scaled64 FalseCost, return PredPathCost; } -bool SelectOptimizeImpl::isSelectKindSupported(SelectInst *SI) { - bool VectorCond = !SI->getCondition()->getType()->isIntegerTy(1); +bool SelectOptimizeImpl::isSelectKindSupported(const SelectLike SI) { + bool VectorCond = !SI.getCondition()->getType()->isIntegerTy(1); if (VectorCond) return false; TargetLowering::SelectSupportKind SelectKind; - if (SI->getType()->isVectorTy()) + if (SI.getType()->isVectorTy()) SelectKind = TargetLowering::ScalarCondVectorVal; else SelectKind = TargetLowering::ScalarValSelect; diff --git a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp index ecdf9ab9e98..98d8a6d9409 100644 --- a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp @@ -58,6 +58,7 @@ #include "llvm/Support/CommandLine.h" #include "llvm/Support/Compiler.h" #include "llvm/Support/Debug.h" +#include "llvm/Support/DebugCounter.h" #include "llvm/Support/ErrorHandling.h" #include "llvm/Support/KnownBits.h" #include "llvm/Support/MathExtras.h" @@ -87,6 +88,9 @@ STATISTIC(LdStFP2Int , "Number of fp load/store pairs transformed to int"); STATISTIC(SlicedLoads, "Number of load sliced"); STATISTIC(NumFPLogicOpsConv, "Number of logic ops converted to fp ops"); +DEBUG_COUNTER(DAGCombineCounter, "dagcombine", + "Controls whether a DAG combine is performed for a node"); + static cl::opt CombinerGlobalAA("combiner-global-alias-analysis", cl::Hidden, cl::desc("Enable DAG combiner's use of IR alias analysis")); @@ -2076,6 +2080,9 @@ SDValue DAGCombiner::visit(SDNode *N) { } SDValue DAGCombiner::combine(SDNode *N) { + if (!DebugCounter::shouldExecute(DAGCombineCounter)) + return SDValue(); + SDValue RV; if (!DisableGenericCombines) RV = visit(N); @@ -26014,6 +26021,7 @@ SDValue DAGCombiner::visitSCALAR_TO_VECTOR(SDNode *N) { // Try to convert a scalar binop with an extracted vector element to a vector // binop. This is intended to reduce potentially expensive register moves. // TODO: Check if both operands are extracted. + // TODO: How to prefer scalar/vector ops with multiple uses of the extact? // TODO: Generalize this, so it can be called from visitINSERT_VECTOR_ELT(). SDValue Scalar = N->getOperand(0); unsigned Opcode = Scalar.getOpcode(); @@ -26022,6 +26030,8 @@ SDValue DAGCombiner::visitSCALAR_TO_VECTOR(SDNode *N) { TLI.isBinOp(Opcode) && Scalar.getValueType() == VecEltVT && Scalar.getOperand(0).getValueType() == VecEltVT && Scalar.getOperand(1).getValueType() == VecEltVT && + Scalar->isOnlyUserOf(Scalar.getOperand(0).getNode()) && + Scalar->isOnlyUserOf(Scalar.getOperand(1).getNode()) && DAG.isSafeToSpeculativelyExecute(Opcode) && hasOperation(Opcode, VT)) { // Match an extract element and get a shuffle mask equivalent. SmallVector ShufMask(VT.getVectorNumElements(), -1); diff --git a/llvm/lib/CodeGen/SelectionDAG/FastISel.cpp b/llvm/lib/CodeGen/SelectionDAG/FastISel.cpp index 6d80b282a1e..d213ea89de1 100644 --- a/llvm/lib/CodeGen/SelectionDAG/FastISel.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/FastISel.cpp @@ -2210,15 +2210,12 @@ Register FastISel::fastEmitZExtFromI1(MVT VT, unsigned Op0) { /// might result in multiple MBB's for one BB. As such, the start of the /// BB might correspond to a different MBB than the end. bool FastISel::handlePHINodesInSuccessorBlocks(const BasicBlock *LLVMBB) { - const Instruction *TI = LLVMBB->getTerminator(); - SmallPtrSet SuccsHandled; FuncInfo.OrigNumPHINodesToUpdate = FuncInfo.PHINodesToUpdate.size(); // Check successor nodes' PHI nodes that expect a constant to be available // from this block. - for (unsigned succ = 0, e = TI->getNumSuccessors(); succ != e; ++succ) { - const BasicBlock *SuccBB = TI->getSuccessor(succ); + for (const BasicBlock *SuccBB : successors(LLVMBB)) { if (!isa(SuccBB->begin())) continue; MachineBasicBlock *SuccMBB = FuncInfo.MBBMap[SuccBB]; diff --git a/llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp b/llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp index 296ed3a3c3d..adfeea073bf 100644 --- a/llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp @@ -3534,8 +3534,7 @@ bool SelectionDAGLegalize::ExpandNode(SDNode *Node) { Results.push_back(ExpandFABS(Node)); break; case ISD::IS_FPCLASS: { - auto CNode = cast(Node->getOperand(1)); - auto Test = static_cast(CNode->getZExtValue()); + auto Test = static_cast(Node->getConstantOperandVal(1)); if (SDValue Expanded = TLI.expandIS_FPCLASS(Node->getValueType(0), Node->getOperand(0), Test, Node->getFlags(), SDLoc(Node), DAG)) diff --git a/llvm/lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp b/llvm/lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp index 589fec0e56f..f0a04589fbf 100644 --- a/llvm/lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp @@ -522,8 +522,11 @@ SDValue DAGTypeLegalizer::SoftenFloatRes_FP_EXTEND(SDNode *N) { Op = GetPromotedFloat(Op); // If the promotion did the FP_EXTEND to the destination type for us, // there's nothing left to do here. - if (Op.getValueType() == N->getValueType(0)) + if (Op.getValueType() == N->getValueType(0)) { + if (IsStrict) + ReplaceValueWith(SDValue(N, 1), Chain); return BitConvertToInteger(Op); + } } // There's only a libcall for f16 -> f32 and shifting is only valid for bf16 @@ -541,8 +544,10 @@ SDValue DAGTypeLegalizer::SoftenFloatRes_FP_EXTEND(SDNode *N) { } } - if (Op.getValueType() == MVT::bf16) + if (Op.getValueType() == MVT::bf16) { + // FIXME: Need ReplaceValueWith on chain in strict case return SoftenFloatRes_BF16_TO_FP(N); + } RTLIB::Libcall LC = RTLIB::getFPEXT(Op.getValueType(), N->getValueType(0)); assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported FP_EXTEND!"); diff --git a/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp b/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp index c278bdc0736..7fc25260053 100644 --- a/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp @@ -1143,7 +1143,9 @@ void DAGTypeLegalizer::SplitVectorResult(SDNode *N, unsigned ResNo) { case ISD::FMINNUM: case ISD::VP_FMINNUM: case ISD::FMAXNUM: case ISD::VP_FMAXNUM: case ISD::FMINIMUM: + case ISD::VP_FMINIMUM: case ISD::FMAXIMUM: + case ISD::VP_FMAXIMUM: case ISD::SDIV: case ISD::VP_SDIV: case ISD::UDIV: case ISD::VP_UDIV: case ISD::FDIV: case ISD::VP_FDIV: @@ -4131,7 +4133,9 @@ void DAGTypeLegalizer::WidenVectorResult(SDNode *N, unsigned ResNo) { case ISD::FMINNUM: case ISD::VP_FMINNUM: case ISD::FMAXNUM: case ISD::VP_FMAXNUM: case ISD::FMINIMUM: + case ISD::VP_FMINIMUM: case ISD::FMAXIMUM: + case ISD::VP_FMAXIMUM: case ISD::SMIN: case ISD::VP_SMIN: case ISD::SMAX: case ISD::VP_SMAX: case ISD::UMIN: case ISD::VP_UMIN: diff --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp b/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp index 01d31806c84..9a22088d2c6 100644 --- a/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp @@ -2881,12 +2881,6 @@ bool SelectionDAG::isSplatValue(SDValue V, const APInt &DemandedElts, } } - // Fallback - this is a splat if all demanded elts are the same constant. - if (computeKnownBits(V, DemandedElts, Depth).isConstant()) { - UndefElts = ~DemandedElts; - return true; - } - return false; } @@ -5233,22 +5227,8 @@ bool SelectionDAG::isKnownNeverZeroFloat(SDValue Op) const { "Floating point type expected"); // If the value is a constant, we can obviously see if it is a zero or not. - if (const ConstantFPSDNode *C = dyn_cast(Op)) - return !C->isZero(); - - // Return false if we find any zero in a vector. - if (Op->getOpcode() == ISD::BUILD_VECTOR || - Op->getOpcode() == ISD::SPLAT_VECTOR) { - for (const SDValue &OpVal : Op->op_values()) { - if (OpVal.isUndef()) - return false; - if (auto *C = dyn_cast(OpVal)) - if (C->isZero()) - return false; - } - return true; - } - return false; + return ISD::matchUnaryFpPredicate( + Op, [](ConstantFPSDNode *C) { return !C->isZero(); }); } bool SelectionDAG::isKnownNeverZero(SDValue Op, unsigned Depth) const { diff --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp index 2c477b94743..5ce1013f30f 100644 --- a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp @@ -153,6 +153,7 @@ static const unsigned MaxParallelChains = 64; static SDValue getCopyFromPartsVector(SelectionDAG &DAG, const SDLoc &DL, const SDValue *Parts, unsigned NumParts, MVT PartVT, EVT ValueVT, const Value *V, + SDValue InChain, std::optional CC); /// getCopyFromParts - Create a value that contains the specified legal parts @@ -163,6 +164,7 @@ static SDValue getCopyFromPartsVector(SelectionDAG &DAG, const SDLoc &DL, static SDValue getCopyFromParts(SelectionDAG &DAG, const SDLoc &DL, const SDValue *Parts, unsigned NumParts, MVT PartVT, EVT ValueVT, const Value *V, + SDValue InChain, std::optional CC = std::nullopt, std::optional AssertOp = std::nullopt) { // Let the target assemble the parts if it wants to @@ -173,7 +175,7 @@ getCopyFromParts(SelectionDAG &DAG, const SDLoc &DL, const SDValue *Parts, if (ValueVT.isVector()) return getCopyFromPartsVector(DAG, DL, Parts, NumParts, PartVT, ValueVT, V, - CC); + InChain, CC); assert(NumParts > 0 && "No parts to assemble!"); SDValue Val = Parts[0]; @@ -194,10 +196,10 @@ getCopyFromParts(SelectionDAG &DAG, const SDLoc &DL, const SDValue *Parts, EVT HalfVT = EVT::getIntegerVT(*DAG.getContext(), RoundBits/2); if (RoundParts > 2) { - Lo = getCopyFromParts(DAG, DL, Parts, RoundParts / 2, - PartVT, HalfVT, V); - Hi = getCopyFromParts(DAG, DL, Parts + RoundParts / 2, - RoundParts / 2, PartVT, HalfVT, V); + Lo = getCopyFromParts(DAG, DL, Parts, RoundParts / 2, PartVT, HalfVT, V, + InChain); + Hi = getCopyFromParts(DAG, DL, Parts + RoundParts / 2, RoundParts / 2, + PartVT, HalfVT, V, InChain); } else { Lo = DAG.getNode(ISD::BITCAST, DL, HalfVT, Parts[0]); Hi = DAG.getNode(ISD::BITCAST, DL, HalfVT, Parts[1]); @@ -213,7 +215,7 @@ getCopyFromParts(SelectionDAG &DAG, const SDLoc &DL, const SDValue *Parts, unsigned OddParts = NumParts - RoundParts; EVT OddVT = EVT::getIntegerVT(*DAG.getContext(), OddParts * PartBits); Hi = getCopyFromParts(DAG, DL, Parts + RoundParts, OddParts, PartVT, - OddVT, V, CC); + OddVT, V, InChain, CC); // Combine the round and odd parts. Lo = Val; @@ -243,7 +245,8 @@ getCopyFromParts(SelectionDAG &DAG, const SDLoc &DL, const SDValue *Parts, assert(ValueVT.isFloatingPoint() && PartVT.isInteger() && !PartVT.isVector() && "Unexpected split"); EVT IntVT = EVT::getIntegerVT(*DAG.getContext(), ValueVT.getSizeInBits()); - Val = getCopyFromParts(DAG, DL, Parts, NumParts, PartVT, IntVT, V, CC); + Val = getCopyFromParts(DAG, DL, Parts, NumParts, PartVT, IntVT, V, + InChain, CC); } } @@ -283,10 +286,20 @@ getCopyFromParts(SelectionDAG &DAG, const SDLoc &DL, const SDValue *Parts, if (PartEVT.isFloatingPoint() && ValueVT.isFloatingPoint()) { // FP_ROUND's are always exact here. - if (ValueVT.bitsLT(Val.getValueType())) - return DAG.getNode( - ISD::FP_ROUND, DL, ValueVT, Val, - DAG.getTargetConstant(1, DL, TLI.getPointerTy(DAG.getDataLayout()))); + if (ValueVT.bitsLT(Val.getValueType())) { + + SDValue NoChange = + DAG.getTargetConstant(1, DL, TLI.getPointerTy(DAG.getDataLayout())); + + if (DAG.getMachineFunction().getFunction().getAttributes().hasFnAttr( + llvm::Attribute::StrictFP)) { + return DAG.getNode(ISD::STRICT_FP_ROUND, DL, + DAG.getVTList(ValueVT, MVT::Other), InChain, Val, + NoChange); + } + + return DAG.getNode(ISD::FP_ROUND, DL, ValueVT, Val, NoChange); + } return DAG.getNode(ISD::FP_EXTEND, DL, ValueVT, Val); } @@ -324,6 +337,7 @@ static void diagnosePossiblyInvalidConstraint(LLVMContext &Ctx, const Value *V, static SDValue getCopyFromPartsVector(SelectionDAG &DAG, const SDLoc &DL, const SDValue *Parts, unsigned NumParts, MVT PartVT, EVT ValueVT, const Value *V, + SDValue InChain, std::optional CallConv) { assert(ValueVT.isVector() && "Not a vector value"); assert(NumParts > 0 && "No parts to assemble!"); @@ -362,8 +376,8 @@ static SDValue getCopyFromPartsVector(SelectionDAG &DAG, const SDLoc &DL, // If the register was not expanded, truncate or copy the value, // as appropriate. for (unsigned i = 0; i != NumParts; ++i) - Ops[i] = getCopyFromParts(DAG, DL, &Parts[i], 1, - PartVT, IntermediateVT, V, CallConv); + Ops[i] = getCopyFromParts(DAG, DL, &Parts[i], 1, PartVT, IntermediateVT, + V, InChain, CallConv); } else if (NumParts > 0) { // If the intermediate type was expanded, build the intermediate // operands from the parts. @@ -371,8 +385,8 @@ static SDValue getCopyFromPartsVector(SelectionDAG &DAG, const SDLoc &DL, "Must expand into a divisible number of parts!"); unsigned Factor = NumParts / NumIntermediates; for (unsigned i = 0; i != NumIntermediates; ++i) - Ops[i] = getCopyFromParts(DAG, DL, &Parts[i * Factor], Factor, - PartVT, IntermediateVT, V, CallConv); + Ops[i] = getCopyFromParts(DAG, DL, &Parts[i * Factor], Factor, PartVT, + IntermediateVT, V, InChain, CallConv); } // Build a vector with BUILD_VECTOR or CONCAT_VECTORS from the @@ -926,7 +940,7 @@ SDValue RegsForValue::getCopyFromRegs(SelectionDAG &DAG, } Values[Value] = getCopyFromParts(DAG, dl, Parts.begin(), NumRegs, - RegisterVT, ValueVT, V, CallConv); + RegisterVT, ValueVT, V, Chain, CallConv); Part += NumRegs; Parts.clear(); } @@ -1227,6 +1241,11 @@ void SelectionDAGBuilder::visitDbgInfo(const Instruction &I) { It->Expr, Vals.size() > 1, It->DL, SDNodeOrder); } } + // We must early-exit here to prevent any DPValues from being emitted below, + // as we have just emitted the debug values resulting from assignment + // tracking analysis, making any existing DPValues redundant (and probably + // less correct). + return; } // Is there is any debug-info attached to this instruction, in the form of @@ -1535,6 +1554,11 @@ bool SelectionDAGBuilder::handleDebugValue(ArrayRef Values, unsigned Order, bool IsVariadic) { if (Values.empty()) return true; + + // Filter EntryValue locations out early. + if (visitEntryValueDbgValue(Values, Var, Expr, DbgLoc)) + return true; + SmallVector LocationOps; SmallVector Dependencies; for (const Value *V : Values) { @@ -6009,14 +6033,14 @@ static const CallBase *FindPreallocatedCall(const Value *PreallocatedSetup) { /// If DI is a debug value with an EntryValue expression, lower it using the /// corresponding physical register of the associated Argument value /// (guaranteed to exist by the verifier). -bool SelectionDAGBuilder::visitEntryValueDbgValue(const DbgValueInst &DI) { - DILocalVariable *Variable = DI.getVariable(); - DIExpression *Expr = DI.getExpression(); - if (!Expr->isEntryValue() || !hasSingleElement(DI.getValues())) +bool SelectionDAGBuilder::visitEntryValueDbgValue( + ArrayRef Values, DILocalVariable *Variable, + DIExpression *Expr, DebugLoc DbgLoc) { + if (!Expr->isEntryValue() || !hasSingleElement(Values)) return false; // These properties are guaranteed by the verifier. - Argument *Arg = cast(DI.getValue(0)); + const Argument *Arg = cast(Values[0]); assert(Arg->hasAttribute(Attribute::AttrKind::SwiftAsync)); auto ArgIt = FuncInfo.ValueMap.find(Arg); @@ -6030,9 +6054,8 @@ bool SelectionDAGBuilder::visitEntryValueDbgValue(const DbgValueInst &DI) { for (auto [PhysReg, VirtReg] : FuncInfo.RegInfo->liveins()) if (ArgVReg == VirtReg || ArgVReg == PhysReg) { - SDDbgValue *SDV = - DAG.getVRegDbgValue(Variable, Expr, PhysReg, false /*IsIndidrect*/, - DI.getDebugLoc(), SDNodeOrder); + SDDbgValue *SDV = DAG.getVRegDbgValue( + Variable, Expr, PhysReg, false /*IsIndidrect*/, DbgLoc, SDNodeOrder); DAG.AddDbgValue(SDV, false /*treat as dbg.declare byval parameter*/); return true; } @@ -6324,9 +6347,6 @@ void SelectionDAGBuilder::visitIntrinsicCall(const CallInst &I, DIExpression *Expression = DI.getExpression(); dropDanglingDebugInfo(Variable, Expression); - if (visitEntryValueDbgValue(DI)) - return; - if (DI.isKillLocation()) { handleKillDebugValue(Variable, Expression, DI.getDebugLoc(), SDNodeOrder); return; @@ -10628,9 +10648,9 @@ TargetLowering::LowerCallTo(TargetLowering::CallLoweringInfo &CLI) const { unsigned NumRegs = getNumRegistersForCallingConv(CLI.RetTy->getContext(), CLI.CallConv, VT); - ReturnValues.push_back(getCopyFromParts(CLI.DAG, CLI.DL, &InVals[CurReg], - NumRegs, RegisterVT, VT, nullptr, - CLI.CallConv, AssertOp)); + ReturnValues.push_back(getCopyFromParts( + CLI.DAG, CLI.DL, &InVals[CurReg], NumRegs, RegisterVT, VT, nullptr, + CLI.Chain, CLI.CallConv, AssertOp)); CurReg += NumRegs; } @@ -11109,8 +11129,9 @@ void SelectionDAGISel::LowerArguments(const Function &F) { MVT VT = ValueVTs[0].getSimpleVT(); MVT RegVT = TLI->getRegisterType(*CurDAG->getContext(), VT); std::optional AssertOp; - SDValue ArgValue = getCopyFromParts(DAG, dl, &InVals[0], 1, RegVT, VT, - nullptr, F.getCallingConv(), AssertOp); + SDValue ArgValue = + getCopyFromParts(DAG, dl, &InVals[0], 1, RegVT, VT, nullptr, NewRoot, + F.getCallingConv(), AssertOp); MachineFunction& MF = SDB->DAG.getMachineFunction(); MachineRegisterInfo& RegInfo = MF.getRegInfo(); @@ -11182,7 +11203,7 @@ void SelectionDAGISel::LowerArguments(const Function &F) { AssertOp = ISD::AssertZext; ArgValues.push_back(getCopyFromParts(DAG, dl, &InVals[i], NumParts, - PartVT, VT, nullptr, + PartVT, VT, nullptr, NewRoot, F.getCallingConv(), AssertOp)); } diff --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.h b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.h index 6dcb8c816ad..40e2f791f59 100644 --- a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.h +++ b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.h @@ -612,7 +612,9 @@ private: void visitInlineAsm(const CallBase &Call, const BasicBlock *EHPadBB = nullptr); - bool visitEntryValueDbgValue(const DbgValueInst &I); + bool visitEntryValueDbgValue(ArrayRef Values, + DILocalVariable *Variable, DIExpression *Expr, + DebugLoc DbgLoc); void visitIntrinsicCall(const CallInst &I, unsigned Intrinsic); void visitTargetIntrinsic(const CallInst &I, unsigned Intrinsic); void visitConstrainedFPIntrinsic(const ConstrainedFPIntrinsic &FPI); diff --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp index 678d273e4bd..359d738d2ca 100644 --- a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp @@ -2712,9 +2712,13 @@ CheckPatternPredicate(unsigned Opcode, const unsigned char *MatcherTable, /// CheckNodePredicate - Implements OP_CheckNodePredicate. LLVM_ATTRIBUTE_ALWAYS_INLINE static bool -CheckNodePredicate(const unsigned char *MatcherTable, unsigned &MatcherIndex, - const SelectionDAGISel &SDISel, SDNode *N) { - return SDISel.CheckNodePredicate(N, MatcherTable[MatcherIndex++]); +CheckNodePredicate(unsigned Opcode, const unsigned char *MatcherTable, + unsigned &MatcherIndex, const SelectionDAGISel &SDISel, + SDNode *N) { + unsigned PredNo = Opcode == SelectionDAGISel::OPC_CheckPredicate + ? MatcherTable[MatcherIndex++] + : Opcode - SelectionDAGISel::OPC_CheckPredicate0; + return SDISel.CheckNodePredicate(N, PredNo); } LLVM_ATTRIBUTE_ALWAYS_INLINE static bool @@ -2868,7 +2872,15 @@ static unsigned IsPredicateKnownToFail(const unsigned char *Table, Result = !::CheckPatternPredicate(Opcode, Table, Index, SDISel); return Index; case SelectionDAGISel::OPC_CheckPredicate: - Result = !::CheckNodePredicate(Table, Index, SDISel, N.getNode()); + case SelectionDAGISel::OPC_CheckPredicate0: + case SelectionDAGISel::OPC_CheckPredicate1: + case SelectionDAGISel::OPC_CheckPredicate2: + case SelectionDAGISel::OPC_CheckPredicate3: + case SelectionDAGISel::OPC_CheckPredicate4: + case SelectionDAGISel::OPC_CheckPredicate5: + case SelectionDAGISel::OPC_CheckPredicate6: + case SelectionDAGISel::OPC_CheckPredicate7: + Result = !::CheckNodePredicate(Opcode, Table, Index, SDISel, N.getNode()); return Index; case SelectionDAGISel::OPC_CheckOpcode: Result = !::CheckOpcode(Table, Index, N.getNode()); @@ -3359,8 +3371,16 @@ void SelectionDAGISel::SelectCodeCommon(SDNode *NodeToMatch, if (!::CheckPatternPredicate(Opcode, MatcherTable, MatcherIndex, *this)) break; continue; + case SelectionDAGISel::OPC_CheckPredicate0: + case SelectionDAGISel::OPC_CheckPredicate1: + case SelectionDAGISel::OPC_CheckPredicate2: + case SelectionDAGISel::OPC_CheckPredicate3: + case SelectionDAGISel::OPC_CheckPredicate4: + case SelectionDAGISel::OPC_CheckPredicate5: + case SelectionDAGISel::OPC_CheckPredicate6: + case SelectionDAGISel::OPC_CheckPredicate7: case OPC_CheckPredicate: - if (!::CheckNodePredicate(MatcherTable, MatcherIndex, *this, + if (!::CheckNodePredicate(Opcode, MatcherTable, MatcherIndex, *this, N.getNode())) break; continue; diff --git a/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp index 3bbef6e6d85..b8ed02e268b 100644 --- a/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp @@ -2483,8 +2483,12 @@ bool TargetLowering::SimplifyDemandedBits( if (Known.isNonNegative()) { unsigned Opc = IsVecInReg ? ISD::ZERO_EXTEND_VECTOR_INREG : ISD::ZERO_EXTEND; - if (!TLO.LegalOperations() || isOperationLegal(Opc, VT)) - return TLO.CombineTo(Op, TLO.DAG.getNode(Opc, dl, VT, Src)); + if (!TLO.LegalOperations() || isOperationLegal(Opc, VT)) { + SDNodeFlags Flags; + if (!IsVecInReg) + Flags.setNonNeg(true); + return TLO.CombineTo(Op, TLO.DAG.getNode(Opc, dl, VT, Src, Flags)); + } } // Attempt to avoid multi-use ops if we don't need anything from them. diff --git a/llvm/lib/CodeGen/SlotIndexes.cpp b/llvm/lib/CodeGen/SlotIndexes.cpp index 65726f06ded..8b80c6ccb43 100644 --- a/llvm/lib/CodeGen/SlotIndexes.cpp +++ b/llvm/lib/CodeGen/SlotIndexes.cpp @@ -62,7 +62,7 @@ bool SlotIndexes::runOnMachineFunction(MachineFunction &fn) { mf = &fn; - // Check that the list contains only the sentinal. + // Check that the list contains only the sentinel. assert(indexList.empty() && "Index list non-empty at initial numbering?"); assert(idx2MBBMap.empty() && "Index -> MBB mapping non-empty at initial numbering?"); diff --git a/llvm/lib/CodeGen/StackMaps.cpp b/llvm/lib/CodeGen/StackMaps.cpp index f9115e43487..90aa93e442c 100644 --- a/llvm/lib/CodeGen/StackMaps.cpp +++ b/llvm/lib/CodeGen/StackMaps.cpp @@ -200,14 +200,14 @@ static unsigned getDwarfRegNum(unsigned Reg, const TargetRegisterInfo *TRI) { break; } - assert(RegNum >= 0 && "Invalid Dwarf register number."); + assert(RegNum >= 0 && isUInt<16>(RegNum) && "Invalid Dwarf register number."); return (unsigned)RegNum; } MachineInstr::const_mop_iterator StackMaps::parseOperand(MachineInstr::const_mop_iterator MOI, MachineInstr::const_mop_iterator MOE, LocationVec &Locs, - LiveOutVec &LiveOuts) const { + LiveOutVec &LiveOuts) { const TargetRegisterInfo *TRI = AP.MF->getSubtarget().getRegisterInfo(); if (MOI->isImm()) { switch (MOI->getImm()) { @@ -238,7 +238,22 @@ StackMaps::parseOperand(MachineInstr::const_mop_iterator MOI, ++MOI; assert(MOI->isImm() && "Expected constant operand."); int64_t Imm = MOI->getImm(); - Locs.emplace_back(Location::Constant, sizeof(int64_t), 0, Imm); + if (isInt<32>(Imm)) { + Locs.emplace_back(Location::Constant, sizeof(int64_t), 0, Imm); + } else { + // ConstPool is intentionally a MapVector of 'uint64_t's (as + // opposed to 'int64_t's). We should never be in a situation + // where we have to insert either the tombstone or the empty + // keys into a map, and for a DenseMap these are + // (uint64_t)0 and (uint64_t)-1. They can be and are + // represented using 32 bit integers. + assert((uint64_t)Imm != DenseMapInfo::getEmptyKey() && + (uint64_t)Imm != DenseMapInfo::getTombstoneKey() && + "empty and tombstone keys should fit in 32 bits!"); + auto Result = ConstPool.insert(std::make_pair(Imm, Imm)); + Locs.emplace_back(Location::ConstantIndex, sizeof(int64_t), 0, + Result.first - ConstPool.begin()); + } break; } } @@ -497,27 +512,6 @@ void StackMaps::recordStackMapOpers(const MCSymbol &MILabel, while (MOI != MOE) MOI = parseOperand(MOI, MOE, Locations, LiveOuts); - // Move large constants into the constant pool. - for (auto &Loc : Locations) { - // Constants are encoded as sign-extended integers. - // -1 is directly encoded as .long 0xFFFFFFFF with no constant pool. - if (Loc.Type == Location::Constant && !isInt<32>(Loc.Offset)) { - Loc.Type = Location::ConstantIndex; - // ConstPool is intentionally a MapVector of 'uint64_t's (as - // opposed to 'int64_t's). We should never be in a situation - // where we have to insert either the tombstone or the empty - // keys into a map, and for a DenseMap these are - // (uint64_t)0 and (uint64_t)-1. They can be and are - // represented using 32 bit integers. - assert((uint64_t)Loc.Offset != DenseMapInfo::getEmptyKey() && - (uint64_t)Loc.Offset != - DenseMapInfo::getTombstoneKey() && - "empty and tombstone keys should fit in 32 bits!"); - auto Result = ConstPool.insert(std::make_pair(Loc.Offset, Loc.Offset)); - Loc.Offset = Result.first - ConstPool.begin(); - } - } - // Create an expression to calculate the offset of the callsite from function // entry. const MCExpr *CSOffsetExpr = MCBinaryExpr::createSub( diff --git a/llvm/lib/CodeGen/TargetLoweringBase.cpp b/llvm/lib/CodeGen/TargetLoweringBase.cpp index e92e3cd0439..7dffd8d4f2b 100644 --- a/llvm/lib/CodeGen/TargetLoweringBase.cpp +++ b/llvm/lib/CodeGen/TargetLoweringBase.cpp @@ -752,9 +752,7 @@ TargetLoweringBase::TargetLoweringBase(const TargetMachine &tm) : TM(tm) { GatherAllAliasesMaxDepth = 18; IsStrictFPEnabled = DisableStrictNodeMutation; MaxBytesForAlignment = 0; - // TODO: the default will be switched to 0 in the next commit, along - // with the Target-specific changes necessary. - MaxAtomicSizeInBitsSupported = 1024; + MaxAtomicSizeInBitsSupported = 0; // Assume that even with libcalls, no target supports wider than 128 bit // division. diff --git a/llvm/lib/CodeGen/TargetPassConfig.cpp b/llvm/lib/CodeGen/TargetPassConfig.cpp index 3bbc792f4cb..599ca481890 100644 --- a/llvm/lib/CodeGen/TargetPassConfig.cpp +++ b/llvm/lib/CodeGen/TargetPassConfig.cpp @@ -504,81 +504,6 @@ CGPassBuilderOption llvm::getCGPassBuilderOption() { return Opt; } -static void registerPartialPipelineCallback(PassInstrumentationCallbacks &PIC, - LLVMTargetMachine &LLVMTM) { - StringRef StartBefore; - StringRef StartAfter; - StringRef StopBefore; - StringRef StopAfter; - - unsigned StartBeforeInstanceNum = 0; - unsigned StartAfterInstanceNum = 0; - unsigned StopBeforeInstanceNum = 0; - unsigned StopAfterInstanceNum = 0; - - std::tie(StartBefore, StartBeforeInstanceNum) = - getPassNameAndInstanceNum(StartBeforeOpt); - std::tie(StartAfter, StartAfterInstanceNum) = - getPassNameAndInstanceNum(StartAfterOpt); - std::tie(StopBefore, StopBeforeInstanceNum) = - getPassNameAndInstanceNum(StopBeforeOpt); - std::tie(StopAfter, StopAfterInstanceNum) = - getPassNameAndInstanceNum(StopAfterOpt); - - if (StartBefore.empty() && StartAfter.empty() && StopBefore.empty() && - StopAfter.empty()) - return; - - std::tie(StartBefore, std::ignore) = - LLVMTM.getPassNameFromLegacyName(StartBefore); - std::tie(StartAfter, std::ignore) = - LLVMTM.getPassNameFromLegacyName(StartAfter); - std::tie(StopBefore, std::ignore) = - LLVMTM.getPassNameFromLegacyName(StopBefore); - std::tie(StopAfter, std::ignore) = - LLVMTM.getPassNameFromLegacyName(StopAfter); - if (!StartBefore.empty() && !StartAfter.empty()) - report_fatal_error(Twine(StartBeforeOptName) + Twine(" and ") + - Twine(StartAfterOptName) + Twine(" specified!")); - if (!StopBefore.empty() && !StopAfter.empty()) - report_fatal_error(Twine(StopBeforeOptName) + Twine(" and ") + - Twine(StopAfterOptName) + Twine(" specified!")); - - PIC.registerShouldRunOptionalPassCallback( - [=, EnableCurrent = StartBefore.empty() && StartAfter.empty(), - EnableNext = std::optional(), StartBeforeCount = 0u, - StartAfterCount = 0u, StopBeforeCount = 0u, - StopAfterCount = 0u](StringRef P, Any) mutable { - bool StartBeforePass = !StartBefore.empty() && P.contains(StartBefore); - bool StartAfterPass = !StartAfter.empty() && P.contains(StartAfter); - bool StopBeforePass = !StopBefore.empty() && P.contains(StopBefore); - bool StopAfterPass = !StopAfter.empty() && P.contains(StopAfter); - - // Implement -start-after/-stop-after - if (EnableNext) { - EnableCurrent = *EnableNext; - EnableNext.reset(); - } - - // Using PIC.registerAfterPassCallback won't work because if this - // callback returns false, AfterPassCallback is also skipped. - if (StartAfterPass && StartAfterCount++ == StartAfterInstanceNum) { - assert(!EnableNext && "Error: assign to EnableNext more than once"); - EnableNext = true; - } - if (StopAfterPass && StopAfterCount++ == StopAfterInstanceNum) { - assert(!EnableNext && "Error: assign to EnableNext more than once"); - EnableNext = false; - } - - if (StartBeforePass && StartBeforeCount++ == StartBeforeInstanceNum) - EnableCurrent = true; - if (StopBeforePass && StopBeforeCount++ == StopBeforeInstanceNum) - EnableCurrent = false; - return EnableCurrent; - }); -} - void llvm::registerCodeGenCallback(PassInstrumentationCallbacks &PIC, LLVMTargetMachine &LLVMTM) { @@ -605,8 +530,40 @@ void llvm::registerCodeGenCallback(PassInstrumentationCallbacks &PIC, return true; }); +} - registerPartialPipelineCallback(PIC, LLVMTM); +Expected +TargetPassConfig::getStartStopInfo(PassInstrumentationCallbacks &PIC) { + auto [StartBefore, StartBeforeInstanceNum] = + getPassNameAndInstanceNum(StartBeforeOpt); + auto [StartAfter, StartAfterInstanceNum] = + getPassNameAndInstanceNum(StartAfterOpt); + auto [StopBefore, StopBeforeInstanceNum] = + getPassNameAndInstanceNum(StopBeforeOpt); + auto [StopAfter, StopAfterInstanceNum] = + getPassNameAndInstanceNum(StopAfterOpt); + + if (!StartBefore.empty() && !StartAfter.empty()) + return make_error( + Twine(StartBeforeOptName) + " and " + StartAfterOptName + " specified!", + std::make_error_code(std::errc::invalid_argument)); + if (!StopBefore.empty() && !StopAfter.empty()) + return make_error( + Twine(StopBeforeOptName) + " and " + StopAfterOptName + " specified!", + std::make_error_code(std::errc::invalid_argument)); + + StartStopInfo Result; + Result.StartPass = StartBefore.empty() ? StartAfter : StartBefore; + Result.StopPass = StopBefore.empty() ? StopAfter : StopBefore; + Result.StartInstanceNum = + StartBefore.empty() ? StartAfterInstanceNum : StartBeforeInstanceNum; + Result.StopInstanceNum = + StopBefore.empty() ? StopAfterInstanceNum : StopBeforeInstanceNum; + Result.StartAfter = !StartAfter.empty(); + Result.StopAfter = !StopAfter.empty(); + Result.StartInstanceNum += Result.StartInstanceNum == 0; + Result.StopInstanceNum += Result.StopInstanceNum == 0; + return Result; } // Out of line constructor provides default values for pass options and @@ -678,8 +635,7 @@ bool TargetPassConfig::hasLimitedCodeGenPipeline() { !willCompleteCodeGenPipeline(); } -std::string -TargetPassConfig::getLimitedCodeGenPipelineReason(const char *Separator) { +std::string TargetPassConfig::getLimitedCodeGenPipelineReason() { if (!hasLimitedCodeGenPipeline()) return std::string(); std::string Res; @@ -691,7 +647,7 @@ TargetPassConfig::getLimitedCodeGenPipelineReason(const char *Separator) { for (int Idx = 0; Idx < 4; ++Idx) if (!PassNames[Idx]->empty()) { if (!IsFirst) - Res += Separator; + Res += " and "; IsFirst = false; Res += OptNames[Idx]; } @@ -1289,7 +1245,7 @@ void TargetPassConfig::addMachinePasses() { // enabled, this may result in performance regression. WithColor::warning() << "Using AutoFDO without FSDiscriminator for MFS may regress " - "performance."; + "performance.\n"; } } addPass(createMachineFunctionSplitterPass()); diff --git a/llvm/lib/CodeGen/TwoAddressInstructionPass.cpp b/llvm/lib/CodeGen/TwoAddressInstructionPass.cpp index 526cb847e8a..74d7904aee3 100644 --- a/llvm/lib/CodeGen/TwoAddressInstructionPass.cpp +++ b/llvm/lib/CodeGen/TwoAddressInstructionPass.cpp @@ -1936,13 +1936,16 @@ eliminateRegSequence(MachineBasicBlock::iterator &MBBI) { } bool DefEmitted = false; + bool DefIsPartial = false; for (unsigned i = 1, e = MI.getNumOperands(); i < e; i += 2) { MachineOperand &UseMO = MI.getOperand(i); Register SrcReg = UseMO.getReg(); unsigned SubIdx = MI.getOperand(i+1).getImm(); // Nothing needs to be inserted for undef operands. - if (UseMO.isUndef()) + if (UseMO.isUndef()) { + DefIsPartial = true; continue; + } // Defer any kill flag to the last operand using SrcReg. Otherwise, we // might insert a COPY that uses SrcReg after is was killed. @@ -1987,8 +1990,14 @@ eliminateRegSequence(MachineBasicBlock::iterator &MBBI) { for (int j = MI.getNumOperands() - 1, ee = 0; j > ee; --j) MI.removeOperand(j); } else { - if (LIS) + if (LIS) { + // Force interval recomputation if we moved from full definition + // of register to partial. + if (DefIsPartial && LIS->hasInterval(DstReg) && + MRI->shouldTrackSubRegLiveness(DstReg)) + LIS->removeInterval(DstReg); LIS->RemoveMachineInstrFromMaps(MI); + } LLVM_DEBUG(dbgs() << "Eliminated: " << MI); MI.eraseFromParent(); diff --git a/llvm/lib/CodeGen/UnreachableBlockElim.cpp b/llvm/lib/CodeGen/UnreachableBlockElim.cpp index f17450d264b..1a60e9abbe2 100644 --- a/llvm/lib/CodeGen/UnreachableBlockElim.cpp +++ b/llvm/lib/CodeGen/UnreachableBlockElim.cpp @@ -117,7 +117,7 @@ bool UnreachableMachineBlockElim::runOnMachineFunction(MachineFunction &F) { if (MLI) MLI->removeBlock(&BB); if (MDT && MDT->getNode(&BB)) MDT->eraseNode(&BB); - while (BB.succ_begin() != BB.succ_end()) { + while (!BB.succ_empty()) { MachineBasicBlock* succ = *BB.succ_begin(); for (MachineInstr &Phi : succ->phis()) { diff --git a/llvm/lib/DWARFLinker/Classic/DWARFLinker.cpp b/llvm/lib/DWARFLinker/Classic/DWARFLinker.cpp index ac2c26e5224..4f5a4e2ffc7 100644 --- a/llvm/lib/DWARFLinker/Classic/DWARFLinker.cpp +++ b/llvm/lib/DWARFLinker/Classic/DWARFLinker.cpp @@ -218,7 +218,7 @@ static void analyzeImportedModule( ReportWarning(Twine("Conflicting parseable interfaces for Swift Module ") + *Name + ": " + Entry + " and " + Path, DIE); - Entry = std::string(ResolvedPath.str()); + Entry = std::string(ResolvedPath); } /// The distinct types of work performed by the work loop in @@ -465,7 +465,7 @@ DWARFLinker::getVariableRelocAdjustment(AddressesMap &RelocMgr, if (std::optional RelocAdjustment = RelocMgr.getExprOpAddressRelocAdjustment( *U, Op, AttrOffset + CurExprOffset, - AttrOffset + Op.getEndOffset())) + AttrOffset + Op.getEndOffset(), Options.Verbose)) return std::make_pair(HasLocationAddress, *RelocAdjustment); } break; case dwarf::DW_OP_constx: @@ -478,7 +478,8 @@ DWARFLinker::getVariableRelocAdjustment(AddressesMap &RelocMgr, if (std::optional RelocAdjustment = RelocMgr.getExprOpAddressRelocAdjustment( *U, Op, *AddressOffset, - *AddressOffset + DIE.getDwarfUnit()->getAddressByteSize())) + *AddressOffset + DIE.getDwarfUnit()->getAddressByteSize(), + Options.Verbose)) return std::make_pair(HasLocationAddress, *RelocAdjustment); } } break; @@ -552,7 +553,7 @@ unsigned DWARFLinker::shouldKeepSubprogramDIE( assert(LowPc && "low_pc attribute is not an address."); std::optional RelocAdjustment = - RelocMgr.getSubprogramRelocAdjustment(DIE); + RelocMgr.getSubprogramRelocAdjustment(DIE, Options.Verbose); if (!RelocAdjustment) return Flags; @@ -2035,13 +2036,13 @@ void DWARFLinker::DIECloner::emitDebugAddrSection( if (DwarfVersion < 5) return; - if (AddrPool.DieValues.empty()) + if (AddrPool.getValues().empty()) return; MCSymbol *EndLabel = Emitter->emitDwarfDebugAddrsHeader(Unit); patchAddrBase(*Unit.getOutputUnitDIE(), DIEInteger(Emitter->getDebugAddrSectionSize())); - Emitter->emitDwarfDebugAddrs(AddrPool.DieValues, + Emitter->emitDwarfDebugAddrs(AddrPool.getValues(), Unit.getOrigUnit().getAddressByteSize()); Emitter->emitDwarfDebugAddrsFooter(Unit, EndLabel); } @@ -2240,14 +2241,20 @@ void DWARFLinker::emitAcceleratorEntriesForUnit(CompileUnit &Unit) { } break; case AccelTableKind::DebugNames: { for (const auto &Namespace : Unit.getNamespaces()) - DebugNames.addName(Namespace.Name, Namespace.Die->getOffset(), - Namespace.Die->getTag(), Unit.getUniqueID()); + DebugNames.addName( + Namespace.Name, Namespace.Die->getOffset(), + DWARF5AccelTableData::getDefiningParentDieOffset(*Namespace.Die), + Namespace.Die->getTag(), Unit.getUniqueID()); for (const auto &Pubname : Unit.getPubnames()) - DebugNames.addName(Pubname.Name, Pubname.Die->getOffset(), - Pubname.Die->getTag(), Unit.getUniqueID()); + DebugNames.addName( + Pubname.Name, Pubname.Die->getOffset(), + DWARF5AccelTableData::getDefiningParentDieOffset(*Pubname.Die), + Pubname.Die->getTag(), Unit.getUniqueID()); for (const auto &Pubtype : Unit.getPubtypes()) - DebugNames.addName(Pubtype.Name, Pubtype.Die->getOffset(), - Pubtype.Die->getTag(), Unit.getUniqueID()); + DebugNames.addName( + Pubtype.Name, Pubtype.Die->getOffset(), + DWARF5AccelTableData::getDefiningParentDieOffset(*Pubtype.Die), + Pubtype.Die->getTag(), Unit.getUniqueID()); } break; } } @@ -2644,19 +2651,22 @@ uint64_t DWARFLinker::DIECloner::cloneAllCompileUnits( void DWARFLinker::copyInvariantDebugSection(DWARFContext &Dwarf) { TheDwarfEmitter->emitSectionContents(Dwarf.getDWARFObj().getLocSection().Data, - "debug_loc"); + DebugSectionKind::DebugLoc); TheDwarfEmitter->emitSectionContents( - Dwarf.getDWARFObj().getRangesSection().Data, "debug_ranges"); + Dwarf.getDWARFObj().getRangesSection().Data, + DebugSectionKind::DebugRange); TheDwarfEmitter->emitSectionContents( - Dwarf.getDWARFObj().getFrameSection().Data, "debug_frame"); + Dwarf.getDWARFObj().getFrameSection().Data, DebugSectionKind::DebugFrame); TheDwarfEmitter->emitSectionContents(Dwarf.getDWARFObj().getArangesSection(), - "debug_aranges"); + DebugSectionKind::DebugARanges); TheDwarfEmitter->emitSectionContents( - Dwarf.getDWARFObj().getAddrSection().Data, "debug_addr"); + Dwarf.getDWARFObj().getAddrSection().Data, DebugSectionKind::DebugAddr); TheDwarfEmitter->emitSectionContents( - Dwarf.getDWARFObj().getRnglistsSection().Data, "debug_rnglists"); + Dwarf.getDWARFObj().getRnglistsSection().Data, + DebugSectionKind::DebugRngLists); TheDwarfEmitter->emitSectionContents( - Dwarf.getDWARFObj().getLoclistsSection().Data, "debug_loclists"); + Dwarf.getDWARFObj().getLoclistsSection().Data, + DebugSectionKind::DebugLocLists); } void DWARFLinker::addObjectFile(DWARFFile &File, ObjFileLoaderTy Loader, @@ -2848,7 +2858,7 @@ Error DWARFLinker::link() { SizeByObject[OptContext.File.FileName].Input = getDebugInfoSize(*OptContext.File.Dwarf); SizeByObject[OptContext.File.FileName].Output = - DIECloner(*this, TheDwarfEmitter.get(), OptContext.File, DIEAlloc, + DIECloner(*this, TheDwarfEmitter, OptContext.File, DIEAlloc, OptContext.CompileUnits, Options.Update, DebugStrPool, DebugLineStrPool, StringOffsetPool) .cloneAllCompileUnits(*OptContext.File.Dwarf, OptContext.File, @@ -2867,7 +2877,7 @@ Error DWARFLinker::link() { if (TheDwarfEmitter != nullptr) { TheDwarfEmitter->emitAbbrevs(Abbreviations, Options.TargetDWARFVersion); TheDwarfEmitter->emitStrings(DebugStrPool); - TheDwarfEmitter->emitStringOffsets(StringOffsetPool.DieValues, + TheDwarfEmitter->emitStringOffsets(StringOffsetPool.getValues(), Options.TargetDWARFVersion); TheDwarfEmitter->emitLineStrings(DebugLineStrPool); for (AccelTableKind TableKind : Options.AccelTables) { @@ -3011,7 +3021,7 @@ Error DWARFLinker::cloneModuleUnit(LinkContext &Context, RefModuleUnit &Unit, UnitListTy CompileUnits; CompileUnits.emplace_back(std::move(Unit.Unit)); assert(TheDwarfEmitter); - DIECloner(*this, TheDwarfEmitter.get(), Unit.File, DIEAlloc, CompileUnits, + DIECloner(*this, TheDwarfEmitter, Unit.File, DIEAlloc, CompileUnits, Options.Update, DebugStrPool, DebugLineStrPool, StringOffsetPool) .cloneAllCompileUnits(*Unit.File.Dwarf, Unit.File, Unit.File.Dwarf->isLittleEndian()); @@ -3030,16 +3040,4 @@ void DWARFLinker::verifyInput(const DWARFFile &File) { } } -Error DWARFLinker::createEmitter(const Triple &TheTriple, - OutputFileType FileType, - raw_pwrite_stream &OutFile) { - - TheDwarfEmitter = std::make_unique( - FileType, OutFile, StringsTranslator, WarningHandler); - - return TheDwarfEmitter->init(TheTriple, "__DWARF"); -} - -DwarfEmitter *DWARFLinker::getEmitter() { return TheDwarfEmitter.get(); } - } // namespace llvm diff --git a/llvm/lib/DWARFLinker/Classic/DWARFStreamer.cpp b/llvm/lib/DWARFLinker/Classic/DWARFStreamer.cpp index 020bbb06449..6d522370e44 100644 --- a/llvm/lib/DWARFLinker/Classic/DWARFStreamer.cpp +++ b/llvm/lib/DWARFLinker/Classic/DWARFStreamer.cpp @@ -30,6 +30,18 @@ using namespace llvm; using namespace dwarf_linker; using namespace dwarf_linker::classic; +Expected> DwarfStreamer::createStreamer( + const Triple &TheTriple, DWARFLinkerBase::OutputFileType FileType, + raw_pwrite_stream &OutFile, DWARFLinkerBase::TranslatorFuncTy Translator, + DWARFLinkerBase::MessageHandlerTy Warning) { + std::unique_ptr Streamer = + std::make_unique(FileType, OutFile, Translator, Warning); + if (Error Err = Streamer->init(TheTriple, "__DWARF")) + return std::move(Err); + + return std::move(Streamer); +} + Error DwarfStreamer::init(Triple TheTriple, StringRef Swift5ReflectionSegmentName) { std::string ErrorStr; @@ -212,30 +224,72 @@ void DwarfStreamer::emitDIE(DIE &Die) { } /// Emit contents of section SecName From Obj. -void DwarfStreamer::emitSectionContents(StringRef SecData, StringRef SecName) { - MCSection *Section = - StringSwitch(SecName) - .Case("debug_line", MC->getObjectFileInfo()->getDwarfLineSection()) - .Case("debug_loc", MC->getObjectFileInfo()->getDwarfLocSection()) - .Case("debug_ranges", - MC->getObjectFileInfo()->getDwarfRangesSection()) - .Case("debug_frame", MC->getObjectFileInfo()->getDwarfFrameSection()) - .Case("debug_aranges", - MC->getObjectFileInfo()->getDwarfARangesSection()) - .Case("debug_addr", MC->getObjectFileInfo()->getDwarfAddrSection()) - .Case("debug_rnglists", - MC->getObjectFileInfo()->getDwarfRnglistsSection()) - .Case("debug_loclists", - MC->getObjectFileInfo()->getDwarfLoclistsSection()) - .Default(nullptr); +void DwarfStreamer::emitSectionContents(StringRef SecData, + DebugSectionKind SecKind) { + if (SecData.empty()) + return; - if (Section) { + if (MCSection *Section = getMCSection(SecKind)) { MS->switchSection(Section); MS->emitBytes(SecData); } } +MCSection *DwarfStreamer::getMCSection(DebugSectionKind SecKind) { + switch (SecKind) { + case DebugSectionKind::DebugInfo: + return MC->getObjectFileInfo()->getDwarfInfoSection(); + case DebugSectionKind::DebugLine: + return MC->getObjectFileInfo()->getDwarfLineSection(); + case DebugSectionKind::DebugFrame: + return MC->getObjectFileInfo()->getDwarfFrameSection(); + case DebugSectionKind::DebugRange: + return MC->getObjectFileInfo()->getDwarfRangesSection(); + case DebugSectionKind::DebugRngLists: + return MC->getObjectFileInfo()->getDwarfRnglistsSection(); + case DebugSectionKind::DebugLoc: + return MC->getObjectFileInfo()->getDwarfLocSection(); + case DebugSectionKind::DebugLocLists: + return MC->getObjectFileInfo()->getDwarfLoclistsSection(); + case DebugSectionKind::DebugARanges: + return MC->getObjectFileInfo()->getDwarfARangesSection(); + case DebugSectionKind::DebugAbbrev: + return MC->getObjectFileInfo()->getDwarfAbbrevSection(); + case DebugSectionKind::DebugMacinfo: + return MC->getObjectFileInfo()->getDwarfMacinfoSection(); + case DebugSectionKind::DebugMacro: + return MC->getObjectFileInfo()->getDwarfMacroSection(); + case DebugSectionKind::DebugAddr: + return MC->getObjectFileInfo()->getDwarfAddrSection(); + case DebugSectionKind::DebugStr: + return MC->getObjectFileInfo()->getDwarfStrSection(); + case DebugSectionKind::DebugLineStr: + return MC->getObjectFileInfo()->getDwarfLineStrSection(); + case DebugSectionKind::DebugStrOffsets: + return MC->getObjectFileInfo()->getDwarfStrOffSection(); + case DebugSectionKind::DebugPubNames: + return MC->getObjectFileInfo()->getDwarfPubNamesSection(); + case DebugSectionKind::DebugPubTypes: + return MC->getObjectFileInfo()->getDwarfPubTypesSection(); + case DebugSectionKind::DebugNames: + return MC->getObjectFileInfo()->getDwarfDebugNamesSection(); + case DebugSectionKind::AppleNames: + return MC->getObjectFileInfo()->getDwarfAccelNamesSection(); + case DebugSectionKind::AppleNamespaces: + return MC->getObjectFileInfo()->getDwarfAccelNamespaceSection(); + case DebugSectionKind::AppleObjC: + return MC->getObjectFileInfo()->getDwarfAccelObjCSection(); + case DebugSectionKind::AppleTypes: + return MC->getObjectFileInfo()->getDwarfAccelTypesSection(); + case DebugSectionKind::NumberOfEnumEntries: + llvm_unreachable("Unknown DebugSectionKind value"); + break; + } + + return nullptr; +} + /// Emit the debug_str section stored in \p Pool. void DwarfStreamer::emitStrings(const NonRelocatableStringpool &Pool) { Asm->OutStreamer->switchSection(MOFI->getDwarfStrSection()); diff --git a/llvm/lib/DWARFLinker/DWARFLinkerBase.cpp b/llvm/lib/DWARFLinker/DWARFLinkerBase.cpp new file mode 100644 index 00000000000..7ba98d43274 --- /dev/null +++ b/llvm/lib/DWARFLinker/DWARFLinkerBase.cpp @@ -0,0 +1,64 @@ +//=== DWARFLinkerBase.cpp -------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +#include "llvm/DWARFLinker/DWARFLinkerBase.h" +#include "llvm/ADT/StringSwitch.h" + +using namespace llvm; +using namespace llvm::dwarf_linker; + +std::optional +llvm::dwarf_linker::parseDebugTableName(llvm::StringRef SecName) { + return llvm::StringSwitch>( + SecName.substr(SecName.find_first_not_of("._"))) + .Case(getSectionName(DebugSectionKind::DebugInfo), + DebugSectionKind::DebugInfo) + .Case(getSectionName(DebugSectionKind::DebugLine), + DebugSectionKind::DebugLine) + .Case(getSectionName(DebugSectionKind::DebugFrame), + DebugSectionKind::DebugFrame) + .Case(getSectionName(DebugSectionKind::DebugRange), + DebugSectionKind::DebugRange) + .Case(getSectionName(DebugSectionKind::DebugRngLists), + DebugSectionKind::DebugRngLists) + .Case(getSectionName(DebugSectionKind::DebugLoc), + DebugSectionKind::DebugLoc) + .Case(getSectionName(DebugSectionKind::DebugLocLists), + DebugSectionKind::DebugLocLists) + .Case(getSectionName(DebugSectionKind::DebugARanges), + DebugSectionKind::DebugARanges) + .Case(getSectionName(DebugSectionKind::DebugAbbrev), + DebugSectionKind::DebugAbbrev) + .Case(getSectionName(DebugSectionKind::DebugMacinfo), + DebugSectionKind::DebugMacinfo) + .Case(getSectionName(DebugSectionKind::DebugMacro), + DebugSectionKind::DebugMacro) + .Case(getSectionName(DebugSectionKind::DebugAddr), + DebugSectionKind::DebugAddr) + .Case(getSectionName(DebugSectionKind::DebugStr), + DebugSectionKind::DebugStr) + .Case(getSectionName(DebugSectionKind::DebugLineStr), + DebugSectionKind::DebugLineStr) + .Case(getSectionName(DebugSectionKind::DebugStrOffsets), + DebugSectionKind::DebugStrOffsets) + .Case(getSectionName(DebugSectionKind::DebugPubNames), + DebugSectionKind::DebugPubNames) + .Case(getSectionName(DebugSectionKind::DebugPubTypes), + DebugSectionKind::DebugPubTypes) + .Case(getSectionName(DebugSectionKind::DebugNames), + DebugSectionKind::DebugNames) + .Case(getSectionName(DebugSectionKind::AppleNames), + DebugSectionKind::AppleNames) + .Case(getSectionName(DebugSectionKind::AppleNamespaces), + DebugSectionKind::AppleNamespaces) + .Case(getSectionName(DebugSectionKind::AppleObjC), + DebugSectionKind::AppleObjC) + .Case(getSectionName(DebugSectionKind::AppleTypes), + DebugSectionKind::AppleTypes) + .Default(std::nullopt); +} diff --git a/llvm/lib/DWARFLinker/Parallel/DWARFEmitterImpl.cpp b/llvm/lib/DWARFLinker/Parallel/DWARFEmitterImpl.cpp index 115167f0c7d..b9edcb63a34 100644 --- a/llvm/lib/DWARFLinker/Parallel/DWARFEmitterImpl.cpp +++ b/llvm/lib/DWARFLinker/Parallel/DWARFEmitterImpl.cpp @@ -120,72 +120,6 @@ Error DwarfEmitterImpl::init(Triple TheTriple, return Error::success(); } -void DwarfEmitterImpl::emitSwiftAST(StringRef Buffer) { - MCSection *SwiftASTSection = MOFI->getDwarfSwiftASTSection(); - SwiftASTSection->setAlignment(Align(32)); - MS->switchSection(SwiftASTSection); - MS->emitBytes(Buffer); -} - -/// Emit the swift reflection section stored in \p Buffer. -void DwarfEmitterImpl::emitSwiftReflectionSection( - llvm::binaryformat::Swift5ReflectionSectionKind ReflSectionKind, - StringRef Buffer, uint32_t Alignment, uint32_t) { - MCSection *ReflectionSection = - MOFI->getSwift5ReflectionSection(ReflSectionKind); - if (ReflectionSection == nullptr) - return; - ReflectionSection->setAlignment(Align(Alignment)); - MS->switchSection(ReflectionSection); - MS->emitBytes(Buffer); -} - -void DwarfEmitterImpl::emitSectionContents(StringRef SecData, - StringRef SecName) { - if (SecData.empty()) - return; - - if (MCSection *Section = switchSection(SecName)) { - MS->switchSection(Section); - - MS->emitBytes(SecData); - } -} - -MCSection *DwarfEmitterImpl::switchSection(StringRef SecName) { - return StringSwitch(SecName) - .Case("debug_info", MC->getObjectFileInfo()->getDwarfInfoSection()) - .Case("debug_abbrev", MC->getObjectFileInfo()->getDwarfAbbrevSection()) - .Case("debug_line", MC->getObjectFileInfo()->getDwarfLineSection()) - .Case("debug_loc", MC->getObjectFileInfo()->getDwarfLocSection()) - .Case("debug_ranges", MC->getObjectFileInfo()->getDwarfRangesSection()) - .Case("debug_frame", MC->getObjectFileInfo()->getDwarfFrameSection()) - .Case("debug_aranges", MC->getObjectFileInfo()->getDwarfARangesSection()) - .Case("debug_rnglists", - MC->getObjectFileInfo()->getDwarfRnglistsSection()) - .Case("debug_loclists", - MC->getObjectFileInfo()->getDwarfLoclistsSection()) - .Case("debug_macro", MC->getObjectFileInfo()->getDwarfMacroSection()) - .Case("debug_macinfo", MC->getObjectFileInfo()->getDwarfMacinfoSection()) - .Case("debug_addr", MC->getObjectFileInfo()->getDwarfAddrSection()) - .Case("debug_str", MC->getObjectFileInfo()->getDwarfStrSection()) - .Case("debug_line_str", MC->getObjectFileInfo()->getDwarfLineStrSection()) - .Case("debug_str_offsets", - MC->getObjectFileInfo()->getDwarfStrOffSection()) - .Case("debug_pubnames", - MC->getObjectFileInfo()->getDwarfPubNamesSection()) - .Case("debug_pubtypes", - MC->getObjectFileInfo()->getDwarfPubTypesSection()) - .Case("debug_names", MC->getObjectFileInfo()->getDwarfDebugNamesSection()) - .Case("apple_names", MC->getObjectFileInfo()->getDwarfAccelNamesSection()) - .Case("apple_namespac", - MC->getObjectFileInfo()->getDwarfAccelNamespaceSection()) - .Case("apple_objc", MC->getObjectFileInfo()->getDwarfAccelObjCSection()) - .Case("apple_types", MC->getObjectFileInfo()->getDwarfAccelTypesSection()) - - .Default(nullptr); -} - void DwarfEmitterImpl::emitAbbrevs( const SmallVector> &Abbrevs, unsigned DwarfVersion) { diff --git a/llvm/lib/DWARFLinker/Parallel/DWARFEmitterImpl.h b/llvm/lib/DWARFLinker/Parallel/DWARFEmitterImpl.h index 89a33fe9419..71351f1d8c1 100644 --- a/llvm/lib/DWARFLinker/Parallel/DWARFEmitterImpl.h +++ b/llvm/lib/DWARFLinker/Parallel/DWARFEmitterImpl.h @@ -45,7 +45,7 @@ using CompUnitIDToIdx = DenseMap; /// This class emits DWARF data to the output stream. It emits already /// generated section data and specific data, which could not be generated /// by CompileUnit. -class DwarfEmitterImpl : public ExtraDwarfEmitter { +class DwarfEmitterImpl { public: DwarfEmitterImpl(DWARFLinker::OutputFileType OutFileType, raw_pwrite_stream &OutFile) @@ -58,21 +58,7 @@ public: const Triple &getTargetTriple() { return MC->getTargetTriple(); } /// Dump the file to the disk. - void finish() override { MS->finish(); } - - /// Returns AsmPrinter. - AsmPrinter &getAsmPrinter() const override { return *Asm; } - - /// Emit the swift_ast section stored in \p Buffer. - void emitSwiftAST(StringRef Buffer) override; - - /// Emit the swift reflection section stored in \p Buffer. - void emitSwiftReflectionSection( - llvm::binaryformat::Swift5ReflectionSectionKind ReflSectionKind, - StringRef Buffer, uint32_t Alignment, uint32_t) override; - - /// Emit specified section data. - void emitSectionContents(StringRef SecData, StringRef SecName) override; + void finish() { MS->finish(); } /// Emit abbreviations. void emitAbbrevs(const SmallVector> &Abbrevs, @@ -115,8 +101,6 @@ private: const StringEntryToDwarfStringPoolEntryMap &Strings, uint64_t &NextOffset, MCSection *OutSection); - MCSection *switchSection(StringRef SecName); - /// \defgroup MCObjects MC layer objects constructed by the streamer /// @{ std::unique_ptr MRI; @@ -135,7 +119,8 @@ private: /// The output file we stream the linked Dwarf to. raw_pwrite_stream &OutFile; - DWARFLinker::OutputFileType OutFileType = DWARFLinker::OutputFileType::Object; + DWARFLinkerBase::OutputFileType OutFileType = + DWARFLinkerBase::OutputFileType::Object; uint64_t DebugInfoSectionSize = 0; }; diff --git a/llvm/lib/DWARFLinker/Parallel/DWARFLinkerCompileUnit.cpp b/llvm/lib/DWARFLinker/Parallel/DWARFLinkerCompileUnit.cpp index 6ed284a66a8..8c52040fdbc 100644 --- a/llvm/lib/DWARFLinker/Parallel/DWARFLinkerCompileUnit.cpp +++ b/llvm/lib/DWARFLinker/Parallel/DWARFLinkerCompileUnit.cpp @@ -294,7 +294,7 @@ void CompileUnit::analyzeImportedModule(const DWARFDebugInfoEntry *DieEntry) { ": " + Entry + " and " + Path + ".", &Die); } - Entry = std::string(ResolvedPath.str()); + Entry = std::string(ResolvedPath); } } @@ -1229,8 +1229,9 @@ void CompileUnit::cloneDieAttrExpression( } } -Error CompileUnit::cloneAndEmit(std::optional TargetTriple, - TypeUnit *ArtificialTypeUnit) { +Error CompileUnit::cloneAndEmit( + std::optional> TargetTriple, + TypeUnit *ArtificialTypeUnit) { BumpPtrAllocator Allocator; DWARFDie OrigUnitDIE = getOrigUnit().getUnitDIE(); @@ -1247,18 +1248,17 @@ Error CompileUnit::cloneAndEmit(std::optional TargetTriple, std::nullopt, std::nullopt, Allocator, ArtificialTypeUnit); setOutUnitDIE(OutCUDie.first); - if (getGlobalData().getOptions().NoOutput || (OutCUDie.first == nullptr)) + if (!TargetTriple.has_value() || (OutCUDie.first == nullptr)) return Error::success(); - assert(TargetTriple.has_value()); - if (Error Err = cloneAndEmitLineTable(*TargetTriple)) + if (Error Err = cloneAndEmitLineTable((*TargetTriple).get())) return Err; if (Error Err = cloneAndEmitDebugMacro()) return Err; getOrCreateSectionDescriptor(DebugSectionKind::DebugInfo); - if (Error Err = emitDebugInfo(*TargetTriple)) + if (Error Err = emitDebugInfo((*TargetTriple).get())) return Err; // ASSUMPTION: .debug_info section should already be emitted at this point. @@ -1372,7 +1372,7 @@ DIE *CompileUnit::createPlainDIEandCloneAttributes( // Get relocation adjustment value for the current function. FuncAddressAdjustment = getContaingFile().Addresses->getSubprogramRelocAdjustment( - getDIE(InputDieEntry)); + getDIE(InputDieEntry), false); } else if (InputDieEntry->getTag() == dwarf::DW_TAG_label) { // Get relocation adjustment value for the current label. std::optional lowPC = @@ -1386,7 +1386,7 @@ DIE *CompileUnit::createPlainDIEandCloneAttributes( // Get relocation adjustment value for the current variable. std::pair> LocExprAddrAndRelocAdjustment = getContaingFile().Addresses->getVariableRelocAdjustment( - getDIE(InputDieEntry)); + getDIE(InputDieEntry), false); HasLocationExpressionAddress = LocExprAddrAndRelocAdjustment.first; if (LocExprAddrAndRelocAdjustment.first && @@ -1514,7 +1514,7 @@ TypeEntry *CompileUnit::createTypeDIEandCloneAttributes( return Entry; } -Error CompileUnit::cloneAndEmitLineTable(Triple &TargetTriple) { +Error CompileUnit::cloneAndEmitLineTable(const Triple &TargetTriple) { const DWARFDebugLine::LineTable *InputLineTable = getContaingFile().Dwarf->getLineTableForUnit(&getOrigUnit()); if (InputLineTable == nullptr) { diff --git a/llvm/lib/DWARFLinker/Parallel/DWARFLinkerCompileUnit.h b/llvm/lib/DWARFLinker/Parallel/DWARFLinkerCompileUnit.h index abd978e7c0e..20e20222a4a 100644 --- a/llvm/lib/DWARFLinker/Parallel/DWARFLinkerCompileUnit.h +++ b/llvm/lib/DWARFLinker/Parallel/DWARFLinkerCompileUnit.h @@ -401,8 +401,9 @@ public: const RangesTy &getFunctionRanges() const { return Ranges; } /// Clone and emit this compilation unit. - Error cloneAndEmit(std::optional TargetTriple, - TypeUnit *ArtificialTypeUnit); + Error + cloneAndEmit(std::optional> TargetTriple, + TypeUnit *ArtificialTypeUnit); /// Clone and emit debug locations(.debug_loc/.debug_loclists). Error cloneAndEmitDebugLocations(); @@ -422,7 +423,7 @@ public: BumpPtrAllocator &Allocator, TypeUnit *ArtificialTypeUnit); // Clone and emit line table. - Error cloneAndEmitLineTable(Triple &TargetTriple); + Error cloneAndEmitLineTable(const Triple &TargetTriple); /// Clone attribute location axpression. void cloneDieAttrExpression(const DWARFExpression &InputExpression, diff --git a/llvm/lib/DWARFLinker/Parallel/DWARFLinkerGlobalData.h b/llvm/lib/DWARFLinker/Parallel/DWARFLinkerGlobalData.h index b641343ac80..38c261a8106 100644 --- a/llvm/lib/DWARFLinker/Parallel/DWARFLinkerGlobalData.h +++ b/llvm/lib/DWARFLinker/Parallel/DWARFLinkerGlobalData.h @@ -39,9 +39,6 @@ struct DWARFLinkerOptions { /// Verify the input DWARF. bool VerifyInputDWARF = false; - /// Do not emit output. - bool NoOutput = false; - /// Do not unique types according to ODR bool NoODR = false; @@ -59,13 +56,14 @@ struct DWARFLinkerOptions { unsigned Threads = 1; /// The accelerator table kinds - SmallVector AccelTables; + SmallVector AccelTables; /// Prepend path for the clang modules. std::string PrependPath; /// input verification handler(it might be called asynchronously). - DWARFLinker::InputVerificationHandlerTy InputVerificationHandler = nullptr; + DWARFLinkerBase::InputVerificationHandlerTy InputVerificationHandler = + nullptr; /// A list of all .swiftinterface files referenced by the debug /// info, mapping Module name to path on disk. The entries need to @@ -74,12 +72,12 @@ struct DWARFLinkerOptions { /// this is dsymutil specific fag. /// /// (it might be called asynchronously). - DWARFLinker::SwiftInterfacesMapTy *ParseableSwiftInterfaces = nullptr; + DWARFLinkerBase::SwiftInterfacesMapTy *ParseableSwiftInterfaces = nullptr; /// A list of remappings to apply to file paths. /// /// (it might be called asynchronously). - DWARFLinker::ObjectPrefixMapTy *ObjectPrefixMap = nullptr; + DWARFLinkerBase::ObjectPrefixMapTy *ObjectPrefixMap = nullptr; }; class DWARFLinkerImpl; @@ -147,6 +145,19 @@ public: }); } + /// Set target triple. + void setTargetTriple(const Triple &TargetTriple) { + this->TargetTriple = TargetTriple; + } + + /// Optionally return target triple. + std::optional> getTargetTriple() { + if (TargetTriple) + return std::cref(*TargetTriple); + + return std::nullopt; + } + protected: llvm::parallel::PerThreadBumpPtrAllocator Allocator; StringPool Strings; @@ -154,6 +165,10 @@ protected: DWARFLinkerOptions Options; MessageHandlerTy WarningHandler; MessageHandlerTy ErrorHandler; + + /// Triple for output data. May be not set if generation of output + /// data is not requested. + std::optional TargetTriple; }; } // end of namespace parallel diff --git a/llvm/lib/DWARFLinker/Parallel/DWARFLinkerImpl.cpp b/llvm/lib/DWARFLinker/Parallel/DWARFLinkerImpl.cpp index b0b819cf977..a052969e74c 100644 --- a/llvm/lib/DWARFLinker/Parallel/DWARFLinkerImpl.cpp +++ b/llvm/lib/DWARFLinker/Parallel/DWARFLinkerImpl.cpp @@ -32,11 +32,9 @@ DWARFLinkerImpl::DWARFLinkerImpl(MessageHandlerTy ErrorHandler, DWARFLinkerImpl::LinkContext::LinkContext(LinkingGlobalData &GlobalData, DWARFFile &File, StringMap &ClangModules, - std::atomic &UniqueUnitID, - std::optional TargetTriple) + std::atomic &UniqueUnitID) : OutputSections(GlobalData), InputDWARFFile(File), - ClangModules(ClangModules), TargetTriple(TargetTriple), - UniqueUnitID(UniqueUnitID) { + ClangModules(ClangModules), UniqueUnitID(UniqueUnitID) { if (File.Dwarf) { if (!File.Dwarf->compile_units().empty()) @@ -63,25 +61,10 @@ void DWARFLinkerImpl::LinkContext::addModulesCompileUnit( ModulesCompileUnits.emplace_back(std::move(Unit)); } -Error DWARFLinkerImpl::createEmitter(const Triple &TheTriple, - OutputFileType FileType, - raw_pwrite_stream &OutFile) { - - TheDwarfEmitter = std::make_unique(FileType, OutFile); - - return TheDwarfEmitter->init(TheTriple, "__DWARF"); -} - -ExtraDwarfEmitter *DWARFLinkerImpl::getEmitter() { - return TheDwarfEmitter.get(); -} - void DWARFLinkerImpl::addObjectFile(DWARFFile &File, ObjFileLoaderTy Loader, CompileUnitHandlerTy OnCUDieLoaded) { ObjectContexts.emplace_back(std::make_unique( - GlobalData, File, ClangModules, UniqueUnitID, - (TheDwarfEmitter.get() == nullptr ? std::optional(std::nullopt) - : TheDwarfEmitter->getTargetTriple()))); + GlobalData, File, ClangModules, UniqueUnitID)); if (ObjectContexts.back()->InputDWARFFile.Dwarf) { for (const std::unique_ptr &CU : @@ -117,8 +100,9 @@ Error DWARFLinkerImpl::link() { 0, dwarf::DwarfFormat::DWARF32}; llvm::endianness GlobalEndianness = llvm::endianness::native; - if (TheDwarfEmitter) { - GlobalEndianness = TheDwarfEmitter->getTargetTriple().isLittleEndian() + if (std::optional> CurTriple = + GlobalData.getTargetTriple()) { + GlobalEndianness = (*CurTriple).get().isLittleEndian() ? llvm::endianness::little : llvm::endianness::big; } @@ -131,7 +115,8 @@ Error DWARFLinkerImpl::link() { } if (GlobalData.getOptions().Verbose) { - outs() << "OBJECT: " << Context->InputDWARFFile.FileName << "\n"; + outs() << "DEBUG MAP OBJECT: " << Context->InputDWARFFile.FileName + << "\n"; for (const std::unique_ptr &OrigCU : Context->InputDWARFFile.Dwarf->compile_units()) { @@ -147,7 +132,7 @@ Error DWARFLinkerImpl::link() { if (GlobalData.getOptions().VerifyInputDWARF) verifyInput(Context->InputDWARFFile); - if (!TheDwarfEmitter) + if (!GlobalData.getTargetTriple()) GlobalEndianness = Context->getEndianness(); GlobalFormat.AddrSize = std::max(GlobalFormat.AddrSize, Context->getFormParams().AddrSize); @@ -173,9 +158,9 @@ Error DWARFLinkerImpl::link() { } if (GlobalFormat.AddrSize == 0) { - if (TheDwarfEmitter) - GlobalFormat.AddrSize = - TheDwarfEmitter->getTargetTriple().isArch32Bit() ? 4 : 8; + if (std::optional> TargetTriple = + GlobalData.getTargetTriple()) + GlobalFormat.AddrSize = (*TargetTriple).get().isArch32Bit() ? 4 : 8; else GlobalFormat.AddrSize = 8; } @@ -225,12 +210,10 @@ Error DWARFLinkerImpl::link() { ->getValue() .load() ->Children.empty()) { - std::optional OutTriple = TheDwarfEmitter.get() == nullptr - ? std::optional(std::nullopt) - : TheDwarfEmitter->getTargetTriple(); - - if (Error Err = ArtificialTypeUnit.get()->finishCloningAndEmit(OutTriple)) - return Err; + if (GlobalData.getTargetTriple().has_value()) + if (Error Err = ArtificialTypeUnit.get()->finishCloningAndEmit( + (*GlobalData.getTargetTriple()).get())) + return Err; } // At this stage each compile units are cloned to their own set of debug @@ -258,8 +241,6 @@ Error DWARFLinkerImpl::validateAndUpdateOptions() { return createStringError(std::errc::invalid_argument, "target DWARF version is not set"); - GlobalData.Options.NoOutput = TheDwarfEmitter.get() == nullptr; - if (GlobalData.getOptions().Verbose && GlobalData.getOptions().Threads != 1) { GlobalData.Options.Threads = 1; GlobalData.warn( @@ -690,7 +671,8 @@ void DWARFLinkerImpl::LinkContext::linkSingleCompileUnit( if (CU.isClangModule() || GlobalData.getOptions().UpdateIndexTablesOnly || CU.getContaingFile().Addresses->hasValidRelocs()) { - if (Error Err = CU.cloneAndEmit(TargetTriple, ArtificialTypeUnit)) + if (Error Err = CU.cloneAndEmit(GlobalData.getTargetTriple(), + ArtificialTypeUnit)) return std::move(Err); } @@ -727,7 +709,7 @@ void DWARFLinkerImpl::LinkContext::linkSingleCompileUnit( } Error DWARFLinkerImpl::LinkContext::emitInvariantSections() { - if (GlobalData.getOptions().NoOutput) + if (!GlobalData.getTargetTriple().has_value()) return Error::success(); getOrCreateSectionDescriptor(DebugSectionKind::DebugLoc).OS @@ -749,7 +731,7 @@ Error DWARFLinkerImpl::LinkContext::emitInvariantSections() { } Error DWARFLinkerImpl::LinkContext::cloneAndEmitDebugFrame() { - if (GlobalData.getOptions().NoOutput) + if (!GlobalData.getTargetTriple().has_value()) return Error::success(); if (InputDWARFFile.Dwarf.get() == nullptr) @@ -870,8 +852,9 @@ void DWARFLinkerImpl::LinkContext::emitFDE(uint32_t CIEOffset, } void DWARFLinkerImpl::glueCompileUnitsAndWriteToTheOutput() { - if (GlobalData.getOptions().NoOutput) + if (!GlobalData.getTargetTriple().has_value()) return; + assert(SectionHandler); // Go through all object files, all compile units and assign // offsets to them. @@ -1154,21 +1137,23 @@ void DWARFLinkerImpl::emitCommonSectionsAndWriteCompileUnitsToTheOutput() { AccelTableKind::DebugNames)) CommonSections.getOrCreateSectionDescriptor(DebugSectionKind::DebugNames); - const Triple &TargetTriple = TheDwarfEmitter->getTargetTriple(); - // Emit .debug_str and .debug_line_str sections. TG.spawn([&]() { emitStringSections(); }); if (llvm::is_contained(GlobalData.Options.AccelTables, AccelTableKind::Apple)) { // Emit apple accelerator sections. - TG.spawn([&]() { emitAppleAcceleratorSections(TargetTriple); }); + TG.spawn([&]() { + emitAppleAcceleratorSections((*GlobalData.getTargetTriple()).get()); + }); } if (llvm::is_contained(GlobalData.Options.AccelTables, AccelTableKind::DebugNames)) { // Emit .debug_names section. - TG.spawn([&]() { emitDWARFv5DebugNamesSection(TargetTriple); }); + TG.spawn([&]() { + emitDWARFv5DebugNamesSection((*GlobalData.getTargetTriple()).get()); + }); } // Write compile units to the output file. @@ -1374,7 +1359,8 @@ void DWARFLinkerImpl::emitDWARFv5DebugNamesSection(const Triple &TargetTriple) { case DwarfUnit::AccelType::Namespace: case DwarfUnit::AccelType::Type: { DebugNames->addName(*DebugStrStrings.getExistingEntry(Info.String), - Info.OutOffset, Info.Tag, CU->getUniqueID()); + Info.OutOffset, std::nullopt /*ParentDIEOffset*/, + Info.Tag, CU->getUniqueID()); } break; default: @@ -1419,33 +1405,17 @@ void DWARFLinkerImpl::cleanupDataAfterDWARFOutputIsWritten() { } void DWARFLinkerImpl::writeCompileUnitsToTheOutput() { - bool HasAbbreviations = false; - // Enumerate all sections and store them into the final emitter. forEachObjectSectionsSet([&](OutputSections &Sections) { - Sections.forEach([&](SectionDescriptor &OutSection) { - if (!HasAbbreviations && !OutSection.getContents().empty() && - OutSection.getKind() == DebugSectionKind::DebugAbbrev) - HasAbbreviations = true; - + Sections.forEach([&](std::shared_ptr OutSection) { // Emit section content. - TheDwarfEmitter->emitSectionContents(OutSection.getContents(), - OutSection.getName()); - OutSection.clearSectionContent(); + SectionHandler(OutSection); }); }); - - if (!HasAbbreviations) { - const SmallVector> Abbreviations; - TheDwarfEmitter->emitAbbrevs(Abbreviations, 3); - } } void DWARFLinkerImpl::writeCommonSectionsToTheOutput() { - CommonSections.forEach([&](SectionDescriptor &OutSection) { - // Emit section content. - TheDwarfEmitter->emitSectionContents(OutSection.getContents(), - OutSection.getName()); - OutSection.clearSectionContent(); + CommonSections.forEach([&](std::shared_ptr OutSection) { + SectionHandler(OutSection); }); } diff --git a/llvm/lib/DWARFLinker/Parallel/DWARFLinkerImpl.h b/llvm/lib/DWARFLinker/Parallel/DWARFLinkerImpl.h index b4331df5e32..527c7a0ec36 100644 --- a/llvm/lib/DWARFLinker/Parallel/DWARFLinkerImpl.h +++ b/llvm/lib/DWARFLinker/Parallel/DWARFLinkerImpl.h @@ -29,12 +29,6 @@ public: MessageHandlerTy WarningHandler, TranslatorFuncTy StringsTranslator); - /// Create debug info emitter. - Error createEmitter(const Triple &TheTriple, OutputFileType FileType, - raw_pwrite_stream &OutFile) override; - - ExtraDwarfEmitter *getEmitter() override; - /// Add object file to be linked. Pre-load compile unit die. Call /// \p OnCUDieLoaded for each compile unit die. If specified \p File /// has reference to the Clang module then such module would be @@ -49,6 +43,14 @@ public: /// Link debug info for added files. Error link() override; + /// Set output DWARF handler. May be not set if output generation is not + /// necessary. + void setOutputDWARFHandler(const Triple &TargetTriple, + SectionHandlerTy SectionHandler) override { + GlobalData.setTargetTriple(TargetTriple); + this->SectionHandler = SectionHandler; + } + /// \defgroup Methods setting various linking options: /// /// @{ @@ -190,8 +192,6 @@ protected: StringMap &ClangModules; - std::optional TargetTriple; - /// Flag indicating that new inter-connected compilation units were /// discovered. It is used for restarting units processing /// if new inter-connected units were found. @@ -204,8 +204,7 @@ protected: LinkContext(LinkingGlobalData &GlobalData, DWARFFile &File, StringMap &ClangModules, - std::atomic &UniqueUnitID, - std::optional TargetTriple); + std::atomic &UniqueUnitID); /// Check whether specified \p CUDie is a Clang module reference. /// if \p Quiet is false then display error messages. @@ -364,8 +363,8 @@ protected: /// Common sections. OutputSections CommonSections; - /// The emitter of final dwarf file. - std::unique_ptr TheDwarfEmitter; + /// Hanler for output sections. + SectionHandlerTy SectionHandler = nullptr; /// Overall compile units number. uint64_t OverallNumberOfCU = 0; diff --git a/llvm/lib/DWARFLinker/Parallel/DWARFLinkerTypeUnit.cpp b/llvm/lib/DWARFLinker/Parallel/DWARFLinkerTypeUnit.cpp index 397411895a8..3030aa2c39b 100644 --- a/llvm/lib/DWARFLinker/Parallel/DWARFLinkerTypeUnit.cpp +++ b/llvm/lib/DWARFLinker/Parallel/DWARFLinkerTypeUnit.cpp @@ -337,11 +337,11 @@ uint8_t TypeUnit::getSizeByAttrForm(dwarf::Form Form) const { llvm_unreachable("Unsupported Attr Form"); } -Error TypeUnit::finishCloningAndEmit(std::optional TargetTriple) { +Error TypeUnit::finishCloningAndEmit(const Triple &TargetTriple) { BumpPtrAllocator Allocator; createDIETree(Allocator); - if (getGlobalData().getOptions().NoOutput || (getOutUnitDIE() == nullptr)) + if (getOutUnitDIE() == nullptr) return Error::success(); // Create sections ahead so that they should not be created asynchronously @@ -360,14 +360,12 @@ Error TypeUnit::finishCloningAndEmit(std::optional TargetTriple) { // Add task for emitting .debug_line section. if (!LineTable.Prologue.FileNames.empty()) { - Tasks.push_back([&]() -> Error { - assert(TargetTriple.has_value()); - return emitDebugLine(*TargetTriple, LineTable); - }); + Tasks.push_back( + [&]() -> Error { return emitDebugLine(TargetTriple, LineTable); }); } // Add task for emitting .debug_info section. - Tasks.push_back([&]() -> Error { return emitDebugInfo(*TargetTriple); }); + Tasks.push_back([&]() -> Error { return emitDebugInfo(TargetTriple); }); // Add task for emitting Pub accelerator sections. if (llvm::is_contained(GlobalData.getOptions().AccelTables, diff --git a/llvm/lib/DWARFLinker/Parallel/DWARFLinkerTypeUnit.h b/llvm/lib/DWARFLinker/Parallel/DWARFLinkerTypeUnit.h index 0944de8d131..328da5c0570 100644 --- a/llvm/lib/DWARFLinker/Parallel/DWARFLinkerTypeUnit.h +++ b/llvm/lib/DWARFLinker/Parallel/DWARFLinkerTypeUnit.h @@ -31,7 +31,7 @@ public: void createDIETree(BumpPtrAllocator &Allocator); /// Emits resulting dwarf based on information from DIE tree. - Error finishCloningAndEmit(std::optional TargetTriple); + Error finishCloningAndEmit(const Triple &TargetTriple); /// Returns global type pool. TypePool &getTypePool() { return Types; } diff --git a/llvm/lib/DWARFLinker/Parallel/DWARFLinkerUnit.h b/llvm/lib/DWARFLinker/Parallel/DWARFLinkerUnit.h index 36c24372e49..e16b82f696a 100644 --- a/llvm/lib/DWARFLinker/Parallel/DWARFLinkerUnit.h +++ b/llvm/lib/DWARFLinker/Parallel/DWARFLinkerUnit.h @@ -10,9 +10,9 @@ #define LLVM_LIB_DWARFLINKER_PARALLEL_DWARFLINKERUNIT_H #include "DWARFLinkerGlobalData.h" -#include "IndexedValuesMap.h" #include "OutputSections.h" #include "llvm/CodeGen/DIE.h" +#include "llvm/DWARFLinker/IndexedValuesMap.h" #include "llvm/DWARFLinker/Parallel/DWARFLinker.h" #include "llvm/DWARFLinker/StringPool.h" #include "llvm/DebugInfo/DWARF/DWARFUnit.h" diff --git a/llvm/lib/DWARFLinker/Parallel/DependencyTracker.cpp b/llvm/lib/DWARFLinker/Parallel/DependencyTracker.cpp index 04152e7f9f2..5e30d9a8b66 100644 --- a/llvm/lib/DWARFLinker/Parallel/DependencyTracker.cpp +++ b/llvm/lib/DWARFLinker/Parallel/DependencyTracker.cpp @@ -741,7 +741,7 @@ bool DependencyTracker::isLiveVariableEntry(const UnitEntryPairTy &Entry, // enclosing function, unless requested explicitly. std::pair> LocExprAddrAndRelocAdjustment = Entry.CU->getContaingFile().Addresses->getVariableRelocAdjustment( - DIE); + DIE, Entry.CU->getGlobalData().getOptions().Verbose); if (LocExprAddrAndRelocAdjustment.first) Info.setHasAnAddress(); @@ -784,7 +784,7 @@ bool DependencyTracker::isLiveSubprogramEntry(const UnitEntryPairTy &Entry) { RelocAdjustment = Entry.CU->getContaingFile().Addresses->getSubprogramRelocAdjustment( - DIE); + DIE, Entry.CU->getGlobalData().getOptions().Verbose); if (!RelocAdjustment) return false; diff --git a/llvm/lib/DWARFLinker/Parallel/OutputSections.cpp b/llvm/lib/DWARFLinker/Parallel/OutputSections.cpp index cd1205b60f8..d03f9b40d49 100644 --- a/llvm/lib/DWARFLinker/Parallel/OutputSections.cpp +++ b/llvm/lib/DWARFLinker/Parallel/OutputSections.cpp @@ -15,59 +15,6 @@ using namespace llvm; using namespace dwarf_linker; using namespace dwarf_linker::parallel; -std::optional -dwarf_linker::parallel::parseDebugTableName(llvm::StringRef SecName) { - return llvm::StringSwitch>( - SecName.substr(SecName.find_first_not_of("._"))) - .Case(getSectionName(DebugSectionKind::DebugInfo), - DebugSectionKind::DebugInfo) - .Case(getSectionName(DebugSectionKind::DebugLine), - DebugSectionKind::DebugLine) - .Case(getSectionName(DebugSectionKind::DebugFrame), - DebugSectionKind::DebugFrame) - .Case(getSectionName(DebugSectionKind::DebugRange), - DebugSectionKind::DebugRange) - .Case(getSectionName(DebugSectionKind::DebugRngLists), - DebugSectionKind::DebugRngLists) - .Case(getSectionName(DebugSectionKind::DebugLoc), - DebugSectionKind::DebugLoc) - .Case(getSectionName(DebugSectionKind::DebugLocLists), - DebugSectionKind::DebugLocLists) - .Case(getSectionName(DebugSectionKind::DebugARanges), - DebugSectionKind::DebugARanges) - .Case(getSectionName(DebugSectionKind::DebugAbbrev), - DebugSectionKind::DebugAbbrev) - .Case(getSectionName(DebugSectionKind::DebugMacinfo), - DebugSectionKind::DebugMacinfo) - .Case(getSectionName(DebugSectionKind::DebugMacro), - DebugSectionKind::DebugMacro) - .Case(getSectionName(DebugSectionKind::DebugAddr), - DebugSectionKind::DebugAddr) - .Case(getSectionName(DebugSectionKind::DebugStr), - DebugSectionKind::DebugStr) - .Case(getSectionName(DebugSectionKind::DebugLineStr), - DebugSectionKind::DebugLineStr) - .Case(getSectionName(DebugSectionKind::DebugStrOffsets), - DebugSectionKind::DebugStrOffsets) - .Case(getSectionName(DebugSectionKind::DebugPubNames), - DebugSectionKind::DebugPubNames) - .Case(getSectionName(DebugSectionKind::DebugPubTypes), - DebugSectionKind::DebugPubTypes) - .Case(getSectionName(DebugSectionKind::DebugNames), - DebugSectionKind::DebugNames) - .Case(getSectionName(DebugSectionKind::AppleNames), - DebugSectionKind::AppleNames) - .Case(getSectionName(DebugSectionKind::AppleNamespaces), - DebugSectionKind::AppleNamespaces) - .Case(getSectionName(DebugSectionKind::AppleObjC), - DebugSectionKind::AppleObjC) - .Case(getSectionName(DebugSectionKind::AppleTypes), - DebugSectionKind::AppleTypes) - .Default(std::nullopt); - - return std::nullopt; -} - DebugDieRefPatch::DebugDieRefPatch(uint64_t PatchOffset, CompileUnit *SrcCU, CompileUnit *RefCU, uint32_t RefIdx) : SectionPatch({PatchOffset}), diff --git a/llvm/lib/DWARFLinker/Parallel/OutputSections.h b/llvm/lib/DWARFLinker/Parallel/OutputSections.h index b9df2228920..a21e4b2b75a 100644 --- a/llvm/lib/DWARFLinker/Parallel/OutputSections.h +++ b/llvm/lib/DWARFLinker/Parallel/OutputSections.h @@ -34,51 +34,6 @@ namespace parallel { class TypeUnit; -/// List of tracked debug tables. -enum class DebugSectionKind : uint8_t { - DebugInfo = 0, - DebugLine, - DebugFrame, - DebugRange, - DebugRngLists, - DebugLoc, - DebugLocLists, - DebugARanges, - DebugAbbrev, - DebugMacinfo, - DebugMacro, - DebugAddr, - DebugStr, - DebugLineStr, - DebugStrOffsets, - DebugPubNames, - DebugPubTypes, - DebugNames, - AppleNames, - AppleNamespaces, - AppleObjC, - AppleTypes, - NumberOfEnumEntries // must be last -}; -constexpr static size_t SectionKindsNum = - static_cast(DebugSectionKind::NumberOfEnumEntries); - -static constexpr StringLiteral SectionNames[SectionKindsNum] = { - "debug_info", "debug_line", "debug_frame", "debug_ranges", - "debug_rnglists", "debug_loc", "debug_loclists", "debug_aranges", - "debug_abbrev", "debug_macinfo", "debug_macro", "debug_addr", - "debug_str", "debug_line_str", "debug_str_offsets", "debug_pubnames", - "debug_pubtypes", "debug_names", "apple_names", "apple_namespac", - "apple_objc", "apple_types"}; - -static constexpr const StringLiteral & -getSectionName(DebugSectionKind SectionKind) { - return SectionNames[static_cast(SectionKind)]; -} - -/// Recognise the table name and match it with the DebugSectionKind. -std::optional parseDebugTableName(StringRef Name); - /// There are fields(sizes, offsets) which should be updated after /// sections are generated. To remember offsets and related data /// the descendants of SectionPatch structure should be used. @@ -194,12 +149,13 @@ class OutputSections; /// This structure is used to keep data of the concrete section. /// Like data bits, list of patches, format. -struct SectionDescriptor { +struct SectionDescriptor : SectionDescriptorBase { friend OutputSections; SectionDescriptor(DebugSectionKind SectionKind, LinkingGlobalData &GlobalData, dwarf::FormParams Format, llvm::endianness Endianess) - : OS(Contents), ListDebugStrPatch(&GlobalData.getAllocator()), + : SectionDescriptorBase(SectionKind, Format, Endianess), OS(Contents), + ListDebugStrPatch(&GlobalData.getAllocator()), ListDebugLineStrPatch(&GlobalData.getAllocator()), ListDebugRangePatch(&GlobalData.getAllocator()), ListDebugLocPatch(&GlobalData.getAllocator()), @@ -211,10 +167,9 @@ struct SectionDescriptor { ListDebugTypeStrPatch(&GlobalData.getAllocator()), ListDebugTypeLineStrPatch(&GlobalData.getAllocator()), ListDebugTypeDeclFilePatch(&GlobalData.getAllocator()), - GlobalData(GlobalData), SectionKind(SectionKind), Format(Format), - Endianess(Endianess) {} + GlobalData(GlobalData) {} - /// Erase whole section contents(data bits, list of patches). + /// Erase whole section content(data bits, list of patches). void clearAllSectionData(); /// Erase only section output data bits. @@ -263,7 +218,7 @@ struct SectionDescriptor { void setSizesForSectionCreatedByAsmPrinter(); /// Returns section content. - StringRef getContents() { + StringRef getContents() override { if (SectionOffsetInsideAsmPrinterOutputStart == 0) return StringRef(Contents.data(), Contents.size()); @@ -311,18 +266,6 @@ struct SectionDescriptor { /// Write specified \p Value of \p AttrForm to the \p PatchOffset. void apply(uint64_t PatchOffset, dwarf::Form AttrForm, uint64_t Val); - /// Returns section kind. - DebugSectionKind getKind() { return SectionKind; } - - /// Returns section name. - const StringLiteral &getName() const { return getSectionName(SectionKind); } - - /// Returns endianess used by section. - llvm::endianness getEndianess() const { return Endianess; } - - /// Returns FormParams used by section. - dwarf::FormParams getFormParams() const { return Format; } - /// Returns integer value of \p Size located by specified \p PatchOffset. uint64_t getIntVal(uint64_t PatchOffset, unsigned Size); @@ -344,9 +287,6 @@ protected: LinkingGlobalData &GlobalData; - /// The section kind. - DebugSectionKind SectionKind = DebugSectionKind::NumberOfEnumEntries; - /// Section data bits. OutSectionDataTy Contents; @@ -355,10 +295,6 @@ protected: /// real section content inside elf file. size_t SectionOffsetInsideAsmPrinterOutputStart = 0; size_t SectionOffsetInsideAsmPrinterOutputEnd = 0; - - /// Output format. - dwarf::FormParams Format = {4, 4, dwarf::DWARF32}; - llvm::endianness Endianess = llvm::endianness::little; }; /// This class keeps contents and offsets to the debug sections. Any objects @@ -387,7 +323,7 @@ public: .str() .c_str()); - return It->second; + return *It->second; } /// Returns descriptor for the specified section of \p SectionKind. @@ -402,7 +338,9 @@ public: .str() .c_str()); - return It->second; + assert(It->second.get() != nullptr); + + return *It->second; } /// Returns descriptor for the specified section of \p SectionKind. @@ -414,7 +352,7 @@ public: if (It == SectionDescriptors.end()) return std::nullopt; - return &It->second; + return It->second.get(); } /// Returns descriptor for the specified section of \p SectionKind. @@ -426,26 +364,44 @@ public: if (It == SectionDescriptors.end()) return std::nullopt; - return &It->second; + return It->second.get(); } /// Returns descriptor for the specified section of \p SectionKind. /// If descriptor does not exist then creates it. SectionDescriptor & getOrCreateSectionDescriptor(DebugSectionKind SectionKind) { - return SectionDescriptors - .try_emplace(SectionKind, SectionKind, GlobalData, Format, Endianness) - .first->second; + SectionsSetTy::iterator It = SectionDescriptors.find(SectionKind); + + if (It == SectionDescriptors.end()) { + SectionDescriptor *Section = + new SectionDescriptor(SectionKind, GlobalData, Format, Endianness); + auto Result = SectionDescriptors.try_emplace(SectionKind, Section); + assert(Result.second); + + It = Result.first; + } + + return *It->second; } /// Erases data of all sections. void eraseSections() { for (auto &Section : SectionDescriptors) - Section.second.clearAllSectionData(); + Section.second->clearAllSectionData(); } /// Enumerate all sections and call \p Handler for each. void forEach(function_ref Handler) { + for (auto &Section : SectionDescriptors) { + assert(Section.second.get() != nullptr); + Handler(*(Section.second)); + } + } + + /// Enumerate all sections and call \p Handler for each. + void forEach( + function_ref Section)> Handler) { for (auto &Section : SectionDescriptors) Handler(Section.second); } @@ -456,10 +412,11 @@ public: void assignSectionsOffsetAndAccumulateSize( std::array &SectionSizesAccumulator) { for (auto &Section : SectionDescriptors) { - Section.second.StartOffset = SectionSizesAccumulator[static_cast( - Section.second.getKind())]; - SectionSizesAccumulator[static_cast(Section.second.getKind())] += - Section.second.getContents().size(); + Section.second->StartOffset = + SectionSizesAccumulator[static_cast( + Section.second->getKind())]; + SectionSizesAccumulator[static_cast( + Section.second->getKind())] += Section.second->getContents().size(); } } @@ -505,7 +462,8 @@ protected: llvm::endianness Endianness = llvm::endianness::native; /// All keeping sections. - using SectionsSetTy = std::map; + using SectionsSetTy = + std::map>; SectionsSetTy SectionDescriptors; }; diff --git a/llvm/lib/DebugInfo/DWARF/DWARFCompileUnit.cpp b/llvm/lib/DebugInfo/DWARF/DWARFCompileUnit.cpp index 6461f2ac031..30afa651ffc 100644 --- a/llvm/lib/DebugInfo/DWARF/DWARFCompileUnit.cpp +++ b/llvm/lib/DebugInfo/DWARF/DWARFCompileUnit.cpp @@ -35,10 +35,16 @@ void DWARFCompileUnit::dump(raw_ostream &OS, DIDumpOptions DumpOpts) { OS << " (next unit at " << format("0x%08" PRIx64, getNextUnitOffset()) << ")\n"; - if (DWARFDie CUDie = getUnitDIE(false)) + if (DWARFDie CUDie = getUnitDIE(false)) { CUDie.dump(OS, 0, DumpOpts); - else + if (DumpOpts.DumpNonSkeleton) { + DWARFDie NonSkeletonCUDie = getNonSkeletonUnitDIE(false); + if (NonSkeletonCUDie && CUDie != NonSkeletonCUDie) + NonSkeletonCUDie.dump(OS, 0, DumpOpts); + } + } else { OS << "\n\n"; + } } // VTable anchor. diff --git a/llvm/lib/DebugInfo/DWARF/DWARFContext.cpp b/llvm/lib/DebugInfo/DWARF/DWARFContext.cpp index c671aedbc9e..792df53d304 100644 --- a/llvm/lib/DebugInfo/DWARF/DWARFContext.cpp +++ b/llvm/lib/DebugInfo/DWARF/DWARFContext.cpp @@ -1024,9 +1024,17 @@ void DWARFContext::dump( auto dumpDebugInfo = [&](const char *Name, unit_iterator_range Units) { OS << '\n' << Name << " contents:\n"; if (auto DumpOffset = DumpOffsets[DIDT_ID_DebugInfo]) - for (const auto &U : Units) + for (const auto &U : Units) { U->getDIEForOffset(*DumpOffset) .dump(OS, 0, DumpOpts.noImplicitRecursion()); + DWARFDie CUDie = U->getUnitDIE(false); + DWARFDie CUNonSkeletonDie = U->getNonSkeletonUnitDIE(false); + if (CUNonSkeletonDie && CUDie != CUNonSkeletonDie) { + CUNonSkeletonDie.getDwarfUnit() + ->getDIEForOffset(*DumpOffset) + .dump(OS, 0, DumpOpts.noImplicitRecursion()); + } + } else for (const auto &U : Units) U->dump(OS, DumpOpts); @@ -1345,11 +1353,7 @@ DWARFTypeUnit *DWARFContext::getTypeUnitForHash(uint16_t Version, uint64_t Hash, DWOUnits.getUnitForIndexEntry(*R)); return nullptr; } - const DenseMap &Map = State->getTypeUnitMap(IsDWO); - auto Iter = Map.find(Hash); - if (Iter != Map.end()) - return Iter->second; - return nullptr; + return State->getTypeUnitMap(IsDWO).lookup(Hash); } DWARFCompileUnit *DWARFContext::getDWOCompileUnitForHash(uint64_t Hash) { @@ -1537,15 +1541,38 @@ DWARFCompileUnit *DWARFContext::getCompileUnitForDataAddress(uint64_t Address) { return nullptr; } -DWARFContext::DIEsForAddress DWARFContext::getDIEsForAddress(uint64_t Address) { +DWARFContext::DIEsForAddress DWARFContext::getDIEsForAddress(uint64_t Address, + bool CheckDWO) { DIEsForAddress Result; DWARFCompileUnit *CU = getCompileUnitForCodeAddress(Address); if (!CU) return Result; - Result.CompileUnit = CU; - Result.FunctionDIE = CU->getSubroutineForAddress(Address); + if (CheckDWO) { + // We were asked to check the DWO file and this debug information is more + // complete that any information in the skeleton compile unit, so search the + // DWO first to see if we have a match. + DWARFDie CUDie = CU->getUnitDIE(false); + DWARFDie CUDwoDie = CU->getNonSkeletonUnitDIE(false); + if (CheckDWO && CUDwoDie && CUDie != CUDwoDie) { + // We have a DWO file, lets search it. + DWARFCompileUnit *CUDwo = + dyn_cast_or_null(CUDwoDie.getDwarfUnit()); + if (CUDwo) { + Result.FunctionDIE = CUDwo->getSubroutineForAddress(Address); + if (Result.FunctionDIE) + Result.CompileUnit = CUDwo; + } + } + } + + // Search the normal DWARF if we didn't find a match in the DWO file or if + // we didn't check the DWO file above. + if (!Result) { + Result.CompileUnit = CU; + Result.FunctionDIE = CU->getSubroutineForAddress(Address); + } std::vector Worklist; Worklist.push_back(Result.FunctionDIE); diff --git a/llvm/lib/DebugInfo/DWARF/DWARFDebugLine.cpp b/llvm/lib/DebugInfo/DWARF/DWARFDebugLine.cpp index 78792cf8389..28f05644a3a 100644 --- a/llvm/lib/DebugInfo/DWARF/DWARFDebugLine.cpp +++ b/llvm/lib/DebugInfo/DWARF/DWARFDebugLine.cpp @@ -1456,7 +1456,7 @@ bool DWARFDebugLine::Prologue::getFileNameByIndex( // sys::path::append skips empty strings. sys::path::append(FilePath, Style, IncludeDir, FileName); - Result = std::string(FilePath.str()); + Result = std::string(FilePath); return true; } diff --git a/llvm/lib/DebugInfo/DWARF/DWARFTypePrinter.cpp b/llvm/lib/DebugInfo/DWARF/DWARFTypePrinter.cpp index 20242d958b6..76817fda441 100644 --- a/llvm/lib/DebugInfo/DWARF/DWARFTypePrinter.cpp +++ b/llvm/lib/DebugInfo/DWARF/DWARFTypePrinter.cpp @@ -181,8 +181,7 @@ DWARFTypePrinter::appendUnqualifiedNameBefore(DWARFDie D, Word = true; StringRef Name = NamePtr; static constexpr StringRef MangledPrefix = "_STN|"; - if (Name.starts_with(MangledPrefix)) { - Name = Name.drop_front(MangledPrefix.size()); + if (Name.consume_front(MangledPrefix)) { auto Separator = Name.find('|'); assert(Separator != StringRef::npos); StringRef BaseName = Name.substr(0, Separator); diff --git a/llvm/lib/DebugInfo/DWARF/DWARFVerifier.cpp b/llvm/lib/DebugInfo/DWARF/DWARFVerifier.cpp index d25b732fdba..c4c14f5e2c9 100644 --- a/llvm/lib/DebugInfo/DWARF/DWARFVerifier.cpp +++ b/llvm/lib/DebugInfo/DWARF/DWARFVerifier.cpp @@ -7,6 +7,7 @@ //===----------------------------------------------------------------------===// #include "llvm/DebugInfo/DWARF/DWARFVerifier.h" #include "llvm/ADT/IntervalMap.h" +#include "llvm/ADT/STLExtras.h" #include "llvm/ADT/SmallSet.h" #include "llvm/BinaryFormat/Dwarf.h" #include "llvm/DebugInfo/DWARF/DWARFAbbreviationDeclaration.h" @@ -1272,6 +1273,20 @@ unsigned DWARFVerifier::verifyNameIndexAttribute( NI.getUnitOffset(), Abbr.Code, AttrEnc.Form, dwarf::DW_FORM_data8); return 1; } + return 0; + } + + if (AttrEnc.Index == dwarf::DW_IDX_parent) { + constexpr static auto AllowedForms = {dwarf::Form::DW_FORM_flag_present, + dwarf::Form::DW_FORM_ref4}; + if (!is_contained(AllowedForms, AttrEnc.Form)) { + error() << formatv("NameIndex @ {0:x}: Abbreviation {1:x}: DW_IDX_parent " + "uses an unexpected form {2} (should be " + "DW_FORM_ref4 or DW_FORM_flag_present).\n", + NI.getUnitOffset(), Abbr.Code, AttrEnc.Form); + return 1; + } + return 0; } // A list of known index attributes and their expected form classes. @@ -1286,7 +1301,6 @@ unsigned DWARFVerifier::verifyNameIndexAttribute( {dwarf::DW_IDX_compile_unit, DWARFFormValue::FC_Constant, {"constant"}}, {dwarf::DW_IDX_type_unit, DWARFFormValue::FC_Constant, {"constant"}}, {dwarf::DW_IDX_die_offset, DWARFFormValue::FC_Reference, {"reference"}}, - {dwarf::DW_IDX_parent, DWARFFormValue::FC_Constant, {"constant"}}, }; ArrayRef TableRef(Table); diff --git a/llvm/lib/DebugInfo/LogicalView/Readers/LVCodeViewReader.cpp b/llvm/lib/DebugInfo/LogicalView/Readers/LVCodeViewReader.cpp index 1f6724988ae..fca18e19578 100644 --- a/llvm/lib/DebugInfo/LogicalView/Readers/LVCodeViewReader.cpp +++ b/llvm/lib/DebugInfo/LogicalView/Readers/LVCodeViewReader.cpp @@ -217,9 +217,7 @@ Error LVCodeViewReader::resolveSymbolName(const coff_section *CoffSection, // and they are printed only if the command line option 'internal=system'. bool LVCodeViewReader::isSystemEntry(LVElement *Element, StringRef Name) const { Name = Name.empty() ? Element->getName() : Name; - auto Find = [=](const char *String) -> bool { - return StringRef::npos != Name.find(String); - }; + auto Find = [=](const char *String) -> bool { return Name.contains(String); }; auto Starts = [=](const char *Pattern) -> bool { return Name.starts_with(Pattern); }; diff --git a/llvm/lib/DebugInfo/Symbolize/MarkupFilter.cpp b/llvm/lib/DebugInfo/Symbolize/MarkupFilter.cpp index 01d49709f9b..3528da42b12 100644 --- a/llvm/lib/DebugInfo/Symbolize/MarkupFilter.cpp +++ b/llvm/lib/DebugInfo/Symbolize/MarkupFilter.cpp @@ -611,12 +611,9 @@ std::optional MarkupFilter::parseMode(StringRef Str) const { // Pop off each of r/R, w/W, and x/X from the front, in that order. StringRef Remainder = Str; - if (!Remainder.empty() && tolower(Remainder.front()) == 'r') - Remainder = Remainder.drop_front(); - if (!Remainder.empty() && tolower(Remainder.front()) == 'w') - Remainder = Remainder.drop_front(); - if (!Remainder.empty() && tolower(Remainder.front()) == 'x') - Remainder = Remainder.drop_front(); + Remainder.consume_front_insensitive("r"); + Remainder.consume_front_insensitive("w"); + Remainder.consume_front_insensitive("x"); // If anything remains, then the string wasn't a mode. if (!Remainder.empty()) { diff --git a/llvm/lib/DebugInfo/Symbolize/SymbolizableObjectFile.cpp b/llvm/lib/DebugInfo/Symbolize/SymbolizableObjectFile.cpp index 0c404327c69..d4fc48e146f 100644 --- a/llvm/lib/DebugInfo/Symbolize/SymbolizableObjectFile.cpp +++ b/llvm/lib/DebugInfo/Symbolize/SymbolizableObjectFile.cpp @@ -210,8 +210,8 @@ Error SymbolizableObjectFile::addSymbol(const SymbolRef &Symbol, SymbolAddress = OpdExtractor->getAddress(&OpdOffset); } // Mach-O symbol table names have leading underscore, skip it. - if (Module->isMachO() && !SymbolName.empty() && SymbolName[0] == '_') - SymbolName = SymbolName.drop_front(); + if (Module->isMachO()) + SymbolName.consume_front("_"); if (Obj.isELF() && ELFSymbolRef(Symbol).getBinding() != ELF::STB_LOCAL) ELFSymIdx = 0; diff --git a/llvm/lib/DebugInfo/Symbolize/Symbolize.cpp b/llvm/lib/DebugInfo/Symbolize/Symbolize.cpp index 43e5c9e9329..5f29226c14b 100644 --- a/llvm/lib/DebugInfo/Symbolize/Symbolize.cpp +++ b/llvm/lib/DebugInfo/Symbolize/Symbolize.cpp @@ -303,7 +303,7 @@ std::string getDarwinDWARFResourceForPath(const std::string &Path, } sys::path::append(ResourceName, "Contents", "Resources", "DWARF"); sys::path::append(ResourceName, Basename); - return std::string(ResourceName.str()); + return std::string(ResourceName); } bool checkFileCRC(StringRef Path, uint32_t CRCHash) { @@ -434,14 +434,14 @@ bool LLVMSymbolizer::findDebugBinary(const std::string &OrigPath, // Try relative/path/to/original_binary/debuglink_name llvm::sys::path::append(DebugPath, DebuglinkName); if (checkFileCRC(DebugPath, CRCHash)) { - Result = std::string(DebugPath.str()); + Result = std::string(DebugPath); return true; } // Try relative/path/to/original_binary/.debug/debuglink_name DebugPath = OrigDir; llvm::sys::path::append(DebugPath, ".debug", DebuglinkName); if (checkFileCRC(DebugPath, CRCHash)) { - Result = std::string(DebugPath.str()); + Result = std::string(DebugPath); return true; } // Make the path absolute so that lookups will go to @@ -463,7 +463,7 @@ bool LLVMSymbolizer::findDebugBinary(const std::string &OrigPath, llvm::sys::path::append(DebugPath, llvm::sys::path::relative_path(OrigDir), DebuglinkName); if (checkFileCRC(DebugPath, CRCHash)) { - Result = std::string(DebugPath.str()); + Result = std::string(DebugPath); return true; } return false; diff --git a/llvm/lib/Debuginfod/Debuginfod.cpp b/llvm/lib/Debuginfod/Debuginfod.cpp index 9df30ab55cb..4928fcb3b3f 100644 --- a/llvm/lib/Debuginfod/Debuginfod.cpp +++ b/llvm/lib/Debuginfod/Debuginfod.cpp @@ -54,7 +54,7 @@ std::optional> DebuginfodUrls; llvm::sys::RWMutex UrlsMutex; } // namespace -static std::string uniqueKey(llvm::StringRef S) { +std::string getDebuginfodCacheKey(llvm::StringRef S) { return utostr(xxh3_64bits(S)); } @@ -72,7 +72,7 @@ SmallVector getDefaultDebuginfodUrls() { std::shared_lock ReadGuard(UrlsMutex); if (!DebuginfodUrls) { // Only read from the environment variable if the user hasn't already - // set the value + // set the value. ReadGuard.unlock(); std::unique_lock WriteGuard(UrlsMutex); DebuginfodUrls = SmallVector(); @@ -86,7 +86,7 @@ SmallVector getDefaultDebuginfodUrls() { return DebuginfodUrls.value(); } -// Set the default debuginfod URL list, override the environment variable +// Set the default debuginfod URL list, override the environment variable. void setDefaultDebuginfodUrls(const SmallVector &URLs) { std::unique_lock WriteGuard(UrlsMutex); DebuginfodUrls = URLs; @@ -120,27 +120,43 @@ std::chrono::milliseconds getDefaultDebuginfodTimeout() { /// cache and return the cached file path. They first search the local cache, /// followed by the debuginfod servers. -Expected getCachedOrDownloadSource(BuildIDRef ID, - StringRef SourceFilePath) { +std::string getDebuginfodSourceUrlPath(BuildIDRef ID, + StringRef SourceFilePath) { SmallString<64> UrlPath; sys::path::append(UrlPath, sys::path::Style::posix, "buildid", buildIDToString(ID), "source", sys::path::convert_to_slash(SourceFilePath)); - return getCachedOrDownloadArtifact(uniqueKey(UrlPath), UrlPath); + return std::string(UrlPath); } -Expected getCachedOrDownloadExecutable(BuildIDRef ID) { +Expected getCachedOrDownloadSource(BuildIDRef ID, + StringRef SourceFilePath) { + std::string UrlPath = getDebuginfodSourceUrlPath(ID, SourceFilePath); + return getCachedOrDownloadArtifact(getDebuginfodCacheKey(UrlPath), UrlPath); +} + +std::string getDebuginfodExecutableUrlPath(BuildIDRef ID) { SmallString<64> UrlPath; sys::path::append(UrlPath, sys::path::Style::posix, "buildid", buildIDToString(ID), "executable"); - return getCachedOrDownloadArtifact(uniqueKey(UrlPath), UrlPath); + return std::string(UrlPath); } -Expected getCachedOrDownloadDebuginfo(BuildIDRef ID) { +Expected getCachedOrDownloadExecutable(BuildIDRef ID) { + std::string UrlPath = getDebuginfodExecutableUrlPath(ID); + return getCachedOrDownloadArtifact(getDebuginfodCacheKey(UrlPath), UrlPath); +} + +std::string getDebuginfodDebuginfoUrlPath(BuildIDRef ID) { SmallString<64> UrlPath; sys::path::append(UrlPath, sys::path::Style::posix, "buildid", buildIDToString(ID), "debuginfo"); - return getCachedOrDownloadArtifact(uniqueKey(UrlPath), UrlPath); + return std::string(UrlPath); +} + +Expected getCachedOrDownloadDebuginfo(BuildIDRef ID) { + std::string UrlPath = getDebuginfodDebuginfoUrlPath(ID); + return getCachedOrDownloadArtifact(getDebuginfodCacheKey(UrlPath), UrlPath); } // General fetching function. diff --git a/llvm/lib/ExecutionEngine/ExecutionEngine.cpp b/llvm/lib/ExecutionEngine/ExecutionEngine.cpp index 2559ed6a31a..31c290ad505 100644 --- a/llvm/lib/ExecutionEngine/ExecutionEngine.cpp +++ b/llvm/lib/ExecutionEngine/ExecutionEngine.cpp @@ -197,7 +197,7 @@ std::string ExecutionEngine::getMangledName(const GlobalValue *GV) { : GV->getParent()->getDataLayout(); Mangler::getNameWithPrefix(FullName, GV->getName(), DL); - return std::string(FullName.str()); + return std::string(FullName); } void ExecutionEngine::addGlobalMapping(const GlobalValue *GV, void *Addr) { @@ -386,7 +386,7 @@ void ExecutionEngine::runStaticConstructorsDestructors(Module &module, Constant *FP = CS->getOperand(1); if (FP->isNullValue()) - continue; // Found a sentinal value, ignore. + continue; // Found a sentinel value, ignore. // Strip off constant expression casts. if (ConstantExpr *CE = dyn_cast(FP)) diff --git a/llvm/lib/ExecutionEngine/JITLink/ELFLinkGraphBuilder.h b/llvm/lib/ExecutionEngine/JITLink/ELFLinkGraphBuilder.h index 56d1efa4bde..e1b11dfcfc2 100644 --- a/llvm/lib/ExecutionEngine/JITLink/ELFLinkGraphBuilder.h +++ b/llvm/lib/ExecutionEngine/JITLink/ELFLinkGraphBuilder.h @@ -397,6 +397,12 @@ template Error ELFLinkGraphBuilder::graphifySections() { orc::ExecutorAddr(Sec.sh_addr), Sec.sh_addralign, 0); + if (Sec.sh_type == ELF::SHT_ARM_EXIDX) { + // Add live symbol to avoid dead-stripping for .ARM.exidx sections + G->addAnonymousSymbol(*B, orc::ExecutorAddrDiff(), + orc::ExecutorAddrDiff(), false, true); + } + setGraphBlock(SecIndex, B); } diff --git a/llvm/lib/ExecutionEngine/JITLink/ELF_aarch32.cpp b/llvm/lib/ExecutionEngine/JITLink/ELF_aarch32.cpp index 132989fcbce..908b88fef1b 100644 --- a/llvm/lib/ExecutionEngine/JITLink/ELF_aarch32.cpp +++ b/llvm/lib/ExecutionEngine/JITLink/ELF_aarch32.cpp @@ -31,10 +31,13 @@ namespace llvm { namespace jitlink { /// Translate from ELF relocation type to JITLink-internal edge kind. -Expected getJITLinkEdgeKind(uint32_t ELFType) { +Expected +getJITLinkEdgeKind(uint32_t ELFType, const aarch32::ArmConfig &ArmCfg) { switch (ELFType) { case ELF::R_ARM_ABS32: return aarch32::Data_Pointer32; + case ELF::R_ARM_GOT_PREL: + return aarch32::Data_RequestGOTAndTransformToDelta32; case ELF::R_ARM_REL32: return aarch32::Data_Delta32; case ELF::R_ARM_CALL: @@ -45,6 +48,13 @@ Expected getJITLinkEdgeKind(uint32_t ELFType) { return aarch32::Arm_MovwAbsNC; case ELF::R_ARM_MOVT_ABS: return aarch32::Arm_MovtAbs; + case ELF::R_ARM_NONE: + return aarch32::None; + case ELF::R_ARM_PREL31: + return aarch32::Data_PRel31; + case ELF::R_ARM_TARGET1: + return (ArmCfg.Target1Rel) ? aarch32::Data_Delta32 + : aarch32::Data_Pointer32; case ELF::R_ARM_THM_CALL: return aarch32::Thumb_Call; case ELF::R_ARM_THM_JUMP24: @@ -71,6 +81,10 @@ Expected getELFRelocationType(Edge::Kind Kind) { return ELF::R_ARM_REL32; case aarch32::Data_Pointer32: return ELF::R_ARM_ABS32; + case aarch32::Data_PRel31: + return ELF::R_ARM_PREL31; + case aarch32::Data_RequestGOTAndTransformToDelta32: + return ELF::R_ARM_GOT_PREL; case aarch32::Arm_Call: return ELF::R_ARM_CALL; case aarch32::Arm_Jump24: @@ -91,6 +105,8 @@ Expected getELFRelocationType(Edge::Kind Kind) { return ELF::R_ARM_THM_MOVW_PREL_NC; case aarch32::Thumb_MovtPrel: return ELF::R_ARM_THM_MOVT_PREL; + case aarch32::None: + return ELF::R_ARM_NONE; } return make_error(formatv("Invalid aarch32 edge {0:d}: ", @@ -128,16 +144,6 @@ private: using ELFT = ELFType; using Base = ELFLinkGraphBuilder; - bool excludeSection(const typename ELFT::Shdr &Sect) const override { - // TODO: An .ARM.exidx (Exception Index table) entry is 8-bytes in size and - // consists of 2 words. It might be sufficient to process only relocations - // in the the second word (offset 4). Please find more details in: Exception - // Handling ABI for the Arm® Architecture -> Index table entries - if (Sect.sh_type == ELF::SHT_ARM_EXIDX) - return true; - return false; - } - Error addRelocations() override { LLVM_DEBUG(dbgs() << "Processing relocations:\n"); using Self = ELFLinkGraphBuilder_aarch32; @@ -167,7 +173,7 @@ private: inconvertibleErrorCode()); uint32_t Type = Rel.getType(false); - Expected Kind = getJITLinkEdgeKind(Type); + Expected Kind = getJITLinkEdgeKind(Type, ArmCfg); if (!Kind) return Kind.takeError(); @@ -216,12 +222,15 @@ public: ArmCfg(std::move(ArmCfg)) {} }; -template +template Error buildTables_ELF_aarch32(LinkGraph &G) { LLVM_DEBUG(dbgs() << "Visiting edges in graph:\n"); - aarch32::StubsManager PLT; - visitExistingEdges(G, PLT); + StubsManagerType StubsManager; + visitExistingEdges(G, StubsManager); + aarch32::GOTBuilder GOT; + visitExistingEdges(G, GOT); + return Error::success(); } @@ -250,21 +259,8 @@ createLinkGraphFromELFObject_aarch32(MemoryBufferRef ObjectBuffer) { // Resolve our internal configuration for the target. If at some point the // CPUArch alone becomes too unprecise, we can find more details in the // Tag_CPU_arch_profile. - aarch32::ArmConfig ArmCfg; - using namespace ARMBuildAttrs; - auto Arch = static_cast(ARM::getArchAttr(AK)); - switch (Arch) { - case v7: - case v8_A: - ArmCfg = aarch32::getArmConfigForCPUArch(Arch); - assert(ArmCfg.Stubs != aarch32::Unsupported && - "Provide a config for each supported CPU"); - break; - default: - return make_error( - "Failed to build ELF link graph: Unsupported CPU arch " + - StringRef(aarch32::getCPUArchName(Arch))); - } + auto Arch = static_cast(ARM::getArchAttr(AK)); + aarch32::ArmConfig ArmCfg = aarch32::getArmConfigForCPUArch(Arch); // Populate the link-graph. switch (TT.getArch()) { @@ -309,11 +305,15 @@ void link_ELF_aarch32(std::unique_ptr G, PassCfg.PrePrunePasses.push_back(markAllSymbolsLive); switch (ArmCfg.Stubs) { - case aarch32::Thumbv7: + case aarch32::StubsFlavor::pre_v7: PassCfg.PostPrunePasses.push_back( - buildTables_ELF_aarch32); + buildTables_ELF_aarch32); break; - case aarch32::Unsupported: + case aarch32::StubsFlavor::v7: + PassCfg.PostPrunePasses.push_back( + buildTables_ELF_aarch32); + break; + case aarch32::StubsFlavor::Undefined: llvm_unreachable("Check before building graph"); } } diff --git a/llvm/lib/ExecutionEngine/JITLink/aarch32.cpp b/llvm/lib/ExecutionEngine/JITLink/aarch32.cpp index 671ee1a8125..00be2f57d06 100644 --- a/llvm/lib/ExecutionEngine/JITLink/aarch32.cpp +++ b/llvm/lib/ExecutionEngine/JITLink/aarch32.cpp @@ -15,6 +15,7 @@ #include "llvm/ADT/StringExtras.h" #include "llvm/BinaryFormat/ELF.h" #include "llvm/ExecutionEngine/JITLink/JITLink.h" +#include "llvm/ExecutionEngine/Orc/Shared/MemoryFlags.h" #include "llvm/Object/ELFObjectFile.h" #include "llvm/Support/Endian.h" #include "llvm/Support/ManagedStatic.h" @@ -395,7 +396,10 @@ Expected readAddendData(LinkGraph &G, Block &B, Edge::OffsetT Offset, switch (Kind) { case Data_Delta32: case Data_Pointer32: + case Data_RequestGOTAndTransformToDelta32: return SignExtend64<32>(support::endian::read32(FixupPtr, Endian)); + case Data_PRel31: + return SignExtend64<31>(support::endian::read32(FixupPtr, Endian)); default: return make_error( "In graph " + G.getName() + ", section " + B.getSection().getName() + @@ -464,39 +468,50 @@ Error applyFixupData(LinkGraph &G, Block &B, const Edge &E) { char *BlockWorkingMem = B.getAlreadyMutableContent().data(); char *FixupPtr = BlockWorkingMem + E.getOffset(); - auto Write32 = [FixupPtr, Endian = G.getEndianness()](int64_t Value) { - assert(isInt<32>(Value) && "Must be in signed 32-bit range"); - uint32_t Imm = static_cast(Value); - if (LLVM_LIKELY(Endian == endianness::little)) - endian::write32(FixupPtr, Imm); - else - endian::write32(FixupPtr, Imm); - }; - Edge::Kind Kind = E.getKind(); uint64_t FixupAddress = (B.getAddress() + E.getOffset()).getValue(); int64_t Addend = E.getAddend(); Symbol &TargetSymbol = E.getTarget(); uint64_t TargetAddress = TargetSymbol.getAddress().getValue(); - // Regular data relocations have size 4, alignment 1 and write the full 32-bit - // result to the place; no need for overflow checking. There are three - // exceptions: R_ARM_ABS8, R_ARM_ABS16, R_ARM_PREL31 + // Data relocations have alignment 1, size 4 (except R_ARM_ABS8 and + // R_ARM_ABS16) and write the full 32-bit result (except R_ARM_PREL31). switch (Kind) { case Data_Delta32: { int64_t Value = TargetAddress - FixupAddress + Addend; if (!isInt<32>(Value)) return makeTargetOutOfRangeError(G, B, E); - Write32(Value); + if (LLVM_LIKELY(G.getEndianness() == endianness::little)) + endian::write32le(FixupPtr, Value); + else + endian::write32be(FixupPtr, Value); return Error::success(); } case Data_Pointer32: { int64_t Value = TargetAddress + Addend; - if (!isInt<32>(Value)) + if (!isUInt<32>(Value)) return makeTargetOutOfRangeError(G, B, E); - Write32(Value); + if (LLVM_LIKELY(G.getEndianness() == endianness::little)) + endian::write32le(FixupPtr, Value); + else + endian::write32be(FixupPtr, Value); return Error::success(); } + case Data_PRel31: { + int64_t Value = TargetAddress - FixupAddress + Addend; + if (!isInt<31>(Value)) + return makeTargetOutOfRangeError(G, B, E); + if (LLVM_LIKELY(G.getEndianness() == endianness::little)) { + uint32_t MSB = endian::read32le(FixupPtr) & 0x80000000; + endian::write32le(FixupPtr, MSB | (Value & ~0x80000000)); + } else { + uint32_t MSB = endian::read32be(FixupPtr) & 0x80000000; + endian::write32be(FixupPtr, MSB | (Value & ~0x80000000)); + } + return Error::success(); + } + case Data_RequestGOTAndTransformToDelta32: + llvm_unreachable("Should be transformed"); default: return make_error( "In graph " + G.getName() + ", section " + B.getSection().getName() + @@ -678,28 +693,240 @@ Error applyFixupThumb(LinkGraph &G, Block &B, const Edge &E, } } +const uint8_t GOTEntryInit[] = { + 0x00, + 0x00, + 0x00, + 0x00, +}; + +/// Create a new node in the link-graph for the given pointer value. +template +static Block &allocPointer(LinkGraph &G, Section &S, + const uint8_t (&Content)[Size]) { + static_assert(Size == 4, "Pointers are 32-bit"); + constexpr uint64_t Alignment = 4; + ArrayRef Init(reinterpret_cast(Content), Size); + return G.createContentBlock(S, Init, orc::ExecutorAddr(), Alignment, 0); +} + +Symbol &GOTBuilder::createEntry(LinkGraph &G, Symbol &Target) { + if (!GOTSection) + GOTSection = &G.createSection(getSectionName(), orc::MemProt::Read); + Block &B = allocPointer(G, *GOTSection, GOTEntryInit); + constexpr int64_t GOTEntryAddend = 0; + B.addEdge(Data_Pointer32, 0, Target, GOTEntryAddend); + return G.addAnonymousSymbol(B, 0, B.getSize(), false, false); +} + +bool GOTBuilder::visitEdge(LinkGraph &G, Block *B, Edge &E) { + Edge::Kind KindToSet = Edge::Invalid; + switch (E.getKind()) { + case aarch32::Data_RequestGOTAndTransformToDelta32: { + KindToSet = aarch32::Data_Delta32; + break; + } + default: + return false; + } + LLVM_DEBUG(dbgs() << " Transforming " << G.getEdgeKindName(E.getKind()) + << " edge at " << B->getFixupAddress(E) << " (" + << B->getAddress() << " + " + << formatv("{0:x}", E.getOffset()) << ") into " + << G.getEdgeKindName(KindToSet) << "\n"); + E.setKind(KindToSet); + E.setTarget(getEntryForTarget(G, E.getTarget())); + return true; +} + +const uint8_t ArmThumbv5LdrPc[] = { + 0x78, 0x47, // bx pc + 0xfd, 0xe7, // b #-6 ; Arm recommended sequence to follow bx pc + 0x04, 0xf0, 0x1f, 0xe5, // ldr pc, [pc,#-4] ; L1 + 0x00, 0x00, 0x00, 0x00, // L1: .word S +}; + +const uint8_t Armv7ABS[] = { + 0x00, 0xc0, 0x00, 0xe3, // movw r12, #0x0000 ; lower 16-bit + 0x00, 0xc0, 0x40, 0xe3, // movt r12, #0x0000 ; upper 16-bit + 0x1c, 0xff, 0x2f, 0xe1 // bx r12 +}; + const uint8_t Thumbv7ABS[] = { 0x40, 0xf2, 0x00, 0x0c, // movw r12, #0x0000 ; lower 16-bit 0xc0, 0xf2, 0x00, 0x0c, // movt r12, #0x0000 ; upper 16-bit 0x60, 0x47 // bx r12 }; -template <> -Symbol &StubsManager::createEntry(LinkGraph &G, Symbol &Target) { +/// Create a new node in the link-graph for the given stub template. +template +static Block &allocStub(LinkGraph &G, Section &S, const uint8_t (&Code)[Size]) { constexpr uint64_t Alignment = 4; - Block &B = addStub(G, Thumbv7ABS, Alignment); - LLVM_DEBUG({ - const char *StubPtr = B.getContent().data(); - HalfWords Reg12 = encodeRegMovtT1MovwT3(12); - assert(checkRegister(StubPtr, Reg12) && - checkRegister(StubPtr + 4, Reg12) && - "Linker generated stubs may only corrupt register r12 (IP)"); - }); + ArrayRef Template(reinterpret_cast(Code), Size); + return G.createContentBlock(S, Template, orc::ExecutorAddr(), Alignment, 0); +} + +static Block &createStubPrev7(LinkGraph &G, Section &S, Symbol &Target) { + Block &B = allocStub(G, S, ArmThumbv5LdrPc); + B.addEdge(Data_Pointer32, 8, Target, 0); + return B; +} + +static Block &createStubThumbv7(LinkGraph &G, Section &S, Symbol &Target) { + Block &B = allocStub(G, S, Thumbv7ABS); B.addEdge(Thumb_MovwAbsNC, 0, Target, 0); B.addEdge(Thumb_MovtAbs, 4, Target, 0); - Symbol &Stub = G.addAnonymousSymbol(B, 0, B.getSize(), true, false); - Stub.setTargetFlags(ThumbSymbol); - return Stub; + + [[maybe_unused]] const char *StubPtr = B.getContent().data(); + [[maybe_unused]] HalfWords Reg12 = encodeRegMovtT1MovwT3(12); + assert(checkRegister(StubPtr, Reg12) && + checkRegister(StubPtr + 4, Reg12) && + "Linker generated stubs may only corrupt register r12 (IP)"); + return B; +} + +static Block &createStubArmv7(LinkGraph &G, Section &S, Symbol &Target) { + Block &B = allocStub(G, S, Armv7ABS); + B.addEdge(Arm_MovwAbsNC, 0, Target, 0); + B.addEdge(Arm_MovtAbs, 4, Target, 0); + + [[maybe_unused]] const char *StubPtr = B.getContent().data(); + [[maybe_unused]] uint32_t Reg12 = encodeRegMovtA1MovwA2(12); + assert(checkRegister(StubPtr, Reg12) && + checkRegister(StubPtr + 4, Reg12) && + "Linker generated stubs may only corrupt register r12 (IP)"); + return B; +} + +static bool needsStub(const Edge &E) { + Symbol &Target = E.getTarget(); + + // Create stubs for external branch targets. + if (!Target.isDefined()) { + switch (E.getKind()) { + case Arm_Call: + case Arm_Jump24: + case Thumb_Call: + case Thumb_Jump24: + return true; + default: + return false; + } + } + + // For local targets, create interworking stubs if we switch Arm/Thumb with an + // instruction that cannot switch the instruction set state natively. + bool TargetIsThumb = Target.getTargetFlags() & ThumbSymbol; + switch (E.getKind()) { + case Arm_Jump24: + return TargetIsThumb; // Branch to Thumb needs interworking stub + case Thumb_Jump24: + return !TargetIsThumb; // Branch to Arm needs interworking stub + default: + break; + } + + return false; +} + +// The ArmThumbv5LdrPc stub has 2 entrypoints: Thumb at offset 0 is taken only +// for Thumb B instructions. Thumb BL is rewritten to BLX and takes the Arm +// entrypoint at offset 4. Arm branches always use that one. +Symbol *StubsManager_prev7::getOrCreateSlotEntrypoint(LinkGraph &G, + StubMapEntry &Slot, + bool Thumb) { + constexpr orc::ExecutorAddrDiff ThumbEntrypointOffset = 0; + constexpr orc::ExecutorAddrDiff ArmEntrypointOffset = 4; + if (Thumb && !Slot.ThumbEntry) { + Slot.ThumbEntry = + &G.addAnonymousSymbol(*Slot.B, ThumbEntrypointOffset, 4, true, false); + Slot.ThumbEntry->setTargetFlags(ThumbSymbol); + } + if (!Thumb && !Slot.ArmEntry) + Slot.ArmEntry = + &G.addAnonymousSymbol(*Slot.B, ArmEntrypointOffset, 8, true, false); + return Thumb ? Slot.ThumbEntry : Slot.ArmEntry; +} + +bool StubsManager_prev7::visitEdge(LinkGraph &G, Block *B, Edge &E) { + if (!needsStub(E)) + return false; + + Symbol &Target = E.getTarget(); + assert(Target.hasName() && "Edge cannot point to anonymous target"); + auto [Slot, NewStub] = getStubMapSlot(Target.getName()); + + if (NewStub) { + if (!StubsSection) + StubsSection = &G.createSection(getSectionName(), + orc::MemProt::Read | orc::MemProt::Exec); + LLVM_DEBUG({ + dbgs() << " Created stub entry for " << Target.getName() << " in " + << StubsSection->getName() << "\n"; + }); + Slot->B = &createStubPrev7(G, *StubsSection, Target); + } + + // The ArmThumbv5LdrPc stub has 2 entrypoints: Thumb at offset 0 is taken only + // for Thumb B instructions. Thumb BL is rewritten to BLX and takes the Arm + // entrypoint at offset 4. Arm branches always use that one. + bool UseThumb = E.getKind() == Thumb_Jump24; + Symbol *StubEntrypoint = getOrCreateSlotEntrypoint(G, *Slot, UseThumb); + + LLVM_DEBUG({ + dbgs() << " Using " << (UseThumb ? "Thumb" : "Arm") << " entrypoint " + << *StubEntrypoint << " in " + << StubEntrypoint->getBlock().getSection().getName() << "\n"; + }); + + E.setTarget(*StubEntrypoint); + return true; +} + +bool StubsManager_v7::visitEdge(LinkGraph &G, Block *B, Edge &E) { + if (!needsStub(E)) + return false; + + // Stub Arm/Thumb follows instruction set state at relocation site. + // TODO: We may reduce them at relaxation time and reuse freed slots. + bool MakeThumb = (E.getKind() > LastArmRelocation); + LLVM_DEBUG(dbgs() << " Preparing " << (MakeThumb ? "Thumb" : "Arm") + << " stub for " << G.getEdgeKindName(E.getKind()) + << " edge at " << B->getFixupAddress(E) << " (" + << B->getAddress() << " + " + << formatv("{0:x}", E.getOffset()) << ")\n"); + + Symbol &Target = E.getTarget(); + assert(Target.hasName() && "Edge cannot point to anonymous target"); + Symbol *&StubSymbol = getStubSymbolSlot(Target.getName(), MakeThumb); + + if (!StubSymbol) { + if (!StubsSection) + StubsSection = &G.createSection(getSectionName(), + orc::MemProt::Read | orc::MemProt::Exec); + Block &B = MakeThumb ? createStubThumbv7(G, *StubsSection, Target) + : createStubArmv7(G, *StubsSection, Target); + StubSymbol = &G.addAnonymousSymbol(B, 0, B.getSize(), true, false); + if (MakeThumb) + StubSymbol->setTargetFlags(ThumbSymbol); + + LLVM_DEBUG({ + dbgs() << " Created " << (MakeThumb ? "Thumb" : "Arm") << " entry for " + << Target.getName() << " in " << StubsSection->getName() << ": " + << *StubSymbol << "\n"; + }); + } + + assert(MakeThumb == (StubSymbol->getTargetFlags() & ThumbSymbol) && + "Instruction set states of stub and relocation site should be equal"); + LLVM_DEBUG({ + dbgs() << " Using " << (MakeThumb ? "Thumb" : "Arm") << " entry " + << *StubSymbol << " in " + << StubSymbol->getBlock().getSection().getName() << "\n"; + }); + + E.setTarget(*StubSymbol); + return true; } const char *getEdgeKindName(Edge::Kind K) { @@ -710,6 +937,8 @@ const char *getEdgeKindName(Edge::Kind K) { switch (K) { KIND_NAME_CASE(Data_Delta32) KIND_NAME_CASE(Data_Pointer32) + KIND_NAME_CASE(Data_PRel31) + KIND_NAME_CASE(Data_RequestGOTAndTransformToDelta32) KIND_NAME_CASE(Arm_Call) KIND_NAME_CASE(Arm_Jump24) KIND_NAME_CASE(Arm_MovwAbsNC) @@ -720,6 +949,7 @@ const char *getEdgeKindName(Edge::Kind K) { KIND_NAME_CASE(Thumb_MovtAbs) KIND_NAME_CASE(Thumb_MovwPrelNC) KIND_NAME_CASE(Thumb_MovtPrel) + KIND_NAME_CASE(None) default: return getGenericEdgeKindName(K); } diff --git a/llvm/lib/ExecutionEngine/Orc/LLJIT.cpp b/llvm/lib/ExecutionEngine/Orc/LLJIT.cpp index e259c393d07..833dcb9d5bf 100644 --- a/llvm/lib/ExecutionEngine/Orc/LLJIT.cpp +++ b/llvm/lib/ExecutionEngine/Orc/LLJIT.cpp @@ -734,6 +734,12 @@ Error LLJITBuilderState::prepareForConstruction() { case Triple::aarch64: UseJITLink = !TT.isOSBinFormatCOFF(); break; + case Triple::arm: + case Triple::armeb: + case Triple::thumb: + case Triple::thumbeb: + UseJITLink = TT.isOSBinFormatELF(); + break; case Triple::x86_64: UseJITLink = !TT.isOSBinFormatCOFF(); break; diff --git a/llvm/lib/ExecutionEngine/Orc/MachOPlatform.cpp b/llvm/lib/ExecutionEngine/Orc/MachOPlatform.cpp index 6c17f14aa4c..377a31e63ec 100644 --- a/llvm/lib/ExecutionEngine/Orc/MachOPlatform.cpp +++ b/llvm/lib/ExecutionEngine/Orc/MachOPlatform.cpp @@ -255,12 +255,11 @@ struct ObjCImageInfoFlags { namespace llvm { namespace orc { -Expected> -MachOPlatform::Create(ExecutionSession &ES, ObjectLinkingLayer &ObjLinkingLayer, - JITDylib &PlatformJD, - std::unique_ptr OrcRuntime, - MachOHeaderMUBuilder BuildMachOHeaderMU, - std::optional RuntimeAliases) { +Expected> MachOPlatform::Create( + ExecutionSession &ES, ObjectLinkingLayer &ObjLinkingLayer, + JITDylib &PlatformJD, std::unique_ptr OrcRuntime, + HeaderOptions PlatformJDOpts, MachOHeaderMUBuilder BuildMachOHeaderMU, + std::optional RuntimeAliases) { // If the target is not supported then bail out immediately. if (!supportedTarget(ES.getTargetTriple())) @@ -290,9 +289,9 @@ MachOPlatform::Create(ExecutionSession &ES, ObjectLinkingLayer &ObjLinkingLayer, // Create the instance. Error Err = Error::success(); - auto P = std::unique_ptr( - new MachOPlatform(ES, ObjLinkingLayer, PlatformJD, std::move(OrcRuntime), - std::move(BuildMachOHeaderMU), Err)); + auto P = std::unique_ptr(new MachOPlatform( + ES, ObjLinkingLayer, PlatformJD, std::move(OrcRuntime), + std::move(PlatformJDOpts), std::move(BuildMachOHeaderMU), Err)); if (Err) return std::move(Err); return std::move(P); @@ -301,6 +300,7 @@ MachOPlatform::Create(ExecutionSession &ES, ObjectLinkingLayer &ObjLinkingLayer, Expected> MachOPlatform::Create(ExecutionSession &ES, ObjectLinkingLayer &ObjLinkingLayer, JITDylib &PlatformJD, const char *OrcRuntimePath, + HeaderOptions PlatformJDOpts, MachOHeaderMUBuilder BuildMachOHeaderMU, std::optional RuntimeAliases) { @@ -312,11 +312,16 @@ MachOPlatform::Create(ExecutionSession &ES, ObjectLinkingLayer &ObjLinkingLayer, return Create(ES, ObjLinkingLayer, PlatformJD, std::move(*OrcRuntimeArchiveGenerator), - std::move(BuildMachOHeaderMU), std::move(RuntimeAliases)); + std::move(PlatformJDOpts), std::move(BuildMachOHeaderMU), + std::move(RuntimeAliases)); } Error MachOPlatform::setupJITDylib(JITDylib &JD) { - if (auto Err = JD.define(BuildMachOHeaderMU(*this))) + return setupJITDylib(JD, /*Opts=*/{}); +} + +Error MachOPlatform::setupJITDylib(JITDylib &JD, HeaderOptions Opts) { + if (auto Err = JD.define(BuildMachOHeaderMU(*this, std::move(Opts)))) return Err; return ES.lookup({&JD}, MachOHeaderStartSymbol).takeError(); @@ -432,7 +437,8 @@ MachOPlatform::MachOPlatform( ExecutionSession &ES, ObjectLinkingLayer &ObjLinkingLayer, JITDylib &PlatformJD, std::unique_ptr OrcRuntimeGenerator, - MachOHeaderMUBuilder BuildMachOHeaderMU, Error &Err) + HeaderOptions PlatformJDOpts, MachOHeaderMUBuilder BuildMachOHeaderMU, + Error &Err) : ES(ES), PlatformJD(PlatformJD), ObjLinkingLayer(ObjLinkingLayer), BuildMachOHeaderMU(std::move(BuildMachOHeaderMU)) { ErrorAsOutParameter _(&Err); @@ -497,7 +503,8 @@ MachOPlatform::MachOPlatform( // the support methods callable. The bootstrap is now complete. // Step (1) Add header materialization unit and request. - if ((Err = PlatformJD.define(this->BuildMachOHeaderMU(*this)))) + if ((Err = PlatformJD.define( + this->BuildMachOHeaderMU(*this, std::move(PlatformJDOpts))))) return; if ((Err = ES.lookup(&PlatformJD, MachOHeaderStartSymbol).takeError())) return; @@ -1669,9 +1676,10 @@ Error MachOPlatform::MachOPlatformPlugin::addSymbolTableRegistration( } template -jitlink::Block &createTrivialHeaderBlock(MachOPlatform &MOP, - jitlink::LinkGraph &G, - jitlink::Section &HeaderSection) { +jitlink::Block &createHeaderBlock(MachOPlatform &MOP, + const MachOPlatform::HeaderOptions &Opts, + JITDylib &JD, jitlink::LinkGraph &G, + jitlink::Section &HeaderSection) { auto HdrInfo = getMachOHeaderInfoFromTriple(MOP.getExecutionSession().getTargetTriple()); MachOBuilder B(HdrInfo.PageSize); @@ -1680,6 +1688,19 @@ jitlink::Block &createTrivialHeaderBlock(MachOPlatform &MOP, B.Header.cputype = HdrInfo.CPUType; B.Header.cpusubtype = HdrInfo.CPUSubType; + if (Opts.IDDylib) + B.template addLoadCommand( + Opts.IDDylib->Name, Opts.IDDylib->Timestamp, + Opts.IDDylib->CurrentVersion, Opts.IDDylib->CompatibilityVersion); + else + B.template addLoadCommand(JD.getName(), 0, 0, 0); + + for (auto &D : Opts.LoadDylibs) + B.template addLoadCommand( + D.Name, D.Timestamp, D.CurrentVersion, D.CompatibilityVersion); + for (auto &P : Opts.RPaths) + B.template addLoadCommand(P); + auto HeaderContent = G.allocateBuffer(B.layout()); B.write(HeaderContent); @@ -1688,10 +1709,11 @@ jitlink::Block &createTrivialHeaderBlock(MachOPlatform &MOP, } SimpleMachOHeaderMU::SimpleMachOHeaderMU(MachOPlatform &MOP, - SymbolStringPtr HeaderStartSymbol) + SymbolStringPtr HeaderStartSymbol, + MachOPlatform::HeaderOptions Opts) : MaterializationUnit( createHeaderInterface(MOP, std::move(HeaderStartSymbol))), - MOP(MOP) {} + MOP(MOP), Opts(std::move(Opts)) {} void SimpleMachOHeaderMU::materialize( std::unique_ptr R) { @@ -1725,7 +1747,7 @@ SimpleMachOHeaderMU::createHeaderBlock(JITDylib &JD, jitlink::LinkGraph &G, switch (MOP.getExecutionSession().getTargetTriple().getArch()) { case Triple::aarch64: case Triple::x86_64: - return createTrivialHeaderBlock(MOP, G, HeaderSection); + return ::createHeaderBlock(MOP, Opts, JD, G, HeaderSection); default: llvm_unreachable("Unsupported architecture"); } diff --git a/llvm/lib/ExecutionEngine/Orc/TargetProcess/JITLoaderPerf.cpp b/llvm/lib/ExecutionEngine/Orc/TargetProcess/JITLoaderPerf.cpp index 5e0623102d3..f7852b0ca62 100644 --- a/llvm/lib/ExecutionEngine/Orc/TargetProcess/JITLoaderPerf.cpp +++ b/llvm/lib/ExecutionEngine/Orc/TargetProcess/JITLoaderPerf.cpp @@ -323,7 +323,7 @@ static Error InitDebuggingDir(PerfState &State) { return make_error(std::move(ErrStr), inconvertibleErrorCode()); } - State.JitPath = std::string(UniqueDebugDir.str()); + State.JitPath = std::string(UniqueDebugDir); return Error::success(); } diff --git a/llvm/lib/ExecutionEngine/RuntimeDyld/RuntimeDyldChecker.cpp b/llvm/lib/ExecutionEngine/RuntimeDyld/RuntimeDyldChecker.cpp index 7fadbdd6a1f..11fb21a9c1c 100644 --- a/llvm/lib/ExecutionEngine/RuntimeDyld/RuntimeDyldChecker.cpp +++ b/llvm/lib/ExecutionEngine/RuntimeDyld/RuntimeDyldChecker.cpp @@ -400,6 +400,15 @@ private: StringRef Symbol; std::tie(Symbol, RemainingExpr) = parseSymbol(RemainingExpr); + // Parse optional parameter to filter by stub kind + StringRef KindNameFilter; + if (RemainingExpr.starts_with(",")) { + RemainingExpr = RemainingExpr.substr(1).ltrim(); + size_t ClosingBracket = RemainingExpr.find(")"); + KindNameFilter = RemainingExpr.substr(0, ClosingBracket); + RemainingExpr = RemainingExpr.substr(ClosingBracket); + } + if (!RemainingExpr.starts_with(")")) return std::make_pair( unexpectedToken(RemainingExpr, Expr, "expected ')'"), ""); @@ -407,8 +416,9 @@ private: uint64_t StubAddr; std::string ErrorMsg; - std::tie(StubAddr, ErrorMsg) = Checker.getStubOrGOTAddrFor( - StubContainerName, Symbol, PCtx.IsInsideLoad, IsStubAddr); + std::tie(StubAddr, ErrorMsg) = + Checker.getStubOrGOTAddrFor(StubContainerName, Symbol, KindNameFilter, + PCtx.IsInsideLoad, IsStubAddr); if (ErrorMsg != "") return std::make_pair(EvalResult(ErrorMsg), ""); @@ -985,11 +995,14 @@ std::pair RuntimeDyldCheckerImpl::getSectionAddr( } std::pair RuntimeDyldCheckerImpl::getStubOrGOTAddrFor( - StringRef StubContainerName, StringRef SymbolName, bool IsInsideLoad, - bool IsStubAddr) const { + StringRef StubContainerName, StringRef SymbolName, StringRef StubKindFilter, + bool IsInsideLoad, bool IsStubAddr) const { - auto StubInfo = IsStubAddr ? GetStubInfo(StubContainerName, SymbolName) - : GetGOTInfo(StubContainerName, SymbolName); + assert((StubKindFilter.empty() || IsStubAddr) && + "Kind name filter only supported for stubs"); + auto StubInfo = + IsStubAddr ? GetStubInfo(StubContainerName, SymbolName, StubKindFilter) + : GetGOTInfo(StubContainerName, SymbolName); if (!StubInfo) { std::string ErrMsg; diff --git a/llvm/lib/ExecutionEngine/RuntimeDyld/RuntimeDyldCheckerImpl.h b/llvm/lib/ExecutionEngine/RuntimeDyld/RuntimeDyldCheckerImpl.h index 9f44a9389f4..bda554e9e5b 100644 --- a/llvm/lib/ExecutionEngine/RuntimeDyld/RuntimeDyldCheckerImpl.h +++ b/llvm/lib/ExecutionEngine/RuntimeDyld/RuntimeDyldCheckerImpl.h @@ -64,7 +64,8 @@ private: std::pair getStubOrGOTAddrFor(StringRef StubContainerName, StringRef Symbol, - bool IsInsideLoad, bool IsStubAddr) const; + StringRef StubKindFilter, bool IsInsideLoad, + bool IsStubAddr) const; std::optional getSectionLoadAddress(void *LocalAddr) const; diff --git a/llvm/lib/FileCheck/FileCheck.cpp b/llvm/lib/FileCheck/FileCheck.cpp index b728c14d288..0d5bdf7903a 100644 --- a/llvm/lib/FileCheck/FileCheck.cpp +++ b/llvm/lib/FileCheck/FileCheck.cpp @@ -1784,7 +1784,7 @@ bool FileCheck::readCheckFile( PatternContext->createLineVariable(); - std::vector ImplicitNegativeChecks; + std::vector ImplicitNegativeChecks; for (StringRef PatternString : Req.ImplicitCheckNot) { // Create a buffer with fake command line content in order to display the // command line option responsible for the specific implicit CHECK-NOT. @@ -1807,14 +1807,15 @@ bool FileCheck::readCheckFile( } } - ImplicitNegativeChecks.push_back( - Pattern(Check::CheckNot, PatternContext.get())); - ImplicitNegativeChecks.back().parsePattern(PatternInBuffer, - "IMPLICIT-CHECK", SM, Req); + ImplicitNegativeChecks.emplace_back( + Pattern(Check::CheckNot, PatternContext.get()), + StringRef("IMPLICIT-CHECK")); + ImplicitNegativeChecks.back().DagNotPat.parsePattern( + PatternInBuffer, "IMPLICIT-CHECK", SM, Req); } - std::vector DagNotMatches = ImplicitNegativeChecks; - + std::vector DagNotMatches = + ImplicitNegativeChecks; // LineNumber keeps track of the line on which CheckPrefix instances are // found. unsigned LineNumber = 1; @@ -1926,7 +1927,7 @@ bool FileCheck::readCheckFile( // Handle CHECK-DAG/-NOT. if (CheckTy == Check::CheckDAG || CheckTy == Check::CheckNot) { - DagNotMatches.push_back(P); + DagNotMatches.emplace_back(P, UsedPrefix); continue; } @@ -2165,7 +2166,7 @@ size_t FileCheckString::Check(const SourceMgr &SM, StringRef Buffer, FileCheckRequest &Req, std::vector *Diags) const { size_t LastPos = 0; - std::vector NotStrings; + std::vector NotStrings; // IsLabelScanMode is true when we are scanning forward to find CHECK-LABEL // bounds; we have not processed variable definitions within the bounded block @@ -2302,17 +2303,19 @@ bool FileCheckString::CheckSame(const SourceMgr &SM, StringRef Buffer) const { return false; } -bool FileCheckString::CheckNot(const SourceMgr &SM, StringRef Buffer, - const std::vector &NotStrings, - const FileCheckRequest &Req, - std::vector *Diags) const { +bool FileCheckString::CheckNot( + const SourceMgr &SM, StringRef Buffer, + const std::vector &NotStrings, + const FileCheckRequest &Req, std::vector *Diags) const { bool DirectiveFail = false; - for (const Pattern *Pat : NotStrings) { - assert((Pat->getCheckTy() == Check::CheckNot) && "Expect CHECK-NOT!"); - Pattern::MatchResult MatchResult = Pat->match(Buffer, SM); - if (Error Err = reportMatchResult(/*ExpectedMatch=*/false, SM, Prefix, - Pat->getLoc(), *Pat, 1, Buffer, - std::move(MatchResult), Req, Diags)) { + for (auto NotInfo : NotStrings) { + assert((NotInfo->DagNotPat.getCheckTy() == Check::CheckNot) && + "Expect CHECK-NOT!"); + Pattern::MatchResult MatchResult = NotInfo->DagNotPat.match(Buffer, SM); + if (Error Err = reportMatchResult( + /*ExpectedMatch=*/false, SM, NotInfo->DagNotPrefix, + NotInfo->DagNotPat.getLoc(), NotInfo->DagNotPat, 1, Buffer, + std::move(MatchResult), Req, Diags)) { cantFail(handleErrors(std::move(Err), [&](const ErrorReported &E) {})); DirectiveFail = true; continue; @@ -2321,10 +2324,11 @@ bool FileCheckString::CheckNot(const SourceMgr &SM, StringRef Buffer, return DirectiveFail; } -size_t FileCheckString::CheckDag(const SourceMgr &SM, StringRef Buffer, - std::vector &NotStrings, - const FileCheckRequest &Req, - std::vector *Diags) const { +size_t +FileCheckString::CheckDag(const SourceMgr &SM, StringRef Buffer, + std::vector &NotStrings, + const FileCheckRequest &Req, + std::vector *Diags) const { if (DagNotStrings.empty()) return 0; @@ -2344,13 +2348,14 @@ size_t FileCheckString::CheckDag(const SourceMgr &SM, StringRef Buffer, // group, so we don't use a range-based for loop here. for (auto PatItr = DagNotStrings.begin(), PatEnd = DagNotStrings.end(); PatItr != PatEnd; ++PatItr) { - const Pattern &Pat = *PatItr; + const Pattern &Pat = PatItr->DagNotPat; + const StringRef DNPrefix = PatItr->DagNotPrefix; assert((Pat.getCheckTy() == Check::CheckDAG || Pat.getCheckTy() == Check::CheckNot) && "Invalid CHECK-DAG or CHECK-NOT!"); if (Pat.getCheckTy() == Check::CheckNot) { - NotStrings.push_back(&Pat); + NotStrings.push_back(&*PatItr); continue; } @@ -2367,7 +2372,7 @@ size_t FileCheckString::CheckDag(const SourceMgr &SM, StringRef Buffer, // With a group of CHECK-DAGs, a single mismatching means the match on // that group of CHECK-DAGs fails immediately. if (MatchResult.TheError || Req.VerboseVerbose) { - if (Error Err = reportMatchResult(/*ExpectedMatch=*/true, SM, Prefix, + if (Error Err = reportMatchResult(/*ExpectedMatch=*/true, SM, DNPrefix, Pat.getLoc(), Pat, 1, MatchBuffer, std::move(MatchResult), Req, Diags)) { cantFail( @@ -2430,13 +2435,13 @@ size_t FileCheckString::CheckDag(const SourceMgr &SM, StringRef Buffer, } if (!Req.VerboseVerbose) cantFail(printMatch( - /*ExpectedMatch=*/true, SM, Prefix, Pat.getLoc(), Pat, 1, Buffer, + /*ExpectedMatch=*/true, SM, DNPrefix, Pat.getLoc(), Pat, 1, Buffer, Pattern::MatchResult(MatchPos, MatchLen, Error::success()), Req, Diags)); // Handle the end of a CHECK-DAG group. if (std::next(PatItr) == PatEnd || - std::next(PatItr)->getCheckTy() == Check::CheckNot) { + std::next(PatItr)->DagNotPat.getCheckTy() == Check::CheckNot) { if (!NotStrings.empty()) { // If there are CHECK-NOTs between two CHECK-DAGs or from CHECK to // CHECK-DAG, verify that there are no 'not' strings occurred in that diff --git a/llvm/lib/FileCheck/FileCheckImpl.h b/llvm/lib/FileCheck/FileCheckImpl.h index c15461684ea..c772eddd8ec 100644 --- a/llvm/lib/FileCheck/FileCheckImpl.h +++ b/llvm/lib/FileCheck/FileCheckImpl.h @@ -823,9 +823,19 @@ struct FileCheckString { /// The location in the match file that the check string was specified. SMLoc Loc; - /// All of the strings that are disallowed from occurring between this match - /// string and the previous one (or start of file). - std::vector DagNotStrings; + /// Hold the information about the DAG/NOT strings in the program, which are + /// not explicitly stored otherwise. This allows for better and more accurate + /// diagnostic messages. + struct DagNotPrefixInfo { + Pattern DagNotPat; + StringRef DagNotPrefix; + + DagNotPrefixInfo(const Pattern &P, StringRef S) + : DagNotPat(P), DagNotPrefix(S) {} + }; + + /// Hold the DAG/NOT strings occurring in the input file. + std::vector DagNotStrings; FileCheckString(const Pattern &P, StringRef S, SMLoc L) : Pat(P), Prefix(S), Loc(L) {} @@ -845,12 +855,12 @@ struct FileCheckString { /// \p Buffer. Errors are reported against \p SM and diagnostics recorded in /// \p Diags according to the verbosity level set in \p Req. bool CheckNot(const SourceMgr &SM, StringRef Buffer, - const std::vector &NotStrings, + const std::vector &NotStrings, const FileCheckRequest &Req, std::vector *Diags) const; /// Matches "dag strings" and their mixed "not strings". size_t CheckDag(const SourceMgr &SM, StringRef Buffer, - std::vector &NotStrings, + std::vector &NotStrings, const FileCheckRequest &Req, std::vector *Diags) const; }; diff --git a/llvm/lib/Frontend/Offloading/OffloadWrapper.cpp b/llvm/lib/Frontend/Offloading/OffloadWrapper.cpp new file mode 100644 index 00000000000..76a8eebdb36 --- /dev/null +++ b/llvm/lib/Frontend/Offloading/OffloadWrapper.cpp @@ -0,0 +1,620 @@ +//===- OffloadWrapper.cpp ---------------------------------------*- C++ -*-===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +#include "llvm/Frontend/Offloading/OffloadWrapper.h" +#include "llvm/ADT/ArrayRef.h" +#include "llvm/BinaryFormat/Magic.h" +#include "llvm/Frontend/Offloading/Utility.h" +#include "llvm/IR/Constants.h" +#include "llvm/IR/GlobalVariable.h" +#include "llvm/IR/IRBuilder.h" +#include "llvm/IR/LLVMContext.h" +#include "llvm/IR/Module.h" +#include "llvm/Object/OffloadBinary.h" +#include "llvm/Support/Error.h" +#include "llvm/TargetParser/Triple.h" +#include "llvm/Transforms/Utils/ModuleUtils.h" + +using namespace llvm; +using namespace llvm::offloading; + +namespace { +/// Magic number that begins the section containing the CUDA fatbinary. +constexpr unsigned CudaFatMagic = 0x466243b1; +constexpr unsigned HIPFatMagic = 0x48495046; + +IntegerType *getSizeTTy(Module &M) { + return M.getDataLayout().getIntPtrType(M.getContext()); +} + +// struct __tgt_device_image { +// void *ImageStart; +// void *ImageEnd; +// __tgt_offload_entry *EntriesBegin; +// __tgt_offload_entry *EntriesEnd; +// }; +StructType *getDeviceImageTy(Module &M) { + LLVMContext &C = M.getContext(); + StructType *ImageTy = StructType::getTypeByName(C, "__tgt_device_image"); + if (!ImageTy) + ImageTy = + StructType::create("__tgt_device_image", PointerType::getUnqual(C), + PointerType::getUnqual(C), PointerType::getUnqual(C), + PointerType::getUnqual(C)); + return ImageTy; +} + +PointerType *getDeviceImagePtrTy(Module &M) { + return PointerType::getUnqual(getDeviceImageTy(M)); +} + +// struct __tgt_bin_desc { +// int32_t NumDeviceImages; +// __tgt_device_image *DeviceImages; +// __tgt_offload_entry *HostEntriesBegin; +// __tgt_offload_entry *HostEntriesEnd; +// }; +StructType *getBinDescTy(Module &M) { + LLVMContext &C = M.getContext(); + StructType *DescTy = StructType::getTypeByName(C, "__tgt_bin_desc"); + if (!DescTy) + DescTy = StructType::create( + "__tgt_bin_desc", Type::getInt32Ty(C), getDeviceImagePtrTy(M), + PointerType::getUnqual(C), PointerType::getUnqual(C)); + return DescTy; +} + +PointerType *getBinDescPtrTy(Module &M) { + return PointerType::getUnqual(getBinDescTy(M)); +} + +/// Creates binary descriptor for the given device images. Binary descriptor +/// is an object that is passed to the offloading runtime at program startup +/// and it describes all device images available in the executable or shared +/// library. It is defined as follows +/// +/// __attribute__((visibility("hidden"))) +/// extern __tgt_offload_entry *__start_omp_offloading_entries; +/// __attribute__((visibility("hidden"))) +/// extern __tgt_offload_entry *__stop_omp_offloading_entries; +/// +/// static const char Image0[] = { }; +/// ... +/// static const char ImageN[] = { }; +/// +/// static const __tgt_device_image Images[] = { +/// { +/// Image0, /*ImageStart*/ +/// Image0 + sizeof(Image0), /*ImageEnd*/ +/// __start_omp_offloading_entries, /*EntriesBegin*/ +/// __stop_omp_offloading_entries /*EntriesEnd*/ +/// }, +/// ... +/// { +/// ImageN, /*ImageStart*/ +/// ImageN + sizeof(ImageN), /*ImageEnd*/ +/// __start_omp_offloading_entries, /*EntriesBegin*/ +/// __stop_omp_offloading_entries /*EntriesEnd*/ +/// } +/// }; +/// +/// static const __tgt_bin_desc BinDesc = { +/// sizeof(Images) / sizeof(Images[0]), /*NumDeviceImages*/ +/// Images, /*DeviceImages*/ +/// __start_omp_offloading_entries, /*HostEntriesBegin*/ +/// __stop_omp_offloading_entries /*HostEntriesEnd*/ +/// }; +/// +/// Global variable that represents BinDesc is returned. +GlobalVariable *createBinDesc(Module &M, ArrayRef> Bufs, + EntryArrayTy EntryArray, StringRef Suffix) { + LLVMContext &C = M.getContext(); + auto [EntriesB, EntriesE] = EntryArray; + + auto *Zero = ConstantInt::get(getSizeTTy(M), 0u); + Constant *ZeroZero[] = {Zero, Zero}; + + // Create initializer for the images array. + SmallVector ImagesInits; + ImagesInits.reserve(Bufs.size()); + for (ArrayRef Buf : Bufs) { + // We embed the full offloading entry so the binary utilities can parse it. + auto *Data = ConstantDataArray::get(C, Buf); + auto *Image = new GlobalVariable(M, Data->getType(), /*isConstant=*/true, + GlobalVariable::InternalLinkage, Data, + ".omp_offloading.device_image" + Suffix); + Image->setUnnamedAddr(GlobalValue::UnnamedAddr::Global); + Image->setSection(".llvm.offloading"); + Image->setAlignment(Align(object::OffloadBinary::getAlignment())); + + StringRef Binary(Buf.data(), Buf.size()); + assert(identify_magic(Binary) == file_magic::offload_binary && + "Invalid binary format"); + + // The device image struct contains the pointer to the beginning and end of + // the image stored inside of the offload binary. There should only be one + // of these for each buffer so we parse it out manually. + const auto *Header = + reinterpret_cast( + Binary.bytes_begin()); + const auto *Entry = reinterpret_cast( + Binary.bytes_begin() + Header->EntryOffset); + + auto *Begin = ConstantInt::get(getSizeTTy(M), Entry->ImageOffset); + auto *Size = + ConstantInt::get(getSizeTTy(M), Entry->ImageOffset + Entry->ImageSize); + Constant *ZeroBegin[] = {Zero, Begin}; + Constant *ZeroSize[] = {Zero, Size}; + + auto *ImageB = + ConstantExpr::getGetElementPtr(Image->getValueType(), Image, ZeroBegin); + auto *ImageE = + ConstantExpr::getGetElementPtr(Image->getValueType(), Image, ZeroSize); + + ImagesInits.push_back(ConstantStruct::get(getDeviceImageTy(M), ImageB, + ImageE, EntriesB, EntriesE)); + } + + // Then create images array. + auto *ImagesData = ConstantArray::get( + ArrayType::get(getDeviceImageTy(M), ImagesInits.size()), ImagesInits); + + auto *Images = + new GlobalVariable(M, ImagesData->getType(), /*isConstant*/ true, + GlobalValue::InternalLinkage, ImagesData, + ".omp_offloading.device_images" + Suffix); + Images->setUnnamedAddr(GlobalValue::UnnamedAddr::Global); + + auto *ImagesB = + ConstantExpr::getGetElementPtr(Images->getValueType(), Images, ZeroZero); + + // And finally create the binary descriptor object. + auto *DescInit = ConstantStruct::get( + getBinDescTy(M), + ConstantInt::get(Type::getInt32Ty(C), ImagesInits.size()), ImagesB, + EntriesB, EntriesE); + + return new GlobalVariable(M, DescInit->getType(), /*isConstant*/ true, + GlobalValue::InternalLinkage, DescInit, + ".omp_offloading.descriptor" + Suffix); +} + +void createRegisterFunction(Module &M, GlobalVariable *BinDesc, + StringRef Suffix) { + LLVMContext &C = M.getContext(); + auto *FuncTy = FunctionType::get(Type::getVoidTy(C), /*isVarArg*/ false); + auto *Func = Function::Create(FuncTy, GlobalValue::InternalLinkage, + ".omp_offloading.descriptor_reg" + Suffix, &M); + Func->setSection(".text.startup"); + + // Get __tgt_register_lib function declaration. + auto *RegFuncTy = FunctionType::get(Type::getVoidTy(C), getBinDescPtrTy(M), + /*isVarArg*/ false); + FunctionCallee RegFuncC = + M.getOrInsertFunction("__tgt_register_lib", RegFuncTy); + + // Construct function body + IRBuilder<> Builder(BasicBlock::Create(C, "entry", Func)); + Builder.CreateCall(RegFuncC, BinDesc); + Builder.CreateRetVoid(); + + // Add this function to constructors. + // Set priority to 1 so that __tgt_register_lib is executed AFTER + // __tgt_register_requires (we want to know what requirements have been + // asked for before we load a libomptarget plugin so that by the time the + // plugin is loaded it can report how many devices there are which can + // satisfy these requirements). + appendToGlobalCtors(M, Func, /*Priority*/ 1); +} + +void createUnregisterFunction(Module &M, GlobalVariable *BinDesc, + StringRef Suffix) { + LLVMContext &C = M.getContext(); + auto *FuncTy = FunctionType::get(Type::getVoidTy(C), /*isVarArg*/ false); + auto *Func = + Function::Create(FuncTy, GlobalValue::InternalLinkage, + ".omp_offloading.descriptor_unreg" + Suffix, &M); + Func->setSection(".text.startup"); + + // Get __tgt_unregister_lib function declaration. + auto *UnRegFuncTy = FunctionType::get(Type::getVoidTy(C), getBinDescPtrTy(M), + /*isVarArg*/ false); + FunctionCallee UnRegFuncC = + M.getOrInsertFunction("__tgt_unregister_lib", UnRegFuncTy); + + // Construct function body + IRBuilder<> Builder(BasicBlock::Create(C, "entry", Func)); + Builder.CreateCall(UnRegFuncC, BinDesc); + Builder.CreateRetVoid(); + + // Add this function to global destructors. + // Match priority of __tgt_register_lib + appendToGlobalDtors(M, Func, /*Priority*/ 1); +} + +// struct fatbin_wrapper { +// int32_t magic; +// int32_t version; +// void *image; +// void *reserved; +//}; +StructType *getFatbinWrapperTy(Module &M) { + LLVMContext &C = M.getContext(); + StructType *FatbinTy = StructType::getTypeByName(C, "fatbin_wrapper"); + if (!FatbinTy) + FatbinTy = StructType::create( + "fatbin_wrapper", Type::getInt32Ty(C), Type::getInt32Ty(C), + PointerType::getUnqual(C), PointerType::getUnqual(C)); + return FatbinTy; +} + +/// Embed the image \p Image into the module \p M so it can be found by the +/// runtime. +GlobalVariable *createFatbinDesc(Module &M, ArrayRef Image, bool IsHIP, + StringRef Suffix) { + LLVMContext &C = M.getContext(); + llvm::Type *Int8PtrTy = PointerType::getUnqual(C); + llvm::Triple Triple = llvm::Triple(M.getTargetTriple()); + + // Create the global string containing the fatbinary. + StringRef FatbinConstantSection = + IsHIP ? ".hip_fatbin" + : (Triple.isMacOSX() ? "__NV_CUDA,__nv_fatbin" : ".nv_fatbin"); + auto *Data = ConstantDataArray::get(C, Image); + auto *Fatbin = new GlobalVariable(M, Data->getType(), /*isConstant*/ true, + GlobalVariable::InternalLinkage, Data, + ".fatbin_image" + Suffix); + Fatbin->setSection(FatbinConstantSection); + + // Create the fatbinary wrapper + StringRef FatbinWrapperSection = IsHIP ? ".hipFatBinSegment" + : Triple.isMacOSX() ? "__NV_CUDA,__fatbin" + : ".nvFatBinSegment"; + Constant *FatbinWrapper[] = { + ConstantInt::get(Type::getInt32Ty(C), IsHIP ? HIPFatMagic : CudaFatMagic), + ConstantInt::get(Type::getInt32Ty(C), 1), + ConstantExpr::getPointerBitCastOrAddrSpaceCast(Fatbin, Int8PtrTy), + ConstantPointerNull::get(PointerType::getUnqual(C))}; + + Constant *FatbinInitializer = + ConstantStruct::get(getFatbinWrapperTy(M), FatbinWrapper); + + auto *FatbinDesc = + new GlobalVariable(M, getFatbinWrapperTy(M), + /*isConstant*/ true, GlobalValue::InternalLinkage, + FatbinInitializer, ".fatbin_wrapper" + Suffix); + FatbinDesc->setSection(FatbinWrapperSection); + FatbinDesc->setAlignment(Align(8)); + + return FatbinDesc; +} + +/// Create the register globals function. We will iterate all of the offloading +/// entries stored at the begin / end symbols and register them according to +/// their type. This creates the following function in IR: +/// +/// extern struct __tgt_offload_entry __start_cuda_offloading_entries; +/// extern struct __tgt_offload_entry __stop_cuda_offloading_entries; +/// +/// extern void __cudaRegisterFunction(void **, void *, void *, void *, int, +/// void *, void *, void *, void *, int *); +/// extern void __cudaRegisterVar(void **, void *, void *, void *, int32_t, +/// int64_t, int32_t, int32_t); +/// +/// void __cudaRegisterTest(void **fatbinHandle) { +/// for (struct __tgt_offload_entry *entry = &__start_cuda_offloading_entries; +/// entry != &__stop_cuda_offloading_entries; ++entry) { +/// if (!entry->size) +/// __cudaRegisterFunction(fatbinHandle, entry->addr, entry->name, +/// entry->name, -1, 0, 0, 0, 0, 0); +/// else +/// __cudaRegisterVar(fatbinHandle, entry->addr, entry->name, entry->name, +/// 0, entry->size, 0, 0); +/// } +/// } +Function *createRegisterGlobalsFunction(Module &M, bool IsHIP, + EntryArrayTy EntryArray, + StringRef Suffix, + bool EmitSurfacesAndTextures) { + LLVMContext &C = M.getContext(); + auto [EntriesB, EntriesE] = EntryArray; + + // Get the __cudaRegisterFunction function declaration. + PointerType *Int8PtrTy = PointerType::get(C, 0); + PointerType *Int8PtrPtrTy = PointerType::get(C, 0); + PointerType *Int32PtrTy = PointerType::get(C, 0); + auto *RegFuncTy = FunctionType::get( + Type::getInt32Ty(C), + {Int8PtrPtrTy, Int8PtrTy, Int8PtrTy, Int8PtrTy, Type::getInt32Ty(C), + Int8PtrTy, Int8PtrTy, Int8PtrTy, Int8PtrTy, Int32PtrTy}, + /*isVarArg*/ false); + FunctionCallee RegFunc = M.getOrInsertFunction( + IsHIP ? "__hipRegisterFunction" : "__cudaRegisterFunction", RegFuncTy); + + // Get the __cudaRegisterVar function declaration. + auto *RegVarTy = FunctionType::get( + Type::getVoidTy(C), + {Int8PtrPtrTy, Int8PtrTy, Int8PtrTy, Int8PtrTy, Type::getInt32Ty(C), + getSizeTTy(M), Type::getInt32Ty(C), Type::getInt32Ty(C)}, + /*isVarArg*/ false); + FunctionCallee RegVar = M.getOrInsertFunction( + IsHIP ? "__hipRegisterVar" : "__cudaRegisterVar", RegVarTy); + + // Get the __cudaRegisterSurface function declaration. + FunctionType *RegSurfaceTy = + FunctionType::get(Type::getVoidTy(C), + {Int8PtrPtrTy, Int8PtrTy, Int8PtrTy, Int8PtrTy, + Type::getInt32Ty(C), Type::getInt32Ty(C)}, + /*isVarArg=*/false); + FunctionCallee RegSurface = M.getOrInsertFunction( + IsHIP ? "__hipRegisterSurface" : "__cudaRegisterSurface", RegSurfaceTy); + + // Get the __cudaRegisterTexture function declaration. + FunctionType *RegTextureTy = FunctionType::get( + Type::getVoidTy(C), + {Int8PtrPtrTy, Int8PtrTy, Int8PtrTy, Int8PtrTy, Type::getInt32Ty(C), + Type::getInt32Ty(C), Type::getInt32Ty(C)}, + /*isVarArg=*/false); + FunctionCallee RegTexture = M.getOrInsertFunction( + IsHIP ? "__hipRegisterTexture" : "__cudaRegisterTexture", RegTextureTy); + + auto *RegGlobalsTy = FunctionType::get(Type::getVoidTy(C), Int8PtrPtrTy, + /*isVarArg*/ false); + auto *RegGlobalsFn = + Function::Create(RegGlobalsTy, GlobalValue::InternalLinkage, + IsHIP ? ".hip.globals_reg" : ".cuda.globals_reg", &M); + RegGlobalsFn->setSection(".text.startup"); + + // Create the loop to register all the entries. + IRBuilder<> Builder(BasicBlock::Create(C, "entry", RegGlobalsFn)); + auto *EntryBB = BasicBlock::Create(C, "while.entry", RegGlobalsFn); + auto *IfThenBB = BasicBlock::Create(C, "if.then", RegGlobalsFn); + auto *IfElseBB = BasicBlock::Create(C, "if.else", RegGlobalsFn); + auto *SwGlobalBB = BasicBlock::Create(C, "sw.global", RegGlobalsFn); + auto *SwManagedBB = BasicBlock::Create(C, "sw.managed", RegGlobalsFn); + auto *SwSurfaceBB = BasicBlock::Create(C, "sw.surface", RegGlobalsFn); + auto *SwTextureBB = BasicBlock::Create(C, "sw.texture", RegGlobalsFn); + auto *IfEndBB = BasicBlock::Create(C, "if.end", RegGlobalsFn); + auto *ExitBB = BasicBlock::Create(C, "while.end", RegGlobalsFn); + + auto *EntryCmp = Builder.CreateICmpNE(EntriesB, EntriesE); + Builder.CreateCondBr(EntryCmp, EntryBB, ExitBB); + Builder.SetInsertPoint(EntryBB); + auto *Entry = Builder.CreatePHI(PointerType::getUnqual(C), 2, "entry"); + auto *AddrPtr = + Builder.CreateInBoundsGEP(offloading::getEntryTy(M), Entry, + {ConstantInt::get(getSizeTTy(M), 0), + ConstantInt::get(Type::getInt32Ty(C), 0)}); + auto *Addr = Builder.CreateLoad(Int8PtrTy, AddrPtr, "addr"); + auto *NamePtr = + Builder.CreateInBoundsGEP(offloading::getEntryTy(M), Entry, + {ConstantInt::get(getSizeTTy(M), 0), + ConstantInt::get(Type::getInt32Ty(C), 1)}); + auto *Name = Builder.CreateLoad(Int8PtrTy, NamePtr, "name"); + auto *SizePtr = + Builder.CreateInBoundsGEP(offloading::getEntryTy(M), Entry, + {ConstantInt::get(getSizeTTy(M), 0), + ConstantInt::get(Type::getInt32Ty(C), 2)}); + auto *Size = Builder.CreateLoad(getSizeTTy(M), SizePtr, "size"); + auto *FlagsPtr = + Builder.CreateInBoundsGEP(offloading::getEntryTy(M), Entry, + {ConstantInt::get(getSizeTTy(M), 0), + ConstantInt::get(Type::getInt32Ty(C), 3)}); + auto *Flags = Builder.CreateLoad(Type::getInt32Ty(C), FlagsPtr, "flags"); + auto *DataPtr = + Builder.CreateInBoundsGEP(offloading::getEntryTy(M), Entry, + {ConstantInt::get(getSizeTTy(M), 0), + ConstantInt::get(Type::getInt32Ty(C), 4)}); + auto *Data = Builder.CreateLoad(Type::getInt32Ty(C), DataPtr, "textype"); + auto *Kind = Builder.CreateAnd( + Flags, ConstantInt::get(Type::getInt32Ty(C), 0x7), "type"); + + // Extract the flags stored in the bit-field and convert them to C booleans. + auto *ExternBit = Builder.CreateAnd( + Flags, ConstantInt::get(Type::getInt32Ty(C), + llvm::offloading::OffloadGlobalExtern)); + auto *Extern = Builder.CreateLShr( + ExternBit, ConstantInt::get(Type::getInt32Ty(C), 3), "extern"); + auto *ConstantBit = Builder.CreateAnd( + Flags, ConstantInt::get(Type::getInt32Ty(C), + llvm::offloading::OffloadGlobalConstant)); + auto *Const = Builder.CreateLShr( + ConstantBit, ConstantInt::get(Type::getInt32Ty(C), 4), "constant"); + auto *NormalizedBit = Builder.CreateAnd( + Flags, ConstantInt::get(Type::getInt32Ty(C), + llvm::offloading::OffloadGlobalNormalized)); + auto *Normalized = Builder.CreateLShr( + NormalizedBit, ConstantInt::get(Type::getInt32Ty(C), 5), "normalized"); + auto *FnCond = + Builder.CreateICmpEQ(Size, ConstantInt::getNullValue(getSizeTTy(M))); + Builder.CreateCondBr(FnCond, IfThenBB, IfElseBB); + + // Create kernel registration code. + Builder.SetInsertPoint(IfThenBB); + Builder.CreateCall(RegFunc, {RegGlobalsFn->arg_begin(), Addr, Name, Name, + ConstantInt::get(Type::getInt32Ty(C), -1), + ConstantPointerNull::get(Int8PtrTy), + ConstantPointerNull::get(Int8PtrTy), + ConstantPointerNull::get(Int8PtrTy), + ConstantPointerNull::get(Int8PtrTy), + ConstantPointerNull::get(Int32PtrTy)}); + Builder.CreateBr(IfEndBB); + Builder.SetInsertPoint(IfElseBB); + + auto *Switch = Builder.CreateSwitch(Kind, IfEndBB); + // Create global variable registration code. + Builder.SetInsertPoint(SwGlobalBB); + Builder.CreateCall(RegVar, + {RegGlobalsFn->arg_begin(), Addr, Name, Name, Extern, Size, + Const, ConstantInt::get(Type::getInt32Ty(C), 0)}); + Builder.CreateBr(IfEndBB); + Switch->addCase(Builder.getInt32(llvm::offloading::OffloadGlobalEntry), + SwGlobalBB); + + // Create managed variable registration code. + Builder.SetInsertPoint(SwManagedBB); + Builder.CreateBr(IfEndBB); + Switch->addCase(Builder.getInt32(llvm::offloading::OffloadGlobalManagedEntry), + SwManagedBB); + // Create surface variable registration code. + Builder.SetInsertPoint(SwSurfaceBB); + if (EmitSurfacesAndTextures) + Builder.CreateCall(RegSurface, {RegGlobalsFn->arg_begin(), Addr, Name, Name, + Data, Extern}); + Builder.CreateBr(IfEndBB); + Switch->addCase(Builder.getInt32(llvm::offloading::OffloadGlobalSurfaceEntry), + SwSurfaceBB); + + // Create texture variable registration code. + Builder.SetInsertPoint(SwTextureBB); + if (EmitSurfacesAndTextures) + Builder.CreateCall(RegTexture, {RegGlobalsFn->arg_begin(), Addr, Name, Name, + Data, Normalized, Extern}); + Builder.CreateBr(IfEndBB); + Switch->addCase(Builder.getInt32(llvm::offloading::OffloadGlobalTextureEntry), + SwTextureBB); + + Builder.SetInsertPoint(IfEndBB); + auto *NewEntry = Builder.CreateInBoundsGEP( + offloading::getEntryTy(M), Entry, ConstantInt::get(getSizeTTy(M), 1)); + auto *Cmp = Builder.CreateICmpEQ( + NewEntry, + ConstantExpr::getInBoundsGetElementPtr( + ArrayType::get(offloading::getEntryTy(M), 0), EntriesE, + ArrayRef({ConstantInt::get(getSizeTTy(M), 0), + ConstantInt::get(getSizeTTy(M), 0)}))); + Entry->addIncoming( + ConstantExpr::getInBoundsGetElementPtr( + ArrayType::get(offloading::getEntryTy(M), 0), EntriesB, + ArrayRef({ConstantInt::get(getSizeTTy(M), 0), + ConstantInt::get(getSizeTTy(M), 0)})), + &RegGlobalsFn->getEntryBlock()); + Entry->addIncoming(NewEntry, IfEndBB); + Builder.CreateCondBr(Cmp, ExitBB, EntryBB); + Builder.SetInsertPoint(ExitBB); + Builder.CreateRetVoid(); + + return RegGlobalsFn; +} + +// Create the constructor and destructor to register the fatbinary with the CUDA +// runtime. +void createRegisterFatbinFunction(Module &M, GlobalVariable *FatbinDesc, + bool IsHIP, EntryArrayTy EntryArray, + StringRef Suffix, + bool EmitSurfacesAndTextures) { + LLVMContext &C = M.getContext(); + auto *CtorFuncTy = FunctionType::get(Type::getVoidTy(C), /*isVarArg*/ false); + auto *CtorFunc = Function::Create( + CtorFuncTy, GlobalValue::InternalLinkage, + (IsHIP ? ".hip.fatbin_reg" : ".cuda.fatbin_reg") + Suffix, &M); + CtorFunc->setSection(".text.startup"); + + auto *DtorFuncTy = FunctionType::get(Type::getVoidTy(C), /*isVarArg*/ false); + auto *DtorFunc = Function::Create( + DtorFuncTy, GlobalValue::InternalLinkage, + (IsHIP ? ".hip.fatbin_unreg" : ".cuda.fatbin_unreg") + Suffix, &M); + DtorFunc->setSection(".text.startup"); + + auto *PtrTy = PointerType::getUnqual(C); + + // Get the __cudaRegisterFatBinary function declaration. + auto *RegFatTy = FunctionType::get(PtrTy, PtrTy, /*isVarArg=*/false); + FunctionCallee RegFatbin = M.getOrInsertFunction( + IsHIP ? "__hipRegisterFatBinary" : "__cudaRegisterFatBinary", RegFatTy); + // Get the __cudaRegisterFatBinaryEnd function declaration. + auto *RegFatEndTy = + FunctionType::get(Type::getVoidTy(C), PtrTy, /*isVarArg=*/false); + FunctionCallee RegFatbinEnd = + M.getOrInsertFunction("__cudaRegisterFatBinaryEnd", RegFatEndTy); + // Get the __cudaUnregisterFatBinary function declaration. + auto *UnregFatTy = + FunctionType::get(Type::getVoidTy(C), PtrTy, /*isVarArg=*/false); + FunctionCallee UnregFatbin = M.getOrInsertFunction( + IsHIP ? "__hipUnregisterFatBinary" : "__cudaUnregisterFatBinary", + UnregFatTy); + + auto *AtExitTy = + FunctionType::get(Type::getInt32Ty(C), PtrTy, /*isVarArg=*/false); + FunctionCallee AtExit = M.getOrInsertFunction("atexit", AtExitTy); + + auto *BinaryHandleGlobal = new llvm::GlobalVariable( + M, PtrTy, false, llvm::GlobalValue::InternalLinkage, + llvm::ConstantPointerNull::get(PtrTy), + (IsHIP ? ".hip.binary_handle" : ".cuda.binary_handle") + Suffix); + + // Create the constructor to register this image with the runtime. + IRBuilder<> CtorBuilder(BasicBlock::Create(C, "entry", CtorFunc)); + CallInst *Handle = CtorBuilder.CreateCall( + RegFatbin, + ConstantExpr::getPointerBitCastOrAddrSpaceCast(FatbinDesc, PtrTy)); + CtorBuilder.CreateAlignedStore( + Handle, BinaryHandleGlobal, + Align(M.getDataLayout().getPointerTypeSize(PtrTy))); + CtorBuilder.CreateCall(createRegisterGlobalsFunction(M, IsHIP, EntryArray, + Suffix, + EmitSurfacesAndTextures), + Handle); + if (!IsHIP) + CtorBuilder.CreateCall(RegFatbinEnd, Handle); + CtorBuilder.CreateCall(AtExit, DtorFunc); + CtorBuilder.CreateRetVoid(); + + // Create the destructor to unregister the image with the runtime. We cannot + // use a standard global destructor after CUDA 9.2 so this must be called by + // `atexit()` intead. + IRBuilder<> DtorBuilder(BasicBlock::Create(C, "entry", DtorFunc)); + LoadInst *BinaryHandle = DtorBuilder.CreateAlignedLoad( + PtrTy, BinaryHandleGlobal, + Align(M.getDataLayout().getPointerTypeSize(PtrTy))); + DtorBuilder.CreateCall(UnregFatbin, BinaryHandle); + DtorBuilder.CreateRetVoid(); + + // Add this function to constructors. + appendToGlobalCtors(M, CtorFunc, /*Priority*/ 1); +} +} // namespace + +Error offloading::wrapOpenMPBinaries(Module &M, ArrayRef> Images, + EntryArrayTy EntryArray, + llvm::StringRef Suffix) { + GlobalVariable *Desc = createBinDesc(M, Images, EntryArray, Suffix); + if (!Desc) + return createStringError(inconvertibleErrorCode(), + "No binary descriptors created."); + createRegisterFunction(M, Desc, Suffix); + createUnregisterFunction(M, Desc, Suffix); + return Error::success(); +} + +Error offloading::wrapCudaBinary(Module &M, ArrayRef Image, + EntryArrayTy EntryArray, + llvm::StringRef Suffix, + bool EmitSurfacesAndTextures) { + GlobalVariable *Desc = createFatbinDesc(M, Image, /*IsHip=*/false, Suffix); + if (!Desc) + return createStringError(inconvertibleErrorCode(), + "No fatbin section created."); + + createRegisterFatbinFunction(M, Desc, /*IsHip=*/false, EntryArray, Suffix, + EmitSurfacesAndTextures); + return Error::success(); +} + +Error offloading::wrapHIPBinary(Module &M, ArrayRef Image, + EntryArrayTy EntryArray, llvm::StringRef Suffix, + bool EmitSurfacesAndTextures) { + GlobalVariable *Desc = createFatbinDesc(M, Image, /*IsHip=*/true, Suffix); + if (!Desc) + return createStringError(inconvertibleErrorCode(), + "No fatbin section created."); + + createRegisterFatbinFunction(M, Desc, /*IsHip=*/true, EntryArray, Suffix, + EmitSurfacesAndTextures); + return Error::success(); +} diff --git a/llvm/lib/Frontend/Offloading/Utility.cpp b/llvm/lib/Frontend/Offloading/Utility.cpp index 25f609517eb..531919bccb9 100644 --- a/llvm/lib/Frontend/Offloading/Utility.cpp +++ b/llvm/lib/Frontend/Offloading/Utility.cpp @@ -1,4 +1,4 @@ -//===- Utility.cpp ------ Collection of geneirc offloading utilities ------===// +//===- Utility.cpp ------ Collection of generic offloading utilities ------===// // // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. // See https://llvm.org/LICENSE.txt for license information. @@ -28,11 +28,10 @@ StructType *offloading::getEntryTy(Module &M) { } // TODO: Rework this interface to be more generic. -void offloading::emitOffloadingEntry(Module &M, Constant *Addr, StringRef Name, - uint64_t Size, int32_t Flags, int32_t Data, - StringRef SectionName) { - llvm::Triple Triple(M.getTargetTriple()); - +std::pair +offloading::getOffloadingEntryInitializer(Module &M, Constant *Addr, + StringRef Name, uint64_t Size, + int32_t Flags, int32_t Data) { Type *Int8PtrTy = PointerType::getUnqual(M.getContext()); Type *Int32Ty = Type::getInt32Ty(M.getContext()); Type *SizeTy = M.getDataLayout().getIntPtrType(M.getContext()); @@ -54,6 +53,16 @@ void offloading::emitOffloadingEntry(Module &M, Constant *Addr, StringRef Name, ConstantInt::get(Int32Ty, Data), }; Constant *EntryInitializer = ConstantStruct::get(getEntryTy(M), EntryData); + return {EntryInitializer, Str}; +} + +void offloading::emitOffloadingEntry(Module &M, Constant *Addr, StringRef Name, + uint64_t Size, int32_t Flags, int32_t Data, + StringRef SectionName) { + llvm::Triple Triple(M.getTargetTriple()); + + auto [EntryInitializer, NameGV] = + getOffloadingEntryInitializer(M, Addr, Name, Size, Flags, Data); auto *Entry = new GlobalVariable( M, getEntryTy(M), diff --git a/llvm/lib/Frontend/OpenMP/OMPIRBuilder.cpp b/llvm/lib/Frontend/OpenMP/OMPIRBuilder.cpp index f6cf358119f..211281452de 100644 --- a/llvm/lib/Frontend/OpenMP/OMPIRBuilder.cpp +++ b/llvm/lib/Frontend/OpenMP/OMPIRBuilder.cpp @@ -2876,9 +2876,10 @@ OpenMPIRBuilder::applyWorkshareLoopTarget(DebugLoc DL, CanonicalLoopInfo *CLI, // We need to model loop body region as the function f(cnt, loop_arg). // That's why we replace loop induction variable by the new counter // which will be one of loop body function argument - for (auto Use = CLI->getIndVar()->user_begin(); - Use != CLI->getIndVar()->user_end(); ++Use) { - if (Instruction *Inst = dyn_cast(*Use)) { + SmallVector Users(CLI->getIndVar()->user_begin(), + CLI->getIndVar()->user_end()); + for (auto Use : Users) { + if (Instruction *Inst = dyn_cast(Use)) { if (ParallelRegionBlockSet.count(Inst->getParent())) { Inst->replaceUsesOfWith(CLI->getIndVar(), NewLoopCntLoad); } diff --git a/llvm/lib/IR/AsmWriter.cpp b/llvm/lib/IR/AsmWriter.cpp index 278cdfce411..3c15784a0ed 100644 --- a/llvm/lib/IR/AsmWriter.cpp +++ b/llvm/lib/IR/AsmWriter.cpp @@ -1140,6 +1140,9 @@ void SlotTracker::processFunctionMetadata(const Function &F) { void SlotTracker::processDPValueMetadata(const DPValue &DPV) { CreateMetadataSlot(DPV.getVariable()); CreateMetadataSlot(DPV.getDebugLoc()); + if (DPV.isDbgAssign()) { + CreateMetadataSlot(DPV.getAssignID()); + } } void SlotTracker::processInstructionMetadata(const Instruction &I) { @@ -4571,7 +4574,22 @@ void AssemblyWriter::printDPMarker(const DPMarker &Marker) { void AssemblyWriter::printDPValue(const DPValue &Value) { // There's no formal representation of a DPValue -- print purely as a // debugging aid. - Out << " DPValue { "; + Out << " DPValue "; + + switch (Value.getType()) { + case DPValue::LocationType::Value: + Out << "value"; + break; + case DPValue::LocationType::Declare: + Out << "declare"; + break; + case DPValue::LocationType::Assign: + Out << "assign"; + break; + default: + llvm_unreachable("Tried to print a DPValue with an invalid LocationType!"); + } + Out << " { "; auto WriterCtx = getContext(); WriteAsOperandInternal(Out, Value.getRawLocation(), WriterCtx, true); Out << ", "; @@ -4579,6 +4597,14 @@ void AssemblyWriter::printDPValue(const DPValue &Value) { Out << ", "; WriteAsOperandInternal(Out, Value.getExpression(), WriterCtx, true); Out << ", "; + if (Value.isDbgAssign()) { + WriteAsOperandInternal(Out, Value.getAssignID(), WriterCtx, true); + Out << ", "; + WriteAsOperandInternal(Out, Value.getRawAddress(), WriterCtx, true); + Out << ", "; + WriteAsOperandInternal(Out, Value.getAddressExpression(), WriterCtx, true); + Out << ", "; + } WriteAsOperandInternal(Out, Value.getDebugLoc().get(), WriterCtx, true); Out << " marker @" << Value.getMarker(); Out << " }"; diff --git a/llvm/lib/IR/AutoUpgrade.cpp b/llvm/lib/IR/AutoUpgrade.cpp index 3a3b41fb786..b90bbe71ac1 100644 --- a/llvm/lib/IR/AutoUpgrade.cpp +++ b/llvm/lib/IR/AutoUpgrade.cpp @@ -53,7 +53,7 @@ static void rename(GlobalValue *GV) { GV->setName(GV->getName() + ".old"); } // Upgrade the declarations of the SSE4.1 ptest intrinsics whose arguments have // changed their type from v4f32 to v2i64. -static bool UpgradePTESTIntrinsic(Function* F, Intrinsic::ID IID, +static bool upgradePTESTIntrinsic(Function *F, Intrinsic::ID IID, Function *&NewFn) { // Check whether this is an old version of the function, which received // v4f32 arguments. @@ -69,7 +69,7 @@ static bool UpgradePTESTIntrinsic(Function* F, Intrinsic::ID IID, // Upgrade the declarations of intrinsic functions whose 8-bit immediate mask // arguments have changed their type from i32 to i8. -static bool UpgradeX86IntrinsicsWith8BitMask(Function *F, Intrinsic::ID IID, +static bool upgradeX86IntrinsicsWith8BitMask(Function *F, Intrinsic::ID IID, Function *&NewFn) { // Check that the last argument is an i32. Type *LastArgType = F->getFunctionType()->getParamType( @@ -85,7 +85,7 @@ static bool UpgradeX86IntrinsicsWith8BitMask(Function *F, Intrinsic::ID IID, // Upgrade the declaration of fp compare intrinsics that change return type // from scalar to vXi1 mask. -static bool UpgradeX86MaskedFPCompare(Function *F, Intrinsic::ID IID, +static bool upgradeX86MaskedFPCompare(Function *F, Intrinsic::ID IID, Function *&NewFn) { // Check if the return type is a vector. if (F->getReturnType()->isVectorTy()) @@ -96,7 +96,7 @@ static bool UpgradeX86MaskedFPCompare(Function *F, Intrinsic::ID IID, return true; } -static bool UpgradeX86BF16Intrinsic(Function *F, Intrinsic::ID IID, +static bool upgradeX86BF16Intrinsic(Function *F, Intrinsic::ID IID, Function *&NewFn) { if (F->getReturnType()->getScalarType()->isBFloatTy()) return false; @@ -106,7 +106,7 @@ static bool UpgradeX86BF16Intrinsic(Function *F, Intrinsic::ID IID, return true; } -static bool UpgradeX86BF16DPIntrinsic(Function *F, Intrinsic::ID IID, +static bool upgradeX86BF16DPIntrinsic(Function *F, Intrinsic::ID IID, Function *&NewFn) { if (F->getFunctionType()->getParamType(1)->getScalarType()->isBFloatTy()) return false; @@ -116,7 +116,7 @@ static bool UpgradeX86BF16DPIntrinsic(Function *F, Intrinsic::ID IID, return true; } -static bool ShouldUpgradeX86Intrinsic(Function *F, StringRef Name) { +static bool shouldUpgradeX86Intrinsic(Function *F, StringRef Name) { // All of the intrinsics matches below should be marked with which llvm // version started autoupgrading them. At some point in the future we would // like to use this information to remove upgrade code for some older @@ -483,13 +483,13 @@ static bool ShouldUpgradeX86Intrinsic(Function *F, StringRef Name) { Name.starts_with("vcvtph2ps.")); // Added in 11.0 } -static bool UpgradeX86IntrinsicFunction(Function *F, StringRef Name, +static bool upgradeX86IntrinsicFunction(Function *F, StringRef Name, Function *&NewFn) { // Only handle intrinsics that start with "x86.". if (!Name.consume_front("x86.")) return false; - if (ShouldUpgradeX86Intrinsic(F, Name)) { + if (shouldUpgradeX86Intrinsic(F, Name)) { NewFn = nullptr; return true; } @@ -515,7 +515,7 @@ static bool UpgradeX86IntrinsicFunction(Function *F, StringRef Name, .Case("nzc", Intrinsic::x86_sse41_ptestnzc) .Default(Intrinsic::not_intrinsic); if (ID != Intrinsic::not_intrinsic) - return UpgradePTESTIntrinsic(F, ID, NewFn); + return upgradePTESTIntrinsic(F, ID, NewFn); return false; } @@ -533,7 +533,7 @@ static bool UpgradeX86IntrinsicFunction(Function *F, StringRef Name, .Case("avx2.mpsadbw", Intrinsic::x86_avx2_mpsadbw) .Default(Intrinsic::not_intrinsic); if (ID != Intrinsic::not_intrinsic) - return UpgradeX86IntrinsicsWith8BitMask(F, ID, NewFn); + return upgradeX86IntrinsicsWith8BitMask(F, ID, NewFn); if (Name.consume_front("avx512.mask.cmp.")) { // Added in 7.0 @@ -546,7 +546,7 @@ static bool UpgradeX86IntrinsicFunction(Function *F, StringRef Name, .Case("ps.512", Intrinsic::x86_avx512_mask_cmp_ps_512) .Default(Intrinsic::not_intrinsic); if (ID != Intrinsic::not_intrinsic) - return UpgradeX86MaskedFPCompare(F, ID, NewFn); + return upgradeX86MaskedFPCompare(F, ID, NewFn); return false; // No other 'x86.avx523.mask.cmp.*'. } @@ -567,7 +567,7 @@ static bool UpgradeX86IntrinsicFunction(Function *F, StringRef Name, Intrinsic::x86_avx512bf16_cvtneps2bf16_512) .Default(Intrinsic::not_intrinsic); if (ID != Intrinsic::not_intrinsic) - return UpgradeX86BF16Intrinsic(F, ID, NewFn); + return upgradeX86BF16Intrinsic(F, ID, NewFn); // Added in 9.0 ID = StringSwitch(Name) @@ -576,7 +576,7 @@ static bool UpgradeX86IntrinsicFunction(Function *F, StringRef Name, .Case("dpbf16ps.512", Intrinsic::x86_avx512bf16_dpbf16ps_512) .Default(Intrinsic::not_intrinsic); if (ID != Intrinsic::not_intrinsic) - return UpgradeX86BF16DPIntrinsic(F, ID, NewFn); + return upgradeX86BF16DPIntrinsic(F, ID, NewFn); return false; // No other 'x86.avx512bf16.*'. } @@ -623,7 +623,7 @@ static bool UpgradeX86IntrinsicFunction(Function *F, StringRef Name, // Upgrade ARM (IsArm) or Aarch64 (!IsArm) intrinsic fns. Return true iff so. // IsArm: 'arm.*', !IsArm: 'aarch64.*'. -static bool UpgradeArmOrAarch64IntrinsicFunction(bool IsArm, Function *F, +static bool upgradeArmOrAarch64IntrinsicFunction(bool IsArm, Function *F, StringRef Name, Function *&NewFn) { if (Name.starts_with("rbit")) { @@ -899,7 +899,7 @@ static bool UpgradeArmOrAarch64IntrinsicFunction(bool IsArm, Function *F, return false; // No other 'arm.*', 'aarch64.*'. } -static Intrinsic::ID ShouldUpgradeNVPTXBF16Intrinsic(StringRef Name) { +static Intrinsic::ID shouldUpgradeNVPTXBF16Intrinsic(StringRef Name) { if (Name.consume_front("abs.")) return StringSwitch(Name) .Case("bf16", Intrinsic::nvvm_abs_bf16) @@ -979,7 +979,7 @@ static Intrinsic::ID ShouldUpgradeNVPTXBF16Intrinsic(StringRef Name) { return Intrinsic::not_intrinsic; } -static bool UpgradeIntrinsicFunction1(Function *F, Function *&NewFn) { +static bool upgradeIntrinsicFunction1(Function *F, Function *&NewFn) { assert(F && "Illegal to upgrade a non-existent Function."); StringRef Name = F->getName(); @@ -993,7 +993,7 @@ static bool UpgradeIntrinsicFunction1(Function *F, Function *&NewFn) { case 'a': { bool IsArm = Name.consume_front("arm."); if (IsArm || Name.consume_front("aarch64.")) { - if (UpgradeArmOrAarch64IntrinsicFunction(IsArm, F, Name, NewFn)) + if (upgradeArmOrAarch64IntrinsicFunction(IsArm, F, Name, NewFn)) return true; break; } @@ -1190,7 +1190,7 @@ static bool UpgradeIntrinsicFunction1(Function *F, Function *&NewFn) { // Check for nvvm intrinsics that need a return type adjustment. if (!F->getReturnType()->getScalarType()->isBFloatTy()) { - Intrinsic::ID IID = ShouldUpgradeNVPTXBF16Intrinsic(Name); + Intrinsic::ID IID = shouldUpgradeNVPTXBF16Intrinsic(Name); if (IID != Intrinsic::not_intrinsic) { NewFn = nullptr; return true; @@ -1209,7 +1209,8 @@ static bool UpgradeIntrinsicFunction1(Function *F, Function *&NewFn) { Expand = true; else if (Name.consume_front("max.") || Name.consume_front("min.")) // nvvm.{min,max}.{i,ii,ui,ull} - Expand = Name == "i" || Name == "ll" || Name == "ui" || Name == "ull"; + Expand = Name == "s" || Name == "i" || Name == "ll" || Name == "us" || + Name == "ui" || Name == "ull"; else if (Name.consume_front("atomic.load.add.")) // nvvm.atomic.load.add.{f32.p,f64.p} Expand = Name.starts_with("f32.p") || Name.starts_with("f64.p"); @@ -1353,7 +1354,7 @@ static bool UpgradeIntrinsicFunction1(Function *F, Function *&NewFn) { break; case 'x': - if (UpgradeX86IntrinsicFunction(F, Name, NewFn)) + if (upgradeX86IntrinsicFunction(F, Name, NewFn)) return true; } @@ -1398,7 +1399,7 @@ static bool UpgradeIntrinsicFunction1(Function *F, Function *&NewFn) { bool llvm::UpgradeIntrinsicFunction(Function *F, Function *&NewFn) { NewFn = nullptr; - bool Upgraded = UpgradeIntrinsicFunction1(F, NewFn); + bool Upgraded = upgradeIntrinsicFunction1(F, NewFn); assert(F != NewFn && "Intrinsic function upgraded to the same function"); // Upgrade intrinsic attributes. This does not change the function. @@ -1442,8 +1443,8 @@ GlobalVariable *llvm::UpgradeGlobalVariable(GlobalVariable *GV) { // Handles upgrading SSE2/AVX2/AVX512BW PSLLDQ intrinsics by converting them // to byte shuffles. -static Value *UpgradeX86PSLLDQIntrinsics(IRBuilder<> &Builder, - Value *Op, unsigned Shift) { +static Value *upgradeX86PSLLDQIntrinsics(IRBuilder<> &Builder, Value *Op, + unsigned Shift) { auto *ResultTy = cast(Op->getType()); unsigned NumElts = ResultTy->getNumElements() * 8; @@ -1476,7 +1477,7 @@ static Value *UpgradeX86PSLLDQIntrinsics(IRBuilder<> &Builder, // Handles upgrading SSE2/AVX2/AVX512BW PSRLDQ intrinsics by converting them // to byte shuffles. -static Value *UpgradeX86PSRLDQIntrinsics(IRBuilder<> &Builder, Value *Op, +static Value *upgradeX86PSRLDQIntrinsics(IRBuilder<> &Builder, Value *Op, unsigned Shift) { auto *ResultTy = cast(Op->getType()); unsigned NumElts = ResultTy->getNumElements() * 8; @@ -1528,8 +1529,8 @@ static Value *getX86MaskVec(IRBuilder<> &Builder, Value *Mask, return Mask; } -static Value *EmitX86Select(IRBuilder<> &Builder, Value *Mask, - Value *Op0, Value *Op1) { +static Value *emitX86Select(IRBuilder<> &Builder, Value *Mask, Value *Op0, + Value *Op1) { // If the mask is all ones just emit the first operation. if (const auto *C = dyn_cast(Mask)) if (C->isAllOnesValue()) @@ -1540,8 +1541,8 @@ static Value *EmitX86Select(IRBuilder<> &Builder, Value *Mask, return Builder.CreateSelect(Mask, Op0, Op1); } -static Value *EmitX86ScalarSelect(IRBuilder<> &Builder, Value *Mask, - Value *Op0, Value *Op1) { +static Value *emitX86ScalarSelect(IRBuilder<> &Builder, Value *Mask, Value *Op0, + Value *Op1) { // If the mask is all ones just emit the first operation. if (const auto *C = dyn_cast(Mask)) if (C->isAllOnesValue()) @@ -1557,7 +1558,7 @@ static Value *EmitX86ScalarSelect(IRBuilder<> &Builder, Value *Mask, // Handle autoupgrade for masked PALIGNR and VALIGND/Q intrinsics. // PALIGNR handles large immediates by shifting while VALIGN masks the immediate // so we need to handle both cases. VALIGN also doesn't have 128-bit lanes. -static Value *UpgradeX86ALIGNIntrinsics(IRBuilder<> &Builder, Value *Op0, +static Value *upgradeX86ALIGNIntrinsics(IRBuilder<> &Builder, Value *Op0, Value *Op1, Value *Shift, Value *Passthru, Value *Mask, bool IsVALIGN) { @@ -1599,10 +1600,10 @@ static Value *UpgradeX86ALIGNIntrinsics(IRBuilder<> &Builder, Value *Op0, Value *Align = Builder.CreateShuffleVector( Op1, Op0, ArrayRef(Indices, NumElts), "palignr"); - return EmitX86Select(Builder, Mask, Align, Passthru); + return emitX86Select(Builder, Mask, Align, Passthru); } -static Value *UpgradeX86VPERMT2Intrinsics(IRBuilder<> &Builder, CallBase &CI, +static Value *upgradeX86VPERMT2Intrinsics(IRBuilder<> &Builder, CallBase &CI, bool ZeroMask, bool IndexForm) { Type *Ty = CI.getType(); unsigned VecWidth = Ty->getPrimitiveSizeInBits(); @@ -1660,10 +1661,10 @@ static Value *UpgradeX86VPERMT2Intrinsics(IRBuilder<> &Builder, CallBase &CI, Value *PassThru = ZeroMask ? ConstantAggregateZero::get(Ty) : Builder.CreateBitCast(CI.getArgOperand(1), Ty); - return EmitX86Select(Builder, CI.getArgOperand(3), V, PassThru); + return emitX86Select(Builder, CI.getArgOperand(3), V, PassThru); } -static Value *UpgradeX86BinaryIntrinsics(IRBuilder<> &Builder, CallBase &CI, +static Value *upgradeX86BinaryIntrinsics(IRBuilder<> &Builder, CallBase &CI, Intrinsic::ID IID) { Type *Ty = CI.getType(); Value *Op0 = CI.getOperand(0); @@ -1674,7 +1675,7 @@ static Value *UpgradeX86BinaryIntrinsics(IRBuilder<> &Builder, CallBase &CI, if (CI.arg_size() == 4) { // For masked intrinsics. Value *VecSrc = CI.getOperand(2); Value *Mask = CI.getOperand(3); - Res = EmitX86Select(Builder, Mask, Res, VecSrc); + Res = emitX86Select(Builder, Mask, Res, VecSrc); } return Res; } @@ -1701,7 +1702,7 @@ static Value *upgradeX86Rotate(IRBuilder<> &Builder, CallBase &CI, if (CI.arg_size() == 4) { // For masked intrinsics. Value *VecSrc = CI.getOperand(2); Value *Mask = CI.getOperand(3); - Res = EmitX86Select(Builder, Mask, Res, VecSrc); + Res = emitX86Select(Builder, Mask, Res, VecSrc); } return Res; } @@ -1774,14 +1775,13 @@ static Value *upgradeX86ConcatShift(IRBuilder<> &Builder, CallBase &CI, ZeroMask ? ConstantAggregateZero::get(CI.getType()) : CI.getArgOperand(0); Value *Mask = CI.getOperand(NumArgs - 1); - Res = EmitX86Select(Builder, Mask, Res, VecSrc); + Res = emitX86Select(Builder, Mask, Res, VecSrc); } return Res; } -static Value *UpgradeMaskedStore(IRBuilder<> &Builder, - Value *Ptr, Value *Data, Value *Mask, - bool Aligned) { +static Value *upgradeMaskedStore(IRBuilder<> &Builder, Value *Ptr, Value *Data, + Value *Mask, bool Aligned) { // Cast the pointer to the right type. Ptr = Builder.CreateBitCast(Ptr, llvm::PointerType::getUnqual(Data->getType())); @@ -1801,9 +1801,8 @@ static Value *UpgradeMaskedStore(IRBuilder<> &Builder, return Builder.CreateMaskedStore(Data, Ptr, Alignment, Mask); } -static Value *UpgradeMaskedLoad(IRBuilder<> &Builder, - Value *Ptr, Value *Passthru, Value *Mask, - bool Aligned) { +static Value *upgradeMaskedLoad(IRBuilder<> &Builder, Value *Ptr, + Value *Passthru, Value *Mask, bool Aligned) { Type *ValTy = Passthru->getType(); // Cast the pointer to the right type. Ptr = Builder.CreateBitCast(Ptr, llvm::PointerType::getUnqual(ValTy)); @@ -1831,7 +1830,7 @@ static Value *upgradeAbs(IRBuilder<> &Builder, CallBase &CI) { Function *F = Intrinsic::getDeclaration(CI.getModule(), Intrinsic::abs, Ty); Value *Res = Builder.CreateCall(F, {Op0, Builder.getInt1(false)}); if (CI.arg_size() == 3) - Res = EmitX86Select(Builder, CI.getArgOperand(2), Res, CI.getArgOperand(1)); + Res = emitX86Select(Builder, CI.getArgOperand(2), Res, CI.getArgOperand(1)); return Res; } @@ -1859,13 +1858,13 @@ static Value *upgradePMULDQ(IRBuilder<> &Builder, CallBase &CI, bool IsSigned) { Value *Res = Builder.CreateMul(LHS, RHS); if (CI.arg_size() == 4) - Res = EmitX86Select(Builder, CI.getArgOperand(3), Res, CI.getArgOperand(2)); + Res = emitX86Select(Builder, CI.getArgOperand(3), Res, CI.getArgOperand(2)); return Res; } // Applying mask on vector of i1's and make sure result is at least 8 bits wide. -static Value *ApplyX86MaskOn1BitsVec(IRBuilder<> &Builder, Value *Vec, +static Value *applyX86MaskOn1BitsVec(IRBuilder<> &Builder, Value *Vec, Value *Mask) { unsigned NumElts = cast(Vec->getType())->getNumElements(); if (Mask) { @@ -1915,19 +1914,19 @@ static Value *upgradeMaskedCompare(IRBuilder<> &Builder, CallBase &CI, Value *Mask = CI.getArgOperand(CI.arg_size() - 1); - return ApplyX86MaskOn1BitsVec(Builder, Cmp, Mask); + return applyX86MaskOn1BitsVec(Builder, Cmp, Mask); } // Replace a masked intrinsic with an older unmasked intrinsic. -static Value *UpgradeX86MaskedShift(IRBuilder<> &Builder, CallBase &CI, +static Value *upgradeX86MaskedShift(IRBuilder<> &Builder, CallBase &CI, Intrinsic::ID IID) { Function *Intrin = Intrinsic::getDeclaration(CI.getModule(), IID); Value *Rep = Builder.CreateCall(Intrin, { CI.getArgOperand(0), CI.getArgOperand(1) }); - return EmitX86Select(Builder, CI.getArgOperand(3), Rep, CI.getArgOperand(2)); + return emitX86Select(Builder, CI.getArgOperand(3), Rep, CI.getArgOperand(2)); } -static Value* upgradeMaskedMove(IRBuilder<> &Builder, CallBase &CI) { +static Value *upgradeMaskedMove(IRBuilder<> &Builder, CallBase &CI) { Value* A = CI.getArgOperand(0); Value* B = CI.getArgOperand(1); Value* Src = CI.getArgOperand(2); @@ -1941,8 +1940,7 @@ static Value* upgradeMaskedMove(IRBuilder<> &Builder, CallBase &CI) { return Builder.CreateInsertElement(A, Select, (uint64_t)0); } - -static Value* UpgradeMaskToInt(IRBuilder<> &Builder, CallBase &CI) { +static Value *upgradeMaskToInt(IRBuilder<> &Builder, CallBase &CI) { Value* Op = CI.getArgOperand(0); Type* ReturnOp = CI.getType(); unsigned NumElts = cast(CI.getType())->getNumElements(); @@ -2184,7 +2182,7 @@ static bool upgradeAVX512MaskToSelect(StringRef Name, IRBuilder<> &Builder, Rep = Builder.CreateCall(Intrinsic::getDeclaration(CI.getModule(), IID), Args); unsigned NumArgs = CI.arg_size(); - Rep = EmitX86Select(Builder, CI.getArgOperand(NumArgs - 1), Rep, + Rep = emitX86Select(Builder, CI.getArgOperand(NumArgs - 1), Rep, CI.getArgOperand(NumArgs - 2)); return true; } @@ -2200,7 +2198,7 @@ void llvm::UpgradeInlineAsmString(std::string *AsmStr) { } } -static Value *UpgradeARMIntrinsicCall(StringRef Name, CallBase *CI, Function *F, +static Value *upgradeARMIntrinsicCall(StringRef Name, CallBase *CI, Function *F, IRBuilder<> &Builder) { if (Name == "mve.vctp64.old") { // Replace the old v4i1 vctp64 with a v2i1 vctp and predicate-casts to the @@ -2294,7 +2292,7 @@ static Value *UpgradeARMIntrinsicCall(StringRef Name, CallBase *CI, Function *F, llvm_unreachable("Unknown function for ARM CallBase upgrade."); } -static Value *UpgradeAMDGCNIntrinsicCall(StringRef Name, CallBase *CI, +static Value *upgradeAMDGCNIntrinsicCall(StringRef Name, CallBase *CI, Function *F, IRBuilder<> &Builder) { const bool IsInc = Name.starts_with("atomic.inc."); if (IsInc || Name.starts_with("atomic.dec.")) { @@ -2351,18 +2349,10 @@ void llvm::UpgradeIntrinsicCall(CallBase *CI, Function *NewFn) { assert(Name.starts_with("llvm.") && "Intrinsic doesn't start with 'llvm.'"); Name = Name.substr(5); - bool IsX86 = Name.starts_with("x86."); - if (IsX86) - Name = Name.substr(4); - bool IsNVVM = Name.starts_with("nvvm."); - if (IsNVVM) - Name = Name.substr(5); - bool IsARM = Name.starts_with("arm."); - if (IsARM) - Name = Name.substr(4); - bool IsAMDGCN = Name.starts_with("amdgcn."); - if (IsAMDGCN) - Name = Name.substr(7); + bool IsX86 = Name.consume_front("x86."); + bool IsNVVM = Name.consume_front("nvvm."); + bool IsARM = Name.consume_front("arm."); + bool IsAMDGCN = Name.consume_front("amdgcn."); if (IsX86 && Name.starts_with("sse4a.movnt.")) { SmallVector Elts; @@ -2448,7 +2438,7 @@ void llvm::UpgradeIntrinsicCall(CallBase *CI, Function *NewFn) { if (IsX86 && Name == "avx512.mask.store.ss") { Value *Mask = Builder.CreateAnd(CI->getArgOperand(2), Builder.getInt8(1)); - UpgradeMaskedStore(Builder, CI->getArgOperand(0), CI->getArgOperand(1), + upgradeMaskedStore(Builder, CI->getArgOperand(0), CI->getArgOperand(1), Mask, false); // Remove intrinsic. @@ -2456,10 +2446,10 @@ void llvm::UpgradeIntrinsicCall(CallBase *CI, Function *NewFn) { return; } - if (IsX86 && (Name.starts_with("avx512.mask.store"))) { + if (IsX86 && Name.starts_with("avx512.mask.store")) { // "avx512.mask.storeu." or "avx512.mask.store." bool Aligned = Name[17] != 'u'; // "avx512.mask.storeu". - UpgradeMaskedStore(Builder, CI->getArgOperand(0), CI->getArgOperand(1), + upgradeMaskedStore(Builder, CI->getArgOperand(0), CI->getArgOperand(1), CI->getArgOperand(2), Aligned); // Remove intrinsic. @@ -2515,7 +2505,7 @@ void llvm::UpgradeIntrinsicCall(CallBase *CI, Function *NewFn) { CI->getType()), {CI->getArgOperand(0)}); } - Rep = EmitX86Select(Builder, CI->getArgOperand(2), Rep, + Rep = emitX86Select(Builder, CI->getArgOperand(2), Rep, CI->getArgOperand(1)); } else if (IsX86 && (Name.starts_with("avx512.ptestm") || Name.starts_with("avx512.ptestnm"))) { @@ -2528,12 +2518,12 @@ void llvm::UpgradeIntrinsicCall(CallBase *CI, Function *NewFn) { ICmpInst::Predicate Pred = Name.starts_with("avx512.ptestm") ? ICmpInst::ICMP_NE : ICmpInst::ICMP_EQ; Rep = Builder.CreateICmp(Pred, Rep, Zero); - Rep = ApplyX86MaskOn1BitsVec(Builder, Rep, Mask); + Rep = applyX86MaskOn1BitsVec(Builder, Rep, Mask); } else if (IsX86 && (Name.starts_with("avx512.mask.pbroadcast"))){ unsigned NumElts = cast(CI->getArgOperand(1)->getType()) ->getNumElements(); Rep = Builder.CreateVectorSplat(NumElts, CI->getArgOperand(0)); - Rep = EmitX86Select(Builder, CI->getArgOperand(2), Rep, + Rep = emitX86Select(Builder, CI->getArgOperand(2), Rep, CI->getArgOperand(1)); } else if (IsX86 && (Name.starts_with("avx512.kunpck"))) { unsigned NumElts = CI->getType()->getScalarSizeInBits(); @@ -2634,7 +2624,7 @@ void llvm::UpgradeIntrinsicCall(CallBase *CI, Function *NewFn) { Rep = Builder.CreateCall(Intrinsic::getDeclaration(F->getParent(), IID), { CI->getOperand(0), CI->getArgOperand(1) }); - Rep = ApplyX86MaskOn1BitsVec(Builder, Rep, CI->getArgOperand(2)); + Rep = applyX86MaskOn1BitsVec(Builder, Rep, CI->getArgOperand(2)); } else if (IsX86 && Name.starts_with("avx512.mask.fpclass.p")) { Type *OpTy = CI->getArgOperand(0)->getType(); unsigned VecWidth = OpTy->getPrimitiveSizeInBits(); @@ -2657,7 +2647,7 @@ void llvm::UpgradeIntrinsicCall(CallBase *CI, Function *NewFn) { Rep = Builder.CreateCall(Intrinsic::getDeclaration(F->getParent(), IID), { CI->getOperand(0), CI->getArgOperand(1) }); - Rep = ApplyX86MaskOn1BitsVec(Builder, Rep, CI->getArgOperand(2)); + Rep = applyX86MaskOn1BitsVec(Builder, Rep, CI->getArgOperand(2)); } else if (IsX86 && Name.starts_with("avx512.cmp.p")) { SmallVector Args(CI->args()); Type *OpTy = Args[0]->getType(); @@ -2700,7 +2690,7 @@ void llvm::UpgradeIntrinsicCall(CallBase *CI, Function *NewFn) { Value *Op = CI->getArgOperand(0); Value *Zero = llvm::Constant::getNullValue(Op->getType()); Rep = Builder.CreateICmp(ICmpInst::ICMP_SLT, Op, Zero); - Rep = ApplyX86MaskOn1BitsVec(Builder, Rep, nullptr); + Rep = applyX86MaskOn1BitsVec(Builder, Rep, nullptr); } else if(IsX86 && (Name == "ssse3.pabs.b.128" || Name == "ssse3.pabs.w.128" || Name == "ssse3.pabs.d.128" || @@ -2712,25 +2702,25 @@ void llvm::UpgradeIntrinsicCall(CallBase *CI, Function *NewFn) { Name == "sse41.pmaxsd" || Name.starts_with("avx2.pmaxs") || Name.starts_with("avx512.mask.pmaxs"))) { - Rep = UpgradeX86BinaryIntrinsics(Builder, *CI, Intrinsic::smax); + Rep = upgradeX86BinaryIntrinsics(Builder, *CI, Intrinsic::smax); } else if (IsX86 && (Name == "sse2.pmaxu.b" || Name == "sse41.pmaxuw" || Name == "sse41.pmaxud" || Name.starts_with("avx2.pmaxu") || Name.starts_with("avx512.mask.pmaxu"))) { - Rep = UpgradeX86BinaryIntrinsics(Builder, *CI, Intrinsic::umax); + Rep = upgradeX86BinaryIntrinsics(Builder, *CI, Intrinsic::umax); } else if (IsX86 && (Name == "sse41.pminsb" || Name == "sse2.pmins.w" || Name == "sse41.pminsd" || Name.starts_with("avx2.pmins") || Name.starts_with("avx512.mask.pmins"))) { - Rep = UpgradeX86BinaryIntrinsics(Builder, *CI, Intrinsic::smin); + Rep = upgradeX86BinaryIntrinsics(Builder, *CI, Intrinsic::smin); } else if (IsX86 && (Name == "sse2.pminu.b" || Name == "sse41.pminuw" || Name == "sse41.pminud" || Name.starts_with("avx2.pminu") || Name.starts_with("avx512.mask.pminu"))) { - Rep = UpgradeX86BinaryIntrinsics(Builder, *CI, Intrinsic::umin); + Rep = upgradeX86BinaryIntrinsics(Builder, *CI, Intrinsic::umin); } else if (IsX86 && (Name == "sse2.pmulu.dq" || Name == "avx2.pmulu.dq" || Name == "avx512.pmulu.dq.512" || @@ -2788,7 +2778,7 @@ void llvm::UpgradeIntrinsicCall(CallBase *CI, Function *NewFn) { } bool IsPS2PD = SrcTy->getElementType()->isFloatTy(); - bool IsUnsigned = (StringRef::npos != Name.find("cvtu")); + bool IsUnsigned = Name.contains("cvtu"); if (IsPS2PD) Rep = Builder.CreateFPExt(Rep, DstTy, "cvtps2pd"); else if (CI->arg_size() == 4 && @@ -2805,7 +2795,7 @@ void llvm::UpgradeIntrinsicCall(CallBase *CI, Function *NewFn) { } if (CI->arg_size() >= 3) - Rep = EmitX86Select(Builder, CI->getArgOperand(2), Rep, + Rep = emitX86Select(Builder, CI->getArgOperand(2), Rep, CI->getArgOperand(1)); } else if (IsX86 && (Name.starts_with("avx512.mask.vcvtph2ps.") || Name.starts_with("vcvtph2ps."))) { @@ -2821,13 +2811,13 @@ void llvm::UpgradeIntrinsicCall(CallBase *CI, Function *NewFn) { Rep, FixedVectorType::get(Type::getHalfTy(C), NumDstElts)); Rep = Builder.CreateFPExt(Rep, DstTy, "cvtph2ps"); if (CI->arg_size() >= 3) - Rep = EmitX86Select(Builder, CI->getArgOperand(2), Rep, + Rep = emitX86Select(Builder, CI->getArgOperand(2), Rep, CI->getArgOperand(1)); } else if (IsX86 && Name.starts_with("avx512.mask.load")) { // "avx512.mask.loadu." or "avx512.mask.load." bool Aligned = Name[16] != 'u'; // "avx512.mask.loadu". Rep = - UpgradeMaskedLoad(Builder, CI->getArgOperand(0), CI->getArgOperand(1), + upgradeMaskedLoad(Builder, CI->getArgOperand(0), CI->getArgOperand(1), CI->getArgOperand(2), Aligned); } else if (IsX86 && Name.starts_with("avx512.mask.expand.load.")) { auto *ResultTy = cast(CI->getType()); @@ -2968,12 +2958,12 @@ void llvm::UpgradeIntrinsicCall(CallBase *CI, Function *NewFn) { Value *SV = Builder.CreateShuffleVector(CI->getArgOperand(0), ShuffleMask); - bool DoSext = (StringRef::npos != Name.find("pmovsx")); + bool DoSext = Name.contains("pmovsx"); Rep = DoSext ? Builder.CreateSExt(SV, DstTy) : Builder.CreateZExt(SV, DstTy); // If there are 3 arguments, it's a masked intrinsic so we need a select. if (CI->arg_size() == 3) - Rep = EmitX86Select(Builder, CI->getArgOperand(2), Rep, + Rep = emitX86Select(Builder, CI->getArgOperand(2), Rep, CI->getArgOperand(1)); } else if (Name == "avx512.mask.pmov.qd.256" || Name == "avx512.mask.pmov.qd.512" || @@ -2981,7 +2971,7 @@ void llvm::UpgradeIntrinsicCall(CallBase *CI, Function *NewFn) { Name == "avx512.mask.pmov.wb.512") { Type *Ty = CI->getArgOperand(1)->getType(); Rep = Builder.CreateTrunc(CI->getArgOperand(0), Ty); - Rep = EmitX86Select(Builder, CI->getArgOperand(2), Rep, + Rep = emitX86Select(Builder, CI->getArgOperand(2), Rep, CI->getArgOperand(1)); } else if (IsX86 && (Name.starts_with("avx.vbroadcastf128") || Name == "avx2.vbroadcasti128")) { @@ -3017,7 +3007,7 @@ void llvm::UpgradeIntrinsicCall(CallBase *CI, Function *NewFn) { } Rep = Builder.CreateShuffleVector(CI->getArgOperand(0), CI->getArgOperand(1), ShuffleMask); - Rep = EmitX86Select(Builder, CI->getArgOperand(4), Rep, + Rep = emitX86Select(Builder, CI->getArgOperand(4), Rep, CI->getArgOperand(3)); }else if (IsX86 && (Name.starts_with("avx512.mask.broadcastf") || Name.starts_with("avx512.mask.broadcasti"))) { @@ -3034,7 +3024,7 @@ void llvm::UpgradeIntrinsicCall(CallBase *CI, Function *NewFn) { Rep = Builder.CreateShuffleVector(CI->getArgOperand(0), CI->getArgOperand(0), ShuffleMask); - Rep = EmitX86Select(Builder, CI->getArgOperand(2), Rep, + Rep = emitX86Select(Builder, CI->getArgOperand(2), Rep, CI->getArgOperand(1)); } else if (IsX86 && (Name.starts_with("avx2.pbroadcast") || Name.starts_with("avx2.vbroadcast") || @@ -3049,64 +3039,60 @@ void llvm::UpgradeIntrinsicCall(CallBase *CI, Function *NewFn) { Rep = Builder.CreateShuffleVector(Op, M); if (CI->arg_size() == 3) - Rep = EmitX86Select(Builder, CI->getArgOperand(2), Rep, + Rep = emitX86Select(Builder, CI->getArgOperand(2), Rep, CI->getArgOperand(1)); } else if (IsX86 && (Name.starts_with("sse2.padds.") || Name.starts_with("avx2.padds.") || Name.starts_with("avx512.padds.") || Name.starts_with("avx512.mask.padds."))) { - Rep = UpgradeX86BinaryIntrinsics(Builder, *CI, Intrinsic::sadd_sat); + Rep = upgradeX86BinaryIntrinsics(Builder, *CI, Intrinsic::sadd_sat); } else if (IsX86 && (Name.starts_with("sse2.psubs.") || Name.starts_with("avx2.psubs.") || Name.starts_with("avx512.psubs.") || Name.starts_with("avx512.mask.psubs."))) { - Rep = UpgradeX86BinaryIntrinsics(Builder, *CI, Intrinsic::ssub_sat); + Rep = upgradeX86BinaryIntrinsics(Builder, *CI, Intrinsic::ssub_sat); } else if (IsX86 && (Name.starts_with("sse2.paddus.") || Name.starts_with("avx2.paddus.") || Name.starts_with("avx512.mask.paddus."))) { - Rep = UpgradeX86BinaryIntrinsics(Builder, *CI, Intrinsic::uadd_sat); + Rep = upgradeX86BinaryIntrinsics(Builder, *CI, Intrinsic::uadd_sat); } else if (IsX86 && (Name.starts_with("sse2.psubus.") || Name.starts_with("avx2.psubus.") || Name.starts_with("avx512.mask.psubus."))) { - Rep = UpgradeX86BinaryIntrinsics(Builder, *CI, Intrinsic::usub_sat); + Rep = upgradeX86BinaryIntrinsics(Builder, *CI, Intrinsic::usub_sat); } else if (IsX86 && Name.starts_with("avx512.mask.palignr.")) { - Rep = UpgradeX86ALIGNIntrinsics(Builder, CI->getArgOperand(0), - CI->getArgOperand(1), - CI->getArgOperand(2), - CI->getArgOperand(3), - CI->getArgOperand(4), - false); + Rep = upgradeX86ALIGNIntrinsics( + Builder, CI->getArgOperand(0), CI->getArgOperand(1), + CI->getArgOperand(2), CI->getArgOperand(3), CI->getArgOperand(4), + false); } else if (IsX86 && Name.starts_with("avx512.mask.valign.")) { - Rep = UpgradeX86ALIGNIntrinsics(Builder, CI->getArgOperand(0), - CI->getArgOperand(1), - CI->getArgOperand(2), - CI->getArgOperand(3), - CI->getArgOperand(4), - true); + Rep = upgradeX86ALIGNIntrinsics( + Builder, CI->getArgOperand(0), CI->getArgOperand(1), + CI->getArgOperand(2), CI->getArgOperand(3), CI->getArgOperand(4), + true); } else if (IsX86 && (Name == "sse2.psll.dq" || Name == "avx2.psll.dq")) { // 128/256-bit shift left specified in bits. unsigned Shift = cast(CI->getArgOperand(1))->getZExtValue(); - Rep = UpgradeX86PSLLDQIntrinsics(Builder, CI->getArgOperand(0), + Rep = upgradeX86PSLLDQIntrinsics(Builder, CI->getArgOperand(0), Shift / 8); // Shift is in bits. } else if (IsX86 && (Name == "sse2.psrl.dq" || Name == "avx2.psrl.dq")) { // 128/256-bit shift right specified in bits. unsigned Shift = cast(CI->getArgOperand(1))->getZExtValue(); - Rep = UpgradeX86PSRLDQIntrinsics(Builder, CI->getArgOperand(0), + Rep = upgradeX86PSRLDQIntrinsics(Builder, CI->getArgOperand(0), Shift / 8); // Shift is in bits. } else if (IsX86 && (Name == "sse2.psll.dq.bs" || Name == "avx2.psll.dq.bs" || Name == "avx512.psll.dq.512")) { // 128/256/512-bit shift left specified in bytes. unsigned Shift = cast(CI->getArgOperand(1))->getZExtValue(); - Rep = UpgradeX86PSLLDQIntrinsics(Builder, CI->getArgOperand(0), Shift); + Rep = upgradeX86PSLLDQIntrinsics(Builder, CI->getArgOperand(0), Shift); } else if (IsX86 && (Name == "sse2.psrl.dq.bs" || Name == "avx2.psrl.dq.bs" || Name == "avx512.psrl.dq.512")) { // 128/256/512-bit shift right specified in bytes. unsigned Shift = cast(CI->getArgOperand(1))->getZExtValue(); - Rep = UpgradeX86PSRLDQIntrinsics(Builder, CI->getArgOperand(0), Shift); + Rep = upgradeX86PSRLDQIntrinsics(Builder, CI->getArgOperand(0), Shift); } else if (IsX86 && (Name == "sse41.pblendw" || Name.starts_with("sse41.blendp") || Name.starts_with("avx.blend.p") || @@ -3167,7 +3153,7 @@ void llvm::UpgradeIntrinsicCall(CallBase *CI, Function *NewFn) { // If the intrinsic has a mask operand, handle that. if (CI->arg_size() == 5) - Rep = EmitX86Select(Builder, CI->getArgOperand(4), Rep, + Rep = emitX86Select(Builder, CI->getArgOperand(4), Rep, CI->getArgOperand(3)); } else if (IsX86 && (Name.starts_with("avx.vextractf128.") || Name == "avx2.vextracti128" || @@ -3192,7 +3178,7 @@ void llvm::UpgradeIntrinsicCall(CallBase *CI, Function *NewFn) { // If the intrinsic has a mask operand, handle that. if (CI->arg_size() == 4) - Rep = EmitX86Select(Builder, CI->getArgOperand(3), Rep, + Rep = emitX86Select(Builder, CI->getArgOperand(3), Rep, CI->getArgOperand(2)); } else if (!IsX86 && Name == "stackprotectorcheck") { Rep = nullptr; @@ -3210,7 +3196,7 @@ void llvm::UpgradeIntrinsicCall(CallBase *CI, Function *NewFn) { Rep = Builder.CreateShuffleVector(Op0, Op0, Idxs); if (CI->arg_size() == 4) - Rep = EmitX86Select(Builder, CI->getArgOperand(3), Rep, + Rep = emitX86Select(Builder, CI->getArgOperand(3), Rep, CI->getArgOperand(2)); } else if (IsX86 && (Name.starts_with("avx.vperm2f128.") || Name == "avx2.vperm2i128")) { @@ -3270,7 +3256,7 @@ void llvm::UpgradeIntrinsicCall(CallBase *CI, Function *NewFn) { Rep = Builder.CreateShuffleVector(Op0, Op0, Idxs); if (CI->arg_size() == 4) - Rep = EmitX86Select(Builder, CI->getArgOperand(3), Rep, + Rep = emitX86Select(Builder, CI->getArgOperand(3), Rep, CI->getArgOperand(2)); } else if (IsX86 && (Name == "sse2.pshufl.w" || Name.starts_with("avx512.mask.pshufl.w."))) { @@ -3289,7 +3275,7 @@ void llvm::UpgradeIntrinsicCall(CallBase *CI, Function *NewFn) { Rep = Builder.CreateShuffleVector(Op0, Op0, Idxs); if (CI->arg_size() == 4) - Rep = EmitX86Select(Builder, CI->getArgOperand(3), Rep, + Rep = emitX86Select(Builder, CI->getArgOperand(3), Rep, CI->getArgOperand(2)); } else if (IsX86 && (Name == "sse2.pshufh.w" || Name.starts_with("avx512.mask.pshufh.w."))) { @@ -3308,7 +3294,7 @@ void llvm::UpgradeIntrinsicCall(CallBase *CI, Function *NewFn) { Rep = Builder.CreateShuffleVector(Op0, Op0, Idxs); if (CI->arg_size() == 4) - Rep = EmitX86Select(Builder, CI->getArgOperand(3), Rep, + Rep = emitX86Select(Builder, CI->getArgOperand(3), Rep, CI->getArgOperand(2)); } else if (IsX86 && Name.starts_with("avx512.mask.shuf.p")) { Value *Op0 = CI->getArgOperand(0); @@ -3333,7 +3319,7 @@ void llvm::UpgradeIntrinsicCall(CallBase *CI, Function *NewFn) { Rep = Builder.CreateShuffleVector(Op0, Op1, Idxs); - Rep = EmitX86Select(Builder, CI->getArgOperand(4), Rep, + Rep = emitX86Select(Builder, CI->getArgOperand(4), Rep, CI->getArgOperand(3)); } else if (IsX86 && (Name.starts_with("avx512.mask.movddup") || Name.starts_with("avx512.mask.movshdup") || @@ -3355,7 +3341,7 @@ void llvm::UpgradeIntrinsicCall(CallBase *CI, Function *NewFn) { Rep = Builder.CreateShuffleVector(Op0, Op0, Idxs); - Rep = EmitX86Select(Builder, CI->getArgOperand(2), Rep, + Rep = emitX86Select(Builder, CI->getArgOperand(2), Rep, CI->getArgOperand(1)); } else if (IsX86 && (Name.starts_with("avx512.mask.punpckl") || Name.starts_with("avx512.mask.unpckl."))) { @@ -3371,7 +3357,7 @@ void llvm::UpgradeIntrinsicCall(CallBase *CI, Function *NewFn) { Rep = Builder.CreateShuffleVector(Op0, Op1, Idxs); - Rep = EmitX86Select(Builder, CI->getArgOperand(3), Rep, + Rep = emitX86Select(Builder, CI->getArgOperand(3), Rep, CI->getArgOperand(2)); } else if (IsX86 && (Name.starts_with("avx512.mask.punpckh") || Name.starts_with("avx512.mask.unpckh."))) { @@ -3387,7 +3373,7 @@ void llvm::UpgradeIntrinsicCall(CallBase *CI, Function *NewFn) { Rep = Builder.CreateShuffleVector(Op0, Op1, Idxs); - Rep = EmitX86Select(Builder, CI->getArgOperand(3), Rep, + Rep = emitX86Select(Builder, CI->getArgOperand(3), Rep, CI->getArgOperand(2)); } else if (IsX86 && (Name.starts_with("avx512.mask.and.") || Name.starts_with("avx512.mask.pand."))) { @@ -3396,7 +3382,7 @@ void llvm::UpgradeIntrinsicCall(CallBase *CI, Function *NewFn) { Rep = Builder.CreateAnd(Builder.CreateBitCast(CI->getArgOperand(0), ITy), Builder.CreateBitCast(CI->getArgOperand(1), ITy)); Rep = Builder.CreateBitCast(Rep, FTy); - Rep = EmitX86Select(Builder, CI->getArgOperand(3), Rep, + Rep = emitX86Select(Builder, CI->getArgOperand(3), Rep, CI->getArgOperand(2)); } else if (IsX86 && (Name.starts_with("avx512.mask.andn.") || Name.starts_with("avx512.mask.pandn."))) { @@ -3406,7 +3392,7 @@ void llvm::UpgradeIntrinsicCall(CallBase *CI, Function *NewFn) { Rep = Builder.CreateAnd(Rep, Builder.CreateBitCast(CI->getArgOperand(1), ITy)); Rep = Builder.CreateBitCast(Rep, FTy); - Rep = EmitX86Select(Builder, CI->getArgOperand(3), Rep, + Rep = emitX86Select(Builder, CI->getArgOperand(3), Rep, CI->getArgOperand(2)); } else if (IsX86 && (Name.starts_with("avx512.mask.or.") || Name.starts_with("avx512.mask.por."))) { @@ -3415,7 +3401,7 @@ void llvm::UpgradeIntrinsicCall(CallBase *CI, Function *NewFn) { Rep = Builder.CreateOr(Builder.CreateBitCast(CI->getArgOperand(0), ITy), Builder.CreateBitCast(CI->getArgOperand(1), ITy)); Rep = Builder.CreateBitCast(Rep, FTy); - Rep = EmitX86Select(Builder, CI->getArgOperand(3), Rep, + Rep = emitX86Select(Builder, CI->getArgOperand(3), Rep, CI->getArgOperand(2)); } else if (IsX86 && (Name.starts_with("avx512.mask.xor.") || Name.starts_with("avx512.mask.pxor."))) { @@ -3424,19 +3410,19 @@ void llvm::UpgradeIntrinsicCall(CallBase *CI, Function *NewFn) { Rep = Builder.CreateXor(Builder.CreateBitCast(CI->getArgOperand(0), ITy), Builder.CreateBitCast(CI->getArgOperand(1), ITy)); Rep = Builder.CreateBitCast(Rep, FTy); - Rep = EmitX86Select(Builder, CI->getArgOperand(3), Rep, + Rep = emitX86Select(Builder, CI->getArgOperand(3), Rep, CI->getArgOperand(2)); } else if (IsX86 && Name.starts_with("avx512.mask.padd.")) { Rep = Builder.CreateAdd(CI->getArgOperand(0), CI->getArgOperand(1)); - Rep = EmitX86Select(Builder, CI->getArgOperand(3), Rep, + Rep = emitX86Select(Builder, CI->getArgOperand(3), Rep, CI->getArgOperand(2)); } else if (IsX86 && Name.starts_with("avx512.mask.psub.")) { Rep = Builder.CreateSub(CI->getArgOperand(0), CI->getArgOperand(1)); - Rep = EmitX86Select(Builder, CI->getArgOperand(3), Rep, + Rep = emitX86Select(Builder, CI->getArgOperand(3), Rep, CI->getArgOperand(2)); } else if (IsX86 && Name.starts_with("avx512.mask.pmull.")) { Rep = Builder.CreateMul(CI->getArgOperand(0), CI->getArgOperand(1)); - Rep = EmitX86Select(Builder, CI->getArgOperand(3), Rep, + Rep = emitX86Select(Builder, CI->getArgOperand(3), Rep, CI->getArgOperand(2)); } else if (IsX86 && Name.starts_with("avx512.mask.add.p")) { if (Name.ends_with(".512")) { @@ -3452,7 +3438,7 @@ void llvm::UpgradeIntrinsicCall(CallBase *CI, Function *NewFn) { } else { Rep = Builder.CreateFAdd(CI->getArgOperand(0), CI->getArgOperand(1)); } - Rep = EmitX86Select(Builder, CI->getArgOperand(3), Rep, + Rep = emitX86Select(Builder, CI->getArgOperand(3), Rep, CI->getArgOperand(2)); } else if (IsX86 && Name.starts_with("avx512.mask.div.p")) { if (Name.ends_with(".512")) { @@ -3468,7 +3454,7 @@ void llvm::UpgradeIntrinsicCall(CallBase *CI, Function *NewFn) { } else { Rep = Builder.CreateFDiv(CI->getArgOperand(0), CI->getArgOperand(1)); } - Rep = EmitX86Select(Builder, CI->getArgOperand(3), Rep, + Rep = emitX86Select(Builder, CI->getArgOperand(3), Rep, CI->getArgOperand(2)); } else if (IsX86 && Name.starts_with("avx512.mask.mul.p")) { if (Name.ends_with(".512")) { @@ -3484,7 +3470,7 @@ void llvm::UpgradeIntrinsicCall(CallBase *CI, Function *NewFn) { } else { Rep = Builder.CreateFMul(CI->getArgOperand(0), CI->getArgOperand(1)); } - Rep = EmitX86Select(Builder, CI->getArgOperand(3), Rep, + Rep = emitX86Select(Builder, CI->getArgOperand(3), Rep, CI->getArgOperand(2)); } else if (IsX86 && Name.starts_with("avx512.mask.sub.p")) { if (Name.ends_with(".512")) { @@ -3500,7 +3486,7 @@ void llvm::UpgradeIntrinsicCall(CallBase *CI, Function *NewFn) { } else { Rep = Builder.CreateFSub(CI->getArgOperand(0), CI->getArgOperand(1)); } - Rep = EmitX86Select(Builder, CI->getArgOperand(3), Rep, + Rep = emitX86Select(Builder, CI->getArgOperand(3), Rep, CI->getArgOperand(2)); } else if (IsX86 && (Name.starts_with("avx512.mask.max.p") || Name.starts_with("avx512.mask.min.p")) && @@ -3516,14 +3502,14 @@ void llvm::UpgradeIntrinsicCall(CallBase *CI, Function *NewFn) { Rep = Builder.CreateCall(Intrinsic::getDeclaration(F->getParent(), IID), { CI->getArgOperand(0), CI->getArgOperand(1), CI->getArgOperand(4) }); - Rep = EmitX86Select(Builder, CI->getArgOperand(3), Rep, + Rep = emitX86Select(Builder, CI->getArgOperand(3), Rep, CI->getArgOperand(2)); } else if (IsX86 && Name.starts_with("avx512.mask.lzcnt.")) { Rep = Builder.CreateCall(Intrinsic::getDeclaration(F->getParent(), Intrinsic::ctlz, CI->getType()), { CI->getArgOperand(0), Builder.getInt1(false) }); - Rep = EmitX86Select(Builder, CI->getArgOperand(2), Rep, + Rep = emitX86Select(Builder, CI->getArgOperand(2), Rep, CI->getArgOperand(1)); } else if (IsX86 && Name.starts_with("avx512.mask.psll")) { bool IsImmediate = Name[16] == 'i' || @@ -3592,7 +3578,7 @@ void llvm::UpgradeIntrinsicCall(CallBase *CI, Function *NewFn) { llvm_unreachable("Unexpected size"); } - Rep = UpgradeX86MaskedShift(Builder, *CI, IID); + Rep = upgradeX86MaskedShift(Builder, *CI, IID); } else if (IsX86 && Name.starts_with("avx512.mask.psrl")) { bool IsImmediate = Name[16] == 'i' || (Name.size() > 18 && Name[18] == 'i'); @@ -3660,7 +3646,7 @@ void llvm::UpgradeIntrinsicCall(CallBase *CI, Function *NewFn) { llvm_unreachable("Unexpected size"); } - Rep = UpgradeX86MaskedShift(Builder, *CI, IID); + Rep = upgradeX86MaskedShift(Builder, *CI, IID); } else if (IsX86 && Name.starts_with("avx512.mask.psra")) { bool IsImmediate = Name[16] == 'i' || (Name.size() > 18 && Name[18] == 'i'); @@ -3726,11 +3712,11 @@ void llvm::UpgradeIntrinsicCall(CallBase *CI, Function *NewFn) { llvm_unreachable("Unexpected size"); } - Rep = UpgradeX86MaskedShift(Builder, *CI, IID); + Rep = upgradeX86MaskedShift(Builder, *CI, IID); } else if (IsX86 && Name.starts_with("avx512.mask.move.s")) { Rep = upgradeMaskedMove(Builder, *CI); } else if (IsX86 && Name.starts_with("avx512.cvtmask2")) { - Rep = UpgradeMaskToInt(Builder, *CI); + Rep = upgradeMaskToInt(Builder, *CI); } else if (IsX86 && Name.ends_with(".movntdqa")) { MDNode *Node = MDNode::get( C, ConstantAsMetadata::get(ConstantInt::get(Type::getInt32Ty(C), 1))); @@ -3846,8 +3832,7 @@ void llvm::UpgradeIntrinsicCall(CallBase *CI, Function *NewFn) { PassThru = Builder.CreateExtractElement(CI->getArgOperand(2), (uint64_t)0); - Rep = EmitX86ScalarSelect(Builder, CI->getArgOperand(3), - Rep, PassThru); + Rep = emitX86ScalarSelect(Builder, CI->getArgOperand(3), Rep, PassThru); Rep = Builder.CreateInsertElement(CI->getArgOperand(IsMask3 ? 2 : 0), Rep, (uint64_t)0); } else if (IsX86 && (Name.starts_with("avx512.mask.vfmadd.p") || @@ -3898,7 +3883,7 @@ void llvm::UpgradeIntrinsicCall(CallBase *CI, Function *NewFn) { IsMask3 ? CI->getArgOperand(2) : CI->getArgOperand(0); - Rep = EmitX86Select(Builder, CI->getArgOperand(3), Rep, PassThru); + Rep = emitX86Select(Builder, CI->getArgOperand(3), Rep, PassThru); } else if (IsX86 && Name.starts_with("fma.vfmsubadd.p")) { unsigned VecWidth = CI->getType()->getPrimitiveSizeInBits(); unsigned EltWidth = CI->getType()->getScalarSizeInBits(); @@ -3969,7 +3954,7 @@ void llvm::UpgradeIntrinsicCall(CallBase *CI, Function *NewFn) { IsMask3 ? CI->getArgOperand(2) : CI->getArgOperand(0); - Rep = EmitX86Select(Builder, CI->getArgOperand(3), Rep, PassThru); + Rep = emitX86Select(Builder, CI->getArgOperand(3), Rep, PassThru); } else if (IsX86 && (Name.starts_with("avx512.mask.pternlog.") || Name.starts_with("avx512.maskz.pternlog."))) { bool ZeroMask = Name[11] == 'z'; @@ -3997,7 +3982,7 @@ void llvm::UpgradeIntrinsicCall(CallBase *CI, Function *NewFn) { Args); Value *PassThru = ZeroMask ? ConstantAggregateZero::get(CI->getType()) : CI->getArgOperand(0); - Rep = EmitX86Select(Builder, CI->getArgOperand(4), Rep, PassThru); + Rep = emitX86Select(Builder, CI->getArgOperand(4), Rep, PassThru); } else if (IsX86 && (Name.starts_with("avx512.mask.vpmadd52") || Name.starts_with("avx512.maskz.vpmadd52"))) { bool ZeroMask = Name[11] == 'z'; @@ -4025,13 +4010,13 @@ void llvm::UpgradeIntrinsicCall(CallBase *CI, Function *NewFn) { Args); Value *PassThru = ZeroMask ? ConstantAggregateZero::get(CI->getType()) : CI->getArgOperand(0); - Rep = EmitX86Select(Builder, CI->getArgOperand(3), Rep, PassThru); + Rep = emitX86Select(Builder, CI->getArgOperand(3), Rep, PassThru); } else if (IsX86 && (Name.starts_with("avx512.mask.vpermi2var.") || Name.starts_with("avx512.mask.vpermt2var.") || Name.starts_with("avx512.maskz.vpermt2var."))) { bool ZeroMask = Name[11] == 'z'; bool IndexForm = Name[17] == 'i'; - Rep = UpgradeX86VPERMT2Intrinsics(Builder, *CI, ZeroMask, IndexForm); + Rep = upgradeX86VPERMT2Intrinsics(Builder, *CI, ZeroMask, IndexForm); } else if (IsX86 && (Name.starts_with("avx512.mask.vpdpbusd.") || Name.starts_with("avx512.maskz.vpdpbusd.") || Name.starts_with("avx512.mask.vpdpbusds.") || @@ -4061,7 +4046,7 @@ void llvm::UpgradeIntrinsicCall(CallBase *CI, Function *NewFn) { Args); Value *PassThru = ZeroMask ? ConstantAggregateZero::get(CI->getType()) : CI->getArgOperand(0); - Rep = EmitX86Select(Builder, CI->getArgOperand(3), Rep, PassThru); + Rep = emitX86Select(Builder, CI->getArgOperand(3), Rep, PassThru); } else if (IsX86 && (Name.starts_with("avx512.mask.vpdpwssd.") || Name.starts_with("avx512.maskz.vpdpwssd.") || Name.starts_with("avx512.mask.vpdpwssds.") || @@ -4091,7 +4076,7 @@ void llvm::UpgradeIntrinsicCall(CallBase *CI, Function *NewFn) { Args); Value *PassThru = ZeroMask ? ConstantAggregateZero::get(CI->getType()) : CI->getArgOperand(0); - Rep = EmitX86Select(Builder, CI->getArgOperand(3), Rep, PassThru); + Rep = emitX86Select(Builder, CI->getArgOperand(3), Rep, PassThru); } else if (IsX86 && (Name == "addcarryx.u32" || Name == "addcarryx.u64" || Name == "addcarry.u32" || Name == "addcarry.u64" || Name == "subborrow.u32" || Name == "subborrow.u64")) { @@ -4140,24 +4125,26 @@ void llvm::UpgradeIntrinsicCall(CallBase *CI, Function *NewFn) { Value *Val = CI->getArgOperand(1); Rep = Builder.CreateAtomicRMW(AtomicRMWInst::FAdd, Ptr, Val, MaybeAlign(), AtomicOrdering::SequentiallyConsistent); - } else if (IsNVVM && (Name == "max.i" || Name == "max.ll" || - Name == "max.ui" || Name == "max.ull")) { + } else if (IsNVVM && Name.consume_front("max.") && + (Name == "s" || Name == "i" || Name == "ll" || Name == "us" || + Name == "ui" || Name == "ull")) { Value *Arg0 = CI->getArgOperand(0); Value *Arg1 = CI->getArgOperand(1); - Value *Cmp = Name.ends_with(".ui") || Name.ends_with(".ull") + Value *Cmp = Name.starts_with("u") ? Builder.CreateICmpUGE(Arg0, Arg1, "max.cond") : Builder.CreateICmpSGE(Arg0, Arg1, "max.cond"); Rep = Builder.CreateSelect(Cmp, Arg0, Arg1, "max"); - } else if (IsNVVM && (Name == "min.i" || Name == "min.ll" || - Name == "min.ui" || Name == "min.ull")) { + } else if (IsNVVM && Name.consume_front("min.") && + (Name == "s" || Name == "i" || Name == "ll" || Name == "us" || + Name == "ui" || Name == "ull")) { Value *Arg0 = CI->getArgOperand(0); Value *Arg1 = CI->getArgOperand(1); - Value *Cmp = Name.ends_with(".ui") || Name.ends_with(".ull") + Value *Cmp = Name.starts_with("u") ? Builder.CreateICmpULE(Arg0, Arg1, "min.cond") : Builder.CreateICmpSLE(Arg0, Arg1, "min.cond"); Rep = Builder.CreateSelect(Cmp, Arg0, Arg1, "min"); } else if (IsNVVM && Name == "clz.ll") { - // llvm.nvvm.clz.ll returns an i32, but llvm.ctlz.i64 and returns an i64. + // llvm.nvvm.clz.ll returns an i32, but llvm.ctlz.i64 returns an i64. Value *Arg = CI->getArgOperand(0); Value *Ctlz = Builder.CreateCall( Intrinsic::getDeclaration(F->getParent(), Intrinsic::ctlz, @@ -4165,7 +4152,7 @@ void llvm::UpgradeIntrinsicCall(CallBase *CI, Function *NewFn) { {Arg, Builder.getFalse()}, "ctlz"); Rep = Builder.CreateTrunc(Ctlz, Builder.getInt32Ty(), "ctlz.trunc"); } else if (IsNVVM && Name == "popc.ll") { - // llvm.nvvm.popc.ll returns an i32, but llvm.ctpop.i64 and returns an + // llvm.nvvm.popc.ll returns an i32, but llvm.ctpop.i64 returns an // i64. Value *Arg = CI->getArgOperand(0); Value *Popc = Builder.CreateCall( @@ -4181,7 +4168,7 @@ void llvm::UpgradeIntrinsicCall(CallBase *CI, Function *NewFn) { {Builder.getFloatTy()}), CI->getArgOperand(0), "h2f"); } else { - Intrinsic::ID IID = ShouldUpgradeNVPTXBF16Intrinsic(Name); + Intrinsic::ID IID = shouldUpgradeNVPTXBF16Intrinsic(Name); if (IID != Intrinsic::not_intrinsic && !F->getReturnType()->getScalarType()->isBFloatTy()) { rename(F); @@ -4202,9 +4189,9 @@ void llvm::UpgradeIntrinsicCall(CallBase *CI, Function *NewFn) { } } } else if (IsARM) { - Rep = UpgradeARMIntrinsicCall(Name, CI, F, Builder); + Rep = upgradeARMIntrinsicCall(Name, CI, F, Builder); } else if (IsAMDGCN) { - Rep = UpgradeAMDGCNIntrinsicCall(Name, CI, F, Builder); + Rep = upgradeAMDGCNIntrinsicCall(Name, CI, F, Builder); } else { llvm_unreachable("Unknown function for CallBase upgrade."); } @@ -4623,7 +4610,7 @@ void llvm::UpgradeIntrinsicCall(CallBase *CI, Function *NewFn) { Args[3] = getX86MaskVec(Builder, Args[3], NumElts); NewCall = Builder.CreateCall(NewFn, Args); - Value *Res = ApplyX86MaskOn1BitsVec(Builder, NewCall, nullptr); + Value *Res = applyX86MaskOn1BitsVec(Builder, NewCall, nullptr); NewCall->takeName(CI); CI->replaceAllUsesWith(Res); @@ -4832,7 +4819,7 @@ bool llvm::UpgradeDebugInfo(Module &M) { /// This checks for objc retain release marker which should be upgraded. It /// returns true if module is modified. -static bool UpgradeRetainReleaseMarker(Module &M) { +static bool upgradeRetainReleaseMarker(Module &M) { bool Changed = false; const char *MarkerKey = "clang.arc.retainAutoreleasedReturnValueMarker"; NamedMDNode *ModRetainReleaseMarker = M.getNamedMetadata(MarkerKey); @@ -4931,7 +4918,7 @@ void llvm::UpgradeARCRuntime(Module &M) { // Upgrade the retain release marker. If there is no need to upgrade // the marker, that means either the module is already new enough to contain // new intrinsics or it is not ARC. There is no need to upgrade runtime call. - if (!UpgradeRetainReleaseMarker(M)) + if (!upgradeRetainReleaseMarker(M)) return; std::pair RuntimeFuncs[] = { diff --git a/llvm/lib/IR/BasicBlock.cpp b/llvm/lib/IR/BasicBlock.cpp index 03b74b0480f..dca52832838 100644 --- a/llvm/lib/IR/BasicBlock.cpp +++ b/llvm/lib/IR/BasicBlock.cpp @@ -74,9 +74,6 @@ void BasicBlock::convertToNewDbgValues() { for (Instruction &I : make_early_inc_range(InstList)) { assert(!I.DbgMarker && "DbgMarker already set on old-format instrs?"); if (DbgVariableIntrinsic *DVI = dyn_cast(&I)) { - if (isa(DVI)) - continue; - // Convert this dbg.value to a DPValue. DPValue *Value = new DPValue(DVI); DPVals.push_back(Value); @@ -240,12 +237,12 @@ void BasicBlock::insertInto(Function *NewParent, BasicBlock *InsertBefore) { assert(NewParent && "Expected a parent"); assert(!Parent && "Already has a parent"); - setIsNewDbgInfoFormat(NewParent->IsNewDbgInfoFormat); - if (InsertBefore) NewParent->insert(InsertBefore->getIterator(), this); else NewParent->insert(NewParent->end(), this); + + setIsNewDbgInfoFormat(NewParent->IsNewDbgInfoFormat); } BasicBlock::~BasicBlock() { @@ -824,9 +821,15 @@ void BasicBlock::spliceDebugInfoEmptyBlock(BasicBlock::iterator Dest, // There are instructions in this block; if the First iterator was // with begin() / getFirstInsertionPt() then the caller intended debug-info - // at the start of the block to be transferred. - if (!Src->empty() && First == Src->begin() && ReadFromHead) - Dest->DbgMarker->absorbDebugValues(*First->DbgMarker, InsertAtHead); + // at the start of the block to be transferred. Return otherwise. + if (Src->empty() || First != Src->begin() || !ReadFromHead) + return; + + // Is there actually anything to transfer? + if (!First->hasDbgValues()) + return; + + createMarker(Dest)->absorbDebugValues(*First->DbgMarker, InsertAtHead); return; } diff --git a/llvm/lib/IR/ConstantFold.cpp b/llvm/lib/IR/ConstantFold.cpp index 7fdc35e7fca..034e397bc69 100644 --- a/llvm/lib/IR/ConstantFold.cpp +++ b/llvm/lib/IR/ConstantFold.cpp @@ -679,15 +679,16 @@ Constant *llvm::ConstantFoldBinaryInstruction(unsigned Opcode, Constant *C1, // Simplify BinOps with their identity values first. They are no-ops and we // can always return the other value, including undef or poison values. - // FIXME: remove unnecessary duplicated identity patterns below. - // FIXME: Use AllowRHSConstant with getBinOpIdentity to handle additional ops, - // like X << 0 = X. - Constant *Identity = ConstantExpr::getBinOpIdentity(Opcode, C1->getType()); - if (Identity) { + if (Constant *Identity = ConstantExpr::getBinOpIdentity( + Opcode, C1->getType(), /*AllowRHSIdentity*/ false)) { if (C1 == Identity) return C2; if (C2 == Identity) return C1; + } else if (Constant *Identity = ConstantExpr::getBinOpIdentity( + Opcode, C1->getType(), /*AllowRHSIdentity*/ true)) { + if (C2 == Identity) + return C1; } // Binary operations propagate poison. @@ -734,9 +735,6 @@ Constant *llvm::ConstantFoldBinaryInstruction(unsigned Opcode, Constant *C1, // X / 0 -> poison if (match(C2, m_CombineOr(m_Undef(), m_Zero()))) return PoisonValue::get(C2->getType()); - // undef / 1 -> undef - if (match(C2, m_One())) - return C1; // undef / X -> 0 otherwise return Constant::getNullValue(C1->getType()); case Instruction::URem: @@ -755,18 +753,12 @@ Constant *llvm::ConstantFoldBinaryInstruction(unsigned Opcode, Constant *C1, // X >>l undef -> poison if (isa(C2)) return PoisonValue::get(C2->getType()); - // undef >>l 0 -> undef - if (match(C2, m_Zero())) - return C1; // undef >>l X -> 0 return Constant::getNullValue(C1->getType()); case Instruction::AShr: // X >>a undef -> poison if (isa(C2)) return PoisonValue::get(C2->getType()); - // undef >>a 0 -> undef - if (match(C2, m_Zero())) - return C1; // TODO: undef >>a X -> poison if the shift is exact // undef >>a X -> 0 return Constant::getNullValue(C1->getType()); @@ -774,9 +766,6 @@ Constant *llvm::ConstantFoldBinaryInstruction(unsigned Opcode, Constant *C1, // X << undef -> undef if (isa(C2)) return PoisonValue::get(C2->getType()); - // undef << 0 -> undef - if (match(C2, m_Zero())) - return C1; // undef << X -> 0 return Constant::getNullValue(C1->getType()); case Instruction::FSub: @@ -810,21 +799,12 @@ Constant *llvm::ConstantFoldBinaryInstruction(unsigned Opcode, Constant *C1, // Handle simplifications when the RHS is a constant int. if (ConstantInt *CI2 = dyn_cast(C2)) { switch (Opcode) { - case Instruction::Add: - if (CI2->isZero()) return C1; // X + 0 == X - break; - case Instruction::Sub: - if (CI2->isZero()) return C1; // X - 0 == X - break; case Instruction::Mul: - if (CI2->isZero()) return C2; // X * 0 == 0 - if (CI2->isOne()) - return C1; // X * 1 == X + if (CI2->isZero()) + return C2; // X * 0 == 0 break; case Instruction::UDiv: case Instruction::SDiv: - if (CI2->isOne()) - return C1; // X / 1 == X if (CI2->isZero()) return PoisonValue::get(CI2->getType()); // X / 0 == poison break; @@ -836,9 +816,8 @@ Constant *llvm::ConstantFoldBinaryInstruction(unsigned Opcode, Constant *C1, return PoisonValue::get(CI2->getType()); // X % 0 == poison break; case Instruction::And: - if (CI2->isZero()) return C2; // X & 0 == 0 - if (CI2->isMinusOne()) - return C1; // X & -1 == X + if (CI2->isZero()) + return C2; // X & 0 == 0 if (ConstantExpr *CE1 = dyn_cast(C1)) { // If and'ing the address of a global with a constant, fold it. @@ -880,16 +859,14 @@ Constant *llvm::ConstantFoldBinaryInstruction(unsigned Opcode, Constant *C1, } break; case Instruction::Or: - if (CI2->isZero()) return C1; // X | 0 == X if (CI2->isMinusOne()) - return C2; // X | -1 == -1 + return C2; // X | -1 == -1 break; case Instruction::Xor: - if (CI2->isZero()) return C1; // X ^ 0 == X - if (ConstantExpr *CE1 = dyn_cast(C1)) { switch (CE1->getOpcode()) { - default: break; + default: + break; case Instruction::ICmp: case Instruction::FCmp: // cmp pred ^ true -> cmp !pred diff --git a/llvm/lib/IR/DebugInfo.cpp b/llvm/lib/IR/DebugInfo.cpp index c6dc42e8ac8..d8c1b0d534f 100644 --- a/llvm/lib/IR/DebugInfo.cpp +++ b/llvm/lib/IR/DebugInfo.cpp @@ -44,6 +44,42 @@ using namespace llvm; using namespace llvm::at; using namespace llvm::dwarf; +TinyPtrVector llvm::findDbgDeclares(Value *V) { + // This function is hot. Check whether the value has any metadata to avoid a + // DenseMap lookup. + if (!V->isUsedByMetadata()) + return {}; + auto *L = LocalAsMetadata::getIfExists(V); + if (!L) + return {}; + auto *MDV = MetadataAsValue::getIfExists(V->getContext(), L); + if (!MDV) + return {}; + + TinyPtrVector Declares; + for (User *U : MDV->users()) + if (auto *DDI = dyn_cast(U)) + Declares.push_back(DDI); + + return Declares; +} +TinyPtrVector llvm::findDPVDeclares(Value *V) { + // This function is hot. Check whether the value has any metadata to avoid a + // DenseMap lookup. + if (!V->isUsedByMetadata()) + return {}; + auto *L = LocalAsMetadata::getIfExists(V); + if (!L) + return {}; + + TinyPtrVector Declares; + for (DPValue *DPV : L->getAllDPValueUsers()) + if (DPV->getType() == DPValue::LocationType::Declare) + Declares.push_back(DPV); + + return Declares; +} + template static void findDbgIntrinsics(SmallVectorImpl &Result, Value *V, @@ -97,12 +133,6 @@ static void findDbgIntrinsics(SmallVectorImpl &Result, Value *V, } } -void llvm::findDbgDeclares(SmallVectorImpl &DbgUsers, - Value *V, SmallVectorImpl *DPValues) { - findDbgIntrinsics(DbgUsers, V, - DPValues); -} - void llvm::findDbgValues(SmallVectorImpl &DbgValues, Value *V, SmallVectorImpl *DPValues) { findDbgIntrinsics(DbgValues, V, @@ -133,6 +163,18 @@ DebugLoc llvm::getDebugValueLoc(DbgVariableIntrinsic *DII) { return DILocation::get(DII->getContext(), 0, 0, Scope, InlinedAt); } +DebugLoc llvm::getDebugValueLoc(DPValue *DPV) { + // Original dbg.declare must have a location. + const DebugLoc &DeclareLoc = DPV->getDebugLoc(); + MDNode *Scope = DeclareLoc.getScope(); + DILocation *InlinedAt = DeclareLoc.getInlinedAt(); + // Because no machine insts can come from debug intrinsics, only the scope + // and inlinedAt is significant. Zero line numbers are used in case this + // DebugLoc leaks into any adjacent instructions. Produce an unknown location + // with the correct scope / inlinedAt fields. + return DILocation::get(DPV->getContext(), 0, 0, Scope, InlinedAt); +} + //===----------------------------------------------------------------------===// // DebugInfoFinder implementations. //===----------------------------------------------------------------------===// @@ -850,6 +892,9 @@ bool llvm::stripNonLineTableDebugInfo(Module &M) { // Strip heapallocsite attachments, they point into the DIType system. if (I.hasMetadataOtherThanDebugLoc()) I.setMetadata("heapallocsite", nullptr); + + // Strip any DPValues attached. + I.dropDbgValues(); } } } @@ -1749,21 +1794,17 @@ AssignmentMarkerRange at::getAssignmentMarkers(DIAssignID *ID) { void at::deleteAssignmentMarkers(const Instruction *Inst) { auto Range = getAssignmentMarkers(Inst); - if (Range.empty()) + SmallVector DPVAssigns = getDPVAssignmentMarkers(Inst); + if (Range.empty() && DPVAssigns.empty()) return; SmallVector ToDelete(Range.begin(), Range.end()); for (auto *DAI : ToDelete) DAI->eraseFromParent(); + for (auto *DPV : DPVAssigns) + DPV->eraseFromParent(); } void at::RAUW(DIAssignID *Old, DIAssignID *New) { - // Replace MetadataAsValue uses. - if (auto *OldIDAsValue = - MetadataAsValue::getIfExists(Old->getContext(), Old)) { - auto *NewIDAsValue = MetadataAsValue::get(Old->getContext(), New); - OldIDAsValue->replaceAllUsesWith(NewIDAsValue); - } - // Replace attachments. AssignmentInstRange InstRange = getAssignmentInsts(Old); // Use intermediate storage for the instruction ptrs because the @@ -1772,12 +1813,18 @@ void at::RAUW(DIAssignID *Old, DIAssignID *New) { SmallVector InstVec(InstRange.begin(), InstRange.end()); for (auto *I : InstVec) I->setMetadata(LLVMContext::MD_DIAssignID, New); + + Old->replaceAllUsesWith(New); } void at::deleteAll(Function *F) { SmallVector ToDelete; + SmallVector DPToDelete; for (BasicBlock &BB : *F) { for (Instruction &I : BB) { + for (auto &DPV : I.getDbgValueRange()) + if (DPV.isDbgAssign()) + DPToDelete.push_back(&DPV); if (auto *DAI = dyn_cast(&I)) ToDelete.push_back(DAI); else @@ -1786,11 +1833,38 @@ void at::deleteAll(Function *F) { } for (auto *DAI : ToDelete) DAI->eraseFromParent(); + for (auto *DPV : DPToDelete) + DPV->eraseFromParent(); } -bool at::calculateFragmentIntersect( +/// Get the FragmentInfo for the variable if it exists, otherwise return a +/// FragmentInfo that covers the entire variable if the variable size is +/// known, otherwise return a zero-sized fragment. +static DIExpression::FragmentInfo +getFragmentOrEntireVariable(const DPValue *DPV) { + DIExpression::FragmentInfo VariableSlice(0, 0); + // Get the fragment or variable size, or zero. + if (auto Sz = DPV->getFragmentSizeInBits()) + VariableSlice.SizeInBits = *Sz; + if (auto Frag = DPV->getExpression()->getFragmentInfo()) + VariableSlice.OffsetInBits = Frag->OffsetInBits; + return VariableSlice; +} + +static DIExpression::FragmentInfo +getFragmentOrEntireVariable(const DbgVariableIntrinsic *DVI) { + DIExpression::FragmentInfo VariableSlice(0, 0); + // Get the fragment or variable size, or zero. + if (auto Sz = DVI->getFragmentSizeInBits()) + VariableSlice.SizeInBits = *Sz; + if (auto Frag = DVI->getExpression()->getFragmentInfo()) + VariableSlice.OffsetInBits = Frag->OffsetInBits; + return VariableSlice; +} +template +bool calculateFragmentIntersectImpl( const DataLayout &DL, const Value *Dest, uint64_t SliceOffsetInBits, - uint64_t SliceSizeInBits, const DbgAssignIntrinsic *DAI, + uint64_t SliceSizeInBits, const T *AssignRecord, std::optional &Result) { // There are multiple offsets at play in this function, so let's break it // down. Starting with how variables may be stored in allocas: @@ -1819,7 +1893,7 @@ bool at::calculateFragmentIntersect( // dbg.assign, that has been killed, if any. // // calculateFragmentIntersect(..., SliceOffsetInBits=0, - // SliceSizeInBits=32, Dest=%dest, DAI=dbg.assign) + // SliceSizeInBits=32, Dest=%dest, Assign=dbg.assign) // // Drawing the store (s) in memory followed by the shortened version ($), // then the dbg.assign (d), with the fragment information on a seperate scale @@ -1832,7 +1906,8 @@ bool at::calculateFragmentIntersect( // | | // s[######] - Original stores 64 bits to Dest. // $----[##] - DSE says the lower 32 bits are dead, to be removed. - // d [##] - DAI's address-modifying expression adds 4 bytes to dest. + // d [##] - Assign's address-modifying expression adds 4 bytes to + // dest. // Variable | | // Fragment 128| // Offsets 159 @@ -1847,10 +1922,10 @@ bool at::calculateFragmentIntersect( // // 3. That offset along with the store size (32) represents the bits of the // variable that'd be affected by the store. Call it SliceOfVariable. - // Intersect that with DAI's fragment info: - // SliceOfVariable ∩ DAI_fragment = none + // Intersect that with Assign's fragment info: + // SliceOfVariable ∩ Assign_fragment = none // - // In this case: none of the dead bits of the store affect DAI. + // In this case: none of the dead bits of the store affect Assign. // // # Example 2 // Similar example with the same goal. This time the upper 16 bits @@ -1861,7 +1936,7 @@ bool at::calculateFragmentIntersect( // !DIExpression(DW_OP_plus_uconst, 4)) // // calculateFragmentIntersect(..., SliceOffsetInBits=48, - // SliceSizeInBits=16, Dest=%dest, DAI=dbg.assign) + // SliceSizeInBits=16, Dest=%dest, Assign=dbg.assign) // // Memory // offset @@ -1870,7 +1945,8 @@ bool at::calculateFragmentIntersect( // | | // s[######] - Original stores 64 bits to Dest. // $[####]-- - DSE says the upper 16 bits are dead, to be removed. - // d [##] - DAI's address-modifying expression adds 4 bytes to dest. + // d [##] - Assign's address-modifying expression adds 4 bytes to + // dest. // Variable | | // Fragment 128| // Offsets 159 @@ -1879,13 +1955,14 @@ bool at::calculateFragmentIntersect( // 1. SliceOffsetInBits:48 + VarFrag.OffsetInBits:128 = 176 // 2. 176 - (expression_offset:32 + (d.address - dest):0) = 144 // 3. SliceOfVariable offset = 144, size = 16: - // SliceOfVariable ∩ DAI_fragment = (offset: 144, size: 16) - // SliceOfVariable tells us the bits of the variable described by DAI that are - // affected by the DSE. - if (DAI->isKillAddress()) + // SliceOfVariable ∩ Assign_fragment = (offset: 144, size: 16) + // SliceOfVariable tells us the bits of the variable described by Assign that + // are affected by the DSE. + if (AssignRecord->isKillAddress()) return false; - DIExpression::FragmentInfo VarFrag = DAI->getFragmentOrEntireVariable(); + DIExpression::FragmentInfo VarFrag = + getFragmentOrEntireVariable(AssignRecord); if (VarFrag.SizeInBits == 0) return false; // Variable size is unknown. @@ -1893,12 +1970,14 @@ bool at::calculateFragmentIntersect( // address-modifying expression. int64_t PointerOffsetInBits; { - auto DestOffsetInBytes = DAI->getAddress()->getPointerOffsetFrom(Dest, DL); + auto DestOffsetInBytes = + AssignRecord->getAddress()->getPointerOffsetFrom(Dest, DL); if (!DestOffsetInBytes) return false; // Can't calculate difference in addresses. int64_t ExprOffsetInBytes; - if (!DAI->getAddressExpression()->extractIfOffset(ExprOffsetInBytes)) + if (!AssignRecord->getAddressExpression()->extractIfOffset( + ExprOffsetInBytes)) return false; int64_t PointerOffsetInBytes = *DestOffsetInBytes + ExprOffsetInBytes; @@ -1912,7 +1991,8 @@ bool at::calculateFragmentIntersect( if (NewOffsetInBits < 0) return false; // Fragment offsets can only be positive. DIExpression::FragmentInfo SliceOfVariable(SliceSizeInBits, NewOffsetInBits); - // Intersect the variable slice with DAI's fragment to trim it down to size. + // Intersect the variable slice with AssignRecord's fragment to trim it down + // to size. DIExpression::FragmentInfo TrimmedSliceOfVariable = DIExpression::FragmentInfo::intersect(SliceOfVariable, VarFrag); if (TrimmedSliceOfVariable == VarFrag) @@ -1921,6 +2001,20 @@ bool at::calculateFragmentIntersect( Result = TrimmedSliceOfVariable; return true; } +bool at::calculateFragmentIntersect( + const DataLayout &DL, const Value *Dest, uint64_t SliceOffsetInBits, + uint64_t SliceSizeInBits, const DbgAssignIntrinsic *DbgAssign, + std::optional &Result) { + return calculateFragmentIntersectImpl(DL, Dest, SliceOffsetInBits, + SliceSizeInBits, DbgAssign, Result); +} +bool at::calculateFragmentIntersect( + const DataLayout &DL, const Value *Dest, uint64_t SliceOffsetInBits, + uint64_t SliceSizeInBits, const DPValue *DPVAssign, + std::optional &Result) { + return calculateFragmentIntersectImpl(DL, Dest, SliceOffsetInBits, + SliceSizeInBits, DPVAssign, Result); +} /// Collect constant properies (base, size, offset) of \p StoreDest. /// Return std::nullopt if any properties are not constants or the @@ -1971,9 +2065,9 @@ std::optional at::getAssignmentInfo(const DataLayout &DL, } /// Returns nullptr if the assignment shouldn't be attributed to this variable. -static CallInst *emitDbgAssign(AssignmentInfo Info, Value *Val, Value *Dest, - Instruction &StoreLikeInst, - const VarRecord &VarRec, DIBuilder &DIB) { +static void emitDbgAssign(AssignmentInfo Info, Value *Val, Value *Dest, + Instruction &StoreLikeInst, const VarRecord &VarRec, + DIBuilder &DIB) { auto *ID = StoreLikeInst.getMetadata(LLVMContext::MD_DIAssignID); assert(ID && "Store instruction must have DIAssignID metadata"); (void)ID; @@ -1997,7 +2091,7 @@ static CallInst *emitDbgAssign(AssignmentInfo Info, Value *Val, Value *Dest, // Discard stores to bits outside this variable. if (FragStartBit >= FragEndBit) - return nullptr; + return; StoreToWholeVariable = FragStartBit <= VarStartBit && FragEndBit >= *Size; } @@ -2012,8 +2106,17 @@ static CallInst *emitDbgAssign(AssignmentInfo Info, Value *Val, Value *Dest, } DIExpression *AddrExpr = DIExpression::get(StoreLikeInst.getContext(), std::nullopt); - return DIB.insertDbgAssign(&StoreLikeInst, Val, VarRec.Var, Expr, Dest, - AddrExpr, VarRec.DL); + if (StoreLikeInst.getParent()->IsNewDbgInfoFormat) { + auto *Assign = DPValue::createLinkedDPVAssign( + &StoreLikeInst, Val, VarRec.Var, Expr, Dest, AddrExpr, VarRec.DL); + (void)Assign; + LLVM_DEBUG(if (Assign) errs() << " > INSERT: " << *Assign << "\n"); + return; + } + auto *Assign = DIB.insertDbgAssign(&StoreLikeInst, Val, VarRec.Var, Expr, + Dest, AddrExpr, VarRec.DL); + (void)Assign; + LLVM_DEBUG(if (Assign) errs() << " > INSERT: " << *Assign << "\n"); } #undef DEBUG_TYPE // Silence redefinition warning (from ConstantsContext.h). @@ -2100,12 +2203,8 @@ void at::trackAssignments(Function::iterator Start, Function::iterator End, I.setMetadata(LLVMContext::MD_DIAssignID, ID); } - for (const VarRecord &R : LocalIt->second) { - auto *Assign = - emitDbgAssign(*Info, ValueComponent, DestComponent, I, R, DIB); - (void)Assign; - LLVM_DEBUG(if (Assign) errs() << " > INSERT: " << *Assign << "\n"); - } + for (const VarRecord &R : LocalIt->second) + emitDbgAssign(*Info, ValueComponent, DestComponent, I, R, DIB); } } } @@ -2125,32 +2224,38 @@ bool AssignmentTrackingPass::runOnFunction(Function &F) { // storage" is limited to Allocas). We'll use this to find dbg.declares to // delete after running `trackAssignments`. DenseMap> DbgDeclares; + DenseMap> DPVDeclares; // Create another similar map of {storage : variables} that we'll pass to // trackAssignments. StorageToVarsMap Vars; + auto ProcessDeclare = [&](auto *Declare, auto &DeclareList) { + // FIXME: trackAssignments doesn't let you specify any modifiers to the + // variable (e.g. fragment) or location (e.g. offset), so we have to + // leave dbg.declares with non-empty expressions in place. + if (Declare->getExpression()->getNumElements() != 0) + return; + if (!Declare->getAddress()) + return; + if (AllocaInst *Alloca = + dyn_cast(Declare->getAddress()->stripPointerCasts())) { + // FIXME: Skip VLAs for now (let these variables use dbg.declares). + if (!Alloca->isStaticAlloca()) + return; + // Similarly, skip scalable vectors (use dbg.declares instead). + if (auto Sz = Alloca->getAllocationSize(*DL); Sz && Sz->isScalable()) + return; + DeclareList[Alloca].insert(Declare); + Vars[Alloca].insert(VarRecord(Declare)); + } + }; for (auto &BB : F) { for (auto &I : BB) { - DbgDeclareInst *DDI = dyn_cast(&I); - if (!DDI) - continue; - // FIXME: trackAssignments doesn't let you specify any modifiers to the - // variable (e.g. fragment) or location (e.g. offset), so we have to - // leave dbg.declares with non-empty expressions in place. - if (DDI->getExpression()->getNumElements() != 0) - continue; - if (!DDI->getAddress()) - continue; - if (AllocaInst *Alloca = - dyn_cast(DDI->getAddress()->stripPointerCasts())) { - // FIXME: Skip VLAs for now (let these variables use dbg.declares). - if (!Alloca->isStaticAlloca()) - continue; - // Similarly, skip scalable vectors (use dbg.declares instead). - if (auto Sz = Alloca->getAllocationSize(*DL); Sz && Sz->isScalable()) - continue; - DbgDeclares[Alloca].insert(DDI); - Vars[Alloca].insert(VarRecord(DDI)); + for (auto &DPV : I.getDbgValueRange()) { + if (DPV.isDbgDeclare()) + ProcessDeclare(&DPV, DPVDeclares); } + if (DbgDeclareInst *DDI = dyn_cast(&I)) + ProcessDeclare(DDI, DbgDeclares); } } @@ -2166,27 +2271,30 @@ bool AssignmentTrackingPass::runOnFunction(Function &F) { trackAssignments(F.begin(), F.end(), Vars, *DL); // Delete dbg.declares for variables now tracked with assignment tracking. - for (auto &P : DbgDeclares) { - const AllocaInst *Alloca = P.first; - auto Markers = at::getAssignmentMarkers(Alloca); + auto DeleteSubsumedDeclare = [&](const auto &Markers, auto &Declares) { (void)Markers; - for (DbgDeclareInst *DDI : P.second) { - // Assert that the alloca that DDI uses is now linked to a dbg.assign + for (auto *Declare : Declares) { + // Assert that the alloca that Declare uses is now linked to a dbg.assign // describing the same variable (i.e. check that this dbg.declare has // been replaced by a dbg.assign). Use DebugVariableAggregate to Discard // the fragment part because trackAssignments may alter the // fragment. e.g. if the alloca is smaller than the variable, then // trackAssignments will create an alloca-sized fragment for the // dbg.assign. - assert(llvm::any_of(Markers, [DDI](DbgAssignIntrinsic *DAI) { - return DebugVariableAggregate(DAI) == DebugVariableAggregate(DDI); + assert(llvm::any_of(Markers, [Declare](auto *Assign) { + return DebugVariableAggregate(Assign) == + DebugVariableAggregate(Declare); })); - // Delete DDI because the variable location is now tracked using + // Delete Declare because the variable location is now tracked using // assignment tracking. - DDI->eraseFromParent(); + Declare->eraseFromParent(); Changed = true; } - } + }; + for (auto &P : DbgDeclares) + DeleteSubsumedDeclare(at::getAssignmentMarkers(P.first), P.second); + for (auto &P : DPVDeclares) + DeleteSubsumedDeclare(at::getDPVAssignmentMarkers(P.first), P.second); return Changed; } diff --git a/llvm/lib/IR/DebugProgramInstruction.cpp b/llvm/lib/IR/DebugProgramInstruction.cpp index 7b709a2de03..fd234685d5f 100644 --- a/llvm/lib/IR/DebugProgramInstruction.cpp +++ b/llvm/lib/IR/DebugProgramInstruction.cpp @@ -14,8 +14,9 @@ namespace llvm { DPValue::DPValue(const DbgVariableIntrinsic *DVI) - : DebugValueUser(DVI->getRawLocation()), Variable(DVI->getVariable()), - Expression(DVI->getExpression()), DbgLoc(DVI->getDebugLoc()) { + : DebugValueUser({DVI->getRawLocation(), nullptr, nullptr}), + Variable(DVI->getVariable()), Expression(DVI->getExpression()), + DbgLoc(DVI->getDebugLoc()), AddressExpression(nullptr) { switch (DVI->getIntrinsicID()) { case Intrinsic::dbg_value: Type = LocationType::Value; @@ -23,6 +24,15 @@ DPValue::DPValue(const DbgVariableIntrinsic *DVI) case Intrinsic::dbg_declare: Type = LocationType::Declare; break; + case Intrinsic::dbg_assign: { + Type = LocationType::Assign; + const DbgAssignIntrinsic *Assign = + static_cast(DVI); + resetDebugValue(1, Assign->getRawAddress()); + AddressExpression = Assign->getAddressExpression(); + setAssignId(Assign->getAssignID()); + break; + } default: llvm_unreachable( "Trying to create a DPValue with an invalid intrinsic type!"); @@ -30,17 +40,77 @@ DPValue::DPValue(const DbgVariableIntrinsic *DVI) } DPValue::DPValue(const DPValue &DPV) - : DebugValueUser(DPV.getRawLocation()), - Variable(DPV.getVariable()), Expression(DPV.getExpression()), - DbgLoc(DPV.getDebugLoc()), Type(DPV.getType()) {} + : DebugValueUser(DPV.DebugValues), Variable(DPV.getVariable()), + Expression(DPV.getExpression()), DbgLoc(DPV.getDebugLoc()), + AddressExpression(DPV.AddressExpression), Type(DPV.getType()) {} DPValue::DPValue(Metadata *Location, DILocalVariable *DV, DIExpression *Expr, const DILocation *DI, LocationType Type) - : DebugValueUser(Location), Variable(DV), Expression(Expr), DbgLoc(DI), - Type(Type) {} + : DebugValueUser({Location, nullptr, nullptr}), Variable(DV), + Expression(Expr), DbgLoc(DI), Type(Type) {} + +DPValue::DPValue(Metadata *Value, DILocalVariable *Variable, + DIExpression *Expression, DIAssignID *AssignID, + Metadata *Address, DIExpression *AddressExpression, + const DILocation *DI) + : DebugValueUser({Value, Address, AssignID}), Variable(Variable), + Expression(Expression), DbgLoc(DI), AddressExpression(AddressExpression), + Type(LocationType::Assign) {} void DPValue::deleteInstr() { delete this; } +DPValue *DPValue::createDPValue(Value *Location, DILocalVariable *DV, + DIExpression *Expr, const DILocation *DI) { + return new DPValue(ValueAsMetadata::get(Location), DV, Expr, DI, + LocationType::Value); +} + +DPValue *DPValue::createDPValue(Value *Location, DILocalVariable *DV, + DIExpression *Expr, const DILocation *DI, + DPValue &InsertBefore) { + auto *NewDPValue = createDPValue(Location, DV, Expr, DI); + NewDPValue->insertBefore(&InsertBefore); + return NewDPValue; +} + +DPValue *DPValue::createDPVDeclare(Value *Address, DILocalVariable *DV, + DIExpression *Expr, const DILocation *DI) { + return new DPValue(ValueAsMetadata::get(Address), DV, Expr, DI, + LocationType::Declare); +} + +DPValue *DPValue::createDPVDeclare(Value *Address, DILocalVariable *DV, + DIExpression *Expr, const DILocation *DI, + DPValue &InsertBefore) { + auto *NewDPVDeclare = createDPVDeclare(Address, DV, Expr, DI); + NewDPVDeclare->insertBefore(&InsertBefore); + return NewDPVDeclare; +} + +DPValue *DPValue::createDPVAssign(Value *Val, DILocalVariable *Variable, + DIExpression *Expression, + DIAssignID *AssignID, Value *Address, + DIExpression *AddressExpression, + const DILocation *DI) { + return new DPValue(ValueAsMetadata::get(Val), Variable, Expression, AssignID, + ValueAsMetadata::get(Address), AddressExpression, DI); +} + +DPValue *DPValue::createLinkedDPVAssign(Instruction *LinkedInstr, Value *Val, + DILocalVariable *Variable, + DIExpression *Expression, + Value *Address, + DIExpression *AddressExpression, + const DILocation *DI) { + auto *Link = LinkedInstr->getMetadata(LLVMContext::MD_DIAssignID); + assert(Link && "Linked instruction must have DIAssign metadata attached"); + auto *NewDPVAssign = DPValue::createDPVAssign(Val, Variable, Expression, + cast(Link), Address, + AddressExpression, DI); + LinkedInstr->getParent()->insertDPValueAfter(NewDPVAssign, LinkedInstr); + return NewDPVAssign; +} + iterator_range DPValue::location_ops() const { auto *MD = getRawLocation(); // If a Value has been deleted, the "location" for this DPValue will be @@ -96,10 +166,15 @@ static ValueAsMetadata *getAsMetadata(Value *V) { void DPValue::replaceVariableLocationOp(Value *OldValue, Value *NewValue, bool AllowEmpty) { assert(NewValue && "Values must be non-null"); + + bool DbgAssignAddrReplaced = isDbgAssign() && OldValue == getAddress(); + if (DbgAssignAddrReplaced) + setAddress(NewValue); + auto Locations = location_ops(); auto OldIt = find(Locations, OldValue); if (OldIt == Locations.end()) { - if (AllowEmpty) + if (AllowEmpty || DbgAssignAddrReplaced) return; llvm_unreachable("OldValue must be a current location"); } @@ -190,9 +265,6 @@ DPValue::createDebugIntrinsic(Module *M, Instruction *InsertBefore) const { "Cannot clone from BasicBlock that is not part of a Module or " "DICompileUnit!"); LLVMContext &Context = getDebugLoc()->getContext(); - Value *Args[] = {MetadataAsValue::get(Context, getRawLocation()), - MetadataAsValue::get(Context, getVariable()), - MetadataAsValue::get(Context, getExpression())}; Function *IntrinsicFn; // Work out what sort of intrinsic we're going to produce. @@ -203,16 +275,34 @@ DPValue::createDebugIntrinsic(Module *M, Instruction *InsertBefore) const { case DPValue::LocationType::Value: IntrinsicFn = Intrinsic::getDeclaration(M, Intrinsic::dbg_value); break; + case DPValue::LocationType::Assign: + IntrinsicFn = Intrinsic::getDeclaration(M, Intrinsic::dbg_assign); + break; case DPValue::LocationType::End: case DPValue::LocationType::Any: llvm_unreachable("Invalid LocationType"); - break; } // Create the intrinsic from this DPValue's information, optionally insert // into the target location. - DbgVariableIntrinsic *DVI = cast( - CallInst::Create(IntrinsicFn->getFunctionType(), IntrinsicFn, Args)); + DbgVariableIntrinsic *DVI; + if (isDbgAssign()) { + Value *AssignArgs[] = { + MetadataAsValue::get(Context, getRawLocation()), + MetadataAsValue::get(Context, getVariable()), + MetadataAsValue::get(Context, getExpression()), + MetadataAsValue::get(Context, getAssignID()), + MetadataAsValue::get(Context, getRawAddress()), + MetadataAsValue::get(Context, getAddressExpression())}; + DVI = cast(CallInst::Create( + IntrinsicFn->getFunctionType(), IntrinsicFn, AssignArgs)); + } else { + Value *Args[] = {MetadataAsValue::get(Context, getRawLocation()), + MetadataAsValue::get(Context, getVariable()), + MetadataAsValue::get(Context, getExpression())}; + DVI = cast( + CallInst::Create(IntrinsicFn->getFunctionType(), IntrinsicFn, Args)); + } DVI->setTailCall(); DVI->setDebugLoc(getDebugLoc()); if (InsertBefore) @@ -221,8 +311,30 @@ DPValue::createDebugIntrinsic(Module *M, Instruction *InsertBefore) const { return DVI; } -void DPValue::handleChangedLocation(Metadata *NewLocation) { - resetDebugValue(NewLocation); +Value *DPValue::getAddress() const { + auto *MD = getRawAddress(); + if (auto *V = dyn_cast(MD)) + return V->getValue(); + + // When the value goes to null, it gets replaced by an empty MDNode. + assert(!cast(MD)->getNumOperands() && "Expected an empty MDNode"); + return nullptr; +} + +DIAssignID *DPValue::getAssignID() const { + return cast(DebugValues[2]); +} + +void DPValue::setAssignId(DIAssignID *New) { resetDebugValue(2, New); } + +void DPValue::setKillAddress() { + resetDebugValue( + 1, ValueAsMetadata::get(UndefValue::get(getAddress()->getType()))); +} + +bool DPValue::isKillAddress() const { + Value *Addr = getAddress(); + return !Addr || isa(Addr); } const BasicBlock *DPValue::getParent() const { @@ -249,6 +361,35 @@ const LLVMContext &DPValue::getContext() const { return getBlock()->getContext(); } +void DPValue::insertBefore(DPValue *InsertBefore) { + assert(!getMarker() && + "Cannot insert a DPValue that is already has a DPMarker!"); + assert(InsertBefore->getMarker() && + "Cannot insert a DPValue before a DPValue that does not have a " + "DPMarker!"); + InsertBefore->getMarker()->insertDPValue(this, InsertBefore); +} +void DPValue::insertAfter(DPValue *InsertAfter) { + assert(!getMarker() && + "Cannot insert a DPValue that is already has a DPMarker!"); + assert(InsertAfter->getMarker() && + "Cannot insert a DPValue after a DPValue that does not have a " + "DPMarker!"); + InsertAfter->getMarker()->insertDPValueAfter(this, InsertAfter); +} +void DPValue::moveBefore(DPValue *MoveBefore) { + assert(getMarker() && + "Canot move a DPValue that does not currently have a DPMarker!"); + removeFromParent(); + insertBefore(MoveBefore); +} +void DPValue::moveAfter(DPValue *MoveAfter) { + assert(getMarker() && + "Canot move a DPValue that does not currently have a DPMarker!"); + removeFromParent(); + insertAfter(MoveAfter); +} + /////////////////////////////////////////////////////////////////////////////// // An empty, global, DPMarker for the purpose of describing empty ranges of @@ -313,9 +454,14 @@ void DPMarker::eraseFromParent() { iterator_range DPMarker::getDbgValueRange() { return make_range(StoredDPValues.begin(), StoredDPValues.end()); } +iterator_range +DPMarker::getDbgValueRange() const { + return make_range(StoredDPValues.begin(), StoredDPValues.end()); +} void DPValue::removeFromParent() { getMarker()->StoredDPValues.erase(getIterator()); + Marker = nullptr; } void DPValue::eraseFromParent() { @@ -328,6 +474,18 @@ void DPMarker::insertDPValue(DPValue *New, bool InsertAtHead) { StoredDPValues.insert(It, *New); New->setMarker(this); } +void DPMarker::insertDPValue(DPValue *New, DPValue *InsertBefore) { + assert(InsertBefore->getMarker() == this && + "DPValue 'InsertBefore' must be contained in this DPMarker!"); + StoredDPValues.insert(InsertBefore->getIterator(), *New); + New->setMarker(this); +} +void DPMarker::insertDPValueAfter(DPValue *New, DPValue *InsertAfter) { + assert(InsertAfter->getMarker() == this && + "DPValue 'InsertAfter' must be contained in this DPMarker!"); + StoredDPValues.insert(++(InsertAfter->getIterator()), *New); + New->setMarker(this); +} void DPMarker::absorbDebugValues(DPMarker &Src, bool InsertAtHead) { auto It = InsertAtHead ? StoredDPValues.begin() : StoredDPValues.end(); diff --git a/llvm/lib/IR/Dominators.cpp b/llvm/lib/IR/Dominators.cpp index 0f4d112c69c..cc51b4905a6 100644 --- a/llvm/lib/IR/Dominators.cpp +++ b/llvm/lib/IR/Dominators.cpp @@ -49,10 +49,9 @@ static constexpr bool ExpensiveChecksEnabled = false; #endif bool BasicBlockEdge::isSingleEdge() const { - const Instruction *TI = Start->getTerminator(); unsigned NumEdgesToEnd = 0; - for (unsigned int i = 0, n = TI->getNumSuccessors(); i < n; ++i) { - if (TI->getSuccessor(i) == End) + for (const BasicBlock *Succ : successors(Start)) { + if (Succ == End) ++NumEdgesToEnd; if (NumEdgesToEnd >= 2) return false; diff --git a/llvm/lib/IR/Globals.cpp b/llvm/lib/IR/Globals.cpp index 239acd2181e..481a1d802e6 100644 --- a/llvm/lib/IR/Globals.cpp +++ b/llvm/lib/IR/Globals.cpp @@ -147,8 +147,7 @@ std::string GlobalValue::getGlobalIdentifier(StringRef Name, // Value names may be prefixed with a binary '1' to indicate // that the backend should not modify the symbols due to any platform // naming convention. Do not include that '1' in the PGO profile name. - if (Name[0] == '\1') - Name = Name.substr(1); + Name.consume_front("\1"); std::string GlobalName; if (llvm::GlobalValue::isLocalLinkage(Linkage)) { diff --git a/llvm/lib/IR/Instruction.cpp b/llvm/lib/IR/Instruction.cpp index 717e33f1857..d7bf1447921 100644 --- a/llvm/lib/IR/Instruction.cpp +++ b/llvm/lib/IR/Instruction.cpp @@ -146,9 +146,9 @@ void Instruction::insertBefore(BasicBlock &BB, bool InsertAtHead = InsertPos.getHeadBit(); if (!InsertAtHead) { DPMarker *SrcMarker = BB.getMarker(InsertPos); - if (!SrcMarker) - SrcMarker = BB.createMarker(InsertPos); - DbgMarker->absorbDebugValues(*SrcMarker, false); + // If there's no source marker, InsertPos is very likely end(). + if (SrcMarker) + DbgMarker->absorbDebugValues(*SrcMarker, false); } // If we're inserting a terminator, check if we need to flush out diff --git a/llvm/lib/IR/Instructions.cpp b/llvm/lib/IR/Instructions.cpp index 299b4e74677..87874c3abc4 100644 --- a/llvm/lib/IR/Instructions.cpp +++ b/llvm/lib/IR/Instructions.cpp @@ -3203,8 +3203,8 @@ unsigned CastInst::isEliminableCastPair( return 0; case 4: // No-op cast in second op implies firstOp as long as the DestTy - // is floating point. - if (DstTy->isFloatingPointTy()) + // matches MidTy. + if (DstTy == MidTy) return firstOp; return 0; case 5: diff --git a/llvm/lib/IR/Metadata.cpp b/llvm/lib/IR/Metadata.cpp index 515893d079b..37017a222d4 100644 --- a/llvm/lib/IR/Metadata.cpp +++ b/llvm/lib/IR/Metadata.cpp @@ -152,26 +152,47 @@ DPValue *DebugValueUser::getUser() { return static_cast(this); } const DPValue *DebugValueUser::getUser() const { return static_cast(this); } -void DebugValueUser::handleChangedValue(Metadata *NewMD) { - getUser()->handleChangedLocation(NewMD); + +void DebugValueUser::handleChangedValue(void *Old, Metadata *New) { + // NOTE: We could inform the "owner" that a value has changed through + // getOwner, if needed. + auto OldMD = static_cast(Old); + ptrdiff_t Idx = std::distance(&*DebugValues.begin(), OldMD); + resetDebugValue(Idx, New); } -void DebugValueUser::trackDebugValue() { - if (DebugValue) - MetadataTracking::track(&DebugValue, *DebugValue, *this); +void DebugValueUser::trackDebugValue(size_t Idx) { + assert(Idx < 3 && "Invalid debug value index."); + Metadata *&MD = DebugValues[Idx]; + if (MD) + MetadataTracking::track(&MD, *MD, *this); } -void DebugValueUser::untrackDebugValue() { - if (DebugValue) - MetadataTracking::untrack(DebugValue); +void DebugValueUser::trackDebugValues() { + for (Metadata *&MD : DebugValues) + if (MD) + MetadataTracking::track(&MD, *MD, *this); } -void DebugValueUser::retrackDebugValue(DebugValueUser &X) { - assert(DebugValue == X.DebugValue && "Expected values to match"); - if (X.DebugValue) { - MetadataTracking::retrack(X.DebugValue, DebugValue); - X.DebugValue = nullptr; - } +void DebugValueUser::untrackDebugValue(size_t Idx) { + assert(Idx < 3 && "Invalid debug value index."); + Metadata *&MD = DebugValues[Idx]; + if (MD) + MetadataTracking::untrack(MD); +} + +void DebugValueUser::untrackDebugValues() { + for (Metadata *&MD : DebugValues) + if (MD) + MetadataTracking::untrack(MD); +} + +void DebugValueUser::retrackDebugValues(DebugValueUser &X) { + assert(DebugValueUser::operator==(X) && "Expected values to match"); + for (const auto &[MD, XMD] : zip(DebugValues, X.DebugValues)) + if (XMD) + MetadataTracking::retrack(XMD, MD); + X.DebugValues.fill(nullptr); } bool MetadataTracking::track(void *Ref, Metadata &MD, OwnerTy Owner) { @@ -362,7 +383,7 @@ void ReplaceableMetadataImpl::replaceAllUsesWith(Metadata *MD) { } if (Owner.is()) { - Owner.get()->getUser()->handleChangedLocation(MD); + Owner.get()->handleChangedValue(Pair.first, MD); continue; } @@ -418,16 +439,22 @@ void ReplaceableMetadataImpl::resolveAllUses(bool ResolveUsers) { // commentry in DIArgList::handleChangedOperand for details. Hidden behind // conditional compilation to avoid a compile time regression. ReplaceableMetadataImpl *ReplaceableMetadataImpl::getOrCreate(Metadata &MD) { - if (auto *N = dyn_cast(&MD)) - return N->isResolved() ? nullptr : N->Context.getOrCreateReplaceableUses(); + if (auto *N = dyn_cast(&MD)) { + return !N->isResolved() || N->isAlwaysReplaceable() + ? N->Context.getOrCreateReplaceableUses() + : nullptr; + } if (auto ArgList = dyn_cast(&MD)) return ArgList; return dyn_cast(&MD); } ReplaceableMetadataImpl *ReplaceableMetadataImpl::getIfExists(Metadata &MD) { - if (auto *N = dyn_cast(&MD)) - return N->isResolved() ? nullptr : N->Context.getReplaceableUses(); + if (auto *N = dyn_cast(&MD)) { + return !N->isResolved() || N->isAlwaysReplaceable() + ? N->Context.getReplaceableUses() + : nullptr; + } if (auto ArgList = dyn_cast(&MD)) return ArgList; return dyn_cast(&MD); @@ -435,7 +462,7 @@ ReplaceableMetadataImpl *ReplaceableMetadataImpl::getIfExists(Metadata &MD) { bool ReplaceableMetadataImpl::isReplaceable(const Metadata &MD) { if (auto *N = dyn_cast(&MD)) - return !N->isResolved(); + return !N->isResolved() || N->isAlwaysReplaceable(); return isa(&MD) || isa(&MD); } @@ -503,7 +530,7 @@ void ValueAsMetadata::handleRAUW(Value *From, Value *To) { assert(From && "Expected valid value"); assert(To && "Expected valid value"); assert(From != To && "Expected changed value"); - assert(From->getType() == To->getType() && "Unexpected type change"); + assert(&From->getContext() == &To->getContext() && "Expected same context"); LLVMContext &Context = From->getType()->getContext(); auto &Store = Context.pImpl->ValuesAsMetadata; @@ -1506,6 +1533,21 @@ bool Value::eraseMetadata(unsigned KindID) { return Changed; } +void Value::eraseMetadataIf(function_ref Pred) { + if (!HasMetadata) + return; + + auto &MetadataStore = getContext().pImpl->ValueMetadata; + MDAttachments &Info = MetadataStore.find(this)->second; + assert(!Info.empty() && "bit out of sync with hash table"); + Info.remove_if([Pred](const MDAttachments::Attachment &I) { + return Pred(I.MDKind, I.Node); + }); + + if (Info.empty()) + clearMetadata(); +} + void Value::clearMetadata() { if (!HasMetadata) return; @@ -1529,6 +1571,13 @@ MDNode *Instruction::getMetadataImpl(StringRef Kind) const { return Value::getMetadata(KindID); } +void Instruction::eraseMetadataIf(function_ref Pred) { + if (DbgLoc && Pred(LLVMContext::MD_dbg, DbgLoc.getAsMDNode())) + DbgLoc = {}; + + Value::eraseMetadataIf(Pred); +} + void Instruction::dropUnknownNonDebugMetadata(ArrayRef KnownIDs) { if (!Value::hasMetadata()) return; // Nothing to remove! @@ -1539,17 +1588,9 @@ void Instruction::dropUnknownNonDebugMetadata(ArrayRef KnownIDs) { // A DIAssignID attachment is debug metadata, don't drop it. KnownSet.insert(LLVMContext::MD_DIAssignID); - auto &MetadataStore = getContext().pImpl->ValueMetadata; - MDAttachments &Info = MetadataStore.find(this)->second; - assert(!Info.empty() && "bit out of sync with hash table"); - Info.remove_if([&KnownSet](const MDAttachments::Attachment &I) { - return !KnownSet.count(I.MDKind); + Value::eraseMetadataIf([&KnownSet](unsigned MDKind, MDNode *Node) { + return !KnownSet.count(MDKind); }); - - if (Info.empty()) { - // Drop our entry at the store. - clearMetadata(); - } } void Instruction::updateDIAssignIDMapping(DIAssignID *ID) { diff --git a/llvm/lib/IR/StructuralHash.cpp b/llvm/lib/IR/StructuralHash.cpp index ce2b5a38b2f..b6de1ed725d 100644 --- a/llvm/lib/IR/StructuralHash.cpp +++ b/llvm/lib/IR/StructuralHash.cpp @@ -125,12 +125,9 @@ public: for (auto &Inst : *BB) updateInstruction(Inst, DetailedHash); - const Instruction *Term = BB->getTerminator(); - for (unsigned i = 0, e = Term->getNumSuccessors(); i != e; ++i) { - if (!VisitedBBs.insert(Term->getSuccessor(i)).second) - continue; - BBs.push_back(Term->getSuccessor(i)); - } + for (const BasicBlock *Succ : successors(BB)) + if (VisitedBBs.insert(Succ).second) + BBs.push_back(Succ); } } diff --git a/llvm/lib/Analysis/VFABIDemangling.cpp b/llvm/lib/IR/VFABIDemangler.cpp similarity index 80% rename from llvm/lib/Analysis/VFABIDemangling.cpp rename to llvm/lib/IR/VFABIDemangler.cpp index 8562d8fbfa1..cdfb9fbfaa0 100644 --- a/llvm/lib/Analysis/VFABIDemangling.cpp +++ b/llvm/lib/IR/VFABIDemangler.cpp @@ -1,4 +1,4 @@ -//===- VFABIDemangling.cpp - Vector Function ABI demangling utilities. ---===// +//===- VFABIDemangler.cpp - Vector Function ABI demangler -----------------===// // // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. // See https://llvm.org/LICENSE.txt for license information. @@ -6,14 +6,18 @@ // //===----------------------------------------------------------------------===// -#include "llvm/Analysis/VectorUtils.h" +#include "llvm/IR/VFABIDemangler.h" +#include "llvm/ADT/SetVector.h" +#include "llvm/ADT/SmallString.h" +#include "llvm/ADT/StringSwitch.h" +#include "llvm/IR/Module.h" #include "llvm/Support/Debug.h" #include "llvm/Support/raw_ostream.h" #include using namespace llvm; -#define DEBUG_TYPE "vfabi-demangling" +#define DEBUG_TYPE "vfabi-demangler" namespace { /// Utilities for the Vector Function ABI name parser. @@ -32,8 +36,7 @@ static ParseRet tryParseISA(StringRef &MangledName, VFISAKind &ISA) { if (MangledName.empty()) return ParseRet::Error; - if (MangledName.starts_with(VFABI::_LLVM_)) { - MangledName = MangledName.drop_front(strlen(VFABI::_LLVM_)); + if (MangledName.consume_front(VFABI::_LLVM_)) { ISA = VFISAKind::LLVM; } else { ISA = StringSwitch(MangledName.take_front(1)) @@ -519,3 +522,123 @@ VFParamKind VFABI::getVFParamKindFromString(const StringRef Token) { " that have a textual representation in the mangled name" " of the Vector Function ABI"); } + +void VFABI::getVectorVariantNames( + const CallInst &CI, SmallVectorImpl &VariantMappings) { + const StringRef S = CI.getFnAttr(VFABI::MappingsAttrName).getValueAsString(); + if (S.empty()) + return; + + SmallVector ListAttr; + S.split(ListAttr, ","); + + for (const auto &S : SetVector(ListAttr.begin(), ListAttr.end())) { + std::optional Info = + VFABI::tryDemangleForVFABI(S, CI.getFunctionType()); + if (Info && CI.getModule()->getFunction(Info->VectorName)) { + LLVM_DEBUG(dbgs() << "VFABI: Adding mapping '" << S << "' for " << CI + << "\n"); + VariantMappings.push_back(std::string(S)); + } else + LLVM_DEBUG(dbgs() << "VFABI: Invalid mapping '" << S << "'\n"); + } +} + +FunctionType *VFABI::createFunctionType(const VFInfo &Info, + const FunctionType *ScalarFTy) { + // Create vector parameter types + SmallVector VecTypes; + ElementCount VF = Info.Shape.VF; + int ScalarParamIndex = 0; + for (auto VFParam : Info.Shape.Parameters) { + if (VFParam.ParamKind == VFParamKind::GlobalPredicate) { + VectorType *MaskTy = + VectorType::get(Type::getInt1Ty(ScalarFTy->getContext()), VF); + VecTypes.push_back(MaskTy); + continue; + } + + Type *OperandTy = ScalarFTy->getParamType(ScalarParamIndex++); + if (VFParam.ParamKind == VFParamKind::Vector) + OperandTy = VectorType::get(OperandTy, VF); + VecTypes.push_back(OperandTy); + } + + auto *RetTy = ScalarFTy->getReturnType(); + if (!RetTy->isVoidTy()) + RetTy = VectorType::get(RetTy, VF); + return FunctionType::get(RetTy, VecTypes, false); +} + +void VFABI::setVectorVariantNames(CallInst *CI, + ArrayRef VariantMappings) { + if (VariantMappings.empty()) + return; + + SmallString<256> Buffer; + llvm::raw_svector_ostream Out(Buffer); + for (const std::string &VariantMapping : VariantMappings) + Out << VariantMapping << ","; + // Get rid of the trailing ','. + assert(!Buffer.str().empty() && "Must have at least one char."); + Buffer.pop_back(); + + Module *M = CI->getModule(); +#ifndef NDEBUG + for (const std::string &VariantMapping : VariantMappings) { + LLVM_DEBUG(dbgs() << "VFABI: adding mapping '" << VariantMapping << "'\n"); + std::optional VI = + VFABI::tryDemangleForVFABI(VariantMapping, CI->getFunctionType()); + assert(VI && "Cannot add an invalid VFABI name."); + assert(M->getNamedValue(VI->VectorName) && + "Cannot add variant to attribute: " + "vector function declaration is missing."); + } +#endif + CI->addFnAttr( + Attribute::get(M->getContext(), MappingsAttrName, Buffer.str())); +} + +bool VFShape::hasValidParameterList() const { + for (unsigned Pos = 0, NumParams = Parameters.size(); Pos < NumParams; + ++Pos) { + assert(Parameters[Pos].ParamPos == Pos && "Broken parameter list."); + + switch (Parameters[Pos].ParamKind) { + default: // Nothing to check. + break; + case VFParamKind::OMP_Linear: + case VFParamKind::OMP_LinearRef: + case VFParamKind::OMP_LinearVal: + case VFParamKind::OMP_LinearUVal: + // Compile time linear steps must be non-zero. + if (Parameters[Pos].LinearStepOrPos == 0) + return false; + break; + case VFParamKind::OMP_LinearPos: + case VFParamKind::OMP_LinearRefPos: + case VFParamKind::OMP_LinearValPos: + case VFParamKind::OMP_LinearUValPos: + // The runtime linear step must be referring to some other + // parameters in the signature. + if (Parameters[Pos].LinearStepOrPos >= int(NumParams)) + return false; + // The linear step parameter must be marked as uniform. + if (Parameters[Parameters[Pos].LinearStepOrPos].ParamKind != + VFParamKind::OMP_Uniform) + return false; + // The linear step parameter can't point at itself. + if (Parameters[Pos].LinearStepOrPos == int(Pos)) + return false; + break; + case VFParamKind::GlobalPredicate: + // The global predicate must be the unique. Can be placed anywhere in the + // signature. + for (unsigned NextPos = Pos + 1; NextPos < NumParams; ++NextPos) + if (Parameters[NextPos].ParamKind == VFParamKind::GlobalPredicate) + return false; + break; + } + } + return true; +} diff --git a/llvm/lib/IR/Value.cpp b/llvm/lib/IR/Value.cpp index 94b0ae7435c..c4e47975b18 100644 --- a/llvm/lib/IR/Value.cpp +++ b/llvm/lib/IR/Value.cpp @@ -51,9 +51,9 @@ static inline Type *checkType(Type *Ty) { } Value::Value(Type *ty, unsigned scid) - : VTy(checkType(ty)), UseList(nullptr), SubclassID(scid), HasValueHandle(0), - SubclassOptionalData(0), SubclassData(0), NumUserOperands(0), - IsUsedByMD(false), HasName(false), HasMetadata(false) { + : SubclassID(scid), HasValueHandle(0), SubclassOptionalData(0), + SubclassData(0), NumUserOperands(0), IsUsedByMD(false), HasName(false), + HasMetadata(false), VTy(checkType(ty)), UseList(nullptr) { static_assert(ConstantFirstVal == 0, "!(SubclassID < ConstantFirstVal)"); // FIXME: Why isn't this in the subclass gunk?? // Note, we cannot call isa before the CallInst has been diff --git a/llvm/lib/IR/Verifier.cpp b/llvm/lib/IR/Verifier.cpp index b6ad85b2d46..91cf91fbc78 100644 --- a/llvm/lib/IR/Verifier.cpp +++ b/llvm/lib/IR/Verifier.cpp @@ -107,6 +107,7 @@ #include "llvm/IR/Type.h" #include "llvm/IR/Use.h" #include "llvm/IR/User.h" +#include "llvm/IR/VFABIDemangler.h" #include "llvm/IR/Value.h" #include "llvm/InitializePasses.h" #include "llvm/Pass.h" @@ -172,6 +173,11 @@ private: } } + void Write(const DPValue *V) { + if (V) + V->print(*OS, MST, false); + } + void Write(const Metadata *MD) { if (!MD) return; @@ -2161,6 +2167,15 @@ void Verifier::verifyFunctionAttrs(FunctionType *FT, AttributeList Attrs, V); } + Check( + (Attrs.hasFnAttr("aarch64_new_zt0") + Attrs.hasFnAttr("aarch64_in_zt0") + + Attrs.hasFnAttr("aarch64_inout_zt0") + + Attrs.hasFnAttr("aarch64_out_zt0") + + Attrs.hasFnAttr("aarch64_preserves_zt0")) <= 1, + "Attributes 'aarch64_new_zt0', 'aarch64_in_zt0', 'aarch64_out_zt0', " + "'aarch64_inout_zt0' and 'aarch64_preserves_zt0' are mutually exclusive", + V); + if (Attrs.hasFnAttr(Attribute::JumpTable)) { const GlobalValue *GV = cast(V); Check(GV->hasGlobalUnnamedAddr(), @@ -2260,6 +2275,13 @@ void Verifier::verifyFunctionAttrs(FunctionType *FT, AttributeList Attrs, CheckFailed( "invalid value for 'branch-target-enforcement' attribute: " + S, V); } + + if (auto A = Attrs.getFnAttr("vector-function-abi-variant"); A.isValid()) { + StringRef S = A.getValueAsString(); + const std::optional Info = VFABI::tryDemangleForVFABI(S, FT); + if (!Info) + CheckFailed("invalid name for a VFABI variant: " + S, V); + } } void Verifier::verifyFunctionMetadata( @@ -4723,6 +4745,12 @@ void Verifier::visitDIAssignIDMetadata(Instruction &I, MDNode *MD) { "dbg.assign not in same function as inst", DAI, &I); } } + for (DPValue *DPV : cast(MD)->getAllDPValueUsers()) { + CheckDI(DPV->isDbgAssign(), + "!DIAssignID should only be used by Assign DPVs.", MD, DPV); + CheckDI(DPV->getFunction() == I.getFunction(), + "DPVAssign not in same function as inst", DPV, &I); + } } void Verifier::visitCallStackMetadata(MDNode *MD) { diff --git a/llvm/lib/InterfaceStub/IFSHandler.cpp b/llvm/lib/InterfaceStub/IFSHandler.cpp index da46592bd38..e80a59a572d 100644 --- a/llvm/lib/InterfaceStub/IFSHandler.cpp +++ b/llvm/lib/InterfaceStub/IFSHandler.cpp @@ -201,6 +201,12 @@ Expected> ifs::readIFSFromBuffer(StringRef Buf) { "IFS arch '" + *Stub->Target.ArchString + "' is unsupported"); Stub->Target.Arch = eMachine; } + for (const auto &Item : Stub->Symbols) { + if (Item.Type == IFSSymbolType::Unknown) + return createStringError( + std::make_error_code(std::errc::invalid_argument), + "IFS symbol type for symbol '" + Item.Name + "' is unsupported"); + } return std::move(Stub); } diff --git a/llvm/lib/InterfaceStub/IFSStub.cpp b/llvm/lib/InterfaceStub/IFSStub.cpp index f043f7e9e38..cde15ccfdba 100644 --- a/llvm/lib/InterfaceStub/IFSStub.cpp +++ b/llvm/lib/InterfaceStub/IFSStub.cpp @@ -89,8 +89,9 @@ uint8_t ifs::convertIFSSymbolTypeToELF(IFSSymbolType SymbolType) { case IFSSymbolType::TLS: return ELF::STT_TLS; case IFSSymbolType::NoType: - default: return ELF::STT_NOTYPE; + default: + llvm_unreachable("unknown symbol type"); } } diff --git a/llvm/lib/LTO/LTO.cpp b/llvm/lib/LTO/LTO.cpp index 6a1e53b9699..b38c568d10c 100644 --- a/llvm/lib/LTO/LTO.cpp +++ b/llvm/lib/LTO/LTO.cpp @@ -1573,7 +1573,7 @@ std::string lto::getThinLTOOutputFile(StringRef Path, StringRef OldPrefix, llvm::errs() << "warning: could not create directory '" << ParentPath << "': " << EC.message() << '\n'; } - return std::string(NewPath.str()); + return std::string(NewPath); } namespace { diff --git a/llvm/lib/LTO/ThinLTOCodeGenerator.cpp b/llvm/lib/LTO/ThinLTOCodeGenerator.cpp index 443439b71e7..535faf5f780 100644 --- a/llvm/lib/LTO/ThinLTOCodeGenerator.cpp +++ b/llvm/lib/LTO/ThinLTOCodeGenerator.cpp @@ -947,11 +947,11 @@ ThinLTOCodeGenerator::writeGeneratedObject(int count, StringRef CacheEntryPath, // Cache is enabled, hard-link the entry (or copy if hard-link fails). auto Err = sys::fs::create_hard_link(CacheEntryPath, OutputPath); if (!Err) - return std::string(OutputPath.str()); + return std::string(OutputPath); // Hard linking failed, try to copy. Err = sys::fs::copy_file(CacheEntryPath, OutputPath); if (!Err) - return std::string(OutputPath.str()); + return std::string(OutputPath); // Copy failed (could be because the CacheEntry was removed from the cache // in the meantime by another process), fall back and try to write down the // buffer to the output. @@ -964,7 +964,7 @@ ThinLTOCodeGenerator::writeGeneratedObject(int count, StringRef CacheEntryPath, if (Err) report_fatal_error(Twine("Can't open output '") + OutputPath + "'\n"); OS << OutputBuffer.getBuffer(); - return std::string(OutputPath.str()); + return std::string(OutputPath); } // Main entry point for the ThinLTO processing diff --git a/llvm/lib/LineEditor/LineEditor.cpp b/llvm/lib/LineEditor/LineEditor.cpp index bb408411a33..d0d138bb1f9 100644 --- a/llvm/lib/LineEditor/LineEditor.cpp +++ b/llvm/lib/LineEditor/LineEditor.cpp @@ -25,7 +25,7 @@ std::string LineEditor::getDefaultHistoryPath(StringRef ProgName) { SmallString<32> Path; if (sys::path::home_directory(Path)) { sys::path::append(Path, "." + ProgName + "-history"); - return std::string(Path.str()); + return std::string(Path); } return std::string(); } diff --git a/llvm/lib/MC/ELFObjectWriter.cpp b/llvm/lib/MC/ELFObjectWriter.cpp index cb8af1aa995..531d29954c3 100644 --- a/llvm/lib/MC/ELFObjectWriter.cpp +++ b/llvm/lib/MC/ELFObjectWriter.cpp @@ -226,6 +226,8 @@ class ELFObjectWriter : public MCObjectWriter { bool SeenGnuAbi = false; + std::optional OverrideABIVersion; + bool hasRelocationAddend() const; bool shouldRelocateWithSymbol(const MCAssembler &Asm, const MCValue &Val, @@ -238,6 +240,7 @@ public: void reset() override { SeenGnuAbi = false; + OverrideABIVersion.reset(); Relocations.clear(); Renames.clear(); MCObjectWriter::reset(); @@ -264,6 +267,10 @@ public: void markGnuAbi() override { SeenGnuAbi = true; } bool seenGnuAbi() const { return SeenGnuAbi; } + bool seenOverrideABIVersion() const { return OverrideABIVersion.has_value(); } + uint8_t getOverrideABIVersion() const { return OverrideABIVersion.value(); } + void setOverrideABIVersion(uint8_t V) override { OverrideABIVersion = V; } + friend struct ELFWriter; }; @@ -417,7 +424,9 @@ void ELFWriter::writeHeader(const MCAssembler &Asm) { ? int(ELF::ELFOSABI_GNU) : OSABI); // e_ident[EI_ABIVERSION] - W.OS << char(OWriter.TargetObjectWriter->getABIVersion()); + W.OS << char(OWriter.seenOverrideABIVersion() + ? OWriter.getOverrideABIVersion() + : OWriter.TargetObjectWriter->getABIVersion()); W.OS.write_zeros(ELF::EI_NIDENT - ELF::EI_PAD); diff --git a/llvm/lib/MC/MCFragment.cpp b/llvm/lib/MC/MCFragment.cpp index 4e6459c5d6e..a8da46dbd87 100644 --- a/llvm/lib/MC/MCFragment.cpp +++ b/llvm/lib/MC/MCFragment.cpp @@ -264,7 +264,7 @@ MCFragment::MCFragment(FragmentType Kind, bool HasInstructions, } void MCFragment::destroy() { - // First check if we are the sentinal. + // First check if we are the sentinel. if (Kind == FragmentType(~0)) { delete this; return; diff --git a/llvm/lib/MC/MCObjectFileInfo.cpp b/llvm/lib/MC/MCObjectFileInfo.cpp index a79759557b2..7b382c131ef 100644 --- a/llvm/lib/MC/MCObjectFileInfo.cpp +++ b/llvm/lib/MC/MCObjectFileInfo.cpp @@ -52,6 +52,10 @@ static bool useCompactUnwind(const Triple &T) { if (T.isSimulatorEnvironment()) return true; + // XROS always has it. + if (T.isXROS()) + return true; + return false; } diff --git a/llvm/lib/MC/MCParser/DarwinAsmParser.cpp b/llvm/lib/MC/MCParser/DarwinAsmParser.cpp index edea5a56bec..3cd44e7195b 100644 --- a/llvm/lib/MC/MCParser/DarwinAsmParser.cpp +++ b/llvm/lib/MC/MCParser/DarwinAsmParser.cpp @@ -1147,6 +1147,7 @@ static Triple::OSType getOSTypeFromPlatform(MachO::PlatformType Type) { case MachO::PLATFORM_IOS: return Triple::IOS; case MachO::PLATFORM_TVOS: return Triple::TvOS; case MachO::PLATFORM_WATCHOS: return Triple::WatchOS; + case MachO::PLATFORM_XROS: return Triple::XROS; case MachO::PLATFORM_BRIDGEOS: /* silence warning */ break; case MachO::PLATFORM_DRIVERKIT: return Triple::DriverKit; @@ -1154,6 +1155,7 @@ static Triple::OSType getOSTypeFromPlatform(MachO::PlatformType Type) { case MachO::PLATFORM_IOSSIMULATOR: /* silence warning */ break; case MachO::PLATFORM_TVOSSIMULATOR: /* silence warning */ break; case MachO::PLATFORM_WATCHOSSIMULATOR: /* silence warning */ break; + case MachO::PLATFORM_XROS_SIMULATOR: /* silence warning */ break; } llvm_unreachable("Invalid mach-o platform type"); } diff --git a/llvm/lib/MC/MCStreamer.cpp b/llvm/lib/MC/MCStreamer.cpp index 0062d083531..bc145aef0b8 100644 --- a/llvm/lib/MC/MCStreamer.cpp +++ b/llvm/lib/MC/MCStreamer.cpp @@ -1313,6 +1313,9 @@ static VersionTuple getMachoBuildVersionSupportedOS(const Triple &Target) { case Triple::DriverKit: // DriverKit always uses the build version load command. return VersionTuple(); + case Triple::XROS: + // XROS always uses the build version load command. + return VersionTuple(); default: break; } @@ -1339,6 +1342,9 @@ getMachoBuildVersionPlatformType(const Triple &Target) { : MachO::PLATFORM_WATCHOS; case Triple::DriverKit: return MachO::PLATFORM_DRIVERKIT; + case Triple::XROS: + return Target.isSimulatorEnvironment() ? MachO::PLATFORM_XROS_SIMULATOR + : MachO::PLATFORM_XROS; default: break; } @@ -1371,6 +1377,9 @@ void MCStreamer::emitVersionForTarget( case Triple::DriverKit: Version = Target.getDriverKitVersion(); break; + case Triple::XROS: + Version = Target.getOSVersion(); + break; default: llvm_unreachable("unexpected OS type"); } diff --git a/llvm/lib/MC/WasmObjectWriter.cpp b/llvm/lib/MC/WasmObjectWriter.cpp index e43f111113b..ead4f9eff4c 100644 --- a/llvm/lib/MC/WasmObjectWriter.cpp +++ b/llvm/lib/MC/WasmObjectWriter.cpp @@ -972,7 +972,7 @@ void WasmObjectWriter::writeTableSection(ArrayRef Tables) { encodeULEB128(Tables.size(), W->OS); for (const wasm::WasmTable &Table : Tables) { - encodeULEB128(Table.Type.ElemType, W->OS); + encodeULEB128((uint32_t)Table.Type.ElemType, W->OS); encodeULEB128(Table.Type.Limits.Flags, W->OS); encodeULEB128(Table.Type.Limits.Minimum, W->OS); if (Table.Type.Limits.Flags & wasm::WASM_LIMITS_FLAG_HAS_MAX) diff --git a/llvm/lib/ObjCopy/CommonConfig.cpp b/llvm/lib/ObjCopy/CommonConfig.cpp index f44e70d996b..ff3cb4d44c1 100644 --- a/llvm/lib/ObjCopy/CommonConfig.cpp +++ b/llvm/lib/ObjCopy/CommonConfig.cpp @@ -20,11 +20,7 @@ NameOrPattern::create(StringRef Pattern, MatchStyle MS, return NameOrPattern(Pattern); case MatchStyle::Wildcard: { SmallVector Data; - bool IsPositiveMatch = true; - if (Pattern[0] == '!') { - IsPositiveMatch = false; - Pattern = Pattern.drop_front(); - } + bool IsPositiveMatch = !Pattern.consume_front("!"); Expected GlobOrErr = GlobPattern::create(Pattern); // If we couldn't create it as a glob, report the error, but try again diff --git a/llvm/lib/Object/Archive.cpp b/llvm/lib/Object/Archive.cpp index 4ac4d727afb..e447e5b2331 100644 --- a/llvm/lib/Object/Archive.cpp +++ b/llvm/lib/Object/Archive.cpp @@ -567,7 +567,7 @@ Expected Archive::Child::getFullName() const { SmallString<128> FullName = sys::path::parent_path( Parent->getMemoryBufferRef().getBufferIdentifier()); sys::path::append(FullName, Name); - return std::string(FullName.str()); + return std::string(FullName); } Expected Archive::Child::getBuffer() const { diff --git a/llvm/lib/Object/ArchiveWriter.cpp b/llvm/lib/Object/ArchiveWriter.cpp index 2f70c9edd13..155926a8c59 100644 --- a/llvm/lib/Object/ArchiveWriter.cpp +++ b/llvm/lib/Object/ArchiveWriter.cpp @@ -950,7 +950,7 @@ Expected computeArchiveRelativePath(StringRef From, StringRef To) { for (auto ToE = sys::path::end(PathTo); ToI != ToE; ++ToI) sys::path::append(Relative, sys::path::Style::posix, *ToI); - return std::string(Relative.str()); + return std::string(Relative); } static Error writeArchiveToStream(raw_ostream &Out, diff --git a/llvm/lib/Object/Binary.cpp b/llvm/lib/Object/Binary.cpp index 0b9d9548528..2dfae8ab5d3 100644 --- a/llvm/lib/Object/Binary.cpp +++ b/llvm/lib/Object/Binary.cpp @@ -84,6 +84,7 @@ Expected> object::createBinary(MemoryBufferRef Buffer, // PDB does not support the Binary interface. return errorCodeToError(object_error::invalid_file_type); case file_magic::unknown: + case file_magic::clang_ast: case file_magic::cuda_fatbinary: case file_magic::coff_cl_gl_object: case file_magic::dxcontainer_object: diff --git a/llvm/lib/Object/COFFImportFile.cpp b/llvm/lib/Object/COFFImportFile.cpp index eeb13ffe9c1..60556c149bf 100644 --- a/llvm/lib/Object/COFFImportFile.cpp +++ b/llvm/lib/Object/COFFImportFile.cpp @@ -33,6 +33,25 @@ using namespace llvm; namespace llvm { namespace object { +StringRef COFFImportFile::getFileFormatName() const { + switch (getMachine()) { + case COFF::IMAGE_FILE_MACHINE_I386: + return "COFF-import-file-i386"; + case COFF::IMAGE_FILE_MACHINE_AMD64: + return "COFF-import-file-x86-64"; + case COFF::IMAGE_FILE_MACHINE_ARMNT: + return "COFF-import-file-ARM"; + case COFF::IMAGE_FILE_MACHINE_ARM64: + return "COFF-import-file-ARM64"; + case COFF::IMAGE_FILE_MACHINE_ARM64EC: + return "COFF-import-file-ARM64EC"; + case COFF::IMAGE_FILE_MACHINE_ARM64X: + return "COFF-import-file-ARM64X"; + default: + return "COFF-import-file-"; + } +} + static uint16_t getImgRelRelocation(MachineTypes Machine) { switch (Machine) { default: @@ -131,7 +150,7 @@ namespace { class ObjectFactory { using u16 = support::ulittle16_t; using u32 = support::ulittle32_t; - MachineTypes Machine; + MachineTypes NativeMachine; BumpPtrAllocator Alloc; StringRef ImportName; StringRef Library; @@ -140,7 +159,7 @@ class ObjectFactory { public: ObjectFactory(StringRef S, MachineTypes M) - : Machine(M), ImportName(S), Library(llvm::sys::path::stem(S)), + : NativeMachine(M), ImportName(S), Library(llvm::sys::path::stem(S)), ImportDescriptorSymbolName(("__IMPORT_DESCRIPTOR_" + Library).str()), NullThunkSymbolName(("\x7f" + Library + "_NULL_THUNK_DATA").str()) {} @@ -163,10 +182,14 @@ public: // Create a short import file which is described in PE/COFF spec 7. Import // Library Format. NewArchiveMember createShortImport(StringRef Sym, uint16_t Ordinal, - ImportType Type, ImportNameType NameType); + ImportType Type, ImportNameType NameType, + MachineTypes Machine); // Create a weak external file which is described in PE/COFF Aux Format 3. - NewArchiveMember createWeakExternal(StringRef Sym, StringRef Weak, bool Imp); + NewArchiveMember createWeakExternal(StringRef Sym, StringRef Weak, bool Imp, + MachineTypes Machine); + + bool is64Bit() const { return COFF::is64Bit(NativeMachine); } }; } // namespace @@ -178,7 +201,7 @@ ObjectFactory::createImportDescriptor(std::vector &Buffer) { // COFF Header coff_file_header Header{ - u16(Machine), + u16(NativeMachine), u16(NumberOfSections), u32(0), u32(sizeof(Header) + (NumberOfSections * sizeof(coff_section)) + @@ -189,7 +212,7 @@ ObjectFactory::createImportDescriptor(std::vector &Buffer) { (ImportName.size() + 1)), u32(NumberOfSymbols), u16(0), - u16(is64Bit(Machine) ? C_Invalid : IMAGE_FILE_32BIT_MACHINE), + u16(is64Bit() ? C_Invalid : IMAGE_FILE_32BIT_MACHINE), }; append(Buffer, Header); @@ -231,11 +254,11 @@ ObjectFactory::createImportDescriptor(std::vector &Buffer) { const coff_relocation RelocationTable[NumberOfRelocations] = { {u32(offsetof(coff_import_directory_table_entry, NameRVA)), u32(2), - u16(getImgRelRelocation(Machine))}, + u16(getImgRelRelocation(NativeMachine))}, {u32(offsetof(coff_import_directory_table_entry, ImportLookupTableRVA)), - u32(3), u16(getImgRelRelocation(Machine))}, + u32(3), u16(getImgRelRelocation(NativeMachine))}, {u32(offsetof(coff_import_directory_table_entry, ImportAddressTableRVA)), - u32(4), u16(getImgRelRelocation(Machine))}, + u32(4), u16(getImgRelRelocation(NativeMachine))}, }; append(Buffer, RelocationTable); @@ -317,7 +340,7 @@ ObjectFactory::createNullImportDescriptor(std::vector &Buffer) { // COFF Header coff_file_header Header{ - u16(Machine), + u16(NativeMachine), u16(NumberOfSections), u32(0), u32(sizeof(Header) + (NumberOfSections * sizeof(coff_section)) + @@ -325,7 +348,7 @@ ObjectFactory::createNullImportDescriptor(std::vector &Buffer) { sizeof(coff_import_directory_table_entry)), u32(NumberOfSymbols), u16(0), - u16(is64Bit(Machine) ? C_Invalid : IMAGE_FILE_32BIT_MACHINE), + u16(is64Bit() ? C_Invalid : IMAGE_FILE_32BIT_MACHINE), }; append(Buffer, Header); @@ -374,11 +397,11 @@ ObjectFactory::createNullImportDescriptor(std::vector &Buffer) { NewArchiveMember ObjectFactory::createNullThunk(std::vector &Buffer) { const uint32_t NumberOfSections = 2; const uint32_t NumberOfSymbols = 1; - uint32_t VASize = is64Bit(Machine) ? 8 : 4; + uint32_t VASize = is64Bit() ? 8 : 4; // COFF Header coff_file_header Header{ - u16(Machine), + u16(NativeMachine), u16(NumberOfSections), u32(0), u32(sizeof(Header) + (NumberOfSections * sizeof(coff_section)) + @@ -388,7 +411,7 @@ NewArchiveMember ObjectFactory::createNullThunk(std::vector &Buffer) { VASize), u32(NumberOfSymbols), u16(0), - u16(is64Bit(Machine) ? C_Invalid : IMAGE_FILE_32BIT_MACHINE), + u16(is64Bit() ? C_Invalid : IMAGE_FILE_32BIT_MACHINE), }; append(Buffer, Header); @@ -403,8 +426,7 @@ NewArchiveMember ObjectFactory::createNullThunk(std::vector &Buffer) { u32(0), u16(0), u16(0), - u32((is64Bit(Machine) ? IMAGE_SCN_ALIGN_8BYTES - : IMAGE_SCN_ALIGN_4BYTES) | + u32((is64Bit() ? IMAGE_SCN_ALIGN_8BYTES : IMAGE_SCN_ALIGN_4BYTES) | IMAGE_SCN_CNT_INITIALIZED_DATA | IMAGE_SCN_MEM_READ | IMAGE_SCN_MEM_WRITE)}, {{'.', 'i', 'd', 'a', 't', 'a', '$', '4'}, @@ -417,8 +439,7 @@ NewArchiveMember ObjectFactory::createNullThunk(std::vector &Buffer) { u32(0), u16(0), u16(0), - u32((is64Bit(Machine) ? IMAGE_SCN_ALIGN_8BYTES - : IMAGE_SCN_ALIGN_4BYTES) | + u32((is64Bit() ? IMAGE_SCN_ALIGN_8BYTES : IMAGE_SCN_ALIGN_4BYTES) | IMAGE_SCN_CNT_INITIALIZED_DATA | IMAGE_SCN_MEM_READ | IMAGE_SCN_MEM_WRITE)}, }; @@ -426,12 +447,12 @@ NewArchiveMember ObjectFactory::createNullThunk(std::vector &Buffer) { // .idata$5, ILT append(Buffer, u32(0)); - if (is64Bit(Machine)) + if (is64Bit()) append(Buffer, u32(0)); // .idata$4, IAT append(Buffer, u32(0)); - if (is64Bit(Machine)) + if (is64Bit()) append(Buffer, u32(0)); // Symbol Table @@ -456,7 +477,8 @@ NewArchiveMember ObjectFactory::createNullThunk(std::vector &Buffer) { NewArchiveMember ObjectFactory::createShortImport(StringRef Sym, uint16_t Ordinal, ImportType ImportType, - ImportNameType NameType) { + ImportNameType NameType, + MachineTypes Machine) { size_t ImpSize = ImportName.size() + Sym.size() + 2; // +2 for NULs size_t Size = sizeof(coff_import_header) + ImpSize; char *Buf = Alloc.Allocate(Size); @@ -482,7 +504,8 @@ NewArchiveMember ObjectFactory::createShortImport(StringRef Sym, } NewArchiveMember ObjectFactory::createWeakExternal(StringRef Sym, - StringRef Weak, bool Imp) { + StringRef Weak, bool Imp, + MachineTypes Machine) { std::vector Buffer; const uint32_t NumberOfSections = 1; const uint32_t NumberOfSymbols = 5; @@ -566,8 +589,11 @@ Error writeImportLibrary(StringRef ImportName, StringRef Path, ArrayRef Exports, MachineTypes Machine, bool MinGW) { + MachineTypes NativeMachine = + isArm64EC(Machine) ? IMAGE_FILE_MACHINE_ARM64 : Machine; + std::vector Members; - ObjectFactory OF(llvm::sys::path::filename(ImportName), Machine); + ObjectFactory OF(llvm::sys::path::filename(ImportName), NativeMachine); std::vector ImportDescriptor; Members.push_back(OF.createImportDescriptor(ImportDescriptor)); @@ -601,13 +627,15 @@ Error writeImportLibrary(StringRef ImportName, StringRef Path, return Name.takeError(); if (!E.AliasTarget.empty() && *Name != E.AliasTarget) { - Members.push_back(OF.createWeakExternal(E.AliasTarget, *Name, false)); - Members.push_back(OF.createWeakExternal(E.AliasTarget, *Name, true)); + Members.push_back( + OF.createWeakExternal(E.AliasTarget, *Name, false, Machine)); + Members.push_back( + OF.createWeakExternal(E.AliasTarget, *Name, true, Machine)); continue; } Members.push_back( - OF.createShortImport(*Name, E.Ordinal, ImportType, NameType)); + OF.createShortImport(*Name, E.Ordinal, ImportType, NameType, Machine)); } return writeArchive(Path, Members, SymtabWritingMode::NormalSymtab, diff --git a/llvm/lib/Object/ELFObjectFile.cpp b/llvm/lib/Object/ELFObjectFile.cpp index ae21b81c10c..28b96c341e3 100644 --- a/llvm/lib/Object/ELFObjectFile.cpp +++ b/llvm/lib/Object/ELFObjectFile.cpp @@ -830,6 +830,10 @@ Expected> static readBBAddrMapImpl( std::move(BBAddrMapOrErr->begin(), BBAddrMapOrErr->end(), std::back_inserter(BBAddrMaps)); } + if (PGOAnalyses) + assert(PGOAnalyses->size() == BBAddrMaps.size() && + "The same number of BBAddrMaps and PGOAnalysisMaps should be " + "returned when PGO information is requested"); return BBAddrMaps; } diff --git a/llvm/lib/Object/ObjectFile.cpp b/llvm/lib/Object/ObjectFile.cpp index c05eb0a0468..6a226a3bbdb 100644 --- a/llvm/lib/Object/ObjectFile.cpp +++ b/llvm/lib/Object/ObjectFile.cpp @@ -155,6 +155,7 @@ ObjectFile::createObjectFile(MemoryBufferRef Object, file_magic Type, switch (Type) { case file_magic::unknown: case file_magic::bitcode: + case file_magic::clang_ast: case file_magic::coff_cl_gl_object: case file_magic::archive: case file_magic::macho_universal_binary: diff --git a/llvm/lib/Object/OffloadBinary.cpp b/llvm/lib/Object/OffloadBinary.cpp index 1de784c44da..bfc35e41fe6 100644 --- a/llvm/lib/Object/OffloadBinary.cpp +++ b/llvm/lib/Object/OffloadBinary.cpp @@ -343,3 +343,35 @@ StringRef object::getImageKindName(ImageKind Kind) { return ""; } } + +bool object::areTargetsCompatible(const OffloadFile::TargetID &LHS, + const OffloadFile::TargetID &RHS) { + // Exact matches are not considered compatible because they are the same + // target. We are interested in different targets that are compatible. + if (LHS == RHS) + return false; + + // The triples must match at all times. + if (LHS.first != RHS.first) + return false; + + // Only The AMDGPU target requires additional checks. + llvm::Triple T(LHS.first); + if (!T.isAMDGPU()) + return false; + + // The base processor must always match. + if (LHS.second.split(":").first != RHS.second.split(":").first) + return false; + + // Check combintions of on / off features that must match. + if (LHS.second.contains("xnack+") && RHS.second.contains("xnack-")) + return false; + if (LHS.second.contains("xnack-") && RHS.second.contains("xnack+")) + return false; + if (LHS.second.contains("sramecc-") && RHS.second.contains("sramecc+")) + return false; + if (LHS.second.contains("sramecc+") && RHS.second.contains("sramecc-")) + return false; + return true; +} diff --git a/llvm/lib/Object/RelocationResolver.cpp b/llvm/lib/Object/RelocationResolver.cpp index ae97107f67f..564d9da78e9 100644 --- a/llvm/lib/Object/RelocationResolver.cpp +++ b/llvm/lib/Object/RelocationResolver.cpp @@ -538,6 +538,8 @@ static bool supportsLoongArch(uint64_t Type) { case ELF::R_LARCH_32: case ELF::R_LARCH_32_PCREL: case ELF::R_LARCH_64: + case ELF::R_LARCH_ADD6: + case ELF::R_LARCH_SUB6: case ELF::R_LARCH_ADD8: case ELF::R_LARCH_SUB8: case ELF::R_LARCH_ADD16: @@ -563,6 +565,10 @@ static uint64_t resolveLoongArch(uint64_t Type, uint64_t Offset, uint64_t S, return (S + Addend - Offset) & 0xFFFFFFFF; case ELF::R_LARCH_64: return S + Addend; + case ELF::R_LARCH_ADD6: + return (LocData & 0xC0) | ((LocData + S + Addend) & 0x3F); + case ELF::R_LARCH_SUB6: + return (LocData & 0xC0) | ((LocData - (S + Addend)) & 0x3F); case ELF::R_LARCH_ADD8: return (LocData + (S + Addend)) & 0xFF; case ELF::R_LARCH_SUB8: @@ -879,8 +885,10 @@ uint64_t resolveRelocation(RelocationResolver Resolver, const RelocationRef &R, if (GetRelSectionType() == ELF::SHT_RELA) { Addend = getELFAddend(R); - // RISCV relocations use both LocData and Addend. - if (Obj->getArch() != Triple::riscv32 && + // LoongArch and RISCV relocations use both LocData and Addend. + if (Obj->getArch() != Triple::loongarch32 && + Obj->getArch() != Triple::loongarch64 && + Obj->getArch() != Triple::riscv32 && Obj->getArch() != Triple::riscv64) LocData = 0; } diff --git a/llvm/lib/Object/WasmObjectFile.cpp b/llvm/lib/Object/WasmObjectFile.cpp index 94cd96968ff..b9a8e970216 100644 --- a/llvm/lib/Object/WasmObjectFile.cpp +++ b/llvm/lib/Object/WasmObjectFile.cpp @@ -258,7 +258,7 @@ static wasm::WasmLimits readLimits(WasmObjectFile::ReadContext &Ctx) { static wasm::WasmTableType readTableType(WasmObjectFile::ReadContext &Ctx) { wasm::WasmTableType TableType; - TableType.ElemType = readUint8(Ctx); + TableType.ElemType = wasm::ValType(readVaruint32(Ctx)); TableType.Limits = readLimits(Ctx); return TableType; } @@ -1163,8 +1163,8 @@ Error WasmObjectFile::parseImportSection(ReadContext &Ctx) { Im.Table = readTableType(Ctx); NumImportedTables++; auto ElemType = Im.Table.ElemType; - if (ElemType != wasm::WASM_TYPE_FUNCREF && - ElemType != wasm::WASM_TYPE_EXTERNREF) + if (ElemType != wasm::ValType::FUNCREF && + ElemType != wasm::ValType::EXTERNREF) return make_error("invalid table element type", object_error::parse_failed); break; @@ -1220,8 +1220,8 @@ Error WasmObjectFile::parseTableSection(ReadContext &Ctx) { T.Index = NumImportedTables + Tables.size(); Tables.push_back(T); auto ElemType = Tables.back().Type.ElemType; - if (ElemType != wasm::WASM_TYPE_FUNCREF && - ElemType != wasm::WASM_TYPE_EXTERNREF) { + if (ElemType != wasm::ValType::FUNCREF && + ElemType != wasm::ValType::EXTERNREF) { return make_error("invalid table element type", object_error::parse_failed); } @@ -1534,21 +1534,22 @@ Error WasmObjectFile::parseElemSection(ReadContext &Ctx) { } if (Segment.Flags & wasm::WASM_ELEM_SEGMENT_MASK_HAS_ELEM_KIND) { - Segment.ElemKind = readUint8(Ctx); + auto ElemKind = readVaruint32(Ctx); if (Segment.Flags & wasm::WASM_ELEM_SEGMENT_HAS_INIT_EXPRS) { - if (Segment.ElemKind != uint8_t(wasm::ValType::FUNCREF) && - Segment.ElemKind != uint8_t(wasm::ValType::EXTERNREF)) { + Segment.ElemKind = wasm::ValType(ElemKind); + if (Segment.ElemKind != wasm::ValType::FUNCREF && + Segment.ElemKind != wasm::ValType::EXTERNREF) { return make_error("invalid reference type", object_error::parse_failed); } } else { - if (Segment.ElemKind != 0) + if (ElemKind != 0) return make_error("invalid elemtype", object_error::parse_failed); - Segment.ElemKind = uint8_t(wasm::ValType::FUNCREF); + Segment.ElemKind = wasm::ValType::FUNCREF; } } else { - Segment.ElemKind = uint8_t(wasm::ValType::FUNCREF); + Segment.ElemKind = wasm::ValType::FUNCREF; } if (Segment.Flags & wasm::WASM_ELEM_SEGMENT_HAS_INIT_EXPRS) diff --git a/llvm/lib/Passes/PassBuilder.cpp b/llvm/lib/Passes/PassBuilder.cpp index bfc97d5464c..000594f0e7f 100644 --- a/llvm/lib/Passes/PassBuilder.cpp +++ b/llvm/lib/Passes/PassBuilder.cpp @@ -81,6 +81,7 @@ #include "llvm/CodeGen/ExpandLargeFpConvert.h" #include "llvm/CodeGen/ExpandMemCmp.h" #include "llvm/CodeGen/GCMetadata.h" +#include "llvm/CodeGen/GlobalMerge.h" #include "llvm/CodeGen/HardwareLoops.h" #include "llvm/CodeGen/IndirectBrExpand.h" #include "llvm/CodeGen/InterleavedAccess.h" @@ -92,6 +93,7 @@ #include "llvm/CodeGen/ShadowStackGCLowering.h" #include "llvm/CodeGen/SjLjEHPrepare.h" #include "llvm/CodeGen/StackProtector.h" +#include "llvm/CodeGen/TargetPassConfig.h" #include "llvm/CodeGen/TypePromotion.h" #include "llvm/CodeGen/WasmEHPrepare.h" #include "llvm/CodeGen/WinEHPrepare.h" @@ -300,109 +302,13 @@ cl::opt PrintPipelinePasses( "(best-effort only).")); } // namespace llvm -namespace { - -// The following passes/analyses have custom names, otherwise their name will -// include `(anonymous namespace)`. These are special since they are only for -// testing purposes and don't live in a header file. - -/// No-op module pass which does nothing. -struct NoOpModulePass : PassInfoMixin { - PreservedAnalyses run(Module &M, ModuleAnalysisManager &) { - return PreservedAnalyses::all(); - } - - static StringRef name() { return "NoOpModulePass"; } -}; - -/// No-op module analysis. -class NoOpModuleAnalysis : public AnalysisInfoMixin { - friend AnalysisInfoMixin; - static AnalysisKey Key; - -public: - struct Result {}; - Result run(Module &, ModuleAnalysisManager &) { return Result(); } - static StringRef name() { return "NoOpModuleAnalysis"; } -}; - -/// No-op CGSCC pass which does nothing. -struct NoOpCGSCCPass : PassInfoMixin { - PreservedAnalyses run(LazyCallGraph::SCC &C, CGSCCAnalysisManager &, - LazyCallGraph &, CGSCCUpdateResult &UR) { - return PreservedAnalyses::all(); - } - static StringRef name() { return "NoOpCGSCCPass"; } -}; - -/// No-op CGSCC analysis. -class NoOpCGSCCAnalysis : public AnalysisInfoMixin { - friend AnalysisInfoMixin; - static AnalysisKey Key; - -public: - struct Result {}; - Result run(LazyCallGraph::SCC &, CGSCCAnalysisManager &, LazyCallGraph &G) { - return Result(); - } - static StringRef name() { return "NoOpCGSCCAnalysis"; } -}; - -/// No-op function pass which does nothing. -struct NoOpFunctionPass : PassInfoMixin { - PreservedAnalyses run(Function &F, FunctionAnalysisManager &) { - return PreservedAnalyses::all(); - } - static StringRef name() { return "NoOpFunctionPass"; } -}; - -/// No-op function analysis. -class NoOpFunctionAnalysis : public AnalysisInfoMixin { - friend AnalysisInfoMixin; - static AnalysisKey Key; - -public: - struct Result {}; - Result run(Function &, FunctionAnalysisManager &) { return Result(); } - static StringRef name() { return "NoOpFunctionAnalysis"; } -}; - -/// No-op loop nest pass which does nothing. -struct NoOpLoopNestPass : PassInfoMixin { - PreservedAnalyses run(LoopNest &L, LoopAnalysisManager &, - LoopStandardAnalysisResults &, LPMUpdater &) { - return PreservedAnalyses::all(); - } - static StringRef name() { return "NoOpLoopNestPass"; } -}; - -/// No-op loop pass which does nothing. -struct NoOpLoopPass : PassInfoMixin { - PreservedAnalyses run(Loop &L, LoopAnalysisManager &, - LoopStandardAnalysisResults &, LPMUpdater &) { - return PreservedAnalyses::all(); - } - static StringRef name() { return "NoOpLoopPass"; } -}; - -/// No-op loop analysis. -class NoOpLoopAnalysis : public AnalysisInfoMixin { - friend AnalysisInfoMixin; - static AnalysisKey Key; - -public: - struct Result {}; - Result run(Loop &, LoopAnalysisManager &, LoopStandardAnalysisResults &) { - return Result(); - } - static StringRef name() { return "NoOpLoopAnalysis"; } -}; - AnalysisKey NoOpModuleAnalysis::Key; AnalysisKey NoOpCGSCCAnalysis::Key; AnalysisKey NoOpFunctionAnalysis::Key; AnalysisKey NoOpLoopAnalysis::Key; +namespace { + /// Whether or not we should populate a PassInstrumentationCallbacks's class to /// pass name map. /// @@ -411,7 +317,8 @@ AnalysisKey NoOpLoopAnalysis::Key; /// We currently only use this for --print-before/after. bool shouldPopulateClassToPassNames() { return PrintPipelinePasses || !printBeforePasses().empty() || - !printAfterPasses().empty() || !isFilterPassesEmpty(); + !printAfterPasses().empty() || !isFilterPassesEmpty() || + TargetPassConfig::hasLimitedCodeGenPipeline(); } // A pass for testing -print-on-crash. @@ -488,6 +395,12 @@ PassBuilder::PassBuilder(TargetMachine *TM, PipelineTuningOptions PTO, #define CGSCC_ANALYSIS(NAME, CREATE_PASS) \ PIC->addClassToPassName(decltype(CREATE_PASS)::name(), NAME); #include "PassRegistry.def" + +#define MACHINE_FUNCTION_ANALYSIS(NAME, PASS_NAME, CONSTRUCTOR) \ + PIC->addClassToPassName(PASS_NAME::name(), NAME); +#define MACHINE_FUNCTION_PASS(NAME, PASS_NAME, CONSTRUCTOR) \ + PIC->addClassToPassName(PASS_NAME::name(), NAME); +#include "llvm/CodeGen/MachinePassRegistry.def" } } @@ -523,6 +436,17 @@ void PassBuilder::registerFunctionAnalyses(FunctionAnalysisManager &FAM) { C(FAM); } +void PassBuilder::registerMachineFunctionAnalyses( + MachineFunctionAnalysisManager &MFAM) { + +#define MACHINE_FUNCTION_ANALYSIS(NAME, PASS_NAME, CONSTRUCTOR) \ + MFAM.registerPass([&] { return PASS_NAME(); }); +#include "llvm/CodeGen/MachinePassRegistry.def" + + for (auto &C : MachineFunctionAnalysisRegistrationCallbacks) + C(MFAM); +} + void PassBuilder::registerLoopAnalyses(LoopAnalysisManager &LAM) { #define LOOP_ANALYSIS(NAME, CREATE_PASS) \ LAM.registerPass([&] { return CREATE_PASS; }); @@ -737,6 +661,10 @@ Expected parseGlobalDCEPassOptions(StringRef Params) { return parseSinglePassOption(Params, "vfe-linkage-unit-visibility", "GlobalDCE"); } +Expected parseCGProfilePassOptions(StringRef Params) { + return parseSinglePassOption(Params, "in-lto-post-link", "CGProfile"); +} + Expected parseInlinerPassOptions(StringRef Params) { return parseSinglePassOption(Params, "only-mandatory", "InlinerPass"); } @@ -824,6 +752,26 @@ Expected parseHWASanPassOptions(StringRef Params) { return Result; } +Expected parseEmbedBitcodePassOptions(StringRef Params) { + EmbedBitcodeOptions Result; + while (!Params.empty()) { + StringRef ParamName; + std::tie(ParamName, Params) = Params.split(';'); + + if (ParamName == "thinlto") { + Result.IsThinLTO = true; + } else if (ParamName == "emit-summary") { + Result.EmitLTOSummary = true; + } else { + return make_error( + formatv("invalid EmbedBitcode pass parameter '{0}' ", ParamName) + .str(), + inconvertibleErrorCode()); + } + } + return Result; +} + Expected parseMSanPassOptions(StringRef Params) { MemorySanitizerOptions Result; while (!Params.empty()) { @@ -1161,6 +1109,32 @@ Expected parseWinEHPrepareOptions(StringRef Params) { "WinEHPreparePass"); } +Expected parseGlobalMergeOptions(StringRef Params) { + GlobalMergeOptions Result; + while (!Params.empty()) { + StringRef ParamName; + std::tie(ParamName, Params) = Params.split(';'); + + bool Enable = !ParamName.consume_front("no-"); + if (ParamName == "group-by-use") + Result.GroupByUse = Enable; + else if (ParamName == "ignore-single-use") + Result.IgnoreSingleUse = Enable; + else if (ParamName == "merge-const") + Result.MergeConst = Enable; + else if (ParamName == "merge-external") + Result.MergeExternal = Enable; + else if (ParamName.consume_front("max-offset=")) { + if (ParamName.getAsInteger(0, Result.MaxOffset)) + return make_error( + formatv("invalid GlobalMergePass parameter '{0}' ", ParamName) + .str(), + inconvertibleErrorCode()); + } + } + return Result; +} + } // namespace /// Tests whether a pass name starts with a valid prefix for a default pipeline @@ -1877,6 +1851,33 @@ Error PassBuilder::parseLoopPass(LoopPassManager &LPM, inconvertibleErrorCode()); } +Error PassBuilder::parseMachinePass(MachineFunctionPassManager &MFPM, + const PipelineElement &E) { + StringRef Name = E.Name; + if (!E.InnerPipeline.empty()) + return make_error("invalid pipeline", + inconvertibleErrorCode()); + +#define MACHINE_MODULE_PASS(NAME, PASS_NAME, CONSTRUCTOR) \ + if (Name == NAME) { \ + MFPM.addPass(PASS_NAME()); \ + return Error::success(); \ + } +#define MACHINE_FUNCTION_PASS(NAME, PASS_NAME, CONSTRUCTOR) \ + if (Name == NAME) { \ + MFPM.addPass(PASS_NAME()); \ + return Error::success(); \ + } +#include "llvm/CodeGen/MachinePassRegistry.def" + + for (auto &C : MachinePipelineParsingCallbacks) + if (C(Name, MFPM)) + return Error::success(); + return make_error( + formatv("unknown machine pass '{0}'", Name).str(), + inconvertibleErrorCode()); +} + bool PassBuilder::parseAAPassName(AAManager &AA, StringRef Name) { #define MODULE_ALIAS_ANALYSIS(NAME, CREATE_PASS) \ if (Name == NAME) { \ @@ -1898,6 +1899,15 @@ bool PassBuilder::parseAAPassName(AAManager &AA, StringRef Name) { return false; } +Error PassBuilder::parseMachinePassPipeline( + MachineFunctionPassManager &MFPM, ArrayRef Pipeline) { + for (const auto &Element : Pipeline) { + if (auto Err = parseMachinePass(MFPM, Element)) + return Err; + } + return Error::success(); +} + Error PassBuilder::parseLoopPassPipeline(LoopPassManager &LPM, ArrayRef Pipeline) { for (const auto &Element : Pipeline) { @@ -2057,6 +2067,20 @@ Error PassBuilder::parsePassPipeline(LoopPassManager &CGPM, return Error::success(); } +Error PassBuilder::parsePassPipeline(MachineFunctionPassManager &MFPM, + StringRef PipelineText) { + auto Pipeline = parsePipelineText(PipelineText); + if (!Pipeline || Pipeline->empty()) + return make_error( + formatv("invalid machine pass pipeline '{0}'", PipelineText).str(), + inconvertibleErrorCode()); + + if (auto Err = parseMachinePassPipeline(MFPM, *Pipeline)) + return Err; + + return Error::success(); +} + Error PassBuilder::parseAAPipeline(AAManager &AA, StringRef PipelineText) { // If the pipeline just consists of the word 'default' just replace the AA // manager with our default one. @@ -2151,6 +2175,21 @@ void PassBuilder::printPassNames(raw_ostream &OS) { OS << "Loop analyses:\n"; #define LOOP_ANALYSIS(NAME, CREATE_PASS) printPassName(NAME, OS); #include "PassRegistry.def" + + OS << "Machine module passes (WIP):\n"; +#define MACHINE_MODULE_PASS(NAME, PASS_NAME, CONSTRUCTOR) \ + printPassName(NAME, OS); +#include "llvm/CodeGen/MachinePassRegistry.def" + + OS << "Machine function passes (WIP):\n"; +#define MACHINE_FUNCTION_PASS(NAME, PASS_NAME, CONSTRUCTOR) \ + printPassName(NAME, OS); +#include "llvm/CodeGen/MachinePassRegistry.def" + + OS << "Machine function analyses (WIP):\n"; +#define MACHINE_FUNCTION_ANALYSIS(NAME, PASS_NAME, CONSTRUCTOR) \ + printPassName(NAME, OS); +#include "llvm/CodeGen/MachinePassRegistry.def" } void PassBuilder::registerParseTopLevelPipelineCallback( diff --git a/llvm/lib/Passes/PassBuilderPipelines.cpp b/llvm/lib/Passes/PassBuilderPipelines.cpp index 5c6c391049a..6ede8638291 100644 --- a/llvm/lib/Passes/PassBuilderPipelines.cpp +++ b/llvm/lib/Passes/PassBuilderPipelines.cpp @@ -1477,7 +1477,8 @@ PassBuilder::buildModuleOptimizationPipeline(OptimizationLevel Level, MPM.addPass(ConstantMergePass()); if (PTO.CallGraphProfile && !LTOPreLink) - MPM.addPass(CGProfilePass()); + MPM.addPass(CGProfilePass(LTOPhase == ThinOrFullLTOPhase::FullLTOPostLink || + LTOPhase == ThinOrFullLTOPhase::ThinLTOPostLink)); // TODO: Relative look table converter pass caused an issue when full lto is // enabled. See https://reviews.llvm.org/D94355 for more details. @@ -1530,14 +1531,17 @@ PassBuilder::buildPerModuleDefaultPipeline(OptimizationLevel Level, } ModulePassManager -PassBuilder::buildFatLTODefaultPipeline(OptimizationLevel Level) { +PassBuilder::buildFatLTODefaultPipeline(OptimizationLevel Level, bool ThinLTO, + bool EmitSummary) { ModulePassManager MPM; - // FatLTO always uses UnifiedLTO, so use the ThinLTOPreLink pipeline - MPM.addPass(buildThinLTOPreLinkDefaultPipeline(Level)); - MPM.addPass(EmbedBitcodePass()); + if (ThinLTO) + MPM.addPass(buildThinLTOPreLinkDefaultPipeline(Level)); + else + MPM.addPass(buildLTOPreLinkDefaultPipeline(Level)); + MPM.addPass(EmbedBitcodePass(ThinLTO, EmitSummary)); - // Use the ThinLTO post-link pipeline with sample profiling, other - if (PGOOpt && PGOOpt->Action == PGOOptions::SampleUse) + // Use the ThinLTO post-link pipeline with sample profiling + if (ThinLTO && PGOOpt && PGOOpt->Action == PGOOptions::SampleUse) MPM.addPass(buildThinLTODefaultPipeline(Level, /*ImportSummary=*/nullptr)); else { // otherwise, just use module optimization @@ -1972,7 +1976,7 @@ PassBuilder::buildLTODefaultPipeline(OptimizationLevel Level, MPM.addPass(MergeFunctionsPass()); if (PTO.CallGraphProfile) - MPM.addPass(CGProfilePass()); + MPM.addPass(CGProfilePass(/*InLTOPostLink=*/true)); invokeFullLinkTimeOptimizationLastEPCallbacks(MPM, Level); diff --git a/llvm/lib/Passes/PassRegistry.def b/llvm/lib/Passes/PassRegistry.def index 0b53b59787d..e59795c7b08 100644 --- a/llvm/lib/Passes/PassRegistry.def +++ b/llvm/lib/Passes/PassRegistry.def @@ -47,7 +47,6 @@ MODULE_PASS("attributor", AttributorPass()) MODULE_PASS("attributor-light", AttributorLightPass()) MODULE_PASS("called-value-propagation", CalledValuePropagationPass()) MODULE_PASS("canonicalize-aliases", CanonicalizeAliasesPass()) -MODULE_PASS("cg-profile", CGProfilePass()) MODULE_PASS("check-debugify", NewPMCheckDebugifyPass()) MODULE_PASS("constmerge", ConstantMergePass()) MODULE_PASS("coro-cleanup", CoroCleanupPass()) @@ -59,7 +58,6 @@ MODULE_PASS("dfsan", DataFlowSanitizerPass()) MODULE_PASS("dot-callgraph", CallGraphDOTPrinterPass()) MODULE_PASS("dxil-upgrade", DXILUpgradePass()) MODULE_PASS("elim-avail-extern", EliminateAvailableExternallyPass()) -MODULE_PASS("embed-bitcode", EmbedBitcodePass()) MODULE_PASS("extract-blocks", BlockExtractorPass({}, false)) MODULE_PASS("forceattrs", ForceFunctionAttrsPass()) MODULE_PASS("function-import", FunctionImportPass()) @@ -151,6 +149,21 @@ MODULE_PASS_WITH_PARAMS( "asan", "AddressSanitizerPass", [](AddressSanitizerOptions Opts) { return AddressSanitizerPass(Opts); }, parseASanPassOptions, "kernel") +MODULE_PASS_WITH_PARAMS( + "cg-profile", "CGProfilePass", + [](bool InLTOPostLink) { return CGProfilePass(InLTOPostLink);}, + parseCGProfilePassOptions, "in-lto-post-link") +MODULE_PASS_WITH_PARAMS( + "global-merge", "GlobalMergePass", + [TM = TM](GlobalMergeOptions Opts) { return GlobalMergePass(TM, Opts); }, + parseGlobalMergeOptions, + "group-by-use;ignore-single-use;max-offset=N;merge-const;merge-external;" + "no-group-by-use;no-ignore-single-use;no-merge-const;no-merge-external;" + "size-only") +MODULE_PASS_WITH_PARAMS( + "embed-bitcode", "EmbedBitcodePass", + [](EmbedBitcodeOptions Opts) { return EmbedBitcodePass(Opts); }, + parseEmbedBitcodePassOptions, "thinlto;emit-summary") MODULE_PASS_WITH_PARAMS( "globaldce", "GlobalDCEPass", [](bool InLTOPostLink) { return GlobalDCEPass(InLTOPostLink); }, diff --git a/llvm/lib/Passes/StandardInstrumentations.cpp b/llvm/lib/Passes/StandardInstrumentations.cpp index d467fe5c9a8..aea8acebcb8 100644 --- a/llvm/lib/Passes/StandardInstrumentations.cpp +++ b/llvm/lib/Passes/StandardInstrumentations.cpp @@ -2119,8 +2119,8 @@ DCData::DCData(const BasicBlock &B) { addSuccessorLabel(C.getCaseSuccessor()->getName().str(), Value); } } else - for (const_succ_iterator I = succ_begin(&B), E = succ_end(&B); I != E; ++I) - addSuccessorLabel((*I)->getName().str(), ""); + for (const BasicBlock *Succ : successors(&B)) + addSuccessorLabel(Succ->getName().str(), ""); } DotCfgChangeReporter::DotCfgChangeReporter(bool Verbose) diff --git a/llvm/lib/ProfileData/Coverage/CoverageMapping.cpp b/llvm/lib/ProfileData/Coverage/CoverageMapping.cpp index eece6a2cc71..da8e1d87319 100644 --- a/llvm/lib/ProfileData/Coverage/CoverageMapping.cpp +++ b/llvm/lib/ProfileData/Coverage/CoverageMapping.cpp @@ -229,6 +229,7 @@ Expected CounterMappingContext::evaluateBitmap( unsigned SizeInBits = llvm::alignTo(uint64_t(1) << NC, CHAR_BIT); unsigned SizeInBytes = SizeInBits / CHAR_BIT; + assert(ID + SizeInBytes <= BitmapBytes.size() && "BitmapBytes overrun"); ArrayRef Bytes(&BitmapBytes[ID], SizeInBytes); // Mask each bitmap byte into the BitVector. Go in reverse so that the @@ -247,14 +248,14 @@ class MCDCRecordProcessor { /// Each index of the bitmap corresponds to a possible test vector. An index /// with a bit value of '1' indicates that the corresponding Test Vector /// identified by that index was executed. - BitVector &ExecutedTestVectorBitmap; + const BitVector &ExecutedTestVectorBitmap; /// Decision Region to which the ExecutedTestVectorBitmap applies. - CounterMappingRegion &Region; + const CounterMappingRegion &Region; /// Array of branch regions corresponding each conditions in the boolean /// expression. - ArrayRef Branches; + ArrayRef Branches; /// Total number of conditions in the boolean expression. unsigned NumConditions; @@ -276,8 +277,9 @@ class MCDCRecordProcessor { MCDCRecord::TestVectors ExecVectors; public: - MCDCRecordProcessor(BitVector &Bitmap, CounterMappingRegion &Region, - ArrayRef Branches) + MCDCRecordProcessor(const BitVector &Bitmap, + const CounterMappingRegion &Region, + ArrayRef Branches) : ExecutedTestVectorBitmap(Bitmap), Region(Region), Branches(Branches), NumConditions(Region.MCDCParams.NumConditions), Folded(NumConditions, false), IndependencePairs(NumConditions), @@ -342,7 +344,7 @@ private: /// Walk the bits in the bitmap. A bit set to '1' indicates that the test /// vector at the corresponding index was executed during a test run. - void findExecutedTestVectors(BitVector &ExecutedTestVectorBitmap) { + void findExecutedTestVectors(const BitVector &ExecutedTestVectorBitmap) { for (unsigned Idx = 0; Idx < ExecutedTestVectorBitmap.size(); ++Idx) { if (ExecutedTestVectorBitmap[Idx] == 0) continue; @@ -445,11 +447,11 @@ public: // visualize where the condition is. // - Record whether the condition is constant folded so that we exclude it // from being measured. - for (const auto &B : Branches) { - Map[B.MCDCParams.ID] = &B; - PosToID[I] = B.MCDCParams.ID - 1; - CondLoc[I] = B.startLoc(); - Folded[I++] = (B.Count.isZero() && B.FalseCount.isZero()); + for (const auto *B : Branches) { + Map[B->MCDCParams.ID] = B; + PosToID[I] = B->MCDCParams.ID - 1; + CondLoc[I] = B->startLoc(); + Folded[I++] = (B->Count.isZero() && B->FalseCount.isZero()); } // Initialize a base test vector as 'DontCare'. @@ -473,8 +475,9 @@ public: }; Expected CounterMappingContext::evaluateMCDCRegion( - CounterMappingRegion Region, BitVector ExecutedTestVectorBitmap, - ArrayRef Branches) { + const CounterMappingRegion &Region, + const BitVector &ExecutedTestVectorBitmap, + ArrayRef Branches) { MCDCRecordProcessor MCDCProcessor(ExecutedTestVectorBitmap, Region, Branches); return MCDCProcessor.processMCDCRecord(); @@ -566,14 +569,14 @@ static unsigned getMaxBitmapSize(const CounterMappingContext &Ctx, const CoverageMappingRecord &Record) { unsigned MaxBitmapID = 0; unsigned NumConditions = 0; - // The last DecisionRegion has the highest bitmap byte index used in the - // function, which when combined with its number of conditions, yields the - // full bitmap size. + // Scan max(BitmapIdx). + // Note that `<=` is used insted of `<`, because `BitmapIdx == 0` is valid + // and `MaxBitmapID is `unsigned`. `BitmapIdx` is unique in the record. for (const auto &Region : reverse(Record.MappingRegions)) { - if (Region.Kind == CounterMappingRegion::MCDCDecisionRegion) { + if (Region.Kind == CounterMappingRegion::MCDCDecisionRegion && + MaxBitmapID <= Region.MCDCParams.BitmapIdx) { MaxBitmapID = Region.MCDCParams.BitmapIdx; NumConditions = Region.MCDCParams.NumConditions; - break; } } unsigned SizeInBits = llvm::alignTo(uint64_t(1) << NumConditions, CHAR_BIT); @@ -638,7 +641,7 @@ Error CoverageMapping::loadFunctionRecord( unsigned NumConds = 0; const CounterMappingRegion *MCDCDecision; - std::vector MCDCBranches; + std::vector MCDCBranches; FunctionRecord Function(OrigFuncName, Record.Filenames); for (const auto &Region : Record.MappingRegions) { @@ -666,7 +669,7 @@ Error CoverageMapping::loadFunctionRecord( // correspond to it in a vector, according to the number of conditions // recorded for the region (tracked by NumConds). if (NumConds > 0 && Region.Kind == CounterMappingRegion::MCDCBranchRegion) { - MCDCBranches.push_back(Region); + MCDCBranches.push_back(&Region); // As we move through all of the MCDCBranchRegions that follow the // MCDCDecisionRegion, decrement NumConds to make sure we account for @@ -1319,8 +1322,15 @@ LineCoverageStats::LineCoverageStats( !StartOfSkippedRegion && ((WrappedSegment && WrappedSegment->HasCount) || (MinRegionCount > 0)); - if (!Mapped) + // if there is any starting segment at this line with a counter, it must be + // mapped + Mapped |= std::any_of( + LineSegments.begin(), LineSegments.end(), + [](const auto *Seq) { return Seq->IsRegionEntry && Seq->HasCount; }); + + if (!Mapped) { return; + } // Pick the max count from the non-gap, region entry segments and the // wrapped count. diff --git a/llvm/lib/ProfileData/GCOV.cpp b/llvm/lib/ProfileData/GCOV.cpp index f7bf42e5c4d..fcfeb5b0f58 100644 --- a/llvm/lib/ProfileData/GCOV.cpp +++ b/llvm/lib/ProfileData/GCOV.cpp @@ -666,7 +666,7 @@ static std::string mangleCoveragePath(StringRef Filename, bool PreservePaths) { if (S < I) Result.append(S, I); - return std::string(Result.str()); + return std::string(Result); } std::string Context::getCoveragePath(StringRef filename, diff --git a/llvm/lib/ProfileData/InstrProf.cpp b/llvm/lib/ProfileData/InstrProf.cpp index 4264da8ad75..2640027455e 100644 --- a/llvm/lib/ProfileData/InstrProf.cpp +++ b/llvm/lib/ProfileData/InstrProf.cpp @@ -921,7 +921,7 @@ std::vector TemporalProfTraceTy::createBPFunctionNodes( if (Timestamp < Trace.FunctionNameRefs.size()) FunctionIds.insert(Trace.FunctionNameRefs[Timestamp]); - int N = std::ceil(std::log2(LargestTraceSize)); + const int N = Log2_64(LargestTraceSize) + 1; // TODO: We need to use the Trace.Weight field to give more weight to more // important utilities @@ -929,8 +929,8 @@ std::vector TemporalProfTraceTy::createBPFunctionNodes( for (size_t TraceIdx = 0; TraceIdx < Traces.size(); TraceIdx++) { auto &Trace = Traces[TraceIdx].FunctionNameRefs; for (size_t Timestamp = 0; Timestamp < Trace.size(); Timestamp++) { - for (int I = std::floor(std::log2(Timestamp + 1)); I < N; I++) { - auto &FunctionId = Trace[Timestamp]; + for (int I = Log2_64(Timestamp + 1); I < N; I++) { + auto FunctionId = Trace[Timestamp]; UtilityNodeT GroupId = TraceIdx * N + I; FuncGroups[FunctionId].push_back(GroupId); } @@ -938,7 +938,7 @@ std::vector TemporalProfTraceTy::createBPFunctionNodes( } std::vector Nodes; - for (auto &Id : FunctionIds) { + for (auto Id : FunctionIds) { auto &UNs = FuncGroups[Id]; llvm::sort(UNs); UNs.erase(std::unique(UNs.begin(), UNs.end()), UNs.end()); diff --git a/llvm/lib/Remarks/YAMLRemarkParser.cpp b/llvm/lib/Remarks/YAMLRemarkParser.cpp index 218b6691398..a287ef57425 100644 --- a/llvm/lib/Remarks/YAMLRemarkParser.cpp +++ b/llvm/lib/Remarks/YAMLRemarkParser.cpp @@ -302,11 +302,8 @@ Expected YAMLRemarkParser::parseStr(yaml::KeyValueNode &Node) { } else Result = Value->getRawValue(); - if (Result.front() == '\'') - Result = Result.drop_front(); - - if (Result.back() == '\'') - Result = Result.drop_back(); + Result.consume_front("\'"); + Result.consume_back("\'"); return Result; } @@ -456,11 +453,8 @@ Expected YAMLStrTabRemarkParser::parseStr(yaml::KeyValueNode &Node) { else return Str.takeError(); - if (Result.front() == '\'') - Result = Result.drop_front(); - - if (Result.back() == '\'') - Result = Result.drop_back(); + Result.consume_front("\'"); + Result.consume_back("\'"); return Result; } diff --git a/llvm/lib/Support/BalancedPartitioning.cpp b/llvm/lib/Support/BalancedPartitioning.cpp index 5843be94991..cb6ba611799 100644 --- a/llvm/lib/Support/BalancedPartitioning.cpp +++ b/llvm/lib/Support/BalancedPartitioning.cpp @@ -117,7 +117,7 @@ void BalancedPartitioning::bisect(const FunctionNodeRange Nodes, if (NumNodes <= 1 || RecDepth >= Config.SplitDepth) { // We've reach the lowest level of the recursion tree. Fall back to the // original order and assign to buckets. - llvm::stable_sort(Nodes, [](const auto &L, const auto &R) { + llvm::sort(Nodes, [](const auto &L, const auto &R) { return L.InputOrderIndex < R.InputOrderIndex; }); for (auto &N : Nodes) @@ -167,26 +167,22 @@ void BalancedPartitioning::runIterations(const FunctionNodeRange Nodes, unsigned RightBucket, std::mt19937 &RNG) const { unsigned NumNodes = std::distance(Nodes.begin(), Nodes.end()); - DenseMap UtilityNodeDegree; + DenseMap UtilityNodeIndex; for (auto &N : Nodes) for (auto &UN : N.UtilityNodes) - ++UtilityNodeDegree[UN]; + ++UtilityNodeIndex[UN]; // Remove utility nodes if they have just one edge or are connected to all // functions for (auto &N : Nodes) llvm::erase_if(N.UtilityNodes, [&](auto &UN) { - return UtilityNodeDegree[UN] <= 1 || UtilityNodeDegree[UN] >= NumNodes; + return UtilityNodeIndex[UN] == 1 || UtilityNodeIndex[UN] == NumNodes; }); // Renumber utility nodes so they can be used to index into Signatures - DenseMap UtilityNodeIndex; + UtilityNodeIndex.clear(); for (auto &N : Nodes) for (auto &UN : N.UtilityNodes) - if (!UtilityNodeIndex.count(UN)) - UtilityNodeIndex[UN] = UtilityNodeIndex.size(); - for (auto &N : Nodes) - for (auto &UN : N.UtilityNodes) - UN = UtilityNodeIndex[UN]; + UN = UtilityNodeIndex.insert({UN, UtilityNodeIndex.size()}).first->second; // Initialize signatures SignaturesT Signatures(/*Size=*/UtilityNodeIndex.size()); diff --git a/llvm/lib/Support/Caching.cpp b/llvm/lib/Support/Caching.cpp index 628e23e1cb3..1ef51db218e 100644 --- a/llvm/lib/Support/Caching.cpp +++ b/llvm/lib/Support/Caching.cpp @@ -163,8 +163,8 @@ Expected llvm::localCache(const Twine &CacheNameRef, // This CacheStream will move the temporary file into the cache when done. return std::make_unique( std::make_unique(Temp->FD, /* ShouldClose */ false), - AddBuffer, std::move(*Temp), std::string(EntryPath.str()), - ModuleName.str(), Task); + AddBuffer, std::move(*Temp), std::string(EntryPath), ModuleName.str(), + Task); }; }; } diff --git a/llvm/lib/Support/CommandLine.cpp b/llvm/lib/Support/CommandLine.cpp index 7360d733d96..cb9eb9183f7 100644 --- a/llvm/lib/Support/CommandLine.cpp +++ b/llvm/lib/Support/CommandLine.cpp @@ -164,10 +164,7 @@ public: // This collects the different subcommands that have been registered. SmallPtrSet RegisteredSubCommands; - CommandLineParser() { - registerSubCommand(&SubCommand::getTopLevel()); - registerSubCommand(&SubCommand::getAll()); - } + CommandLineParser() { registerSubCommand(&SubCommand::getTopLevel()); } void ResetAllOptionOccurrences(); @@ -183,6 +180,7 @@ public: if (Opt.Subs.size() == 1 && *Opt.Subs.begin() == &SubCommand::getAll()) { for (auto *SC : RegisteredSubCommands) Action(*SC); + Action(SubCommand::getAll()); return; } for (auto *SC : Opt.Subs) { @@ -348,15 +346,15 @@ public: // For all options that have been registered for all subcommands, add the // option to this subcommand now. - if (sub != &SubCommand::getAll()) { - for (auto &E : SubCommand::getAll().OptionsMap) { - Option *O = E.second; - if ((O->isPositional() || O->isSink() || O->isConsumeAfter()) || - O->hasArgStr()) - addOption(O, sub); - else - addLiteralOption(*O, sub, E.first()); - } + assert(sub != &SubCommand::getAll() && + "SubCommand::getAll() should not be registered"); + for (auto &E : SubCommand::getAll().OptionsMap) { + Option *O = E.second; + if ((O->isPositional() || O->isSink() || O->isConsumeAfter()) || + O->hasArgStr()) + addOption(O, sub); + else + addLiteralOption(*O, sub, E.first()); } } @@ -384,7 +382,6 @@ public: SubCommand::getTopLevel().reset(); SubCommand::getAll().reset(); registerSubCommand(&SubCommand::getTopLevel()); - registerSubCommand(&SubCommand::getAll()); DefaultOptions.clear(); } @@ -532,8 +529,8 @@ SubCommand *CommandLineParser::LookupSubCommand(StringRef Name, // Find a subcommand with the edit distance == 1. SubCommand *NearestMatch = nullptr; for (auto *S : RegisteredSubCommands) { - if (S == &SubCommand::getAll()) - continue; + assert(S != &SubCommand::getAll() && + "SubCommand::getAll() is not expected in RegisteredSubCommands"); if (S->getName().empty()) continue; @@ -1633,10 +1630,8 @@ bool CommandLineParser::ParseCommandLineOptions(int argc, // otherwise feed it to the eating positional. ArgName = StringRef(argv[i] + 1); // Eat second dash. - if (!ArgName.empty() && ArgName[0] == '-') { + if (ArgName.consume_front("-")) HaveDoubleDash = true; - ArgName = ArgName.substr(1); - } Handler = LookupLongOption(*ChosenSubCommand, ArgName, Value, LongOptionsUseDoubleDash, HaveDoubleDash); @@ -1647,10 +1642,8 @@ bool CommandLineParser::ParseCommandLineOptions(int argc, } else { // We start with a '-', must be an argument. ArgName = StringRef(argv[i] + 1); // Eat second dash. - if (!ArgName.empty() && ArgName[0] == '-') { + if (ArgName.consume_front("-")) HaveDoubleDash = true; - ArgName = ArgName.substr(1); - } Handler = LookupLongOption(*ChosenSubCommand, ArgName, Value, LongOptionsUseDoubleDash, HaveDoubleDash); diff --git a/llvm/lib/Support/FileCollector.cpp b/llvm/lib/Support/FileCollector.cpp index c0ce6b5d74e..92bcdf00b8a 100644 --- a/llvm/lib/Support/FileCollector.cpp +++ b/llvm/lib/Support/FileCollector.cpp @@ -71,7 +71,7 @@ void FileCollector::PathCanonicalizer::updateWithRealPath( // cases? What if there is nothing on disk? if (sys::fs::real_path(Directory, RealPath)) return; - CachedDirs[Directory] = std::string(RealPath.str()); + CachedDirs[Directory] = std::string(RealPath); } else { RealPath = DirWithSymlink->second; } diff --git a/llvm/lib/Support/FormatVariadic.cpp b/llvm/lib/Support/FormatVariadic.cpp index 10de7f16dcf..7bbc80e14c9 100644 --- a/llvm/lib/Support/FormatVariadic.cpp +++ b/llvm/lib/Support/FormatVariadic.cpp @@ -72,8 +72,7 @@ formatv_object_base::parseReplacementItem(StringRef Spec) { return ReplacementItem{}; } RepString = RepString.trim(); - if (!RepString.empty() && RepString.front() == ',') { - RepString = RepString.drop_front(); + if (RepString.consume_front(",")) { if (!consumeFieldLayout(RepString, Where, Align, Pad)) assert(false && "Invalid replacement field layout specification!"); } diff --git a/llvm/lib/Support/GraphWriter.cpp b/llvm/lib/Support/GraphWriter.cpp index 57559ad0830..0c7aacb2fe2 100644 --- a/llvm/lib/Support/GraphWriter.cpp +++ b/llvm/lib/Support/GraphWriter.cpp @@ -128,7 +128,7 @@ std::string llvm::createGraphFilename(const Twine &Name, int &FD) { } errs() << "Writing '" << Filename << "'... "; - return std::string(Filename.str()); + return std::string(Filename); } // Execute the graph viewer. Return true if there were errors. diff --git a/llvm/lib/Support/InitLLVM.cpp b/llvm/lib/Support/InitLLVM.cpp index 7f475f42f3c..b7e463a1912 100644 --- a/llvm/lib/Support/InitLLVM.cpp +++ b/llvm/lib/Support/InitLLVM.cpp @@ -38,6 +38,11 @@ using namespace llvm::sys; InitLLVM::InitLLVM(int &Argc, const char **&Argv, bool InstallPipeSignalExitHandler) { +#ifndef NDEBUG + static std::atomic Initialized{false}; + assert(!Initialized && "InitLLVM was already initialized!"); + Initialized = true; +#endif #ifdef __MVS__ // Bring stdin/stdout/stderr into a known state. sys::AddSignalHandler(CleanupStdHandles, nullptr); diff --git a/llvm/lib/Support/LockFileManager.cpp b/llvm/lib/Support/LockFileManager.cpp index b64d4830277..a2b0fe8ca8f 100644 --- a/llvm/lib/Support/LockFileManager.cpp +++ b/llvm/lib/Support/LockFileManager.cpp @@ -162,7 +162,7 @@ LockFileManager::LockFileManager(StringRef FileName) this->FileName = FileName; if (std::error_code EC = sys::fs::make_absolute(this->FileName)) { std::string S("failed to obtain absolute path for "); - S.append(std::string(this->FileName.str())); + S.append(std::string(this->FileName)); setError(EC, S); return; } @@ -181,7 +181,7 @@ LockFileManager::LockFileManager(StringRef FileName) if (std::error_code EC = sys::fs::createUniqueFile( UniqueLockFileName, UniqueLockFileID, UniqueLockFileName)) { std::string S("failed to create unique file "); - S.append(std::string(UniqueLockFileName.str())); + S.append(std::string(UniqueLockFileName)); setError(EC, S); return; } @@ -202,7 +202,7 @@ LockFileManager::LockFileManager(StringRef FileName) // We failed to write out PID, so report the error, remove the // unique lock file, and fail. std::string S("failed to write to "); - S.append(std::string(UniqueLockFileName.str())); + S.append(std::string(UniqueLockFileName)); setError(Out.error(), S); sys::fs::remove(UniqueLockFileName); return; @@ -248,7 +248,7 @@ LockFileManager::LockFileManager(StringRef FileName) // ownership. if ((EC = sys::fs::remove(LockFileName))) { std::string S("failed to remove lockfile "); - S.append(std::string(UniqueLockFileName.str())); + S.append(std::string(UniqueLockFileName)); setError(EC, S); return; } diff --git a/llvm/lib/Support/Path.cpp b/llvm/lib/Support/Path.cpp index c2456dcac09..c8de2c0625a 100644 --- a/llvm/lib/Support/Path.cpp +++ b/llvm/lib/Support/Path.cpp @@ -104,7 +104,7 @@ namespace { if (is_style_windows(style)) { if (pos == StringRef::npos) - pos = str.find_last_of(':', str.size() - 2); + pos = str.find_last_of(':', str.size() - 1); } if (pos == StringRef::npos || (pos == 1 && is_separator(str[0], style))) @@ -1145,7 +1145,7 @@ void directory_entry::replace_filename(const Twine &Filename, file_type Type, basic_file_status Status) { SmallString<128> PathStr = path::parent_path(Path); path::append(PathStr, Filename); - this->Path = std::string(PathStr.str()); + this->Path = std::string(PathStr); this->Type = Type; this->Status = Status; } diff --git a/llvm/lib/Support/Process.cpp b/llvm/lib/Support/Process.cpp index 30c64d3ed9e..f81c13970d5 100644 --- a/llvm/lib/Support/Process.cpp +++ b/llvm/lib/Support/Process.cpp @@ -59,7 +59,7 @@ Process::FindInEnvPath(StringRef EnvName, StringRef FileName, SmallString<128> FilePath(Dir); path::append(FilePath, FileName); if (fs::exists(Twine(FilePath))) { - FoundPath = std::string(FilePath.str()); + FoundPath = std::string(FilePath); break; } } diff --git a/llvm/lib/Support/RISCVISAInfo.cpp b/llvm/lib/Support/RISCVISAInfo.cpp index 390d950486a..3c02492e99f 100644 --- a/llvm/lib/Support/RISCVISAInfo.cpp +++ b/llvm/lib/Support/RISCVISAInfo.cpp @@ -55,6 +55,7 @@ static const RISCVSupportedExtension SupportedExtensions[] = { {"m", {2, 0}}, {"smaia", {1, 0}}, + {"smepmp", {1, 0}}, {"ssaia", {1, 0}}, {"svinval", {1, 0}}, {"svnapot", {1, 0}}, @@ -88,6 +89,8 @@ static const RISCVSupportedExtension SupportedExtensions[] = { {"xtheadvdot", {1, 0}}, {"xventanacondops", {1, 0}}, + {"za128rs", {1, 0}}, + {"za64rs", {1, 0}}, {"zawrs", {1, 0}}, {"zba", {1, 0}}, @@ -116,9 +119,14 @@ static const RISCVSupportedExtension SupportedExtensions[] = { {"zhinx", {1, 0}}, {"zhinxmin", {1, 0}}, + {"zic64b", {1, 0}}, {"zicbom", {1, 0}}, {"zicbop", {1, 0}}, {"zicboz", {1, 0}}, + {"ziccamoa", {1, 0}}, + {"ziccif", {1, 0}}, + {"zicclsm", {1, 0}}, + {"ziccrse", {1, 0}}, {"zicntr", {2, 0}}, {"zicsr", {2, 0}}, {"zifencei", {2, 0}}, @@ -187,7 +195,7 @@ static const RISCVSupportedExtension SupportedExperimentalExtensions[] = { {"zcmop", {0, 2}}, - {"zfbfmin", {0, 8}}, + {"zfbfmin", {1, 0}}, {"zicfilp", {0, 4}}, {"zicfiss", {0, 4}}, @@ -198,8 +206,8 @@ static const RISCVSupportedExtension SupportedExperimentalExtensions[] = { {"ztso", {0, 1}}, - {"zvfbfmin", {0, 8}}, - {"zvfbfwma", {0, 8}}, + {"zvfbfmin", {1, 0}}, + {"zvfbfwma", {1, 0}}, }; static void verifyTables() { @@ -1278,20 +1286,20 @@ RISCVISAInfo::postProcessAndChecking(std::unique_ptr &&ISAInfo) { StringRef RISCVISAInfo::computeDefaultABI() const { if (XLen == 32) { + if (hasExtension("e")) + return "ilp32e"; if (hasExtension("d")) return "ilp32d"; if (hasExtension("f")) return "ilp32f"; - if (hasExtension("e")) - return "ilp32e"; return "ilp32"; } else if (XLen == 64) { + if (hasExtension("e")) + return "lp64e"; if (hasExtension("d")) return "lp64d"; if (hasExtension("f")) return "lp64f"; - if (hasExtension("e")) - return "lp64e"; return "lp64"; } llvm_unreachable("Invalid XLEN"); diff --git a/llvm/lib/Support/SmallVector.cpp b/llvm/lib/Support/SmallVector.cpp index f7e7e80332c..b6ce3784204 100644 --- a/llvm/lib/Support/SmallVector.cpp +++ b/llvm/lib/Support/SmallVector.cpp @@ -153,8 +153,7 @@ void SmallVectorBase::grow_pod(void *FirstEl, size_t MinSize, NewElts = replaceAllocation(NewElts, TSize, NewCapacity, size()); } - this->BeginX = NewElts; - this->Capacity = NewCapacity; + this->set_allocation_range(NewElts, NewCapacity); } template class llvm::SmallVectorBase; diff --git a/llvm/lib/Support/StringRef.cpp b/llvm/lib/Support/StringRef.cpp index feee47ca693..945ae378eb9 100644 --- a/llvm/lib/Support/StringRef.cpp +++ b/llvm/lib/Support/StringRef.cpp @@ -388,20 +388,14 @@ static unsigned GetAutoSenseRadix(StringRef &Str) { if (Str.empty()) return 10; - if (Str.starts_with("0x") || Str.starts_with("0X")) { - Str = Str.substr(2); + if (Str.consume_front_insensitive("0x")) return 16; - } - if (Str.starts_with("0b") || Str.starts_with("0B")) { - Str = Str.substr(2); + if (Str.consume_front_insensitive("0b")) return 2; - } - if (Str.starts_with("0o")) { - Str = Str.substr(2); + if (Str.consume_front("0o")) return 8; - } if (Str[0] == '0' && Str.size() > 1 && isDigit(Str[1])) { Str = Str.substr(1); @@ -523,8 +517,7 @@ bool StringRef::consumeInteger(unsigned Radix, APInt &Result) { // Skip leading zeroes. This can be a significant improvement if // it means we don't need > 64 bits. - while (!Str.empty() && Str.front() == '0') - Str = Str.substr(1); + Str = Str.ltrim('0'); // If it was nothing but zeroes.... if (Str.empty()) { diff --git a/llvm/lib/Support/Unicode.cpp b/llvm/lib/Support/Unicode.cpp index 621ffc71218..288b75c872e 100644 --- a/llvm/lib/Support/Unicode.cpp +++ b/llvm/lib/Support/Unicode.cpp @@ -25,7 +25,7 @@ namespace unicode { /// it's actually displayed on most terminals. \return true if the character is /// considered printable. bool isPrintable(int UCS) { - // https://unicode.org/Public/15.0.0/ucdxml/ + // https://unicode.org/Public/15.1.0/ucdxml/ static const UnicodeCharRange PrintableRanges[] = { {0x0020, 0x007E}, {0x00A0, 0x00AC}, {0x00AE, 0x0377}, {0x037A, 0x037F}, {0x0384, 0x038A}, {0x038C, 0x038C}, @@ -119,151 +119,152 @@ bool isPrintable(int UCS) { {0x2DB8, 0x2DBE}, {0x2DC0, 0x2DC6}, {0x2DC8, 0x2DCE}, {0x2DD0, 0x2DD6}, {0x2DD8, 0x2DDE}, {0x2DE0, 0x2E5D}, {0x2E80, 0x2E99}, {0x2E9B, 0x2EF3}, {0x2F00, 0x2FD5}, - {0x2FF0, 0x2FFB}, {0x3000, 0x303F}, {0x3041, 0x3096}, - {0x3099, 0x30FF}, {0x3105, 0x312F}, {0x3131, 0x318E}, - {0x3190, 0x31E3}, {0x31F0, 0x321E}, {0x3220, 0xA48C}, - {0xA490, 0xA4C6}, {0xA4D0, 0xA62B}, {0xA640, 0xA6F7}, - {0xA700, 0xA7CA}, {0xA7D0, 0xA7D1}, {0xA7D3, 0xA7D3}, - {0xA7D5, 0xA7D9}, {0xA7F2, 0xA82C}, {0xA830, 0xA839}, - {0xA840, 0xA877}, {0xA880, 0xA8C5}, {0xA8CE, 0xA8D9}, - {0xA8E0, 0xA953}, {0xA95F, 0xA97C}, {0xA980, 0xA9CD}, - {0xA9CF, 0xA9D9}, {0xA9DE, 0xA9FE}, {0xAA00, 0xAA36}, - {0xAA40, 0xAA4D}, {0xAA50, 0xAA59}, {0xAA5C, 0xAAC2}, - {0xAADB, 0xAAF6}, {0xAB01, 0xAB06}, {0xAB09, 0xAB0E}, - {0xAB11, 0xAB16}, {0xAB20, 0xAB26}, {0xAB28, 0xAB2E}, - {0xAB30, 0xAB6B}, {0xAB70, 0xABED}, {0xABF0, 0xABF9}, - {0xAC00, 0xD7A3}, {0xD7B0, 0xD7C6}, {0xD7CB, 0xD7FB}, - {0xF900, 0xFA6D}, {0xFA70, 0xFAD9}, {0xFB00, 0xFB06}, - {0xFB13, 0xFB17}, {0xFB1D, 0xFB36}, {0xFB38, 0xFB3C}, - {0xFB3E, 0xFB3E}, {0xFB40, 0xFB41}, {0xFB43, 0xFB44}, - {0xFB46, 0xFBC2}, {0xFBD3, 0xFD8F}, {0xFD92, 0xFDC7}, - {0xFDCF, 0xFDCF}, {0xFDF0, 0xFE19}, {0xFE20, 0xFE52}, - {0xFE54, 0xFE66}, {0xFE68, 0xFE6B}, {0xFE70, 0xFE74}, - {0xFE76, 0xFEFC}, {0xFF01, 0xFFBE}, {0xFFC2, 0xFFC7}, - {0xFFCA, 0xFFCF}, {0xFFD2, 0xFFD7}, {0xFFDA, 0xFFDC}, - {0xFFE0, 0xFFE6}, {0xFFE8, 0xFFEE}, {0xFFFC, 0xFFFD}, - {0x10000, 0x1000B}, {0x1000D, 0x10026}, {0x10028, 0x1003A}, - {0x1003C, 0x1003D}, {0x1003F, 0x1004D}, {0x10050, 0x1005D}, - {0x10080, 0x100FA}, {0x10100, 0x10102}, {0x10107, 0x10133}, - {0x10137, 0x1018E}, {0x10190, 0x1019C}, {0x101A0, 0x101A0}, - {0x101D0, 0x101FD}, {0x10280, 0x1029C}, {0x102A0, 0x102D0}, - {0x102E0, 0x102FB}, {0x10300, 0x10323}, {0x1032D, 0x1034A}, - {0x10350, 0x1037A}, {0x10380, 0x1039D}, {0x1039F, 0x103C3}, - {0x103C8, 0x103D5}, {0x10400, 0x1049D}, {0x104A0, 0x104A9}, - {0x104B0, 0x104D3}, {0x104D8, 0x104FB}, {0x10500, 0x10527}, - {0x10530, 0x10563}, {0x1056F, 0x1057A}, {0x1057C, 0x1058A}, - {0x1058C, 0x10592}, {0x10594, 0x10595}, {0x10597, 0x105A1}, - {0x105A3, 0x105B1}, {0x105B3, 0x105B9}, {0x105BB, 0x105BC}, - {0x10600, 0x10736}, {0x10740, 0x10755}, {0x10760, 0x10767}, - {0x10780, 0x10785}, {0x10787, 0x107B0}, {0x107B2, 0x107BA}, - {0x10800, 0x10805}, {0x10808, 0x10808}, {0x1080A, 0x10835}, - {0x10837, 0x10838}, {0x1083C, 0x1083C}, {0x1083F, 0x10855}, - {0x10857, 0x1089E}, {0x108A7, 0x108AF}, {0x108E0, 0x108F2}, - {0x108F4, 0x108F5}, {0x108FB, 0x1091B}, {0x1091F, 0x10939}, - {0x1093F, 0x1093F}, {0x10980, 0x109B7}, {0x109BC, 0x109CF}, - {0x109D2, 0x10A03}, {0x10A05, 0x10A06}, {0x10A0C, 0x10A13}, - {0x10A15, 0x10A17}, {0x10A19, 0x10A35}, {0x10A38, 0x10A3A}, - {0x10A3F, 0x10A48}, {0x10A50, 0x10A58}, {0x10A60, 0x10A9F}, - {0x10AC0, 0x10AE6}, {0x10AEB, 0x10AF6}, {0x10B00, 0x10B35}, - {0x10B39, 0x10B55}, {0x10B58, 0x10B72}, {0x10B78, 0x10B91}, - {0x10B99, 0x10B9C}, {0x10BA9, 0x10BAF}, {0x10C00, 0x10C48}, - {0x10C80, 0x10CB2}, {0x10CC0, 0x10CF2}, {0x10CFA, 0x10D27}, - {0x10D30, 0x10D39}, {0x10E60, 0x10E7E}, {0x10E80, 0x10EA9}, - {0x10EAB, 0x10EAD}, {0x10EB0, 0x10EB1}, {0x10EFD, 0x10F27}, - {0x10F30, 0x10F59}, {0x10F70, 0x10F89}, {0x10FB0, 0x10FCB}, - {0x10FE0, 0x10FF6}, {0x11000, 0x1104D}, {0x11052, 0x11075}, - {0x1107F, 0x110BC}, {0x110BE, 0x110C2}, {0x110D0, 0x110E8}, - {0x110F0, 0x110F9}, {0x11100, 0x11134}, {0x11136, 0x11147}, - {0x11150, 0x11176}, {0x11180, 0x111DF}, {0x111E1, 0x111F4}, - {0x11200, 0x11211}, {0x11213, 0x11241}, {0x11280, 0x11286}, - {0x11288, 0x11288}, {0x1128A, 0x1128D}, {0x1128F, 0x1129D}, - {0x1129F, 0x112A9}, {0x112B0, 0x112EA}, {0x112F0, 0x112F9}, - {0x11300, 0x11303}, {0x11305, 0x1130C}, {0x1130F, 0x11310}, - {0x11313, 0x11328}, {0x1132A, 0x11330}, {0x11332, 0x11333}, - {0x11335, 0x11339}, {0x1133B, 0x11344}, {0x11347, 0x11348}, - {0x1134B, 0x1134D}, {0x11350, 0x11350}, {0x11357, 0x11357}, - {0x1135D, 0x11363}, {0x11366, 0x1136C}, {0x11370, 0x11374}, - {0x11400, 0x1145B}, {0x1145D, 0x11461}, {0x11480, 0x114C7}, - {0x114D0, 0x114D9}, {0x11580, 0x115B5}, {0x115B8, 0x115DD}, - {0x11600, 0x11644}, {0x11650, 0x11659}, {0x11660, 0x1166C}, - {0x11680, 0x116B9}, {0x116C0, 0x116C9}, {0x11700, 0x1171A}, - {0x1171D, 0x1172B}, {0x11730, 0x11746}, {0x11800, 0x1183B}, - {0x118A0, 0x118F2}, {0x118FF, 0x11906}, {0x11909, 0x11909}, - {0x1190C, 0x11913}, {0x11915, 0x11916}, {0x11918, 0x11935}, - {0x11937, 0x11938}, {0x1193B, 0x11946}, {0x11950, 0x11959}, - {0x119A0, 0x119A7}, {0x119AA, 0x119D7}, {0x119DA, 0x119E4}, - {0x11A00, 0x11A47}, {0x11A50, 0x11AA2}, {0x11AB0, 0x11AF8}, - {0x11B00, 0x11B09}, {0x11C00, 0x11C08}, {0x11C0A, 0x11C36}, - {0x11C38, 0x11C45}, {0x11C50, 0x11C6C}, {0x11C70, 0x11C8F}, - {0x11C92, 0x11CA7}, {0x11CA9, 0x11CB6}, {0x11D00, 0x11D06}, - {0x11D08, 0x11D09}, {0x11D0B, 0x11D36}, {0x11D3A, 0x11D3A}, - {0x11D3C, 0x11D3D}, {0x11D3F, 0x11D47}, {0x11D50, 0x11D59}, - {0x11D60, 0x11D65}, {0x11D67, 0x11D68}, {0x11D6A, 0x11D8E}, - {0x11D90, 0x11D91}, {0x11D93, 0x11D98}, {0x11DA0, 0x11DA9}, - {0x11EE0, 0x11EF8}, {0x11F00, 0x11F10}, {0x11F12, 0x11F3A}, - {0x11F3E, 0x11F59}, {0x11FB0, 0x11FB0}, {0x11FC0, 0x11FF1}, - {0x11FFF, 0x12399}, {0x12400, 0x1246E}, {0x12470, 0x12474}, - {0x12480, 0x12543}, {0x12F90, 0x12FF2}, {0x13000, 0x1342F}, - {0x13440, 0x13455}, {0x14400, 0x14646}, {0x16800, 0x16A38}, - {0x16A40, 0x16A5E}, {0x16A60, 0x16A69}, {0x16A6E, 0x16ABE}, - {0x16AC0, 0x16AC9}, {0x16AD0, 0x16AED}, {0x16AF0, 0x16AF5}, - {0x16B00, 0x16B45}, {0x16B50, 0x16B59}, {0x16B5B, 0x16B61}, - {0x16B63, 0x16B77}, {0x16B7D, 0x16B8F}, {0x16E40, 0x16E9A}, - {0x16F00, 0x16F4A}, {0x16F4F, 0x16F87}, {0x16F8F, 0x16F9F}, - {0x16FE0, 0x16FE4}, {0x16FF0, 0x16FF1}, {0x17000, 0x187F7}, - {0x18800, 0x18CD5}, {0x18D00, 0x18D08}, {0x1AFF0, 0x1AFF3}, - {0x1AFF5, 0x1AFFB}, {0x1AFFD, 0x1AFFE}, {0x1B000, 0x1B122}, - {0x1B132, 0x1B132}, {0x1B150, 0x1B152}, {0x1B155, 0x1B155}, - {0x1B164, 0x1B167}, {0x1B170, 0x1B2FB}, {0x1BC00, 0x1BC6A}, - {0x1BC70, 0x1BC7C}, {0x1BC80, 0x1BC88}, {0x1BC90, 0x1BC99}, - {0x1BC9C, 0x1BC9F}, {0x1CF00, 0x1CF2D}, {0x1CF30, 0x1CF46}, - {0x1CF50, 0x1CFC3}, {0x1D000, 0x1D0F5}, {0x1D100, 0x1D126}, - {0x1D129, 0x1D172}, {0x1D17B, 0x1D1EA}, {0x1D200, 0x1D245}, - {0x1D2C0, 0x1D2D3}, {0x1D2E0, 0x1D2F3}, {0x1D300, 0x1D356}, - {0x1D360, 0x1D378}, {0x1D400, 0x1D454}, {0x1D456, 0x1D49C}, - {0x1D49E, 0x1D49F}, {0x1D4A2, 0x1D4A2}, {0x1D4A5, 0x1D4A6}, - {0x1D4A9, 0x1D4AC}, {0x1D4AE, 0x1D4B9}, {0x1D4BB, 0x1D4BB}, - {0x1D4BD, 0x1D4C3}, {0x1D4C5, 0x1D505}, {0x1D507, 0x1D50A}, - {0x1D50D, 0x1D514}, {0x1D516, 0x1D51C}, {0x1D51E, 0x1D539}, - {0x1D53B, 0x1D53E}, {0x1D540, 0x1D544}, {0x1D546, 0x1D546}, - {0x1D54A, 0x1D550}, {0x1D552, 0x1D6A5}, {0x1D6A8, 0x1D7CB}, - {0x1D7CE, 0x1DA8B}, {0x1DA9B, 0x1DA9F}, {0x1DAA1, 0x1DAAF}, - {0x1DF00, 0x1DF1E}, {0x1DF25, 0x1DF2A}, {0x1E000, 0x1E006}, - {0x1E008, 0x1E018}, {0x1E01B, 0x1E021}, {0x1E023, 0x1E024}, - {0x1E026, 0x1E02A}, {0x1E030, 0x1E06D}, {0x1E08F, 0x1E08F}, - {0x1E100, 0x1E12C}, {0x1E130, 0x1E13D}, {0x1E140, 0x1E149}, - {0x1E14E, 0x1E14F}, {0x1E290, 0x1E2AE}, {0x1E2C0, 0x1E2F9}, - {0x1E2FF, 0x1E2FF}, {0x1E4D0, 0x1E4F9}, {0x1E7E0, 0x1E7E6}, - {0x1E7E8, 0x1E7EB}, {0x1E7ED, 0x1E7EE}, {0x1E7F0, 0x1E7FE}, - {0x1E800, 0x1E8C4}, {0x1E8C7, 0x1E8D6}, {0x1E900, 0x1E94B}, - {0x1E950, 0x1E959}, {0x1E95E, 0x1E95F}, {0x1EC71, 0x1ECB4}, - {0x1ED01, 0x1ED3D}, {0x1EE00, 0x1EE03}, {0x1EE05, 0x1EE1F}, - {0x1EE21, 0x1EE22}, {0x1EE24, 0x1EE24}, {0x1EE27, 0x1EE27}, - {0x1EE29, 0x1EE32}, {0x1EE34, 0x1EE37}, {0x1EE39, 0x1EE39}, - {0x1EE3B, 0x1EE3B}, {0x1EE42, 0x1EE42}, {0x1EE47, 0x1EE47}, - {0x1EE49, 0x1EE49}, {0x1EE4B, 0x1EE4B}, {0x1EE4D, 0x1EE4F}, - {0x1EE51, 0x1EE52}, {0x1EE54, 0x1EE54}, {0x1EE57, 0x1EE57}, - {0x1EE59, 0x1EE59}, {0x1EE5B, 0x1EE5B}, {0x1EE5D, 0x1EE5D}, - {0x1EE5F, 0x1EE5F}, {0x1EE61, 0x1EE62}, {0x1EE64, 0x1EE64}, - {0x1EE67, 0x1EE6A}, {0x1EE6C, 0x1EE72}, {0x1EE74, 0x1EE77}, - {0x1EE79, 0x1EE7C}, {0x1EE7E, 0x1EE7E}, {0x1EE80, 0x1EE89}, - {0x1EE8B, 0x1EE9B}, {0x1EEA1, 0x1EEA3}, {0x1EEA5, 0x1EEA9}, - {0x1EEAB, 0x1EEBB}, {0x1EEF0, 0x1EEF1}, {0x1F000, 0x1F02B}, - {0x1F030, 0x1F093}, {0x1F0A0, 0x1F0AE}, {0x1F0B1, 0x1F0BF}, - {0x1F0C1, 0x1F0CF}, {0x1F0D1, 0x1F0F5}, {0x1F100, 0x1F1AD}, - {0x1F1E6, 0x1F202}, {0x1F210, 0x1F23B}, {0x1F240, 0x1F248}, - {0x1F250, 0x1F251}, {0x1F260, 0x1F265}, {0x1F300, 0x1F6D7}, - {0x1F6DC, 0x1F6EC}, {0x1F6F0, 0x1F6FC}, {0x1F700, 0x1F776}, - {0x1F77B, 0x1F7D9}, {0x1F7E0, 0x1F7EB}, {0x1F7F0, 0x1F7F0}, - {0x1F800, 0x1F80B}, {0x1F810, 0x1F847}, {0x1F850, 0x1F859}, - {0x1F860, 0x1F887}, {0x1F890, 0x1F8AD}, {0x1F8B0, 0x1F8B1}, - {0x1F900, 0x1FA53}, {0x1FA60, 0x1FA6D}, {0x1FA70, 0x1FA7C}, - {0x1FA80, 0x1FA88}, {0x1FA90, 0x1FABD}, {0x1FABF, 0x1FAC5}, - {0x1FACE, 0x1FADB}, {0x1FAE0, 0x1FAE8}, {0x1FAF0, 0x1FAF8}, - {0x1FB00, 0x1FB92}, {0x1FB94, 0x1FBCA}, {0x1FBF0, 0x1FBF9}, - {0x20000, 0x2A6DF}, {0x2A700, 0x2B739}, {0x2B740, 0x2B81D}, - {0x2B820, 0x2CEA1}, {0x2CEB0, 0x2EBE0}, {0x2F800, 0x2FA1D}, - {0x30000, 0x3134A}, {0x31350, 0x323AF}, {0xE0100, 0xE01EF}}; + {0x2FF0, 0x303F}, {0x3041, 0x3096}, {0x3099, 0x30FF}, + {0x3105, 0x312F}, {0x3131, 0x318E}, {0x3190, 0x31E3}, + {0x31EF, 0x321E}, {0x3220, 0xA48C}, {0xA490, 0xA4C6}, + {0xA4D0, 0xA62B}, {0xA640, 0xA6F7}, {0xA700, 0xA7CA}, + {0xA7D0, 0xA7D1}, {0xA7D3, 0xA7D3}, {0xA7D5, 0xA7D9}, + {0xA7F2, 0xA82C}, {0xA830, 0xA839}, {0xA840, 0xA877}, + {0xA880, 0xA8C5}, {0xA8CE, 0xA8D9}, {0xA8E0, 0xA953}, + {0xA95F, 0xA97C}, {0xA980, 0xA9CD}, {0xA9CF, 0xA9D9}, + {0xA9DE, 0xA9FE}, {0xAA00, 0xAA36}, {0xAA40, 0xAA4D}, + {0xAA50, 0xAA59}, {0xAA5C, 0xAAC2}, {0xAADB, 0xAAF6}, + {0xAB01, 0xAB06}, {0xAB09, 0xAB0E}, {0xAB11, 0xAB16}, + {0xAB20, 0xAB26}, {0xAB28, 0xAB2E}, {0xAB30, 0xAB6B}, + {0xAB70, 0xABED}, {0xABF0, 0xABF9}, {0xAC00, 0xD7A3}, + {0xD7B0, 0xD7C6}, {0xD7CB, 0xD7FB}, {0xF900, 0xFA6D}, + {0xFA70, 0xFAD9}, {0xFB00, 0xFB06}, {0xFB13, 0xFB17}, + {0xFB1D, 0xFB36}, {0xFB38, 0xFB3C}, {0xFB3E, 0xFB3E}, + {0xFB40, 0xFB41}, {0xFB43, 0xFB44}, {0xFB46, 0xFBC2}, + {0xFBD3, 0xFD8F}, {0xFD92, 0xFDC7}, {0xFDCF, 0xFDCF}, + {0xFDF0, 0xFE19}, {0xFE20, 0xFE52}, {0xFE54, 0xFE66}, + {0xFE68, 0xFE6B}, {0xFE70, 0xFE74}, {0xFE76, 0xFEFC}, + {0xFF01, 0xFFBE}, {0xFFC2, 0xFFC7}, {0xFFCA, 0xFFCF}, + {0xFFD2, 0xFFD7}, {0xFFDA, 0xFFDC}, {0xFFE0, 0xFFE6}, + {0xFFE8, 0xFFEE}, {0xFFFC, 0xFFFD}, {0x10000, 0x1000B}, + {0x1000D, 0x10026}, {0x10028, 0x1003A}, {0x1003C, 0x1003D}, + {0x1003F, 0x1004D}, {0x10050, 0x1005D}, {0x10080, 0x100FA}, + {0x10100, 0x10102}, {0x10107, 0x10133}, {0x10137, 0x1018E}, + {0x10190, 0x1019C}, {0x101A0, 0x101A0}, {0x101D0, 0x101FD}, + {0x10280, 0x1029C}, {0x102A0, 0x102D0}, {0x102E0, 0x102FB}, + {0x10300, 0x10323}, {0x1032D, 0x1034A}, {0x10350, 0x1037A}, + {0x10380, 0x1039D}, {0x1039F, 0x103C3}, {0x103C8, 0x103D5}, + {0x10400, 0x1049D}, {0x104A0, 0x104A9}, {0x104B0, 0x104D3}, + {0x104D8, 0x104FB}, {0x10500, 0x10527}, {0x10530, 0x10563}, + {0x1056F, 0x1057A}, {0x1057C, 0x1058A}, {0x1058C, 0x10592}, + {0x10594, 0x10595}, {0x10597, 0x105A1}, {0x105A3, 0x105B1}, + {0x105B3, 0x105B9}, {0x105BB, 0x105BC}, {0x10600, 0x10736}, + {0x10740, 0x10755}, {0x10760, 0x10767}, {0x10780, 0x10785}, + {0x10787, 0x107B0}, {0x107B2, 0x107BA}, {0x10800, 0x10805}, + {0x10808, 0x10808}, {0x1080A, 0x10835}, {0x10837, 0x10838}, + {0x1083C, 0x1083C}, {0x1083F, 0x10855}, {0x10857, 0x1089E}, + {0x108A7, 0x108AF}, {0x108E0, 0x108F2}, {0x108F4, 0x108F5}, + {0x108FB, 0x1091B}, {0x1091F, 0x10939}, {0x1093F, 0x1093F}, + {0x10980, 0x109B7}, {0x109BC, 0x109CF}, {0x109D2, 0x10A03}, + {0x10A05, 0x10A06}, {0x10A0C, 0x10A13}, {0x10A15, 0x10A17}, + {0x10A19, 0x10A35}, {0x10A38, 0x10A3A}, {0x10A3F, 0x10A48}, + {0x10A50, 0x10A58}, {0x10A60, 0x10A9F}, {0x10AC0, 0x10AE6}, + {0x10AEB, 0x10AF6}, {0x10B00, 0x10B35}, {0x10B39, 0x10B55}, + {0x10B58, 0x10B72}, {0x10B78, 0x10B91}, {0x10B99, 0x10B9C}, + {0x10BA9, 0x10BAF}, {0x10C00, 0x10C48}, {0x10C80, 0x10CB2}, + {0x10CC0, 0x10CF2}, {0x10CFA, 0x10D27}, {0x10D30, 0x10D39}, + {0x10E60, 0x10E7E}, {0x10E80, 0x10EA9}, {0x10EAB, 0x10EAD}, + {0x10EB0, 0x10EB1}, {0x10EFD, 0x10F27}, {0x10F30, 0x10F59}, + {0x10F70, 0x10F89}, {0x10FB0, 0x10FCB}, {0x10FE0, 0x10FF6}, + {0x11000, 0x1104D}, {0x11052, 0x11075}, {0x1107F, 0x110BC}, + {0x110BE, 0x110C2}, {0x110D0, 0x110E8}, {0x110F0, 0x110F9}, + {0x11100, 0x11134}, {0x11136, 0x11147}, {0x11150, 0x11176}, + {0x11180, 0x111DF}, {0x111E1, 0x111F4}, {0x11200, 0x11211}, + {0x11213, 0x11241}, {0x11280, 0x11286}, {0x11288, 0x11288}, + {0x1128A, 0x1128D}, {0x1128F, 0x1129D}, {0x1129F, 0x112A9}, + {0x112B0, 0x112EA}, {0x112F0, 0x112F9}, {0x11300, 0x11303}, + {0x11305, 0x1130C}, {0x1130F, 0x11310}, {0x11313, 0x11328}, + {0x1132A, 0x11330}, {0x11332, 0x11333}, {0x11335, 0x11339}, + {0x1133B, 0x11344}, {0x11347, 0x11348}, {0x1134B, 0x1134D}, + {0x11350, 0x11350}, {0x11357, 0x11357}, {0x1135D, 0x11363}, + {0x11366, 0x1136C}, {0x11370, 0x11374}, {0x11400, 0x1145B}, + {0x1145D, 0x11461}, {0x11480, 0x114C7}, {0x114D0, 0x114D9}, + {0x11580, 0x115B5}, {0x115B8, 0x115DD}, {0x11600, 0x11644}, + {0x11650, 0x11659}, {0x11660, 0x1166C}, {0x11680, 0x116B9}, + {0x116C0, 0x116C9}, {0x11700, 0x1171A}, {0x1171D, 0x1172B}, + {0x11730, 0x11746}, {0x11800, 0x1183B}, {0x118A0, 0x118F2}, + {0x118FF, 0x11906}, {0x11909, 0x11909}, {0x1190C, 0x11913}, + {0x11915, 0x11916}, {0x11918, 0x11935}, {0x11937, 0x11938}, + {0x1193B, 0x11946}, {0x11950, 0x11959}, {0x119A0, 0x119A7}, + {0x119AA, 0x119D7}, {0x119DA, 0x119E4}, {0x11A00, 0x11A47}, + {0x11A50, 0x11AA2}, {0x11AB0, 0x11AF8}, {0x11B00, 0x11B09}, + {0x11C00, 0x11C08}, {0x11C0A, 0x11C36}, {0x11C38, 0x11C45}, + {0x11C50, 0x11C6C}, {0x11C70, 0x11C8F}, {0x11C92, 0x11CA7}, + {0x11CA9, 0x11CB6}, {0x11D00, 0x11D06}, {0x11D08, 0x11D09}, + {0x11D0B, 0x11D36}, {0x11D3A, 0x11D3A}, {0x11D3C, 0x11D3D}, + {0x11D3F, 0x11D47}, {0x11D50, 0x11D59}, {0x11D60, 0x11D65}, + {0x11D67, 0x11D68}, {0x11D6A, 0x11D8E}, {0x11D90, 0x11D91}, + {0x11D93, 0x11D98}, {0x11DA0, 0x11DA9}, {0x11EE0, 0x11EF8}, + {0x11F00, 0x11F10}, {0x11F12, 0x11F3A}, {0x11F3E, 0x11F59}, + {0x11FB0, 0x11FB0}, {0x11FC0, 0x11FF1}, {0x11FFF, 0x12399}, + {0x12400, 0x1246E}, {0x12470, 0x12474}, {0x12480, 0x12543}, + {0x12F90, 0x12FF2}, {0x13000, 0x1342F}, {0x13440, 0x13455}, + {0x14400, 0x14646}, {0x16800, 0x16A38}, {0x16A40, 0x16A5E}, + {0x16A60, 0x16A69}, {0x16A6E, 0x16ABE}, {0x16AC0, 0x16AC9}, + {0x16AD0, 0x16AED}, {0x16AF0, 0x16AF5}, {0x16B00, 0x16B45}, + {0x16B50, 0x16B59}, {0x16B5B, 0x16B61}, {0x16B63, 0x16B77}, + {0x16B7D, 0x16B8F}, {0x16E40, 0x16E9A}, {0x16F00, 0x16F4A}, + {0x16F4F, 0x16F87}, {0x16F8F, 0x16F9F}, {0x16FE0, 0x16FE4}, + {0x16FF0, 0x16FF1}, {0x17000, 0x187F7}, {0x18800, 0x18CD5}, + {0x18D00, 0x18D08}, {0x1AFF0, 0x1AFF3}, {0x1AFF5, 0x1AFFB}, + {0x1AFFD, 0x1AFFE}, {0x1B000, 0x1B122}, {0x1B132, 0x1B132}, + {0x1B150, 0x1B152}, {0x1B155, 0x1B155}, {0x1B164, 0x1B167}, + {0x1B170, 0x1B2FB}, {0x1BC00, 0x1BC6A}, {0x1BC70, 0x1BC7C}, + {0x1BC80, 0x1BC88}, {0x1BC90, 0x1BC99}, {0x1BC9C, 0x1BC9F}, + {0x1CF00, 0x1CF2D}, {0x1CF30, 0x1CF46}, {0x1CF50, 0x1CFC3}, + {0x1D000, 0x1D0F5}, {0x1D100, 0x1D126}, {0x1D129, 0x1D172}, + {0x1D17B, 0x1D1EA}, {0x1D200, 0x1D245}, {0x1D2C0, 0x1D2D3}, + {0x1D2E0, 0x1D2F3}, {0x1D300, 0x1D356}, {0x1D360, 0x1D378}, + {0x1D400, 0x1D454}, {0x1D456, 0x1D49C}, {0x1D49E, 0x1D49F}, + {0x1D4A2, 0x1D4A2}, {0x1D4A5, 0x1D4A6}, {0x1D4A9, 0x1D4AC}, + {0x1D4AE, 0x1D4B9}, {0x1D4BB, 0x1D4BB}, {0x1D4BD, 0x1D4C3}, + {0x1D4C5, 0x1D505}, {0x1D507, 0x1D50A}, {0x1D50D, 0x1D514}, + {0x1D516, 0x1D51C}, {0x1D51E, 0x1D539}, {0x1D53B, 0x1D53E}, + {0x1D540, 0x1D544}, {0x1D546, 0x1D546}, {0x1D54A, 0x1D550}, + {0x1D552, 0x1D6A5}, {0x1D6A8, 0x1D7CB}, {0x1D7CE, 0x1DA8B}, + {0x1DA9B, 0x1DA9F}, {0x1DAA1, 0x1DAAF}, {0x1DF00, 0x1DF1E}, + {0x1DF25, 0x1DF2A}, {0x1E000, 0x1E006}, {0x1E008, 0x1E018}, + {0x1E01B, 0x1E021}, {0x1E023, 0x1E024}, {0x1E026, 0x1E02A}, + {0x1E030, 0x1E06D}, {0x1E08F, 0x1E08F}, {0x1E100, 0x1E12C}, + {0x1E130, 0x1E13D}, {0x1E140, 0x1E149}, {0x1E14E, 0x1E14F}, + {0x1E290, 0x1E2AE}, {0x1E2C0, 0x1E2F9}, {0x1E2FF, 0x1E2FF}, + {0x1E4D0, 0x1E4F9}, {0x1E7E0, 0x1E7E6}, {0x1E7E8, 0x1E7EB}, + {0x1E7ED, 0x1E7EE}, {0x1E7F0, 0x1E7FE}, {0x1E800, 0x1E8C4}, + {0x1E8C7, 0x1E8D6}, {0x1E900, 0x1E94B}, {0x1E950, 0x1E959}, + {0x1E95E, 0x1E95F}, {0x1EC71, 0x1ECB4}, {0x1ED01, 0x1ED3D}, + {0x1EE00, 0x1EE03}, {0x1EE05, 0x1EE1F}, {0x1EE21, 0x1EE22}, + {0x1EE24, 0x1EE24}, {0x1EE27, 0x1EE27}, {0x1EE29, 0x1EE32}, + {0x1EE34, 0x1EE37}, {0x1EE39, 0x1EE39}, {0x1EE3B, 0x1EE3B}, + {0x1EE42, 0x1EE42}, {0x1EE47, 0x1EE47}, {0x1EE49, 0x1EE49}, + {0x1EE4B, 0x1EE4B}, {0x1EE4D, 0x1EE4F}, {0x1EE51, 0x1EE52}, + {0x1EE54, 0x1EE54}, {0x1EE57, 0x1EE57}, {0x1EE59, 0x1EE59}, + {0x1EE5B, 0x1EE5B}, {0x1EE5D, 0x1EE5D}, {0x1EE5F, 0x1EE5F}, + {0x1EE61, 0x1EE62}, {0x1EE64, 0x1EE64}, {0x1EE67, 0x1EE6A}, + {0x1EE6C, 0x1EE72}, {0x1EE74, 0x1EE77}, {0x1EE79, 0x1EE7C}, + {0x1EE7E, 0x1EE7E}, {0x1EE80, 0x1EE89}, {0x1EE8B, 0x1EE9B}, + {0x1EEA1, 0x1EEA3}, {0x1EEA5, 0x1EEA9}, {0x1EEAB, 0x1EEBB}, + {0x1EEF0, 0x1EEF1}, {0x1F000, 0x1F02B}, {0x1F030, 0x1F093}, + {0x1F0A0, 0x1F0AE}, {0x1F0B1, 0x1F0BF}, {0x1F0C1, 0x1F0CF}, + {0x1F0D1, 0x1F0F5}, {0x1F100, 0x1F1AD}, {0x1F1E6, 0x1F202}, + {0x1F210, 0x1F23B}, {0x1F240, 0x1F248}, {0x1F250, 0x1F251}, + {0x1F260, 0x1F265}, {0x1F300, 0x1F6D7}, {0x1F6DC, 0x1F6EC}, + {0x1F6F0, 0x1F6FC}, {0x1F700, 0x1F776}, {0x1F77B, 0x1F7D9}, + {0x1F7E0, 0x1F7EB}, {0x1F7F0, 0x1F7F0}, {0x1F800, 0x1F80B}, + {0x1F810, 0x1F847}, {0x1F850, 0x1F859}, {0x1F860, 0x1F887}, + {0x1F890, 0x1F8AD}, {0x1F8B0, 0x1F8B1}, {0x1F900, 0x1FA53}, + {0x1FA60, 0x1FA6D}, {0x1FA70, 0x1FA7C}, {0x1FA80, 0x1FA88}, + {0x1FA90, 0x1FABD}, {0x1FABF, 0x1FAC5}, {0x1FACE, 0x1FADB}, + {0x1FAE0, 0x1FAE8}, {0x1FAF0, 0x1FAF8}, {0x1FB00, 0x1FB92}, + {0x1FB94, 0x1FBCA}, {0x1FBF0, 0x1FBF9}, {0x20000, 0x2A6DF}, + {0x2A700, 0x2B739}, {0x2B740, 0x2B81D}, {0x2B820, 0x2CEA1}, + {0x2CEB0, 0x2EBE0}, {0x2EBF0, 0x2EE5D}, {0x2F800, 0x2FA1D}, + {0x30000, 0x3134A}, {0x31350, 0x323AF}, {0xE0100, 0xE01EF}, + }; static const UnicodeCharSet Printables(PrintableRanges); // Clang special cases 0x00AD (SOFT HYPHEN) which is rendered as an actual @@ -275,14 +276,14 @@ bool isPrintable(int UCS) { /// formatting characters. bool isFormatting(int UCS) { - // https://unicode.org/Public/15.0.0/ucdxml/ + // https://unicode.org/Public/15.1.0/ucdxml/ static const UnicodeCharRange Cf[] = { {0x00AD, 0x00AD}, {0x0600, 0x0605}, {0x061C, 0x061C}, {0x06DD, 0x06DD}, {0x070F, 0x070F}, {0x0890, 0x0891}, {0x08E2, 0x08E2}, {0x180E, 0x180E}, {0x200B, 0x200F}, {0x202A, 0x202E}, {0x2060, 0x2064}, {0x2066, 0x206F}, {0xFEFF, 0xFEFF}, {0xFFF9, 0xFFFB}, {0x110BD, 0x110BD}, - {0x110CD, 0x110CD}, {0x13430, 0x13438}, {0x1BCA0, 0x1BCA3}, + {0x110CD, 0x110CD}, {0x13430, 0x1343F}, {0x1BCA0, 0x1BCA3}, {0x1D173, 0x1D17A}, {0xE0001, 0xE0001}, {0xE0020, 0xE007F}}; static const UnicodeCharSet Format(Cf); @@ -446,29 +447,28 @@ static inline int charWidth(int UCS) { {0x2753, 0x2755}, {0x2757, 0x2757}, {0x2795, 0x2797}, {0x27B0, 0x27B0}, {0x27BF, 0x27BF}, {0x2B1B, 0x2B1C}, {0x2B50, 0x2B50}, {0x2B55, 0x2B55}, {0x2E80, 0x2E99}, - {0x2E9B, 0x2EF3}, {0x2F00, 0x2FD5}, {0x2FF0, 0x2FFB}, - {0x3000, 0x303E}, {0x3041, 0x3096}, {0x3099, 0x30FF}, - {0x3105, 0x312F}, {0x3131, 0x318E}, {0x3190, 0x31E3}, - {0x31F0, 0x321E}, {0x3220, 0x3247}, {0x3250, 0xA48C}, - {0xA490, 0xA4C6}, {0xA960, 0xA97C}, {0xAC00, 0xD7A3}, - {0xF900, 0xFAFF}, {0xFE10, 0xFE19}, {0xFE30, 0xFE52}, - {0xFE54, 0xFE66}, {0xFE68, 0xFE6B}, {0xFF01, 0xFF60}, - {0xFFE0, 0xFFE6}, {0x16FE0, 0x16FE4}, {0x16FF0, 0x16FF1}, - {0x17000, 0x187F7}, {0x18800, 0x18CD5}, {0x18D00, 0x18D08}, - {0x1AFF0, 0x1AFF3}, {0x1AFF5, 0x1AFFB}, {0x1AFFD, 0x1AFFE}, - {0x1B000, 0x1B122}, {0x1B132, 0x1B132}, {0x1B150, 0x1B152}, - {0x1B155, 0x1B155}, {0x1B164, 0x1B167}, {0x1B170, 0x1B2FB}, - {0x1F004, 0x1F004}, {0x1F0CF, 0x1F0CF}, {0x1F18E, 0x1F18E}, - {0x1F191, 0x1F19A}, {0x1F200, 0x1F202}, {0x1F210, 0x1F23B}, - {0x1F240, 0x1F248}, {0x1F250, 0x1F251}, {0x1F260, 0x1F265}, - {0x1F300, 0x1F64F}, {0x1F680, 0x1F6C5}, {0x1F6CC, 0x1F6CC}, - {0x1F6D0, 0x1F6D2}, {0x1F6D5, 0x1F6D7}, {0x1F6DC, 0x1F6DF}, - {0x1F6EB, 0x1F6EC}, {0x1F6F4, 0x1F6FC}, {0x1F7E0, 0x1F7EB}, - {0x1F7F0, 0x1F7F0}, {0x1F900, 0x1F9FF}, {0x1FA70, 0x1FA7C}, - {0x1FA80, 0x1FA88}, {0x1FA90, 0x1FABD}, {0x1FABF, 0x1FAC5}, - {0x1FACE, 0x1FADB}, {0x1FAE0, 0x1FAE8}, {0x1FAF0, 0x1FAF8}, - {0x20000, 0x2FFFD}, {0x30000, 0x3FFFD} - }; + {0x2E9B, 0x2EF3}, {0x2F00, 0x2FD5}, {0x2FF0, 0x303E}, + {0x3041, 0x3096}, {0x3099, 0x30FF}, {0x3105, 0x312F}, + {0x3131, 0x318E}, {0x3190, 0x31E3}, {0x31EF, 0x321E}, + {0x3220, 0x3247}, {0x3250, 0xA48C}, {0xA490, 0xA4C6}, + {0xA960, 0xA97C}, {0xAC00, 0xD7A3}, {0xF900, 0xFAFF}, + {0xFE10, 0xFE19}, {0xFE30, 0xFE52}, {0xFE54, 0xFE66}, + {0xFE68, 0xFE6B}, {0xFF01, 0xFF60}, {0xFFE0, 0xFFE6}, + {0x16FE0, 0x16FE4}, {0x16FF0, 0x16FF1}, {0x17000, 0x187F7}, + {0x18800, 0x18CD5}, {0x18D00, 0x18D08}, {0x1AFF0, 0x1AFF3}, + {0x1AFF5, 0x1AFFB}, {0x1AFFD, 0x1AFFE}, {0x1B000, 0x1B122}, + {0x1B132, 0x1B132}, {0x1B150, 0x1B152}, {0x1B155, 0x1B155}, + {0x1B164, 0x1B167}, {0x1B170, 0x1B2FB}, {0x1F004, 0x1F004}, + {0x1F0CF, 0x1F0CF}, {0x1F18E, 0x1F18E}, {0x1F191, 0x1F19A}, + {0x1F200, 0x1F202}, {0x1F210, 0x1F23B}, {0x1F240, 0x1F248}, + {0x1F250, 0x1F251}, {0x1F260, 0x1F265}, {0x1F300, 0x1F64F}, + {0x1F680, 0x1F6C5}, {0x1F6CC, 0x1F6CC}, {0x1F6D0, 0x1F6D2}, + {0x1F6D5, 0x1F6D7}, {0x1F6DC, 0x1F6DF}, {0x1F6EB, 0x1F6EC}, + {0x1F6F4, 0x1F6FC}, {0x1F7E0, 0x1F7EB}, {0x1F7F0, 0x1F7F0}, + {0x1F900, 0x1F9FF}, {0x1FA70, 0x1FA7C}, {0x1FA80, 0x1FA88}, + {0x1FA90, 0x1FABD}, {0x1FABF, 0x1FAC5}, {0x1FACE, 0x1FADB}, + {0x1FAE0, 0x1FAE8}, {0x1FAF0, 0x1FAF8}, {0x20000, 0x2FFFD}, + {0x30000, 0x3FFFD}}; static const UnicodeCharSet DoubleWidthCharacters(DoubleWidthCharacterRanges); if (DoubleWidthCharacters.contains(UCS)) diff --git a/llvm/lib/Support/UnicodeCaseFold.cpp b/llvm/lib/Support/UnicodeCaseFold.cpp index e8c24db3891..abf6df8d1e3 100644 --- a/llvm/lib/Support/UnicodeCaseFold.cpp +++ b/llvm/lib/Support/UnicodeCaseFold.cpp @@ -2,11 +2,11 @@ // // This file was generated by utils/unicode-case-fold.py from the Unicode // case folding database at -// http://www.unicode.org/Public/15.0.0/ucd/CaseFolding.txt +// http://www.unicode.org/Public/15.1.0/ucd/CaseFolding.txt // // To regenerate this file, run: // utils/unicode-case-fold.py \ -// "http://www.unicode.org/Public/15.0.0/ucd/CaseFolding.txt" \ +// "http://www.unicode.org/Public/15.1.0/ucd/CaseFolding.txt" \ // > lib/Support/UnicodeCaseFold.cpp // //===----------------------------------------------------------------------===// @@ -511,6 +511,9 @@ int llvm::sys::unicode::foldCharSimple(int C) { // GREEK CAPITAL LETTER ETA WITH PROSGEGRAMMENI if (C == 0x1fcc) return 0x1fc3; + // GREEK SMALL LETTER IOTA WITH DIALYTIKA AND OXIA + if (C == 0x1fd3) + return 0x0390; if (C < 0x1fd8) return C; // 2 characters @@ -521,6 +524,9 @@ int llvm::sys::unicode::foldCharSimple(int C) { // 2 characters if (C <= 0x1fdb) return C + -100; + // GREEK SMALL LETTER UPSILON WITH DIALYTIKA AND OXIA + if (C == 0x1fe3) + return 0x03b0; if (C < 0x1fe8) return C; // 2 characters @@ -741,6 +747,9 @@ int llvm::sys::unicode::foldCharSimple(int C) { // 80 characters if (C <= 0xabbf) return C + -38864; + // LATIN SMALL LIGATURE LONG S T + if (C == 0xfb05) + return 0xfb06; if (C < 0xff21) return C; // 26 characters diff --git a/llvm/lib/Support/UnicodeNameToCodepoint.cpp b/llvm/lib/Support/UnicodeNameToCodepoint.cpp index 40592660aca..8d66348cfab 100644 --- a/llvm/lib/Support/UnicodeNameToCodepoint.cpp +++ b/llvm/lib/Support/UnicodeNameToCodepoint.cpp @@ -320,7 +320,7 @@ struct GeneratedNamesData { uint32_t End; }; -// Unicode 15.0 Table 4-8. Name Derivation Rule Prefix Strings +// Unicode 15.1 Table 4-8. Name Derivation Rule Prefix Strings static const GeneratedNamesData GeneratedNamesDataTable[] = { {"CJK UNIFIED IDEOGRAPH-", 0x3400, 0x4DBF}, {"CJK UNIFIED IDEOGRAPH-", 0x4E00, 0x9FFF}, @@ -329,6 +329,7 @@ static const GeneratedNamesData GeneratedNamesDataTable[] = { {"CJK UNIFIED IDEOGRAPH-", 0x2B740, 0x2B81D}, {"CJK UNIFIED IDEOGRAPH-", 0x2B820, 0x2CEA1}, {"CJK UNIFIED IDEOGRAPH-", 0x2CEB0, 0x2EBE0}, + {"CJK UNIFIED IDEOGRAPH-", 0x2EBF0, 0x2EE5D}, {"CJK UNIFIED IDEOGRAPH-", 0x30000, 0x3134A}, {"CJK UNIFIED IDEOGRAPH-", 0x31350, 0x323AF}, {"TANGUT IDEOGRAPH-", 0x17000, 0x187F7}, diff --git a/llvm/lib/Support/UnicodeNameToCodepointGenerated.cpp b/llvm/lib/Support/UnicodeNameToCodepointGenerated.cpp index 33631870643..bfd51a5434c 100644 --- a/llvm/lib/Support/UnicodeNameToCodepointGenerated.cpp +++ b/llvm/lib/Support/UnicodeNameToCodepointGenerated.cpp @@ -73,913 +73,913 @@ extern const uint8_t *UnicodeNameToCodepointIndex; extern const std::size_t UnicodeNameToCodepointIndexSize; extern const std::size_t UnicodeNameToCodepointLargestNameSize; const char *UnicodeNameToCodepointDict = - " _-ABCDEFGHIJKLMNOPQRSTUVWXYZ0123456789S VERTICALLY BELOW AND SMALL " - "TAHRIGHTWARDS TRIANGLE-HEADED ARROW DOWNWARDS TRIANGLE-HEADED ARROW " - "DOWNWARDS EQUILATERAL ARROWHEADSEMICIRCULAR ANTICLOCKWISE ARROWLOWER LEFT " - "CURLY BRACKET SECTIONLE COMMA QUOTATION MARK ORNAMENTEDIUM SHADE AND " - "RIGHT HALF BLOCK SHADOWED WHITE RIGHTWARDS ARROWTHIRD WHITE RIGHT " - "POINTING INDEXEDIUM SHADE AND LOWER HALF BLOCKE TO MIDDLE LEFT TO LOWER " - "CENTREFACE WITH SYMBOLS COVERING MOUTH CONTAINING SMALL WHITE TRIANGLEE " - "SQUARED LATIN CAPITAL LETTER POWNWARDS HARPOON WITH BARB RIGHTAISING BOTH " - "HANDS IN CELEBRATIONTOP HALF DIVIDED BY VERTICAL BARED UPWARDS " - "EQUILATERAL ARROWHEADTICAL BAR DOUBLE RIGHT TURNSTILEER ARROWS CIRCLING " - "ANTICLOCKWISELAR SIGN WITH OVERLAID BACKSLASHHAND WITH MIDDLE FINGER " - "EXTENDEDPER BODY TILTING FROM HIP JOINTS BETWEEN MIDDLE AND RING " - "FINGERSESS-THAN ABOVE DOUBLE-LINE EQUAL BAR AT END OF HORIZONTAL " - "STROKEWNWARDS ARROW WITH TIP LEFTWARDSER IGI SHIR OVER SHIR UD OVER " - "UDINTING DOWNWARDS THEN NORTH EASTS AND UPWARDS OPEN CIRCLE ARROWS LOWER " - "HALF INVERSE MEDIUM SHADE LETTER BYELORUSSIAN-UKRAINIAN IROFLEX CLICK " - "WITH RETROFLEX HOOK LEFTWARDS TRIANGLE-HEADED ARROWE-POINTED BLACK " - "RIGHTWARDS ARROWM LEFT MEMBER OF DOUBLE VERTICALIGHTWARDS HARPOON WITH " - "BARB DOWNTRIANGLE-HEADED RIGHTWARDS ARROWUPPER AND LOWER ONE EIGHTH BLOCK " - "KORANIC STOP SIGN ISOLATED FORMDIFIER LETTER LABIALIZATION " - "MARKRIANGLE-HEADED OPEN CIRCLE ARROWD ARROW WITH TRIANGLE ARROWHEADSIDE " - "AND JOINED WITH INTERSECTIONRIGHT SEMICIRCLE WITH THREE DOTSFT-POINTING " - "ANGLE QUOTATION MARK HORIZONTAL STROKES TO THE RIGHTAND MIDDLE RIGHT TO " - "LOWER CENTRETER-THAN ABOVE DOUBLE-LINE EQUALHUR KAZAKH KIRGHIZ ALEF " - "MAKSURA ATHARVAVEDIC INDEPENDENT SVARITAOWER RIGHT CURLY BRACKET " - "SECTIONHT-POINTING ANGLE QUOTATION MARKLE-LINE EQUAL ABOVE " - "GREATER-THANAND LEFTWARDS OPEN CIRCLE ARROWSUG2 OVER TUG2 TUG2 OVER TUG2 " - "PAPNORMAL FACTOR SEMIDIRECT PRODUCTLAGAB TIMES U OVER LAGAB TIMES UTION " - "SIGN WITH CIRCUMFLEX ACCENTIRECT PRODUCT WITH BOTTOM CLOSEDER TAB NI OVER " - "NI DISH OVER DISHTIMES ASH2 KU OVER HI TIMES ASH2 TRIANGULAR THREE " - "QUARTERS BLOCKH SUPERSCRIPT ALEF ISOLATED FORMGREATER-THAN ABOVE SLANTED " - "EQUALH HORIZONTAL MIDDLE BLACK STRIPEH HAMZA ABOVE WITH ALEF MAKSURA DIC " - "KASHMIRI INDEPENDENT SVARITAED ARABIC-INDIC DIGIT FOUR ABOVEROXIMATELY " - "NOR ACTUALLY EQUAL TOED COMMA QUOTATION MARK ORNAMENTVED STEM PARAGRAPH " - "SIGN ORNAMENTARDS ARROW ABOVE LEFTWARDS ARROWSWIRL BIRGA WITH DOUBLE " - "ORNAMENTED ARABIC-INDIC DIGIT FOUR BELOWMARK WITH LEFT RIGHT ARROW " - "ABOVEOUBLE-LINE EQUAL ABOVE LESS-THANRONT-TILTED SHADOWED WHITE ARROWL " - "ARABIC LETTER TAH AND TWO DOTSEN ARM ENDING IN ARROW POINTING " - "ARDROP-SPOKED PROPELLER ASTERISKRONG CENTRALIZATION STROKE BELOWVE " - "LESS-THAN ABOVE SLANTED EQUALOF UPWARDS TRIANGLE-HEADED ARROWLEFTWARDS " - "HARPOON WITH BARB DOWN TORTOISE SHELL BRACKET ORNAMENTLL BUT UPPER LEFT " - "QUADRANT BLACKDED HIGH STOP WITH FILLED CENTREETALLED BLACK AND WHITE " - "FLORETTEWO DOTS ABOVE AND TWO DOTS BELOWE CONTAINING BLACK SMALL " - "LOZENGEARDS HARPOON WITH BARB DOWNWARDSTOM-LIGHTED RIGHTWARDS ARROWHEADWO " - "DOTS OVER ONE DOT PUNCTUATIONAISED HAND WITH FINGERS SPLAYEDA-HIRAGANA " - "PROLONGED SOUND MARKRING OVER TWO RINGS PUNCTUATIONRIGHTWARDS HARPOON " - "WITH BARB UPIN WHITE CIRCLE IN BLACK SQUARE CROSSING ASH OVER ASH OVER " - "ASHLEFTWARDS EQUILATERAL ARROWHEADAND MIDDLE LEFT TO LOWER CENTREUPWARDS " - "HARPOON WITH BARB RIGHTTNAMESE ALTERNATE READING MARK RINGS OVER ONE RING " - "PUNCTUATIONACK-TILTED SHADOWED WHITE ARROWONE HUNDRED THIRTY-FIVE " - "DEGREESETALLED OUTLINED BLACK FLORETTEAND JOINED BY DASH WITH SUBSETDOT " - "BELOW AND THREE DOTS ABOVEHT CENTRALIZATION STROKE BELOWQAF WITH LAM WITH " - "ALEF MAKSURAAGGRAVATED INDEPENDENT SVARITAON WITH RIGHTWARDS ARROW " - "ABOVEMINTON RACQUET AND SHUTTLECOCKOPEN CENTRE EIGHT POINTED " - "STARGREATER-THAN ABOVE EQUALS SIGNINDEX THUMB CURVE THUMB INSIDESAD WITH " - "LAM WITH ALEF MAKSURADIVIDED BY HORIZONTAL BAR AND DOWNWARDS AND " - "RIGHTWARDS ARROWGHT FOUR POINTED PINWHEEL STAREART EXCLAMATION MARK " - "ORNAMENTOINTING ANGLE BRACKET ORNAMENTMODIFIER LETTER LEFT HALF " - "RINGMAKSURA WITH SUPERSCRIPT ALEF HIGH-REVERSED-9 QUOTATION MARKEFT " - "SEMICIRCLE WITH THREE DOTSCKED FACE WITH EXPLODING HEADDOT OVER TWO DOTS " - "PUNCTUATIONLIGHT FOUR POINTED BLACK CUSPSUPERSCRIPT ALEF INITIAL " - "FORMEFTWARDS HARPOON WITH BARB UPOMBINING ANUSVARA ABOVE RIGHTDOWN MIDDLE " - "THUMB INDEX CROSSEXTENDED ARABIC-INDIC DIGIT T DOWN INDEX THUMB HOOK " - "MIDDLENS-SERIF INTERROBANG ORNAMENTPUNCTUATION CHINOOK FULL " - "STOPCONTAINING BLACK SMALL CIRCLET-HANDED INTERLACED PENTAGRAMUP HEAVY " - "AND RIGHT DOWN LIGHT WITH REVERSED NEGATION SLASHWITH RIGHTWARDS ARROW AT " - "LEFTONAL INDICATOR SYMBOL LETTER DOWN HEAVY AND RIGHT UP " - "LIGHTSEMICIRCULAR PATH AROUND POLE OVER RIGHTWARDS ARROW TO BAREVERSED " - "LUNATE EPSILON SYMBOLSALTIRE WITH ROUNDED CORNERSRECTANGULAR PATH AROUND " - "POLEASTERISKS ALIGNED VERTICALLYUPPER CENTRE TO MIDDLE RIGHTHREE HUNDRED " - "FIFTEEN DEGREESEFT ARC GREATER-THAN BRACKETMONOGRAMMOS TESSERA " - "DODEKATALEFTWARDS OF DOWNWARDS ARROWIBE SYLLABLE BOUNDARY " - "MARKEROUND-TIPPED RIGHTWARDS ARROWHADED WHITE RIGHTWARDS ARROWUP HEAVY " - "AND LEFT DOWN LIGHTEDGE-TAILED RIGHTWARDS ARROWDOUBLE ANUSVARA " - "ANTARGOMUKHAE-FEATHERED RIGHTWARDS ARROWBESIDE AND JOINED WITH UNIONACE " - "DIRECTION POSITION NOSE UPWARDS AND RIGHTWARDS ARROWT LITTER IN ITS PLACE " - "SYMBOLU ALAYHI WAAALIHEE WA-SALLAMDOWN HEAVY AND LEFT UP LIGHTMIDDLE RING " - "LITTLE CONJOINEDISMILLAH AR-RAHMAN AR-RAHEEMLIQUID MEASURE FIRST " - "SUBUNITFTING POINT RIGHTWARDS ARROWLARGE EQUILATERAL " - "ARROWHEADW-REVERSED-9 QUOTATION MARKRIANGULAR ONE QUARTER BLOCKPPY PERSON " - "RAISING ONE HANDTWO HUNDRED SEVENTY DEGREESTALIC LATIN CAPITAL LETTER " - "RIPLE VERTICAL BAR OPERATORFOUR FINGERS CONJOINED BENTPHARYNGEAL VOICED " - "FRICATIVEBETWEEN TWO HORIZONTAL BARSRIGHT ARC LESS-THAN BRACKETZERO FOR " - "ODD POWERS OF FOURIMPERFECTUM CUM PROLATIONE DOUBLE PRIME QUOTATION " - "MARKHEAD MARK WITH MOON AND SUNDOUBLE ANGLE QUOTATION MARK AND LEFT " - "SEMICIRCLE ARROWSLESS-THAN ABOVE EQUALS SIGNIDE ARC ANTICLOCKWISE " - "ARROWEMICIRCULAR CLOCKWISE ARROWLOWER TONAL RANGE INDICATORENTATION FORM " - "FOR VERTICAL UPPER MIDDLE LEFT TO UPPER DIVIDED BY HORIZONTAL " - "RULEKATHAKA INDEPENDENT SVARITALIGHT CENTRALIZATION STROKELOWER MIDDLE " - "LEFT TO LOWER WO DOTS BELOW AND DOT ABOVEOUR BALLOON-SPOKED ASTERISKONE " - "LARGE AND ONE SMALL EYE BARREE WITH TWO DOTS BELOWBRDA RNYING YIG MGO " - "MDUN MABRDA RNYING YIG MGO SGAB MAN-OUTLINED RIGHTWARDS ARROWCIRCLE WITH " - "NORTHWEST ARROWFINGER COVERING CLOSED LIPSCONTINUOUS UNDERLINE SYMBOLEAVY " - "WHITE RIGHTWARDS ARROWWALLPLANE SHOULDER HIP MOVEIDE-HEADED RIGHTWARDS " - "ARROWOTATED FLORAL HEART BULLETDOTTED LUNATE SIGMA SYMBOLUNEVEN EYES AND " - "WAVY MOUTHOCKED FEMALE AND MALE SIGN OR APPROXIMATELY EQUAL TOWITH " - "LEFTWARDS ARROW ABOVEONOMICAL SYMBOL FOR URANUSTHREE DOTS ABOVE " - "DOWNWARDSYAJURVEDIC MIDLINE SVARITACAT FACE WITH SMILING EYESMEEM WITH " - "HAH WITH TATWEELSSIAN ASTROLOGICAL SYMBOL MARRIED PARTNERSHIP " - "SYMBOLDOTTED SUBSTITUTION MARKERU REVERSED OVER U REVERSEDLANTED SOUTH " - "ARROW WITH HOCRIPT LIGATURE ET ORNAMENTAND MIDDLE FINGERS CROSSEDE " - "ONE-WAY LEFT WAY TRAFFIC LESS THAN THE DENOMINATORIDEOGRAPHIC ITERATION " - "MARKRIPLE DOT PUNCTUATION MARKLINE FEED SEPARATOR SYMBOLLEFTWARDS OF " - "UPWARDS ARROWDROP-SHADOWED WHITE SQUAREALEF MAKSURA ISOLATED FORMOORPLANE " - "SHOULDER HIP MOVE NEGATED WITH VERTICAL BARJECT REPLACEMENT CHARACTERBLE " - "TENNIS PADDLE AND BALLERSTRASS ELLIPTIC FUNCTIONCLOCKWISE ARROW WITH " - "MINUSINDUSTRIAL STANDARD SYMBOLORTHOGONAL CROSSHATCH FILLRIGHT " - "PARENTHESIS ORNAMENTAND RIGHT ONE EIGHTH BLOCKHTORA SKLIRON CHROMA VASIS " - "WITHIN TRIANGLE ARROWHEADLLALLAHOU ALAYHE WASSALLAM GAD OVER GAD GAR OVER " - "GARRIST CIRCLE HITTING WALL FFICULTY AT THE BEGINNINGMBINING " - "CRYPTOGRAMMIC DOTP-BARBED RIGHTWARDS ARROWRANCH BANK " - "IDENTIFICATIONINVERTED EXCLAMATION MARKLEFTWARDS ARROW WITH HOOKOUBLE " - "BIRGA WITH ORNAMENTREE-HUNDRED-AND-TWENTIETH WITH DOUBLE GRAVE ACCENTELD " - "HOCKEY STICK AND BALLDIAERESIS AND HOOK SYMBOLLOW QUILT SQUARE " - "ORNAMENTFECTIVENESS OR DISTORTION WITH DOUBLE VERTICAL BAR WITH DOUBLE " - "MIDDLE TILDETTED SUBSTITUTION BRACKETLEFT PARENTHESIS ORNAMENTDRY MEASURE " - "FIRST SUBUNITTAB OVER TAB GAR OVER GAR WITH CIRCLED ONE OVERLAYSTRUMENTAL " - "NOTATION SYMBOBREVE WITH INVERTED BREVEOLD ASSYRIAN WORD DIVIDERONE UNDER " - "EIGHTEEN SYMBOLBUT NOT ACTUALLY EQUAL TOTERNION INTEGRAL OPERATORSTROKE " - "AND TWO DOTS ABOVEMULTIPLICATION SIGN BELOWCAT FACE WITH CLOSED EYESRIGHT " - "DIAGONAL HALF BLACKCROSSING NORTH EAST ARROWING ON THE FLOOR " - "LAUGHINGRIPLE BIRGA WITH ORNAMENTMEDIUM TRIANGLE ARROWHEADNIVERSAL " - "RECYCLING SYMBOL OVER NUN LAGAR TIMES SALDOUBLE CANDRABINDU VIRAMASMALL " - "ARABIC LETTER TAH ISOSCELES RIGHT TRIANGLEE PLUS A PLUS SU PLUS " - "NALY-RECYCLED PAPER SYMBOLOTTOM-SHADED WHITE ARROWOTTOM SHADED WHITE " - "ARROWSTROKE THROUGH DESCENDERSYLLABLE REPETITION MARKARROW POINTING " - "DIRECTLY ARM CIRCLE HITTING WALL MALL CIRCLE TO THE " - "RIGHTONE-HUNDRED-AND-SIXTIETHRIGHTWARDS THEN CURVING LARGE TRIANGLE " - "ARROWHEADFINGER AND THUMB CROSSEDPOINTING DOWNWARDS ABOVEPERSCRIPT ALEF " - "MOKHASSASHEAVY BLACK HEART BULLETORIZONTAL BAR WITH NOTCHING FACE WITH " - "OPEN MOUTHDESCENDING MUSICAL NOTESSINGLE-LINE NOT EQUAL TOBLACK " - "LENTICULAR BRACKETDOWNSCALING FACTOR KIIZHMTAVRULI CAPITAL LETTER BLIC " - "ADDRESS LOUDSPEAKERLINE HORIZONTAL ELLIPSISEQUAL TO OR GREATER-THAN " - "POINTING BACKHAND INDEXAND MALE AND FEMALE SIGNCULINE ORDINAL " - "INDICATOREYES AND HAND OVER MOUTHREVERSED NINE-LIKE BHALELICATION PROGRAM " - "COMMANDIGATURE OPEN ET ORNAMENTDIAGONAL CROSSHATCH FILLWITH CANCELLATION " - "STROKETED INTERPOLATION MARKERLEFT DIAGONAL HALF BLACKMODIFIER " - "FITZPATRICK TYPTEARDROP-SPOKED ASTERISKBUSINESS SUIT LEVITATINGE HUNDRED " - "TWENTY-EIGHTH INTERSECTION WITH SERIFSWELVE POINTED BLACK " - "STARGREATER-THAN OR EQUAL TOALTERNATE SECTION MARKERCONSECUTIVE EQUALS " - "SIGNSWO DOTS VERTICALLY ABOVEUPWARD POINTING TRIANGLET BLACK RIGHTWARDS " - "ARROWVOICED LARYNGEAL SPIRANTGLOTTAL STOP WITH STROKE OVER TOP SQUARE " - "BRACKETDOUBLE HORIZONTAL STROKEWITH UPWARDS ARROW ABOVEUPRIGHT " - "RECTANGULAR ZEROBERKANAN BEORC BJARKAN BWO-WAY LEFT WAY TRAFFIC POINTING " - "AT THE VIEWERARTY HORN AND PARTY HATCURRENT SYMBOL FORM TWOARABIC LETTER " - "TAH ABOVEPUNCTUATION END OF TEXTALGAMATION OR COPRODUCTLEFT-SHADED WHITE " - "ARROWREE VARIATION SELECTOR GREEK SMALL LETTER IOTAHT TRIFOLIATE " - "SNOWFLAKECLUSTER-INITIAL LETTER ORAH WITH NINE BRANCHESUPWARDS THEN NORTH " - "WESTCIRCUMFLEX ACCENT ABOVEHREE POINTED BLACK STARRAISED OMISSION " - "BRACKETORIGINAL OF OR EQUAL TOHANKED RIGHTWARDS ARROW CAKE WITH SWIRL " - "DESIGNP WITH EXCLAMATION MARKSHAPE WITH A DOT INSIDEININE ORDINAL " - "INDICATORWHITE FOUR POINTED CUSPESS OUTLINED WHITE STARATTACHING VERTICAL " - "OMETSING DIAGONAL CROSSING RIGHT-POINTING TRIANGLE ROTATED NINETY " - "DEGREESAND WOMAN HOLDING HANDSRIGHT HORIZONTAL SECANTIVE FINGERS SPREAD " - "OPENZANTINE MUSICAL SYMBOL DOWNWARDS THEN CURVING UP SPREAD THUMB " - "FORWARDISTED RIGHTWARDS ARROWSAVOURING DELICIOUS FOODPA OVER PA GAR OVER " - "GAR WITH HALF-CIRCLE BELOWRTOISE SHELL BRACKETED LSCHREIBER PAUSE " - "SYMBOLSOLIDUS BINARY RELATIONASCENDING MUSICAL NOTESIDE ARC CLOCKWISE " - "ARROWVERTICAL BISECTING LINEALEF MAKSURA FINAL FORME-ROTATED DIVISION " - "SIGNANG DEPARTING TONE MARKOVER RIGHTWARDS HARPOONOVERLAPPING LOGICAL " - "ANDUBLE VERTICAL BAR BELOWIGHT-SHADED WHITE ARROWMITIAN CONJUGATE " - "MATRIXRIGHT DIAGONAL ELLIPSISDOT BELOW AND DOT ABOVE OVER STAMPED " - "ENVELOPELATIN CAPITAL LETTER S WITH THREE DOTS ABOVELE BESIDE VERTICAL " - "BAR WITH DECORATIVE COVER WITH CIRCUMFLEX ABOVELEFT TRIANGLE OPERATORLONG " - "HORIZONTAL STROKE WITH SINGLE ZAPYATAYAMNYAM YIG GI MGO RGYANNOT " - "INCLUDING THE POLEI YFESIS TETARTIMORIONWITH HORIZONTAL STROKEUPPER RIGHT " - "AND LOWER CURLY BRACKET ORNAMENTPUNCTUATION KUNDDALIYAE-ROUND NOTEHEAD " - "DOWN USTOMER ACCOUNT NUMBERUPPER ONE EIGHTH BLOCKPRECEDED BY " - "APOSTROPHEIGEL LONG-BRANCH-SOL SYIAKENG PUACHUE HMONG DOWN-POINTING " - "TRIANGLEIN DEPARTING TONE MARKINDIRECT QUESTION MARKDOMAIN " - "ANTIRESTRICTIONING HEAD IN SILHOUETTEPERSET OF NOR EQUAL TOS-SHAPED BAG " - "DELIMITERRECTILINEAR BLACK STARREASE FONT SIZE SYMBOLCONSONANT SIGN " - "MEDIAL DOUBLE SOLIDUS OVERLAYCONSONANT MODIFIER BARGREATER-THAN " - "DIAERESISCOMPATIBILITY IDEOGRAPND RECORDING COPYRIGHTREE-CIRCLE ALTERNATE " - "IDOUBLE VERTICAL STROKEPOINTING UPWARDS BELOWDOUBLE-LINED HEAD MARKUIGHUR " - "KIRGHIZ YEH WITEAST-POINTING AIRPLANEN-POTABLE WATER SYMBOLWITH VOICED " - "SOUND MARKHEXIFORM LONG ANUSVARASEMI-VOICED SOUND MARKQUESTION MARK " - "ORNAMENTHORT HORIZONTAL STROKEWITH JEEM INITIAL FORMSHORT RIGHTWARDS " - "ARROW RIGHT ARROWHEAD ABOVEACKSLANTED SOUTH ARROWRIGHT-POINTING " - "FLEURONDRESSED TO THE SUBJECTTRIPLE RIGHT TURNSTILETRIPLE VERTICAL " - "STROKEROUND A POINT OPERATOROVER SHIR BUR OVER BUROVER NU11 BUR OVER " - "BUROVER LEFTWARDS HARPOON SYMBOL FOR LIGHTHOUSESHORT VERTICAL " - "STROKESWASALLAM ISOLATED FORMKEEPING STILL MOUNTAINARMENIAN ETERNITY " - "SIGNLOW PARAPHRASE BRACKETRROW WITH ROUNDED HEADTWO HORIZONTAL STROKESBAR " - "ABOVE INTERSECTIONSYMPTOTICALLY EQUAL TOUBSCRIPT SMALL LETTER INVERTED " - "SMALL V ABOVEDOWNWARDS ZIGZAG ARROWINVERTED SMALL V BELOWLETTER SMALL " - "CAPITAL SH AMPERSAND ORNAMENTEQUAL TO OR LESS-THANLESS-THAN OR EQUAL " - "TOABOVE SHORT DOWN TACKMIDDLE RING LITTLE ONDIGRAMMOS EX DODEKATAOPPOSING " - "AN PLUS NAGAND TELEPHONE RECEIVERSIDE TO SIDE SCISSORSER RIGHT CORNER " - "ANGLEWESTERN PWO KAREN TONWO-CIRCLE ALTERNATE IWO-CIRCLE NUKTA " - "ABOVEO-FLOORPLANE TWISTINGXTRA SHORT VOWEL MARKOHAMMAD ISOLATED " - "FORMMORPHOLOGICAL DIVIDERYIG MGO TSHEG SHAD MAOP SHADED WHITE ARROWDOWN " - "HORIZONTAL LIGHTDOWN HORIZONTAL HEAVYMALE WITH STROKE SIGNDOWNWARDS ARROW " - "ABOVEWITH INVERTED V ABOVENTISTRY SYMBOL LIGHT ACUTE AND HOOK SYMBOLSHORT " - "LEFTWARDS ARROWALLING DIAGONAL SLASHAKIA TELOUS ICHIMATOSDOUBLE LEFT " - "TURNSTILEHALF TRIANGULAR COLONLATTENED OPEN A ABOVEINVERTED BRIDGE " - "BELOWTHICK LETTER SELECTOREFT HORIZONTAL SECANTINTERSECTION " - "OPERATORDELIMITER TSHEG BSTARGRUENT WITH DOT ABOVEEFT OPEN BOX " - "OPERATORINTERSECTING LOGICAL EIGHT SPOKED ASTERISKFINAL CONSONANT SIGN " - "HOCKEY STICK AND PUCK AND SLANTED PARALLELARD SHELL FLOPPY DISKBESIDE " - "RIGHT TRIANGLETILDE OPERATOR ABOVE ELATIONAL COMPOSITIONARKENING OF THE " - "LIGHTVERY HEAVY BARB ARROWRATING SYSTEM COMMANDEFT-POINTING TRIANGLEGHT " - "OPEN BOX OPERATORVERTICAL LINE OVERLAYARYSTIAN FIVE HUNDREDPAP PLUS PAP " - "PLUS LU3RELICT HOUSE BUILDING WITH VERTICAL STROKEHOUSAND MILLIONS " - "SIGNTEEN POINTED ASTERISKVOICED ITERATION MARKBUT NOT EQUIVALENT TOHAND " - "INTERIOR PRODUCTCRUCIFORM NUMBER FOURREVERSED FEATHER MARKINVERTED " - "GLOTTAL STOPCROSSE STICK AND BALLAND VOWEL LENGTH MARKHORIZONTAL " - "TABULATIONQUADRANT CIRCULAR ARCFLATTENED PARENTHESISBOTTOM U-SHAPED ARROW " - "WITH SHORT RIGHT LEGRISING DIAGONAL SLASHCTOR OR CROSS PRODUCTTRIANGULAR " - "HALF BLOCKTOUCHING INSIDE MOUTHGRAMMOS OKTO DODEKATAVAL WITH OVAL " - "INSIDEIRCLES HITTING WALL WET CULTIVATION SIGNINSIDE MOUTH RELAXEDFORMS " - "LIGHT VERTICALTHROUGH SMALL CIRCLECHEMICAL SYMBOL FOR UP-POINTING " - "TRIANGLECHARACTER INTRODUCERBETWEEN PALM FACINGSINVERSE WHITE " - "CIRCLEINVERTED CANDRABINDUDOTLESS HEAD OF KHAHHREE-DOT NUKTA " - "ABOVESEPARATOR MIDDLE DOTREVERSED ONE HUNDREDWITH FOUR DOTS " - "ABOVESEPARATOR KEY SYMBOLTRANSPOSITION MARKERCURRENCY SYMBOL RIELBSET OF " - "NOR EQUAL TOCURVED ANGLE BRACKETMULTIPLE PUNCTUATIONHORIZONTAL BAR WITH " - "PLUS GISH TIMES TAK4IMAGE OF OR EQUAL TODOUBLE ANGLE BRACKET79 OVER " - "LAK-079 GUNUCENTRE VERTICAL LINEWITH SOROCHYA NOZHKAINDEX RING LITTLE " - "ONRIGHT ANGLE WITH DOTRUMAI PALAUNG TONE-5A- SHOG GI MGO RGYANHIGH TONE " - "APOSTROPHEFOUR RAISED KNUCKLES OVER LAGAR GUNU SHEHIGH RATHA OR LOW " - "PADOWN ARROWHEAD BELOWINING OBLIQUE STROKE OVER TUR ZA OVER ZAUBHAANAHU " - "WA TAAALAAENARMONIOS ANTIFONIAGRA GCAN -CHAR RTAGSLEFT AND LOWER " - "RIGHTANGE ANTIRESTRICTIONLE WITH POPPING CORK AND DIAGONAL STROKESINGLE " - "DOT TONE MARKAND SOUTH WEST ARROW WITH HORIZONTAL BARLATALIZED HOOK " - "BELOWLASHING SWEAT SYMBOLRIGHT QUADRANT BLACKOTLESS J WITH STROKEONE MARK " - "SGAW KAREN FINAL CONSONANT MARKYIG MGO PHUR SHAD MAAND SOUTH EAST " - "ARROWAND NORTH WEST ARROWEMESTVENNY ZADERZHKAEVERSED ROTATED RANAAND " - "NORTH EAST ARROWWORD REPETITION MARKREAN STANDARD SYMBOLYRENAIC TWO " - "DRACHMASCONSONANT SIGN HAARUE CONSONANT MODIFIER ABOVE LEFT " - "TRIANGLELEFT-TO-RIGHT SECANTL FUNCTIONAL SYMBOL HAR2 TIMES GAL PLUS RIGHT " - "U-SHAPED ARROWRIGHT-POINTING ANGLENIS RACQUET AND BALL BEGIN LOGOGRAM " - "MARKSCRIPTION CHARACTER DOUBLE DOT TONE MARKOVER LEFTWARDS " - "ARROWJUDEO-SPANISH VARIKACRESCENT MOON SYMBOLHALF CIRCLE WITH DOTFIVE " - "SPOKED ASTERISKSIDEWAYS NOON GHUNNAARXIS KAI FTHORA VOUL-DOWN-OUTPUT " - "SYMBOLGHTWARDS ARROW BELOWE POINTED WHITE STARWARE-FUNCTION " - "SYMBOLONCAVE-SIDED DIAMONDCJK UNIFIED IDEOGRAPKHAMTI REDUPLICATIONSTAR " - "WITH MIDDLE DOTTIGHTLY-CLOSED EYESHORT STROKE OVERLAYURRENCY SYMBOL " - "BAHTMSHELL MOBILE PHONEHAND COVERING MOUTHNE HUNDRED TWENTY PHEAD-SHAPED " - "POINTERWITH YEH FINAL FORMGIBBOUS MOON SYMBOLTO LOWER RIGHT FILLCIRCLED " - "SANS-SERIF NDRED POINTS SYMBOLTHANG LONG ANUSVARANAXIAN FIVE " - "HUNDREDCIRCLED WHITE ARROWTWENTY-FIVE DEGREESAHU ALAYHI " - "WA-AALIHARENTHESIS NOTEHEADKULL AND CROSSBONESUP HORIZONTAL HEAVYUP " - "HORIZONTAL LIGHTARTIAL DIFFERENTIALVERTICAL TABULATIONFIVE FINGERS " - "SPREADEVEN POWERS OF FOURLUB-SPOKED ASTERISKSTRAIGHT THUMB BENTSTRATIAN " - "FIFTY MNASATED TELLER MACHINETURNED PADA PISELEHLEFT U-SHAPED " - "ARROWALTERNATE LAKH MARKLEFT TO LOWER RIGHTSLANTED NORTH ARROWTURNED " - "SECTION MARKLEFT POINTING INDEXLF MADDA OVER MADDAVERSE FINAL " - "BARLINELEADING MCHAN RTAGSANS-SERIF CAPITAL LANSPOSITION BRACKETLANTED " - "EQUAL ABOVE DENOMINATOR SIXTEENARABIC FORM SHAPINGIGATURE " - "AYIN-DALETHFT-POINTING FLEURONIN CHEN SPUNGS SHADA END LOGOGRAM " - "MARKIMIDIA SEXTULA SIGND CIRCUMFLEX ACCENTILDING CONSTRUCTIONSH PLUS HU " - "PLUS ASHSEVEN EIGHTHS BLOCKTART OF RUB EL HIZBTRANNO MALO POVYSHEGAPPED " - "CIRCLE ARROWC DIGRAPH WITH CURLMOVES AGAINST CHEEKSEQUENCE " - "INTRODUCERHURISAZ THURS THORNBETWEEN MIDDLE RINGING SHIRT WITH " - "SASHT-FACING BABY CHICKINSIDE CIRCLE BELOWET WITH WHITE CROSSVARIANT FORM " - "ILIMMUVARIANT WITH SQUAREVARIATION INDICATORVASTNESS OR WASTINGSYMBOL FOR " - "BEGINNERISPUTED END OF AYAHITED LIABILITY SIGNVERSAL INTERSECTIONRIGHT " - "MIDDLE STROKEOP SEMICIRCLE ARROW AND RETROFLEX HOOK WITH VERTICAL " - "TAILOCAL NOTATION SYMBO WITH STRIKETHROUGHRROW NO-BREAK SPACER-INITIAL " - "LETTER RAOTATED ARDHAVISARGADOWN AND HORIZONTAL AND " - "PROSGEGRAMMENIQUADRUPLE CRESCENTSUBLE DOT WITHIN DOTNOGRAPHIC FULL STOP " - "FLUTTERING IN WINDPARAGRAPH SEPARATORNORTH ARROW WITH HOOVER E NUN OVER " - "NUNRY CULTIVATION SIGNOW-9 QUOTATION MARKQUESTION MARK ABOVERIGHT TO " - "LOWER LEFTDOWN POINTING INDEXPREFIXED NASAL SIGN IN A RECTANGLE " - "BOXRAILING MCHAN RTAGSREE-QUARTER CIRCLE NETWORKED COMPUTERS LOVE YOU " - "HAND SIGNWOMEN HOLDING HANDS KASKAL U GUNU DISHENTY-TWO POINT TWOERTICAL " - "BAR VIRAMAKBAR ISOLATED FORMARROW SHAFT WIDTH THUMB INDEX THUMBNYET " - "THYOOM TA-ROLKANTAJA NAASIKYAYALOWER MIDDLE RIGHTEPIGRAPHIC LETTER " - "TILTING FROM WAISTNYOOGA NAAKSIKYAYAVERY SMALL DIAMONDKOREAN CHARACTER " - "OOUCHTONE TELEPHONEHILOSOPHERS SULFUR AND NO DOTS ABOVEHAIS LUS NTOG " - "NTOGJEEM ISOLATED FORMHORIZONTALLY BELOWUM WITH DRUMSTICKSATIN SMALL " - "LETTER IX SPOKED ASTERISKTROFLEX HOOK BELOW AND YPOGEGRAMMENIATERRESTRIAL " - "ALIENSET OVER BUILDINGSRYUKOVAYA SVETLAYAFIVE EIGHTHS BLOCKOW TONE " - "APOSTROPHE SPREAD THUMB SIDEASTROLOGICAL SIGN ASTED SWEET POTATORATUM " - "SUPER STRATUHOLDING BACK TEARSSOUL ISOLATED FORMENTERING TONE MARKSMALL " - "CIRCLE ABOVEWEST POINTING LEAFEAST POINTING LEAFU-GAAHLAA " - "TTUDDAAGABBREVIATION MARK EVERSED CHELYUSTKAAND LOW RIGHT RINGORK ON THE " - "DECAYEDLEFT MIDDLE STROKEGGLY VERTICAL LINERIST CIRCLE FRONT MATHEMATICAL " - "SPACER-STRING FRETBOARDLEFT-STEM TONE BARYPTIAN HIEROGLYPH AND SMASH " - "PRODUCTSINGLE PUNCTUATIONYLLABLE LENGTHENER WITH CROSSED-TAILOU ALAYHE " - "WASALLAMWHITE VERTICAL BARLOSED CIRCLE ARROWSHAN REDUPLICATIONL-UP-OUTPUT " - "SYMBOL WITH CIRCLE ABOVE WITH CIRCLE BELOWUP ARROWHEAD BELOWTYPE A " - "ELECTRONICSU-SHAPED ORNAMENTSOTLESS DALATH RISH WITH FLOWING SANDEVENTEEN " - "FULL STOPTOP U-SHAPED ARROW WITH KAVYKA ABOVESMALL RED TRIANGLEBOTTOM " - "RIGHT KASRAQUARTER NOTE STEM DOUBLE PUNCTUATIONTO LOWER LEFT FILLNINETEEN " - "FULL STOPFORKED PARAGRAPHOSNORMAL SUBGROUP OFCUP WITHOUT HANDLEWITH " - "JUSTIFICATIONBAARAKA WA-TAAALAAFORTY-FIVE DEGREESIGATURE ZAYIN-YODHIRROR " - "HORIZONTALLYCONTINUING OVERLAP NOT LITTER SYMBOLPERFIXED LETTER " - "RAD-HEIGHT LEFT HOOKHUNDREDS UNIT MARKS PRESSED TOGETHERGISH CROSSING " - "GISHVARIANT FORM LIMMU FOR SIMALUNGUN SAWITH STROKE SYMBOLBASELINE ROUND " - "DOTIGSAW PUZZLE PIECEIN POSSESSION SIGNUTLINED BLACK STARPUNCTUATION " - "BINDU COPPER ANTIMONIATENISH VERSE DIVIDERN-FLOORPLANE SPACEITAN SMALL " - "SCRIPT INDEPENDENT VOWEL X-STRING FRETBOARDPACING CANDRABINDUCANTILLATION " - "SIGN GATIVE ACKNOWLEDGENITE PART INTEGRALUPPER MIDDLE RIGHTSEPTUPLE " - "CRESCENTS OVER INVERTED SHUS INSIDE AND ABOVECTLY EQUIVALENT TOSYMMETRIC " - "SWAPPINGHOUSANDS SEPARATORTEN THOUSAND SIGN GRAVEYARD SYMBOLAMPHYLIAN " - "DIGAMMAHEART-SHAPED EYESLHOUETTE OF JAPAN WITH TILDE ABOVEEMICOLON " - "UNDERBARCROSS PUNCTUATIONPINWHEEL ASTERISKAND BLACK SQUARESVOCALIZATION " - "MARKSIGN O WITH CROSSPRESSIONLESS FACEIDEOGRAPHIC COMMAPRIZNAK MODIFIER " - "CIRCLES WITH DOTSHAH ISOLATED FORMBRACKET EXTENSIONBRIGHTNESS SYMBOL " - "LAGAR OVER LAGARYEH ISOLATED FORM LAGAB TIMES ASH2AEUM ONE " - "PLETHRONTARTING FROM SIGNPUNCTUATION SIGN IASTRE MARK ABOVE0 WHEELED " - "CHARIOTIGHTEEN FULL STOPAMBDA WITH STROKETIAL ARTS UNIFORMALTERNATE " - "NUMBER ULAR MEDIUM SHADEOPEN-HEADED ARROWBUT RELIEVED FACEVRE TOURNOIS " - "SIGNLAPPING LESS-THANBOTTOM HALF BLACKLIAN HIEROGLYPH APRECEDING " - "SOLIDUSTAN ISOLATED FORMGENERIC MATERIALSASTERN PWO KAREN CTION " - "APPLICATIONCANCELLATION MARKSTRAIGHT MOVEMENTK-LETTER CAPITAL VEE WITH " - "UNDERBAROURTEEN FULL STOPTHREE SOUND WAVES PLUS SHA3 PLUS ACAL SYMBOL " - "BOTTOMINVERTED MCHU CANKE BOTTLE AND CUPKHAH INITIAL FORMVERAGE WITH " - "SLASHAUKAZ LAGU LOGR LHORIZONTAL SINGLEURNED DAMMA BELOWFLICK " - "ALTERNATINGQUAT REVERSED ESHATHERING TOGETHEROWER NUMERAL SIGNURNED COMMA " - "ABOVEHORIZONTAL DOUBLEUP POINTING INDEXCANDRABINDU ABOVETRIPLE DASH " - "ARROWEAR SCREEN SYMBOLDELPHIC FIVE MNASLAGOLITIC LETTER LAH ISOLATED " - "FORMUP AND HORIZONTALAPLI DYO DODEKATABERBER ACADEMY YA OVER ZU PLUS " - "SARDENTAL PERCUSSIVEING POLE AND FISHINEAR ANNOTATION LD PERMIC LETTER " - "FRACTION ONE HALF WITH SOUND WAVESFROM SMALL CIRCLEBE WITH MERIDIANSRIGHT " - "HALF CIRCLE WITH BULLET NOSETERSYLLABIC TSHEGVARIANT FORM ASH9 TO BLACK " - "DIAMONDVARIANT FORM IMINSQUARED TIMES KURVARIANT FORM USSUFINGER-POST " - "ARROWHIRTEEN FULL STOPVERY SMALL SQUAREMANENT PAPER SIGN ALTERNATION " - "MARKCONSONANT SIGN PAABBREVIATION SIGNN-WALLPLANE SPACECLOSED LITTLE " - "YUSMEDIUM BARB ARROWMALL WHITE CIRCLENASALIZATION MARKREATIONAL " - "VEHICLENAUDIZ NYD NAUD NCONTINUATION SIGNCONTOURED OUTLINENG STROKE " - "OVERLAYNFORMATION SOURCEY ON BLACK SQUARESERVER EYE SYMBOLGREATER-THAN " - "NOR GREATER-THAN SIGNCOMBINING NUMBER WITH NOT EQUAL TORYBLION BASE " - "SIGNTONAL RANGE MARK S REVOLVING LIGHTMILITARY AIRPLANENEGATIVE CIRCLED A " - "PLUS HA PLUS DA AND PALATAL HOOKWHITE SHOGI PIECEWHITE PARENTHESISMEEM " - "INITIAL FORMN-BREAKING HYPHENN-CIRCUIT-OUTPUT WO VERTICAL DOTS NE EYEBROW " - "RAISEDK PERMITTED HERELOWER OVER UPPERRIGHT HALF BLACKDOUBLE HEAD " - "MARKUMBER SIGN ABOVEMIDDLE AND BELOWQ WITH HOOK TAILRIZONTAL " - "ELLIPSEHYPHENATION MARK AND LIGHT RIGHT WITH HEADSTROKEIMENSIONAL " - "ANGLEQUALS SIGN BELOWSTRAIGHT STRETCH PLUS KAK PLUS AEPSILON " - "UNDERBARK-NO-EVIL MONKEYNAL DIGIT SHAPESINES CONVERGING RIGHT DOWN BARB " - "WAVY HAMZA BELOWEVERSED VISARGA STUCK-OUT TONGUEE-NO-EVIL MONKEYCORNER " - "LEFTWARDSSLANTED EQUAL TO CAPPED MOUNTAINDVUMYA ZAPYATYMIEVERY OTHER TIME " - "WITH DOT INSIDEOLD TAMIL VIRAMAADIAN SYLLABICS EN MILLIONS SIGNRAYS AND " - "DOTTED UP MIDDLE HINGED OR THE IMAGE OFVOWEL LENGTHENERCREAMING IN " - "FEARPLACEHOLDER MARKINDEX THUMB SIDEVARIANT FORM ESHLD ASSYRIAN ONE SHU2 " - "PLUS KASKALHMATULLAH ALAYHEULDERED OPEN BOXLEFT ARROW ABOVESMALL CAPITAL " - "ELDEWAYS U BRACKETFALLING DIAGONALEFORE COMPLETIONPEN CENTRE CROSS TIMES " - "DISH TENUINDEPENDENT SHINECIMAL SEPARATORDOUBLE CRESCENTSVERY HEAVY " - "SHAFTDOUBLE DOT ABOVENION WITH SERIFSORIZONTAL JOINERCASIAN ALBANIAN " - "ANABAZAR SQUARE R-NO-EVIL MONKEYHOLDING TOGETHERSTICKING OUT FARRECORD " - "SEPARATORMIDDLE AND RIGHTPLE MEASURE RESTSMALL NOON ABOVE TIMES GAN2 " - "TENUDITORIAL CORONISRISING TONE MARKR PLUS GAN2 TENUSTERISK " - "OPERATORAFFRICATION MARKLEFT HALF CIRCLELLOW PAN OF FOODCOMPRESSED " - "ARROWB2 TENU PLUS TABDOUBLE ZAPYATAYASIGN RISING TONEISTOS DISC SIGN " - "PRECHGESANG STEMIRCLE X NOTEHEADE PLUS GAN2 TENURIGHT HALF BELOWPRECEDING " - "SUBSETIFTEEN FULL STOPTAKANA-HIRAGANA YATHOS BASE SIGNENTRE WHITE " - "STARUBJOINED LETTER UPERSCRIPT ALAPHRESH-AYIN-DALETHRAIDO RAD REID RYIR " - "MKPARAQ MEUNIPPER-MOUTH FACEWITH LEFT UPTURNMESTVENNY KLYUCHE-ENDED " - "MULTIMAPTRIPLE CRESCENTSIDED GREEK CROSSUPPER OVER LOWERENUMERATION " - "SIGNHIGH SPACING DOT WITH BUNNY EARSCORNER DOWNWARDSEND OF TEXT " - "MARKWALLED ENCLOSUREDOUBLE TURNSTILEVIEWING CEREMONYL-CARRIER " - "LETTERDOTTED CRESCENTS LIGHT MOON ARTAWITH HEARING AIDMAGNIFYING " - "GLASSWITH HAMZA ABOVEIGHTH NOTE STEM UDLY CRYING FACEPOSTPOSITION " - "MENSERIFS AT BOTTOMO-MINOAN SIGN CMARENTHESES ABOVEE-PIECE " - "SWIMSUITCONSONANT JOINERNTAIGANA LETTER LIGHT BARB ARROWOLD WHITE " - "CIRCLELIGHT AND RIGHT BOLD GREEK CROSSSITION INDICATOR INSERTION " - "POINTLTERNATE HASANTA AND HEAVY RIGHTFFERENCE BETWEENCH WITH UMBRELLAWITH " - "CENTRED DOTSANS-SERIF ARROW SMALL ROTATIONSDOWN RIGHT BARB BOTTOM HALF " - "RINGIVE POINTED STARDOING CARTWHEELST SYRIAC CROSSGROUP SEPARATORMIDDLE " - "DIAGONALST QUARTER MOONSSICAL BUILDING PARESTIGMENON OUBLE BACKSLASH " - "TIMES IGI GUNU DEYTEROU ICHOUR-FINAL LETTER FOUR DOTS WITH NJOINING " - "MACRONFOUR ENCLOSURESBELGTHOR SYMBOLKISIM5 TIMES BIPEN SQUARED DOTPENSION " - "RAILWAYKTOVIK NUMERAL QUADRUPLE ARROWERCURY SUBLIMAT TOUCHING " - "INDEXATINATE MYSLITEFORWARD TILTINGINVERTED STROKECAPITAL LETTERSXTEEN " - "FULL STOPUMAI PALAUNG FARIGHTWARDS AND NOON FINAL FORM AND BOTTOM " - "ENDRIGHTWARDS TICKHORIZONTAL FILLOWER HALF BLACKIZED WHEELCHAIROW-FALLING " - "TONEDOWN SEQUENTIALOLIDUS OPERATORS IN SILHOUETTERIGHT RERENGGANEH " - "INITIAL FORMIRCUMFLEX BELOWNOT APPROXIMATEHREE DOTS BELOWHOUSAND " - "STATERSATA LINK ESCAPEULTIPLICATION XS ELEVATUS MARKITH FINGERNAILSNOON " - "WITH KASRAWITH DOWN ARROWSTERESIS SYMBOLGEMINATION MARKVERTICAL SECANT " - "THROUGH CIRCLE2 CHARIOT FRAMETIP ON THE LEFTNVERTED UBADAMA AND LOWER " - "LEFTQUADRUPLE DASH THUMB STRAIGHTR WITH FISHHOOKRIGHT HALF RINGUBLE RING " - "BELOWUGMENTATION DOTINUS SIGN BELOWFIVE-LIKE BHALEHORIZONTAL DASHCORNER " - "WITH DOTWITH RAIN DROPSNO GOOD GESTURESTROKE NOT SIGNINVERTED LAZY " - "SSALTER PAHLAVI ZAIN FINAL FORMERICAN FOOTBALLMURDA MAHAPRANADAGESH OR " - "MAPIQBAR ABOVE UNION PLUS HI PLUS AHOOKED INDEX UPRMAN PENNY SIGNBLOCK " - "DIAGONAL ALTERNATE FORMTRIANGULAR MARKPLUS SIGN BELOWDI ALLAHOU " - "ANHUVOWEL SEPARATORVOWEL SHORTENERPUT SYMBOL FOR ALMOST EQUAL TOOGOGRAM " - "KHAMTI DOWNWARDS TRENDLEVEL TONE MARKLEVEN FULL STOPSIXTEENTH NOTESCKET " - "CALCULATORACHES THE LIMITALIF LENGTHENERON TOP OF MODEMIGN PALI " - "VIRAMAAMOUNT OF CHECKORIZONTAL COLONNA DOUBLE HELIXIMISEOS " - "CHRONOUMARRYING MAIDENODO SOFT HYPHENEXPONENT SYMBOLCLOSED BY CURVEBROWS " - "STRAIGHT BELOW LONG DASHTHROWING A KISS NEPOSTOYANNAYAAMARITAN SOURCEZERO " - "WITH SLASHIAMOND UNDERBARLONG HOOK BELOWRECEPTIVE EARTHIDING " - "ENCLOSURELONG VOWEL SIGNLOOK OF TRIUMPHHAKING PARALLELGHT REPEAT " - "SIGNPRISHTHAMATRA ELOSED INSULAR GDOUBLE TRIANGLEAI LAING DIGIT TVIMADUR " - "SYMBOLOND PLACE MEDALDIALYTIKA TONOSYNCHRONOUS IDLELIGHT AND LEFT " - "S-KAPYEOUNPIEUPONTOUR INTEGRALALAYHE ASSALLAMONJOINED HINGEDSHITA PLUS " - "GISHRECITATIVE MARKETIC VERSE SIGNUR POINTED STARMALAKON CHROMA LMOST " - "EQUAL TO HALF FILL SPACEND OF PARAGRAPHLD TAMIL SHORT TWO WITH " - "STROKEPERTHO PEORTH P WITH DIAERESISN-ARY SUMMATIONING SYMBOL FOR WHITE " - "DOT RIGHTESSARON CHRONONTILDE DIAERESISU PLUS U PLUS UBINDING " - "BRACKETREVERSE SOLIDUSUSTER NOTEHEAD WITH RIGHT LEGORT EQUALS SIGNEFT " - "REPEAT SIGN OPERATOR WITH HEH MEDIAL FORM CORNER BRACKETLATION " - "FUNCTIONFRACTION DIGIT REAMY EYEBROWS DESCENDING TONETOP RIGHT FATHATHREE " - "DISH TENUGGLY LINE BELOWMEEM FINAL FORMDIGA AELA-PILLAODIFIER DAMAGEDAND " - "PARALLEL TOO-CURRENCY SIGNESIDE LESS-THANFTER COMPLETIONREVERSED OPEN E " - "WITH DESCENDER OVER SIG4 SHU2E OVER INFINITYICTED LEFT ENTR CLOUD AND " - "RAINLEFT HAND INDEXIMPERFECTA RESTE MUSICAL NOTESBENT OVER INDEXO-HEADED " - "ARROW INGLE HEAD MARKE ISOLATED FORMLEFT DOWN BARB LEFT HALF BELOW OVER " - "MOUNTAINSLEFT HALF BLACKSHORT OVER LONGIRCULAR VIRAMAINVERTED " - "BIRGAUSPENSION MARKNORTH ARABIAN SECOND SUBUNITRIGHT CROSSBARWITH LEFT " - "HOOKD-UP NEWSPAPERINSERTION SIGNS-OR-PLUS SIGNPARATED SYMBOLDOUBLE-STRUCK " - "ING HANDS SIGNINOLOGICAL DOTPAO KAREN TONEERIAL ARAMAIC UPPED INDEX UP " - "HASER FOR VAVWORD SEPARATORPARTMENT STOREERIC INDICATORSEL " - "LOCOMOTIVEPLITTING APARTBLADE SCISSORSBLACK TRIANGLETELPIECE " - "CLOCKINVERTED DAMMAPLETE INFINITYPLE WITH HEARTREVERSED-SCHWATETARTOS " - "ICHOSREATIVE HEAVENINFINITY BELOWHREE-LEGGED TEPROTECTED AREABAG " - "MEMBERSHIPTRIANGLE WITH PPED MIDDLE UPBHATTIPROLU AAFORWARD INDEX " - "E-PER-EM SPACEIGHTWARDS VANEX-PER-EM SPACERD PLACE MEDALIKHAYA PUTNAYAPEN " - "MARK BELOWTRANSMIT STATEDEYTEROS ICHOSEXTENDED BHALEAND COLD SWEATORD " - "SEPARATOR SHESHIG TIMES ORANGE DIAMONDR-OFF CALENDARR-PER-EM " - "SPACEEMIVOWEL SIGN EXCLAMATION OHAMNUC PII KUUHVONIC ASTERISKLEFTWARDS " - "AND OPPOSING PIRIGLEFTWARDS TICKDI ALLAAHU ANHTIMES SHU TENUSEPARATOR " - "MARKOTHERS CIRCLEDTHOUSANDS MARKUBHAYATO MUKHATHOUSANDS SIGNSMALL " - "TRIANGLEUNDER RELATIONMEDIUM DIAMOND WITH LONG LEGOBLIQUE HYPHENFATHATAN " - "ABOVELESS-THAN NOR SMALL LETTER DGYPTOLOGICAL ATHREE POINTED OT TILDE " - "ABOVEANGLE OPENING OSITION SYMBOLTWO WHITE DOTSTURKIC LETTER REE-LINE " - "STAFFONE SOUND WAVE1 OVER LAK-081TWO ENCLOSURESUNIT SEPARATORENNA WITH " - "BARSAI LENGTH MARKREH FINAL FORMLOTUS POSITIONDIO MICROPHONELOWER " - "DIAGONALROSS ON SHIELDAFETY SCISSORSUNION OPERATOROLD RESOLUTIONSIDE-DOWN " - "FACETWO DOT LEADERGHT WITH STARSUAL WHEELCHAIRYOUTHFUL FOLLYLETTER " - "OVERLAPLEVEN TWELFTHSALLAJALALOUHOUTIMES OPERATORVRON SNOWFLAKEED SYMBOL " - "FOR TOP HALF BLACKALF TREE TRUNKOOTNOTE MARKERSMALL LETTER JLIGHTLY SMALL " - "DIRECTION FLIPLINE EXTENSIONDIAGONAL MOUTHCRIFICIAL WINEDIAGONAL PATH END " - "OF SECTIONLITTLE SECTIONDUN3 GUNU GUNUEPENTHETIC YUTVERTICAL HEAVYJOINED " - "SQUARESZAKAYA LANTERNCOLON OPERATORQUINARIUS SIGNOVER GUD LUGALVERTICAL " - "COLONTHAKA ANUDATTATHALAN ETHEL ODASIA PNEUMATAVERTICAL ABOVEHESIVE " - "BANDAGERING MEGAPHONEOUSING THUNDERNYI ZLA NAA DAERTICAL JOINEROUR OBOLS " - "SIGNTHER CHRISTMASAROUND-PROFILEO HEADED ARROWWITH DOT BELOWUP RIGHT BARB " - "MRACHNOTIKHAYAISED ROUND DOTVENIENCE STOREISSION TICKETSITA PLUS GISH " - "WITH FATHATAN XO EKFONITIKONVERTICAL LIGHTMOTHETIC ABOVEAU LENGTH MARK " - "AND DIAERESISIVE KEY SYMBOLIVE OBOLS SIGNIWAZ TIR TYR TSURROUND FROM " - "STRONG ISOLATEMENSION ORIGINA-ESASA DOTTEDZAH WITH MEEM CENTURIAL " - "SIGNCEPTER OF JOVESPEECH BUBBLES WITH BACK YERSHAN MEDIAL WACERTAINTY " - "SIGNFINAL ANUSVARALACE OF SAJDAHFFICE BUILDINGGUNU TIMES ASHSMOKING " - "SYMBOLFFED FLATBREADDOES NOT EXIST CROSSING ESH2HIRD-STAGE HLIMID-LEVEL " - "TONEUND MARK ABOVESQUIGGLE ARROWHERICAL ANGLEUE OF LIBERTYCROSSING " - "MUSHQUARTERS SIGNGYA GRAM SHADCROSSING GABACIRCLE INSIDE " - "DIMINUTION-1HAKASSIAN CHE B BAR SYMBOLED DOUBLE VERURNED W BELOWGAW KAREN " - "SHAUFFLE PRODUCTEELING PERSONGTER TSHEG MAUSICAL LEIMMATOP HALF " - "RINGUPWARDS TRENDCITATION MARKUDDISA SIRRAHEAVENLY EARTHTIRTA TUMETESHREE " - "TWELFTHSUSHING UPWARDC-SIMPLIFIED RANKS CASKET CROSSING GAN2GIFT " - "ENVELOPEWO-LINE STAFFCHECKER BOARDH-SPEED TRAINUPPER RIGHT-SI WITH STROKE " - "BZHI MIG CANH-HEELED SHOEUPSILON WITH CROSSING KA2CRIPTION TAKEGAR " - "FRACTION TED HAND SIGNRACKETS ABOVEEDIC ANUSVARA DIRECTIONAL THIRD " - "SUBUNITHIEROGLYPHIC HAM DIGIT ONECRIPTIONAL PAH-TYPE SYMBOLCULATED LORRY " - "BAT AND BALLED PAPERCLIPSHINESE TONE Y AND YEN SIGN AND SKI BOOTBY " - "DEFINITIONCHRYSANTHEMUMLATERAL CLICKOTEHEAD BLACK WITH INK PEN WITH " - "JEGOGANSMALL LETTERSANNED LEATHERTU WAS-SALAAM WITH OVERBARLEFT CROSSBAR " - "WITH TEE TOPRIPLE SVARITA WITHOUT SNOWAN RUPEE SIGNERTION SYMBOLAMUHU " - "ALAYNAAEMPHATIC TONERIZONTAL TAILOPPOSING NAGAMESSENIAN TENLEGETOS " - "ICHOSNTY FULL STOPMODIFIER MARKARLAUG SYMBOLMOBILE PHONES TIMES " - "KASKALSSAGE WAITINGARGOSYNTHETONVICE CONTROL VARIANT " - "FORMYUUKALEAPINTUFINAL SEMKATHARCHAIC KOPPADVOECHELNAYA L-FLOORPLANE " - "L-TYPE SYMBOLL-YEORINHIEUHAR WITH QUILLNUMERATOR ONEFICATION CARDMINUS " - "WHITE XAPPED PRESENTMINUS SIMILARNUMERIC SIGN MINDER RIBBONOGOTYPE SIGN " - "OBLIQUE LINE SHESH PLUS KIDIC MARK SIGNMASORA CIRCLEMARKS CHAPTERRRIAGE " - "RETURNONAL COMPUTERACCOMMODATIONRPENTRY PLANEMALO POVYSHE OMAN NUMERAL " - "EUROPE-AFRICAROTATED BIRGALOSING SPIRALOLVING HEARTSSIA-AUSTRALIALVE FULL " - "STOPLVEOLAR CLICKWAVY LOW LINEWAVY OVERLINEMALL LETTER " - "ZWAW-AYIN-RESHMAILBOX WITH U WITH STROKEONGRATULATIONDIAERESIZED UALL " - "LOST SIGNVOWEL SIGN PAYOD YOD PATAHMELODIC QITSARN PENTATHLONYMBOL TAU " - "RHORNAMENT STROKOON NOTEHEAD LISION SYMBOLW RING INSIDEEVERSED DAMMAWITH " - "ASTERISKONG-LEGGED DEONG RIGHT LEGSILI PNEUMATALOCATION SIGNLOCK WITH " - "KEYRTABLE STEREOMEDIUM SQUARESIGN PAMUDPODSIGN AVAGRAHAUPERIMPOSED " - "XFROWNING FACET-FLOORPLANE OPPOSING KURUPONDIUS SIGNE-GRAVE-ACUTEDOUBLE " - "MUCAADE-FLOORPLANE INTEREST SIGNFT ARROWHEAD BASAN LETTER RIGHT " - "HARPOONINVERTED FORKBALL AND HOOPDOUBLE HYPHENINVERTED TURNIOT SYLLABLE " - "BACKSLASH BARNASALIZED TONIRCLED INDEX E-ACUTE-GRAVEVE-LINE STAFFILABIAL " - "CLICKZHOU NUMERAL G-SSANGKIYEOKIDE LOST SIGNPREPONDERANCEIFI ROHINGYA " - "BOWING DEEPLYPPOSING LUGALBOTTOM CORNERIGHT TWELFTHSTAI LAING TONBOHAIRIC " - "KHEITE ORDER MARKE-MAIL SYMBOLSYNDESMOS NEOILE SEPARATORSAMYOK SANNYAPLUS " - "OPERATORFULL SURROUNDDOUBLE STROKESAL PLUS TUG2T-SHAPED SIGNIMAGE BRACKET " - "OF THE HORNSNG TERMINATORS KAI APOTHESS UP " - "TOGETHERFOREMENTIONEDJ-SIMPLIFIED TROFLEX CLICKDOTTED ZLAMA JES SU NGA " - "ROFIXED-FORM RAS KRYZHEM ON VERTICAL BARSMULTIOCULAR OWITH INTEGRALK WORK " - "SYMBOLSELECTED AREAVERTICAL FILLOUT MIDDLE UPOURTH SUBUNITSTERTIUS " - "SIGNARROW OVERLAYSTABLE SYMBOLARRED TRIDENTIVE SLOW SIGNNINE TWELFTHSVEN " - "POINT ONEISH LIRA SIGNNAP PIZZICATONING MOVEMENTAWELLEMET YAZPAIRED " - "ARROWSER BOARD FILLPA NJI PIPAEMDOUBLE CIRCLEVERGREEN TREEITING " - "THROUGHVERLAY MIDDLEIVE POINT ONEAUDATE CHRIVIEHU FEOH FE FDOUBLE ARCH UH " - "PLUS GISHDOT OPERATORDOWN NEUTRALDOUBLE ARROWERPENDICULARDOWN HARPOONE-2 " - "PLASTICSE-6 PLASTICSE-5 PLASTICSFOLDED HANDSTRIPLE FLAMEE-4 PLASTICSE-3 " - "PLASTICSFLAG ON POSTDASHED ARROWUGHT BALLOONEAGULL BELOWE-1 PLASTICSGEBA " - "KAREN IEIGHTH NOTESUPPER CORNERE-WALLPLANE EEPING SMALLTRAGRAM FOR FT " - "RERENGGANGAW KAREN EUULL NOTEHEADCROSSING NUNFOUNTAIN PENUBSCRIPT " - "TWOFORMING ARTSTRIPLE DANDAGBY FOOTBALLE-7 PLASTICSDICTION SIGNUME " - "INTEGRALENARIUS SIGNCRESCENT BAREVERING FACEDUG TIMES NIENOS " - "CHRONOUEMISOFT SIGNENT ARROW POUN WITH RAYSDIGRAPH KOTODIGRAPH " - "YORIFERENCE MARKCROSSING LU2CROSSING KALGERED TREMOLDE MARK SIGNCROSSING " - "GI4TOP-LIGHTED ETRETES SIGNFEMININE DOTDENTAL CLICKFALLING DOTSEMELY " - "HEAVY META STAVROUWITH SMALL VMUM TIMES PAMPTY CENTRE MPHASIS " - "MARKMONOGRAPH UKMING TO MEETSH ZIDA TENUMIDDLE PIECEWIGGLY FENCEAA " - "AS-SALAAMMEDIUM SHAFTMEDARY CAMELSHED BARLINEMBELLISHMENTMANNAZ MAN MACE " - "INTEGRALMALL SECTION6 LONG NGGOOS SUBPUNCTISNJALA GONDI X-LINE " - "STAFFS-MINUS SIGNNGLE BARLINENERSHIP SIGNNEPOSTOYANNYNDING PERSONNCK " - "CONSTANTNATURAL SIGNNARROW SHAFTSAZ IS ISS IN-OFF SYMBOLN-COPPER OREN " - "ELEMENT OFSECTION SIGNLEFT-LIGHTEDVOLTAGE SIGNLEFT HARPOONAND CRESCENTAND " - "OPERATORANG KHANG GYLEADING EYESSMALL DOUBLELAYING CARDSALTERNATING " - "LATALIZATIONSMALL TRIPLELARGE TRIPLELARGE DOUBLELAM WITH YEHSMILING " - "FACEAR DIAERESISACUTE ACCENTWDATA SQUAREMADDA ABOVE M NSHUT NYAMSHORT " - "RIKRIKLUS NOTEHEADLU PLUS ESH2LOWERED FLAGAFU LEERAEWALOWER CORNERLLE " - "PATTERN LINKING MARKLINGING FIRELIMBS DIGITSLICKING LIPSALLPOINT PENALT " - "PAN SIGNLER CONSTANT OVER MIDDLEPROTOS ICHOS LINE SYMBOLPOUTING FACEPORT " - "CONTROL OF ANTIMONY ON PEDESTALPHEME JOINERRIGHT DOUBLE OVER KISIM5 " - "KLYUCHEVAYA OVER TWO PIRIGHT SINGLEOWER RIGHT-S SKEWED LEFTR-LINE " + " _-ABCDEFGHIJKLMNOPQRSTUVWXYZ0123456789E SQUARED LATIN CAPITAL LETTER " + "PEDIUM SHADE AND LOWER HALF BLOCK KORANIC STOP SIGN ISOLATED " + "FORMATHARVAVEDIC INDEPENDENT SVARITA CONTAINING SMALL WHITE TRIANGLES " + "VERTICALLY BELOW AND SMALL TAHER IGI SHIR OVER SHIR UD OVER UDER ARROWS " + "CIRCLING ANTICLOCKWISEIDE AND JOINED WITH INTERSECTIONM LEFT MEMBER OF " + "DOUBLE VERTICALED UPWARDS EQUILATERAL ARROWHEADDIFIER LETTER " + "LABIALIZATION MARK LEFTWARDS TRIANGLE-HEADED ARROWNORMAL FACTOR " + "SEMIDIRECT PRODUCTE TO MIDDLE LEFT TO LOWER CENTREER TAB NI OVER NI DISH " + "OVER DISH LETTER BYELORUSSIAN-UKRAINIAN ILOWER LEFT CURLY BRACKET SECTION " + "BETWEEN MIDDLE AND RING FINGERSDIC KASHMIRI INDEPENDENT SVARITAHUR KAZAKH " + "KIRGHIZ ALEF MAKSURA S AND UPWARDS OPEN CIRCLE ARROWS BAR AT END OF " + "HORIZONTAL STROKE LOWER HALF INVERSE MEDIUM SHADE TORTOISE SHELL BRACKET " + "ORNAMENTHT-POINTING ANGLE QUOTATION MARK TRIANGULAR THREE QUARTERS " + "BLOCKOUBLE-LINE EQUAL ABOVE LESS-THANE-POINTED BLACK RIGHTWARDS " + "ARROWWNWARDS ARROW WITH TIP LEFTWARDSOWER RIGHT CURLY BRACKET " + "SECTIONINTING DOWNWARDS THEN NORTH EASTOWNWARDS HARPOON WITH BARB " + "RIGHTRIGHTWARDS TRIANGLE-HEADED ARROW SHADOWED WHITE RIGHTWARDS " + "ARROWSEMICIRCULAR ANTICLOCKWISE ARROW HORIZONTAL STROKES TO THE RIGHTVE " + "LESS-THAN ABOVE SLANTED EQUALFT-POINTING ANGLE QUOTATION MARKVED STEM " + "PARAGRAPH SIGN ORNAMENTIRECT PRODUCT WITH BOTTOM CLOSEDUG2 OVER TUG2 TUG2 " + "OVER TUG2 PAPD ARROW WITH TRIANGLE ARROWHEADSESS-THAN ABOVE DOUBLE-LINE " + "EQUALTER-THAN ABOVE DOUBLE-LINE EQUALUPPER AND LOWER ONE EIGHTH " + "BLOCKSWIRL BIRGA WITH DOUBLE ORNAMENT DOWNWARDS TRIANGLE-HEADED ARROW " + "DOWNWARDS EQUILATERAL ARROWHEADTRIANGLE-HEADED RIGHTWARDS ARROWWO DOTS " + "ABOVE AND TWO DOTS BELOWIGHTWARDS HARPOON WITH BARB DOWNMARK WITH LEFT " + "RIGHT ARROW ABOVEETALLED BLACK AND WHITE FLORETTERIGHT SEMICIRCLE WITH " + "THREE DOTSWO DOTS OVER ONE DOT PUNCTUATIONEDIUM SHADE AND RIGHT HALF " + "BLOCKRIANGLE-HEADED OPEN CIRCLE ARROWPER BODY TILTING FROM HIP JOINTSHAND " + "WITH MIDDLE FINGER EXTENDEDGREATER-THAN ABOVE SLANTED EQUALED COMMA " + "QUOTATION MARK ORNAMENTLL BUT UPPER LEFT QUADRANT BLACKRONT-TILTED " + "SHADOWED WHITE ARROWEN ARM ENDING IN ARROW POINTING AND LEFTWARDS OPEN " + "CIRCLE ARROWSLEFTWARDS HARPOON WITH BARB DOWNLAGAB TIMES U OVER LAGAB " + "TIMES ULAR SIGN WITH OVERLAID BACKSLASHLE-LINE EQUAL ABOVE GREATER-THANOF " + "UPWARDS TRIANGLE-HEADED ARROWRONG CENTRALIZATION STROKE BELOWTIMES ASH2 " + "KU OVER HI TIMES ASH2H SUPERSCRIPT ALEF ISOLATED FORMH HORIZONTAL MIDDLE " + "BLACK STRIPEED ARABIC-INDIC DIGIT FOUR BELOWH HAMZA ABOVE WITH ALEF " + "MAKSURA ED ARABIC-INDIC DIGIT FOUR ABOVETION SIGN WITH CIRCUMFLEX " + "ACCENTROFLEX CLICK WITH RETROFLEX HOOKFACE WITH SYMBOLS COVERING MOUTHLE " + "COMMA QUOTATION MARK ORNAMENTTOM-LIGHTED RIGHTWARDS ARROWHEADL ARABIC " + "LETTER TAH AND TWO DOTSARDROP-SPOKED PROPELLER ASTERISKARDS ARROW ABOVE " + "LEFTWARDS ARROWTOP HALF DIVIDED BY VERTICAL BARAISING BOTH HANDS IN " + "CELEBRATIONTHIRD WHITE RIGHT POINTING INDEXARDS HARPOON WITH BARB " + "DOWNWARDSTICAL BAR DOUBLE RIGHT TURNSTILEAND MIDDLE RIGHT TO LOWER " + "CENTREE CONTAINING BLACK SMALL LOZENGEDED HIGH STOP WITH FILLED " + "CENTREROXIMATELY NOR ACTUALLY EQUAL TOTNAMESE ALTERNATE READING MARK " + "LEFTWARDS EQUILATERAL ARROWHEADAND MIDDLE LEFT TO LOWER CENTREAISED HAND " + "WITH FINGERS SPLAYEDIN WHITE CIRCLE IN BLACK SQUAREUPWARDS HARPOON WITH " + "BARB RIGHTA-HIRAGANA PROLONGED SOUND MARKACK-TILTED SHADOWED WHITE " + "ARROWETALLED OUTLINED BLACK FLORETTEONE HUNDRED THIRTY-FIVE DEGREESRINGS " + "OVER ONE RING PUNCTUATIONRIGHTWARDS HARPOON WITH BARB UP CROSSING ASH " + "OVER ASH OVER ASHRING OVER TWO RINGS PUNCTUATIONINDEX THUMB CURVE THUMB " + "INSIDEDOT BELOW AND THREE DOTS ABOVEQAF WITH LAM WITH ALEF MAKSURAOPEN " + "CENTRE EIGHT POINTED STARGREATER-THAN ABOVE EQUALS SIGNMINTON RACQUET AND " + "SHUTTLECOCKDOWNWARDS AND RIGHTWARDS ARROWHT CENTRALIZATION STROKE " + "BELOWOINTING ANGLE BRACKET ORNAMENTHIGH-REVERSED-9 QUOTATION MARKAND " + "JOINED BY DASH WITH SUBSETMODIFIER LETTER LEFT HALF RINGAGGRAVATED " + "INDEPENDENT SVARITAON WITH RIGHTWARDS ARROW ABOVEGHT FOUR POINTED " + "PINWHEEL STAREART EXCLAMATION MARK ORNAMENTMAKSURA WITH SUPERSCRIPT ALEF " + "EFT SEMICIRCLE WITH THREE DOTSSAD WITH LAM WITH ALEF MAKSURADIVIDED BY " + "HORIZONTAL BAR AND EXTENDED ARABIC-INDIC DIGIT TDOT OVER TWO DOTS " + "PUNCTUATION OVER RIGHTWARDS ARROW TO BARPUNCTUATION CHINOOK FULL " + "STOPLIGHT FOUR POINTED BLACK CUSPEVERSED LUNATE EPSILON SYMBOLSUPERSCRIPT " + "ALEF INITIAL FORM WITH REVERSED NEGATION SLASHUP HEAVY AND RIGHT DOWN " + "LIGHTEFTWARDS HARPOON WITH BARB UPDOWN HEAVY AND RIGHT UP LIGHTNS-SERIF " + "INTERROBANG ORNAMENTDOWN MIDDLE THUMB INDEX CROSSCONTAINING BLACK SMALL " + "CIRCLE DOWN INDEX THUMB HOOK MIDDLEWITH RIGHTWARDS ARROW AT LEFTT-HANDED " + "INTERLACED PENTAGRAMOMBINING ANUSVARA ABOVE RIGHTONAL INDICATOR SYMBOL " + "LETTER CKED FACE WITH EXPLODING HEADSEMICIRCULAR PATH AROUND POLEACE " + "DIRECTION POSITION NOSE SALTIRE WITH ROUNDED CORNERSASTERISKS ALIGNED " + "VERTICALLYEFT ARC GREATER-THAN BRACKETUP HEAVY AND LEFT DOWN " + "LIGHTEDGE-TAILED RIGHTWARDS ARROWIBE SYLLABLE BOUNDARY MARKERDOWN HEAVY " + "AND LEFT UP LIGHTOUND-TIPPED RIGHTWARDS ARROWMONOGRAMMOS TESSERA " + "DODEKATAHREE HUNDRED FIFTEEN DEGREESLEFTWARDS OF DOWNWARDS " + "ARROWE-FEATHERED RIGHTWARDS ARROWLIQUID MEASURE FIRST SUBUNITHADED WHITE " + "RIGHTWARDS ARROWUPWARDS AND RIGHTWARDS ARROWFTING POINT RIGHTWARDS " + "ARROWDOUBLE ANUSVARA ANTARGOMUKHAU ALAYHI WAAALIHEE WA-SALLAMMIDDLE RING " + "LITTLE CONJOINEDT LITTER IN ITS PLACE SYMBOLUPPER CENTRE TO MIDDLE " + "RIGHTRECTANGULAR PATH AROUND POLEBESIDE AND JOINED WITH UNIONISMILLAH " + "AR-RAHMAN AR-RAHEEMRIPLE VERTICAL BAR OPERATORLESS-THAN ABOVE EQUALS " + "SIGNDOUBLE ANGLE QUOTATION MARKFINGER COVERING CLOSED LIPSPPY PERSON " + "RAISING ONE HANDBETWEEN TWO HORIZONTAL BARSENTATION FORM FOR VERTICAL " + "HEAD MARK WITH MOON AND SUN DIVIDED BY HORIZONTAL RULEW-REVERSED-9 " + "QUOTATION MARKCIRCLE WITH NORTHWEST ARROWONE LARGE AND ONE SMALL EYE AND " + "LEFT SEMICIRCLE ARROWSLARGE EQUILATERAL ARROWHEADEAVY WHITE RIGHTWARDS " + "ARROWZERO FOR ODD POWERS OF FOURFOUR FINGERS CONJOINED BENTLIGHT " + "CENTRALIZATION STROKEIMPERFECTUM CUM PROLATIONE WO DOTS BELOW AND DOT " + "ABOVEDOUBLE PRIME QUOTATION MARKUPPER MIDDLE LEFT TO UPPER TALIC LATIN " + "CAPITAL LETTER RIGHT ARC LESS-THAN BRACKETBRDA RNYING YIG MGO MDUN MABRDA " + "RNYING YIG MGO SGAB MAIDE-HEADED RIGHTWARDS ARROWTWO HUNDRED SEVENTY " + "DEGREESIDE ARC ANTICLOCKWISE ARROWCONTINUOUS UNDERLINE SYMBOLN-OUTLINED " + "RIGHTWARDS ARROWOUR BALLOON-SPOKED ASTERISKPHARYNGEAL VOICED " + "FRICATIVEEMICIRCULAR CLOCKWISE ARROWLOWER TONAL RANGE INDICATORKATHAKA " + "INDEPENDENT SVARITALOWER MIDDLE LEFT TO LOWER WALLPLANE SHOULDER HIP MOVE " + "BARREE WITH TWO DOTS BELOWRIANGULAR ONE QUARTER BLOCKOTATED FLORAL HEART " + "BULLETLEFTWARDS OF UPWARDS ARROW WITHIN TRIANGLE ARROWHEADOORPLANE " + "SHOULDER HIP MOVEORTHOGONAL CROSSHATCH FILLRIGHT PARENTHESIS " + "ORNAMENTERSTRASS ELLIPTIC FUNCTIONWITH LEFTWARDS ARROW ABOVEDOTTED LUNATE " + "SIGMA SYMBOLDOTTED SUBSTITUTION MARKERMEEM WITH HAH WITH TATWEELUNEVEN " + "EYES AND WAVY MOUTHMARRIED PARTNERSHIP SYMBOLU REVERSED OVER U " + "REVERSEDONOMICAL SYMBOL FOR URANUSOCKED FEMALE AND MALE SIGNYAJURVEDIC " + "MIDLINE SVARITADROP-SHADOWED WHITE SQUAREE ONE-WAY LEFT WAY TRAFFICRIPLE " + "DOT PUNCTUATION MARKLLALLAHOU ALAYHE WASSALLAMLINE FEED SEPARATOR " + "SYMBOLALEF MAKSURA ISOLATED FORM OR APPROXIMATELY EQUAL TOSSIAN " + "ASTROLOGICAL SYMBOL CLOCKWISE ARROW WITH MINUS LESS THAN THE " + "DENOMINATORCRIPT LIGATURE ET ORNAMENT NEGATED WITH VERTICAL BARLANTED " + "SOUTH ARROW WITH HOJECT REPLACEMENT CHARACTERTHREE DOTS ABOVE " + "DOWNWARDSCAT FACE WITH SMILING EYESHTORA SKLIRON CHROMA VASIS GAD OVER " + "GAD GAR OVER GARAND MIDDLE FINGERS CROSSEDIDEOGRAPHIC ITERATION MARKAND " + "RIGHT ONE EIGHTH BLOCKBLE TENNIS PADDLE AND BALLINDUSTRIAL STANDARD " + "SYMBOLONE UNDER EIGHTEEN SYMBOLRIPLE BIRGA WITH ORNAMENTBREVE WITH " + "INVERTED BREVESTRUMENTAL NOTATION SYMBOSTROKE AND TWO DOTS ABOVEDOUBLE " + "CANDRABINDU VIRAMAREE-HUNDRED-AND-TWENTIETHDRY MEASURE FIRST SUBUNIT WITH " + "DOUBLE GRAVE ACCENT WITH DOUBLE MIDDLE TILDE WITH DOUBLE VERTICAL BARLOW " + "QUILT SQUARE ORNAMENTTAB OVER TAB GAR OVER GARRANCH BANK " + "IDENTIFICATIONING ON THE FLOOR LAUGHINGMULTIPLICATION SIGN BELOWBUT NOT " + "ACTUALLY EQUAL TOINVERTED EXCLAMATION MARKTERNION INTEGRAL " + "OPERATORP-BARBED RIGHTWARDS ARROWELD HOCKEY STICK AND BALLOUBLE BIRGA " + "WITH ORNAMENT WITH CIRCLED ONE OVERLAYNIVERSAL RECYCLING SYMBOLCAT FACE " + "WITH CLOSED EYESMEDIUM TRIANGLE ARROWHEADOLD ASSYRIAN WORD " + "DIVIDERCROSSING NORTH EAST ARROWMBINING CRYPTOGRAMMIC DOTTTED " + "SUBSTITUTION BRACKETFFICULTY AT THE BEGINNINGDIAERESIS AND HOOK " + "SYMBOLRIGHT DIAGONAL HALF BLACKRIST CIRCLE HITTING WALL LEFT PARENTHESIS " + "ORNAMENTFECTIVENESS OR DISTORTION OVER NUN LAGAR TIMES SALLEFTWARDS ARROW " + "WITH HOOKLICATION PROGRAM COMMANDEYES AND HAND OVER MOUTHAND MALE AND " + "FEMALE SIGNORIZONTAL BAR WITH NOTCHISOSCELES RIGHT TRIANGLET BLACK " + "RIGHTWARDS ARROWING FACE WITH OPEN MOUTHARM CIRCLE HITTING WALL GLOTTAL " + "STOP WITH STROKEDOWNSCALING FACTOR KIIZHINTERSECTION WITH SERIFSE HUNDRED " + "TWENTY-EIGHTH LEFT DIAGONAL HALF BLACKSMALL ARABIC LETTER TAH BERKANAN " + "BEORC BJARKAN BMTAVRULI CAPITAL LETTER TEARDROP-SPOKED ASTERISKPERSCRIPT " + "ALEF MOKHASSASBUSINESS SUIT LEVITATINGEQUAL TO OR GREATER-THANMODIFIER " + "FITZPATRICK TYPTED INTERPOLATION MARKERALTERNATE SECTION MARKERWITH " + "CANCELLATION STROKEREVERSED NINE-LIKE BHALECULINE ORDINAL INDICATORUPWARD " + "POINTING TRIANGLERIGHTWARDS THEN CURVING E PLUS A PLUS SU PLUS NAFINGER " + "AND THUMB CROSSEDONE-HUNDRED-AND-SIXTIETHPOINTING DOWNWARDS ABOVEARROW " + "POINTING DIRECTLY DOUBLE HORIZONTAL STROKEBLIC ADDRESS " + "LOUDSPEAKERGREATER-THAN OR EQUAL TOVOICED LARYNGEAL SPIRANTLY-RECYCLED " + "PAPER SYMBOLWO DOTS VERTICALLY ABOVEUPRIGHT RECTANGULAR ZEROCONSECUTIVE " + "EQUALS SIGNSWITH UPWARDS ARROW ABOVEMALL CIRCLE TO THE RIGHTSTROKE " + "THROUGH DESCENDER POINTING BACKHAND INDEXDESCENDING MUSICAL " + "NOTESOTTOM-SHADED WHITE ARROWSYLLABLE REPETITION MARKOTTOM SHADED WHITE " + "ARROWDIAGONAL CROSSHATCH FILL OVER TOP SQUARE BRACKETIGATURE OPEN ET " + "ORNAMENTBLACK LENTICULAR BRACKETLARGE TRIANGLE ARROWHEADLINE HORIZONTAL " + "ELLIPSISWELVE POINTED BLACK STARSINGLE-LINE NOT EQUAL TOHEAVY BLACK HEART " + "BULLETIGHT-SHADED WHITE ARROWIDE ARC CLOCKWISE ARROWWO-WAY LEFT WAY " + "TRAFFICRIGHT DIAGONAL ELLIPSISREE VARIATION SELECTOR CLUSTER-INITIAL " + "LETTER GREEK SMALL LETTER IOTA WITH HALF-CIRCLE BELOWUPWARDS THEN NORTH " + "WESTCIRCUMFLEX ACCENT ABOVEHANKED RIGHTWARDS ARROWORAH WITH NINE " + "BRANCHESCURRENT SYMBOL FORM TWOORIGINAL OF OR EQUAL TODOWNWARDS THEN " + "CURVING HREE POINTED BLACK STARRAISED OMISSION BRACKETRTOISE SHELL " + "BRACKETED HT TRIFOLIATE SNOWFLAKE CAKE WITH SWIRL DESIGNSHAPE WITH A DOT " + "INSIDERIGHT HORIZONTAL SECANTMITIAN CONJUGATE MATRIXE-ROTATED DIVISION " + "SIGNUP SPREAD THUMB FORWARDARTY HORN AND PARTY HATDOT BELOW AND DOT " + "ABOVERIGHT-POINTING TRIANGLELSCHREIBER PAUSE SYMBOL ROTATED NINETY " + "DEGREESAVOURING DELICIOUS FOODP WITH EXCLAMATION MARKWHITE FOUR POINTED " + "CUSPASCENDING MUSICAL NOTESISTED RIGHTWARDS ARROWSZANTINE MUSICAL SYMBOL " + "ESS OUTLINED WHITE STARIVE FINGERS SPREAD OPENPA OVER PA GAR OVER " + "GARVERTICAL BISECTING LINE POINTING AT THE VIEWERPUNCTUATION END OF " + "TEXTATTACHING VERTICAL OMETOVERLAPPING LOGICAL ANDLEFT-SHADED WHITE " + "ARROWAND WOMAN HOLDING HANDSANG DEPARTING TONE MARKOVER RIGHTWARDS " + "HARPOONALGAMATION OR COPRODUCTALEF MAKSURA FINAL FORMUBLE VERTICAL BAR " + "BELOWSING DIAGONAL CROSSING ARABIC LETTER TAH ABOVEININE ORDINAL " + "INDICATORSOLIDUS BINARY RELATIONLONG HORIZONTAL STROKETRIPLE VERTICAL " + "STROKELEFT TRIANGLE OPERATOR WITH SINGLE ZAPYATAYAACKSLANTED SOUTH ARROW " + "WITH THREE DOTS ABOVELOW PARAPHRASE BRACKETARMENIAN ETERNITY SIGNSHORT " + "RIGHTWARDS ARROWCONSONANT SIGN MEDIAL RECTILINEAR BLACK STARCOMPATIBILITY " + "IDEOGRAPSHORT VERTICAL STROKESLE BESIDE VERTICAL BARCONSONANT MODIFIER " + "BARLATIN CAPITAL LETTER SYIAKENG PUACHUE HMONG KEEPING STILL " + "MOUNTAINWASALLAM ISOLATED FORMGREATER-THAN DIAERESISDOUBLE VERTICAL " + "STROKENOT INCLUDING THE POLEWITH HORIZONTAL STROKECURLY BRACKET " + "ORNAMENTWITH JEEM INITIAL FORMING HEAD IN SILHOUETTEUSTOMER ACCOUNT " + "NUMBERSEMI-VOICED SOUND MARKDOUBLE-LINED HEAD MARKUPPER RIGHT AND LOWER " + "S-SHAPED BAG DELIMITERDOUBLE SOLIDUS OVERLAYINDIRECT QUESTION MARKUPPER " + "ONE EIGHTH BLOCKIN DEPARTING TONE MARKWITH VOICED SOUND MARKIGEL " + "LONG-BRANCH-SOL SN-POTABLE WATER SYMBOLND RECORDING " + "COPYRIGHTSYMPTOTICALLY EQUAL TOHEXIFORM LONG ANUSVARATWO HORIZONTAL " + "STROKESROUND A POINT OPERATORDRESSED TO THE SUBJECTDOWNWARDS ZIGZAG " + "ARROWHORT HORIZONTAL STROKEDOMAIN ANTIRESTRICTIONTRIPLE RIGHT " + "TURNSTILERROW WITH ROUNDED HEADINVERTED SMALL V BELOWINVERTED SMALL V " + "ABOVEDOWN-POINTING TRIANGLEI YFESIS TETARTIMORIONMNYAM YIG GI MGO " + "RGYANBAR ABOVE INTERSECTIONOVER SHIR BUR OVER BURRIGHT-POINTING " + "FLEURONOVER LEFTWARDS HARPOONPRECEDED BY APOSTROPHE SYMBOL FOR LIGHTHOUSE " + "WITH CIRCUMFLEX ABOVEREASE FONT SIZE SYMBOLPOINTING UPWARDS BELOWOVER " + "NU11 BUR OVER BURREE-CIRCLE ALTERNATE IUIGHUR KIRGHIZ YEH WITQUESTION " + "MARK ORNAMENT WITH DECORATIVE COVER RIGHT ARROWHEAD ABOVEPERSET OF NOR " + "EQUAL TOE-ROUND NOTEHEAD DOWN UBSCRIPT SMALL LETTER EAST-POINTING " + "AIRPLANEPUNCTUATION KUNDDALIYA OVER STAMPED ENVELOPEDIGRAMMOS EX " + "DODEKATAINTERSECTION OPERATORVOICED ITERATION MARKINVERTED BRIDGE " + "BELOWSHORT LEFTWARDS ARROWINTERSECTING LOGICAL QUADRANT CIRCULAR ARCTILDE " + "OPERATOR ABOVE HORIZONTAL TABULATIONACUTE AND HOOK SYMBOLABOVE SHORT DOWN " + "TACKYIG MGO TSHEG SHAD MAVERTICAL LINE OVERLAYARYSTIAN FIVE " + "HUNDREDHOUSAND MILLIONS SIGNEFT OPEN BOX OPERATORMALE WITH STROKE SIGNPAP " + "PLUS PAP PLUS LU3AND VOWEL LENGTH MARKBESIDE RIGHT TRIANGLENTISTRY SYMBOL " + "LIGHT CROSSE STICK AND BALLDOWNWARDS ARROW ABOVEEFT-POINTING " + "TRIANGLEO-FLOORPLANE TWISTINGOHAMMAD ISOLATED FORMALLING DIAGONAL " + "SLASHAKIA TELOUS ICHIMATOSLETTER SMALL CAPITAL FLATTENED PARENTHESISTHICK " + "LETTER SELECTORLESS-THAN OR EQUAL TOHOCKEY STICK AND PUCKEQUAL TO OR " + "LESS-THANHORIZONTAL REFLECTION AND SLANTED PARALLELXTRA SHORT VOWEL " + "MARKHAND INTERIOR PRODUCTCRUCIFORM NUMBER FOURDOWN HORIZONTAL LIGHTDOWN " + "HORIZONTAL HEAVYRATING SYSTEM COMMANDELATIONAL COMPOSITIONHALF TRIANGULAR " + "COLONINVERTED GLOTTAL STOPREVERSED FEATHER MARKSIDE TO SIDE SCISSORSGHT " + "OPEN BOX OPERATORBUT NOT EQUIVALENT TO WITH SHORT RIGHT LEGFINAL " + "CONSONANT SIGN DELIMITER TSHEG BSTARDOUBLE LEFT TURNSTILETEEN POINTED " + "ASTERISKVERY HEAVY BARB ARROWRELICT HOUSE BUILDINGARKENING OF THE " + "LIGHTARD SHELL FLOPPY DISKOPPOSING AN PLUS NAGAGRAMMOS OKTO DODEKATAEIGHT " + "SPOKED ASTERISKRISING DIAGONAL SLASHLATTENED OPEN A ABOVESH AMPERSAND " + "ORNAMENTWITH INVERTED V ABOVETRIANGULAR HALF BLOCKER RIGHT CORNER ANGLEOP " + "SHADED WHITE ARROWCTOR OR CROSS PRODUCTMIDDLE RING LITTLE ONGRUENT WITH " + "DOT ABOVEBOTTOM U-SHAPED ARROWWO-CIRCLE NUKTA ABOVEWO-CIRCLE ALTERNATE " + "ITOUCHING INSIDE MOUTHND TELEPHONE RECEIVER WITH VERTICAL STROKEEFT " + "HORIZONTAL SECANTWESTERN PWO KAREN TONMORPHOLOGICAL DIVIDERCURVED ANGLE " + "BRACKET79 OVER LAK-079 GUNUWITH SOROCHYA NOZHKAFORMS LIGHT VERTICALE " + "POINTED WHITE STARIRCLES HITTING WALL RUMAI PALAUNG TONE-5DOTLESS HEAD OF " + "KHAHMULTIPLE PUNCTUATIONCENTRE VERTICAL LINESEPARATOR MIDDLE DOTHIGH TONE " + "APOSTROPHEHIGH RATHA OR LOW PASINGLE DOT TONE MARKCHARACTER INTRODUCER " + "OVER TUR ZA OVER ZASEPARATOR KEY SYMBOLWITH FOUR DOTS ABOVEHREE-DOT NUKTA " + "ABOVE BEGIN LOGOGRAM MARKDOUBLE DOT TONE MARKRIGHT U-SHAPED ARROWVAL WITH " + "OVAL INSIDEINDEX RING LITTLE ONWET CULTIVATION SIGNNIS RACQUET AND " + "BALLDOWN ARROWHEAD BELOWBETWEEN PALM FACINGSINSIDE MOUTH RELAXEDRIGHT " + "QUADRANT BLACKINING OBLIQUE STROKEFOUR RAISED KNUCKLESWORD REPETITION " + "MARKSIDEWAYS NOON GHUNNADOUBLE ANGLE BRACKETWARE-FUNCTION SYMBOLBSET OF " + "NOR EQUAL TORIGHT-POINTING ANGLEHORIZONTAL BAR WITH OVER LEFTWARDS " + "ARROWSCRIPTION CHARACTER REVERSED ONE HUNDREDCURRENCY SYMBOL RIELINVERTED " + "CANDRABINDUTRANSPOSITION MARKERA- SHOG GI MGO RGYANIMAGE OF OR EQUAL " + "TOUP-POINTING TRIANGLEINVERSE WHITE CIRCLEREAN STANDARD " + "SYMBOLLEFT-TO-RIGHT SECANTSTAR WITH MIDDLE DOTLE WITH POPPING CORKHALF " + "CIRCLE WITH DOTOTLESS J WITH STROKECRESCENT MOON SYMBOL WITH HORIZONTAL " + "BAR OVER LAGAR GUNU SHEKHAMTI REDUPLICATIONONCAVE-SIDED DIAMONDHAR2 TIMES " + "GAL PLUS E CONSONANT MODIFIERUBHAANAHU WA TAAALAAYRENAIC TWO " + "DRACHMASLATALIZED HOOK BELOWLASHING SWEAT SYMBOLGRA GCAN -CHAR " + "RTAGSGHTWARDS ARROW BELOWAND SOUTH EAST ARROW AND DIAGONAL STROKEAND " + "NORTH WEST ARROWAND NORTH EAST ARROWRIGHT ANGLE WITH DOTARXIS KAI FTHORA " + "VOUAND SOUTH WEST ARROWENARMONIOS ANTIFONIACJK UNIFIED IDEOGRAPFIVE " + "SPOKED ASTERISKYIG MGO PHUR SHAD MAONE MARK SGAW KAREN LEFT AND LOWER " + "RIGHTANGE ANTIRESTRICTIONJUDEO-SPANISH VARIKAL-DOWN-OUTPUT SYMBOLFINAL " + "CONSONANT MARKCHEMICAL SYMBOL FOR EMESTVENNY ZADERZHKATHROUGH SMALL " + "CIRCLEL FUNCTIONAL SYMBOL ABOVE LEFT TRIANGLECONSONANT SIGN HAARUEVERSED " + "ROTATED RANAPLUS GISH TIMES TAK4ET WITH WHITE CROSSWOMEN HOLDING " + "HANDSBETWEEN MIDDLE RING WITH STRIKETHROUGHOP SEMICIRCLE ARROWRAILING " + "MCHAN RTAGSUP HORIZONTAL LIGHTARABIC FORM SHAPINGNE HUNDRED TWENTY PNDRED " + "POINTS SYMBOL FLUTTERING IN WINDARTIAL DIFFERENTIALT-FACING BABY " + "CHICKIGATURE AYIN-DALETHING SHIRT WITH SASHURRENCY SYMBOL BAHTQUADRUPLE " + "CRESCENTSMOVES AGAINST CHEEKMSHELL MOBILE PHONEGIBBOUS MOON SYMBOLTO " + "LOWER RIGHT FILLOW-9 QUOTATION MARKTART OF RUB EL HIZBSEQUENCE " + "INTRODUCERNETWORKED COMPUTERSFIVE FINGERS SPREADIMIDIA SEXTULA SIGNKULL " + "AND CROSSBONESTRANNO MALO POVYSHEFT-POINTING FLEURONIN CHEN SPUNGS " + "SHADANS-SERIF CAPITAL LOVER E NUN OVER NUND CIRCUMFLEX ACCENTILDING " + "CONSTRUCTIONUP HORIZONTAL HEAVYANSPOSITION BRACKETWITH YEH FINAL FORMA " + "END LOGOGRAM MARKLANTED EQUAL ABOVE DENOMINATOR SIXTEENOTATED " + "ARDHAVISARGAQUESTION MARK ABOVE LOVE YOU HAND SIGNLEADING MCHAN " + "RTAGSHURISAZ THURS THORNSEVEN EIGHTHS BLOCKC DIGRAPH WITH CURLRIGHT TO " + "LOWER LEFTGAPPED CIRCLE ARROWSH PLUS HU PLUS ASH WITH VERTICAL " + "TAILPREFIXED NASAL SIGNR-INITIAL LETTER RANAXIAN FIVE HUNDREDARENTHESIS " + "NOTEHEADDOWN POINTING INDEXLUB-SPOKED ASTERISKTWENTY-FIVE DEGREESVARIANT " + "FORM ILIMMUITED LIABILITY SIGNRROW NO-BREAK SPACENORTH ARROW WITH HOEVEN " + "POWERS OF FOURAHU ALAYHI WA-AALIHISPUTED END OF AYAHVASTNESS OR " + "WASTINGRIGHT MIDDLE STROKE IN A RECTANGLE BOXVARIATION INDICATORVERSE " + "FINAL BARLINETIGHTLY-CLOSED EYESLF MADDA OVER MADDA AND " + "PROSGEGRAMMENIALTERNATE LAKH MARKSYMBOL FOR BEGINNERHAND COVERING " + "MOUTHREE-QUARTER CIRCLE HEAD-SHAPED POINTER AND RETROFLEX HOOKVARIANT " + "WITH SQUARETHANG LONG ANUSVARATURNED PADA PISELEHINSIDE CIRCLE " + "BELOWVERTICAL TABULATION KASKAL U GUNU DISHHORT STROKE OVERLAYPARAGRAPH " + "SEPARATORLEFT POINTING INDEXLEFT TO LOWER RIGHTRY CULTIVATION SIGNUBLE " + "DOT WITHIN DOTDOWN AND HORIZONTALSTRAIGHT THUMB BENTTURNED SECTION " + "MARKSLANTED NORTH ARROWLEFT U-SHAPED ARROWVERSAL INTERSECTIONNOGRAPHIC " + "FULL STOPATED TELLER MACHINEOCAL NOTATION SYMBOCIRCLED SANS-SERIF " + "STRATIAN FIFTY MNASCIRCLED WHITE ARROWKOREAN CHARACTER OIRROR " + "HORIZONTALLYERTICAL BAR VIRAMAPERFIXED LETTER RAFORKED " + "PARAGRAPHOSL-UP-OUTPUT SYMBOL NOT LITTER SYMBOLSINGLE PUNCTUATIONSEPTUPLE " + "CRESCENTSPUNCTUATION BINDU IGATURE ZAYIN-YODHBOTTOM RIGHT KASRAITAN SMALL " + "SCRIPT SYMMETRIC SWAPPINGSOUL ISOLATED FORMATIN SMALL LETTER SET OVER " + "BUILDINGSIX SPOKED ASTERISKUP ARROWHEAD BELOWIGSAW PUZZLE PIECEEVERSED " + "CHELYUSTKALEFT-STEM TONE BARVARIANT FORM LIMMUUTLINED BLACK STARASTED " + "SWEET POTATOKBAR ISOLATED FORMWEST POINTING LEAFSMALL CIRCLE " + "ABOVEABBREVIATION MARK ARROW SHAFT WIDTH OVER INVERTED SHUBASELINE ROUND " + "DOTFIVE EIGHTHS BLOCKPACING CANDRABINDU FOR SIMALUNGUN SAKANTAJA " + "NAASIKYAYAMATHEMATICAL SPACELEFT MIDDLE STROKEAND LOW RIGHT RINGD-HEIGHT " + "LEFT HOOKSHAN REDUPLICATIONLOSED CIRCLE ARROWBAARAKA " + "WA-TAAALAAATERRESTRIAL ALIENJEEM ISOLATED FORMFORTY-FIVE DEGREESSMALL RED " + "TRIANGLEUM WITH DRUMSTICKSTYPE A ELECTRONICSWHITE VERTICAL BAREVENTEEN " + "FULL STOPVERY SMALL DIAMONDIN POSSESSION SIGNQUARTER NOTE STEM LOWER " + "MIDDLE RIGHTINDEPENDENT VOWEL TROFLEX HOOK BELOWASTROLOGICAL SIGN CTLY " + "EQUIVALENT TO AND NO DOTS ABOVES PRESSED TOGETHERNITE PART " + "INTEGRALX-STRING FRETBOARDTILTING FROM WAISTNISH VERSE " + "DIVIDERHORIZONTALLY BELOWCANTILLATION SIGN NINETEEN FULL STOPHOUSANDS " + "SEPARATORYLLABLE LENGTHENER WITH FLOWING SANDNORMAL SUBGROUP OF THUMB " + "INDEX THUMBEAST POINTING LEAFHUNDREDS UNIT MARKDOUBLE PUNCTUATIONGATIVE " + "ACKNOWLEDGECUP WITHOUT HANDLEYPTIAN HIEROGLYPH N-FLOORPLANE SPACER-STRING " + "FRETBOARD WITH CIRCLE ABOVEGGLY VERTICAL LINEOU ALAYHE WASALLAMTOP " + "U-SHAPED ARROWU-GAAHLAA TTUDDAAG AND SMASH PRODUCTEPIGRAPHIC LETTER " + "U-SHAPED ORNAMENTSENTY-TWO POINT TWO AND YPOGEGRAMMENINYOOGA " + "NAAKSIKYAYACOPPER ANTIMONIATEHILOSOPHERS SULFUR WITH CIRCLE BELOWNYET " + "THYOOM TA-ROLENTERING TONE MARK WITH CROSSED-TAILRATUM SUPER " + "STRATUHOLDING BACK TEARSRYUKOVAYA SVETLAYAHAIS LUS NTOG NTOGOTLESS DALATH " + "RISHOUCHTONE TELEPHONES INSIDE AND ABOVEUPPER MIDDLE RIGHTORK ON THE " + "DECAYEDWITH STROKE SYMBOLOW TONE APOSTROPHERIST CIRCLE FRONT TO LOWER " + "LEFT FILLCONTINUING OVERLAPWITH JUSTIFICATIONGISH CROSSING GISH WITH " + "KAVYKA ABOVE SPREAD THUMB SIDESERVER EYE SYMBOLS REVOLVING LIGHT " + "GRAVEYARD SYMBOLRIGHT HALF CIRCLEBRACKET EXTENSIONHORIZONTAL SINGLEAND " + "BLACK SQUARESVARIANT FORM ASH9Y ON BLACK SQUAREVOCALIZATION MARKURNED " + "DAMMA BELOWIGHTEEN FULL STOPTIAL ARTS UNIFORMPRESSIONLESS FACEVERAGE WITH " + "SLASHCLOSED LITTLE YUS WITH SOUND WAVES WITH BULLET NOSEIDEOGRAPHIC " + "COMMACANDRABINDU ABOVEUP POINTING INDEXAPLI DYO DODEKATAUP AND " + "HORIZONTALEAR SCREEN SYMBOL LAGAR OVER LAGARLAH ISOLATED FORMWITH NOT " + "EQUAL TOBE WITH MERIDIANSVARIANT FORM IMINCONTINUATION SIGNAMBDA WITH " + "STROKEINVERTED MCHU CANDELPHIC FIVE MNAS AND PALATAL HOOKPRIZNAK MODIFIER " + "CONSONANT SIGN PARYBLION BASE SIGNASTERN PWO KAREN OWER NUMERAL " + "SIGNGENERIC MATERIALSALTERNATE NUMBER BOTTOM HALF BLACKSIGN O WITH CROSS " + "WITH TILDE ABOVEYEH ISOLATED FORMHIRTEEN FULL STOPVEE WITH UNDERBARURNED " + "COMMA ABOVE LAGAB TIMES ASH2LAGOLITIC LETTER AEUM ONE PLETHRON PLUS SHA3 " + "PLUS AHORIZONTAL DOUBLEVARIANT FORM USSUSTRAIGHT MOVEMENTK-LETTER CAPITAL " + "ULAR MEDIUM SHADECTION APPLICATIONHAH ISOLATED FORMAMPHYLIAN DIGAMMA TO " + "BLACK DIAMONDCIRCLES WITH DOTSMEEM INITIAL FORMBUT RELIEVED FACELD PERMIC " + "LETTER WHITE SHOGI PIECEWHITE PARENTHESISNASALIZATION MARKKHAH INITIAL " + "FORMLIAN HIEROGLYPH ANAUDIZ NYD NAUD NVRE TOURNOIS SIGNFLICK " + "ALTERNATINGGREATER-THAN SIGNCOMBINING NUMBER TEN THOUSAND SIGNKE BOTTLE " + "AND CUPFROM SMALL CIRCLEPINWHEEL ASTERISKSQUARED TIMES KURMEDIUM BARB " + "ARROWINEAR ANNOTATION PRECEDING SOLIDUSA PLUS HA PLUS DADENTAL " + "PERCUSSIVEEMICOLON UNDERBARTARTING FROM SIGNN-BREAKING HYPHENTONAL RANGE " + "MARK N-CIRCUIT-OUTPUT IASTRE MARK ABOVEFINGER-POST ARROWTHREE SOUND " + "WAVESLHOUETTE OF JAPAN ALTERNATION MARKCROSS PUNCTUATIONTRIPLE DASH " + "ARROWQUAT REVERSED ESHVERY SMALL SQUAREGREATER-THAN NOR N-WALLPLANE " + "SPACECAL SYMBOL BOTTOMHEART-SHAPED EYESPUNCTUATION SIGN 0 WHEELED " + "CHARIOTOPEN-HEADED ARROWMANENT PAPER SIGNBRIGHTNESS SYMBOLCONTOURED " + "OUTLINECANCELLATION MARKATHERING TOGETHERBERBER ACADEMY YANFORMATION " + "SOURCENG STROKE OVERLAYING POLE AND FISHLAPPING LESS-THAN OVER ZU PLUS " + "SARREATIONAL VEHICLEMILITARY AIRPLANEOURTEEN FULL STOPTAN ISOLATED " + "FORMABBREVIATION SIGNMALL WHITE CIRCLENE EYEBROW RAISEDWO VERTICAL DOTS " + "NEGATIVE CIRCLED TERSYLLABIC TSHEGAUKAZ LAGU LOGR LFRACTION ONE HALFE " + "PLUS GAN2 TENUYATHOS BASE SIGNENTRE WHITE STAROLD WHITE CIRCLESITION " + "INDICATORWITH HEARING AIDENUMERATION SIGNVIEWING CEREMONYEVERSED VISARGA " + "RECORD SEPARATORL-CARRIER LETTER WITH BUNNY EARSOLD TAMIL VIRAMAEVERY " + "OTHER TIMEE-NO-EVIL MONKEYSTUCK-OUT TONGUESLANTED EQUAL TODVUMYA " + "ZAPYATYMILEFT HALF CIRCLERISING TONE MARKDEWAYS U BRACKETLEFT ARROW " + "ABOVEULDERED OPEN BOXSMALL CAPITAL EL WITH HEADSTROKE LIGHT MOON " + "ARTACORNER LEFTWARDSORIZONTAL JOINERPLACEHOLDER MARKCONSONANT JOINEREN " + "MILLIONS SIGNCORNER DOWNWARDSPLE MEASURE RESTFALLING DIAGONALLD ASSYRIAN " + "ONE VERY HEAVY SHAFTPRECHGESANG STEMUMBER SIGN ABOVERIZONTAL ELLIPSESMALL " + "NOON ABOVEECIMAL SEPARATORPRECEDING SUBSETCOMPRESSED ARROWK-NO-EVIL " + "MONKEYVOWEL LENGTHENERUBJOINED LETTER UP MIDDLE HINGEDK PERMITTED " + "HERECREAMING IN FEAR WITH DOT INSIDESTRAIGHT STRETCHRIGHT DOWN BARB " + "E-PIECE SWIMSUIT OR THE IMAGE OFANABAZAR SQUARE STICKING OUT " + "FARPOSTPOSITION MENEND OF TEXT MARKYIR MKPARAQ MEUN AND LIGHT RIGHTRAYS " + "AND DOTTED ARENTHESES ABOVE AND HEAVY RIGHTFFERENCE BETWEENSTERISK " + "OPERATOR TIMES DISH TENUR-NO-EVIL MONKEYADIAN SYLLABICS WAVY HAMZA " + "BELOWVARIANT FORM ESH TIMES GAN2 TENUSHU2 PLUS KASKALMAGNIFYING GLASSIDED " + "GREEK CROSSLTERNATE HASANTAUPPER OVER LOWERCASIAN ALBANIAN LOWER OVER " + "UPPERNTAIGANA LETTER HOLDING TOGETHERDOUBLE TURNSTILEINDEPENDENT " + "SHINDOUBLE HEAD MARKNAL DIGIT SHAPESDOUBLE DOT ABOVESANS-SERIF ARROWINDEX " + "THUMB SIDEHYPHENATION MARKRAIDO RAD REID RINES CONVERGING DITORIAL " + "CORONISMESTVENNY KLYUCHQUALS SIGN BELOWDOUBLE CRESCENTSAFFRICATION " + "MARKMIDDLE AND BELOWUDLY CRYING FACEDOUBLE ZAPYATAYAMIDDLE AND RIGHT " + "CAPPED MOUNTAINIMENSIONAL ANGLENION WITH SERIFSUPERSCRIPT ALAPHIRCLE X " + "NOTEHEADDOTTED CRESCENTSRESH-AYIN-DALETHB2 TENU PLUS TABRIGHT HALF " + "BLACKEPSILON UNDERBAR SMALL ROTATIONSSIGN RISING TONESERIFS AT " + "BOTTOMTRIPLE CRESCENTSDOWN RIGHT BARB BOTTOM HALF RINGLLOW PAN OF " + "FOODHIGH SPACING DOTPEN CENTRE CROSSO-MINOAN SIGN CMCH WITH UMBRELLAEFORE " + "COMPLETIONISTOS DISC SIGN INSERTION POINTLIGHT AND RIGHT BOLD GREEK " + "CROSSR PLUS GAN2 TENUIGHTH NOTE STEM LIGHT BARB ARROWIFTEEN FULL STOPIVE " + "POINTED STARWITH HAMZA ABOVETAKANA-HIRAGANA WITH CENTRED DOTIPPER-MOUTH " + "FACEE-ENDED MULTIMAPQ WITH HOOK TAILRIGHT HALF BELOWWITH LEFT UPTURN PLUS " + "KAK PLUS AWALLED ENCLOSUREHMATULLAH ALAYHEIMISEOS CHRONOUIMPERFECTA " + "RESTREAMY EYEBROWS FTER COMPLETION DEYTEROU ICHOUR-FINAL LETTER ST " + "QUARTER MOONTRIANGULAR MARKRECEPTIVE EARTH CORNER BRACKETIGN PALI " + "VIRAMAHOUSAND STATERSR WITH FISHHOOKKTOVIK NUMERAL RECITATIVE MARKBLOCK " + "DIAGONAL IAMOND UNDERBARBROWS STRAIGHT CLOUD AND RAINIDING " + "ENCLOSUREUSTER NOTEHEAD ICTED LEFT ENTRKISIM5 TIMES BISSICAL BUILDING " + "ALTERNATE FORMUR POINTED STARHALF FILL SPACEHAKING PARALLELFORWARD " + "TILTINGINVERTED STROKEREVERSED OPEN ESTROKE NOT SIGNGHT REPEAT " + "SIGNPRISHTHAMATRA EGEMINATION MARKHOOKED INDEX UPHORIZONTAL DASHINVERTED " + "LAZY SFIVE-LIKE BHALEHORIZONTAL FILLITH FINGERNAILSTHREE DISH TENUATINATE " + "MYSLITEGGLY LINE BELOWTOP RIGHT FATHAHEH MEDIAL FORMREVERSE SOLIDUSIZED " + "WHEELCHAIRTHROWING A KISSDAGESH OR MAPIQPUT SYMBOL FOR IRCUMFLEX BELOWATA " + "LINK ESCAPEBENT OVER INDEXBELOW LONG DASH AND BOTTOM ENDHREE DOTS " + "BELOWQUADRUPLE ARROWINGLE HEAD MARKTIP ON THE LEFTSTERESIS SYMBOLGROUP " + "SEPARATORING SYMBOL FOR CORNER WITH DOTQUADRUPLE DASH FRACTION DIGIT " + "UGMENTATION DOTST SYRIAC CROSS AND LOWER LEFTBAR ABOVE UNIONTILDE " + "DIAERESISFOUR DOTS WITH CAPITAL LETTERSINUS SIGN BELOWVERTICAL " + "SECANTBINDING BRACKETFOUR ENCLOSURESCKET CALCULATORBELGTHOR SYMBOLCLOSED " + "BY CURVEON TOP OF MODEMRIGHTWARDS AND PERTHO PEORTH PRIGHT RERENGGANS IN " + "SILHOUETTEAMARITAN SOURCES ELEVATUS MARKUMAI PALAUNG FAEH INITIAL " + "FORMLMOST EQUAL TO SHITA PLUS GISHONTOUR INTEGRALMIDDLE DIAGONALVOWEL " + "SEPARATORDI ALLAHOU ANHUVOWEL SHORTENERXTEEN FULL STOP TIMES IGI GUNULEFT " + "HAND INDEXNJOINING MACRONU PLUS U PLUS UNO GOOD GESTURENOON FINAL FORMEFT " + "REPEAT SIGNNOON WITH KASRADOWN SEQUENTIALAMOUNT OF CHECKRIGHT HALF " + "RINGACHES THE LIMITEXPONENT SYMBOLLONG HOOK BELOWNOT APPROXIMATEPEN " + "SQUARED DOTOND PLACE MEDAL OVER SIG4 SHU2WHITE DOT RIGHTMEEM FINAL " + "FORMO-HEADED ARROW LIGHT AND LEFT ESSARON CHRONONDIALYTIKA TONOSPENSION " + "RAILWAYALAYHE ASSALLAMO-CURRENCY SIGN PARESTIGMENON TWO WITH STROKEDOING " + "CARTWHEELALMOST EQUAL TO WITH DESCENDERONJOINED HINGEDLEVEL TONE " + "MARKLEVEN FULL STOPMARRYING MAIDENRIGHTWARDS TICKSIXTEENTH NOTESALIF " + "LENGTHENER OVER MOUNTAINSESIDE LESS-THAN TOUCHING INDEX WITH " + "DIAERESISNVERTED UBADAMAAI LAING DIGIT SHORT OVER LONGOUBLE " + "BACKSLASHORIZONTAL COLON THUMB STRAIGHTN-ARY SUMMATIONZAIN FINAL " + "FORMERCURY SUBLIMATTVIMADUR SYMBOLODO SOFT HYPHENOLIDUS OPERATORLATION " + "FUNCTIONERICAN FOOTBALLODIFIER DAMAGEDS-KAPYEOUNPIEUPSALTER PAHLAVI PLUS " + "SIGN BELOW WITH RIGHT LEGORT EQUALS SIGNE MUSICAL NOTESND OF " + "PARAGRAPHDIGA AELA-PILLAE ISOLATED FORMOGOGRAM KHAMTI THROUGH CIRCLEZERO " + "WITH SLASH NEPOSTOYANNAYANA DOUBLE HELIXDOWNWARDS TRENDE OVER " + "INFINITYULTIPLICATION XDOUBLE TRIANGLEOW-FALLING TONEMURDA MAHAPRANAWITH " + "DOWN ARROWMALAKON CHROMA YNCHRONOUS IDLEDESCENDING TONELEFT HALF " + "BLACKUBLE RING BELOWRMAN PENNY SIGNLOOK OF TRIUMPHLONG VOWEL SIGN PLUS HI " + "PLUS A2 CHARIOT FRAMEAND PARALLEL TOLOSED INSULAR GLD TAMIL SHORT WITH " + "RAIN DROPSETIC VERSE SIGNLEFT DOWN BARB OWER HALF BLACKLEFT HALF " + "BELOWCERTAINTY SIGNDIRECTION FLIPINVERTED BIRGAINOLOGICAL DOTING HANDS " + "SIGNTWO DOT LEADERINSERTION SIGNTWO ENCLOSURESINFINITY BELOWOSITION " + "SYMBOLHESIVE BANDAGETHOUSANDS MARKPAO KAREN TONED-UP NEWSPAPERUNION " + "OPERATORTHREE POINTED THOUSANDS SIGNDIO MICROPHONESHESHIG TIMES ZAH WITH " + "MEEM OBLIQUE HYPHENPARATED SYMBOLMRACHNOTIKHAYAERIAL ARAMAIC SEL " + "LOCOMOTIVEOUR OBOLS SIGNERIC INDICATORS-OR-PLUS SIGNDOUBLE-STRUCK ZAKAYA " + "LANTERN CROSSING ESH2WITH LEFT HOOKSECOND SUBUNITSEPARATOR MARKWITH " + "FATHATAN WITH DOT BELOWMOTHETIC ABOVEX-PER-EM SPACETRIANGLE WITH OVER GUD " + "LUGALRING MEGAPHONETELPIECE CLOCKOUSING THUNDERED SYMBOL FOR TRANSMIT " + "STATETETARTOS ICHOSHREE-LEGGED TEWORD SEPARATORUSPENSION MARKREH FINAL " + "FORMR-PER-EM SPACER-OFF CALENDARNYI ZLA NAA DAUND MARK ABOVEMID-LEVEL " + "TONEA-ESASA DOTTEDTHER CHRISTMASHIRD-STAGE HLISHAN MEDIAL WAMENSION " + "ORIGINDOES NOT EXISTBLACK TRIANGLEO HEADED ARROWUNDER RELATIONMEDIUM " + "DIAMONDCENTURIAL SIGNCEPTER OF JOVEBHATTIPROLU AAQUINARIUS SIGNIGHTWARDS " + "VANENORTH ARABIAN IKHAYA PUTNAYATWO WHITE DOTSUPPED INDEX UPERTICAL " + "JOINERTHAKA ANUDATTATHALAN ETHEL OXO EKFONITIKONBLADE SCISSORSDUN3 GUNU " + "GUNUPLITTING APARTALF TREE TRUNK WITH LONG LEGGHT WITH STARSSQUIGGLE " + "ARROWVRON SNOWFLAKEIWAZ TIR TYR TSMALL TRIANGLEORD SEPARATOR VERTICAL " + "LIGHTALLAJALALOUHOULEVEN TWELFTHSLITTLE SECTIONOTHERS CIRCLED1 OVER " + "LAK-081ONE SOUND WAVEDIAGONAL PATH UBHAYATO MUKHADIAGONAL MOUTHLETTER " + "OVERLAPAU LENGTH MARKLINE EXTENSIONGYPTOLOGICAL AIVE KEY SYMBOLIVE OBOLS " + "SIGNREATIVE HEAVENLIGHTLY SMALL SMALL LETTER JEXCLAMATION OHLEFTWARDS AND " + "TIMES OPERATORVONIC ASTERISKEMIVOWEL SIGN TIMES SHU TENUJOINED " + "SQUARESAMNUC PII KUUHAROUND-PROFILEVERTICAL COLON AND DIAERESISFATHATAN " + "ABOVEUAL WHEELCHAIRSMALL LETTER DDI ALLAAHU ANHLESS-THAN NOR DASIA " + "PNEUMATAEND OF SECTIONRIGHT CROSSBARPROTECTED AREASTRONG ISOLATEVERTICAL " + "HEAVYPLETE INFINITYITA PLUS GISH VERTICAL ABOVEPLE WITH HEARTLEFTWARDS " + "TICKORANGE DIAMONDRD PLACE MEDALREE-LINE STAFFFORWARD INDEX FINAL " + "ANUSVARAUNIT SEPARATORTOP HALF BLACKREVERSED-SCHWAAI LENGTH MARKCRIFICIAL " + "WINEEPENTHETIC YUTOPPOSING PIRIGAFETY SCISSORSBAG MEMBERSHIPOLD " + "RESOLUTIONLOTUS POSITIONSPEECH BUBBLES HASER FOR VAVYOUTHFUL FOLLYLACE OF " + "SAJDAHLOWER DIAGONALPARTMENT STORETURKIC LETTER WITH BACK YERANGLE " + "OPENING COLON OPERATORENNA WITH BARSISSION TICKETSPEN MARK BELOWEXTENDED " + "BHALEAND COLD SWEATFFED FLATBREADOT TILDE ABOVEUP RIGHT BARB PPED MIDDLE " + "UPINVERTED DAMMAGUNU TIMES ASHVENIENCE STORESMOKING SYMBOLISED ROUND " + "DOTOOTNOTE MARKERSIDE-DOWN FACEROSS ON SHIELDFFICE BUILDINGE-PER-EM " + "SPACEDEYTEROS ICHOSIRCULAR VIRAMAOPPOSING NAGADVOECHELNAYA URNED W " + "BELOWEMPHATIC TONENINE TWELFTHSRIZONTAL TAILNG TERMINATORWO-LINE " + "STAFFOGOTYPE SIGN E-MAIL SYMBOL WITH TEE TOPGAW KAREN SHAC-SIMPLIFIED " + "UPPER RIGHT-SOURTH SUBUNIT WITH OVERBARSAMYOK SANNYA BAT AND BALL B BAR " + "SYMBOLSAL PLUS TUG2DOUBLE STROKEHREE TWELFTHS WITHOUT SNOWCULATED LORRY " + "WITH JEGOGAN WITH INK PENTIRTA TUMETESCROSSING GABAROTATED BIRGAOMAN " + "NUMERAL HAM DIGIT ONE AND YEN SIGNHAKASSIAN CHECIRCLE INSIDEHERICAL " + "ANGLECROSSING GAN2HIEROGLYPHIC RTABLE STEREOONAL COMPUTERCITATION " + "MARKCRIPTION TAKETOP HALF RINGU WITH STROKERPENTRY " + "PLANEYUUKALEAPINTURRIAGE RETURNCHECKER BOARDCRIPTIONAL PATHIRD SUBUNIT " + "VARIANT FORM AND SKI BOOTED DOUBLE VEROLVING HEARTSOBLIQUE LINE " + "CHRYSANTHEMUMUPSILON WITH OTEHEAD BLACK TIMES KASKALS KAI APOTHESOON " + "NOTEHEAD RNAMENT STROKYMBOL TAU RHOS KRYZHEM ON GYA GRAM SHADH-HEELED " + "SHOES UP TOGETHERER BOARD FILLEAVENLY EARTHGTER TSHEG MARN " + "PENTATHLONRANKS CASKET YOD YOD PATAHGIFT ENVELOPEONGRATULATIONRIPLE " + "SVARITAHINESE TONE YUPWARDS TRENDONG RIGHT LEGONG-LEGGED DECROSSING " + "MUSHNUMERIC SIGN NING MOVEMENTNUMERATOR ONENTY FULL STOPH-TYPE " + "SYMBOLH-SPEED TRAINIRCLED INDEX RIGHT HARPOONVE-LINE STAFFSIGN " + "PAMUDPODLOCK WITH KEYSYNDESMOS NEOFOREMENTIONEDLOCATION SIGNVEN POINT " + "ONEISH LIRA SIGNSILI PNEUMATAAWELLEMET YAZEVERSED DAMMAW RING " + "INSIDELISION SYMBOLVERGREEN TREEITING THROUGHVERLAY MIDDLEAUDATE " + "CHRIVIZHOU NUMERAL IVE POINT ONEIVE SLOW SIGNLVEOLAR CLICKMALL LETTER " + "ZMAILBOX WITH INTEREST SIGNE-ACUTE-GRAVEUPERIMPOSED XWAW-AYIN-RESHUDDISA " + "SIRRAHWAVY OVERLINEWAVY LOW LINEBASAN LETTER VOWEL SIGN PALVE FULL STOPI " + "WITH STROKEEUROPE-AFRICAINVERTED FORKBALL AND HOOPDIC MARK SIGNINVERTED " + "TURNIOT SYLLABLE BACKSLASH BARLOSING SPIRALSIGN AVAGRAHAPLUS OPERATORTU " + "WAS-SALAAMSTABLE SYMBOLARRED TRIDENTANNED LEATHERSMALL LETTERSARLAUG " + "SYMBOLLATERAL CLICKSSAGE WAITINGARGOSYNTHETONPPOSING LUGALVICE CONTROL " + "APPED PRESENTFINAL SEMKATHARCHAIC KOPPAFICATION CARDAR WITH " + "QUILLL-FLOORPLANE L-YEORINHIEUHL-TYPE SYMBOLAMUHU ALAYNAAALL LOST " + "SIGNJ-SIMPLIFIED DIAERESIZED UE-FLOORPLANE JES SU NGA ROLEGETOS " + "ICHOSE-GRAVE-ACUTEFIXED-FORM RAVERTICAL BARSK WORK SYMBOLSIA-AUSTRALIAAN " + "RUPEE SIGNVERTICAL FILL OPPOSING KURSTERTIUS SIGNLEFT CROSSBAR OF THE " + "HORNSPREPONDERANCEARROW OVERLAYTAI LAING TONWITH INTEGRALIFI ROHINGYA " + "BOWING DEEPLY DIMINUTION-1BOTTOM CORNERMODIFIER MARKMOBILE PHONESIGHT " + "TWELFTHS DIRECTIONAL WITH ASTERISKMULTIOCULAR OMINUS WHITE XMINUS " + "SIMILARBOHAIRIC KHEIMINDER RIBBONILABIAL CLICKILE SEPARATORT-SHAPED " + "SIGNIMAGE BRACKETFULL SURROUNDUSHING UPWARDED PAPERCLIPSGAR FRACTION " + "DOUBLE MUCAADBY DEFINITIONDOUBLE HYPHENOUT MIDDLE UPTED HAND " + "SIGNNASALIZED TONNAP PIZZICATO BZHI MIG CANDOUBLE CIRCLEMALO POVYSHE " + "USICAL LEIMMATE ORDER MARKRACKETS ABOVEIDE LOST SIGNEDIC " + "ANUSVARAG-SSANGKIYEOKSELECTED AREADOTTED ZLAMA CROSSING KA2PA NJI " + "PIPAEMQUARTERS SIGNSHESH PLUS KIPAIRED ARROWSUFFLE PRODUCTMELODIC " + "QITSAEHU FEOH FE FMESSENIAN TENFT ARROWHEAD FROWNING FACEMEDIUM " + "SQUARET-FLOORPLANE EELING PERSONUE OF LIBERTYACCOMMODATIONUPONDIUS " + "SIGNERTION SYMBOLMASORA CIRCLEMARKS CHAPTERTRAGRAM FOR UME " + "INTEGRALCROSSING GI4DOUBLE ARCH E-2 PLASTICSGAW KAREN EUGBY " + "FOOTBALLENARIUS SIGNUH PLUS GISHTOP-LIGHTED EIGHTH NOTESETRETES " + "SIGNDIGRAPH YORIFERENCE MARKFEMININE DOTDENTAL CLICKE-1 PLASTICSE-7 " + "PLASTICSEMISOFT SIGNEMELY HEAVY DIGRAPH KOTODOUBLE ARROWFALLING DOTSDE " + "MARK SIGNEVERING FACEFOLDED HANDSEAGULL BELOWUPPER CORNERUGHT " + "BALLOONFORMING ARTSCROSSING LU2DOT OPERATORGEBA KAREN IDUG TIMES NITRIPLE " + "FLAMEENOS CHRONOUTRIPLE DANDADOWN NEUTRALCRESCENT BARCROSSING NUNE-5 " + "PLASTICSENT ARROW POFOUNTAIN PENUN WITH RAYSUBSCRIPT " + "TWOERPENDICULARDICTION SIGNDASHED ARROWE-3 PLASTICSULL NOTEHEADFLAG ON " + "POSTFT RERENGGANE-4 PLASTICSGERED TREMOLE-6 PLASTICSEEPING SMALLCROSSING " + "KALE-WALLPLANE DOWN HARPOONWITH SMALL VMUM TIMES PAMPTY CENTRE MPHASIS " + "MARKMONOGRAPH UKMING TO MEETSH ZIDA TENUMIDDLE PIECEWIGGLY FENCESECTION " + "SIGNMETA STAVROUAA AS-SALAAMMEDIUM SHAFTMEDARY CAMELSHED " + "BARLINEMBELLISHMENTMANNAZ MAN MACE INTEGRALNDING PERSONS SUBPUNCTISNJALA " + "GONDI X-LINE STAFFS-MINUS SIGNNGLE BARLINENERSHIP SIGNNEPOSTOYANNYMALL " + "SECTION6 LONG NGGOONCK CONSTANTNATURAL SIGNNARROW SHAFTSAZ IS ISS IN-OFF " + "SYMBOLN-COPPER OREN ELEMENT OFALTERNATING LEFT-LIGHTEDVOLTAGE SIGNLEFT " + "HARPOONAND CRESCENTAND OPERATORANG KHANG GYLEADING EYESSMALL DOUBLELAYING " + "CARDSLER CONSTANTLATALIZATIONSMALL TRIPLELARGE TRIPLELARGE DOUBLELAM WITH " + "YEHSMILING FACEACUTE ACCENTWDATA SQUAREMADDA ABOVE M NSHUT NYAMSHORT " + "RIKRIKLUS NOTEHEADLU PLUS ESH2LOWERED FLAGAFU LEERAEWALOWER " + "CORNERNORTHERN TSELLE PATTERN LINKING MARKLINGING FIRELIMBS DIGITSLICKING " + "LIPSALLPOINT PENALT PAN SIGN OVER MIDDLEPROTOS ICHOS LINE SYMBOLPOUTING " + "FACEPORT CONTROL OF ANTIMONY ON PEDESTALPHEME JOINERRIGHT DOUBLE OVER " + "KISIM5 KLYUCHEVAYA OVER TWO PIRIGHT SINGLEOWER RIGHT-S SKEWED LEFTR-LINE " "STAFFRCHAIC SAMPI AND PICTURE AND TOP ENDRANCHING OUTREFACE COLONRAH BEN " "YOMORAFFIC LIGHTREN CROSSINGOVER KASKAL CROSSING GUQUIRREL TAILQUARTER " "SIGNQUARED ARROWREVERSE MARKRIAGE SYMBOLRIAL TRAMWAY IN TRIANGLEOGOGRAM " "NYAJRNAM BCAD MAONISHED FACEROLLING EYESON US SYMBOLOK HAND SIGNROUNDED " - "ZEROOING TO MEETOID NOTEHEADOHAZARD SIGNYMBOL BINDU YAN NUMERAL Y-MOUTH " - "FACEO-WALLPLANE NUITY SYMBOLS ABOVE SIGNXIRON KLASMANOTCHED TAILNOTCHED " - "HOOKNORTHERN TSEOUR TWELFTHSRING OVERLAYOUGHT BUBBLEOUCHES THUMBRION " + "ZEROOING TO MEETOID NOTEHEADOHAZARD SIGNYMBOL BINDU YAN NUMERAL RROUND " + "FROM Y-MOUTH FACEO-WALLPLANE NUITY SYMBOLS ABOVE SIGNXIRON KLASMANOTCHED " + "TAILNOTCHED HOOKOUR TWELFTHSRING OVERLAYOUGHT BUBBLEOUCHES THUMBRION " "CHRONONOTTOM HALF O WITH DAGESH WITH INDEX WITH UPTURN-DZUD RTAGS " "RISTMAS TREEOQ NSHUT YUMOPPOSING LU2OPLE HUGGINGOPENING " - "LEFTYOUTHFULNESSYOD TRIANGLEINTEGRATION HIBITED SIGNCENDING NODETHIC " - "LETTER BAHIRGOMUKHAINUSOID SIGNTHETA SYMBOLVAKRAHASANYABACK OF HANDBEHIND " - "CLOUDING OPERATORING HITTING ING HAND FANING ENVELOPETHODOX CROSST " - "MONGKEUAEQIRAGANA HOKACHAIR SYMBOLCHARACTER-18CHARACTER-1BIRTY-SECOND " - "THREE HEARTSVER EQUAL TOHEAD-BANDAGEATTOOED HEADIVE TWELFTHSHASIS " - "SYMBOLATNAH HAFUKHTERMINAL MARC-SSANGPIEUPHYPHEN-MINUSIGATURE SHRIBRATION " - "MODEIDENTICAL TOUSEATED FACET-WALLPLANE BRIDGE ABOVEBYSMAL WATERBSCRIPT " - "ALEFTEARS OF JOYTE SEPARATORBUTTON MOUSEINVERTEBRATEUTH ARABIAN BLUE " - "DIAMONDCABBAGE-TREEBLOWING FACETERNATE AYINILLED CIRCLEBLACK " - "CIRCLECALENDAR PADUTH-SLAVEY KHREE FINGERSIN MIDDLE UPBINING MARK INDEX " - "MIDDLEBETWEEN LIPSKANA REPEAT KHMIMIC KHEICK-O-LANTERNCIAN LETTER HALF " - "BRACKETARALLELOGRAMVICTORY HANDGREEN DRAGONHAH WITH DALCIRCLED " - "PLUSCIRCLES AND K-FEATHERED SS-THAN SIGNGROUND SLIDEL-WALLPLANE SUR OVER " - "SURGUARDED AREAHAND FORMAT KAPPA SYMBOLZZA WA JALLOR OPERATORRACHMA " - "SIGNRITING HANDHREE BALUDARANSMISSIONORCE SYMBOLRIPLE PRIMERADITIONAL " - "RISING DOTSGSUM -KHYILORT BARLINERAISED FLAGGE AT " - "NIGHTGAYANUKITTATETRAFONIASONIAN SIGN OLD NUBIAN ENTHESIZED OMAN SIYAQ " - "ROSS ACCENTROR-BARRED RONTHISMATATONAL MARK ENG DIGRAPHOPPOSING IMTRAIGHT " - "WAWROKUTASTI AREAKTHROUGHTENS DIGIT I TIMES NUNGRAMMA SIGNRCHAIC JNYAEN " - "STRAIGHTI TIMES BADOPPOSING ENPUT MORTUUMPERISPOMENIEEZING FACERIGHT " - "HEAVYRIGHT LIGHTRIGHT GUARDPARAKALESMATHIRDS SIGNHIGH STROKEUETTE BREADUG " - "RTAGS GYTIGHT ACUTEHEAVEN MARKPHNAEK MUANHEATED FACETHREE " - "TIMESPODCHASHIEMGHAIN WITH HAWH HMONG POST OFFICEHANG KHUDAMTIEE " - "SHEUOQOUNDED FACEGENTLE WINDHOKHLOM ON EDICAL MASKGUISED FACEOUTHERN " - "TSETHAM DIGIT OUBLE DANDAOUBLE ACUTEHORA DIGIT TH-THALATHARA SOMPENG RING " - "LIQUIDUBLE TONGUERESPONDS TOHAGGAR YAZHOVERSTRUCK HLETIC SHOEHITE " - "DRAGONQUIQUADRATERIGHT-LIGHTRIGHT-HAND QUERED FLAGLUPOVODNAYALU PLUS " - "IGISVASTI SIGNLTERNATE YAEUNJOMNDEUQLTERNATE AALTED FLOWERLT OF " - "CLOTHIVERY TRUCKLOTI NAGRI LOSING MARKLOSED ENTRYLON SKEWED SIMILE SIGNIX " - "TWELFTHSSINGLE AND JECT SYMBOLTWO FINGERSMED RGYINGSME LONG CANIPLE " - "TONGUEMBLER GLASSMBA BAYANNASHEQEL SIGNIRCLED TEXTJIHVAMULIYASYURA " - "SASAKETEI MAYEK MACING FACEISIGOTHIC ZLEAF CLOVERTUNE COOKIESMALL CLOUDLD " - "SCRIPT XLD POLISH OLCE TSA CANKRAINIAN IELATIN CROSSLEEP " - "SYMBOLKTIESELSKABSPIRATED FAFINAL SIGMAL OF THREADL TIMES LALL-SHAPED " - "HALACKLETTER LACK SULFURLINE FILLERLEU SATANGAJOYOUS LAKELETION " - "MARKSTORIC SITEKAARA POLLULEFT SYMBOLLEFT SINGLETRUNCATED ASTERED " - "SIGNLEFT DOUBLESTEAMY ROOMFIRE ENGINETA EQUAL TONTIMONY ORETRIAN CAMELNSE " - "CHEEKS FGHANI SIGNIEN MONSTERRYVNIA SIGNNITIAL IZHENIKOLSBURG IL " - "FRAGMENTS-SSANGSIOSNG LEFT LEGILCROW SIGNILIQUA SIGNOF MASHFAATEORGIAN " - "NARIBLE-CREE YOHINGYA YEHEPIDAUREAN RPOON ABOVETRESS SIGN OF " - "ENVELOPETRESVETLAYANYIS -KHYILRUNNING MANNUSVARA ONENUN HAFUKHAG-BJARKAN " - "BNUMBER ZERONUMBER SIGNMIDDLE HOOKMOVED BELOWMONOCULAR OT-DIAGONAL " - "SHAAYATHIYAMIDDLE STEMFOURTH ROOTMIDDLE BENTMICAL HEARTMFON PIPAEMESH " - "DIGRAPHTY THOUSANDERCENT SIGNND OF PIECEND ODD SIGNNBLENDED " - "UKIMULTANEOUSIN EQUAL TON-LUE KARANSECOND MARKN THE " - "VERGEINDERGARTENINDICESIMA MUUSIKATOANMUNCIA SIGN0 FOOTSTOOLATION POINTE " - "WITH VEILATION SPACEAESHAE NYAMCH AND LAMPAESCULAPIUSCELANDIC-YR WITH " - "TITLO WITH TRILL WRIST FLEX WITH PLATECE OF PIZZAWASLA " - "ABOVECCUMULATIONCARET TILDEACTIVE SIGNCAN RGYINGSURRENT SIGN WITH DASIA " - "TIMES ESH2DOUBLE RINGULO TWO SUMDOUBLE SHAD UPPER HALF WITH CARON WITH " - "COMMACHING CHICKWE PALAUNG DENT EMBLEM WITH FLASHAGONAL SIGN WITH " - "JACKSUMAN FIGURE WITH MAPIQATH PRODUCTAGAZ DAEG DWING NEEDLEBANK SYMBOLWO " - "TWELFTHSBOTTOM MARKDYO CHRONONUNIT DIGIT DIATONON DI6 LONG " - "NGGEVAMAGOMUKHABELOW RIGHT5 LONG MBOOUTH CORNERSDUATION CAPWINKING " - "EYEUNJO WYNN WVA V CHELNUBLACK ARROWWITH GARDENBETA SYMBOLUTING " - "WHALEBUMPY ABOVEACKED COMMADESK PERSONAWNING FACEE NOTEHEAD BZHI -KHYIL3 " - "LONG NGGOUSHING HANDAILLESS PHIVE OF PEACEXTINGUISHERXI RADICAL XESTES " - "SIGNBREVE BELOWXAGRAM FOR VARYS ICHOSWHITE JOKER OF FORTUNECROSSING " - "PICROSSING IMCROSSING ENCROSSING BUEAVER DENE OF FLOWERSZERO THIRDSDE " - "KIKAKUI OVER BULUG OVER IDIM VYKA ABOVE ARM SPIRAL AMUSED FACEZIGZAG " - "LINEDASH SYMBOLDONG TSHUGS I ZAPYATOYCURVED BENDDOLLAR SIGNUISHED " - "FACEARAM GONDI CTION MARK DECORATIONCROSSING URCOMBINATION S " - "ZAPYATOYDOACHASHMEECREDIT SIGNVISARGA ONE SHOE STILE TACK BELOWDOUBLE AND " - "DALETH-RESHASE TO THE DOUBLE MARKARPEGGIATO ARMS RAISEDCONTAIN AS E2 " - "TIMES AN PLUS MASH2 PLUS NUNUZ AND MACRONCOND SCREENUPADHMANIYA " - "PROPORTIONAR ECLIPSEINITIAL RABA SATANGAL-AMMONIACION BOTTLEINDU " - "BELOWBELOW LEFTLA USED ASW OR MODELSMILO SIGNLACK JOKERING-SHIFT VIE " - "CAMERAINHERENT AST PALETTEATTY WITH ATRICHISMAIXTHS DISHKHAMTI " - "TONST-FEEDINGSTRUCTION LANE MERGEKINDI MVOPKAI SYMBOLSTROM SIGNJONG TILE " - "ASTERISCUSKA SATANGAASPIRATIONK2 PLUS BUSTRAL SIGNSSANGARAEASPACE MARKT " - "AND BOLTAYER BEADSVEL SLIDERKRYZHEVAYASYMBOL VIDSS OF MILKISMUTH OREIT " - "MBAAKETVERAGE BOXSYLLABLE MAUTOMOBILEITH DIGIT H-HAGALL HCROSS " - "MARKCROPHONIC TOP CORNERGHT LIFTERGIMEL-HETHGOLUBCHIK COMPONENT GREE " - "SLASHCOLATE BARGUA PI MAOTING HEARTTIMES SIGNGGRAVATIONH-LOW " - "TONEHAAPRAANA CISIVENESSCIRCLED CAUR CORNERSUR HUNDREDHAMZA MARKHAN DIGIT " - "UR YIG MGOUPPER HOOKTRIPLE DOTUP OR DOWNFOR RECORDFORMATTINGDA SATANGADA " - "PLUS HAD WITH DOTFRONT WALLD KEYBOARDFTOGGOS OUCY MESSAGEG MUNDARI " - "G-HAGALL HTRETCHED CTRESS AND TREFACTIONCURLY HAIRCURLED WAWGAGE " - "CLAIMGANDA MARKGAP FILLERGAS BZUNG GBAKURUNENGGING FACEICK FIGUREIDDLE " - "MARKBSTRUCTIONBROKEN BARIDEOGRAPH IED SHRIMPTAMAN SIGNIGATING RAIGATURE " - "OETAIL GLASSBOLD SHAFTICAL TAPERIKRON ISONT-TO-LEFT BLUE HEARTILE " - "FOLDERT-STACCATOUTH OR SPYBLACK FLAGINDEX BENTHEAVY BEATCHECK " - "MARKHERMOMETERCHAD RTAGSCH BALLOONTHMIKON N URIPIGMENTTHDAY CAKETHAPASCAN " - "HOOK ABOVECAPITAL ETHOTIC HOOKHREE ABOVETESE CROSSTERNATIVE HUNGARIAN I " - "ARCHAIONURVED OMETC WITH DOTTEMPLATIONUSEL HORSE WITH LOW WITH BASE WITH " - "BELTOTING STAR WITH EGGSRING THUMB WITH PAGEOSTAL MARKOSSED SHEI WITH " - "RAINORTHERN TA WITH RINGOUND OMEGA TIMES SHEOUR FIFTHS THOUSANDSOUT INDEX " - "OUTER JOINOUTHERN TARING ABOVEYEH BARREERUPEE MARKRUDIMENTA O-STACCATORSI " - "SYMBOLOANDAKHIATOF HYGIEIA2 PLUS ASHROUNDED ERROUND DOT 2 LONG MBOOLING " - "FACEOLON EQUAL SCHROEDEROMMA BELOWON MEDIAL 1 LONG MBEROEZENIAN ROAD " - "OMEGAOON LILITHOON SELENAYMBOL AIVAOP NKAARAEOPEN SHELFRKING FACEOROME " - "SIGN WITH TICK WITH TAIL LATE FORM KABA TENURHO SYMBOLRGE SQUARERGE " - "CIRCLEREVERSED I DRAWINGS QUISH QUADRESH BELOWR2 PLUS SUZH " - "DIGRAPHRAGGISMATA AND MOUSE AND KNIFE AND BREVERCHAIC KHA AND " + "LEFTYOUTHFULNESSYOD TRIANGLEINTEGRATION BACK OF HANDCENDING NODETHIC " + "LETTER BAHIRGOMUKHAINUSOID SIGNTHETA SYMBOLVAKRAHASANYAHIBITED SIGNBEHIND " + "CLOUDING OPERATORING HITTING ING HAND FANING ENVELOPET MONGKEUAEQTHODOX " + "CROSSIRAGANA HOKACHAIR SYMBOLCHARACTER-18CHARACTER-1BIRTY-SECOND THREE " + "HEARTSVER EQUAL TOATTOOED HEADHEAD-BANDAGEIVE TWELFTHSHASIS SYMBOLATNAH " + "HAFUKHIDENTICAL TOTERMINAL MART-WALLPLANE HYPHEN-MINUSIGATURE SHRIBRATION " + "MODEUSEATED FACEC-SSANGPIEUPBYSMAL WATERBRIDGE ABOVEBUTTON MOUSEBSCRIPT " + "ALEFTE SEPARATORTEARS OF JOYINVERTEBRATEUTH ARABIAN BLUE DIAMONDBLOWING " + "FACETERNATE AYINCABBAGE-TREEILLED CIRCLEBLACK CIRCLEUTH-SLAVEY KCALENDAR " + "PADHREE FINGERSIN MIDDLE UPBINING MARK INDEX MIDDLEBETWEEN LIPSCIAN " + "LETTER HALF BRACKETARALLELOGRAMHAH WITH DALVICTORY HANDCIRCLED " + "PLUSCIRCLES AND K-FEATHERED SUR OVER SURSS-THAN SIGNKANA REPEAT KAPPA " + "SYMBOLCK-O-LANTERNGREEN DRAGONGUARDED AREAGROUND SLIDEKHMIMIC KHEIAR " + "DIAERESISHAND FORMAT L-WALLPLANE ORCE SYMBOLENTHESIZED GAYANUKITTAOMAN " + "SIYAQ RANSMISSIONRITING HANDROSS ACCENTRAISED FLAGRISING DOTSOLD NUBIAN " + "TETRAFONIASORT BARLINEGSUM -KHYILRADITIONAL RIPLE PRIMEGE AT NIGHTZZA WA " + "JALLRACHMA SIGNROKUTASTI AONIAN SIGN ENG DIGRAPHTRAIGHT " + "WAWRONTHISMATAROR-BARRED REAKTHROUGHTENS DIGIT I TIMES NUNOR " + "OPERATORTONAL MARK EN STRAIGHTGRAMMA SIGNRCHAIC JNYAI TIMES BADOPPOSING " + "ENOPPOSING IMPERISPOMENIEEZING FACERIGHT HEAVYRIGHT LIGHTPUT " + "MORTUUMPARAKALESMATHIRDS SIGNHIGH STROKEUETTE BREADUG RTAGS GYTIEE " + "SHEUOQPOST OFFICEHAWH HMONG HANG KHUDAMPODCHASHIEMGHAIN WITH QUERED " + "FLAGTHREE TIMESHEATED FACEPHNAEK MUANHEAVEN MARKTIGHT ACUTERIGHT GUARDRA " + "SOMPENG GENTLE WINDHOKHLOM ON THAM DIGIT EDICAL MASKGUISED FACEOUNDED " + "FACEOUBLE DANDAOUBLE ACUTEHORA DIGIT TH-THALATHAHREE BALUDAOUTHERN " + "TSERING LIQUIDUBLE TONGUERESPONDS TOOVERSTRUCK HAGGAR YAZHHLETIC SHOEHITE " + "DRAGONQUIQUADRATERIGHT-LIGHTRIGHT-HAND SVASTI SIGNLUPOVODNAYALU PLUS " + "IGIEUNJOMNDEUQLTERNATE YALTERNATE AALTED FLOWERLT OF CLOTHIVERY TRUCKLOTI " + "NAGRI LOSING MARKLOSED ENTRYIX TWELFTHSLON SKEWED SIMILE SIGNJECT " + "SYMBOLSINGLE AND TWO FINGERSIPLE TONGUEMED RGYINGSME LONG CANMBLER " + "GLASSMBA BAYANNASHEQEL SIGNIRCLED TEXTJIHVAMULIYASYURA SASAKETEI MAYEK " + "ISIGOTHIC ZMACING FACETUNE COOKIELEAF CLOVERSMALL CLOUDLD SCRIPT XLD " + "POLISH OLCE TSA CANKRAINIAN IELATIN CROSSLEEP SYMBOLKTIESELSKABSPIRATED " + "FAL OF THREADFINAL SIGMAL TIMES LALL-SHAPED HALACKLETTER LACK SULFURKAARA " + "POLLULINE FILLERJOYOUS LAKELEU SATANGALETION MARKSTORIC SITELEFT " + "SYMBOLLEFT SINGLESTERED SIGNTRUNCATED ASTEAMY ROOMLEFT DOUBLEFIRE " + "ENGINETA EQUAL TORYVNIA SIGNTRIAN CAMELFGHANI SIGNNSE CHEEKS IEN " + "MONSTERNTIMONY ORENITIAL IZHENIKOLSBURG IL FRAGMENTS-SSANGSIOSNG LEFT " + "LEGILCROW SIGNILIQUA SIGNOF ENVELOPEEORGIAN NARIBLE-CREE YOHINGYA " + "YEHEPIDAUREAN RPOON ABOVEOF MASHFAATTRESS SIGN TRESVETLAYANYIS " + "-KHYILRUNNING MANNUSVARA ONENUN HAFUKHAG-BJARKAN BNUMBER ZERONUMBER " + "SIGNMIDDLE HOOKMOVED BELOWT-DIAGONAL MONOCULAR OSHAAYATHIYAMIDDLE " + "STEMFOURTH ROOTMIDDLE BENTMICAL HEARTESH DIGRAPHMFON PIPAEMTY " + "THOUSANDERCENT SIGNND OF PIECEND ODD SIGNNBLENDED UKIMULTANEOUSIN EQUAL " + "TON-LUE KARANINDERGARTENN THE VERGESECOND MARKINDICESIMA " + "MUUSIKATOANMUNCIA SIGN0 FOOTSTOOLATION POINTE WITH VEILATION SPACEAESHAE " + "NYAMCH AND LAMPAESCULAPIUSCELANDIC-YR WITH TITLO WITH TRILL WRIST FLEX " + "WITH PLATECE OF PIZZAWASLA ABOVECCUMULATIONCARET TILDECAN RGYINGSURRENT " + "SIGNACTIVE SIGN WITH DASIA TIMES ESH2DOUBLE RINGULO TWO SUMDOUBLE SHAD " + "UPPER HALF WITH CARON WITH COMMACHING CHICKWE PALAUNG DENT EMBLEM WITH " + "FLASHAGONAL SIGN WITH JACKSUMAN FIGURE WITH MAPIQATH PRODUCTAGAZ DAEG " + "DWING NEEDLEBANK SYMBOLWO TWELFTHSBOTTOM MARKDYO CHRONONUNIT DIGIT 6 LONG " + "NGGEDIATONON DIVAMAGOMUKHABELOW RIGHT5 LONG MBOOUTH CORNERSDUATION " + "CAPWINKING EYEUNJO WYNN WVA V CHELNUBLACK ARROWWITH GARDENBETA " + "SYMBOLUTING WHALEBUMPY ABOVEACKED COMMADESK PERSONAWNING FACEE NOTEHEAD " + "BZHI -KHYIL3 LONG NGGOUSHING HANDAILLESS PHIVE OF PEACEXTINGUISHERXI " + "RADICAL XESTES SIGNBREVE BELOWXAGRAM FOR VARYS ICHOSWHITE JOKERCROSSING " + "IM I ZAPYATOYCTION MARK CROSSING URZERO THIRDSCROSSING PIDONG " + "TSHUGSCROSSING ENCROSSING BU OF FLOWERS OF FORTUNEDE KIKAKUI OVER " + "BULUGARM SPIRAL OVER IDIM EAVER DENE DALETH-RESHVISARGA " + "ONEDOACHASHMEEUPADHMANIYA AND MACRONDOUBLE MARK DECORATIONARAM GONDI " + "UISHED FACEDOLLAR SIGNCURVED BENDDASH SYMBOLZIGZAG LINEAMUSED FACEDOUBLE " + "AND SHOE STILECOMBINATIONCOND SCREEN TACK BELOWARPEGGIATO S ZAPYATOY " + "PLUS NUNUZ PROPORTION PLUS MASH2E2 TIMES ANCONTAIN AS ARMS RAISEDCREDIT " + "SIGNASE TO THE JONG TILE AR ECLIPSELA USED ASVIE CAMERASTROM SIGNKAI " + "SYMBOLW OR MODELK2 PLUS BUKINDI MVOPINDU BELOWING LARGE SMILO " + "SIGNING-SHIFT STRAL SIGNINHERENT ALACK JOKERASPIRATIONINITIAL RAKA " + "SATANGAASTERISCUSBELOW LEFTVERAGE BOXSS OF MILKSSANGARAEAISMUTH OREIXTHS " + "DISHIT MBAAKETKHAMTI TONSYLLABLE MAUTOMOBILEITH DIGIT ATRICHISMAST " + "PALETTEATTY WITH T AND BOLTLANE MERGEION BOTTLESTRUCTION L-AMMONIACBA " + "SATANGASPACE MARKAYER BEADSST-FEEDINGVEL SLIDERKRYZHEVAYASYMBOL " + "VIDH-HAGALL HCROSS MARKCROPHONIC TOP CORNERGHT LIFTERGIMEL-HETHGOLUBCHIK " + "COMPONENT GREE SLASHCOLATE BARGUA PI MAOTING HEARTTIMES " + "SIGNGGRAVATIONH-LOW TONEHAAPRAANA CISIVENESSCIRCLED CAUR CORNERSUR " + "HUNDREDHAMZA MARKHAN DIGIT UR YIG MGOUPPER HOOKTRIPLE DOTUP OR DOWNFOR " + "RECORDFORMATTINGDA SATANGADA PLUS HAD WITH DOTFRONT WALLD KEYBOARDFTOGGOS " + "OUCY MESSAGEG MUNDARI G-HAGALL HTRETCHED CTRESS AND TREFACTIONCURLY " + "HAIRCURLED WAWGAGE CLAIMGANDA MARKGAP FILLERGAS BZUNG GBAKURUNENGGING " + "FACEICK FIGUREIDDLE MARKBSTRUCTIONBROKEN BARIDEOGRAPH IED SHRIMPTAMAN " + "SIGNIGATING RAIGATURE OETAIL GLASSBOLD SHAFTICAL TAPERIKRON ISONT-TO-LEFT " + "BLUE HEARTILE FOLDERT-STACCATOUTH OR SPYBLACK FLAGINDEX BENTHEAVY " + "BEATCHECK MARKHERMOMETERCHAD RTAGSCH BALLOONTHMIKON N URIPIGMENTTHDAY " + "CAKETHAPASCAN HOOK ABOVECAPITAL ETHOTIC HOOKHREE ABOVETESE CROSSTERNATIVE " + "HUNGARIAN I ARCHAIONURVED OMETC WITH DOTTEMPLATIONUSEL HORSE WITH LOW " + "WITH BASE WITH BELTOTING STAR WITH EGGSRING THUMB WITH PAGEOSTAL " + "MARKOSSED SHEI WITH PLUSORTHERN TA WITH RINGOUND OMEGA TIMES SHEOUR " + "FIFTHSOUT INDEX OUTER JOINOUTHERN TARING ABOVEYEH BARREERUPEE " + "MARKRUDIMENTA O-STACCATORSI SYMBOLOANDAKHIATOF HYGIEIA2 PLUS ASHROUNDED " + "ERROUND DOT 2 LONG MBOOLING FACEOLON EQUAL SCHROEDEROMMA BELOWON MEDIAL 1 " + "LONG MBEROEZENIAN ROAD OMEGAOON LILITHOON SELENAYMBOL AIVAOP NKAARAEOPEN " + "SHELFRKING FACEOROME SIGN WITH TICK WITH TAIL LATE FORM KABA TENURHO " + "SYMBOLRGE SQUARERGE CIRCLEREVERSED I DRAWINGS QUISH QUADRESH BELOWR2 PLUS " + "SUZH DIGRAPHRAGGISMATA AND MOUSE AND KNIFE AND BREVERCHAIC KHA AND " "ARROWRDHACANDRA AND ACUTEZU OVER ZURECIPITATERED DRAGON OVER KAD5 RGYA " "GRAM RESUPINUSRIGHT SIGNZAR AMULET POVODNAYA PLUS SHU2PASSIMBANGPEDAL " "MARKRIGHT HOOKZEIRO SIGN OF DHARMAPLUS BELOWPLUS ERIN2PLUS NAGA POETRY " "MARPOLICE CARPOUND SIGNPPOPOTAMUSPRALINEAR LPAPRAANA EBENSTIMMELL " "MODIFIEW-MID TONEAKKHANGYAOLLOW HEARTLOGICAL ORLONG FINALLONG OVER LONG " "TSHEGAILED BIRDLOWER HOOKALEF LAMEDSIDEWAYS ILTERNATE ULTIC " - "CROSSAEDA-PILLAM STALLIONADDA WITH ADAK BINDIMADDA MARKMALL ALEPHACE " - "FILLERSHMIRI YEHLEK ATTAK SMALL TAH ANGULAR TOLE LETTER " + "CROSSAEDA-PILLAM STALLIONADDA WITH ADAK BINDIMADDA MARKSHMIRI YEHMALL " + "ALEPHACE FILLERLEK ATTAK SMALL TAH ANGULAR TOLE LETTER " "LE-DELAYEDANGKHANKHUANDHI MARKLEFT GUARDLEFT HEAVYLEFT LIGHTLEFT " - "SERIFLEFT-HAND ABATA TREELENDED YUSLET SYMBOLALLY MARK LGIZ " - "EOLHXSIXTEENTHSLHAG RTAGSLIGHT BEATLIGHT BULBALENT SIGNALEF WITH " - "LIMITATIONLINDRICITYWO SHORTS SELINE ESHWITH STRAWN NGGEUAETSE-CREE " - "SKWITH WINGSNAKE BELOWSBUB -CHALNANGMONTHONASPIRATEDNDA PA NJINDU " - "TEMPLEWITH SPOONNGLICANA WNGUAGE TAGXED BICEPSXHEEJ CEEVNOTE WITH NTITY " - "MARKNTO SHRINENUMBER TENY AND RICEMILLE SIGNAB2 TIMES ME PLUS ENSHARP " - "SIGNMEEM ABOVEWHITE FLAGWHITE HAIRMEL SYMBOLWHOLE NOTEWING HEARTA TANG " - "LAIA PLUS KURA PLUS IGIVIOUS PAGEMINO TILE SGOR RTAGSMONOFONIASMONOGRAM " - "BMONOSPACE MONTH SIGNMOTORCYCLEED FINGERSUP NEUTRALEQUIHOPPEREICH " - "STARKENETRATIONF SHE-GOATUMAN EARTHEIGHTIETHSUBLE DASH DIRGA " - "MUREDIATONIKI ELT BUCKLEEUTRAL YERU2 PLUS BAENTHUSIASMTWENTIETHSDED " - "PERSONTWO SHORTSDUOUS TREEUM ROTUNDADIGIT ZEROEDESTRIANSTWO THIRDSEARLY " - "FORMEEKING EYEUAM TSHOOJEONGCHIEUMFAHRENHEITTYPE COLONENS " - "SYMBOLFFICULTIESUP HARPOONEVERSED PEUARDEDNESSEARTH MARKUNKIA SIGNE PLUS " - "SUMETTA-PILLAU CIN HAU DOUBLE BARFINAL HETHVEUAENGAMARISTERA URNED AYB0 " - "LONG LEEEN WITH CARTRIDGEETER SIGN PLUS GALED PLANETSTAL BALLKU RU " - "KHAHIMA SIMA PLUS SAGS DIGRAPHHOT SASAKKSTREPTONXHAUSTIONCANG " - "TE-UHINOCEROSUNGLASSESDUS RTAGSYRANISMA ONE THIRDKING BOOTE AT " - "LEFTQUADCOLONARM CLOCKKEMPHRENG GARSHUNICAPITAL QCAPITAL IRFUL FACE PLUS " - "KU3HOOK MARK FROM BARCAPITAL D PLUS GUDURLY " - "LOOPMUKPHRENGSTEBASKETSEMICOLONURNED GANHIYYAALAA PLUS LALLARGEMENTAOS " - "ICHOSVINE LEAFLAN SIGN RA OR RITTED STEMHARD SIGNDENT AND SMALL " - "YUSEMBEDDINGELEGRAPH PADE SUITR PLUS RAHEADSCARF DIVIDERSANTAYALANHALF " - "SIGNHALSHELET RICKSHAWVISARGAYANVERTED RANSKRIT SON GROUNDRWARI DDA3 PLUS " - "ANNUSVARAYAY BLOSSOMANTHAKHATCHOSEONG UR-DE-LISED DIGIT " - "PAA-PILLAHARACTERSARCHAIC MPANYANGGANTESSENCENTERPRISE-KHYUD PAHI " - "SYMBOLSEPTEMBERQUEEN OF WITH FACEURUZ UR UL ME HANDVICE MARK PLUS ZA7KYO " - "TOWERMRACHNAYASPIRITUS NSERT AT PLUS TURVIGINTILEON TEUAEQFEH WITH " - "LACKFOOT QUSHSHAYASOF PASUQCHAVIYANION-JOINERNTRACTIONCHANICAL " - "L-THIEUTHDEPARTUREL-PHIEUPHZIR SASAKL-KHIEUKHBASE UNITNGER SHIPNGER " - "ROOTIGHTH ASHROJECTIONVANAGARI NCLOSING BEER MUGSIGN NUKTAIGN SAFHAIGN " - "TOMPIPLE HEART5 LONG JONG SANDAL OF BLOODTABE SIGNWRINKLES B " - "DIGRAPHTANDSTILLPIDERY HAT OF MEATTAKHALLUST ON BONEPOSITIONSPPOSITIONOP " - "HALF O OF PAPERPPOINTED IGH HAMZABOTH BENTZERO SIGNUTRA MARKBIAL " - "SIGNWORDSPACETUTEYASATBICYCLISTRO WIDTH E SCOTS SUMED HEADBKHASIAN BITE " - "LIPSRIED FACEINARBORASIN SQUAREINAL NOTEBING CANEUVUZHAKKUINNYIIYHEOO " - "DENNENINISHMENTBO GYFU GBO BAIMAIING STONENFORZANDONDAILING ING " - "LANEST-THIEUTHILE TILDEUURDHAJA ILIPPINE ING GLOVEING DOLLSING CARD RNEY " - "PARAPENTASEMEUE MAEMBAPENT SIGNHWAZ EH EETTI " - "BALLJERUSALEMTUKWENTISXCITEMENTI PLUS LIN-CREE THX-X BELOWATHAMASATTEH " - "ABOVE OVER LUMIVINATIONONGSEONG TED PLANTN MODIFIEFACING UPKAMEYTSA AS " - "MEMBERHREE FOR NO TELEIAKA- SHOG UNGSEONG ATTACHED " - "TROMIKONK-KHIEUKHK-CHIEUCHETRASIMOUSTRELNAYAK GESTUREIRST MARKVER " - "LUGALZENE RINGNIHSHVASANIGHT OF 1 CHARIOTISEN-ISENNIGGAHITAWRY " - "SMILEVELOPMENTICE CREAMEURO SIGNBRUL SHADNGUN SIGNIDEOGRAM IDEWAYS " - "UN-PANSIOSIA SYMBOLEMPTY SETVERLONG AIALECT-P ITRA SIGNNING SIGNONG GRAVE " - "OVER BAL5 BATHTUB5 CYPERUSNA KHONNAAVE ARROWPROJECTORER BUBBLE " - "STREAMEROTAL SIGNAINTBRUSHOCCLUSIONAISED DOT APODEXIAFINAL NUN AND " - "TAILLONG TIP CRESCENDOFINAL NGAFINAL MEM247 DIPTELOND HAIRAJANYALANWASH " - "TAILAF PERSONCUBE ROOTRCHAIC IIFISH TAILAFFE FACE AND CURLODIASTOLEDOWN " - "HANDLOWER DOTOVER MUSH2 GARMENTALAYALAM CONJOINEREAVY DOWNLIVERANCEERCIAL " - "ATREFORMED LITTLE UP SPARKLERLISSANDO EIGHT OF LINE FACEGREATER " - "YCOMPLETEDLIGHTNINGOW KAVYKATONE MAI Y-FOURTHSY-FOURTH CORN " - "FACEUPTSTIMMEGITTARIUSMETOBELUSLLABLE OMLLABLE B0TO CORNERAL " - "RUNOUTMHANCHOLLD SALTIRE TIMES HAMALL RINGOKOUFISMAMBROIDERYFROM WALLE-EM " - "DASHRED JOKERFLAT SIGNMAEMGBIEEABOVE TO TIMES UDMARK SHADMARK CIM DAD " - "WITH Z DIGRAPHOKED HEADULL BLANKOKED TAILFOUR BENTEBIT SIGNDRAM " - "SIGNELLOWSHIPACE NOTE OVER GAN2LVIN SIGNOUTH WINDTREDECILEENTRY SAWRDEL " - "DKARTRAIGHT U AND BELTDOWN STEPRCHAIC RACULTATIONDOWN SIGNUPPER DOTG IN " - "HOLEOURA SIGNREAK HEREUBSTITUTEADEG ADEGM HE-GOATHALF NOTEREDNE ON " - "G-PANSIOSADMA GDANRPORATIONU TTUDDAGOF STIMMETRESVETLOOUT MOUTHP " - "DIGRAPHES AKURU YEH ABOVEOM SYMBOLRTS MEDALP ELAMITECLOSED " - "PLALPAPRANAO-EM DASHRTER MARKHAIKSUKI ESAME DOTSHAB CEEBANEROSIS WING " - "STAREFORMED TORTH WINDEFAIDRIN H-KHIEUKHZAL SASAKZAKRYTAYAH-CREE " - "THH-THIEUTHYEH WITH ERTY LINELEFT TACKVOETOCHIELEFT RINGTIMES NA2TIMES " - "PAPVOCALIC RCK SEXTANA PLUS NAALI GALI COIN SIGNP-PHIEUPHYEAR " - "SIGNANGGEUAETVRAKHIYA GRIK SIGNANG CITI SIVE FACEEOUT BOXNAVIYANIAPITAL " - "FEGORIAN ESH LOOPDIFONIASAMS HORNMIONIAN VE SASAKNAMENNY NCE " - "SIGNM-KIYEOKWO ABOVEANC SIGNBACKWARDM ALLAAHDOCUMENTT OCLOCKBIEE FON ON " - "LEFT OF YARNT NGGEETOVER BU DVANTAGEAEN NYAMEK ONKARAY-NIGHTIS FORM IS " - "WHEELIS-PILLAZAKRYTOELUB SUITOVER GA2LTRY LEGOVER GI4A SIGN AORM FEEDIRD " - "MARKBILLIONSE-MACRONVOMITINGAZHAAKKU " - "TALENTSVOLUTIONDVISVARAT-KIYEOKOTIFIED SCAN LINMARRATAN " - "RASWADIEVERANCEMANGALAMV OVER MACKSPACE NUTILLUABAAFILIMALL AXESHOE JOTME " - "BADGEABOAFILIANE TREEDIAMONDSLATION XP-KIYEOKING BOWLING BELLING ROD " - "MANDARINEN NTEUMBER POLEBEVERAGEM-TIKEUTWBOY HATE-WELSH ANS SIGNT-HINGE " - "P-TIKEUTUKEUTNDAMMATION ULLS LEGSHORT ERSANYAKA EVEN OF 56 TURO2INAGARI " - "MON TIMESHKIR KAT-BISHOPBATBEIT LEANING OT MBUAEMY HOUSEKASRATAN " - "POLNAYALF RING ER TRUTHLOCATIVERIYOOSANARCASITEERAL URNARRIVINGL " - "POLISHDUSHENNA PLUS DI PLUS DUL-LAKUNAL-KIYEOKAIYANNOILONG " - "BARKAIYARAAARTYRIA ALLIANCEARSI YEHYPORROONOVERRIDEOREHEAD YRILLIC ETA " - "SIGNUNG DASH SLIDINGSENTAGONARKLEAN UDAWADI SQUEEZED0 BRONZEEREVODKA PLUS " - "RUDIT CARDLKULIZMYW PRINTSPAVIYANILFWIDTH SPERSIONERDIGRIS8 KANAKOET " - "SHOESVESSEL BSIX DOTSRILLIONS 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- "BUTTONCLEAVERP-CIEUCLAGIOS PALLAWALEK TOOH-HIEUHALTILLOVILIK BH-AR " - "AEORTIETH3 SPICEURFACE UP HANDWIFRUITH-NIEUNH-OSS OORT-TWICHEINAPMINIMA " - "H-PIEUPVOWEL KMINGKALH-MIEUMVILLAINAM ALEFTYSCAPER2 " - "GUNUANGOLATANGLONGLASHES 3 MONTHANGLED LE LEAFANGKUOQSERPINADOFONONRY " - "FACEAPEZIUM9 NGGAAUN MEUTLAYANNAON FACE CHIKI HALANTASEXTILEHANGUL " - "REREKAN CER-WAY GREENY HEART RAMBATENSHUETURATIONCHEVRONAND ENDCK " - "LIMEHEADINGRUM CLEOMERANGLAK-050ZQAPHA P-HIEUHHAARKAAAN MARKORKHON " - "RESILLOP-NIEUNP-MUOY RA REPALAMITE P-MIEUM WOLOSOVOICINGTIKRAMAHAYANNA3 " - "OMEGANUMBERSYELLOW ECEMBER2 WOMANAELAENGDAYANNARDO RJEOF SOAPG-TYR TG-SOL " - "S TEDUNGLYGISMAOUT HUBG-RIEULG-OSS OG-MIEUMWAZ " - "EOHG-HIEUHOFFICERM-HIEUHOLAPUK M-MUOY TROLLEYYA LAMPYAH LI " - "TRYASKAYAYANNARIPPLE GAYANNAEAVY YAAETMEUNM-NIEUNRRECTUSMEETORURD DISKRD " - "FACEOVER DUSIDDHAMTRAINERUM IYEKUP MARKOVER ANOKRYTIED-ANGLEMBOL B02 " - "OLIVEMANCHU REATHY WAAJIBDA FACEUP TACKUP STEPFLUENCEUP SIGNSHIFT " - "TMASSAGESHORT AM-PIEUPM-RIEULMAAYYAAYANMAR OGDIAN DANESE AD NECKOUR OF " - "MAI SATWDRIVERDRIL BUU-EO-EUACTER TD MADDADANCINGD MOUTHOX LINEOX BACKA " - "NAME 3 AREPATSECHKAFINAGH ALESMA OWILO SRAKHANGLIGHT XCOMING DU NJAA " - "SLOWLYWIGNYANVYSOKO DEAVOURUBUFILIL-MIEUMGRADUAL SHAKERCLOSE EALLOT XLEUT " - "KARTHIAN 3 EIGHTTIVATE LEYBALLRISIMOULF FACEY-CREE CLOTHESERNIN AA " - "-PHRUCOASTERSIGN UDCRACKERA-HIGH MERICASGHEUGHE APLOUNFINAL Y STRIDEOCK " - "SALAHAPAKHOCTAGONOCTOBERGENERALRAYANNATORNADOSHAKINGLJUDIJEGOLIAN " - "CONTACTRANGKEPCOPTIC P PIEETOT NGOMER THANLLYFISHGLAGOLIEIGHT KOW " - "ALEFRARIETYOT REPH26 EYYYBUFFALONIKAHITF DAVIDIC " - "WANDTAYANNATCHFORKBULANCEIBIFILIS-IEUNGISIBLE ITALIC S-HIEUHIANGQI " - "UKKAKHAS-CIEUCEULEUNGAUNTLETAULDRONPRENKHAT ASHESPHUTHAOBREVIS " - "S-RIEULS-PIEUPSYNAGMAITON RAS-NIEUNTASHEEL0 SPEARROKEN " - "LS-MIEUMICYCLESUSSYERUAY SIGNSCOOTERICOPTERAXIMATAN-CIEUCATH OF JAIN OMI " - "RTAGSI NTEUMJARATI JAYANNAC-HIEUHJECTIVESUKUUDON-BREVENJAEMLI KEFULAJERAN " - "JC-IEUNGJIBWAY ATAEAN ASUTORUPTHAHA PERVISEN-RIEULF SASAKAU " - "MARKPSTICKSN-PIEUPIVE-PULONGONANN-HIEUHN-GRAVEIL DRUMSANDHI DHALATHSANGAN " - "BERRIESBERGINEPOMOFO UYGHUR DIARGONILLEANNWO MARKDYNAMICWO FOR PLOYAN " - "BOARDERIKHAHITINNABARTA MARKT-CREE NG MASK MENDUT MUQDAMT-MIEUMSAMPHAOWO " - "WAENYMAIC LT-PIEUPBLACHKOEL PUMPBIG YUST-QUEEN6 NGGOOIMILAR MUOMAEEN " - "LEAFT-HIEUHT-RIEULT-HIDETNEQUDAAT-SHIRT5 NGGEENESTED TALL AAOP " - "MARKPPROACHVAV YOD MAELEEYNAMIC UT TIMEEAD ORE0 WHEATIFIED " - "EVAYANNASAYANNA OPEN-OVE DOT NANCIAL LONSUMS-SAJDABORZAYAT-CIEUCROGRESSSA " - "VAH POVODNYVANESE VAPOURS1 ARROWWORSHIPONTIEENBARREKHTAISYOURMUKHI " - "BAMBOOSBOURINGNAYANNABAIRKANTTILIK THALIYADISIMOUE " - "DRINKTTHACANORCULUSHIUCHUS FLEXUSTHESEOSKOMBUVAKOQNDONKORONISQUARIUSKPAK " - "WAKAYANNASTERING7 NGUANCAP TENKARO " - "BASEGMENTFATIGUEPAYEROKPAYANNAKEUAERIDIPLOUNKHA YATST " - "TUBECAYANNAMUNGKAHARRED OARRED BHEXAGONOREVMA QUEEZE THKUQI SOV ROGHI " - "SIGNL-CIEUCNTAINS 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"AGUNGD-OVALFORTISDAGGERGEDOLAGEADALRBITSAGBASAQCUMBERGANGIACUPPEDTRAPLIG-" - "SIOSG-AR AHIBIT EPOCHED " - "ICEHEUAEPCHADINHERMESCHAMKOCEVITUHEISEICHEIKHCHEMA CHESS HIMAHUHIVETE " - "EQUID CARETHALF HRENGTHRAAKANTIKENORACINGUP " - "BOWCKNESSTIMATEREMEDYH-SIOSCHO CHHE MGO DIPLICHIRETHASHKAED CAPFF OF " - "CHURCHHAMILOHAMEDHHAM AIESTAN " - "PALUTAARADDOL-SIOSSOUNAPAILUREAGRANTAGOGUEUDARKAARBUTAET KUTLONG " - "EAPISMALAMEDHLAMADHAPLI MAJANI AFFIX LAFRONAPYRUS QATANVILIANKTIKO " - "KRISISAESURASICKLEAEMMAEKLITONE-SHIFKILLERUNGAAMSPLIT SPITALKUSHU2KY WAYL " - "BACKSPATHISPADESLITIKILISHA LIGIONLIGON U MBITRIISAPERMATASIXTHSSKAPI LD " - "MAPANIMALLLIPOPW-TAILP-SIOSANUARYLASTONAKABATVIRIAMAK-668DOKMAIP-" - "RIEUANGKATANCHOR RULEROW TIE SPLITITABLEAUTUMNMALGAMASSINGPENCIL " - "TIKHYSTROFOMADDAHEUNYAMASHGABISSIMOIX OF ACINTHATTIC " - "ATTERYSHMAAMEUAENAITULUMSURED SURANGK-1358MALL FEPACT IXTY PIYANNAITHER " - "SUCKEDPEPPEREU MBUSTANCEPEAKS ISSHARISSANTKAYAH PBOARDKE " - "PHOSTANCYEUREUTMARCATKEYCAPSYNAFIM BULLM BOARWBERRYK-SIOSM-SIOSSTOLI " - "STLERSMANYA PECIALM-PII VERTKAARSEOSOUNCEE-1-2RACHY2 MBEOKEE " - "YURIIYENAPOSTERREPHAEGIONEGL HEGALIZYGOS CAPOOKARAOMMAEOTHALEBALL " - "TABSRCHID2 KPI2 KPAOLD XRASHA TELUEIDONUGUST2 HOO2 HEN2 MBARELAARELA " - "RAIDA ALLO AMPSYECEKREIWAOMBIEZSEKARDION0 HEEOQPENPCHA 0 JOOPPAGEPEAN 0 " - "MANRITSIROGOMPONSEPEITHPOLI PSILI LACAZHAIN0 DOOPASEQYIZET0 DWOPEN O0 " - "GBO0 GEEPATAK0 HAN0-VASPLHAUEAGLEPITEREKEETPI ROPLUTOPEN-P " - "MOODPMUNKRIEEN1 DWEPEPETPLUTAUKARAOPLET0 OIL1 WVIUBUTS SARI1 TWOQUIRY1 " - "TEEZILDE1 PEE DEKA CHWV COATEATH UBURURILLAEISMAORUTO1-VAS1 " - "YOOYSTERQAAFUZIDI ICON ILUT JERA KAWIPTUNE0 BEE1 FAN FUJI GORA HAA " - "PAATOR-RUBUCIBLRONOSEESHIEVAL VATORBALAGBASA BASSAINTHUBEITHBACUSINNA " - "VAAVUBENDEINGSABHADHBHETHSUTUHITUALITHI AUTHSISTLEAVROSEURAEAWAY " - "IRACYBAARUIPINGIPEHAIHVUSUNOO UTEUXBOOTSBORZYEYBUSEYYALTURN BREW " - "DESTYBSTERICRONUTIESBISAHTUUMUIMMERIMMA IMGBAT-REXBLAKOUNITYILVERILLU " - "DHAM IKURUIKARALABATLATIKESO ELAMDALAGUSAPPLELABORLAULAVIET DKAR L-JUZL " - "NETSPINEKWAENKUSMAKURONARERUKTOP ALOG " - "ALPHAAMEKHANGELLEERILEASEANNONESHE3STORMASEIAK-550K-" - "020ASPERJUEUIJUDULJUDGEASAR ATAF JERVIJANG SUKUNEUAEMSURYAATIYASTARTET " - "TUKO LAKNOBSUNGBAKHAPHKESH2KERETF " - "COWKARORSTNUTGVANGTINNECLUBSTIPPIGORGITMAAUGOGI TON " - "ADENCECHUTEHALQADELTAUQUETHALA " - "GHULUCKAGETILESHADDAHAALUCKTIETSERETSEEBCLIFFCLONEGALGAGADOLDBOATDATUSFLAG" - "SFSAAQFLICTDAIC FORCEFLUTEGHNUTGESH2TSADITORCHCROWNTORSOGEAN " - "TIGMACTRICCUBEDTOYORTRACKTRAIFGAMANGAMALCAUSECALYACANUSHOUR " - "TTOCKHOTELFAIHUCAUDAHOLARHOLAMCCEPTCCOLICECAKCECEKHIUTHTENSEICHONF " - "EWEIAUDAIARDSTE USI-RESF SOWTEGEHI KOIHUTA TUEUMCAANGHUMP " - "URTLECAKESCAKRAFAAFUTTORUHROOMCHIMECHERYCHESTHAYINHATHICHOOICHOOLHANNACHUL" - "AHISTIHIRIQTHINGHIMELCEREKURITYOJKI URINEFEARNHI RODEPTHHETHECHADA7 " - "NINNABLANA POWLINE7 FUA7 GBE7 HUN7 JEE7 MIN7 NENNADA SEGOL7 " - "TWE7-VASENDEPUMMER8 FEE8 GBU8 KPE6 GBA6 KOODWICHNCORA6 " - "RA2MUHORENANONASHI6 SIA6 SOO6 TA2SAUIL6 WEE6-VASWINJA9 WVA9 WVEMMOTH9 " - "YEEMISRA9-VASMINGOMINDUWISAD9 PU2DSMANA UNAA YUEWINDUMI ROWIDE " - "METRYMETEGMUCH SENTO8 KPO8 MAN8 NANMSHAEMROCK8 NWAMPIRE8 " - "RO28-VASENENG5-VAS9 DEE9 KUA9 MEN9 MUN9 NDAENJET9 NDE9 NON9 " - "NUNEMAKERUDAARUHUAO RUAO PLARULAIO KAI3 HINO BOX3 HONO ANGNZEUM3 FOORUSH " - "3 NDIEMBICRYASO3 RA3NUENGXYOOJNTXIVXW XW3 VEE2 MBU2 NJA2 NJUROWN 2 POO2 " - "PTE2 SEEYAMOK3 WEI2-VASRRITOUBITOY-ONEOCADOOBYLA3 BOO4 WUI4-VASX-RAYNIS " - "FNINTHWUAETWU318NGUE NGMAN4 WOO5 KEENGENT5 MBISADHE5 " - "NDUSAKINSAKTASALADNENOENEMKA4 ABBNTHA E GEENSYON3-VASNSUAENSIEE32 JEXING " - "MPARE4 GBI4 KPU4 LEE4 LOO4 MBO4 MONEMLJA4 NDO4 TOO4 VOONNAN " - "WBOATMAALAMAAEHSHOOKM RAMADULTU U UMACUSLWAY " - "SHTINAEMAELURALSICLEWATTOAEPENACHKASHIMAMAQAFU-I-IMALONAEREEMAIZEMAI " - "KMADYAVZMETERINEERKHAVRIDOSKATEALLEYALLI AGMA LOUREWAQFALOOP " - "LOMKASILA3WAAVULOBE LOAN " - "SHARUMEEMUMEPETSHANGAAMAEWFISHMELONMENOEWIANGENUTOAADHUSHARAEOPLEMEIZISHAR" - "2REGIWAAKRUTURUSIYEUXVEUXXEIAUNAVXEYNWAHAZATAZIZ2VIDASIKIWAETSOLVSOKAREIAU" - "GU UTTYRROIVOS VUEQRPSETZELTRIOZETAYAWNROUTSLURZZY " - "RUNASINKUNAHRUKURUISRIFYRTARVIYOSEENTAXITFONZAYNSUABWDERUON " - "YUDHYUKUZELOUSA TUKIULU " - "YWAASELFZIETVEDERGU2SEEVWULUS-TEU-TOU-YESEYEVESTSA-IVEUMVEYZWAW " - "TWAASHTAROA UTANROARSHYAUMEAKPENKOKOKOBAKMA " - "KINIKICKKWAABAGSBALDKCETKAPHKANGKAKOAROOLAANATIMATYABUNGBUOYC-18C-39ISI " - "CASECAYNIQAAIPODBASHKAD3BAYIKAAFBBITBERDJOT " - "BETHJIIMBOOKBOREJADEMFAAMESOALAIMEARALDAMARYMARUMVATMUINMUASMPETAHADAILMMM" - "U2MLYAMIINMIIMLIWNLIUMAPAQLIFUAPONARA3LFIELFERARGIALTALUMNAMLALUISLOVOLOLL" - "EAAEH-YRH-4EH-2FEEEEGULUGUINGRU GROMGOALEESUE-D E-A HEEPHEENE-B E-C " - "HAYNHAVEGIR2E-E E-F " + "SERIFLEFT-HAND ABATA TREELENDED YUSLET SYMBOLALLY MARK SIXTEENTHSLGIZ " + "EOLHXLHAG RTAGSLIGHT BEATLIGHT BULBALENT SIGNLIMITATIONLINDRICITYALEF " + "WITH WO SHORTS WITH SPOONWITH STRAWN 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SIGNVIGINTILEMALL RINGCHOSEONG OKED HEADUR-DE-LISRCHAIC " + "RAELLOWSHIPLIGHTNINGHARACTERSHARD SIGNL-KHIEUKHRPORATIONSIVE FACESMALL " + "YUSVRAKHIYA RWARI DDAFEH WITH URUZ UR UEMBEDDING3 PLUS " + "ANNUSVARAYACHAVIYANINTRACTIONNTESSENCENTERPRISEIGN TOMPINSERT AT IGN " + "SAFHASOF PASUQACE NOTE RTER MARKO-EM DASHRTS " + "MEDALHEADSCARFOKOUFISMALACKFOOT TABE SIGNALI GALI Y BLOSSOMNVERTED " + "RHAIKSUKI LITTLE UP1 CHARIOTONGSEONG LISSANDO ROJECTIONONG GRAVEHWAZ EH E " + "AND CURLONE THIRDALAYALAM VEUAENGAMARISTERA OP HALF OICE " + "CREAMH-THIEUTHTUTEYASATKING BOOTM HE-GOATARM CLOCKAJANYALANRNEY PARARO " + "WIDTH E SCOTS SADEG ADEGOO DENNENCK SEXTANL ME HANDYEH WITH VICE MARKYEH " + "ABOVEOM SYMBOLILE TILDEYEAR SIGNMAEMGBIEET-THIEUTHARCHAIC M2 " + "GARMENTKSTREPTONBEER MUGSON-JOINERRCHAIC IILINE FACEON TEUAEQELEGRAPH ON " + "GROUNDOKED TAILHALF NOTEHALF SIGNKU RU KHASPIRITUS HALSHELETKYO " + "TOWERILIPPINE N MODIFIEES AKURU N-PANSIOSVOCALIC RN-CREE THIDEOGRAM RED " + "JOKERLEFT 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"ROWIANGMETRYMETEGMADYATUEUMMAIZEMAI KHUTA HUMP MACUSWBOATMAALAMAAEHM " + "RAMADULTHROOMEOPLECAKRAFAAFUCAKESURTLESHIMAMAQAFU-I-" + "IMALONCAANGACHKAJUEUIJUDULJUDGEATAF JERVIBHETHASPERBHADHJANG " + "SUKUNEUAEMSURYAATIYABISAHUTIESSTNUTASAR " + "SUTUHSTORMASEIAK-550K-020BEITHIRACYBAARUINNA IPINGIPEHABACUSEVAL " + "VATORBALAGBASA BASSAINTHUAWAY ITUALITHI " + "AUTHSISTLEAVROSEURAEKARORINGSABENDEVAAVUIHVUSBOOTSUTEUXLAMDAUNOO ESO " + "ELAGUSAPPLEIKARALABORLABATVIET ANNONEYBUSANGELLEERILEASEDKAR " + "ESHE3LAULALATIKBORZYKHAPHBLAKOKO LAKNOBST-REXIMGBAUNGBAIMMA " + "UNITYIMMERTUUMUKESH2KERETSTARTKURONIKURUL-JUZL " + "NETKWAENSPINEARERUKUSMADHAM KTOP ET TUILLU ILVER4 LEENSIEE32 JEXING " + "CHADA4 ABB4 GBI4 KPU4 LOO4 MBO4 MON4 NDOEMLJAHETHE4 TOO4 VOONNAN RYASO3 " + "NDIEMBIC3 RA3XYOOJNUENG4 WOONTXIVXW XW3 VEE3 WEIE GEENTHA " + "3-VASNSYONNSUAESAKINCEREK5 KEENGENT5 MBIHIMEL5 " + "NDUSADHENGMANSAKTASALADNENOENEMKA5-VASHIRIQ4 WUIDEPTH4-VASHI " + "ROX-RAYFEARNMINDUNINTHURINERUSH WUAETWU318NGUE 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"IYWAASINKRUTUVIDASONGSOLVSOKAZAYNVEUXUHURURUSVEUMRUNASEEVRUNGVEYZXEIAZELOU" + "TANXEYNRGU2ZIETWAW UTAEVIYOYUDHYUKUWDERTUKIKPENKOKEKOETKOBAKMA " + "KICKBAGSKEUPBALDKCETKAPHKANGKAKOAROOARUMATYABUNGBUOYC-18C-39ISI " + "CANOCASECAYNIQAAIPODBASHKAD3BAYIKAAFBBITBERDJOT " + "BETHJIIMBOOKBOREJADEMFAAMESOALAIALDAMARYMARUMVATMUINMUASMPETAHADAILMMMU2ML" + "YAMIINMIIMLIWNLIUMAPAQLIFUAPONARA3LFIELFERARGIAMLALUISAN " + "XANAELOVOLOLLEAAEH-YRH-4EH-2FEEEEGULUGUINGRU GROMGOALEESUE-D HEROE-A " + "HEEPHEENE-B E-C HAYNHAVEGIR2E-E E-F " "E-" "KOFEUQFITAFIRIFFINFETHFEEMFASTFAIBEURIEZZOEHEHGIEAGIDAGIBAGHWAGHOMEIPTEIRT" - "GGWSEIWSGEDEHERUGAMLG-YRFWAAIKIRIK HIITOCWAAIGERIFATDAGSDAIRINY " - "CHAUCHEHDDAKCKENCOONILUYCORECRETHOPHHOM HMI DZHAHILDHIINHID " - "HHWAHEYTHEYSHEYNDIM2DDHIDEADIARAIANOI-TEI-EUDGERHWAAHUVAHUB2HSHUHSDA WEB6 " - "LA0 BI6 NA-UM 6 PO6 QA6 RU6 SE3 MUOOTH3 MI6 WU3 MEQASR3 LE7 BE3 KU3 JO0 " - "JUOONU3 RIO-YOO-YA0 KO6 DIO-RA6 FU3 JE6 HE0 HOO-KI6 HIO-EO1 KI6 JE3 PA6 " - "JO7 REPARD R S POD7 KI7 LUNWAA3 A3NUUNNUTS7 TI7 VO8 BONTOCQOPA7 DAOPODQEF " + "GGWSEIWSEKAAHERUGAMLGAMEG-YRFWAAIK HIITOCWAAIGERDAGSDAIRINY " + "CHAUCHEHINORDDAKCKENCOONILUYCORECRETHOSTHOPHHOM HOKEHMI DZHAHILDHIINHID " + "HHWAHEYTHEYSHEYNDIM2DDHIDEADIARAIANOI-TEI-EUDGERHUVAHUB2HSHUHSDA WEB6 LA0 " + "BI6 NA-UM 6 PO6 QA6 RU3 MU6 SE3 MI6 WU3 MEQASR3 LE7 BE3 KU3 JO0 JUOONU3 " + "RIO-YOO-YA0 KO6 DIO-RA6 FU3 JE6 HE0 HOO-KI6 HIO-EO1 KI6 JE3 PA6 " + "JONUTSPARD R S POD7 KI7 LUNWAA3 A3NUUN7 RE7 TI7 VO8 BONTOCQOPA7 DAOPODQEF " "QHAUOPUS1 KU7 DD0 NIPAWN3 EE7 EI7 JAPHAB028BPLUGPLUM0 ZO4 ZE5 A2POLO4 DO1 " "DO0 YE5 AN5 AU1 DU4 KE4 FI1 DA4 NE4 TEPEUX4 TUONA 4 WA4 WIPHIN0 SA1 HA5 " - "MO5 NU5 OO5 TEOENG5 TOPEEPOONGPRILPEEIODLE1 IN0 RA0 PU5 VA5 VE5 " - "WAOBROOBAT5 WEOJOD0 WIOJI 5 BB5 DE1 GAAFEL5 FA5 FE7 ZA5 GI5 IN5 JUOFUM3 " - "YU3 TA5 LINEO AAMU2 VINDUENDAP2 BU2 YAA-EUA-HANGA2A-KEA-WOA-YORAFEOUBTNET " - "AACU2 SO2 NO2 RONAAU2 QO2 PEMWAANCER2 KA C D8 DUNANANAM2OXIANAG 9 PA8 KO8 " - "PI8 QENNNA8 SU8 WE9 JA9 PINJAM9 SE9 SI9 SO9 TANRUANTAA8 EN8 FONSUB8 " - "GUORIINSHE OHM1 YINPEANOWC8 JI1 PONHAY1 SA1 RAA IE1 VU1 SI1 QI1 SU9 TU1 " - "X14D15518D121E-81-03-0DZEE-9YITUMXU-5U-AU-8U-7U-6U-OU-4U-3U-2U-1U-" - "UZUPZZEZJEZOOZOR0 UUEZUEHE-VE-J0B904A0-0E800 EUDY8 I8 A72CA-3A-2A-17 " - "O9E39819 L8F06D7AWXAYD6206-0AZUB57B89A-4AUJAL2WAUAEFWI " - "VOKA-9A-8A-7A-6A-5VUUVOYA7AA-OCWICYAD-C2533 " - "DD-ND42D70Y00XWG31C305CIGUQADA2XWV3 IY-1Y-2DIBDJA20B2-0DE65 " - "UBIBBUDVAU5B65575-0BAUXAUXEH4 " - "EX-3BXGX-2CA9CAHCAIX004-0L-3L-4L-5L-6L-7L-8L-9L-2KUEKUGL-0L-1SIISJEJ-" - "2JAHJAWJEUJHAP-3P-4P-2P-1SUUIWRKAQK-2K-3K-4K-7K00S-WNIBNIIOAYS-8S-7S-6S-" - "5S-4S-3O-7O-6O-5O-4O-3O-2O-1O " - "YS-2S-1O-UO-OO-IO-AO-8M-2M-BM-CN-2N-3OMSQOFQIGGVEQIFH-1TJEH-3QARH-5H-6H-" - "7H-8H-9QUFQOTQ00PUQHOJH-FHAQFLYF14EYKEZHF-1F-2TUJF8CFAJR-7R-6R-5R-4R-3R-" - "2FUEG-1G-2G-3G-4G-5G-CP-5R-9R-8T-5T-4T-3T-2T-1T-0T-6P-9P-8P-7P-6IMNT-7I-" - "YI-UI-APOQI-OI-8I-7I-6I-5I-4I-1I-2I-" - "364P01A1D1648224BQW09402938C0U0G0G9F37183S099959291VDLX"; -uint8_t UnicodeNameToCodepointIndex_[242216] = { + "MO5 NU5 OO5 TEOENG5 TOPEEPOONGPRILODLE1 IN0 RA0 PU5 VA5 VE5 WAOBROOBAT5 " + "WEOJOD0 WIOJI 5 BB5 DE1 GAAFEL5 FA5 FE7 ZA5 GI5 IN5 JUOFUM3 YU3 TA5 LINEO " + "NEMA2 VINDUENDAP2 BUACAS2 YANGA2A-EUA-HAA-KEA-WOA-YORAFEOUBTAACU2 SO2 NO2 " + "RONAAU2 QO2 PEMWAA2 KA C D8 DUNANANAM2OXIANAG 9 SE9 PANPEA9 PINJAM8 " + "JINRUA9 SI9 SO9 TA OHM9 TU8 PI1 PO8 KO9 TO8 QENNNA8 SU8 WE9 JANHAY8 GU1 " + "SI8 FO1 SU1 VU8 ENNTAANSUB1 YIORII1 QIA IE1 RA1 SAE-83-01-012114D1551 " + "X18DUMXDZEE-9U-5U-AU-8U-7U-6U-OU-4U-3U-2U-1U-UZUPZZEZJEZOOZOR0 " + "UYOTUEZUEHE-VE-J0B904A0-0E80UKY0 EUDY8 I8 A72CA-3A-2A-19E37 O9819 " + "L8F06D7AWXAYD6206-0AZUB57B89A-4AUJAL2WAUWI " + "VOKA-9A-8A-7A-6A-5VUUVOYA7AA-OCWID-C2533 DD-ND42D70Y00XWG31C305CIGDA2XWV3 " + "IY-1Y-2DIBDJA2-0DE6WOQ5 UBIBBUDVAU5B65575-0XAUXEH4 " + "EX-3BXGX-2CA9CAHX004-0L-3L-4L-5L-6L-7L-8L-9L-2KUEKUGRMTL-0L-1LK " + "LJELKASIILFAJ-2JAWJEUJHAP-3P-4P-2P-1SUUIWRKAQKAUK-2K-3K-4K-7K00NIIS-WOAYS-" + "8S-7S-6S-5S-4RQAS-3O-2O-7O-6O-5O-4O-3O-1O " + "YS-2S-1O-UO-OO-IO-AO-8M-2M-BM-CN-2N-3OIXOGHOMSMU " + "QIGQIFH-1TJEH-3QARH-5H-6H-7H-8H-9QUFQOTQ00HHAPUQH-FHAQFLYFOMF14EYKEZHF-1F-" + "2TUJF8CR-7R-6R-5R-4R-3R-2FUEG-1G-2G-3G-4G-5G-CP-5R-9R-8T-5T-4T-3T-2T-1T-" + "0T-6P-9P-8P-7P-6IMNT-7I-YI-UI-APOQI-OI-8I-7I-6I-5I-4I-1I-2I-" + "3HSA64P01A1D161748494B22QW09403836R7C0U0G0G9F37199959291VD"; +uint8_t UnicodeNameToCodepointIndex_[242258] = { 0x00, 0x05, 0xc0, 0x00, 0x89, 0x15, 0xc0, 0x00, 0xb3, 0x12, 0xc0, 0x00, 0xfb, 0x06, 0xc0, 0x01, 0x21, 0x14, 0xc0, 0x01, 0x45, 0x18, 0xc0, 0x01, 0x5f, 0x16, 0xc0, 0x01, 0x75, 0x03, 0xc0, 0x01, 0x95, 0x04, 0xc0, 0x01, @@ -987,1052 +987,1052 @@ uint8_t UnicodeNameToCodepointIndex_[242216] = { 0x5f, 0x0b, 0xc0, 0x02, 0x7d, 0x19, 0xc0, 0x02, 0x9d, 0x08, 0xc0, 0x02, 0xb5, 0x0d, 0xc0, 0x02, 0xd1, 0x0f, 0xc0, 0x02, 0xef, 0x10, 0xc0, 0x03, 0x0f, 0x1a, 0xc0, 0x03, 0x35, 0x07, 0xc0, 0x03, 0x47, 0x09, 0xc0, 0x03, - 0x98, 0x11, 0xc0, 0x03, 0xba, 0xc5, 0xdc, 0xa7, 0x0f, 0xcc, 0xb1, 0x1c, - 0xc0, 0x04, 0x1e, 0x0c, 0xc0, 0x04, 0x40, 0x42, 0x00, 0x93, 0xc0, 0x04, - 0x56, 0x1b, 0xc0, 0x04, 0x6c, 0x46, 0x69, 0xab, 0xc0, 0x04, 0x80, 0xcd, - 0x7f, 0xc6, 0x0f, 0xa7, 0x39, 0xc7, 0xcc, 0x99, 0x0f, 0xa2, 0xa9, 0xc5, - 0xe2, 0x29, 0x0f, 0xd3, 0xd8, 0x03, 0xc0, 0x04, 0xaf, 0x43, 0x3f, 0x83, + 0x98, 0x11, 0xc0, 0x03, 0xba, 0xc5, 0xdf, 0x8b, 0x0f, 0xcc, 0xb1, 0x1c, + 0xc0, 0x04, 0x1e, 0x0c, 0xc0, 0x04, 0x40, 0x42, 0x00, 0x2a, 0xc0, 0x04, + 0x56, 0x1b, 0xc0, 0x04, 0x6c, 0x46, 0x69, 0xa2, 0xc0, 0x04, 0x80, 0xcd, + 0x76, 0xdb, 0x0f, 0xa7, 0x39, 0xc7, 0xcd, 0x4d, 0x0f, 0xa2, 0xa9, 0xc5, + 0xe1, 0x02, 0x0f, 0xd3, 0xd8, 0x03, 0xc0, 0x04, 0xaf, 0x43, 0x3e, 0x80, 0xc0, 0x04, 0xde, 0x0a, 0xc0, 0x04, 0xf0, 0x14, 0xc0, 0x05, 0x0c, 0x11, 0xc0, 0x05, 0x2b, 0x0e, 0xc0, 0x05, 0x66, 0x0b, 0xc0, 0x05, 0x78, 0x17, 0xc0, 0x05, 0x8d, 0x07, 0xc0, 0x05, 0xb3, 0x1b, 0x40, 0x05, 0xcb, 0x07, 0xc0, 0x05, 0xe3, 0x0b, 0xc0, 0x06, 0x32, 0x16, 0xc0, 0x06, 0x56, 0x03, 0xc0, 0x06, 0x73, 0x0d, 0xc0, 0x06, 0xaf, 0x0e, 0xc0, 0x06, 0xbd, 0x0a, 0xc0, 0x06, 0xcd, 0x05, 0xc0, 0x06, 0xe9, 0x10, 0xc0, 0x06, 0xfe, 0x11, - 0xc0, 0x07, 0x0e, 0x42, 0x00, 0x93, 0xc0, 0x07, 0x40, 0x1b, 0xc0, 0x07, + 0xc0, 0x07, 0x0e, 0x42, 0x00, 0x2a, 0xc0, 0x07, 0x40, 0x1b, 0xc0, 0x07, 0x4a, 0x12, 0xc0, 0x07, 0x5e, 0x17, 0xc0, 0x07, 0x7d, 0x0f, 0xc0, 0x07, - 0xa9, 0x19, 0xc0, 0x07, 0xb7, 0xcc, 0x89, 0xdc, 0x01, 0x4e, 0x60, 0x14, + 0xa9, 0x19, 0xc0, 0x07, 0xb7, 0xcc, 0x89, 0xc7, 0x01, 0x4e, 0x60, 0x14, 0xc0, 0x07, 0xc7, 0x0e, 0xc0, 0x07, 0xd9, 0x0b, 0xc0, 0x07, 0xe1, 0x03, 0xc0, 0x08, 0x0a, 0x11, 0xc0, 0x08, 0x3e, 0x07, 0xc0, 0x08, 0x6c, 0x17, - 0xc0, 0x08, 0x8e, 0x4f, 0x65, 0x46, 0xc0, 0x08, 0xaa, 0x0a, 0x40, 0x08, + 0xc0, 0x08, 0x8e, 0x4f, 0x6a, 0x38, 0xc0, 0x08, 0xaa, 0x0a, 0x40, 0x08, 0xc8, 0x07, 0xc0, 0x08, 0xd6, 0x0b, 0xc0, 0x09, 0x0a, 0x14, 0xc0, 0x09, 0x48, 0x11, 0xc0, 0x09, 0x62, 0x17, 0xc0, 0x09, 0xaa, 0x03, 0xc0, 0x09, - 0xbc, 0xc2, 0xed, 0xdf, 0x0f, 0xa6, 0x01, 0xcf, 0x67, 0x08, 0x0f, 0xcf, + 0xbc, 0xc2, 0xed, 0xb2, 0x0f, 0xa6, 0x01, 0xcf, 0x6a, 0xec, 0x0f, 0xcf, 0x60, 0x07, 0xc0, 0x09, 0xe1, 0x0b, 0xc0, 0x0a, 0x1d, 0x11, 0xc0, 0x0a, - 0x4d, 0x03, 0xc0, 0x0a, 0x8f, 0x17, 0xc0, 0x0a, 0xb7, 0xc9, 0xab, 0x5c, + 0x4d, 0x03, 0xc0, 0x0a, 0x8f, 0x17, 0xc0, 0x0a, 0xb7, 0xc9, 0xb1, 0x4a, 0x0f, 0xcc, 0x78, 0x03, 0xc0, 0x0a, 0xdf, 0x07, 0xc0, 0x0a, 0xf1, 0x0b, - 0xc0, 0x0b, 0x07, 0x11, 0xc0, 0x0b, 0x2f, 0x42, 0x00, 0xaf, 0x40, 0x0b, + 0xc0, 0x0b, 0x07, 0x11, 0xc0, 0x0b, 0x2f, 0x42, 0x03, 0x6e, 0x40, 0x0b, 0x39, 0x03, 0xc0, 0x0b, 0x45, 0x17, 0xc0, 0x0b, 0x7f, 0x0a, 0xc0, 0x0b, 0x95, 0x11, 0xc0, 0x0b, 0xb1, 0x14, 0xc0, 0x0b, 0xdd, 0x07, 0xc0, 0x0b, 0xed, 0x0b, 0xc0, 0x0c, 0x0b, 0x19, 0x40, 0x0c, 0x43, 0x14, 0xc0, 0x0c, - 0x5b, 0xc2, 0x01, 0x66, 0x0f, 0xd4, 0x99, 0x06, 0xc0, 0x0c, 0x7d, 0x0e, - 0xc0, 0x0c, 0x9f, 0x17, 0xc0, 0x0c, 0xc7, 0xc7, 0x2f, 0x38, 0x01, 0x38, + 0x5b, 0xc2, 0x28, 0xac, 0x0f, 0xd4, 0x99, 0x06, 0xc0, 0x0c, 0x7d, 0x0e, + 0xc0, 0x0c, 0x9f, 0x17, 0xc0, 0x0c, 0xc7, 0xc7, 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0x9a, + 0xd3, 0x44, 0x47, 0x01, 0x96, 0x78, 0xc4, 0x1f, 0x76, 0x0f, 0xa4, 0x20, + 0xcf, 0x61, 0x7d, 0x08, 0x49, 0xf9, 0x47, 0x00, 0x3f, 0x40, 0x76, 0xbc, 0x83, 0x08, 0x14, 0x03, 0x00, 0x77, 0x1e, 0x87, 0x08, 0x14, 0x0b, 0x00, 0x77, 0x22, 0x84, 0x08, 0x14, 0x13, 0x00, 0x77, 0x26, 0x89, 0x08, 0x14, 0x21, 0x86, 0x08, 0x14, 0x29, 0x8b, 0x08, 0x14, 0x31, 0x99, 0x08, 0x14, @@ -2041,459 +2041,459 @@ uint8_t UnicodeNameToCodepointIndex_[242216] = { 0x08, 0x14, 0x61, 0x8e, 0x08, 0x14, 0x69, 0x8f, 0x08, 0x14, 0x73, 0x00, 0x77, 0x36, 0x90, 0x08, 0x14, 0x7b, 0x00, 0x77, 0x3a, 0x97, 0x08, 0x14, 0x91, 0x92, 0x08, 0x14, 0x99, 0x94, 0x08, 0x14, 0xa9, 0x95, 0x08, 0x14, - 0xb1, 0x8a, 0x08, 0x14, 0xd9, 0x9a, 0x08, 0x14, 0xe0, 0x42, 0x02, 0xfb, - 0xc0, 0x77, 0x3e, 0xc6, 0x92, 0xca, 0x01, 0x05, 0xf0, 0x15, 0xc0, 0x77, - 0x4b, 0x47, 0x01, 0xff, 0xc0, 0x77, 0x57, 0x05, 0xc0, 0x77, 0xa7, 0x52, - 0x48, 0x06, 0x40, 0x77, 0xb3, 0x00, 0x40, 0x77, 0xc9, 0xc2, 0x00, 0x35, - 0x0f, 0x9f, 0xb9, 0xc5, 0xdb, 0x49, 0x0f, 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0xd9, 0x4e, + 0x6e, 0x86, 0x40, 0xcc, 0x44, 0x43, 0xeb, 0xfe, 0xc0, 0xcc, 0x50, 0xc6, + 0xd5, 0xe5, 0x0f, 0x81, 0x80, 0xc6, 0xd5, 0xe5, 0x0f, 0x83, 0x11, 0x43, + 0xeb, 0xfe, 0x40, 0xcc, 0x7a, 0x07, 0xc0, 0xcc, 0xa4, 0x49, 0x6d, 0xff, + 0xc0, 0xcc, 0xae, 0xd0, 0x60, 0xa4, 0x01, 0x4e, 0xf9, 0x47, 0x03, 0x8b, + 0x40, 0xcc, 0xc6, 0x05, 0xc0, 0xcc, 0xd2, 0xc5, 0x85, 0x66, 0x01, 0x4c, + 0xc9, 0x15, 0xc0, 0xcc, 0xde, 0xc9, 0xae, 0x05, 0x0f, 0xd7, 0x29, 0xd4, + 0x3b, 0xff, 0x01, 0x70, 0x41, 0xc6, 0xd1, 0xe3, 0x01, 0x70, 0x99, 0xd4, + 0x3b, 0x73, 0x01, 0x70, 0xb0, 0xc8, 0x15, 0x41, 0x01, 0x16, 0x29, 0xc5, + 0x1c, 0x05, 0x01, 0x11, 0xc1, 0xc4, 0x23, 0xce, 0x01, 0x10, 0xa1, 0xc5, + 0x03, 0x98, 0x00, 0x16, 0xc8, 0xd1, 0x57, 0xbc, 0x08, 0xc1, 0xd9, 0x45, + 0x00, 0x75, 0xc0, 0xcc, 0xea, 0x4b, 0x6b, 0xd2, 0xc0, 0xcc, 0xfc, 0x47, + 0x00, 0x3f, 0x40, 0xcd, 0x1f, 0xcf, 0x4c, 0x89, 0x01, 0x17, 0x5b, 0x00, + 0xcd, 0x86, 0xc6, 0x01, 0x4e, 0x01, 0x10, 0x60, 0xc9, 0x24, 0x80, 0x01, + 0x17, 0x08, 0xc5, 0x30, 0x8b, 0x01, 0x14, 0x03, 0x00, 0xcd, 0x8c, 0xc3, + 0x00, 0xf3, 0x01, 0x15, 0x60, 0xdd, 0x10, 0xdc, 0x01, 0x57, 0x70, 0xc7, + 0x89, 0x18, 0x0f, 0xad, 0xd9, 0xc4, 0x2a, 0x5e, 0x0f, 0xad, 0xca, 0x00, + 0xcd, 0x92, 0x0e, 0xc0, 0xcd, 0x98, 0x45, 0x0b, 0xcb, 0xc0, 0xcd, 0xa4, + 0x49, 0xb3, 0x0c, 0xc0, 0xcd, 0xd5, 0x44, 0xa5, 0x94, 0xc0, 0xcd, 0xf3, + 0xd7, 0x28, 0x7f, 0x0d, 0xe3, 0x90, 0x99, 0x0d, 0xe1, 0xc3, 0x00, 0xcd, 0xff, 0x96, 0x0d, 0xe0, 0x1b, 0x00, 0xce, 0x1e, 0x95, 0x0d, 0xe0, 0xe3, 0x00, 0xce, 0x26, 0x8c, 0x0d, 0xe0, 0xdb, 0x00, 0xce, 0x36, 0x90, 0x0d, 0xe0, 0xd3, 0x00, 0xce, 0x3a, 0x8f, 0x0d, 0xe0, 0xcb, 0x00, 0xce, 0x44, @@ -2919,14 +2919,14 @@ uint8_t UnicodeNameToCodepointIndex_[242216] = { 0x00, 0xce, 0x90, 0x84, 0x0d, 0xe0, 0x39, 0x9a, 0x0d, 0xe0, 0x0b, 0x00, 0xce, 0x96, 0x91, 0x0d, 0xe2, 0x23, 0x00, 0xce, 0x9a, 0x97, 0x0d, 0xe2, 0x8b, 0x00, 0xce, 0xac, 0x87, 0x0d, 0xe2, 0x3b, 0x00, 0xce, 0xba, 0xc2, - 0x04, 0x30, 0x0d, 0xe2, 0x81, 0x8b, 0x0d, 0xe2, 0x33, 0x00, 0xce, 0xc2, - 0x83, 0x0d, 0xe2, 0x0a, 0x00, 0xce, 0xc6, 0xe0, 0x04, 0xe7, 0x01, 0x3c, - 0xf9, 0xc8, 0x7c, 0x98, 0x07, 0xf2, 0x49, 0xc8, 0x7c, 0x8b, 0x07, 0xf2, - 0x68, 0xc6, 0x01, 0xb1, 0x0f, 0xa5, 0x41, 0xd0, 0x5e, 0x2f, 0x01, 0x72, - 0x18, 0xc5, 0xa4, 0x6b, 0x0f, 0xaf, 0x09, 0x45, 0x01, 0xac, 0x40, 0xce, - 0xcc, 0x00, 0xc0, 0xce, 0xd8, 0x42, 0x00, 0x3c, 0x40, 0xce, 0xf9, 0x4f, - 0x6b, 0x9a, 0xc0, 0xcf, 0x42, 0xc3, 0x47, 0xd8, 0x0f, 0xb5, 0xd8, 0xcf, - 0x21, 0x7d, 0x01, 0x33, 0xe1, 0x4f, 0x69, 0xba, 0x40, 0xcf, 0x4e, 0x9c, + 0x02, 0x30, 0x0d, 0xe2, 0x81, 0x8b, 0x0d, 0xe2, 0x33, 0x00, 0xce, 0xc2, + 0x83, 0x0d, 0xe2, 0x0a, 0x00, 0xce, 0xc6, 0xe0, 0x06, 0x47, 0x01, 0x3c, + 0xf9, 0xc8, 0x7c, 0x4f, 0x07, 0xf2, 0x49, 0xc8, 0x7c, 0x5c, 0x07, 0xf2, + 0x68, 0xc6, 0x0a, 0x31, 0x0f, 0xa5, 0x41, 0xd0, 0x60, 0xd4, 0x01, 0x72, + 0x18, 0xc5, 0xa4, 0x57, 0x0f, 0xaf, 0x09, 0x45, 0x01, 0x36, 0x40, 0xce, + 0xcc, 0x00, 0xc0, 0xce, 0xd8, 0x42, 0x00, 0x2f, 0x40, 0xce, 0xf9, 0x4f, + 0x62, 0x4f, 0xc0, 0xcf, 0x42, 0xc3, 0x4e, 0x41, 0x0f, 0xb5, 0xd8, 0xcf, + 0x24, 0xad, 0x01, 0x33, 0xe1, 0x4f, 0x64, 0xb6, 0x40, 0xcf, 0x4e, 0x9c, 0x0f, 0x8f, 0xf9, 0x9b, 0x0f, 0x8f, 0xf1, 0x9a, 0x0f, 0x8f, 0xe9, 0x99, 0x0f, 0x8f, 0xe1, 0x98, 0x0f, 0x8f, 0xd9, 0x97, 0x0f, 0x8f, 0xd1, 0x96, 0x0f, 0x8f, 0xc9, 0x95, 0x0f, 0x8f, 0xc1, 0x94, 0x0f, 0x8f, 0xb9, 0x93, @@ -2935,58 +2935,58 @@ uint8_t UnicodeNameToCodepointIndex_[242216] = { 0x0f, 0x8f, 0x81, 0x8c, 0x0f, 0x8f, 0x79, 0x8b, 0x0f, 0x8f, 0x71, 0x8a, 0x0f, 0x8f, 0x69, 0x89, 0x0f, 0x8f, 0x61, 0x88, 0x0f, 0x8f, 0x59, 0x87, 0x0f, 0x8f, 0x51, 0x86, 0x0f, 0x8f, 0x49, 0x85, 0x0f, 0x8f, 0x41, 0x84, - 0x0f, 0x8f, 0x39, 0x83, 0x0f, 0x8f, 0x30, 0xc5, 0x21, 0x27, 0x05, 0x4a, - 0x99, 0x4a, 0x6f, 0x72, 0x40, 0xcf, 0x5a, 0x8a, 0x05, 0x4a, 0x91, 0x94, + 0x0f, 0x8f, 0x39, 0x83, 0x0f, 0x8f, 0x30, 0xc5, 0x1e, 0x07, 0x05, 0x4a, + 0x99, 0x4a, 0x6b, 0xd3, 0x40, 0xcf, 0x5a, 0x8a, 0x05, 0x4a, 0x91, 0x94, 0x05, 0x4a, 0x89, 0x90, 0x05, 0x4a, 0x82, 0x00, 0xcf, 0x71, 0x83, 0x05, - 0x4a, 0x31, 0x10, 0xc0, 0xcf, 0x75, 0x0f, 0xc0, 0xcf, 0x87, 0xc2, 0x01, - 0x0e, 0x05, 0x4a, 0x09, 0xc2, 0x00, 0x4c, 0x05, 0x4a, 0x01, 0xc2, 0x1a, - 0x36, 0x05, 0x49, 0xf9, 0xc2, 0x00, 0x96, 0x05, 0x49, 0xf1, 0xc2, 0x00, - 0x9a, 0x05, 0x49, 0xe9, 0xc2, 0x0e, 0xe5, 0x05, 0x49, 0xe1, 0xc2, 0x26, - 0x94, 0x05, 0x49, 0xd1, 0xc2, 0x00, 0x2e, 0x05, 0x49, 0xc9, 0xc2, 0x02, - 0x1d, 0x05, 0x49, 0xb9, 0xc2, 0x07, 0x44, 0x05, 0x49, 0xb1, 0xc2, 0x0c, - 0x25, 0x05, 0x49, 0xa1, 0xc2, 0x00, 0x44, 0x05, 0x49, 0x99, 0xc2, 0x07, - 0x69, 0x05, 0x49, 0x89, 0xc2, 0x06, 0x6b, 0x05, 0x49, 0x80, 0x00, 0xc0, - 0xcf, 0x91, 0x46, 0x00, 0x4c, 0xc0, 0xcf, 0xe6, 0xd5, 0x37, 0x2a, 0x01, - 0x51, 0xe8, 0xd0, 0x5f, 0x4f, 0x0f, 0xa8, 0x71, 0xcd, 0x0f, 0x83, 0x01, - 0x19, 0x51, 0xd4, 0x3a, 0x1e, 0x01, 0x4f, 0xe9, 0xdb, 0x16, 0xc3, 0x00, - 0x05, 0xd8, 0xdc, 0x13, 0x8a, 0x01, 0x3d, 0x49, 0xd7, 0x2a, 0x79, 0x01, - 0x49, 0xc0, 0xc7, 0x05, 0x3a, 0x01, 0x03, 0x39, 0xc8, 0xbb, 0xd3, 0x01, - 0x01, 0x71, 0xc9, 0xac, 0x97, 0x01, 0x01, 0x59, 0xc4, 0x00, 0xfa, 0x01, - 0x00, 0x78, 0xd6, 0x31, 0x23, 0x00, 0x2c, 0x69, 0xc4, 0xbe, 0x2d, 0x0f, - 0xc8, 0xe1, 0xcb, 0x92, 0xc5, 0x00, 0x7e, 0xaa, 0x00, 0xd0, 0x28, 0xc8, - 0x08, 0xff, 0x01, 0x12, 0xb9, 0xcb, 0x97, 0x48, 0x01, 0x12, 0xb1, 0xc8, - 0x15, 0xe3, 0x01, 0x10, 0xc1, 0xc5, 0x03, 0x50, 0x00, 0x16, 0xd1, 0xc4, - 0xe5, 0x73, 0x0f, 0xb6, 0xf9, 0xc5, 0x01, 0x59, 0x01, 0x71, 0x80, 0x45, - 0x0a, 0xe3, 0xc0, 0xd0, 0x2e, 0x43, 0x11, 0x8a, 0xc0, 0xd0, 0x3a, 0x45, - 0x00, 0xcd, 0xc0, 0xd0, 0x46, 0x46, 0x01, 0x17, 0x40, 0xd0, 0x52, 0xce, - 0x6c, 0xce, 0x0f, 0xae, 0xf1, 0x42, 0x00, 0xb2, 0x40, 0xd0, 0x5e, 0xc6, - 0xd3, 0x58, 0x0f, 0xbc, 0x59, 0xc7, 0xcf, 0x78, 0x0f, 0xa6, 0x68, 0xc3, - 0xec, 0x15, 0x0f, 0x93, 0x29, 0x42, 0x01, 0x0d, 0xc0, 0xd0, 0x6a, 0xc2, - 0x08, 0xe9, 0x0f, 0x93, 0x19, 0xc2, 0x12, 0x5d, 0x0f, 0x93, 0x09, 0xc2, - 0x11, 0x47, 0x0f, 0x93, 0x00, 0xc3, 0x05, 0x17, 0x01, 0x0b, 0x03, 0x00, - 0xd0, 0x76, 0x08, 0xc0, 0xd0, 0x7a, 0x15, 0xc0, 0xd0, 0x84, 0xd4, 0x39, - 0xa6, 0x01, 0x0c, 0x19, 0x16, 0xc0, 0xd0, 0x93, 0x07, 0xc0, 0xd0, 0xa6, - 0xc4, 0x24, 0x35, 0x01, 0x0b, 0x40, 0x07, 0xc0, 0xd0, 0xb2, 0xcb, 0x95, - 0xd2, 0x08, 0x0c, 0xa8, 0xd3, 0x43, 0x4e, 0x08, 0x0c, 0xa1, 0xcc, 0x84, - 0x0c, 0x08, 0x0c, 0xb1, 0xcd, 0x7e, 0x33, 0x08, 0x0c, 0xc8, 0xc3, 0x5f, - 0x11, 0x0f, 0xb4, 0x19, 0xc5, 0xde, 0xb9, 0x0f, 0xb7, 0x20, 0xc4, 0x02, - 0x33, 0x01, 0x38, 0x5b, 0x00, 0xd0, 0xc4, 0xc4, 0xbe, 0x2d, 0x01, 0x38, - 0x51, 0x0f, 0xc0, 0xd0, 0xca, 0xcc, 0x8c, 0x04, 0x0f, 0xc8, 0xd1, 0xd4, - 0x24, 0xa8, 0x01, 0x70, 0x31, 0xc3, 0x05, 0xe3, 0x01, 0x71, 0x9b, 0x00, - 0xd0, 0xdc, 0xc6, 0x01, 0xe9, 0x01, 0x70, 0x59, 0xc5, 0x00, 0xea, 0x01, - 0x71, 0xa0, 0xc3, 0x7f, 0x6b, 0x0f, 0x98, 0x40, 0xcb, 0x98, 0x50, 0x01, - 0x31, 0x11, 0xc7, 0xc3, 0xd9, 0x0f, 0xa8, 0xc0, 0xc3, 0x5f, 0x11, 0x0f, - 0x9e, 0x71, 0xca, 0xa9, 0x16, 0x0f, 0x9e, 0x68, 0xca, 0xa9, 0xfc, 0x08, - 0x73, 0xf1, 0x44, 0x05, 0x17, 0x40, 0xd0, 0xe2, 0x44, 0x24, 0x35, 0xc0, - 0xd0, 0xf4, 0x45, 0x05, 0x1b, 0xc0, 0xd1, 0x00, 0x15, 0xc0, 0xd1, 0x0a, - 0x08, 0xc0, 0xd1, 0x16, 0x16, 0xc0, 0xd1, 0x1e, 0xcb, 0x0d, 0x7b, 0x08, - 0x73, 0x90, 0xc4, 0x24, 0x35, 0x08, 0x73, 0x41, 0xc5, 0x05, 0x1b, 0x08, + 0x4a, 0x31, 0x10, 0xc0, 0xcf, 0x75, 0x0f, 0xc0, 0xcf, 0x87, 0xc2, 0x00, + 0x4e, 0x05, 0x4a, 0x09, 0xc2, 0x01, 0x6c, 0x05, 0x4a, 0x01, 0xc2, 0x1b, + 0x06, 0x05, 0x49, 0xf9, 0xc2, 0x00, 0x31, 0x05, 0x49, 0xf1, 0xc2, 0x00, + 0x6a, 0x05, 0x49, 0xe9, 0xc2, 0x0a, 0xa6, 0x05, 0x49, 0xe1, 0xc2, 0x22, + 0x8c, 0x05, 0x49, 0xd1, 0xc2, 0x00, 0x37, 0x05, 0x49, 0xc9, 0xc2, 0x02, + 0xe8, 0x05, 0x49, 0xb9, 0xc2, 0x05, 0x10, 0x05, 0x49, 0xb1, 0xc2, 0x0c, + 0x44, 0x05, 0x49, 0xa1, 0xc2, 0x00, 0x3b, 0x05, 0x49, 0x99, 0xc2, 0x05, + 0xf0, 0x05, 0x49, 0x89, 0xc2, 0x02, 0x8b, 0x05, 0x49, 0x80, 0x00, 0xc0, + 0xcf, 0x91, 0x46, 0x01, 0x6c, 0xc0, 0xcf, 0xe6, 0xd5, 0x35, 0x08, 0x01, + 0x51, 0xe8, 0xd0, 0x5c, 0xc4, 0x0f, 0xa8, 0x71, 0xcd, 0x0e, 0xb1, 0x01, + 0x19, 0x51, 0xd4, 0x38, 0x8f, 0x01, 0x4f, 0xe9, 0xdb, 0x15, 0x64, 0x00, + 0x05, 0xd8, 0xdc, 0x13, 0xfa, 0x01, 0x3d, 0x49, 0xd7, 0x26, 0xb3, 0x01, + 0x49, 0xc0, 0xc7, 0x00, 0x7a, 0x01, 0x03, 0x39, 0xc8, 0xbb, 0x55, 0x01, + 0x01, 0x71, 0xc9, 0xab, 0xc5, 0x01, 0x01, 0x59, 0xc4, 0x01, 0xa3, 0x01, + 0x00, 0x78, 0xd6, 0x2c, 0x27, 0x00, 0x2c, 0x69, 0xc4, 0xbe, 0xaf, 0x0f, + 0xc8, 0xe1, 0xcb, 0x92, 0xa6, 0x00, 0x7e, 0xaa, 0x00, 0xd0, 0x28, 0xc8, + 0x0b, 0xff, 0x01, 0x12, 0xb9, 0xcb, 0x97, 0x3f, 0x01, 0x12, 0xb1, 0xc8, + 0x15, 0x41, 0x01, 0x10, 0xc1, 0xc5, 0x03, 0x98, 0x00, 0x16, 0xd1, 0xc4, + 0xe5, 0x46, 0x0f, 0xb6, 0xf9, 0xc5, 0x03, 0x4a, 0x01, 0x71, 0x80, 0x45, + 0x11, 0x0c, 0xc0, 0xd0, 0x2e, 0x43, 0x0d, 0x79, 0xc0, 0xd0, 0x3a, 0x45, + 0x01, 0x49, 0xc0, 0xd0, 0x46, 0x46, 0x03, 0xec, 0x40, 0xd0, 0x52, 0xce, + 0x6d, 0x28, 0x0f, 0xae, 0xf1, 0x42, 0x00, 0x44, 0x40, 0xd0, 0x5e, 0xc6, + 0xd7, 0x17, 0x0f, 0xbc, 0x59, 0xc7, 0xc5, 0x43, 0x0f, 0xa6, 0x68, 0xc3, + 0x7c, 0xa3, 0x0f, 0x93, 0x29, 0x42, 0x00, 0x4d, 0xc0, 0xd0, 0x6a, 0xc2, + 0x0b, 0xe9, 0x0f, 0x93, 0x19, 0xc2, 0x05, 0xc6, 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0xca, 0xa8, 0xf8, 0x0f, 0x9e, 0x68, 0xca, 0xaa, 0x4c, 0x08, + 0x73, 0xf1, 0x44, 0x05, 0xd7, 0x40, 0xd0, 0xe2, 0x44, 0x23, 0x75, 0xc0, + 0xd0, 0xf4, 0x45, 0x05, 0xdb, 0xc0, 0xd1, 0x00, 0x15, 0xc0, 0xd1, 0x0a, + 0x08, 0xc0, 0xd1, 0x16, 0x16, 0xc0, 0xd1, 0x1e, 0xcb, 0x0d, 0x1e, 0x08, + 0x73, 0x90, 0xc4, 0x23, 0x75, 0x08, 0x73, 0x41, 0xc5, 0x05, 0xdb, 0x08, 0x73, 0x39, 0x15, 0xc0, 0xd1, 0x2c, 0x08, 0xc0, 0xd1, 0x38, 0x16, 0xc0, - 0xd1, 0x44, 0xc3, 0x05, 0x17, 0x08, 0x73, 0x00, 0x47, 0x01, 0xff, 0xc0, - 0xd1, 0x50, 0xcf, 0x61, 0xd1, 0x00, 0xb7, 0x81, 0xcf, 0x68, 0x70, 0x00, - 0xb7, 0x79, 0xcd, 0x7a, 0x71, 0x00, 0xb7, 0x71, 0xd1, 0x50, 0x15, 0x00, - 0xb7, 0x69, 0xd4, 0x3a, 0x32, 0x00, 0xb7, 0x61, 0xd2, 0x4b, 0x1e, 0x00, - 0xb7, 0x58, 0xc2, 0x00, 0x2a, 0x0f, 0x9e, 0x19, 0xd3, 0x44, 0x45, 0x0f, + 0xd1, 0x44, 0xc3, 0x05, 0xd7, 0x08, 0x73, 0x00, 0x47, 0x00, 0x3f, 0xc0, + 0xd1, 0x50, 0xcf, 0x65, 0xa6, 0x00, 0xb7, 0x81, 0xcf, 0x69, 0xcf, 0x00, + 0xb7, 0x79, 0xcd, 0x7d, 0x5b, 0x00, 0xb7, 0x71, 0xd1, 0x56, 0x02, 0x00, + 0xb7, 0x69, 0xd4, 0x39, 0x2f, 0x00, 0xb7, 0x61, 0xd2, 0x48, 0x09, 0x00, + 0xb7, 0x58, 0xc2, 0x00, 0x43, 0x0f, 0x9e, 0x19, 0xd3, 0x40, 0xdd, 0x0f, 0x9d, 0xe8, 0xa2, 0x07, 0xf0, 0x73, 0x00, 0xd1, 0xe0, 0x9e, 0x07, 0xf0, 0x53, 0x00, 0xd2, 0x08, 0x9d, 0x07, 0xf0, 0x4b, 0x00, 0xd2, 0x30, 0xa6, 0x70, 0x08, 0x13, 0x00, 0xd2, 0x58, 0xa5, 0x70, 0x08, 0x0b, 0x00, 0xd2, @@ -3021,315 +3021,315 @@ uint8_t UnicodeNameToCodepointIndex_[242216] = { 0x08, 0xb1, 0xa5, 0x70, 0x08, 0xa9, 0xa4, 0x70, 0x08, 0xa1, 0xa3, 0x70, 0x08, 0x99, 0xa2, 0x70, 0x08, 0x91, 0xa1, 0x70, 0x08, 0x89, 0xa0, 0x70, 0x08, 0x81, 0x9f, 0x70, 0x08, 0x79, 0x9e, 0x70, 0x08, 0x71, 0x9d, 0x70, - 0x08, 0x68, 0x47, 0x13, 0x58, 0xc0, 0xd4, 0x54, 0x45, 0x11, 0xf2, 0x40, - 0xd4, 0xc3, 0xc4, 0x16, 0x57, 0x05, 0x31, 0x01, 0xc3, 0x05, 0x17, 0x05, + 0x08, 0x68, 0x47, 0x13, 0x20, 0xc0, 0xd4, 0x54, 0x45, 0x12, 0x2c, 0x40, + 0xd4, 0xc3, 0xc4, 0x16, 0xc3, 0x05, 0x31, 0x01, 0xc3, 0x05, 0xd7, 0x05, 0x31, 0x09, 0x16, 0xc0, 0xd4, 0xe5, 0x08, 0xc0, 0xd4, 0xf1, 0x15, 0xc0, - 0xd4, 0xfd, 0xc5, 0x05, 0x1b, 0x05, 0x31, 0x41, 0xc4, 0x24, 0x35, 0x05, - 0x31, 0x48, 0x4f, 0x05, 0x17, 0xc0, 0xd5, 0x09, 0x44, 0x02, 0x8d, 0xc0, - 0xd5, 0x2d, 0xd5, 0x33, 0xcd, 0x01, 0x35, 0x41, 0xc4, 0x03, 0x5d, 0x00, - 0x03, 0xe3, 0x00, 0xd5, 0x45, 0xc8, 0x23, 0xac, 0x01, 0x17, 0x71, 0xc9, - 0x39, 0xbf, 0x01, 0x02, 0xf1, 0x16, 0xc0, 0xd5, 0x49, 0xcb, 0x9b, 0x68, - 0x01, 0x4c, 0xd1, 0xc8, 0xbc, 0x8b, 0x01, 0x71, 0xe9, 0x4c, 0x8e, 0x50, - 0xc0, 0xd5, 0x5b, 0xda, 0x1b, 0x6e, 0x01, 0x81, 0xd8, 0x46, 0x11, 0x8d, - 0xc0, 0xd5, 0x6d, 0xd0, 0x60, 0x2f, 0x0f, 0xbd, 0x29, 0x45, 0xe0, 0xee, - 0x40, 0xd5, 0x8f, 0xdc, 0x13, 0xde, 0x00, 0xe7, 0xd1, 0x03, 0xc0, 0xd5, - 0x9b, 0xcb, 0x9c, 0xb2, 0x00, 0xe7, 0xb1, 0xcb, 0x93, 0xc2, 0x00, 0xe7, - 0xa9, 0x14, 0xc0, 0xd5, 0xad, 0xcd, 0x2f, 0x74, 0x00, 0xe7, 0x79, 0xd6, - 0x2f, 0x6b, 0x00, 0xe7, 0x71, 0xc6, 0xd5, 0x68, 0x00, 0xe7, 0x69, 0x48, - 0x59, 0x87, 0xc0, 0xd5, 0xbf, 0xda, 0x1a, 0x36, 0x00, 0xe6, 0xa1, 0xc9, - 0xb2, 0x13, 0x00, 0xe6, 0x98, 0x42, 0x00, 0x68, 0xc0, 0xd5, 0xd7, 0x42, - 0x00, 0x47, 0xc0, 0xd5, 0xe3, 0x47, 0xa4, 0x92, 0xc0, 0xd5, 0xef, 0xe0, - 0x06, 0x87, 0x00, 0xe7, 0x09, 0x16, 0xc0, 0xd5, 0xfb, 0x42, 0x06, 0x6b, - 0xc0, 0xd6, 0x0d, 0x4b, 0x1a, 0x36, 0xc0, 0xd6, 0x19, 0xc7, 0xca, 0x38, - 0x00, 0xe6, 0x91, 0xc5, 0xe3, 0xeb, 0x00, 0xe6, 0x88, 0xc4, 0xea, 0x9b, - 0x0b, 0x7f, 0x89, 0xc2, 0x00, 0x2e, 0x0b, 0x7f, 0x80, 0xc6, 0x9d, 0x44, - 0x0f, 0xa7, 0xc9, 0xc4, 0x7a, 0x3b, 0x0f, 0x9d, 0x70, 0x83, 0x08, 0x2b, + 0xd4, 0xfd, 0xc5, 0x05, 0xdb, 0x05, 0x31, 0x41, 0xc4, 0x23, 0x75, 0x05, + 0x31, 0x48, 0x4f, 0x05, 0xd7, 0xc0, 0xd5, 0x09, 0x44, 0x02, 0xe8, 0xc0, + 0xd5, 0x2d, 0xd5, 0x33, 0x4f, 0x01, 0x35, 0x41, 0xc4, 0x03, 0x8d, 0x00, + 0x03, 0xe3, 0x00, 0xd5, 0x45, 0xc8, 0x26, 0x4c, 0x01, 0x17, 0x71, 0xc9, + 0x39, 0xe8, 0x01, 0x02, 0xf1, 0x16, 0xc0, 0xd5, 0x49, 0xcb, 0x9b, 0xf9, + 0x01, 0x4c, 0xd1, 0xc8, 0xb8, 0x6d, 0x01, 0x71, 0xe9, 0x4c, 0x8e, 0xb3, + 0xc0, 0xd5, 0x5b, 0xda, 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0xea, 0x68, 0x45, 0x00, 0xcd, - 0xc0, 0xea, 0x72, 0xd7, 0x17, 0x18, 0x01, 0x49, 0xd8, 0x46, 0x01, 0xab, - 0x40, 0xea, 0x7c, 0x00, 0xc0, 0xea, 0x88, 0xc3, 0x01, 0x5e, 0x0f, 0x9d, - 0x98, 0xc4, 0x00, 0xfa, 0x0f, 0xa8, 0xb3, 0x00, 0xea, 0x94, 0x95, 0x0f, + 0xe9, 0x65, 0xc5, 0x05, 0xdb, 0x08, 0x08, 0x73, 0x00, 0xe9, 0x77, 0xc4, + 0x23, 0x75, 0x08, 0x08, 0x7a, 0x00, 0xe9, 0x82, 0x46, 0x0e, 0x1f, 0xc0, + 0xe9, 0x8f, 0x4e, 0x71, 0x42, 0x40, 0xe9, 0xa5, 0xce, 0x6e, 0x32, 0x08, + 0x09, 0xf1, 0xcd, 0x78, 0xd6, 0x08, 0x09, 0xf8, 0x0e, 0xc0, 0xe9, 0xb1, + 0x46, 0x10, 0xfc, 0xc0, 0xe9, 0xbd, 0x42, 0x01, 0x58, 0xc0, 0xe9, 0xf6, + 0x49, 0x0a, 0xfb, 0xc0, 0xea, 0x02, 0x43, 0x0d, 0x79, 0xc0, 0xea, 0x1a, + 0x46, 0x03, 0xec, 0x40, 0xea, 0x32, 0xc6, 0x00, 0x29, 0x0f, 0xbc, 0x81, + 0xc6, 0x02, 0xda, 0x0f, 0xbc, 0x30, 0xc6, 0x12, 0x8f, 0x0f, 0xbd, 0x59, + 0xd2, 0x48, 0xbd, 0x0f, 0xbd, 0xb8, 0xd6, 0x03, 0x28, 0x01, 0x1f, 0x09, + 0xcd, 0x02, 0x52, 0x01, 0x1e, 0xf9, 0xcb, 0x19, 0xee, 0x01, 0x1e, 0xe9, + 0xce, 0x25, 0xe6, 0x01, 0x1d, 0xab, 0x00, 0xea, 0x4a, 0x45, 0x00, 0x5d, + 0xc0, 0xea, 0x50, 0x46, 0x03, 0xec, 0xc0, 0xea, 0x68, 0x45, 0x01, 0x49, + 0xc0, 0xea, 0x72, 0xd7, 0x18, 0x26, 0x01, 0x49, 0xd8, 0x46, 0x01, 0x35, + 0x40, 0xea, 0x7c, 0x00, 0xc0, 0xea, 0x88, 0xc3, 0x00, 0xaf, 0x0f, 0x9d, + 0x98, 0xc4, 0x01, 0xa3, 0x0f, 0xa8, 0xb3, 0x00, 0xea, 0x94, 0x95, 0x0f, 0xa6, 0xd0, 0x84, 0x01, 0x88, 0x2b, 0x00, 0xea, 0x9a, 0x92, 0x01, 0x88, 0x31, 0x8f, 0x01, 0x88, 0x39, 0x88, 0x01, 0x88, 0x41, 0x86, 0x01, 0x88, 0x49, 0x96, 0x01, 0x88, 0x51, 0x90, 0x01, 0x88, 0x5b, 0x00, 0xea, 0x9e, @@ -3343,176 +3343,176 @@ uint8_t UnicodeNameToCodepointIndex_[242216] = { 0xeb, 0x10, 0x8b, 0x01, 0x89, 0x3b, 0x00, 0xeb, 0x27, 0x97, 0x01, 0x89, 0x43, 0x00, 0xeb, 0x40, 0x98, 0x01, 0x89, 0x50, 0x92, 0x01, 0x8d, 0xa1, 0x96, 0x01, 0x8d, 0xa9, 0x8d, 0x01, 0x8d, 0xb1, 0x8a, 0x01, 0x8d, 0xb9, - 0x89, 0x01, 0x8d, 0xd8, 0xc3, 0xed, 0x6b, 0x0f, 0xd8, 0x03, 0x00, 0xeb, - 0x46, 0xc3, 0xed, 0x65, 0x0f, 0xd8, 0x1b, 0x00, 0xeb, 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0x09, 0x7f, 0x88, 0x1e, - 0xc1, 0x68, 0x3c, 0x1d, 0x41, 0x68, 0x48, 0x26, 0xc1, 0x68, 0x6c, 0x25, - 0xc1, 0x68, 0x90, 0x24, 0xc1, 0x68, 0xb8, 0x23, 0xc1, 0x68, 0xdf, 0x22, - 0xc1, 0x69, 0x03, 0x21, 0xc1, 0x69, 0x27, 0x20, 0xc1, 0x69, 0x3f, 0x1f, - 0xc1, 0x69, 0x5f, 0x1e, 0xc1, 0x69, 0x7f, 0x1d, 0x41, 0x69, 0x9e, 0x87, + 0xc1, 0x68, 0x48, 0x1d, 0x41, 0x68, 0x54, 0x26, 0xc1, 0x68, 0x78, 0x25, + 0xc1, 0x68, 0x9c, 0x24, 0xc1, 0x68, 0xc4, 0x23, 0xc1, 0x68, 0xeb, 0x22, + 0xc1, 0x69, 0x0f, 0x21, 0xc1, 0x69, 0x33, 0x20, 0xc1, 0x69, 0x4b, 0x1f, + 0xc1, 0x69, 0x6b, 0x1e, 0xc1, 0x69, 0x8b, 0x1d, 0x41, 0x69, 0xaa, 0x87, 0x08, 0x41, 0x99, 0x8b, 0x08, 0x41, 0xa1, 0x91, 0x08, 0x41, 0xa9, 0x83, 0x08, 0x41, 0x90, 0x83, 0x08, 0x41, 0xb9, 0x87, 0x08, 0x41, 0xc0, 0x83, 0x08, 0x41, 0xe1, 0x91, 0x08, 0x41, 0xf8, 0x83, 0x08, 0x40, 0x29, 0x91, @@ -4871,592 +4871,592 @@ uint8_t UnicodeNameToCodepointIndex_[242216] = { 0x08, 0x41, 0x38, 0x83, 0x08, 0x41, 0x41, 0x87, 0x08, 0x41, 0x49, 0x8b, 0x08, 0x41, 0x51, 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0x82, 0xe8, 0x47, 0x7d, 0xc4, 0x41, + 0xc2, 0x11, 0x83, 0x01, 0x82, 0x59, 0x8b, 0x01, 0x82, 0x69, 0x97, 0x01, 0x82, 0x79, 0x87, 0x01, 0x82, 0x89, 0x91, 0x01, 0x82, 0x98, 0x83, 0x01, 0x82, 0x61, 0x8b, 0x01, 0x82, 0x71, 0x97, 0x01, 0x82, 0x81, 0x87, 0x01, 0x82, 0x91, 0x91, 0x01, 0x82, 0xa0, 0x83, 0x01, 0x82, 0xb1, 0x8b, 0x01, @@ -6508,821 +6508,822 @@ uint8_t UnicodeNameToCodepointIndex_[242216] = { 0x84, 0x49, 0x8b, 0x01, 0x84, 0x51, 0x97, 0x01, 0x84, 0x59, 0x87, 0x01, 0x84, 0x61, 0x91, 0x01, 0x84, 0x68, 0x83, 0x01, 0x84, 0x79, 0x8b, 0x01, 0x84, 0x81, 0x87, 0x01, 0x84, 0x89, 0x91, 0x01, 0x84, 0x90, 0x00, 0xc1, - 0xc2, 0x11, 0xcb, 0x97, 0xab, 0x01, 0x01, 0x38, 0x45, 0x66, 0xf4, 0xc1, - 0xc2, 0x1d, 0xcc, 0x0c, 0x86, 0x01, 0x2e, 0xc9, 0xc6, 0x19, 0x7a, 0x01, - 0x2e, 0xc1, 0xcc, 0x04, 0x1b, 0x0f, 0xdc, 0x81, 0x42, 0x00, 0x68, 0x41, - 0xc2, 0x29, 0xc9, 0x11, 0x81, 0x01, 0x37, 0x39, 0x0e, 0xc1, 0xc2, 0x2f, - 0xc8, 0xc1, 0xa3, 0x01, 0x09, 0x39, 0xc8, 0xbd, 0x53, 0x01, 0x02, 0xa1, - 0xd0, 0x0f, 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0x81, 0xa2, 0x09, 0x84, + 0x84, 0x8b, 0x01, 0xfd, 0x8d, 0xa3, 0x09, 0x84, 0x81, 0xa2, 0x09, 0x84, 0x79, 0xa1, 0x09, 0x84, 0x71, 0xa0, 0x09, 0x84, 0x69, 0x9f, 0x09, 0x84, 0x61, 0x9e, 0x09, 0x84, 0x59, 0x9d, 0x09, 0x84, 0x50, 0xa6, 0x09, 0x84, 0x49, 0xa5, 0x09, 0x84, 0x41, 0xa4, 0x09, 0x84, 0x39, 0xa3, 0x09, 0x84, 0x31, 0xa2, 0x09, 0x84, 0x29, 0xa1, 0x09, 0x84, 0x21, 0xa0, 0x09, 0x84, 0x19, 0x9f, 0x09, 0x84, 0x11, 0x9e, 0x09, 0x84, 0x09, 0x9d, 0x09, 0x84, - 0x00, 0xa6, 0x09, 0x83, 0xf9, 0xa5, 0x09, 0x83, 0xeb, 0x01, 0xfd, 0x8f, + 0x00, 0xa6, 0x09, 0x83, 0xf9, 0xa5, 0x09, 0x83, 0xeb, 0x01, 0xfd, 0x91, 0xa4, 0x09, 0x83, 0xe1, 0xa3, 0x09, 0x83, 0xd9, 0xa2, 0x09, 0x83, 0xd1, 0xa1, 0x09, 0x83, 0xc9, 0xa0, 0x09, 0x83, 0xc1, 0x9f, 0x09, 0x83, 0xb9, 0x9e, 0x09, 0x83, 0xb0, 0xa1, 0x09, 0x83, 0xa9, 0xa0, 0x09, 0x83, 0xa1, @@ -7330,604 +7331,604 @@ uint8_t UnicodeNameToCodepointIndex_[242216] = { 0xa6, 0x09, 0x83, 0x81, 0xa5, 0x09, 0x83, 0x79, 0xa4, 0x09, 0x83, 0x71, 0xa3, 0x09, 0x83, 0x69, 0xa2, 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0x1d, 0x1f, 0xc3, + 0xec, 0xeb, 0x08, 0x2a, 0xd0, 0xc2, 0x00, 0x53, 0x08, 0x29, 0xf1, 0xc3, + 0x73, 0x9b, 0x08, 0x2a, 0x28, 0xc3, 0xca, 0x89, 0x08, 0x2a, 0x19, 0xc3, + 0x1f, 0xb3, 0x08, 0x2a, 0x88, 0xc2, 0x00, 0x2c, 0x08, 0x2a, 0x21, 0xc2, + 0x71, 0x26, 0x08, 0x2b, 0x18, 0x9b, 0x08, 0x2a, 0x39, 0x94, 0x08, 0x2a, + 0x68, 0xc2, 0x00, 0x99, 0x08, 0x2a, 0xb9, 0xc3, 0xec, 0x2e, 0x08, 0x2b, 0x10, 0x9d, 0x17, 0xcf, 0x01, 0x88, 0x17, 0xcf, 0x79, 0x87, 0x17, 0xcf, 0x71, 0x86, 0x17, 0xcf, 0x69, 0x85, 0x17, 0xcf, 0x61, 0x84, 0x17, 0xcf, 0x59, 0x83, 0x17, 0xcf, 0x51, 0xa6, 0x17, 0xcf, 0x49, 0xa5, 0x17, 0xcf, @@ -8266,405 +8267,405 @@ uint8_t UnicodeNameToCodepointIndex_[242216] = { 0x49, 0xa5, 0x07, 0xc8, 0x41, 0xa4, 0x07, 0xc8, 0x39, 0xa3, 0x07, 0xc8, 0x31, 0xa2, 0x07, 0xc8, 0x29, 0xa1, 0x07, 0xc8, 0x21, 0xa0, 0x07, 0xc8, 0x19, 0x9d, 0x07, 0xc8, 0x01, 0x9e, 0x07, 0xc8, 0x09, 0x9f, 0x07, 0xc8, - 0x10, 0xc3, 0x05, 0x17, 0x01, 0x74, 0x11, 0x16, 0x42, 0x1d, 0x2a, 0xc3, - 0x05, 0x17, 0x01, 0x74, 0xa1, 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0x27, 0xac, 0x05, 0x34, 0x90, + 0xc2, 0x1c, 0x72, 0x00, 0x20, 0x51, 0xca, 0xa9, 0xb6, 0x05, 0x32, 0x70, + 0xc8, 0x85, 0x33, 0x05, 0x32, 0x51, 0xc7, 0x7f, 0xaa, 0x05, 0x33, 0x40, 0xa1, 0x09, 0x7f, 0x81, 0x9f, 0x09, 0x7f, 0x79, 0x9d, 0x09, 0x7f, 0x70, 0xa6, 0x09, 0x7f, 0x69, 0xa5, 0x09, 0x7f, 0x61, 0xa4, 0x09, 0x7f, 0x59, 0xa2, 0x09, 0x7f, 0x51, 0xa1, 0x09, 0x7f, 0x49, 0xa0, 0x09, 0x7f, 0x41, @@ -8676,7 +8677,7 @@ uint8_t UnicodeNameToCodepointIndex_[242216] = { 0xa3, 0x09, 0x7e, 0xc1, 0xa2, 0x09, 0x7e, 0xb9, 0xa1, 0x09, 0x7e, 0xb1, 0xa0, 0x09, 0x7e, 0xa9, 0x9f, 0x09, 0x7e, 0xa1, 0x9e, 0x09, 0x7e, 0x99, 0x9d, 0x09, 0x7e, 0x90, 0xa6, 0x09, 0x7e, 0x89, 0xa5, 0x09, 0x7e, 0x81, - 0xa3, 0x09, 0x7e, 0x79, 0xa2, 0x09, 0x7e, 0x6b, 0x02, 0x31, 0xc8, 0xa1, + 0xa3, 0x09, 0x7e, 0x79, 0xa2, 0x09, 0x7e, 0x6b, 0x02, 0x31, 0xca, 0xa1, 0x09, 0x7e, 0x61, 0xa0, 0x09, 0x7e, 0x59, 0x9f, 0x09, 0x7e, 0x51, 0x9e, 0x09, 0x7e, 0x49, 0x9d, 0x09, 0x7e, 0x40, 0xa6, 0x09, 0x7e, 0x39, 0xa5, 0x09, 0x7e, 0x31, 0xa4, 0x09, 0x7e, 0x29, 0xa3, 0x09, 0x7e, 0x21, 0xa1, @@ -8693,346 +8694,346 @@ uint8_t UnicodeNameToCodepointIndex_[242216] = { 0x09, 0x7d, 0x29, 0xa3, 0x09, 0x7d, 0x21, 0xa2, 0x09, 0x7d, 0x19, 0xa1, 0x09, 0x7d, 0x11, 0xa0, 0x09, 0x7d, 0x09, 0x9e, 0x09, 0x7d, 0x00, 0xa6, 0x09, 0x7c, 0xf9, 0xa4, 0x09, 0x7c, 0xf1, 0xa2, 0x09, 0x7c, 0xe9, 0xa0, - 0x09, 0x7c, 0xe1, 0x9f, 0x09, 0x7c, 0xd3, 0x02, 0x31, 0xcc, 0x9e, 0x09, + 0x09, 0x7c, 0xe1, 0x9f, 0x09, 0x7c, 0xd3, 0x02, 0x31, 0xce, 0x9e, 0x09, 0x7c, 0xc9, 0x9d, 0x09, 0x7c, 0xc0, 0xa6, 0x09, 0x7c, 0xb9, 0xa5, 0x09, 0x7c, 0xb1, 0xa4, 0x09, 0x7c, 0xa9, 0xa3, 0x09, 0x7c, 0xa1, 0xa2, 0x09, 0x7c, 0x99, 0xa1, 0x09, 0x7c, 0x91, 0x9f, 0x09, 0x7c, 0x89, 0x9e, 0x09, - 0x7c, 0x80, 0xc4, 0x05, 0xde, 0x00, 0x04, 0x79, 0xc2, 0x0a, 0x20, 0x00, - 0x04, 0x70, 0xe0, 0x06, 0xc7, 0x01, 0x01, 0xd0, 0x07, 0xc2, 0x31, 0xd0, - 0xd3, 0x46, 0x92, 0x01, 0x00, 0xd0, 0x44, 0x05, 0x17, 0xc2, 0x31, 0xd6, - 0xc6, 0x29, 0x29, 0x08, 0x8f, 0x91, 0xc6, 0xd1, 0xe4, 0x08, 0x8f, 0x89, - 0x15, 0xc2, 0x31, 0xe2, 0x08, 0xc2, 0x31, 0xee, 0x16, 0x42, 0x31, 0xfa, - 0xc4, 0x24, 0x35, 0x08, 0x8f, 0x49, 0xc5, 0x05, 0x1b, 0x08, 0x8f, 0x41, - 0x15, 0xc2, 0x32, 0x0c, 0x08, 0xc2, 0x32, 0x18, 0x16, 0xc2, 0x32, 0x24, - 0xc3, 0x05, 0x17, 0x08, 0x8f, 0x08, 0xc9, 0xad, 0x27, 0x00, 0x6c, 0x11, - 0xc8, 0xbb, 0x8b, 0x00, 0x6e, 0x50, 0x03, 0xc2, 0x32, 0x30, 0x0b, 0xc2, - 0x32, 0x58, 0x17, 0xc2, 0x32, 0x70, 0x07, 0xc2, 0x32, 0x7c, 0x11, 0xc2, - 0x32, 0x88, 0x0f, 0xc2, 0x32, 0x94, 0xd2, 0x47, 0xe2, 0x00, 0x6c, 0xf1, - 0x48, 0xba, 0xcb, 0xc2, 0x32, 0x9e, 0x48, 0xc2, 0x93, 0xc2, 0x32, 0xae, - 0x48, 0xc2, 0x8b, 0xc2, 0x32, 0xba, 0xc7, 0xc6, 0xaa, 0x00, 0x6d, 0xd1, - 0xc7, 0xc9, 0x3c, 0x00, 0x6d, 0xd9, 0xc7, 0xcc, 0xf4, 0x00, 0x6e, 0x01, - 0xc7, 0xc5, 0xe6, 0x00, 0x6e, 0x21, 0xc7, 0xcf, 0x16, 0x00, 0x6e, 0x30, - 0xc4, 0x16, 0x57, 0x00, 0x6f, 0x31, 0xc3, 0x05, 0x17, 0x00, 0x6f, 0x39, - 0x16, 0xc2, 0x32, 0xcc, 0x08, 0xc2, 0x32, 0xd8, 0x15, 0xc2, 0x32, 0xe4, - 0xc5, 0x05, 0x1b, 0x00, 0x6f, 0x71, 0xc4, 0x24, 0x35, 0x00, 0x6f, 0x78, - 0x45, 0xb0, 0xfc, 0xc2, 0x32, 0xf0, 0x44, 0xcd, 0xdc, 0x42, 0x33, 0x02, - 0xca, 0xa6, 0x28, 0x00, 0x6e, 0x89, 0xc8, 0xb9, 0x2b, 0x00, 0x6e, 0x99, - 0xc9, 0xad, 0x5d, 0x00, 0x6e, 0xb1, 0xc7, 0xcd, 0xdb, 0x00, 0x6e, 0xd1, - 0x42, 0x07, 0x69, 0x42, 0x33, 0x11, 0xca, 0xaa, 0x92, 0x00, 0x6e, 0xc1, - 0xc9, 0x8f, 0xd0, 0x00, 0x6e, 0xf8, 0x49, 0xb1, 0x71, 0xc2, 0x33, 0x1d, - 0x4d, 0x4e, 0x90, 0xc2, 0x33, 0x53, 0x4c, 0x56, 0x20, 0x42, 0x33, 0x6e, - 0xc7, 0x03, 0x28, 0x0e, 0xc8, 0x99, 0xc8, 0x3a, 0x32, 0x0e, 0xc8, 0x91, - 0xc6, 0x23, 0x24, 0x0e, 0xc8, 0x88, 0x4a, 0xa5, 0x9c, 0xc2, 0x33, 0x86, - 0xc4, 0x02, 0xfa, 0x0e, 0xd3, 0xf0, 0xda, 0x1c, 0x0a, 0x0e, 0xd3, 0x81, - 0x44, 0x04, 0x50, 0x42, 0x33, 0xa4, 0xc8, 0xc3, 0xb3, 0x0e, 0xd0, 0x99, - 0xc7, 0xc9, 0x5f, 0x0e, 0xd0, 0x91, 0xc7, 0x82, 0x79, 0x0e, 0xd0, 0x88, - 0xca, 0x9f, 0x84, 0x0e, 0xd0, 0x43, 0x02, 0x33, 0xae, 0xcf, 0x62, 0x58, - 0x0e, 0xd0, 0x38, 0xc3, 0x0c, 0x34, 0x0e, 0xd4, 0x51, 0xc3, 0x00, 0xec, - 0x0e, 0xd4, 0x38, 0xc6, 0xd8, 0xe0, 0x0e, 0xd1, 0x61, 0xc7, 0x82, 0x79, - 0x0e, 0xd1, 0x59, 0xc6, 0xd3, 0x2e, 0x0e, 0xd1, 0x50, 0xd2, 0x48, 0x18, - 0x0e, 0xd3, 0x89, 0x44, 0x03, 0x1d, 0x42, 0x33, 0xb4, 0xd1, 0x53, 0x78, - 0x0e, 0xc9, 0x01, 0x15, 0xc2, 0x33, 0xc0, 0x46, 0x15, 0x2e, 0x42, 0x33, - 0xcc, 0xc7, 0x03, 0x28, 0x0e, 0xc8, 0xa9, 0xc7, 0x01, 0xb1, 0x0e, 0xc8, - 0xa0, 0xc7, 0x03, 0x28, 0x0e, 0xc8, 0x69, 0xc8, 0x3a, 0x32, 0x0e, 0xc8, - 0x61, 0xc6, 0x23, 0x24, 0x0e, 0xc8, 0x58, 0x42, 0x00, 0xf8, 0xc2, 0x33, - 0xd8, 0xd2, 0x4e, 0x90, 0x0e, 0xd4, 0x01, 0xd1, 0x56, 0x20, 0x0e, 0xd3, - 0xf8, 0x43, 0x0e, 0xd0, 0xc2, 0x33, 0xf6, 0x12, 0x42, 0x34, 0x02, 0x42, - 0x00, 0x14, 0xc2, 0x34, 0x0c, 0x45, 0xe2, 0x42, 0xc2, 0x34, 0x18, 0x44, - 0xe0, 0xef, 0x42, 0x34, 0x3c, 0xc3, 0x1e, 0x54, 0x0e, 0xd3, 0x0b, 0x02, - 0x34, 0x4e, 0x4b, 0x95, 0x64, 0x42, 0x34, 0x52, 0x4d, 0x7b, 0x00, 0xc2, - 0x34, 0x64, 0x4c, 0x8e, 0xf8, 0x42, 0x34, 0x70, 0x43, 0x99, 0x2d, 0xc2, - 0x34, 0x82, 0x47, 0xc4, 0xab, 0xc2, 0x34, 0x8e, 0x00, 0xc2, 0x34, 0xa0, - 0x42, 0x00, 0x27, 0xc2, 0x34, 0xac, 0x4f, 0x67, 0x62, 0x42, 0x34, 0xca, - 0xc2, 0x00, 0xac, 0x0e, 0xd3, 0x59, 0x10, 0x42, 0x34, 0xdc, 0x00, 0x42, - 0x35, 0x00, 0x19, 0xc2, 0x35, 0x0c, 0xc7, 0xc9, 0x5f, 0x0e, 0xd1, 0x91, - 0xc7, 0x82, 0x79, 0x0e, 0xd1, 0x88, 0x4d, 0x7e, 0x19, 0xc2, 0x35, 0x18, - 0x4c, 0x8d, 0x48, 0xc2, 0x35, 0x5e, 0x4b, 0x96, 0xae, 0xc2, 0x35, 0xa4, - 0x48, 0xba, 0x9b, 0x42, 0x35, 0xb6, 0x49, 0xaf, 0x28, 0xc2, 0x35, 0xc8, - 0x05, 0xc2, 0x35, 0xd4, 0xc5, 0xdf, 0x18, 0x0e, 0xd2, 0x83, 0x02, 0x35, - 0xe0, 0xc4, 0x67, 0x8b, 0x0e, 0xd2, 0x6b, 0x02, 0x35, 0xe4, 0x45, 0x03, - 0xf5, 0xc2, 0x35, 0xe8, 0xc5, 0x7e, 0x0c, 0x0e, 0xd2, 0x0b, 0x02, 0x36, - 0x0c, 0xc5, 0xb2, 0x44, 0x0e, 0xd1, 0xf2, 0x02, 0x36, 0x10, 0xc6, 0xd4, - 0x8a, 0x0e, 0xd1, 0xd1, 0xc6, 0xd4, 0x0c, 0x0e, 0xd1, 0xc8, 0xc7, 0x03, - 0x28, 0x0e, 0xc8, 0x81, 0xc8, 0x3a, 0x32, 0x0e, 0xc8, 0x79, 0xc6, 0x23, - 0x24, 0x0e, 0xc8, 0x70, 0xd0, 0x60, 0xbf, 0x0e, 0xd1, 0xc1, 0xc6, 0x01, - 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0x67, 0x01, 0x5e, 0x99, 0xc4, 0x03, 0x74, 0x01, 0x5e, 0xa0, 0xc3, + 0x09, 0x9e, 0x01, 0x5e, 0xa9, 0xc3, 0x0d, 0x32, 0x01, 0x5e, 0xb0, 0xc8, + 0x00, 0xbf, 0x01, 0x51, 0xc9, 0xd1, 0x4f, 0xe6, 0x01, 0x51, 0x71, 0xd0, + 0x59, 0x64, 0x01, 0x51, 0x68, 0xce, 0x6f, 0xc8, 0x01, 0x51, 0x41, 0x15, + 0xc2, 0x3d, 0xf0, 0x46, 0x1e, 0x6b, 0xc2, 0x3d, 0xfc, 0xc9, 0x0d, 0xd7, + 0x01, 0x51, 0x29, 0xd7, 0x27, 0x6b, 0x01, 0x51, 0x18, 0xcb, 0x93, 0xae, + 0x0f, 0xae, 0xf9, 0xc3, 0x02, 0x53, 0x0f, 0xa6, 0x18, 0x45, 0x03, 0x8d, + 0xc2, 0x3e, 0x08, 0xcc, 0x40, 0xab, 0x01, 0x10, 0x10, 0x9c, 0x01, 0x25, 0xa9, 0x9b, 0x01, 0x25, 0xa1, 0x9a, 0x01, 0x25, 0x99, 0x99, 0x01, 0x25, 0x91, 0x98, 0x01, 0x25, 0x89, 0x97, 0x01, 0x25, 0x81, 0x96, 0x01, 0x25, 0x79, 0x95, 0x01, 0x25, 0x71, 0x94, 0x01, 0x25, 0x69, 0x93, 0x01, 0x25, @@ -9050,201 +9051,201 @@ uint8_t UnicodeNameToCodepointIndex_[242216] = { 0xe1, 0x90, 0x0f, 0x88, 0xe9, 0x91, 0x0f, 0x88, 0xf1, 0x92, 0x0f, 0x88, 0xf9, 0x93, 0x0f, 0x89, 0x01, 0x94, 0x0f, 0x89, 0x09, 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0x02, 0x42, + 0xab, 0x06, 0xc2, 0x42, 0xb1, 0xcd, 0x81, 0x6b, 0x01, 0x0e, 0x51, 0xcc, + 0x2f, 0x5f, 0x01, 0x0d, 0x79, 0xc6, 0xd3, 0x3f, 0x0f, 0xb3, 0x79, 0x46, + 0x03, 0xb1, 0xc2, 0x42, 0xbd, 0xd1, 0x55, 0xbe, 0x0f, 0xc1, 0xb9, 0xd0, + 0x5a, 0xe4, 0x0f, 0xc1, 0xf8, 0xd2, 0x4e, 0x27, 0x01, 0x57, 0x88, 0xa3, 0x0f, 0x82, 0x99, 0x9d, 0x0f, 0x82, 0x69, 0x9e, 0x0f, 0x82, 0x71, 0x9f, 0x0f, 0x82, 0x79, 0xa0, 0x0f, 0x82, 0x81, 0xa1, 0x0f, 0x82, 0x89, 0xa2, 0x0f, 0x82, 0x90, 0xa3, 0x0f, 0x81, 0xf1, 0xa1, 0x0f, 0x81, 0xe1, 0x9d, @@ -9277,591 +9278,591 @@ uint8_t UnicodeNameToCodepointIndex_[242216] = { 0x0f, 0x84, 0x51, 0xa2, 0x0f, 0x84, 0x59, 0xa3, 0x0f, 0x84, 0x61, 0x9d, 0x0f, 0x84, 0x30, 0x9d, 0x0f, 0x84, 0x69, 0x9e, 0x0f, 0x84, 0x71, 0x9f, 0x0f, 0x84, 0x79, 0xa0, 0x0f, 0x84, 0x81, 0xa1, 0x0f, 0x84, 0x89, 0xa2, - 0x0f, 0x84, 0x91, 0xa3, 0x0f, 0x84, 0x98, 0x05, 0xc2, 0x42, 0xc7, 0x49, - 0x02, 0x5b, 0xc2, 0x42, 0xd9, 0x17, 0xc2, 0x42, 0xe8, 0x44, 0x04, 0x8b, - 0xc2, 0x42, 0xf4, 0x15, 0xc2, 0x43, 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0xf8, 0xa6, 0x0a, 0x20, 0xf1, 0xa5, 0x0a, 0x20, 0xe9, 0xa4, 0x0a, - 0x20, 0xe1, 0xa3, 0x0a, 0x20, 0xd3, 0x02, 0x56, 0x13, 0xa2, 0x0a, 0x20, + 0x20, 0xe1, 0xa3, 0x0a, 0x20, 0xd3, 0x02, 0x56, 0x15, 0xa2, 0x0a, 0x20, 0xc9, 0xa1, 0x0a, 0x20, 0xc1, 0xa0, 0x0a, 0x20, 0xb9, 0x9f, 0x0a, 0x20, 0xb1, 0x9e, 0x0a, 0x20, 0xa9, 0x9d, 0x0a, 0x20, 0xa0, 0xa6, 0x0a, 0x20, 0x99, 0xa5, 0x0a, 0x20, 0x91, 0xa4, 0x0a, 0x20, 0x89, 0xa3, 0x0a, 0x20, 0x81, 0xa2, 0x0a, 0x20, 0x79, 0xa1, 0x0a, 0x20, 0x71, 0xa0, 0x0a, 0x20, 0x69, 0x9f, 0x0a, 0x20, 0x61, 0x9e, 0x0a, 0x20, 0x59, 0x9d, 0x0a, 0x20, - 0x4a, 0x02, 0x56, 0x17, 0xa6, 0x0a, 0x20, 0x41, 0xa5, 0x0a, 0x20, 0x39, + 0x4a, 0x02, 0x56, 0x19, 0xa6, 0x0a, 0x20, 0x41, 0xa5, 0x0a, 0x20, 0x39, 0xa4, 0x0a, 0x20, 0x31, 0xa3, 0x0a, 0x20, 0x29, 0xa2, 0x0a, 0x20, 0x21, 0xa1, 0x0a, 0x20, 0x19, 0xa0, 0x0a, 0x20, 0x11, 0x9f, 0x0a, 0x20, 0x09, 0x9e, 0x0a, 0x20, 0x00, 0x9d, 0x0a, 0x22, 0x11, 0x9e, 0x0a, 0x22, 0x19, 0x9f, 0x0a, 0x22, 0x21, 0xa0, 0x0a, 0x22, 0x29, 0xa1, 0x0a, 0x22, 0x31, - 0xa2, 0x0a, 0x22, 0x39, 0xa3, 0x0a, 0x22, 0x43, 0x02, 0x56, 0x1b, 0xa4, + 0xa2, 0x0a, 0x22, 0x39, 0xa3, 0x0a, 0x22, 0x43, 0x02, 0x56, 0x1d, 0xa4, 0x0a, 0x22, 0x61, 0xa5, 0x0a, 0x22, 0x69, 0xa6, 0x0a, 0x22, 0x70, 0x9d, 0x0a, 0x22, 0x79, 0x9e, 0x0a, 0x22, 0x81, 0x9f, 0x0a, 0x22, 0x89, 0xa0, 0x0a, 0x22, 0x91, 0xa1, 0x0a, 0x22, 0x99, 0xa2, 0x0a, 0x22, 0xa1, 0xa3, @@ -9872,22 +9873,22 @@ uint8_t UnicodeNameToCodepointIndex_[242216] = { 0x0a, 0x23, 0x09, 0xa6, 0x0a, 0x23, 0x10, 0x9d, 0x0a, 0x23, 0x19, 0x9e, 0x0a, 0x23, 0x21, 0x9f, 0x0a, 0x23, 0x29, 0xa0, 0x0a, 0x23, 0x31, 0xa1, 0x0a, 0x23, 0x39, 0xa2, 0x0a, 0x23, 0x41, 0xa3, 0x0a, 0x23, 0x49, 0xa4, - 0x0a, 0x23, 0x53, 0x02, 0x56, 0x27, 0xa5, 0x0a, 0x23, 0x63, 0x02, 0x56, - 0x2b, 0xa6, 0x0a, 0x23, 0x70, 0x9d, 0x0a, 0x23, 0x7b, 0x02, 0x56, 0x2f, - 0x9e, 0x0a, 0x23, 0x8b, 0x02, 0x56, 0x33, 0x9f, 0x0a, 0x23, 0x9b, 0x02, - 0x56, 0x37, 0xa0, 0x0a, 0x23, 0xa9, 0xa1, 0x0a, 0x23, 0xb3, 0x02, 0x56, - 0x3b, 0xa2, 0x0a, 0x23, 0xd3, 0x02, 0x56, 0x47, 0xa3, 0x0a, 0x23, 0xe9, - 0xa4, 0x0a, 0x23, 0xf3, 0x02, 0x56, 0x4f, 0xa5, 0x0a, 0x24, 0x11, 0xa6, - 0x0a, 0x24, 0x18, 0x9d, 0x0a, 0x24, 0x23, 0x02, 0x56, 0x5b, 0x9e, 0x0a, + 0x0a, 0x23, 0x53, 0x02, 0x56, 0x29, 0xa5, 0x0a, 0x23, 0x63, 0x02, 0x56, + 0x2d, 0xa6, 0x0a, 0x23, 0x70, 0x9d, 0x0a, 0x23, 0x7b, 0x02, 0x56, 0x31, + 0x9e, 0x0a, 0x23, 0x8b, 0x02, 0x56, 0x35, 0x9f, 0x0a, 0x23, 0x9b, 0x02, + 0x56, 0x39, 0xa0, 0x0a, 0x23, 0xa9, 0xa1, 0x0a, 0x23, 0xb3, 0x02, 0x56, + 0x3d, 0xa2, 0x0a, 0x23, 0xd3, 0x02, 0x56, 0x49, 0xa3, 0x0a, 0x23, 0xe9, + 0xa4, 0x0a, 0x23, 0xf3, 0x02, 0x56, 0x51, 0xa5, 0x0a, 0x24, 0x11, 0xa6, + 0x0a, 0x24, 0x18, 0x9d, 0x0a, 0x24, 0x23, 0x02, 0x56, 0x5d, 0x9e, 0x0a, 0x24, 0x39, 0x9f, 0x0a, 0x24, 0x41, 0xa0, 0x0a, 0x24, 0x49, 0xa1, 0x0a, - 0x24, 0x51, 0xa2, 0x0a, 0x24, 0x5b, 0x02, 0x56, 0x63, 0xa3, 0x0a, 0x24, + 0x24, 0x51, 0xa2, 0x0a, 0x24, 0x5b, 0x02, 0x56, 0x65, 0xa3, 0x0a, 0x24, 0x69, 0xa4, 0x0a, 0x24, 0x71, 0xa5, 0x0a, 0x24, 0x79, 0xa6, 0x0a, 0x24, 0x80, 0x9d, 0x0a, 0x24, 0x89, 0x9e, 0x0a, 0x24, 0x91, 0x9f, 0x0a, 0x24, 0x99, 0xa0, 0x0a, 0x24, 0xa1, 0xa1, 0x0a, 0x24, 0xa9, 0xa2, 0x0a, 0x24, - 0xb3, 0x02, 0x56, 0x67, 0xa3, 0x0a, 0x24, 0xc1, 0xa4, 0x0a, 0x24, 0xc9, + 0xb3, 0x02, 0x56, 0x69, 0xa3, 0x0a, 0x24, 0xc1, 0xa4, 0x0a, 0x24, 0xc9, 0xa5, 0x0a, 0x24, 0xd1, 0xa6, 0x0a, 0x24, 0xd8, 0x9d, 0x0a, 0x24, 0xe1, 0x9e, 0x0a, 0x24, 0xe9, 0x9f, 0x0a, 0x24, 0xf1, 0xa0, 0x0a, 0x24, 0xf9, - 0xa1, 0x0a, 0x25, 0x01, 0xa2, 0x0a, 0x25, 0x0b, 0x02, 0x56, 0x6b, 0xa3, + 0xa1, 0x0a, 0x25, 0x01, 0xa2, 0x0a, 0x25, 0x0b, 0x02, 0x56, 0x6d, 0xa3, 0x0a, 0x25, 0x19, 0xa4, 0x0a, 0x25, 0x21, 0xa5, 0x0a, 0x25, 0x29, 0xa6, 0x0a, 0x25, 0x30, 0x9d, 0x0a, 0x25, 0x39, 0x9e, 0x0a, 0x25, 0x41, 0x9f, 0x0a, 0x25, 0x49, 0xa0, 0x0a, 0x25, 0x51, 0xa1, 0x0a, 0x25, 0x59, 0xa2, @@ -9910,17 +9911,17 @@ uint8_t UnicodeNameToCodepointIndex_[242216] = { 0x0a, 0x26, 0xe1, 0xa1, 0x0a, 0x26, 0xe9, 0xa2, 0x0a, 0x26, 0xf1, 0xa3, 0x0a, 0x26, 0xf9, 0xa4, 0x0a, 0x27, 0x01, 0xa5, 0x0a, 0x27, 0x09, 0xa6, 0x0a, 0x27, 0x10, 0x9d, 0x0a, 0x27, 0x19, 0x9e, 0x0a, 0x27, 0x21, 0x9f, - 0x0a, 0x27, 0x2b, 0x02, 0x56, 0x6f, 0xa0, 0x0a, 0x27, 0x41, 0xa1, 0x0a, + 0x0a, 0x27, 0x2b, 0x02, 0x56, 0x71, 0xa0, 0x0a, 0x27, 0x41, 0xa1, 0x0a, 0x27, 0x49, 0xa2, 0x0a, 0x27, 0x51, 0xa3, 0x0a, 0x27, 0x59, 0xa4, 0x0a, - 0x27, 0x63, 0x02, 0x56, 0x77, 0xa5, 0x0a, 0x27, 0x71, 0xa6, 0x0a, 0x27, - 0x7a, 0x02, 0x56, 0x7b, 0x9d, 0x0a, 0x27, 0x89, 0x9e, 0x0a, 0x27, 0x91, + 0x27, 0x63, 0x02, 0x56, 0x79, 0xa5, 0x0a, 0x27, 0x71, 0xa6, 0x0a, 0x27, + 0x7a, 0x02, 0x56, 0x7d, 0x9d, 0x0a, 0x27, 0x89, 0x9e, 0x0a, 0x27, 0x91, 0x9f, 0x0a, 0x27, 0x99, 0xa0, 0x0a, 0x27, 0xa1, 0xa1, 0x0a, 0x27, 0xa9, - 0xa2, 0x0a, 0x27, 0xb3, 0x02, 0x56, 0x7f, 0xa3, 0x0a, 0x27, 0xc3, 0x02, - 0x56, 0x83, 0xa4, 0x0a, 0x27, 0xd1, 0xa5, 0x0a, 0x27, 0xd9, 0xa6, 0x0a, + 0xa2, 0x0a, 0x27, 0xb3, 0x02, 0x56, 0x81, 0xa3, 0x0a, 0x27, 0xc3, 0x02, + 0x56, 0x85, 0xa4, 0x0a, 0x27, 0xd1, 0xa5, 0x0a, 0x27, 0xd9, 0xa6, 0x0a, 0x27, 0xe0, 0x9d, 0x0a, 0x27, 0xe9, 0x9e, 0x0a, 0x27, 0xf1, 0x9f, 0x0a, 0x27, 0xf9, 0xa0, 0x0a, 0x28, 0x01, 0xa1, 0x0a, 0x28, 0x09, 0xa2, 0x0a, 0x28, 0x11, 0xa3, 0x0a, 0x28, 0x19, 0xa4, 0x0a, 0x28, 0x23, 0x02, 0x56, - 0x87, 0xa5, 0x0a, 0x28, 0x31, 0xa6, 0x0a, 0x28, 0x38, 0x9d, 0x0a, 0x28, + 0x89, 0xa5, 0x0a, 0x28, 0x31, 0xa6, 0x0a, 0x28, 0x38, 0x9d, 0x0a, 0x28, 0x41, 0x9e, 0x0a, 0x28, 0x49, 0x9f, 0x0a, 0x28, 0x51, 0xa0, 0x0a, 0x28, 0x59, 0xa1, 0x0a, 0x28, 0x61, 0xa2, 0x0a, 0x28, 0x69, 0xa3, 0x0a, 0x28, 0x71, 0xa4, 0x0a, 0x28, 0x79, 0xa5, 0x0a, 0x28, 0x81, 0xa6, 0x0a, 0x28, @@ -9933,7 +9934,7 @@ uint8_t UnicodeNameToCodepointIndex_[242216] = { 0x19, 0xa5, 0x0a, 0x29, 0x21, 0xa6, 0x0a, 0x29, 0x28, 0x9d, 0x0a, 0x29, 0x31, 0x9e, 0x0a, 0x29, 0x39, 0x9f, 0x0a, 0x29, 0x41, 0xa0, 0x0a, 0x29, 0x49, 0xa1, 0x0a, 0x29, 0x51, 0xa2, 0x0a, 0x29, 0x59, 0xa3, 0x0a, 0x29, - 0x61, 0xa4, 0x0a, 0x29, 0x6b, 0x02, 0x56, 0x8b, 0xa5, 0x0a, 0x29, 0x79, + 0x61, 0xa4, 0x0a, 0x29, 0x6b, 0x02, 0x56, 0x8d, 0xa5, 0x0a, 0x29, 0x79, 0xa6, 0x0a, 0x29, 0x80, 0x9d, 0x0a, 0x29, 0x89, 0x9e, 0x0a, 0x29, 0x91, 0x9f, 0x0a, 0x29, 0x99, 0xa0, 0x0a, 0x29, 0xa1, 0xa1, 0x0a, 0x29, 0xa9, 0xa2, 0x0a, 0x29, 0xb1, 0xa3, 0x0a, 0x29, 0xb9, 0xa4, 0x0a, 0x29, 0xc1, @@ -9941,24 +9942,24 @@ uint8_t UnicodeNameToCodepointIndex_[242216] = { 0x9e, 0x0a, 0x29, 0xe1, 0x9f, 0x0a, 0x29, 0xe9, 0xa0, 0x0a, 0x29, 0xf1, 0xa1, 0x0a, 0x29, 0xf9, 0xa2, 0x0a, 0x2a, 0x01, 0xa3, 0x0a, 0x2a, 0x09, 0xa4, 0x0a, 0x2a, 0x11, 0xa5, 0x0a, 0x2a, 0x19, 0xa6, 0x0a, 0x2a, 0x22, - 0x02, 0x56, 0x8f, 0x9d, 0x0a, 0x2a, 0x31, 0x9e, 0x0a, 0x2a, 0x39, 0x9f, + 0x02, 0x56, 0x91, 0x9d, 0x0a, 0x2a, 0x31, 0x9e, 0x0a, 0x2a, 0x39, 0x9f, 0x0a, 0x2a, 0x41, 0xa0, 0x0a, 0x2a, 0x49, 0xa1, 0x0a, 0x2a, 0x53, 0x02, - 0x56, 0x93, 0xa2, 0x0a, 0x2a, 0x61, 0xa3, 0x0a, 0x2a, 0x69, 0xa4, 0x0a, + 0x56, 0x95, 0xa2, 0x0a, 0x2a, 0x61, 0xa3, 0x0a, 0x2a, 0x69, 0xa4, 0x0a, 0x2a, 0x71, 0xa5, 0x0a, 0x2a, 0x79, 0xa6, 0x0a, 0x2a, 0x82, 0x02, 0x56, - 0x97, 0x9d, 0x0a, 0x2a, 0x91, 0x9e, 0x0a, 0x2a, 0x99, 0x9f, 0x0a, 0x2a, + 0x99, 0x9d, 0x0a, 0x2a, 0x91, 0x9e, 0x0a, 0x2a, 0x99, 0x9f, 0x0a, 0x2a, 0xa1, 0xa0, 0x0a, 0x2a, 0xa9, 0xa1, 0x0a, 0x2a, 0xb1, 0xa2, 0x0a, 0x2a, 0xb9, 0xa3, 0x0a, 0x2a, 0xc1, 0xa4, 0x0a, 0x2a, 0xc9, 0xa5, 0x0a, 0x2a, - 0xd1, 0xa6, 0x0a, 0x2a, 0xda, 0x02, 0x56, 0x9b, 0x9d, 0x0a, 0x2a, 0xe9, + 0xd1, 0xa6, 0x0a, 0x2a, 0xda, 0x02, 0x56, 0x9d, 0x9d, 0x0a, 0x2a, 0xe9, 0x9e, 0x0a, 0x2a, 0xf1, 0x9f, 0x0a, 0x2a, 0xf9, 0xa0, 0x0a, 0x2b, 0x01, 0xa1, 0x0a, 0x2b, 0x09, 0xa2, 0x0a, 0x2b, 0x11, 0xa3, 0x0a, 0x2b, 0x19, 0xa4, 0x0a, 0x2b, 0x21, 0xa5, 0x0a, 0x2b, 0x29, 0xa6, 0x0a, 0x2b, 0x30, 0x9d, 0x0a, 0x2b, 0x39, 0x9e, 0x0a, 0x2b, 0x41, 0x9f, 0x0a, 0x2b, 0x49, 0xa0, 0x0a, 0x2b, 0x51, 0xa1, 0x0a, 0x2b, 0x59, 0xa2, 0x0a, 0x2b, 0x61, 0xa3, 0x0a, 0x2b, 0x69, 0xa4, 0x0a, 0x2b, 0x71, 0xa5, 0x0a, 0x2b, 0x79, - 0xa6, 0x0a, 0x2b, 0x82, 0x02, 0x56, 0x9f, 0x9d, 0x0a, 0x2b, 0x91, 0x9e, - 0x0a, 0x2b, 0x99, 0x1f, 0xc2, 0x56, 0xa3, 0xa0, 0x0a, 0x2b, 0xb9, 0xa1, + 0xa6, 0x0a, 0x2b, 0x82, 0x02, 0x56, 0xa1, 0x9d, 0x0a, 0x2b, 0x91, 0x9e, + 0x0a, 0x2b, 0x99, 0x1f, 0xc2, 0x56, 0xa5, 0xa0, 0x0a, 0x2b, 0xb9, 0xa1, 0x0a, 0x2b, 0xc1, 0xa2, 0x0a, 0x2b, 0xc9, 0xa3, 0x0a, 0x2b, 0xd3, 0x02, - 0x56, 0xaf, 0xa4, 0x0a, 0x2b, 0xf1, 0xa5, 0x0a, 0x2b, 0xf9, 0xa6, 0x0a, + 0x56, 0xb1, 0xa4, 0x0a, 0x2b, 0xf1, 0xa5, 0x0a, 0x2b, 0xf9, 0xa6, 0x0a, 0x2c, 0x00, 0x9d, 0x0a, 0x2c, 0x09, 0x9e, 0x0a, 0x2c, 0x11, 0x9f, 0x0a, 0x2c, 0x19, 0xa0, 0x0a, 0x2c, 0x21, 0xa1, 0x0a, 0x2c, 0x29, 0xa2, 0x0a, 0x2c, 0x31, 0xa3, 0x0a, 0x2c, 0x39, 0xa4, 0x0a, 0x2c, 0x41, 0xa5, 0x0a, @@ -9966,25 +9967,25 @@ uint8_t UnicodeNameToCodepointIndex_[242216] = { 0x2c, 0x61, 0x9f, 0x0a, 0x2c, 0x69, 0xa0, 0x0a, 0x2c, 0x71, 0xa1, 0x0a, 0x2c, 0x79, 0xa2, 0x0a, 0x2c, 0x81, 0xa3, 0x0a, 0x2c, 0x89, 0xa4, 0x0a, 0x2c, 0x91, 0xa5, 0x0a, 0x2c, 0x99, 0xa6, 0x0a, 0x2c, 0xa2, 0x02, 0x56, - 0xbb, 0x9d, 0x0a, 0x2c, 0xb1, 0x9e, 0x0a, 0x2c, 0xb9, 0x9f, 0x0a, 0x2c, - 0xc1, 0xa0, 0x0a, 0x2c, 0xc9, 0xa1, 0x0a, 0x2c, 0xd3, 0x02, 0x56, 0xbf, + 0xbd, 0x9d, 0x0a, 0x2c, 0xb1, 0x9e, 0x0a, 0x2c, 0xb9, 0x9f, 0x0a, 0x2c, + 0xc1, 0xa0, 0x0a, 0x2c, 0xc9, 0xa1, 0x0a, 0x2c, 0xd3, 0x02, 0x56, 0xc1, 0xa2, 0x0a, 0x2c, 0xe1, 0xa3, 0x0a, 0x2c, 0xe9, 0xa4, 0x0a, 0x2c, 0xf1, - 0xa5, 0x0a, 0x2c, 0xfb, 0x02, 0x56, 0xc3, 0xa6, 0x0a, 0x2d, 0x08, 0x9d, - 0x0a, 0x2d, 0x11, 0x9e, 0x0a, 0x2d, 0x1b, 0x02, 0x56, 0xc7, 0x9f, 0x0a, + 0xa5, 0x0a, 0x2c, 0xfb, 0x02, 0x56, 0xc5, 0xa6, 0x0a, 0x2d, 0x08, 0x9d, + 0x0a, 0x2d, 0x11, 0x9e, 0x0a, 0x2d, 0x1b, 0x02, 0x56, 0xc9, 0x9f, 0x0a, 0x2d, 0x29, 0xa0, 0x0a, 0x2d, 0x31, 0xa1, 0x0a, 0x2d, 0x39, 0xa2, 0x0a, 0x2d, 0x41, 0xa3, 0x0a, 0x2d, 0x49, 0xa4, 0x0a, 0x2d, 0x51, 0xa5, 0x0a, 0x2d, 0x59, 0xa6, 0x0a, 0x2d, 0x60, 0x9d, 0x0a, 0x2d, 0x69, 0x9e, 0x0a, - 0x2d, 0x73, 0x02, 0x56, 0xcb, 0x9f, 0x0a, 0x2d, 0x81, 0x20, 0xc2, 0x56, - 0xcf, 0xa1, 0x0a, 0x2d, 0x99, 0xa2, 0x0a, 0x2d, 0xa1, 0xa3, 0x0a, 0x2d, - 0xab, 0x02, 0x56, 0xd9, 0xa4, 0x0a, 0x2d, 0xb9, 0xa5, 0x0a, 0x2d, 0xc1, + 0x2d, 0x73, 0x02, 0x56, 0xcd, 0x9f, 0x0a, 0x2d, 0x81, 0x20, 0xc2, 0x56, + 0xd1, 0xa1, 0x0a, 0x2d, 0x99, 0xa2, 0x0a, 0x2d, 0xa1, 0xa3, 0x0a, 0x2d, + 0xab, 0x02, 0x56, 0xdb, 0xa4, 0x0a, 0x2d, 0xb9, 0xa5, 0x0a, 0x2d, 0xc1, 0xa6, 0x0a, 0x2d, 0xc8, 0x9d, 0x0a, 0x2d, 0xd1, 0x9e, 0x0a, 0x2d, 0xd9, - 0x9f, 0x0a, 0x2d, 0xe1, 0xc7, 0xc8, 0x9b, 0x0a, 0x2d, 0xe9, 0xa1, 0x0a, + 0x9f, 0x0a, 0x2d, 0xe1, 0xc7, 0xc8, 0x0d, 0x0a, 0x2d, 0xe9, 0xa1, 0x0a, 0x2d, 0xf1, 0xa2, 0x0a, 0x2d, 0xf9, 0xa3, 0x0a, 0x2e, 0x01, 0xa4, 0x0a, 0x2e, 0x09, 0xa5, 0x0a, 0x2e, 0x11, 0xa6, 0x0a, 0x2e, 0x18, 0x9d, 0x0a, 0x2e, 0x21, 0x9e, 0x0a, 0x2e, 0x29, 0x9f, 0x0a, 0x2e, 0x31, 0xa0, 0x0a, 0x2e, 0x39, 0xa1, 0x0a, 0x2e, 0x41, 0xa2, 0x0a, 0x2e, 0x49, 0xa3, 0x0a, 0x2e, 0x51, 0xa4, 0x0a, 0x2e, 0x59, 0xa5, 0x0a, 0x2e, 0x61, 0xa6, 0x0a, - 0x2e, 0x68, 0x1d, 0xc2, 0x56, 0xdd, 0x9e, 0x0a, 0x2e, 0x81, 0x9f, 0x0a, + 0x2e, 0x68, 0x1d, 0xc2, 0x56, 0xdf, 0x9e, 0x0a, 0x2e, 0x81, 0x9f, 0x0a, 0x2e, 0x89, 0xa0, 0x0a, 0x2e, 0x91, 0xa1, 0x0a, 0x2e, 0x99, 0xa2, 0x0a, 0x2e, 0xa1, 0xa3, 0x0a, 0x2e, 0xa9, 0xa4, 0x0a, 0x2e, 0xb1, 0xa5, 0x0a, 0x2e, 0xb9, 0xa6, 0x0a, 0x2e, 0xc0, 0x9d, 0x0a, 0x2e, 0xc9, 0x9e, 0x0a, @@ -9998,9 +9999,9 @@ uint8_t UnicodeNameToCodepointIndex_[242216] = { 0x2f, 0x79, 0xa0, 0x0a, 0x2f, 0x81, 0xa1, 0x0a, 0x2f, 0x89, 0xa2, 0x0a, 0x2f, 0x91, 0xa3, 0x0a, 0x2f, 0x99, 0xa4, 0x0a, 0x2f, 0xa1, 0xa5, 0x0a, 0x2f, 0xa9, 0xa6, 0x0a, 0x2f, 0xb0, 0x9d, 0x0a, 0x2f, 0xbb, 0x02, 0x56, - 0xe9, 0x9e, 0x0a, 0x2f, 0xc9, 0x9f, 0x0a, 0x2f, 0xd1, 0xa0, 0x0a, 0x2f, + 0xeb, 0x9e, 0x0a, 0x2f, 0xc9, 0x9f, 0x0a, 0x2f, 0xd1, 0xa0, 0x0a, 0x2f, 0xd9, 0xa1, 0x0a, 0x2f, 0xe1, 0xa2, 0x0a, 0x2f, 0xe9, 0xa3, 0x0a, 0x2f, - 0xf1, 0xa4, 0x0a, 0x2f, 0xfb, 0x02, 0x56, 0xed, 0xa5, 0x0a, 0x30, 0x09, + 0xf1, 0xa4, 0x0a, 0x2f, 0xfb, 0x02, 0x56, 0xef, 0xa5, 0x0a, 0x30, 0x09, 0xa6, 0x0a, 0x30, 0x10, 0x9d, 0x0a, 0x30, 0x19, 0x9e, 0x0a, 0x30, 0x21, 0x9f, 0x0a, 0x30, 0x29, 0xa0, 0x0a, 0x30, 0x31, 0xa1, 0x0a, 0x30, 0x39, 0xa2, 0x0a, 0x30, 0x41, 0xa3, 0x0a, 0x30, 0x49, 0xa4, 0x0a, 0x30, 0x51, @@ -10023,11150 +10024,11153 @@ uint8_t UnicodeNameToCodepointIndex_[242216] = { 0xa6, 0x0a, 0x31, 0xd8, 0x9d, 0x0a, 0x31, 0xe1, 0x9e, 0x0a, 0x31, 0xe9, 0x9f, 0x0a, 0x31, 0xf1, 0xa0, 0x0a, 0x31, 0xf9, 0xa1, 0x0a, 0x32, 0x01, 0xa2, 0x0a, 0x32, 0x09, 0xa3, 0x0a, 0x32, 0x11, 0xa4, 0x0a, 0x32, 0x19, - 0xa5, 0x0a, 0x32, 0x21, 0xa6, 0x0a, 0x32, 0x28, 0xd1, 0x03, 0xf5, 0x01, - 0x5b, 0x79, 0xd4, 0x3e, 0x1a, 0x01, 0x5c, 0x61, 0xd5, 0x37, 0xe7, 0x01, - 0x5c, 0x69, 0xd3, 0x41, 0xf8, 0x01, 0x5c, 0x71, 0xd2, 0x4c, 0x3e, 0x01, - 0x5c, 0x78, 0xc8, 0x2d, 0xa6, 0x01, 0x1b, 0x81, 0xc9, 0x23, 0x30, 0x01, - 0x1b, 0x79, 0x05, 0xc2, 0x56, 0xf1, 0x06, 0xc2, 0x56, 0xfd, 0x42, 0x02, - 0x6a, 0xc2, 0x57, 0x10, 0xd0, 0x01, 0x37, 0x01, 0x1a, 0x41, 0x42, 0x00, - 0x58, 0xc2, 0x57, 0x1c, 0xcc, 0x06, 0xfb, 0x01, 0x1a, 0x21, 0xc9, 0x02, - 0xde, 0x01, 0x1a, 0x11, 0xc5, 0x02, 0xe2, 0x01, 0x1a, 0x09, 0xc3, 0xba, - 0x10, 0x01, 0x19, 0xd9, 0xc5, 0x03, 0x62, 0x01, 0x19, 0xc0, 0xc9, 0x1e, - 0x89, 0x01, 0x1b, 0x09, 0xc3, 0xba, 0x10, 0x01, 0x1a, 0xa9, 0xc7, 0x79, - 0xb4, 0x01, 0x1a, 0x88, 0xcb, 0x98, 0x45, 0x01, 0x1b, 0x89, 0xca, 0x9c, - 0x19, 0x01, 0x1b, 0x31, 0x45, 0x9c, 0x24, 0x42, 0x57, 0x28, 0xc5, 0x1f, - 0x01, 0x01, 0x1b, 0x59, 0xc9, 0x1e, 0x89, 0x01, 0x1b, 0x11, 0xc5, 0x02, - 0xa2, 0x01, 0x1a, 0x90, 0xc8, 0x50, 0x0d, 0x01, 0x1a, 0xc9, 0xc5, 0x02, - 0xa2, 0x01, 0x1a, 0x58, 0xc2, 0x00, 0x4d, 0x01, 0x1a, 0xf9, 0xc3, 0x02, - 0xa4, 0x01, 0x19, 0xe8, 0xc2, 0x01, 0x89, 0x01, 0x12, 0x2b, 0x02, 0x57, - 0x34, 0xcb, 0x25, 0x71, 0x01, 0x53, 0x80, 0xc2, 0x04, 0x30, 0x08, 0x59, - 0x99, 0x87, 0x08, 0x59, 0x88, 0xc2, 0x00, 0x29, 0x08, 0x59, 0x21, 0xc2, - 0x04, 0x30, 0x08, 0x59, 0x19, 0x87, 0x08, 0x59, 0x10, 0x87, 0x08, 0x58, - 0x38, 0x90, 0x08, 0x58, 0x29, 0x91, 0x08, 0x58, 0x18, 0xc7, 0x0d, 0x7f, - 0x08, 0x08, 0xc9, 0xc8, 0x4f, 0xa2, 0x08, 0x09, 0x10, 0xc3, 0x05, 0xdf, - 0x08, 0x08, 0x4b, 0x02, 0x57, 0x3a, 0xc4, 0x0d, 0x89, 0x08, 0x08, 0x92, - 0x02, 0x57, 0x3e, 0xc9, 0x4f, 0xa1, 0x08, 0x09, 0x58, 0xc4, 0x15, 0xa9, - 0x08, 0x08, 0x8b, 0x02, 0x57, 0x44, 0x91, 0x08, 0x08, 0x42, 0x02, 0x57, - 0x4a, 0xc2, 0x00, 0x29, 0x08, 0x08, 0x5b, 0x02, 0x57, 0x4e, 0xc3, 0x41, - 0xca, 0x08, 0x08, 0xa2, 0x02, 0x57, 0x52, 0xc2, 0x00, 0xd3, 0x08, 0x08, - 0x53, 0x02, 0x57, 0x58, 0xc3, 0x0d, 0x8a, 0x08, 0x08, 0x9a, 0x02, 0x57, - 0x5c, 0x00, 0xc2, 0x57, 0x62, 0xc2, 0x0d, 0x8b, 0x08, 0x08, 0xaa, 0x02, - 0x57, 0x6e, 0x00, 0xc2, 0x57, 0x74, 0xc2, 0x0d, 0x8b, 0x08, 0x08, 0xb2, - 0x02, 0x57, 0x80, 0xc7, 0x0d, 0x7f, 0x08, 0x09, 0x01, 0xc8, 0x4f, 0xa2, - 0x08, 0x09, 0x48, 0xc9, 0x4f, 0xa1, 0x08, 0x09, 0x90, 0xc7, 0x0d, 0x7f, - 0x08, 0x09, 0x09, 0xc8, 0x4f, 0xa2, 0x08, 0x09, 0x50, 0xc9, 0x4f, 0xa1, - 0x08, 0x09, 0x98, 0xcc, 0x15, 0x06, 0x08, 0x09, 0xc1, 0xcd, 0x81, 0x32, - 0x08, 0x09, 0xd8, 0xca, 0x03, 0x76, 0x01, 0x28, 0x03, 0x02, 0x57, 0x86, - 0x06, 0xc2, 0x57, 0x8c, 0xc2, 0x02, 0x6a, 0x01, 0x2b, 0xab, 0x02, 0x57, - 0x96, 0xc4, 0x00, 0xcd, 0x01, 0x2b, 0xa3, 0x02, 0x57, 0x9c, 0xc5, 0x00, - 0x47, 0x01, 0x2b, 0xb1, 0x44, 0x13, 0x02, 0xc2, 0x57, 0xa2, 0xc8, 0x00, - 0x29, 0x01, 0x28, 0x13, 0x02, 0x57, 0xae, 0x4f, 0x64, 0x74, 0xc2, 0x57, - 0xb4, 0x4c, 0x54, 0x00, 0x42, 0x57, 0xc0, 0x50, 0x60, 0x1f, 0xc2, 0x57, - 0xcc, 0xdd, 0x11, 0xfe, 0x01, 0x2a, 0x29, 0xdd, 0x11, 0x8a, 0x01, 0x2a, - 0x19, 0x50, 0x11, 0x8d, 0x42, 0x57, 0xde, 0x45, 0x00, 0x39, 0x42, 0x57, - 0xf0, 0xd0, 0x58, 0xbf, 0x01, 0x2b, 0xf0, 0xc2, 0x00, 0x6a, 0x01, 0x2b, - 0xdb, 0x02, 0x58, 0x00, 0x4a, 0xa9, 0x70, 0x42, 0x58, 0x06, 0x45, 0x00, - 0x39, 0x42, 0x58, 0x12, 0xc8, 0x00, 0x29, 0x01, 0x28, 0x59, 0xca, 0x03, - 0x76, 0x01, 0x28, 0x48, 0xc8, 0x00, 0x29, 0x01, 0x28, 0x39, 0xca, 0x03, - 0x76, 0x01, 0x28, 0x28, 0xc8, 0x00, 0x29, 0x01, 0x2a, 0x8b, 0x02, 0x58, - 0x24, 0x47, 0x54, 0x55, 0xc2, 0x58, 0x2a, 0x49, 0x45, 0xd4, 0xc2, 0x58, - 0x3c, 0xca, 0x03, 0x76, 0x01, 0x2a, 0x80, 0x4b, 0x9c, 0x2e, 0xc2, 0x58, - 0x4e, 0x4b, 0x93, 0x54, 0xc2, 0x58, 0x60, 0x4a, 0x60, 0x1f, 0xc2, 0x58, - 0x72, 0x4a, 0x11, 0x8d, 0x42, 0x58, 0x8a, 0xd1, 0x53, 0x56, 0x01, 0x2b, - 0x59, 0xcb, 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0x49, 0xc3, 0xec, 0x64, + 0x0e, 0x8b, 0x41, 0xc3, 0xec, 0x76, 0x0e, 0x8b, 0x38, 0x12, 0xc3, 0xb0, + 0xb7, 0xc4, 0xe9, 0xf2, 0x00, 0xfb, 0x63, 0x03, 0xb0, 0xc6, 0xc5, 0x26, + 0xfc, 0x00, 0xfb, 0x52, 0x03, 0xb0, 0xcc, 0xca, 0x90, 0xad, 0x00, 0xfb, + 0x7b, 0x03, 0xb0, 0xd2, 0xcd, 0x45, 0x44, 0x00, 0xfd, 0x48, 0xd3, 0x45, + 0x3e, 0x00, 0xfd, 0x68, 0xd3, 0x45, 0x3e, 0x00, 0xfd, 0x58, 0x12, 0xc3, + 0xb0, 0xd8, 0xc4, 0xe9, 0xf2, 0x00, 0xf9, 0x63, 0x03, 0xb0, 0xe7, 0xc5, + 0x26, 0xfc, 0x00, 0xf9, 0x52, 0x03, 0xb0, 0xed, 0xca, 0x90, 0xad, 0x00, + 0xf9, 0x7b, 0x03, 0xb0, 0xf3, 0xcd, 0x45, 0x44, 0x00, 0xfc, 0xc8, 0xd3, + 0x45, 0x3e, 0x00, 0xfc, 0xe8, 0xd3, 0x45, 0x3e, 0x00, 0xfc, 0xd8, 0x12, + 0xc3, 0xb0, 0xf9, 0xc4, 0xe9, 0xf2, 0x00, 0xf8, 0x63, 0x03, 0xb1, 0x08, + 0xc5, 0x26, 0xfc, 0x00, 0xf8, 0x52, 0x03, 0xb1, 0x0e, 0xca, 0x90, 0xad, + 0x00, 0xf8, 0x7b, 0x03, 0xb1, 0x14, 0xcd, 0x45, 0x44, 0x00, 0xfc, 0x48, + 0xd3, 0x45, 0x3e, 0x00, 0xfc, 0x68, 0xd3, 0x45, 0x3e, 0x00, 0xfc, 0x58, + 0xcb, 0x90, 0xac, 0x00, 0xfb, 0x33, 0x03, 0xb1, 0x1a, 0xc4, 0xe9, 0xf2, + 0x00, 0xfb, 0x23, 0x03, 0xb1, 0x20, 0xc5, 0x26, 0xfc, 0x00, 0xfb, 0x13, + 0x03, 0xb1, 0x26, 0xcd, 0x4d, 0xe4, 0x00, 0xfd, 0x00, 0xd2, 0x4d, 0xdf, + 0x00, 0xfd, 0x38, 0xd2, 0x4d, 0xdf, 0x00, 0xfd, 0x28, 0xd2, 0x4d, 0xdf, + 0x00, 0xfd, 0x18, 0xcb, 0x90, 0xac, 0x00, 0xf9, 0x33, 0x03, 0xb1, 0x2c, + 0xc4, 0xe9, 0xf2, 0x00, 0xf9, 0x23, 0x03, 0xb1, 0x32, 0xc5, 0x26, 0xfc, + 0x00, 0xf9, 0x13, 0x03, 0xb1, 0x38, 0xcd, 0x4d, 0xe4, 0x00, 0xfc, 0x80, + 0xd2, 0x4d, 0xdf, 0x00, 0xfc, 0xb8, 0xd2, 0x4d, 0xdf, 0x00, 0xfc, 0xa8, + 0xd2, 0x4d, 0xdf, 0x00, 0xfc, 0x98, 0xcb, 0x90, 0xac, 0x00, 0xf8, 0x33, + 0x03, 0xb1, 0x3e, 0xc4, 0xe9, 0xf2, 0x00, 0xf8, 0x23, 0x03, 0xb1, 0x44, + 0xc5, 0x26, 0xfc, 0x00, 0xf8, 0x13, 0x03, 0xb1, 0x4a, 0xcd, 0x4d, 0xe4, + 0x00, 0xfc, 0x00, 0xd2, 0x4d, 0xdf, 0x00, 0xfc, 0x38, 0xd2, 0x4d, 0xdf, + 0x00, 0xfc, 0x28, 0xd2, 0x4d, 0xdf, 0x00, 0xfc, 0x18, 0xd0, 0x5e, 0x54, + 0x0e, 0x7d, 0xd9, 0xd0, 0x2b, 0xd5, 0x0e, 0x7d, 0xc0, 0xcb, 0x75, 0xb3, + 0x0e, 0xc1, 0xe0, 0x14, 0xc3, 0xb1, 0x50, 0xce, 0x75, 0xb0, 0x0e, 0xc1, + 0xb8, 0xc6, 0x5b, 0x2e, 0x0e, 0xc2, 0x19, 0xc2, 0x01, 0x6a, 0x0e, 0xc1, + 0x88, 0x46, 0x0d, 0xb9, 0xc3, 0xb1, 0x5c, 0xc9, 0xb1, 0x1d, 0x0e, 0xc7, + 0x11, 0x46, 0x0d, 0xbf, 0x43, 0xb1, 0x68, 0x44, 0x0d, 0x7d, 0xc3, 0xb1, + 0x7a, 0xc8, 0x14, 0x9a, 0x0e, 0xc0, 0xaa, 0x03, 0xb1, 0x89, 0xc3, 0x00, + 0xaf, 0x0e, 0xc4, 0x33, 0x03, 0xb1, 0x8d, 0xce, 0x3b, 0x01, 0x0e, 0xc0, + 0x88, 0x00, 0x43, 0xb1, 0x91, 0xd2, 0x4f, 0xa1, 0x0e, 0xc1, 0x18, 0xcf, + 0x69, 0x93, 0x0e, 0xc1, 0x08, 0xcb, 0x4f, 0xa8, 0x0e, 0xc1, 0x30, 0xc8, + 0xc0, 0x6d, 0x0e, 0xc2, 0xc9, 0xca, 0x4f, 0xa9, 0x0e, 0xc2, 0xc0, 0xc4, + 0x00, 0xb4, 0x0e, 0xc7, 0x89, 0xc3, 0x01, 0x27, 0x0e, 0xc6, 0xe8, 0xc7, + 0x14, 0x91, 0x0e, 0xc5, 0x51, 0xc2, 0x00, 0x2e, 0x0e, 0xc0, 0xd8, 0xc5, + 0x09, 0xa9, 0x00, 0x44, 0x09, 0xc9, 0x49, 0xc2, 0x00, 0x43, 0xb8, 0xc5, + 0x00, 0xd4, 0x00, 0x43, 0xc9, 0xc5, 0x03, 0x98, 0x00, 0x43, 0xb0, 0xc9, + 0xae, 0xb0, 0x00, 0x44, 0x01, 0xc9, 0x17, 0x41, 0x00, 0x43, 0xe8, 0xc9, + 0xae, 0xb0, 0x00, 0x43, 0xf1, 0xc9, 0x17, 0x41, 0x00, 0x43, 0xd8, 0xca, + 0x2b, 0x10, 0x07, 0xf4, 0x41, 0xcd, 0x00, 0x7a, 0x07, 0xf4, 0x38, 0xcd, + 0x00, 0x7a, 0x07, 0xf4, 0x19, 0xca, 0x2b, 0x10, 0x07, 0xf4, 0x20, 0xca, + 0x2b, 0x10, 0x07, 0xdd, 0x89, 0xcd, 0x00, 0x7a, 0x07, 0xdd, 0x80, 0xca, + 0x90, 0xad, 0x00, 0xfb, 0x73, 0x03, 0xb1, 0xa8, 0xcd, 0x45, 0x44, 0x00, + 0xfd, 0x40, 0xd3, 0x45, 0x3e, 0x00, 0xfd, 0x60, 0xd3, 0x45, 0x3e, 0x00, + 0xfd, 0x50, 0xd3, 0x45, 0x3e, 0x00, 0xfd, 0x78, 0xca, 0x90, 0xad, 0x00, + 0xf9, 0x73, 0x03, 0xb1, 0xae, 0xcd, 0x45, 0x44, 0x00, 0xfc, 0xc0, 0xd3, + 0x45, 0x3e, 0x00, 0xfc, 0xe0, 0xd3, 0x45, 0x3e, 0x00, 0xfc, 0xd0, 0xd3, + 0x45, 0x3e, 0x00, 0xfc, 0xf8, 0xca, 0x90, 0xad, 0x00, 0xf8, 0x73, 0x03, + 0xb1, 0xb4, 0xcd, 0x45, 0x44, 0x00, 0xfc, 0x40, 0xd3, 0x45, 0x3e, 0x00, + 0xfc, 0x60, 0xd3, 0x45, 0x3e, 0x00, 0xfc, 0x50, 0xd3, 0x45, 0x3e, 0x00, + 0xfc, 0x78, 0xd2, 0x4d, 0xdf, 0x00, 0xfd, 0x30, 0xd2, 0x4d, 0xdf, 0x00, + 0xfd, 0x20, 0xd2, 0x4d, 0xdf, 0x00, 0xfd, 0x10, 0xd2, 0x4d, 0xdf, 0x00, + 0xfc, 0xb0, 0xd2, 0x4d, 0xdf, 0x00, 0xfc, 0xa0, 0xd2, 0x4d, 0xdf, 0x00, + 0xfc, 0x90, 0xd2, 0x4d, 0xdf, 0x00, 0xfc, 0x30, 0xd2, 0x4d, 0xdf, 0x00, + 0xfc, 0x20, 0xd2, 0x4d, 0xdf, 0x00, 0xfc, 0x10, 0x49, 0x0d, 0xc8, 0xc3, + 0xb1, 0xba, 0xc5, 0xc3, 0x38, 0x0e, 0xc7, 0x38, 0xc5, 0x5b, 0x2e, 0x0e, + 0xc7, 0x19, 0xc4, 0x16, 0xf5, 0x0e, 0xc7, 0x08, 0xc4, 0x16, 0xf5, 0x0e, + 0xc7, 0x01, 0xc9, 0x14, 0x99, 0x0e, 0xc6, 0xf9, 0xc8, 0x20, 0x9c, 0x0e, + 0xc6, 0xf0, 0xc7, 0x14, 0x91, 0x0e, 0xc5, 0x49, 0xc2, 0x00, 0x2e, 0x0e, + 0xc0, 0xd2, 0x03, 0xb1, 0xc6, 0x00, 0x43, 0xb1, 0xcc, 0x00, 0x43, 0xb1, + 0xf0, 0xc6, 0xce, 0xa4, 0x0e, 0xc1, 0xfb, 0x03, 0xb1, 0xfc, 0x05, 0xc3, + 0xb2, 0x02, 0x0a, 0xc3, 0xb2, 0x14, 0xc4, 0x16, 0xf5, 0x0e, 0xc1, 0x10, + 0xd3, 0x45, 0x3e, 0x00, 0xfd, 0x70, 0xd3, 0x45, 0x3e, 0x00, 0xfc, 0xf0, + 0xd3, 0x45, 0x3e, 0x00, 0xfc, 0x70, 0xc5, 0x18, 0x48, 0x0e, 0xc7, 0x51, + 0xc6, 0x0d, 0xd1, 0x0e, 0xc7, 0x40, 0xcb, 0x4f, 0xa8, 0x0e, 0xc1, 0x98, + 0xc6, 0xd7, 0x41, 0x0e, 0xc0, 0xc3, 0x03, 0xb2, 0x20, 0x46, 0x0d, 0xbf, + 0xc3, 0xb2, 0x26, 0xc6, 0x5b, 0x2e, 0x0e, 0xc0, 0xcb, 0x03, 0xb2, 0x35, + 0xcb, 0x96, 0xd1, 0x0e, 0xc0, 0xb9, 0xca, 0xa1, 0x1e, 0x0e, 0xc0, 0xb0, + 0xc9, 0x14, 0x99, 0x0e, 0xc4, 0x61, 0xc4, 0x16, 0xf5, 0x0e, 0xc4, 0x58, + 0xc4, 0x0d, 0x06, 0x0e, 0xc1, 0xf0, 0xcf, 0x68, 0xa3, 0x0e, 0xc1, 0xe9, + 0xc6, 0x1f, 0xa3, 0x0e, 0xc1, 0x49, 0xc5, 0x70, 0x70, 0x0e, 0xc1, 0x40, + 0xc5, 0x5b, 0x2f, 0x0e, 0xc1, 0x59, 0xc5, 0x63, 0x22, 0x0e, 0xc1, 0x50, + 0xce, 0x28, 0xcd, 0x0e, 0xc1, 0xa8, 0xc7, 0x28, 0xd4, 0x0e, 0xc1, 0xa1, + 0xc4, 0x0d, 0xd3, 0x0e, 0xc1, 0x6a, 0x03, 0xb2, 0x3b, 0xcb, 0x4f, 0xa8, + 0x0e, 0xc1, 0x90, 0x00, 0x43, 0xb2, 0x3f, 0xc4, 0x16, 0xf5, 0x0e, 0xc1, + 0x79, 0xc9, 0x14, 0x99, 0x0e, 0xc1, 0x70, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0}; const uint8_t *UnicodeNameToCodepointIndex = UnicodeNameToCodepointIndex_; -const std::size_t UnicodeNameToCodepointIndexSize = 242216; +const std::size_t UnicodeNameToCodepointIndexSize = 242258; const std::size_t UnicodeNameToCodepointLargestNameSize = 74; } // namespace unicode diff --git a/llvm/lib/Support/Unix/Program.inc b/llvm/lib/Support/Unix/Program.inc index 260719b2b58..5d9757bcc51 100644 --- a/llvm/lib/Support/Unix/Program.inc +++ b/llvm/lib/Support/Unix/Program.inc @@ -91,7 +91,7 @@ ErrorOr sys::findProgramByName(StringRef Name, SmallString<128> FilePath(Path); sys::path::append(FilePath, Name); if (sys::fs::can_execute(FilePath.c_str())) - return std::string(FilePath.str()); // Found the executable! + return std::string(FilePath); // Found the executable! } return errc::no_such_file_or_directory; } diff --git a/llvm/lib/Support/VersionTuple.cpp b/llvm/lib/Support/VersionTuple.cpp index c0e007215a5..a4224f23b2f 100644 --- a/llvm/lib/Support/VersionTuple.cpp +++ b/llvm/lib/Support/VersionTuple.cpp @@ -85,9 +85,8 @@ bool VersionTuple::tryParse(StringRef input) { } // If we're not done, parse the micro version, \.[0-9]+ - if (input[0] != '.') + if (!input.consume_front(".")) return true; - input = input.substr(1); if (parseInt(input, micro)) return true; @@ -97,9 +96,8 @@ bool VersionTuple::tryParse(StringRef input) { } // If we're not done, parse the micro version, \.[0-9]+ - if (input[0] != '.') + if (!input.consume_front(".")) return true; - input = input.substr(1); if (parseInt(input, build)) return true; diff --git a/llvm/lib/Support/VirtualFileSystem.cpp b/llvm/lib/Support/VirtualFileSystem.cpp index 367e794d38f..c43b70e239e 100644 --- a/llvm/lib/Support/VirtualFileSystem.cpp +++ b/llvm/lib/Support/VirtualFileSystem.cpp @@ -325,14 +325,14 @@ RealFileSystem::openFileForRead(const Twine &Name) { llvm::ErrorOr RealFileSystem::getCurrentWorkingDirectory() const { if (WD && *WD) - return std::string(WD->get().Specified.str()); + return std::string(WD->get().Specified); if (WD) return WD->getError(); SmallString<128> Dir; if (std::error_code EC = llvm::sys::fs::current_path(Dir)) return EC; - return std::string(Dir.str()); + return std::string(Dir); } std::error_code RealFileSystem::setCurrentWorkingDirectory(const Twine &Path) { @@ -1091,7 +1091,7 @@ class InMemoryFileSystem::DirIterator : public llvm::vfs::detail::DirIterImpl { } break; } - CurrentEntry = directory_entry(std::string(Path.str()), Type); + CurrentEntry = directory_entry(std::string(Path), Type); } else { // When we're at the end, make CurrentEntry invalid and DirIterImpl will // do the rest. @@ -1146,7 +1146,7 @@ std::error_code InMemoryFileSystem::setCurrentWorkingDirectory(const Twine &P) { llvm::sys::path::remove_dots(Path, /*remove_dot_dot=*/true); if (!Path.empty()) - WorkingDirectory = std::string(Path.str()); + WorkingDirectory = std::string(Path); return {}; } @@ -1252,7 +1252,7 @@ class llvm::vfs::RedirectingFSDirIterImpl Type = sys::fs::file_type::regular_file; break; } - CurrentEntry = directory_entry(std::string(PathStr.str()), Type); + CurrentEntry = directory_entry(std::string(PathStr), Type); } else { CurrentEntry = directory_entry(); } @@ -1328,7 +1328,7 @@ RedirectingFileSystem::setCurrentWorkingDirectory(const Twine &Path) { Path.toVector(AbsolutePath); if (std::error_code EC = makeAbsolute(AbsolutePath)) return EC; - WorkingDirectory = std::string(AbsolutePath.str()); + WorkingDirectory = std::string(AbsolutePath); return {}; } diff --git a/llvm/lib/Support/Windows/Path.inc b/llvm/lib/Support/Windows/Path.inc index 2bf68b7972e..3e4c1f74161 100644 --- a/llvm/lib/Support/Windows/Path.inc +++ b/llvm/lib/Support/Windows/Path.inc @@ -777,14 +777,16 @@ std::error_code status(const Twine &path, file_status &result, bool Follow) { if (std::error_code ec = widenPath(path8, path_utf16)) return ec; - DWORD attr = ::GetFileAttributesW(path_utf16.begin()); - if (attr == INVALID_FILE_ATTRIBUTES) - return getStatus(INVALID_HANDLE_VALUE, result); - DWORD Flags = FILE_FLAG_BACKUP_SEMANTICS; - // Handle reparse points. - if (!Follow && (attr & FILE_ATTRIBUTE_REPARSE_POINT)) - Flags |= FILE_FLAG_OPEN_REPARSE_POINT; + if (!Follow) { + DWORD attr = ::GetFileAttributesW(path_utf16.begin()); + if (attr == INVALID_FILE_ATTRIBUTES) + return getStatus(INVALID_HANDLE_VALUE, result); + + // Handle reparse points. + if (attr & FILE_ATTRIBUTE_REPARSE_POINT) + Flags |= FILE_FLAG_OPEN_REPARSE_POINT; + } ScopedFileHandle h( ::CreateFileW(path_utf16.begin(), 0, // Attributes only. @@ -959,7 +961,8 @@ void mapped_file_region::unmapImpl() { ::UnmapViewOfFile(Mapping); - if (Mode == mapmode::readwrite && Exe && hasFlushBufferKernelBug()) { + if (Mode == mapmode::readwrite) { + bool DoFlush = Exe && hasFlushBufferKernelBug(); // There is a Windows kernel bug, the exact trigger conditions of which // are not well understood. When triggered, dirty pages are not properly // flushed and subsequent process's attempts to read a file can return @@ -967,7 +970,27 @@ void mapped_file_region::unmapImpl() { // sufficient to ensure that this bug is not triggered. // The bug only occurs when writing an executable and executing it right // after, under high I/O pressure. - ::FlushFileBuffers(FileHandle); + if (!DoFlush) { + // Separately, on VirtualBox Shared Folder mounts, writes via memory + // maps always end up unflushed (regardless of version of Windows), + // unless flushed with this explicit call, if they are renamed with + // SetFileInformationByHandle(FileRenameInfo) before closing the output + // handle. + // + // As the flushing is quite expensive, use a heuristic to limit the + // cases where we do the flushing. Only do the flushing if we aren't + // sure we are on a local file system. + bool IsLocal = false; + SmallVector FinalPath; + if (!realPathFromHandle(FileHandle, FinalPath)) { + // Not checking the return value here - if the check fails, assume the + // file isn't local. + is_local_internal(FinalPath, IsLocal); + } + DoFlush = !IsLocal; + } + if (DoFlush) + ::FlushFileBuffers(FileHandle); } ::CloseHandle(FileHandle); diff --git a/llvm/lib/Target/AArch64/AArch64.h b/llvm/lib/Target/AArch64/AArch64.h index d20ef63a72e..f7d81f42ef5 100644 --- a/llvm/lib/Target/AArch64/AArch64.h +++ b/llvm/lib/Target/AArch64/AArch64.h @@ -71,6 +71,7 @@ FunctionPass *createAArch64PostSelectOptimize(); FunctionPass *createAArch64StackTaggingPass(bool IsOptNone); FunctionPass *createAArch64StackTaggingPreRAPass(); ModulePass *createAArch64GlobalsTaggingPass(); +ModulePass *createAArch64Arm64ECCallLoweringPass(); void initializeAArch64A53Fix835769Pass(PassRegistry&); void initializeAArch64A57FPLoadBalancingPass(PassRegistry&); @@ -109,6 +110,7 @@ void initializeFalkorMarkStridedAccessesLegacyPass(PassRegistry&); void initializeLDTLSCleanupPass(PassRegistry&); void initializeSMEABIPass(PassRegistry &); void initializeSVEIntrinsicOptsPass(PassRegistry &); +void initializeAArch64Arm64ECCallLoweringPass(PassRegistry &); } // end namespace llvm #endif diff --git a/llvm/lib/Target/AArch64/AArch64.td b/llvm/lib/Target/AArch64/AArch64.td index d5e8ed101d1..36700f73df4 100644 --- a/llvm/lib/Target/AArch64/AArch64.td +++ b/llvm/lib/Target/AArch64/AArch64.td @@ -1520,7 +1520,8 @@ def ProcessorFeatures { FeaturePAuth, FeaturePerfMon]; list TSV110 = [HasV8_2aOps, FeatureCrypto, FeatureFPARMv8, FeatureNEON, FeaturePerfMon, FeatureSPE, - FeatureFullFP16, FeatureFP16FML, FeatureDotProd]; + FeatureFullFP16, FeatureFP16FML, FeatureDotProd, + FeatureJS, FeatureComplxNum]; list Ampere1 = [HasV8_6aOps, FeatureNEON, FeaturePerfMon, FeatureSSBS, FeatureRandGen, FeatureSB, FeatureSHA2, FeatureSHA3, FeatureAES]; diff --git a/llvm/lib/Target/AArch64/AArch64Arm64ECCallLowering.cpp b/llvm/lib/Target/AArch64/AArch64Arm64ECCallLowering.cpp new file mode 100644 index 00000000000..11248bb7aef --- /dev/null +++ b/llvm/lib/Target/AArch64/AArch64Arm64ECCallLowering.cpp @@ -0,0 +1,769 @@ +//===-- AArch64Arm64ECCallLowering.cpp - Lower Arm64EC calls ----*- C++ -*-===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// +/// +/// \file +/// This file contains the IR transform to lower external or indirect calls for +/// the ARM64EC calling convention. Such calls must go through the runtime, so +/// we can translate the calling convention for calls into the emulator. +/// +/// This subsumes Control Flow Guard handling. +/// +//===----------------------------------------------------------------------===// + +#include "AArch64.h" +#include "llvm/ADT/SetVector.h" +#include "llvm/ADT/SmallString.h" +#include "llvm/ADT/SmallVector.h" +#include "llvm/ADT/Statistic.h" +#include "llvm/IR/CallingConv.h" +#include "llvm/IR/IRBuilder.h" +#include "llvm/IR/Instruction.h" +#include "llvm/InitializePasses.h" +#include "llvm/Pass.h" +#include "llvm/Support/CommandLine.h" +#include "llvm/TargetParser/Triple.h" + +using namespace llvm; + +using OperandBundleDef = OperandBundleDefT; + +#define DEBUG_TYPE "arm64eccalllowering" + +STATISTIC(Arm64ECCallsLowered, "Number of Arm64EC calls lowered"); + +static cl::opt LowerDirectToIndirect("arm64ec-lower-direct-to-indirect", + cl::Hidden, cl::init(true)); +static cl::opt GenerateThunks("arm64ec-generate-thunks", cl::Hidden, + cl::init(true)); + +namespace { + +class AArch64Arm64ECCallLowering : public ModulePass { +public: + static char ID; + AArch64Arm64ECCallLowering() : ModulePass(ID) { + initializeAArch64Arm64ECCallLoweringPass(*PassRegistry::getPassRegistry()); + } + + Function *buildExitThunk(FunctionType *FnTy, AttributeList Attrs); + Function *buildEntryThunk(Function *F); + void lowerCall(CallBase *CB); + Function *buildGuestExitThunk(Function *F); + bool processFunction(Function &F, SetVector &DirectCalledFns); + bool runOnModule(Module &M) override; + +private: + int cfguard_module_flag = 0; + FunctionType *GuardFnType = nullptr; + PointerType *GuardFnPtrType = nullptr; + Constant *GuardFnCFGlobal = nullptr; + Constant *GuardFnGlobal = nullptr; + Module *M = nullptr; + + Type *PtrTy; + Type *I64Ty; + Type *VoidTy; + + void getThunkType(FunctionType *FT, AttributeList AttrList, bool EntryThunk, + raw_ostream &Out, FunctionType *&Arm64Ty, + FunctionType *&X64Ty); + void getThunkRetType(FunctionType *FT, AttributeList AttrList, + raw_ostream &Out, Type *&Arm64RetTy, Type *&X64RetTy, + SmallVectorImpl &Arm64ArgTypes, + SmallVectorImpl &X64ArgTypes, bool &HasSretPtr); + void getThunkArgTypes(FunctionType *FT, AttributeList AttrList, + raw_ostream &Out, + SmallVectorImpl &Arm64ArgTypes, + SmallVectorImpl &X64ArgTypes, bool HasSretPtr); + void canonicalizeThunkType(Type *T, Align Alignment, bool Ret, + uint64_t ArgSizeBytes, raw_ostream &Out, + Type *&Arm64Ty, Type *&X64Ty); +}; + +} // end anonymous namespace + +void AArch64Arm64ECCallLowering::getThunkType(FunctionType *FT, + AttributeList AttrList, + bool EntryThunk, raw_ostream &Out, + FunctionType *&Arm64Ty, + FunctionType *&X64Ty) { + Out << (EntryThunk ? "$ientry_thunk$cdecl$" : "$iexit_thunk$cdecl$"); + + Type *Arm64RetTy; + Type *X64RetTy; + + SmallVector Arm64ArgTypes; + SmallVector X64ArgTypes; + + // The first argument to a thunk is the called function, stored in x9. + // For exit thunks, we pass the called function down to the emulator; + // for entry thunks, we just call the Arm64 function directly. + if (!EntryThunk) + Arm64ArgTypes.push_back(PtrTy); + X64ArgTypes.push_back(PtrTy); + + bool HasSretPtr = false; + getThunkRetType(FT, AttrList, Out, Arm64RetTy, X64RetTy, Arm64ArgTypes, + X64ArgTypes, HasSretPtr); + + getThunkArgTypes(FT, AttrList, Out, Arm64ArgTypes, X64ArgTypes, HasSretPtr); + + Arm64Ty = FunctionType::get(Arm64RetTy, Arm64ArgTypes, false); + X64Ty = FunctionType::get(X64RetTy, X64ArgTypes, false); +} + +void AArch64Arm64ECCallLowering::getThunkArgTypes( + FunctionType *FT, AttributeList AttrList, raw_ostream &Out, + SmallVectorImpl &Arm64ArgTypes, + SmallVectorImpl &X64ArgTypes, bool HasSretPtr) { + + Out << "$"; + if (FT->isVarArg()) { + // We treat the variadic function's thunk as a normal function + // with the following type on the ARM side: + // rettype exitthunk( + // ptr x9, ptr x0, i64 x1, i64 x2, i64 x3, ptr x4, i64 x5) + // + // that can coverage all types of variadic function. + // x9 is similar to normal exit thunk, store the called function. + // x0-x3 is the arguments be stored in registers. + // x4 is the address of the arguments on the stack. + // x5 is the size of the arguments on the stack. + // + // On the x64 side, it's the same except that x5 isn't set. + // + // If both the ARM and X64 sides are sret, there are only three + // arguments in registers. + // + // If the X64 side is sret, but the ARM side isn't, we pass an extra value + // to/from the X64 side, and let SelectionDAG transform it into a memory + // location. + Out << "varargs"; + + // x0-x3 + for (int i = HasSretPtr ? 1 : 0; i < 4; i++) { + Arm64ArgTypes.push_back(I64Ty); + X64ArgTypes.push_back(I64Ty); + } + + // x4 + Arm64ArgTypes.push_back(PtrTy); + X64ArgTypes.push_back(PtrTy); + // x5 + Arm64ArgTypes.push_back(I64Ty); + // FIXME: x5 isn't actually passed/used by the x64 side; revisit once we + // have proper isel for varargs + X64ArgTypes.push_back(I64Ty); + return; + } + + unsigned I = 0; + if (HasSretPtr) + I++; + + if (I == FT->getNumParams()) { + Out << "v"; + return; + } + + for (unsigned E = FT->getNumParams(); I != E; ++I) { + Align ParamAlign = AttrList.getParamAlignment(I).valueOrOne(); +#if 0 + // FIXME: Need more information about argument size; see + // https://reviews.llvm.org/D132926 + uint64_t ArgSizeBytes = AttrList.getParamArm64ECArgSizeBytes(I); +#else + uint64_t ArgSizeBytes = 0; +#endif + Type *Arm64Ty, *X64Ty; + canonicalizeThunkType(FT->getParamType(I), ParamAlign, + /*Ret*/ false, ArgSizeBytes, Out, Arm64Ty, X64Ty); + Arm64ArgTypes.push_back(Arm64Ty); + X64ArgTypes.push_back(X64Ty); + } +} + +void AArch64Arm64ECCallLowering::getThunkRetType( + FunctionType *FT, AttributeList AttrList, raw_ostream &Out, + Type *&Arm64RetTy, Type *&X64RetTy, SmallVectorImpl &Arm64ArgTypes, + SmallVectorImpl &X64ArgTypes, bool &HasSretPtr) { + Type *T = FT->getReturnType(); +#if 0 + // FIXME: Need more information about argument size; see + // https://reviews.llvm.org/D132926 + uint64_t ArgSizeBytes = AttrList.getRetArm64ECArgSizeBytes(); +#else + int64_t ArgSizeBytes = 0; +#endif + if (T->isVoidTy()) { + if (FT->getNumParams()) { + auto SRetAttr = AttrList.getParamAttr(0, Attribute::StructRet); + auto InRegAttr = AttrList.getParamAttr(0, Attribute::InReg); + if (SRetAttr.isValid() && InRegAttr.isValid()) { + // sret+inreg indicates a call that returns a C++ class value. This is + // actually equivalent to just passing and returning a void* pointer + // as the first argument. Translate it that way, instead of trying + // to model "inreg" in the thunk's calling convention, to simplify + // the rest of the code. + Out << "i8"; + Arm64RetTy = I64Ty; + X64RetTy = I64Ty; + return; + } + if (SRetAttr.isValid()) { + // FIXME: Sanity-check the sret type; if it's an integer or pointer, + // we'll get screwy mangling/codegen. + // FIXME: For large struct types, mangle as an integer argument and + // integer return, so we can reuse more thunks, instead of "m" syntax. + // (MSVC mangles this case as an integer return with no argument, but + // that's a miscompile.) + Type *SRetType = SRetAttr.getValueAsType(); + Align SRetAlign = AttrList.getParamAlignment(0).valueOrOne(); + Type *Arm64Ty, *X64Ty; + canonicalizeThunkType(SRetType, SRetAlign, /*Ret*/ true, ArgSizeBytes, + Out, Arm64Ty, X64Ty); + Arm64RetTy = VoidTy; + X64RetTy = VoidTy; + Arm64ArgTypes.push_back(FT->getParamType(0)); + X64ArgTypes.push_back(FT->getParamType(0)); + HasSretPtr = true; + return; + } + } + + Out << "v"; + Arm64RetTy = VoidTy; + X64RetTy = VoidTy; + return; + } + + canonicalizeThunkType(T, Align(), /*Ret*/ true, ArgSizeBytes, Out, Arm64RetTy, + X64RetTy); + if (X64RetTy->isPointerTy()) { + // If the X64 type is canonicalized to a pointer, that means it's + // passed/returned indirectly. For a return value, that means it's an + // sret pointer. + X64ArgTypes.push_back(X64RetTy); + X64RetTy = VoidTy; + } +} + +void AArch64Arm64ECCallLowering::canonicalizeThunkType( + Type *T, Align Alignment, bool Ret, uint64_t ArgSizeBytes, raw_ostream &Out, + Type *&Arm64Ty, Type *&X64Ty) { + if (T->isFloatTy()) { + Out << "f"; + Arm64Ty = T; + X64Ty = T; + return; + } + + if (T->isDoubleTy()) { + Out << "d"; + Arm64Ty = T; + X64Ty = T; + return; + } + + if (T->isFloatingPointTy()) { + report_fatal_error( + "Only 32 and 64 bit floating points are supported for ARM64EC thunks"); + } + + auto &DL = M->getDataLayout(); + + if (auto *StructTy = dyn_cast(T)) + if (StructTy->getNumElements() == 1) + T = StructTy->getElementType(0); + + if (T->isArrayTy()) { + Type *ElementTy = T->getArrayElementType(); + uint64_t ElementCnt = T->getArrayNumElements(); + uint64_t ElementSizePerBytes = DL.getTypeSizeInBits(ElementTy) / 8; + uint64_t TotalSizeBytes = ElementCnt * ElementSizePerBytes; + if (ElementTy->isFloatTy() || ElementTy->isDoubleTy()) { + Out << (ElementTy->isFloatTy() ? "F" : "D") << TotalSizeBytes; + if (Alignment.value() >= 8 && !T->isPointerTy()) + Out << "a" << Alignment.value(); + Arm64Ty = T; + if (TotalSizeBytes <= 8) { + // Arm64 returns small structs of float/double in float registers; + // X64 uses RAX. + X64Ty = llvm::Type::getIntNTy(M->getContext(), TotalSizeBytes * 8); + } else { + // Struct is passed directly on Arm64, but indirectly on X64. + X64Ty = PtrTy; + } + return; + } else if (T->isFloatingPointTy()) { + report_fatal_error("Only 32 and 64 bit floating points are supported for " + "ARM64EC thunks"); + } + } + + if ((T->isIntegerTy() || T->isPointerTy()) && DL.getTypeSizeInBits(T) <= 64) { + Out << "i8"; + Arm64Ty = I64Ty; + X64Ty = I64Ty; + return; + } + + unsigned TypeSize = ArgSizeBytes; + if (TypeSize == 0) + TypeSize = DL.getTypeSizeInBits(T) / 8; + Out << "m"; + if (TypeSize != 4) + Out << TypeSize; + if (Alignment.value() >= 8 && !T->isPointerTy()) + Out << "a" << Alignment.value(); + // FIXME: Try to canonicalize Arm64Ty more thoroughly? + Arm64Ty = T; + if (TypeSize == 1 || TypeSize == 2 || TypeSize == 4 || TypeSize == 8) { + // Pass directly in an integer register + X64Ty = llvm::Type::getIntNTy(M->getContext(), TypeSize * 8); + } else { + // Passed directly on Arm64, but indirectly on X64. + X64Ty = PtrTy; + } +} + +// This function builds the "exit thunk", a function which translates +// arguments and return values when calling x64 code from AArch64 code. +Function *AArch64Arm64ECCallLowering::buildExitThunk(FunctionType *FT, + AttributeList Attrs) { + SmallString<256> ExitThunkName; + llvm::raw_svector_ostream ExitThunkStream(ExitThunkName); + FunctionType *Arm64Ty, *X64Ty; + getThunkType(FT, Attrs, /*EntryThunk*/ false, ExitThunkStream, Arm64Ty, + X64Ty); + if (Function *F = M->getFunction(ExitThunkName)) + return F; + + Function *F = Function::Create(Arm64Ty, GlobalValue::LinkOnceODRLinkage, 0, + ExitThunkName, M); + F->setCallingConv(CallingConv::ARM64EC_Thunk_Native); + F->setSection(".wowthk$aa"); + F->setComdat(M->getOrInsertComdat(ExitThunkName)); + // Copy MSVC, and always set up a frame pointer. (Maybe this isn't necessary.) + F->addFnAttr("frame-pointer", "all"); + // Only copy sret from the first argument. For C++ instance methods, clang can + // stick an sret marking on a later argument, but it doesn't actually affect + // the ABI, so we can omit it. This avoids triggering a verifier assertion. + if (FT->getNumParams()) { + auto SRet = Attrs.getParamAttr(0, Attribute::StructRet); + auto InReg = Attrs.getParamAttr(0, Attribute::InReg); + if (SRet.isValid() && !InReg.isValid()) + F->addParamAttr(1, SRet); + } + // FIXME: Copy anything other than sret? Shouldn't be necessary for normal + // C ABI, but might show up in other cases. + BasicBlock *BB = BasicBlock::Create(M->getContext(), "", F); + IRBuilder<> IRB(BB); + Value *CalleePtr = + M->getOrInsertGlobal("__os_arm64x_dispatch_call_no_redirect", PtrTy); + Value *Callee = IRB.CreateLoad(PtrTy, CalleePtr); + auto &DL = M->getDataLayout(); + SmallVector Args; + + // Pass the called function in x9. + Args.push_back(F->arg_begin()); + + Type *RetTy = Arm64Ty->getReturnType(); + if (RetTy != X64Ty->getReturnType()) { + // If the return type is an array or struct, translate it. Values of size + // 8 or less go into RAX; bigger values go into memory, and we pass a + // pointer. + if (DL.getTypeStoreSize(RetTy) > 8) { + Args.push_back(IRB.CreateAlloca(RetTy)); + } + } + + for (auto &Arg : make_range(F->arg_begin() + 1, F->arg_end())) { + // Translate arguments from AArch64 calling convention to x86 calling + // convention. + // + // For simple types, we don't need to do any translation: they're + // represented the same way. (Implicit sign extension is not part of + // either convention.) + // + // The big thing we have to worry about is struct types... but + // fortunately AArch64 clang is pretty friendly here: the cases that need + // translation are always passed as a struct or array. (If we run into + // some cases where this doesn't work, we can teach clang to mark it up + // with an attribute.) + // + // The first argument is the called function, stored in x9. + if (Arg.getType()->isArrayTy() || Arg.getType()->isStructTy() || + DL.getTypeStoreSize(Arg.getType()) > 8) { + Value *Mem = IRB.CreateAlloca(Arg.getType()); + IRB.CreateStore(&Arg, Mem); + if (DL.getTypeStoreSize(Arg.getType()) <= 8) { + Type *IntTy = IRB.getIntNTy(DL.getTypeStoreSizeInBits(Arg.getType())); + Args.push_back(IRB.CreateLoad(IntTy, IRB.CreateBitCast(Mem, PtrTy))); + } else + Args.push_back(Mem); + } else { + Args.push_back(&Arg); + } + } + // FIXME: Transfer necessary attributes? sret? anything else? + + Callee = IRB.CreateBitCast(Callee, PtrTy); + CallInst *Call = IRB.CreateCall(X64Ty, Callee, Args); + Call->setCallingConv(CallingConv::ARM64EC_Thunk_X64); + + Value *RetVal = Call; + if (RetTy != X64Ty->getReturnType()) { + // If we rewrote the return type earlier, convert the return value to + // the proper type. + if (DL.getTypeStoreSize(RetTy) > 8) { + RetVal = IRB.CreateLoad(RetTy, Args[1]); + } else { + Value *CastAlloca = IRB.CreateAlloca(RetTy); + IRB.CreateStore(Call, IRB.CreateBitCast(CastAlloca, PtrTy)); + RetVal = IRB.CreateLoad(RetTy, CastAlloca); + } + } + + if (RetTy->isVoidTy()) + IRB.CreateRetVoid(); + else + IRB.CreateRet(RetVal); + return F; +} + +// This function builds the "entry thunk", a function which translates +// arguments and return values when calling AArch64 code from x64 code. +Function *AArch64Arm64ECCallLowering::buildEntryThunk(Function *F) { + SmallString<256> EntryThunkName; + llvm::raw_svector_ostream EntryThunkStream(EntryThunkName); + FunctionType *Arm64Ty, *X64Ty; + getThunkType(F->getFunctionType(), F->getAttributes(), /*EntryThunk*/ true, + EntryThunkStream, Arm64Ty, X64Ty); + if (Function *F = M->getFunction(EntryThunkName)) + return F; + + Function *Thunk = Function::Create(X64Ty, GlobalValue::LinkOnceODRLinkage, 0, + EntryThunkName, M); + Thunk->setCallingConv(CallingConv::ARM64EC_Thunk_X64); + Thunk->setSection(".wowthk$aa"); + Thunk->setComdat(M->getOrInsertComdat(EntryThunkName)); + // Copy MSVC, and always set up a frame pointer. (Maybe this isn't necessary.) + Thunk->addFnAttr("frame-pointer", "all"); + + auto &DL = M->getDataLayout(); + BasicBlock *BB = BasicBlock::Create(M->getContext(), "", Thunk); + IRBuilder<> IRB(BB); + + Type *RetTy = Arm64Ty->getReturnType(); + Type *X64RetType = X64Ty->getReturnType(); + + bool TransformDirectToSRet = X64RetType->isVoidTy() && !RetTy->isVoidTy(); + unsigned ThunkArgOffset = TransformDirectToSRet ? 2 : 1; + + // Translate arguments to call. + SmallVector Args; + for (unsigned i = ThunkArgOffset, e = Thunk->arg_size(); i != e; ++i) { + Value *Arg = Thunk->getArg(i); + Type *ArgTy = Arm64Ty->getParamType(i - ThunkArgOffset); + if (ArgTy->isArrayTy() || ArgTy->isStructTy() || + DL.getTypeStoreSize(ArgTy) > 8) { + // Translate array/struct arguments to the expected type. + if (DL.getTypeStoreSize(ArgTy) <= 8) { + Value *CastAlloca = IRB.CreateAlloca(ArgTy); + IRB.CreateStore(Arg, IRB.CreateBitCast(CastAlloca, PtrTy)); + Arg = IRB.CreateLoad(ArgTy, CastAlloca); + } else { + Arg = IRB.CreateLoad(ArgTy, IRB.CreateBitCast(Arg, PtrTy)); + } + } + Args.push_back(Arg); + } + + // Call the function passed to the thunk. + Value *Callee = Thunk->getArg(0); + Callee = IRB.CreateBitCast(Callee, PtrTy); + Value *Call = IRB.CreateCall(Arm64Ty, Callee, Args); + + Value *RetVal = Call; + if (TransformDirectToSRet) { + IRB.CreateStore(RetVal, IRB.CreateBitCast(Thunk->getArg(1), PtrTy)); + } else if (X64RetType != RetTy) { + Value *CastAlloca = IRB.CreateAlloca(X64RetType); + IRB.CreateStore(Call, IRB.CreateBitCast(CastAlloca, PtrTy)); + RetVal = IRB.CreateLoad(X64RetType, CastAlloca); + } + + // Return to the caller. Note that the isel has code to translate this + // "ret" to a tail call to __os_arm64x_dispatch_ret. (Alternatively, we + // could emit a tail call here, but that would require a dedicated calling + // convention, which seems more complicated overall.) + if (X64RetType->isVoidTy()) + IRB.CreateRetVoid(); + else + IRB.CreateRet(RetVal); + + return Thunk; +} + +// Builds the "guest exit thunk", a helper to call a function which may or may +// not be an exit thunk. (We optimistically assume non-dllimport function +// declarations refer to functions defined in AArch64 code; if the linker +// can't prove that, we use this routine instead.) +Function *AArch64Arm64ECCallLowering::buildGuestExitThunk(Function *F) { + llvm::raw_null_ostream NullThunkName; + FunctionType *Arm64Ty, *X64Ty; + getThunkType(F->getFunctionType(), F->getAttributes(), /*EntryThunk*/ true, + NullThunkName, Arm64Ty, X64Ty); + auto MangledName = getArm64ECMangledFunctionName(F->getName().str()); + assert(MangledName && "Can't guest exit to function that's already native"); + std::string ThunkName = *MangledName; + if (ThunkName[0] == '?' && ThunkName.find("@") != std::string::npos) { + ThunkName.insert(ThunkName.find("@"), "$exit_thunk"); + } else { + ThunkName.append("$exit_thunk"); + } + Function *GuestExit = + Function::Create(Arm64Ty, GlobalValue::WeakODRLinkage, 0, ThunkName, M); + GuestExit->setComdat(M->getOrInsertComdat(ThunkName)); + GuestExit->setSection(".wowthk$aa"); + GuestExit->setMetadata( + "arm64ec_unmangled_name", + MDNode::get(M->getContext(), + MDString::get(M->getContext(), F->getName()))); + GuestExit->setMetadata( + "arm64ec_ecmangled_name", + MDNode::get(M->getContext(), + MDString::get(M->getContext(), *MangledName))); + F->setMetadata("arm64ec_hasguestexit", MDNode::get(M->getContext(), {})); + BasicBlock *BB = BasicBlock::Create(M->getContext(), "", GuestExit); + IRBuilder<> B(BB); + + // Load the global symbol as a pointer to the check function. + Value *GuardFn; + if (cfguard_module_flag == 2 && !F->hasFnAttribute("guard_nocf")) + GuardFn = GuardFnCFGlobal; + else + GuardFn = GuardFnGlobal; + LoadInst *GuardCheckLoad = B.CreateLoad(GuardFnPtrType, GuardFn); + + // Create new call instruction. The CFGuard check should always be a call, + // even if the original CallBase is an Invoke or CallBr instruction. + Function *Thunk = buildExitThunk(F->getFunctionType(), F->getAttributes()); + CallInst *GuardCheck = B.CreateCall( + GuardFnType, GuardCheckLoad, + {B.CreateBitCast(F, B.getPtrTy()), B.CreateBitCast(Thunk, B.getPtrTy())}); + + // Ensure that the first argument is passed in the correct register. + GuardCheck->setCallingConv(CallingConv::CFGuard_Check); + + Value *GuardRetVal = B.CreateBitCast(GuardCheck, PtrTy); + SmallVector Args; + for (Argument &Arg : GuestExit->args()) + Args.push_back(&Arg); + CallInst *Call = B.CreateCall(Arm64Ty, GuardRetVal, Args); + Call->setTailCallKind(llvm::CallInst::TCK_MustTail); + + if (Call->getType()->isVoidTy()) + B.CreateRetVoid(); + else + B.CreateRet(Call); + + auto SRetAttr = F->getAttributes().getParamAttr(0, Attribute::StructRet); + auto InRegAttr = F->getAttributes().getParamAttr(0, Attribute::InReg); + if (SRetAttr.isValid() && !InRegAttr.isValid()) { + GuestExit->addParamAttr(0, SRetAttr); + Call->addParamAttr(0, SRetAttr); + } + + return GuestExit; +} + +// Lower an indirect call with inline code. +void AArch64Arm64ECCallLowering::lowerCall(CallBase *CB) { + assert(Triple(CB->getModule()->getTargetTriple()).isOSWindows() && + "Only applicable for Windows targets"); + + IRBuilder<> B(CB); + Value *CalledOperand = CB->getCalledOperand(); + + // If the indirect call is called within catchpad or cleanuppad, + // we need to copy "funclet" bundle of the call. + SmallVector Bundles; + if (auto Bundle = CB->getOperandBundle(LLVMContext::OB_funclet)) + Bundles.push_back(OperandBundleDef(*Bundle)); + + // Load the global symbol as a pointer to the check function. + Value *GuardFn; + if (cfguard_module_flag == 2 && !CB->hasFnAttr("guard_nocf")) + GuardFn = GuardFnCFGlobal; + else + GuardFn = GuardFnGlobal; + LoadInst *GuardCheckLoad = B.CreateLoad(GuardFnPtrType, GuardFn); + + // Create new call instruction. The CFGuard check should always be a call, + // even if the original CallBase is an Invoke or CallBr instruction. + Function *Thunk = buildExitThunk(CB->getFunctionType(), CB->getAttributes()); + CallInst *GuardCheck = + B.CreateCall(GuardFnType, GuardCheckLoad, + {B.CreateBitCast(CalledOperand, B.getPtrTy()), + B.CreateBitCast(Thunk, B.getPtrTy())}, + Bundles); + + // Ensure that the first argument is passed in the correct register. + GuardCheck->setCallingConv(CallingConv::CFGuard_Check); + + Value *GuardRetVal = B.CreateBitCast(GuardCheck, CalledOperand->getType()); + CB->setCalledOperand(GuardRetVal); +} + +bool AArch64Arm64ECCallLowering::runOnModule(Module &Mod) { + if (!GenerateThunks) + return false; + + M = &Mod; + + // Check if this module has the cfguard flag and read its value. + if (auto *MD = + mdconst::extract_or_null(M->getModuleFlag("cfguard"))) + cfguard_module_flag = MD->getZExtValue(); + + PtrTy = PointerType::getUnqual(M->getContext()); + I64Ty = Type::getInt64Ty(M->getContext()); + VoidTy = Type::getVoidTy(M->getContext()); + + GuardFnType = FunctionType::get(PtrTy, {PtrTy, PtrTy}, false); + GuardFnPtrType = PointerType::get(GuardFnType, 0); + GuardFnCFGlobal = + M->getOrInsertGlobal("__os_arm64x_check_icall_cfg", GuardFnPtrType); + GuardFnGlobal = + M->getOrInsertGlobal("__os_arm64x_check_icall", GuardFnPtrType); + + SetVector DirectCalledFns; + for (Function &F : Mod) + if (!F.isDeclaration() && + F.getCallingConv() != CallingConv::ARM64EC_Thunk_Native && + F.getCallingConv() != CallingConv::ARM64EC_Thunk_X64) + processFunction(F, DirectCalledFns); + + struct ThunkInfo { + Constant *Src; + Constant *Dst; + unsigned Kind; + }; + SmallVector ThunkMapping; + for (Function &F : Mod) { + if (!F.isDeclaration() && (!F.hasLocalLinkage() || F.hasAddressTaken()) && + F.getCallingConv() != CallingConv::ARM64EC_Thunk_Native && + F.getCallingConv() != CallingConv::ARM64EC_Thunk_X64) { + if (!F.hasComdat()) + F.setComdat(Mod.getOrInsertComdat(F.getName())); + ThunkMapping.push_back({&F, buildEntryThunk(&F), 1}); + } + } + for (Function *F : DirectCalledFns) { + ThunkMapping.push_back( + {F, buildExitThunk(F->getFunctionType(), F->getAttributes()), 4}); + if (!F->hasDLLImportStorageClass()) + ThunkMapping.push_back({buildGuestExitThunk(F), F, 0}); + } + + if (!ThunkMapping.empty()) { + SmallVector ThunkMappingArrayElems; + for (ThunkInfo &Thunk : ThunkMapping) { + ThunkMappingArrayElems.push_back(ConstantStruct::getAnon( + {ConstantExpr::getBitCast(Thunk.Src, PtrTy), + ConstantExpr::getBitCast(Thunk.Dst, PtrTy), + ConstantInt::get(M->getContext(), APInt(32, Thunk.Kind))})); + } + Constant *ThunkMappingArray = ConstantArray::get( + llvm::ArrayType::get(ThunkMappingArrayElems[0]->getType(), + ThunkMappingArrayElems.size()), + ThunkMappingArrayElems); + new GlobalVariable(Mod, ThunkMappingArray->getType(), /*isConstant*/ false, + GlobalValue::ExternalLinkage, ThunkMappingArray, + "llvm.arm64ec.symbolmap"); + } + + return true; +} + +bool AArch64Arm64ECCallLowering::processFunction( + Function &F, SetVector &DirectCalledFns) { + SmallVector IndirectCalls; + + // For ARM64EC targets, a function definition's name is mangled differently + // from the normal symbol. We currently have no representation of this sort + // of symbol in IR, so we change the name to the mangled name, then store + // the unmangled name as metadata. Later passes that need the unmangled + // name (emitting the definition) can grab it from the metadata. + // + // FIXME: Handle functions with weak linkage? + if (F.hasExternalLinkage() || F.hasWeakLinkage() || F.hasLinkOnceLinkage()) { + if (std::optional MangledName = + getArm64ECMangledFunctionName(F.getName().str())) { + F.setMetadata("arm64ec_unmangled_name", + MDNode::get(M->getContext(), + MDString::get(M->getContext(), F.getName()))); + if (F.hasComdat() && F.getComdat()->getName() == F.getName()) { + Comdat *MangledComdat = M->getOrInsertComdat(MangledName.value()); + SmallVector ComdatUsers = + to_vector(F.getComdat()->getUsers()); + for (GlobalObject *User : ComdatUsers) + User->setComdat(MangledComdat); + } + F.setName(MangledName.value()); + } + } + + // Iterate over the instructions to find all indirect call/invoke/callbr + // instructions. Make a separate list of pointers to indirect + // call/invoke/callbr instructions because the original instructions will be + // deleted as the checks are added. + for (BasicBlock &BB : F) { + for (Instruction &I : BB) { + auto *CB = dyn_cast(&I); + if (!CB || CB->getCallingConv() == CallingConv::ARM64EC_Thunk_X64 || + CB->isInlineAsm()) + continue; + + // We need to instrument any call that isn't directly calling an + // ARM64 function. + // + // FIXME: getCalledFunction() fails if there's a bitcast (e.g. + // unprototyped functions in C) + if (Function *F = CB->getCalledFunction()) { + if (!LowerDirectToIndirect || F->hasLocalLinkage() || + F->isIntrinsic() || !F->isDeclaration()) + continue; + + DirectCalledFns.insert(F); + continue; + } + + IndirectCalls.push_back(CB); + ++Arm64ECCallsLowered; + } + } + + if (IndirectCalls.empty()) + return false; + + for (CallBase *CB : IndirectCalls) + lowerCall(CB); + + return true; +} + +char AArch64Arm64ECCallLowering::ID = 0; +INITIALIZE_PASS(AArch64Arm64ECCallLowering, "Arm64ECCallLowering", + "AArch64Arm64ECCallLowering", false, false) + +ModulePass *llvm::createAArch64Arm64ECCallLoweringPass() { + return new AArch64Arm64ECCallLowering; +} diff --git a/llvm/lib/Target/AArch64/AArch64AsmPrinter.cpp b/llvm/lib/Target/AArch64/AArch64AsmPrinter.cpp index 7d2ff146a34..de247253eb1 100644 --- a/llvm/lib/Target/AArch64/AArch64AsmPrinter.cpp +++ b/llvm/lib/Target/AArch64/AArch64AsmPrinter.cpp @@ -167,6 +167,8 @@ public: return false; } + const MCExpr *lowerConstant(const Constant *CV) override; + private: void printOperand(const MachineInstr *MI, unsigned OpNum, raw_ostream &O); bool printAsmMRegister(const MachineOperand &MO, char Mode, raw_ostream &O); @@ -1119,6 +1121,50 @@ void AArch64AsmPrinter::emitFunctionEntryLabel() { TS->emitDirectiveVariantPCS(CurrentFnSym); } + if (TM.getTargetTriple().isWindowsArm64EC()) { + // For ARM64EC targets, a function definition's name is mangled differently + // from the normal symbol. We emit the alias from the unmangled symbol to + // mangled symbol name here. + if (MDNode *Unmangled = + MF->getFunction().getMetadata("arm64ec_unmangled_name")) { + AsmPrinter::emitFunctionEntryLabel(); + + if (MDNode *ECMangled = + MF->getFunction().getMetadata("arm64ec_ecmangled_name")) { + StringRef UnmangledStr = + cast(Unmangled->getOperand(0))->getString(); + MCSymbol *UnmangledSym = + MMI->getContext().getOrCreateSymbol(UnmangledStr); + StringRef ECMangledStr = + cast(ECMangled->getOperand(0))->getString(); + MCSymbol *ECMangledSym = + MMI->getContext().getOrCreateSymbol(ECMangledStr); + OutStreamer->emitSymbolAttribute(UnmangledSym, MCSA_WeakAntiDep); + OutStreamer->emitAssignment( + UnmangledSym, + MCSymbolRefExpr::create(ECMangledSym, MCSymbolRefExpr::VK_WEAKREF, + MMI->getContext())); + OutStreamer->emitSymbolAttribute(ECMangledSym, MCSA_WeakAntiDep); + OutStreamer->emitAssignment( + ECMangledSym, + MCSymbolRefExpr::create(CurrentFnSym, MCSymbolRefExpr::VK_WEAKREF, + MMI->getContext())); + return; + } else { + StringRef UnmangledStr = + cast(Unmangled->getOperand(0))->getString(); + MCSymbol *UnmangledSym = + MMI->getContext().getOrCreateSymbol(UnmangledStr); + OutStreamer->emitSymbolAttribute(UnmangledSym, MCSA_WeakAntiDep); + OutStreamer->emitAssignment( + UnmangledSym, + MCSymbolRefExpr::create(CurrentFnSym, MCSymbolRefExpr::VK_WEAKREF, + MMI->getContext())); + return; + } + } + } + return AsmPrinter::emitFunctionEntryLabel(); } @@ -1818,6 +1864,28 @@ void AArch64AsmPrinter::emitInstruction(const MachineInstr *MI) { case AArch64::SEH_PACSignLR: TS->emitARM64WinCFIPACSignLR(); return; + + case AArch64::SEH_SaveAnyRegQP: + assert(MI->getOperand(1).getImm() - MI->getOperand(0).getImm() == 1 && + "Non-consecutive registers not allowed for save_any_reg"); + assert(MI->getOperand(2).getImm() >= 0 && + "SaveAnyRegQP SEH opcode offset must be non-negative"); + assert(MI->getOperand(2).getImm() <= 1008 && + "SaveAnyRegQP SEH opcode offset must fit into 6 bits"); + TS->emitARM64WinCFISaveAnyRegQP(MI->getOperand(0).getImm(), + MI->getOperand(2).getImm()); + return; + + case AArch64::SEH_SaveAnyRegQPX: + assert(MI->getOperand(1).getImm() - MI->getOperand(0).getImm() == 1 && + "Non-consecutive registers not allowed for save_any_reg"); + assert(MI->getOperand(2).getImm() < 0 && + "SaveAnyRegQPX SEH opcode offset must be negative"); + assert(MI->getOperand(2).getImm() >= -1008 && + "SaveAnyRegQPX SEH opcode offset must fit into 6 bits"); + TS->emitARM64WinCFISaveAnyRegQPX(MI->getOperand(0).getImm(), + -MI->getOperand(2).getImm()); + return; } // Finally, do the automated lowerings for everything else. @@ -2021,6 +2089,15 @@ void AArch64AsmPrinter::emitMachOIFuncStubHelperBody(Module &M, *STI); } +const MCExpr *AArch64AsmPrinter::lowerConstant(const Constant *CV) { + if (const GlobalValue *GV = dyn_cast(CV)) { + return MCSymbolRefExpr::create(MCInstLowering.GetGlobalValueSymbol(GV, 0), + OutContext); + } + + return AsmPrinter::lowerConstant(CV); +} + // Force static initialization. extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeAArch64AsmPrinter() { RegisterAsmPrinter X(getTheAArch64leTarget()); diff --git a/llvm/lib/Target/AArch64/AArch64CallingConvention.h b/llvm/lib/Target/AArch64/AArch64CallingConvention.h index ec46f62d065..3b51ee12b74 100644 --- a/llvm/lib/Target/AArch64/AArch64CallingConvention.h +++ b/llvm/lib/Target/AArch64/AArch64CallingConvention.h @@ -22,6 +22,12 @@ bool CC_AArch64_AAPCS(unsigned ValNo, MVT ValVT, MVT LocVT, bool CC_AArch64_Arm64EC_VarArg(unsigned ValNo, MVT ValVT, MVT LocVT, CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags, CCState &State); +bool CC_AArch64_Arm64EC_Thunk(unsigned ValNo, MVT ValVT, MVT LocVT, + CCValAssign::LocInfo LocInfo, + ISD::ArgFlagsTy ArgFlags, CCState &State); +bool CC_AArch64_Arm64EC_Thunk_Native(unsigned ValNo, MVT ValVT, MVT LocVT, + CCValAssign::LocInfo LocInfo, + ISD::ArgFlagsTy ArgFlags, CCState &State); bool CC_AArch64_DarwinPCS_VarArg(unsigned ValNo, MVT ValVT, MVT LocVT, CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags, CCState &State); @@ -40,12 +46,22 @@ bool CC_AArch64_Win64_VarArg(unsigned ValNo, MVT ValVT, MVT LocVT, bool CC_AArch64_Win64_CFGuard_Check(unsigned ValNo, MVT ValVT, MVT LocVT, CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags, CCState &State); +bool CC_AArch64_Arm64EC_CFGuard_Check(unsigned ValNo, MVT ValVT, MVT LocVT, + CCValAssign::LocInfo LocInfo, + ISD::ArgFlagsTy ArgFlags, CCState &State); bool CC_AArch64_GHC(unsigned ValNo, MVT ValVT, MVT LocVT, CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags, CCState &State); bool RetCC_AArch64_AAPCS(unsigned ValNo, MVT ValVT, MVT LocVT, CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags, CCState &State); +bool RetCC_AArch64_Arm64EC_Thunk(unsigned ValNo, MVT ValVT, MVT LocVT, + CCValAssign::LocInfo LocInfo, + ISD::ArgFlagsTy ArgFlags, CCState &State); +bool RetCC_AArch64_Arm64EC_CFGuard_Check(unsigned ValNo, MVT ValVT, MVT LocVT, + CCValAssign::LocInfo LocInfo, + ISD::ArgFlagsTy ArgFlags, + CCState &State); } // namespace llvm #endif diff --git a/llvm/lib/Target/AArch64/AArch64CallingConvention.td b/llvm/lib/Target/AArch64/AArch64CallingConvention.td index e47996bf38d..78ea4a5180f 100644 --- a/llvm/lib/Target/AArch64/AArch64CallingConvention.td +++ b/llvm/lib/Target/AArch64/AArch64CallingConvention.td @@ -208,6 +208,119 @@ def CC_AArch64_Arm64EC_VarArg : CallingConv<[ CCIfType<[i32, i64], CCAssignToStack<8, 8>>, ]>; +// Arm64EC thunks use a calling convention that's precisely the x64 calling +// convention, except that the registers have different names, and the callee +// address is passed in X9. +let Entry = 1 in +def CC_AArch64_Arm64EC_Thunk : CallingConv<[ + // Byval aggregates are passed by pointer + CCIfByVal>, + + // ARM64EC-specific: promote small integers to i32. (x86 only promotes i1, + // but that would confuse ARM64 lowering code.) + CCIfType<[i1, i8, i16], CCPromoteToType>, + + // The 'nest' parameter, if any, is passed in R10 (X4). + CCIfNest>, + + // A SwiftError is passed in R12 (X19). + CCIfSwiftError>>, + + // Pass SwiftSelf in R13 (X20). + CCIfSwiftSelf>>, + + // Pass SwiftAsync in an otherwise callee saved register so that calls to + // normal functions don't need to save it somewhere. + CCIfSwiftAsync>>, + + // The 'CFGuardTarget' parameter, if any, is passed in RAX (R8). + CCIfCFGuardTarget>, + + // 128 bit vectors are passed by pointer + CCIfType<[v16i8, v8i16, v4i32, v2i64, v8f16, v4f32, v2f64], CCPassIndirect>, + + // 256 bit vectors are passed by pointer + CCIfType<[v32i8, v16i16, v8i32, v4i64, v16f16, v8f32, v4f64], CCPassIndirect>, + + // 512 bit vectors are passed by pointer + CCIfType<[v64i8, v32i16, v16i32, v32f16, v16f32, v8f64, v8i64], CCPassIndirect>, + + // Long doubles are passed by pointer + CCIfType<[f80], CCPassIndirect>, + + // The first 4 MMX vector arguments are passed in GPRs. + CCIfType<[x86mmx], CCBitConvertToType>, + + // The first 4 FP/Vector arguments are passed in XMM registers. + CCIfType<[f16], + CCAssignToRegWithShadow<[H0, H1, H2, H3], + [X0, X1, X2, X3]>>, + CCIfType<[f32], + CCAssignToRegWithShadow<[S0, S1, S2, S3], + [X0, X1, X2, X3]>>, + CCIfType<[f64], + CCAssignToRegWithShadow<[D0, D1, D2, D3], + [X0, X1, X2, X3]>>, + + // The first 4 integer arguments are passed in integer registers. + CCIfType<[i32], CCAssignToRegWithShadow<[W0, W1, W2, W3], + [Q0, Q1, Q2, Q3]>>, + + // Arm64EC thunks: the first argument is always a pointer to the destination + // address, stored in x9. + CCIfType<[i64], CCAssignToReg<[X9]>>, + + CCIfType<[i64], CCAssignToRegWithShadow<[X0, X1, X2, X3], + [Q0, Q1, Q2, Q3]>>, + + // Integer/FP values get stored in stack slots that are 8 bytes in size and + // 8-byte aligned if there are no more registers to hold them. + CCIfType<[i8, i16, i32, i64, f16, f32, f64], CCAssignToStack<8, 8>> +]>; + +// The native side of ARM64EC thunks +let Entry = 1 in +def CC_AArch64_Arm64EC_Thunk_Native : CallingConv<[ + CCIfType<[i64], CCAssignToReg<[X9]>>, + CCDelegateTo +]>; + +let Entry = 1 in +def RetCC_AArch64_Arm64EC_Thunk : CallingConv<[ + // The X86-Win64 calling convention always returns __m64 values in RAX. + CCIfType<[x86mmx], CCBitConvertToType>, + + // Otherwise, everything is the same as 'normal' X86-64 C CC. + + // The X86-64 calling convention always returns FP values in XMM0. + CCIfType<[f16], CCAssignToReg<[H0, H1]>>, + CCIfType<[f32], CCAssignToReg<[S0, S1]>>, + CCIfType<[f64], CCAssignToReg<[D0, D1]>>, + CCIfType<[f128], CCAssignToReg<[Q0, Q1]>>, + + CCIfSwiftError>>, + + // Scalar values are returned in AX first, then DX. For i8, the ABI + // requires the values to be in AL and AH, however this code uses AL and DL + // instead. This is because using AH for the second register conflicts with + // the way LLVM does multiple return values -- a return of {i16,i8} would end + // up in AX and AH, which overlap. Front-ends wishing to conform to the ABI + // for functions that return two i8 values are currently expected to pack the + // values into an i16 (which uses AX, and thus AL:AH). + // + // For code that doesn't care about the ABI, we allow returning more than two + // integer values in registers. + CCIfType<[i1, i8, i16], CCPromoteToType>, + CCIfType<[i32], CCAssignToReg<[W8, W1, W0]>>, + CCIfType<[i64], CCAssignToReg<[X8, X1, X0]>>, + + // Vector types are returned in XMM0 and XMM1, when they fit. XMM2 and XMM3 + // can only be used by ABI non-compliant code. If the target doesn't have XMM + // registers, it won't have vector types. + CCIfType<[v16i8, v8i16, v4i32, v2i64, v8f16, v4f32, v2f64], + CCAssignToReg<[Q0, Q1, Q2, Q3]>> +]>; + // Windows Control Flow Guard checks take a single argument (the target function // address) and have no return value. let Entry = 1 in @@ -215,6 +328,16 @@ def CC_AArch64_Win64_CFGuard_Check : CallingConv<[ CCIfType<[i64], CCAssignToReg<[X15]>> ]>; +let Entry = 1 in +def CC_AArch64_Arm64EC_CFGuard_Check : CallingConv<[ + CCIfType<[i64], CCAssignToReg<[X11, X10]>> +]>; + +let Entry = 1 in +def RetCC_AArch64_Arm64EC_CFGuard_Check : CallingConv<[ + CCIfType<[i64], CCAssignToReg<[X11]>> +]>; + // Darwin uses a calling convention which differs in only two ways // from the standard one at this level: @@ -411,6 +534,11 @@ def CSR_Win_AArch64_CFGuard_Check : CalleeSavedRegs<(add CSR_Win_AArch64_AAPCS, (sequence "X%u", 0, 8), (sequence "Q%u", 0, 7))>; +// To match the x64 calling convention, Arm64EC thunks preserve q6-q15. +def CSR_Win_AArch64_Arm64EC_Thunk : CalleeSavedRegs<(add (sequence "Q%u", 6, 15), + X19, X20, X21, X22, X23, X24, + X25, X26, X27, X28, FP, LR)>; + // AArch64 PCS for vector functions (VPCS) // must (additionally) preserve full Q8-Q23 registers def CSR_AArch64_AAVPCS : CalleeSavedRegs<(add X19, X20, X21, X22, X23, X24, diff --git a/llvm/lib/Target/AArch64/AArch64Combine.td b/llvm/lib/Target/AArch64/AArch64Combine.td index 99f256b8878..1daa7d5fe6a 100644 --- a/llvm/lib/Target/AArch64/AArch64Combine.td +++ b/llvm/lib/Target/AArch64/AArch64Combine.td @@ -44,13 +44,22 @@ def ext_addv_to_udot_addv : GICombineRule< >; } +def ext_uaddv_to_uaddlv_matchinfo : GIDefMatchData<"std::pair">; +def ext_uaddv_to_uaddlv : GICombineRule< + (defs root:$root, ext_uaddv_to_uaddlv_matchinfo:$matchinfo), + (match (wip_match_opcode G_VECREDUCE_ADD):$root, + [{ return matchExtUaddvToUaddlv(*${root}, MRI, ${matchinfo}); }]), + (apply [{ applyExtUaddvToUaddlv(*${root}, MRI, B, Observer, ${matchinfo}); }]) +>; + def AArch64PreLegalizerCombiner: GICombiner< "AArch64PreLegalizerCombinerImpl", [all_combines, fconstant_to_constant, icmp_redundant_trunc, fold_global_offset, shuffle_to_extract, - ext_addv_to_udot_addv]> { + ext_addv_to_udot_addv, + ext_uaddv_to_uaddlv]> { let CombineAllMethodName = "tryCombineAllImpl"; } diff --git a/llvm/lib/Target/AArch64/AArch64ExpandPseudoInsts.cpp b/llvm/lib/Target/AArch64/AArch64ExpandPseudoInsts.cpp index bb7f4d907ff..352c61d48e2 100644 --- a/llvm/lib/Target/AArch64/AArch64ExpandPseudoInsts.cpp +++ b/llvm/lib/Target/AArch64/AArch64ExpandPseudoInsts.cpp @@ -843,8 +843,24 @@ bool AArch64ExpandPseudo::expandCALL_BTI(MachineBasicBlock &MBB, MachineInstr *Call = BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(Opc)).getInstr(); Call->addOperand(CallTarget); + + // 1 because we already added the branch target above. + unsigned RegMaskStartIdx = 1; + // The branch is BL , so we cannot attach the arguments of the called + // function to it. Those must be added as implicitly used by the branch. + while (!MI.getOperand(RegMaskStartIdx).isRegMask()) { + auto MOP = MI.getOperand(RegMaskStartIdx); + assert(MOP.isReg() && "can only add register operands"); + Call->addOperand(MachineOperand::CreateReg( + MOP.getReg(), /*Def=*/false, /*Implicit=*/true, /*isKill=*/false, + /*isDead=*/false, /*isUndef=*/MOP.isUndef())); + RegMaskStartIdx++; + } + for (const MachineOperand &MO : + llvm::drop_begin(MI.operands(), RegMaskStartIdx)) + Call->addOperand(MO); + Call->setCFIType(*MBB.getParent(), MI.getCFIType()); - Call->copyImplicitOps(*MBB.getParent(), MI); MachineInstr *BTI = BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(AArch64::HINT)) diff --git a/llvm/lib/Target/AArch64/AArch64FastISel.cpp b/llvm/lib/Target/AArch64/AArch64FastISel.cpp index e98f6c4984a..b00235d73d6 100644 --- a/llvm/lib/Target/AArch64/AArch64FastISel.cpp +++ b/llvm/lib/Target/AArch64/AArch64FastISel.cpp @@ -3176,6 +3176,9 @@ bool AArch64FastISel::fastLowerCall(CallLoweringInfo &CLI) { if (IsVarArg) return false; + if (Subtarget->isWindowsArm64EC()) + return false; + for (auto Flag : CLI.OutFlags) if (Flag.isInReg() || Flag.isSRet() || Flag.isNest() || Flag.isByVal() || Flag.isSwiftSelf() || Flag.isSwiftAsync() || Flag.isSwiftError()) diff --git a/llvm/lib/Target/AArch64/AArch64FrameLowering.cpp b/llvm/lib/Target/AArch64/AArch64FrameLowering.cpp index caab59201a8..d55deec9760 100644 --- a/llvm/lib/Target/AArch64/AArch64FrameLowering.cpp +++ b/llvm/lib/Target/AArch64/AArch64FrameLowering.cpp @@ -1281,6 +1281,30 @@ static MachineBasicBlock::iterator InsertSEH(MachineBasicBlock::iterator MBBI, .setMIFlag(Flag); break; } + case AArch64::STPQi: + case AArch64::LDPQi: { + unsigned Reg0 = RegInfo->getSEHRegNum(MBBI->getOperand(0).getReg()); + unsigned Reg1 = RegInfo->getSEHRegNum(MBBI->getOperand(1).getReg()); + MIB = BuildMI(MF, DL, TII.get(AArch64::SEH_SaveAnyRegQP)) + .addImm(Reg0) + .addImm(Reg1) + .addImm(Imm * 16) + .setMIFlag(Flag); + break; + } + case AArch64::LDPQpost: + Imm = -Imm; + LLVM_FALLTHROUGH; + case AArch64::STPQpre: { + unsigned Reg0 = RegInfo->getSEHRegNum(MBBI->getOperand(1).getReg()); + unsigned Reg1 = RegInfo->getSEHRegNum(MBBI->getOperand(2).getReg()); + MIB = BuildMI(MF, DL, TII.get(AArch64::SEH_SaveAnyRegQPX)) + .addImm(Reg0) + .addImm(Reg1) + .addImm(Imm * 16) + .setMIFlag(Flag); + break; + } } auto I = MBB->insertAfter(MBBI, MIB); return I; @@ -1299,6 +1323,8 @@ static void fixupSEHOpcode(MachineBasicBlock::iterator MBBI, case AArch64::SEH_SaveReg: case AArch64::SEH_SaveFRegP: case AArch64::SEH_SaveFReg: + case AArch64::SEH_SaveAnyRegQP: + case AArch64::SEH_SaveAnyRegQPX: ImmOpnd = &MBBI->getOperand(ImmIdx); break; } diff --git a/llvm/lib/Target/AArch64/AArch64GlobalsTagging.cpp b/llvm/lib/Target/AArch64/AArch64GlobalsTagging.cpp index 8ce6f94e734..27959489e7d 100644 --- a/llvm/lib/Target/AArch64/AArch64GlobalsTagging.cpp +++ b/llvm/lib/Target/AArch64/AArch64GlobalsTagging.cpp @@ -43,13 +43,25 @@ static bool shouldTagGlobal(GlobalVariable &G) { return false; } - // Don't instrument function pointers that are going into various init arrays - // via `__attribute__((section()))`: - // https://github.com/llvm/llvm-project/issues/69939 - if (G.hasSection() && - (G.getSection() == ".init" || G.getSection() == ".fini" || - G.getSection() == ".init_array" || G.getSection() == ".fini_array" || - G.getSection() == ".ctors" || G.getSection() == ".dtors")) { + // Globals can be placed implicitly or explicitly in sections. There's two + // different types of globals that meet this criteria that cause problems: + // 1. Function pointers that are going into various init arrays (either + // explicitly through `__attribute__((section()))` or implicitly + // through `__attribute__((constructor)))`, such as ".(pre)init(_array)", + // ".fini(_array)", ".ctors", and ".dtors". These function pointers end up + // overaligned and overpadded, making iterating over them problematic, and + // each function pointer is individually tagged (so the iteration over + // them causes SIGSEGV/MTE[AS]ERR). + // 2. Global variables put into an explicit section, where the section's name + // is a valid C-style identifier. The linker emits a `__start_` and + // `__stop_` symbol for the section, so that you can iterate over + // globals within this section. Unfortunately, again, these globals would + // be tagged and so iteration causes SIGSEGV/MTE[AS]ERR. + // + // To mitigate both these cases, and because specifying a section is rare + // outside of these two cases, disable MTE protection for globals in any + // section. + if (G.hasSection()) { Meta.Memtag = false; G.setSanitizerMetadata(Meta); return false; diff --git a/llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp b/llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp index ea5679b4d5e..163ed520a8a 100644 --- a/llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp +++ b/llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp @@ -4275,6 +4275,58 @@ bool AArch64DAGToDAGISel::trySelectXAR(SDNode *N) { SDValue N0 = N->getOperand(0); SDValue N1 = N->getOperand(1); + EVT VT = N->getValueType(0); + + // Essentially: rotr (xor(x, y), imm) -> xar (x, y, imm) + // Rotate by a constant is a funnel shift in IR which is exanded to + // an OR with shifted operands. + // We do the following transform: + // OR N0, N1 -> xar (x, y, imm) + // Where: + // N1 = SRL_PRED true, V, splat(imm) --> rotr amount + // N0 = SHL_PRED true, V, splat(bits-imm) + // V = (xor x, y) + if (VT.isScalableVector() && Subtarget->hasSVE2orSME()) { + if (N0.getOpcode() != AArch64ISD::SHL_PRED || + N1.getOpcode() != AArch64ISD::SRL_PRED) + std::swap(N0, N1); + if (N0.getOpcode() != AArch64ISD::SHL_PRED || + N1.getOpcode() != AArch64ISD::SRL_PRED) + return false; + + auto *TLI = static_cast(getTargetLowering()); + if (!TLI->isAllActivePredicate(*CurDAG, N0.getOperand(0)) || + !TLI->isAllActivePredicate(*CurDAG, N1.getOperand(0))) + return false; + + SDValue XOR = N0.getOperand(1); + if (XOR.getOpcode() != ISD::XOR || XOR != N1.getOperand(1)) + return false; + + APInt ShlAmt, ShrAmt; + if (!ISD::isConstantSplatVector(N0.getOperand(2).getNode(), ShlAmt) || + !ISD::isConstantSplatVector(N1.getOperand(2).getNode(), ShrAmt)) + return false; + + if (ShlAmt + ShrAmt != VT.getScalarSizeInBits()) + return false; + + SDLoc DL(N); + SDValue Imm = + CurDAG->getTargetConstant(ShrAmt.getZExtValue(), DL, MVT::i32); + + SDValue Ops[] = {XOR.getOperand(0), XOR.getOperand(1), Imm}; + if (auto Opc = SelectOpcodeFromVT( + VT, {AArch64::XAR_ZZZI_B, AArch64::XAR_ZZZI_H, AArch64::XAR_ZZZI_S, + AArch64::XAR_ZZZI_D})) { + CurDAG->SelectNodeTo(N, Opc, VT, Ops); + return true; + } + return false; + } + + if (!Subtarget->hasSHA3()) + return false; if (N0->getOpcode() != AArch64ISD::VSHL || N1->getOpcode() != AArch64ISD::VLSHR) @@ -4367,7 +4419,7 @@ void AArch64DAGToDAGISel::Select(SDNode *Node) { case ISD::OR: if (tryBitfieldInsertOp(Node)) return; - if (Subtarget->hasSHA3() && trySelectXAR(Node)) + if (trySelectXAR(Node)) return; break; @@ -5575,25 +5627,25 @@ void AArch64DAGToDAGISel::Select(SDNode *Node) { AArch64::FMINNM_VG4_4Z4Z_D})) SelectDestructiveMultiIntrinsic(Node, 4, true, Op); return; - case Intrinsic::aarch64_sve_fcvts_x2: + case Intrinsic::aarch64_sve_fcvtzs_x2: SelectCVTIntrinsic(Node, 2, AArch64::FCVTZS_2Z2Z_StoS); return; case Intrinsic::aarch64_sve_scvtf_x2: SelectCVTIntrinsic(Node, 2, AArch64::SCVTF_2Z2Z_StoS); return; - case Intrinsic::aarch64_sve_fcvtu_x2: + case Intrinsic::aarch64_sve_fcvtzu_x2: SelectCVTIntrinsic(Node, 2, AArch64::FCVTZU_2Z2Z_StoS); return; case Intrinsic::aarch64_sve_ucvtf_x2: SelectCVTIntrinsic(Node, 2, AArch64::UCVTF_2Z2Z_StoS); return; - case Intrinsic::aarch64_sve_fcvts_x4: + case Intrinsic::aarch64_sve_fcvtzs_x4: SelectCVTIntrinsic(Node, 4, AArch64::FCVTZS_4Z4Z_StoS); return; case Intrinsic::aarch64_sve_scvtf_x4: SelectCVTIntrinsic(Node, 4, AArch64::SCVTF_4Z4Z_StoS); return; - case Intrinsic::aarch64_sve_fcvtu_x4: + case Intrinsic::aarch64_sve_fcvtzu_x4: SelectCVTIntrinsic(Node, 4, AArch64::FCVTZU_4Z4Z_StoS); return; case Intrinsic::aarch64_sve_ucvtf_x4: diff --git a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp index e2d07a09649..332fb376552 100644 --- a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp +++ b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp @@ -1358,6 +1358,10 @@ AArch64TargetLowering::AArch64TargetLowering(const TargetMachine &TM, if (!Subtarget->isLittleEndian()) setOperationAction(ISD::BITCAST, VT, Expand); + + if (Subtarget->hasSVE2orSME()) + // For SLI/SRI. + setOperationAction(ISD::OR, VT, Custom); } // Illegal unpacked integer vector types. @@ -1652,6 +1656,43 @@ AArch64TargetLowering::AArch64TargetLowering(const TargetMachine &TM, IsStrictFPEnabled = true; setMaxAtomicSizeInBitsSupported(128); + + if (Subtarget->isWindowsArm64EC()) { + // FIXME: are there other intrinsics we need to add here? + setLibcallName(RTLIB::MEMCPY, "#memcpy"); + setLibcallName(RTLIB::MEMSET, "#memset"); + setLibcallName(RTLIB::MEMMOVE, "#memmove"); + setLibcallName(RTLIB::REM_F32, "#fmodf"); + setLibcallName(RTLIB::REM_F64, "#fmod"); + setLibcallName(RTLIB::FMA_F32, "#fmaf"); + setLibcallName(RTLIB::FMA_F64, "#fma"); + setLibcallName(RTLIB::SQRT_F32, "#sqrtf"); + setLibcallName(RTLIB::SQRT_F64, "#sqrt"); + setLibcallName(RTLIB::CBRT_F32, "#cbrtf"); + setLibcallName(RTLIB::CBRT_F64, "#cbrt"); + setLibcallName(RTLIB::LOG_F32, "#logf"); + setLibcallName(RTLIB::LOG_F64, "#log"); + setLibcallName(RTLIB::LOG2_F32, "#log2f"); + setLibcallName(RTLIB::LOG2_F64, "#log2"); + setLibcallName(RTLIB::LOG10_F32, "#log10f"); + setLibcallName(RTLIB::LOG10_F64, "#log10"); + setLibcallName(RTLIB::EXP_F32, "#expf"); + setLibcallName(RTLIB::EXP_F64, "#exp"); + setLibcallName(RTLIB::EXP2_F32, "#exp2f"); + setLibcallName(RTLIB::EXP2_F64, "#exp2"); + setLibcallName(RTLIB::EXP10_F32, "#exp10f"); + setLibcallName(RTLIB::EXP10_F64, "#exp10"); + setLibcallName(RTLIB::SIN_F32, "#sinf"); + setLibcallName(RTLIB::SIN_F64, "#sin"); + setLibcallName(RTLIB::COS_F32, "#cosf"); + setLibcallName(RTLIB::COS_F64, "#cos"); + setLibcallName(RTLIB::POW_F32, "#powf"); + setLibcallName(RTLIB::POW_F64, "#pow"); + setLibcallName(RTLIB::LDEXP_F32, "#ldexpf"); + setLibcallName(RTLIB::LDEXP_F64, "#ldexp"); + setLibcallName(RTLIB::FREXP_F32, "#frexpf"); + setLibcallName(RTLIB::FREXP_F64, "#frexp"); + } } void AArch64TargetLowering::addTypeForNEON(MVT VT) { @@ -2160,9 +2201,8 @@ void AArch64TargetLowering::computeKnownBitsForTargetNode( break; } case AArch64ISD::MOVI: { - ConstantSDNode *CN = cast(Op->getOperand(0)); - Known = - KnownBits::makeConstant(APInt(Known.getBitWidth(), CN->getZExtValue())); + Known = KnownBits::makeConstant( + APInt(Known.getBitWidth(), Op->getConstantOperandVal(0))); break; } case AArch64ISD::LOADgot: @@ -2179,8 +2219,8 @@ void AArch64TargetLowering::computeKnownBitsForTargetNode( break; } case ISD::INTRINSIC_W_CHAIN: { - ConstantSDNode *CN = cast(Op->getOperand(1)); - Intrinsic::ID IntID = static_cast(CN->getZExtValue()); + Intrinsic::ID IntID = + static_cast(Op->getConstantOperandVal(1)); switch (IntID) { default: return; case Intrinsic::aarch64_ldaxr: @@ -2338,6 +2378,8 @@ const char *AArch64TargetLowering::getTargetNodeName(unsigned Opcode) const { MAKE_CASE(AArch64ISD::SMSTART) MAKE_CASE(AArch64ISD::SMSTOP) MAKE_CASE(AArch64ISD::RESTORE_ZA) + MAKE_CASE(AArch64ISD::RESTORE_ZT) + MAKE_CASE(AArch64ISD::SAVE_ZT) MAKE_CASE(AArch64ISD::CALL) MAKE_CASE(AArch64ISD::ADRP) MAKE_CASE(AArch64ISD::ADR) @@ -2461,6 +2503,7 @@ const char *AArch64TargetLowering::getTargetNodeName(unsigned Opcode) const { MAKE_CASE(AArch64ISD::SADDV) MAKE_CASE(AArch64ISD::UADDV) MAKE_CASE(AArch64ISD::UADDLV) + MAKE_CASE(AArch64ISD::SADDLV) MAKE_CASE(AArch64ISD::SDOT) MAKE_CASE(AArch64ISD::UDOT) MAKE_CASE(AArch64ISD::SMINV) @@ -2645,6 +2688,7 @@ const char *AArch64TargetLowering::getTargetNodeName(unsigned Opcode) const { MAKE_CASE(AArch64ISD::MSRR) MAKE_CASE(AArch64ISD::RSHRNB_I) MAKE_CASE(AArch64ISD::CTTZ_ELTS) + MAKE_CASE(AArch64ISD::CALL_ARM64EC_TO_X64) } #undef MAKE_CASE return nullptr; @@ -4850,17 +4894,9 @@ static SDValue getSVEPredicateBitCast(EVT VT, SDValue Op, SelectionDAG &DAG) { return DAG.getNode(ISD::AND, DL, VT, Reinterpret, Mask); } -SDValue AArch64TargetLowering::getPStateSM(SelectionDAG &DAG, SDValue Chain, - SMEAttrs Attrs, SDLoc DL, - EVT VT) const { - if (Attrs.hasStreamingInterfaceOrBody()) - return DAG.getConstant(1, DL, VT); - - if (Attrs.hasNonStreamingInterfaceAndBody()) - return DAG.getConstant(0, DL, VT); - - assert(Attrs.hasStreamingCompatibleInterface() && "Unexpected interface"); - +SDValue AArch64TargetLowering::getRuntimePStateSM(SelectionDAG &DAG, + SDValue Chain, SDLoc DL, + EVT VT) const { SDValue Callee = DAG.getExternalSymbol("__arm_sme_state", getPointerTy(DAG.getDataLayout())); Type *Int64Ty = Type::getInt64Ty(*DAG.getContext()); @@ -5409,7 +5445,9 @@ SDValue AArch64TargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op, } case Intrinsic::aarch64_neon_vsri: - case Intrinsic::aarch64_neon_vsli: { + case Intrinsic::aarch64_neon_vsli: + case Intrinsic::aarch64_sve_sri: + case Intrinsic::aarch64_sve_sli: { EVT Ty = Op.getValueType(); if (!Ty.isVector()) @@ -5417,7 +5455,8 @@ SDValue AArch64TargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op, assert(Op.getConstantOperandVal(3) <= Ty.getScalarSizeInBits()); - bool IsShiftRight = IntNo == Intrinsic::aarch64_neon_vsri; + bool IsShiftRight = IntNo == Intrinsic::aarch64_neon_vsri || + IntNo == Intrinsic::aarch64_sve_sri; unsigned Opcode = IsShiftRight ? AArch64ISD::VSRI : AArch64ISD::VSLI; return DAG.getNode(Opcode, dl, Ty, Op.getOperand(1), Op.getOperand(2), Op.getOperand(3)); @@ -6538,18 +6577,33 @@ CCAssignFn *AArch64TargetLowering::CCAssignFnForCall(CallingConv::ID CC, } return CC_AArch64_Win64PCS; case CallingConv::CFGuard_Check: + if (Subtarget->isWindowsArm64EC()) + return CC_AArch64_Arm64EC_CFGuard_Check; return CC_AArch64_Win64_CFGuard_Check; case CallingConv::AArch64_VectorCall: case CallingConv::AArch64_SVE_VectorCall: case CallingConv::AArch64_SME_ABI_Support_Routines_PreserveMost_From_X0: case CallingConv::AArch64_SME_ABI_Support_Routines_PreserveMost_From_X2: return CC_AArch64_AAPCS; + case CallingConv::ARM64EC_Thunk_X64: + return CC_AArch64_Arm64EC_Thunk; + case CallingConv::ARM64EC_Thunk_Native: + return CC_AArch64_Arm64EC_Thunk_Native; } } CCAssignFn * AArch64TargetLowering::CCAssignFnForReturn(CallingConv::ID CC) const { - return RetCC_AArch64_AAPCS; + switch (CC) { + default: + return RetCC_AArch64_AAPCS; + case CallingConv::ARM64EC_Thunk_X64: + return RetCC_AArch64_Arm64EC_Thunk; + case CallingConv::CFGuard_Check: + if (Subtarget->isWindowsArm64EC()) + return RetCC_AArch64_Arm64EC_CFGuard_Check; + return RetCC_AArch64_AAPCS; + } } @@ -6601,6 +6655,8 @@ SDValue AArch64TargetLowering::LowerFormalArguments( const Function &F = MF.getFunction(); MachineFrameInfo &MFI = MF.getFrameInfo(); bool IsWin64 = Subtarget->isCallingConvWin64(F.getCallingConv()); + bool StackViaX4 = CallConv == CallingConv::ARM64EC_Thunk_X64 || + (isVarArg && Subtarget->isWindowsArm64EC()); AArch64FunctionInfo *FuncInfo = MF.getInfo(); SmallVector Outs; @@ -6770,10 +6826,14 @@ SDValue AArch64TargetLowering::LowerFormalArguments( SDValue FIN; MachinePointerInfo PtrInfo; - if (isVarArg && Subtarget->isWindowsArm64EC()) { - // In the ARM64EC varargs convention, fixed arguments on the stack are - // accessed relative to x4, not sp. + if (StackViaX4) { + // In both the ARM64EC varargs convention and the thunk convention, + // arguments on the stack are accessed relative to x4, not sp. In + // the thunk convention, there's an additional offset of 32 bytes + // to account for the shadow store. unsigned ObjOffset = ArgOffset + BEAlign; + if (CallConv == CallingConv::ARM64EC_Thunk_X64) + ObjOffset += 32; Register VReg = MF.addLiveIn(AArch64::X4, &AArch64::GPR64RegClass); SDValue Val = DAG.getCopyFromReg(Chain, DL, VReg, MVT::i64); FIN = DAG.getNode(ISD::ADD, DL, MVT::i64, Val, @@ -6885,9 +6945,18 @@ SDValue AArch64TargetLowering::LowerFormalArguments( // Insert the SMSTART if this is a locally streaming function and // make sure it is Glued to the last CopyFromReg value. if (IsLocallyStreaming) { - Chain = - changeStreamingMode(DAG, DL, /*Enable*/ true, DAG.getRoot(), Glue, - DAG.getConstant(0, DL, MVT::i64), /*Entry*/ true); + SDValue PStateSM; + if (Attrs.hasStreamingCompatibleInterface()) { + PStateSM = getRuntimePStateSM(DAG, Chain, DL, MVT::i64); + Register Reg = MF.getRegInfo().createVirtualRegister( + getRegClassFor(PStateSM.getValueType().getSimpleVT())); + FuncInfo->setPStateSMReg(Reg); + Chain = DAG.getCopyToReg(Chain, DL, Reg, PStateSM); + } else { + PStateSM = DAG.getConstant(0, DL, MVT::i64); + } + Chain = changeStreamingMode(DAG, DL, /*Enable*/ true, Chain, Glue, PStateSM, + /*Entry*/ true); // Ensure that the SMSTART happens after the CopyWithChain such that its // chain result is used. @@ -6940,9 +7009,11 @@ SDValue AArch64TargetLowering::LowerFormalArguments( // On Windows, InReg pointers must be returned, so record the pointer in a // virtual register at the start of the function so it can be returned in the // epilogue. - if (IsWin64) { + if (IsWin64 || F.getCallingConv() == CallingConv::ARM64EC_Thunk_X64) { for (unsigned I = 0, E = Ins.size(); I != E; ++I) { - if (Ins[I].Flags.isInReg() && Ins[I].Flags.isSRet()) { + if ((F.getCallingConv() == CallingConv::ARM64EC_Thunk_X64 || + Ins[I].Flags.isInReg()) && + Ins[I].Flags.isSRet()) { assert(!FuncInfo->getSRetReturnReg()); MVT PtrTy = getPointerTy(DAG.getDataLayout()); @@ -7173,6 +7244,11 @@ static void analyzeCallOperands(const AArch64TargetLowering &TLI, const SmallVector &Outs = CLI.Outs; bool IsCalleeWin64 = Subtarget->isCallingConvWin64(CalleeCC); + // For Arm64EC thunks, allocate 32 extra bytes at the bottom of the stack + // for the shadow store. + if (CalleeCC == CallingConv::ARM64EC_Thunk_X64) + CCInfo.AllocateStack(32, Align(16)); + unsigned NumArgs = Outs.size(); for (unsigned i = 0; i != NumArgs; ++i) { MVT ArgVT = Outs[i].VT; @@ -7601,16 +7677,6 @@ AArch64TargetLowering::LowerCall(CallLoweringInfo &CLI, bool RequiresLazySave = CallerAttrs.requiresLazySave(CalleeAttrs); if (RequiresLazySave) { - SDValue NumZaSaveSlices; - if (!CalleeAttrs.preservesZA()) { - // Set up a lazy save mechanism by storing the runtime live slices - // (worst-case SVL) to the TPIDR2 stack object. - NumZaSaveSlices = DAG.getNode(AArch64ISD::RDSVL, DL, MVT::i64, - DAG.getConstant(1, DL, MVT::i32)); - } else if (CalleeAttrs.preservesZA()) { - NumZaSaveSlices = DAG.getConstant(0, DL, MVT::i64); - } - unsigned TPIDR2Obj = FuncInfo->getLazySaveTPIDR2Obj(); MachinePointerInfo MPI = MachinePointerInfo::getStack(MF, TPIDR2Obj); SDValue TPIDR2ObjAddr = DAG.getFrameIndex(TPIDR2Obj, @@ -7618,6 +7684,8 @@ AArch64TargetLowering::LowerCall(CallLoweringInfo &CLI, SDValue NumZaSaveSlicesAddr = DAG.getNode(ISD::ADD, DL, TPIDR2ObjAddr.getValueType(), TPIDR2ObjAddr, DAG.getConstant(8, DL, TPIDR2ObjAddr.getValueType())); + SDValue NumZaSaveSlices = DAG.getNode(AArch64ISD::RDSVL, DL, MVT::i64, + DAG.getConstant(1, DL, MVT::i32)); Chain = DAG.getTruncStore(Chain, DL, NumZaSaveSlices, NumZaSaveSlicesAddr, MPI, MVT::i16); Chain = DAG.getNode( @@ -7630,22 +7698,19 @@ AArch64TargetLowering::LowerCall(CallLoweringInfo &CLI, CLI.CB) : OptimizationRemarkAnalysis("sme", "SMELazySaveZA", &MF.getFunction()); - DescribeCallsite(R) << " sets up a lazy save for ZA"; - if (CalleeAttrs.preservesZA()) - R << ", but callee preserves ZA, so we request 0 slices to be saved"; - else - R << ", and we request that all slices be saved"; - R << ore::setExtraArgs() - << ore::NV("CalleePreservesZA", CalleeAttrs.preservesZA()); - return R; + return DescribeCallsite(R) << " sets up a lazy save for ZA"; }); } SDValue PStateSM; - std::optional RequiresSMChange = - CallerAttrs.requiresSMChange(CalleeAttrs); + bool RequiresSMChange = CallerAttrs.requiresSMChange(CalleeAttrs); if (RequiresSMChange) { - PStateSM = getPStateSM(DAG, Chain, CallerAttrs, DL, MVT::i64); + if (CallerAttrs.hasStreamingInterfaceOrBody()) + PStateSM = DAG.getConstant(1, DL, MVT::i64); + else if (CallerAttrs.hasNonStreamingInterface()) + PStateSM = DAG.getConstant(0, DL, MVT::i64); + else + PStateSM = getRuntimePStateSM(DAG, Chain, DL, MVT::i64); OptimizationRemarkEmitter ORE(&MF.getFunction()); ORE.emit([&]() { auto R = CLI.CB ? OptimizationRemarkAnalysis("sme", "SMETransition", @@ -7657,6 +7722,34 @@ AArch64TargetLowering::LowerCall(CallLoweringInfo &CLI, }); } + SDValue ZTFrameIdx; + MachineFrameInfo &MFI = MF.getFrameInfo(); + bool ShouldPreserveZT0 = CallerAttrs.requiresPreservingZT0(CalleeAttrs); + + // If the caller has ZT0 state which will not be preserved by the callee, + // spill ZT0 before the call. + if (ShouldPreserveZT0) { + unsigned ZTObj = MFI.CreateSpillStackObject(64, Align(16)); + ZTFrameIdx = DAG.getFrameIndex( + ZTObj, + DAG.getTargetLoweringInfo().getFrameIndexTy(DAG.getDataLayout())); + + Chain = DAG.getNode(AArch64ISD::SAVE_ZT, DL, DAG.getVTList(MVT::Other), + {Chain, DAG.getConstant(0, DL, MVT::i32), ZTFrameIdx}); + } + + // If caller shares ZT0 but the callee is not shared ZA, we need to stop + // PSTATE.ZA before the call if there is no lazy-save active. + bool DisableZA = CallerAttrs.requiresDisablingZABeforeCall(CalleeAttrs); + assert((!DisableZA || !RequiresLazySave) && + "Lazy-save should have PSTATE.SM=1 on entry to the function"); + + if (DisableZA) + Chain = DAG.getNode( + AArch64ISD::SMSTOP, DL, MVT::Other, Chain, + DAG.getTargetConstant((int32_t)(AArch64SVCR::SVCRZA), DL, MVT::i32), + DAG.getConstant(0, DL, MVT::i64), DAG.getConstant(1, DL, MVT::i64)); + // Adjust the stack pointer for the new arguments... // These operations are automatically eliminated by the prolog/epilog pass if (!IsSibCall) @@ -7912,8 +8005,9 @@ AArch64TargetLowering::LowerCall(CallLoweringInfo &CLI, SDValue InGlue; if (RequiresSMChange) { - SDValue NewChain = changeStreamingMode(DAG, DL, *RequiresSMChange, Chain, - InGlue, PStateSM, true); + SDValue NewChain = + changeStreamingMode(DAG, DL, CalleeAttrs.hasStreamingInterface(), Chain, + InGlue, PStateSM, true); Chain = NewChain.getValue(0); InGlue = NewChain.getValue(1); } @@ -7938,7 +8032,7 @@ AArch64TargetLowering::LowerCall(CallLoweringInfo &CLI, Callee = DAG.getNode(AArch64ISD::LOADgot, DL, PtrVT, Callee); } else { const GlobalValue *GV = G->getGlobal(); - Callee = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, 0); + Callee = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, OpFlags); } } else if (auto *S = dyn_cast(Callee)) { if (getTargetMachine().getCodeModel() == CodeModel::Large && @@ -8033,8 +8127,11 @@ AArch64TargetLowering::LowerCall(CallLoweringInfo &CLI, Function *ARCFn = *objcarc::getAttachedARCFunction(CLI.CB); auto GA = DAG.getTargetGlobalAddress(ARCFn, DL, PtrVT); Ops.insert(Ops.begin() + 1, GA); - } else if (GuardWithBTI) + } else if (CallConv == CallingConv::ARM64EC_Thunk_X64) { + CallOpc = AArch64ISD::CALL_ARM64EC_TO_X64; + } else if (GuardWithBTI) { CallOpc = AArch64ISD::CALL_BTI; + } // Returns a chain and a flag for retval copy to use. Chain = DAG.getNode(CallOpc, DL, NodeTys, Ops); @@ -8063,39 +8160,44 @@ AArch64TargetLowering::LowerCall(CallLoweringInfo &CLI, if (RequiresSMChange) { assert(PStateSM && "Expected a PStateSM to be set"); - Result = changeStreamingMode(DAG, DL, !*RequiresSMChange, Result, InGlue, - PStateSM, false); + Result = changeStreamingMode(DAG, DL, !CalleeAttrs.hasStreamingInterface(), + Result, InGlue, PStateSM, false); } + if (CallerAttrs.requiresEnablingZAAfterCall(CalleeAttrs)) + // Unconditionally resume ZA. + Result = DAG.getNode( + AArch64ISD::SMSTART, DL, MVT::Other, Result, + DAG.getTargetConstant((int32_t)(AArch64SVCR::SVCRZA), DL, MVT::i32), + DAG.getConstant(0, DL, MVT::i64), DAG.getConstant(1, DL, MVT::i64)); + + if (ShouldPreserveZT0) + Result = + DAG.getNode(AArch64ISD::RESTORE_ZT, DL, DAG.getVTList(MVT::Other), + {Result, DAG.getConstant(0, DL, MVT::i32), ZTFrameIdx}); + if (RequiresLazySave) { - if (!CalleeAttrs.preservesZA()) { - // Unconditionally resume ZA. - Result = DAG.getNode( - AArch64ISD::SMSTART, DL, MVT::Other, Result, - DAG.getTargetConstant((int32_t)(AArch64SVCR::SVCRZA), DL, MVT::i32), - DAG.getConstant(0, DL, MVT::i64), DAG.getConstant(1, DL, MVT::i64)); + // Conditionally restore the lazy save using a pseudo node. + unsigned FI = FuncInfo->getLazySaveTPIDR2Obj(); + SDValue RegMask = DAG.getRegisterMask( + TRI->SMEABISupportRoutinesCallPreservedMaskFromX0()); + SDValue RestoreRoutine = DAG.getTargetExternalSymbol( + "__arm_tpidr2_restore", getPointerTy(DAG.getDataLayout())); + SDValue TPIDR2_EL0 = DAG.getNode( + ISD::INTRINSIC_W_CHAIN, DL, MVT::i64, Result, + DAG.getConstant(Intrinsic::aarch64_sme_get_tpidr2, DL, MVT::i32)); - // Conditionally restore the lazy save using a pseudo node. - unsigned FI = FuncInfo->getLazySaveTPIDR2Obj(); - SDValue RegMask = DAG.getRegisterMask( - TRI->SMEABISupportRoutinesCallPreservedMaskFromX0()); - SDValue RestoreRoutine = DAG.getTargetExternalSymbol( - "__arm_tpidr2_restore", getPointerTy(DAG.getDataLayout())); - SDValue TPIDR2_EL0 = DAG.getNode( - ISD::INTRINSIC_W_CHAIN, DL, MVT::i64, Result, - DAG.getConstant(Intrinsic::aarch64_sme_get_tpidr2, DL, MVT::i32)); + // Copy the address of the TPIDR2 block into X0 before 'calling' the + // RESTORE_ZA pseudo. + SDValue Glue; + SDValue TPIDR2Block = DAG.getFrameIndex( + FI, DAG.getTargetLoweringInfo().getFrameIndexTy(DAG.getDataLayout())); + Result = DAG.getCopyToReg(Result, DL, AArch64::X0, TPIDR2Block, Glue); + Result = + DAG.getNode(AArch64ISD::RESTORE_ZA, DL, MVT::Other, + {Result, TPIDR2_EL0, DAG.getRegister(AArch64::X0, MVT::i64), + RestoreRoutine, RegMask, Result.getValue(1)}); - // Copy the address of the TPIDR2 block into X0 before 'calling' the - // RESTORE_ZA pseudo. - SDValue Glue; - SDValue TPIDR2Block = DAG.getFrameIndex( - FI, DAG.getTargetLoweringInfo().getFrameIndexTy(DAG.getDataLayout())); - Result = DAG.getCopyToReg(Result, DL, AArch64::X0, TPIDR2Block, Glue); - Result = DAG.getNode(AArch64ISD::RESTORE_ZA, DL, MVT::Other, - {Result, TPIDR2_EL0, - DAG.getRegister(AArch64::X0, MVT::i64), - RestoreRoutine, RegMask, Result.getValue(1)}); - } // Finally reset the TPIDR2_EL0 register to 0. Result = DAG.getNode( ISD::INTRINSIC_VOID, DL, MVT::Other, Result, @@ -8103,7 +8205,7 @@ AArch64TargetLowering::LowerCall(CallLoweringInfo &CLI, DAG.getConstant(0, DL, MVT::i64)); } - if (RequiresSMChange || RequiresLazySave) { + if (RequiresSMChange || RequiresLazySave || ShouldPreserveZT0) { for (unsigned I = 0; I < InVals.size(); ++I) { // The smstart/smstop is chained as part of the call, but when the // resulting chain is discarded (which happens when the call is not part @@ -8198,9 +8300,17 @@ AArch64TargetLowering::LowerReturn(SDValue Chain, CallingConv::ID CallConv, // Emit SMSTOP before returning from a locally streaming function SMEAttrs FuncAttrs(MF.getFunction()); if (FuncAttrs.hasStreamingBody() && !FuncAttrs.hasStreamingInterface()) { - Chain = changeStreamingMode( - DAG, DL, /*Enable*/ false, Chain, /*Glue*/ SDValue(), - DAG.getConstant(1, DL, MVT::i64), /*Entry*/ true); + if (FuncAttrs.hasStreamingCompatibleInterface()) { + Register Reg = FuncInfo->getPStateSMReg(); + assert(Reg.isValid() && "PStateSM Register is invalid"); + SDValue PStateSM = DAG.getCopyFromReg(Chain, DL, Reg, MVT::i64); + Chain = + changeStreamingMode(DAG, DL, /*Enable*/ false, Chain, + /*Glue*/ SDValue(), PStateSM, /*Entry*/ false); + } else + Chain = changeStreamingMode( + DAG, DL, /*Enable*/ false, Chain, + /*Glue*/ SDValue(), DAG.getConstant(1, DL, MVT::i64), /*Entry*/ true); Glue = Chain.getValue(1); } @@ -8221,6 +8331,8 @@ AArch64TargetLowering::LowerReturn(SDValue Chain, CallingConv::ID CallConv, getPointerTy(MF.getDataLayout())); unsigned RetValReg = AArch64::X0; + if (CallConv == CallingConv::ARM64EC_Thunk_X64) + RetValReg = AArch64::X8; Chain = DAG.getCopyToReg(Chain, DL, RetValReg, Val, Glue); Glue = Chain.getValue(1); @@ -8246,6 +8358,21 @@ AArch64TargetLowering::LowerReturn(SDValue Chain, CallingConv::ID CallConv, if (Glue.getNode()) RetOps.push_back(Glue); + if (CallConv == CallingConv::ARM64EC_Thunk_X64) { + // ARM64EC entry thunks use a special return sequence: instead of a regular + // "ret" instruction, they need to explicitly call the emulator. + EVT PtrVT = getPointerTy(DAG.getDataLayout()); + SDValue Arm64ECRetDest = + DAG.getExternalSymbol("__os_arm64x_dispatch_ret", PtrVT); + Arm64ECRetDest = + getAddr(cast(Arm64ECRetDest), DAG, 0); + Arm64ECRetDest = DAG.getLoad(PtrVT, DL, DAG.getEntryNode(), Arm64ECRetDest, + MachinePointerInfo()); + RetOps.insert(RetOps.begin() + 1, Arm64ECRetDest); + RetOps.insert(RetOps.begin() + 2, DAG.getTargetConstant(0, DL, MVT::i32)); + return DAG.getNode(AArch64ISD::TC_RETURN, DL, MVT::Other, RetOps); + } + return DAG.getNode(AArch64ISD::RET_GLUE, DL, MVT::Other, RetOps); } @@ -8279,6 +8406,12 @@ SDValue AArch64TargetLowering::getTargetNode(BlockAddressSDNode* N, EVT Ty, return DAG.getTargetBlockAddress(N->getBlockAddress(), Ty, 0, Flag); } +SDValue AArch64TargetLowering::getTargetNode(ExternalSymbolSDNode *N, EVT Ty, + SelectionDAG &DAG, + unsigned Flag) const { + return DAG.getTargetExternalSymbol(N->getSymbol(), Ty, Flag); +} + // (loadGOT sym) template SDValue AArch64TargetLowering::getGOT(NodeTy *N, SelectionDAG &DAG, @@ -8360,8 +8493,7 @@ SDValue AArch64TargetLowering::LowerGlobalAddress(SDValue Op, } EVT PtrVT = getPointerTy(DAG.getDataLayout()); SDLoc DL(GN); - if (OpFlags & (AArch64II::MO_DLLIMPORT | AArch64II::MO_DLLIMPORTAUX | - AArch64II::MO_COFFSTUB)) + if (OpFlags & (AArch64II::MO_DLLIMPORT | AArch64II::MO_COFFSTUB)) Result = DAG.getLoad(PtrVT, DL, DAG.getEntryNode(), Result, MachinePointerInfo::getGOT(DAG.getMachineFunction())); return Result; @@ -12542,6 +12674,53 @@ static bool isAllConstantBuildVector(const SDValue &PotentialBVec, return true; } +static bool isAllInactivePredicate(SDValue N) { + // Look through cast. + while (N.getOpcode() == AArch64ISD::REINTERPRET_CAST) + N = N.getOperand(0); + + return ISD::isConstantSplatVectorAllZeros(N.getNode()); +} + +static bool isAllActivePredicate(SelectionDAG &DAG, SDValue N) { + unsigned NumElts = N.getValueType().getVectorMinNumElements(); + + // Look through cast. + while (N.getOpcode() == AArch64ISD::REINTERPRET_CAST) { + N = N.getOperand(0); + // When reinterpreting from a type with fewer elements the "new" elements + // are not active, so bail if they're likely to be used. + if (N.getValueType().getVectorMinNumElements() < NumElts) + return false; + } + + if (ISD::isConstantSplatVectorAllOnes(N.getNode())) + return true; + + // "ptrue p., all" can be considered all active when is the same size + // or smaller than the implicit element type represented by N. + // NOTE: A larger element count implies a smaller element type. + if (N.getOpcode() == AArch64ISD::PTRUE && + N.getConstantOperandVal(0) == AArch64SVEPredPattern::all) + return N.getValueType().getVectorMinNumElements() >= NumElts; + + // If we're compiling for a specific vector-length, we can check if the + // pattern's VL equals that of the scalable vector at runtime. + if (N.getOpcode() == AArch64ISD::PTRUE) { + const auto &Subtarget = DAG.getSubtarget(); + unsigned MinSVESize = Subtarget.getMinSVEVectorSizeInBits(); + unsigned MaxSVESize = Subtarget.getMaxSVEVectorSizeInBits(); + if (MaxSVESize && MinSVESize == MaxSVESize) { + unsigned VScale = MaxSVESize / AArch64::SVEBitsPerBlock; + unsigned PatNumElts = + getNumElementsFromSVEPredPattern(N.getConstantOperandVal(0)); + return PatNumElts == (NumElts * VScale); + } + } + + return false; +} + // Attempt to form a vector S[LR]I from (or (and X, BvecC1), (lsl Y, C2)), // to (SLI X, Y, C2), where X and Y have matching vector types, BvecC1 is a // BUILD_VECTORs with constant element C1, C2 is a constant, and: @@ -12567,59 +12746,78 @@ static SDValue tryLowerToSLI(SDNode *N, SelectionDAG &DAG) { // Is one of the operands an AND or a BICi? The AND may have been optimised to // a BICi in order to use an immediate instead of a register. // Is the other operand an shl or lshr? This will have been turned into: - // AArch64ISD::VSHL vector, #shift or AArch64ISD::VLSHR vector, #shift. + // AArch64ISD::VSHL vector, #shift or AArch64ISD::VLSHR vector, #shift + // or (AArch64ISD::SHL_PRED || AArch64ISD::SRL_PRED) mask, vector, #shiftVec. if ((FirstOpc == ISD::AND || FirstOpc == AArch64ISD::BICi) && - (SecondOpc == AArch64ISD::VSHL || SecondOpc == AArch64ISD::VLSHR)) { + (SecondOpc == AArch64ISD::VSHL || SecondOpc == AArch64ISD::VLSHR || + SecondOpc == AArch64ISD::SHL_PRED || + SecondOpc == AArch64ISD::SRL_PRED)) { And = FirstOp; Shift = SecondOp; } else if ((SecondOpc == ISD::AND || SecondOpc == AArch64ISD::BICi) && - (FirstOpc == AArch64ISD::VSHL || FirstOpc == AArch64ISD::VLSHR)) { + (FirstOpc == AArch64ISD::VSHL || FirstOpc == AArch64ISD::VLSHR || + FirstOpc == AArch64ISD::SHL_PRED || + FirstOpc == AArch64ISD::SRL_PRED)) { And = SecondOp; Shift = FirstOp; } else return SDValue(); bool IsAnd = And.getOpcode() == ISD::AND; - bool IsShiftRight = Shift.getOpcode() == AArch64ISD::VLSHR; + bool IsShiftRight = Shift.getOpcode() == AArch64ISD::VLSHR || + Shift.getOpcode() == AArch64ISD::SRL_PRED; + bool ShiftHasPredOp = Shift.getOpcode() == AArch64ISD::SHL_PRED || + Shift.getOpcode() == AArch64ISD::SRL_PRED; - // Is the shift amount constant? - ConstantSDNode *C2node = dyn_cast(Shift.getOperand(1)); - if (!C2node) + // Is the shift amount constant and are all lanes active? + uint64_t C2; + if (ShiftHasPredOp) { + if (!isAllActivePredicate(DAG, Shift.getOperand(0))) + return SDValue(); + APInt C; + if (!ISD::isConstantSplatVector(Shift.getOperand(2).getNode(), C)) + return SDValue(); + C2 = C.getZExtValue(); + } else if (ConstantSDNode *C2node = + dyn_cast(Shift.getOperand(1))) + C2 = C2node->getZExtValue(); + else return SDValue(); - uint64_t C1; + APInt C1AsAPInt; + unsigned ElemSizeInBits = VT.getScalarSizeInBits(); if (IsAnd) { // Is the and mask vector all constant? - if (!isAllConstantBuildVector(And.getOperand(1), C1)) + if (!ISD::isConstantSplatVector(And.getOperand(1).getNode(), C1AsAPInt)) return SDValue(); } else { // Reconstruct the corresponding AND immediate from the two BICi immediates. ConstantSDNode *C1nodeImm = dyn_cast(And.getOperand(1)); ConstantSDNode *C1nodeShift = dyn_cast(And.getOperand(2)); assert(C1nodeImm && C1nodeShift); - C1 = ~(C1nodeImm->getZExtValue() << C1nodeShift->getZExtValue()); + C1AsAPInt = ~(C1nodeImm->getAPIntValue() << C1nodeShift->getAPIntValue()); + C1AsAPInt = C1AsAPInt.zextOrTrunc(ElemSizeInBits); } // Is C1 == ~(Ones(ElemSizeInBits) << C2) or // C1 == ~(Ones(ElemSizeInBits) >> C2), taking into account // how much one can shift elements of a particular size? - uint64_t C2 = C2node->getZExtValue(); - unsigned ElemSizeInBits = VT.getScalarSizeInBits(); if (C2 > ElemSizeInBits) return SDValue(); - APInt C1AsAPInt(ElemSizeInBits, C1); APInt RequiredC1 = IsShiftRight ? APInt::getHighBitsSet(ElemSizeInBits, C2) : APInt::getLowBitsSet(ElemSizeInBits, C2); if (C1AsAPInt != RequiredC1) return SDValue(); SDValue X = And.getOperand(0); - SDValue Y = Shift.getOperand(0); + SDValue Y = ShiftHasPredOp ? Shift.getOperand(1) : Shift.getOperand(0); + SDValue Imm = ShiftHasPredOp ? DAG.getTargetConstant(C2, DL, MVT::i32) + : Shift.getOperand(1); unsigned Inst = IsShiftRight ? AArch64ISD::VSRI : AArch64ISD::VSLI; - SDValue ResultSLI = DAG.getNode(Inst, DL, VT, X, Y, Shift.getOperand(1)); + SDValue ResultSLI = DAG.getNode(Inst, DL, VT, X, Y, Imm); LLVM_DEBUG(dbgs() << "aarch64-lower: transformed: \n"); LLVM_DEBUG(N->dump(&DAG)); @@ -12641,6 +12839,8 @@ SDValue AArch64TargetLowering::LowerVectorOR(SDValue Op, return Res; EVT VT = Op.getValueType(); + if (VT.isScalableVector()) + return Op; SDValue LHS = Op.getOperand(0); BuildVectorSDNode *BVN = @@ -16494,8 +16694,7 @@ static SDValue performUADDVAddCombine(SDValue A, SelectionDAG &DAG) { auto DetectAddExtract = [&](SDValue A) { // Look for add(zext(extract_lo(x)), zext(extract_hi(x))), returning // UADDLP(x) if found. - if (A.getOpcode() != ISD::ADD) - return SDValue(); + assert(A.getOpcode() == ISD::ADD); EVT VT = A.getValueType(); SDValue Op0 = A.getOperand(0); SDValue Op1 = A.getOperand(1); @@ -16538,11 +16737,54 @@ static SDValue performUADDVAddCombine(SDValue A, SelectionDAG &DAG) { return SDValue(); } +// We can convert a UADDV(add(zext(64-bit source), zext(64-bit source))) into +// UADDLV(concat), where the concat represents the 64-bit zext sources. +static SDValue performUADDVZextCombine(SDValue A, SelectionDAG &DAG) { + // Look for add(zext(64-bit source), zext(64-bit source)), returning + // UADDLV(concat(zext, zext)) if found. + assert(A.getOpcode() == ISD::ADD); + EVT VT = A.getValueType(); + if (VT != MVT::v8i16 && VT != MVT::v4i32 && VT != MVT::v2i64) + return SDValue(); + SDValue Op0 = A.getOperand(0); + SDValue Op1 = A.getOperand(1); + if (Op0.getOpcode() != ISD::ZERO_EXTEND || Op0.getOpcode() != Op1.getOpcode()) + return SDValue(); + SDValue Ext0 = Op0.getOperand(0); + SDValue Ext1 = Op1.getOperand(0); + EVT ExtVT0 = Ext0.getValueType(); + EVT ExtVT1 = Ext1.getValueType(); + // Check zext VTs are the same and 64-bit length. + if (ExtVT0 != ExtVT1 || + VT.getScalarSizeInBits() != (2 * ExtVT0.getScalarSizeInBits())) + return SDValue(); + // Get VT for concat of zext sources. + EVT PairVT = ExtVT0.getDoubleNumVectorElementsVT(*DAG.getContext()); + SDValue Concat = + DAG.getNode(ISD::CONCAT_VECTORS, SDLoc(A), PairVT, Ext0, Ext1); + + switch (VT.getSimpleVT().SimpleTy) { + case MVT::v2i64: + case MVT::v4i32: + return DAG.getNode(AArch64ISD::UADDLV, SDLoc(A), VT, Concat); + case MVT::v8i16: { + SDValue Uaddlv = + DAG.getNode(AArch64ISD::UADDLV, SDLoc(A), MVT::v4i32, Concat); + return DAG.getNode(AArch64ISD::NVCAST, SDLoc(A), MVT::v8i16, Uaddlv); + } + default: + llvm_unreachable("Unhandled vector type"); + } +} + static SDValue performUADDVCombine(SDNode *N, SelectionDAG &DAG) { SDValue A = N->getOperand(0); - if (A.getOpcode() == ISD::ADD) + if (A.getOpcode() == ISD::ADD) { if (SDValue R = performUADDVAddCombine(A, DAG)) return DAG.getNode(N->getOpcode(), SDLoc(N), N->getValueType(0), R); + else if (SDValue R = performUADDVZextCombine(A, DAG)) + return R; + } return SDValue(); } @@ -17432,53 +17674,6 @@ static bool isConstantSplatVectorMaskForType(SDNode *N, EVT MemVT) { return false; } -static bool isAllInactivePredicate(SDValue N) { - // Look through cast. - while (N.getOpcode() == AArch64ISD::REINTERPRET_CAST) - N = N.getOperand(0); - - return ISD::isConstantSplatVectorAllZeros(N.getNode()); -} - -static bool isAllActivePredicate(SelectionDAG &DAG, SDValue N) { - unsigned NumElts = N.getValueType().getVectorMinNumElements(); - - // Look through cast. - while (N.getOpcode() == AArch64ISD::REINTERPRET_CAST) { - N = N.getOperand(0); - // When reinterpreting from a type with fewer elements the "new" elements - // are not active, so bail if they're likely to be used. - if (N.getValueType().getVectorMinNumElements() < NumElts) - return false; - } - - if (ISD::isConstantSplatVectorAllOnes(N.getNode())) - return true; - - // "ptrue p., all" can be considered all active when is the same size - // or smaller than the implicit element type represented by N. - // NOTE: A larger element count implies a smaller element type. - if (N.getOpcode() == AArch64ISD::PTRUE && - N.getConstantOperandVal(0) == AArch64SVEPredPattern::all) - return N.getValueType().getVectorMinNumElements() >= NumElts; - - // If we're compiling for a specific vector-length, we can check if the - // pattern's VL equals that of the scalable vector at runtime. - if (N.getOpcode() == AArch64ISD::PTRUE) { - const auto &Subtarget = DAG.getSubtarget(); - unsigned MinSVESize = Subtarget.getMinSVEVectorSizeInBits(); - unsigned MaxSVESize = Subtarget.getMaxSVEVectorSizeInBits(); - if (MaxSVESize && MinSVESize == MaxSVESize) { - unsigned VScale = MaxSVESize / AArch64::SVEBitsPerBlock; - unsigned PatNumElts = - getNumElementsFromSVEPredPattern(N.getConstantOperandVal(0)); - return PatNumElts == (NumElts * VScale); - } - } - - return false; -} - static SDValue performReinterpretCastCombine(SDNode *N) { SDValue LeafOp = SDValue(N, 0); SDValue Op = N->getOperand(0); @@ -22256,8 +22451,8 @@ static SDValue performSETCCCombine(SDNode *N, isNullConstant(LHS->getOperand(0)) && isOneConstant(LHS->getOperand(1)) && LHS->hasOneUse()) { // Invert CSEL's condition. - auto *OpCC = cast(LHS.getOperand(2)); - auto OldCond = static_cast(OpCC->getZExtValue()); + auto OldCond = + static_cast(LHS.getConstantOperandVal(2)); auto NewCond = getInvertedCondCode(OldCond); // csel 0, 1, !cond, X @@ -23951,6 +24146,14 @@ SDValue AArch64TargetLowering::PerformDAGCombine(SDNode *N, return DAG.getMergeValues( {A, DAG.getZExtOrTrunc(B, DL, MVT::i1), A.getValue(2)}, DL); } + case Intrinsic::aarch64_sme_ldr_zt: + return DAG.getNode(AArch64ISD::RESTORE_ZT, SDLoc(N), + DAG.getVTList(MVT::Other), N->getOperand(0), + N->getOperand(2), N->getOperand(3)); + case Intrinsic::aarch64_sme_str_zt: + return DAG.getNode(AArch64ISD::SAVE_ZT, SDLoc(N), + DAG.getVTList(MVT::Other), N->getOperand(0), + N->getOperand(2), N->getOperand(3)); default: break; } @@ -24689,8 +24892,8 @@ void AArch64TargetLowering::ReplaceNodeResults( assert((VT == MVT::i8 || VT == MVT::i16) && "custom lowering for unexpected type"); - ConstantSDNode *CN = cast(N->getOperand(0)); - Intrinsic::ID IntID = static_cast(CN->getZExtValue()); + Intrinsic::ID IntID = + static_cast(N->getConstantOperandVal(0)); switch (IntID) { default: return; @@ -25402,7 +25605,7 @@ bool AArch64TargetLowering::shouldLocalize( RematCost += AdditionalCost; Register Reg = MI.getOperand(0).getReg(); unsigned MaxUses = maxUses(RematCost); - // Don't pass UINT_MAX sentinal value to hasAtMostUserInstrs(). + // Don't pass UINT_MAX sentinel value to hasAtMostUserInstrs(). if (MaxUses == std::numeric_limits::max()) --MaxUses; return MRI.hasAtMostUserInstrs(Reg, MaxUses); @@ -25437,8 +25640,7 @@ bool AArch64TargetLowering::fallBackToDAGISel(const Instruction &Inst) const { if (auto *Base = dyn_cast(&Inst)) { auto CallerAttrs = SMEAttrs(*Inst.getFunction()); auto CalleeAttrs = SMEAttrs(*Base); - if (CallerAttrs.requiresSMChange(CalleeAttrs, - /*BodyOverridesInterface=*/false) || + if (CallerAttrs.requiresSMChange(CalleeAttrs) || CallerAttrs.requiresLazySave(CalleeAttrs)) return true; } diff --git a/llvm/lib/Target/AArch64/AArch64ISelLowering.h b/llvm/lib/Target/AArch64/AArch64ISelLowering.h index 6ddbcd41dcb..6505931e17e 100644 --- a/llvm/lib/Target/AArch64/AArch64ISelLowering.h +++ b/llvm/lib/Target/AArch64/AArch64ISelLowering.h @@ -61,6 +61,11 @@ enum NodeType : unsigned { SMSTART, SMSTOP, RESTORE_ZA, + RESTORE_ZT, + SAVE_ZT, + + // A call with the callee in x16, i.e. "blr x16". + CALL_ARM64EC_TO_X64, // Produces the full sequence of instructions for getting the thread pointer // offset of a variable into X0, using the TLSDesc model. @@ -248,6 +253,7 @@ enum NodeType : unsigned { // Unsigned sum Long across Vector UADDLV, + SADDLV, // Add Pairwise of two vectors ADDP, @@ -1068,6 +1074,8 @@ private: unsigned Flag) const; SDValue getTargetNode(BlockAddressSDNode *N, EVT Ty, SelectionDAG &DAG, unsigned Flag) const; + SDValue getTargetNode(ExternalSymbolSDNode *N, EVT Ty, SelectionDAG &DAG, + unsigned Flag) const; template SDValue getGOT(NodeTy *N, SelectionDAG &DAG, unsigned Flags = 0) const; template @@ -1289,10 +1297,10 @@ private: // This function does not handle predicate bitcasts. SDValue getSVESafeBitCast(EVT VT, SDValue Op, SelectionDAG &DAG) const; - // Returns the runtime value for PSTATE.SM. When the function is streaming- - // compatible, this generates a call to __arm_sme_state. - SDValue getPStateSM(SelectionDAG &DAG, SDValue Chain, SMEAttrs Attrs, - SDLoc DL, EVT VT) const; + // Returns the runtime value for PSTATE.SM by generating a call to + // __arm_sme_state. + SDValue getRuntimePStateSM(SelectionDAG &DAG, SDValue Chain, SDLoc DL, + EVT VT) const; bool preferScalarizeSplat(SDNode *N) const override; diff --git a/llvm/lib/Target/AArch64/AArch64InstrGISel.td b/llvm/lib/Target/AArch64/AArch64InstrGISel.td index 1c88456560d..58ca52f37b6 100644 --- a/llvm/lib/Target/AArch64/AArch64InstrGISel.td +++ b/llvm/lib/Target/AArch64/AArch64InstrGISel.td @@ -227,6 +227,30 @@ def G_SMULL : AArch64GenericInstruction { let hasSideEffects = 0; } +def G_UADDLP : AArch64GenericInstruction { + let OutOperandList = (outs type0:$dst); + let InOperandList = (ins type0:$src1); + let hasSideEffects = 0; +} + +def G_SADDLP : AArch64GenericInstruction { + let OutOperandList = (outs type0:$dst); + let InOperandList = (ins type0:$src1); + let hasSideEffects = 0; +} + +def G_UADDLV : AArch64GenericInstruction { + let OutOperandList = (outs type0:$dst); + let InOperandList = (ins type0:$src1); + let hasSideEffects = 0; +} + +def G_SADDLV : AArch64GenericInstruction { + let OutOperandList = (outs type0:$dst); + let InOperandList = (ins type0:$src1); + let hasSideEffects = 0; +} + def G_UDOT : AArch64GenericInstruction { let OutOperandList = (outs type0:$dst); let InOperandList = (ins type0:$src1, type0:$src2, type0:$src3); @@ -282,6 +306,12 @@ def : GINodeEquiv; def : GINodeEquiv; def : GINodeEquiv; +def : GINodeEquiv; +def : GINodeEquiv; + +def : GINodeEquiv; +def : GINodeEquiv; + def : GINodeEquiv; def : GINodeEquiv; diff --git a/llvm/lib/Target/AArch64/AArch64InstrInfo.cpp b/llvm/lib/Target/AArch64/AArch64InstrInfo.cpp index 42b7a641803..2e8d8c63d6b 100644 --- a/llvm/lib/Target/AArch64/AArch64InstrInfo.cpp +++ b/llvm/lib/Target/AArch64/AArch64InstrInfo.cpp @@ -1068,6 +1068,8 @@ bool AArch64InstrInfo::isSEHInstruction(const MachineInstr &MI) { case AArch64::SEH_EpilogStart: case AArch64::SEH_EpilogEnd: case AArch64::SEH_PACSignLR: + case AArch64::SEH_SaveAnyRegQP: + case AArch64::SEH_SaveAnyRegQPX: return true; } } @@ -8067,9 +8069,10 @@ AArch64InstrInfo::getSerializableBitmaskMachineOperandTargetFlags() const { {MO_S, "aarch64-s"}, {MO_TLS, "aarch64-tls"}, {MO_DLLIMPORT, "aarch64-dllimport"}, - {MO_DLLIMPORTAUX, "aarch64-dllimportaux"}, {MO_PREL, "aarch64-prel"}, - {MO_TAGGED, "aarch64-tagged"}}; + {MO_TAGGED, "aarch64-tagged"}, + {MO_ARM64EC_CALLMANGLE, "aarch64-arm64ec-callmangle"}, + }; return ArrayRef(TargetFlags); } @@ -8227,11 +8230,11 @@ std::optional AArch64InstrInfo::getOutliningCandidateInfo( std::vector &RepeatedSequenceLocs) const { outliner::Candidate &FirstCand = RepeatedSequenceLocs[0]; - unsigned SequenceSize = - std::accumulate(FirstCand.front(), std::next(FirstCand.back()), 0, - [this](unsigned Sum, const MachineInstr &MI) { - return Sum + getInstSizeInBytes(MI); - }); + + unsigned SequenceSize = 0; + for (auto &MI : FirstCand) + SequenceSize += getInstSizeInBytes(MI); + unsigned NumBytesToCreateFrame = 0; // We only allow outlining for functions having exactly matching return @@ -8284,7 +8287,7 @@ AArch64InstrInfo::getOutliningCandidateInfo( AArch64PAuth::getCheckerSizeInBytes(LRCheckMethod); // Checking the authenticated LR value may significantly impact // SequenceSize, so account for it for more precise results. - if (isTailCallReturnInst(*RepeatedSequenceLocs[0].back())) + if (isTailCallReturnInst(RepeatedSequenceLocs[0].back())) SequenceSize += NumBytesToCheckLRInTCEpilogue; // We have to check if sp modifying instructions would get outlined. @@ -8293,37 +8296,36 @@ AArch64InstrInfo::getOutliningCandidateInfo( // are not auto hasIllegalSPModification = [&TRI](outliner::Candidate &C) { int SPValue = 0; - MachineBasicBlock::iterator MBBI = C.front(); - for (;;) { - if (MBBI->modifiesRegister(AArch64::SP, &TRI)) { - switch (MBBI->getOpcode()) { + for (auto &MI : C) { + if (MI.modifiesRegister(AArch64::SP, &TRI)) { + switch (MI.getOpcode()) { case AArch64::ADDXri: case AArch64::ADDWri: - assert(MBBI->getNumOperands() == 4 && "Wrong number of operands"); - assert(MBBI->getOperand(2).isImm() && + assert(MI.getNumOperands() == 4 && "Wrong number of operands"); + assert(MI.getOperand(2).isImm() && "Expected operand to be immediate"); - assert(MBBI->getOperand(1).isReg() && + assert(MI.getOperand(1).isReg() && "Expected operand to be a register"); // Check if the add just increments sp. If so, we search for // matching sub instructions that decrement sp. If not, the // modification is illegal - if (MBBI->getOperand(1).getReg() == AArch64::SP) - SPValue += MBBI->getOperand(2).getImm(); + if (MI.getOperand(1).getReg() == AArch64::SP) + SPValue += MI.getOperand(2).getImm(); else return true; break; case AArch64::SUBXri: case AArch64::SUBWri: - assert(MBBI->getNumOperands() == 4 && "Wrong number of operands"); - assert(MBBI->getOperand(2).isImm() && + assert(MI.getNumOperands() == 4 && "Wrong number of operands"); + assert(MI.getOperand(2).isImm() && "Expected operand to be immediate"); - assert(MBBI->getOperand(1).isReg() && + assert(MI.getOperand(1).isReg() && "Expected operand to be a register"); // Check if the sub just decrements sp. If so, we search for // matching add instructions that increment sp. If not, the // modification is illegal - if (MBBI->getOperand(1).getReg() == AArch64::SP) - SPValue -= MBBI->getOperand(2).getImm(); + if (MI.getOperand(1).getReg() == AArch64::SP) + SPValue -= MI.getOperand(2).getImm(); else return true; break; @@ -8331,9 +8333,6 @@ AArch64InstrInfo::getOutliningCandidateInfo( return true; } } - if (MBBI == C.back()) - break; - ++MBBI; } if (SPValue) return true; @@ -8354,7 +8353,7 @@ AArch64InstrInfo::getOutliningCandidateInfo( for (outliner::Candidate &C : RepeatedSequenceLocs) FlagsSetInAll &= C.Flags; - unsigned LastInstrOpcode = RepeatedSequenceLocs[0].back()->getOpcode(); + unsigned LastInstrOpcode = RepeatedSequenceLocs[0].back().getOpcode(); // Helper lambda which sets call information for every candidate. auto SetCandidateCallInfo = @@ -8373,8 +8372,7 @@ AArch64InstrInfo::getOutliningCandidateInfo( // We check to see if CFI Instructions are present, and if they are // we find the number of CFI Instructions in the candidates. unsigned CFICount = 0; - for (auto &I : make_range(RepeatedSequenceLocs[0].front(), - std::next(RepeatedSequenceLocs[0].back()))) { + for (auto &I : RepeatedSequenceLocs[0]) { if (I.isCFIInstruction()) CFICount++; } @@ -8449,12 +8447,11 @@ AArch64InstrInfo::getOutliningCandidateInfo( // True if it's possible to fix up each stack instruction in this sequence. // Important for frames/call variants that modify the stack. - bool AllStackInstrsSafe = std::all_of( - FirstCand.front(), std::next(FirstCand.back()), IsSafeToFixup); + bool AllStackInstrsSafe = llvm::all_of(FirstCand, IsSafeToFixup); // If the last instruction in any candidate is a terminator, then we should // tail call all of the candidates. - if (RepeatedSequenceLocs[0].back()->isTerminator()) { + if (RepeatedSequenceLocs[0].back().isTerminator()) { FrameID = MachineOutlinerTailCall; NumBytesToCreateFrame = 0; unsigned NumBytesForCall = 4 + NumBytesToCheckLRInTCEpilogue; @@ -8580,9 +8577,8 @@ AArch64InstrInfo::getOutliningCandidateInfo( // if (FlagsSetInAll & MachineOutlinerMBBFlags::HasCalls) { erase_if(RepeatedSequenceLocs, [this, &TRI](outliner::Candidate &C) { - return (std::any_of( - C.front(), std::next(C.back()), - [](const MachineInstr &MI) { return MI.isCall(); })) && + auto IsCall = [](const MachineInstr &MI) { return MI.isCall(); }; + return (llvm::any_of(C, IsCall)) && (!C.isAvailableAcrossAndOutOfSeq(AArch64::LR, TRI) || !findRegisterToSaveLRTo(C)); }); @@ -8602,7 +8598,7 @@ AArch64InstrInfo::getOutliningCandidateInfo( // Check if the range contains a call. These require a save + restore of the // link register. bool ModStackToSaveLR = false; - if (std::any_of(FirstCand.front(), FirstCand.back(), + if (std::any_of(FirstCand.begin(), std::prev(FirstCand.end()), [](const MachineInstr &MI) { return MI.isCall(); })) ModStackToSaveLR = true; @@ -8612,7 +8608,7 @@ AArch64InstrInfo::getOutliningCandidateInfo( // it being valid to tail call this sequence. We should consider this as // well. else if (FrameID != MachineOutlinerThunk && - FrameID != MachineOutlinerTailCall && FirstCand.back()->isCall()) + FrameID != MachineOutlinerTailCall && FirstCand.back().isCall()) ModStackToSaveLR = true; if (ModStackToSaveLR) { diff --git a/llvm/lib/Target/AArch64/AArch64InstrInfo.td b/llvm/lib/Target/AArch64/AArch64InstrInfo.td index 62b2bf490f3..03baa749761 100644 --- a/llvm/lib/Target/AArch64/AArch64InstrInfo.td +++ b/llvm/lib/Target/AArch64/AArch64InstrInfo.td @@ -173,7 +173,7 @@ def HasFAMINMAX : Predicate<"Subtarget->hasFAMINMAX()">, AssemblerPredicateWithAll<(all_of FeatureFAMINMAX), "faminmax">; def HasFP8FMA : Predicate<"Subtarget->hasFP8FMA()">, AssemblerPredicateWithAll<(all_of FeatureFP8FMA), "fp8fma">; -def HasSSVE_FP8FMA : Predicate<"Subtarget->SSVE_FP8FMA() || " +def HasSSVE_FP8FMA : Predicate<"Subtarget->hasSSVE_FP8FMA() || " "(Subtarget->hasSVE2() && Subtarget->hasFP8FMA())">, AssemblerPredicateWithAll<(any_of FeatureSSVE_FP8FMA, (all_of FeatureSVE2, FeatureFP8FMA)), @@ -642,6 +642,11 @@ def AArch64call_rvmarker: SDNode<"AArch64ISD::CALL_RVMARKER", [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue, SDNPVariadic]>; +def AArch64call_arm64ec_to_x64 : SDNode<"AArch64ISD::CALL_ARM64EC_TO_X64", + SDTypeProfile<0, -1, [SDTCisPtrTy<0>]>, + [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue, + SDNPVariadic]>; + def AArch64brcond : SDNode<"AArch64ISD::BRCOND", SDT_AArch64Brcond, [SDNPHasChain]>; def AArch64cbz : SDNode<"AArch64ISD::CBZ", SDT_AArch64cbz, @@ -799,6 +804,7 @@ def AArch64uminv : SDNode<"AArch64ISD::UMINV", SDT_AArch64UnaryVec>; def AArch64smaxv : SDNode<"AArch64ISD::SMAXV", SDT_AArch64UnaryVec>; def AArch64umaxv : SDNode<"AArch64ISD::UMAXV", SDT_AArch64UnaryVec>; def AArch64uaddlv : SDNode<"AArch64ISD::UADDLV", SDT_AArch64uaddlp>; +def AArch64saddlv : SDNode<"AArch64ISD::SADDLV", SDT_AArch64uaddlp>; def AArch64uabd : PatFrags<(ops node:$lhs, node:$rhs), [(abdu node:$lhs, node:$rhs), @@ -2800,6 +2806,10 @@ let isCall = 1, Defs = [LR], Uses = [SP] in { Sched<[WriteBrReg]>; def BLR_BTI : Pseudo<(outs), (ins variable_ops), []>, Sched<[WriteBrReg]>; + let Uses = [X16, SP] in + def BLR_X16 : Pseudo<(outs), (ins), [(AArch64call_arm64ec_to_x64 X16)]>, + Sched<[WriteBrReg]>, + PseudoInstExpansion<(BLR X16)>; } // isCall def : Pat<(AArch64call GPR64:$Rn), @@ -2925,27 +2935,33 @@ def UDF : UDFType<0, "udf">; // Pair (indexed, offset) defm LDPW : LoadPairOffset<0b00, 0, GPR32z, simm7s4, "ldp">; defm LDPX : LoadPairOffset<0b10, 0, GPR64z, simm7s8, "ldp">; +let Predicates = [HasFPARMv8] in { defm LDPS : LoadPairOffset<0b00, 1, FPR32Op, simm7s4, "ldp">; defm LDPD : LoadPairOffset<0b01, 1, FPR64Op, simm7s8, "ldp">; defm LDPQ : LoadPairOffset<0b10, 1, FPR128Op, simm7s16, "ldp">; +} defm LDPSW : LoadPairOffset<0b01, 0, GPR64z, simm7s4, "ldpsw">; // Pair (pre-indexed) def LDPWpre : LoadPairPreIdx<0b00, 0, GPR32z, simm7s4, "ldp">; def LDPXpre : LoadPairPreIdx<0b10, 0, GPR64z, simm7s8, "ldp">; +let Predicates = [HasFPARMv8] in { def LDPSpre : LoadPairPreIdx<0b00, 1, FPR32Op, simm7s4, "ldp">; def LDPDpre : LoadPairPreIdx<0b01, 1, FPR64Op, simm7s8, "ldp">; def LDPQpre : LoadPairPreIdx<0b10, 1, FPR128Op, simm7s16, "ldp">; +} def LDPSWpre : LoadPairPreIdx<0b01, 0, GPR64z, simm7s4, "ldpsw">; // Pair (post-indexed) def LDPWpost : LoadPairPostIdx<0b00, 0, GPR32z, simm7s4, "ldp">; def LDPXpost : LoadPairPostIdx<0b10, 0, GPR64z, simm7s8, "ldp">; +let Predicates = [HasFPARMv8] in { def LDPSpost : LoadPairPostIdx<0b00, 1, FPR32Op, simm7s4, "ldp">; def LDPDpost : LoadPairPostIdx<0b01, 1, FPR64Op, simm7s8, "ldp">; def LDPQpost : LoadPairPostIdx<0b10, 1, FPR128Op, simm7s16, "ldp">; +} def LDPSWpost : LoadPairPostIdx<0b01, 0, GPR64z, simm7s4, "ldpsw">; @@ -2953,9 +2969,11 @@ def LDPSWpost : LoadPairPostIdx<0b01, 0, GPR64z, simm7s4, "ldpsw">; // Pair (no allocate) defm LDNPW : LoadPairNoAlloc<0b00, 0, GPR32z, simm7s4, "ldnp">; defm LDNPX : LoadPairNoAlloc<0b10, 0, GPR64z, simm7s8, "ldnp">; +let Predicates = [HasFPARMv8] in { defm LDNPS : LoadPairNoAlloc<0b00, 1, FPR32Op, simm7s4, "ldnp">; defm LDNPD : LoadPairNoAlloc<0b01, 1, FPR64Op, simm7s8, "ldnp">; defm LDNPQ : LoadPairNoAlloc<0b10, 1, FPR128Op, simm7s16, "ldnp">; +} def : Pat<(AArch64ldp (am_indexed7s64 GPR64sp:$Rn, simm7s8:$offset)), (LDPXi GPR64sp:$Rn, simm7s8:$offset)>; @@ -2973,11 +2991,13 @@ defm LDRW : Load32RO<0b10, 0, 0b01, GPR32, "ldr", i32, load>; defm LDRX : Load64RO<0b11, 0, 0b01, GPR64, "ldr", i64, load>; // Floating-point +let Predicates = [HasFPARMv8] in { defm LDRB : Load8RO<0b00, 1, 0b01, FPR8Op, "ldr", i8, load>; defm LDRH : Load16RO<0b01, 1, 0b01, FPR16Op, "ldr", f16, load>; defm LDRS : Load32RO<0b10, 1, 0b01, FPR32Op, "ldr", f32, load>; defm LDRD : Load64RO<0b11, 1, 0b01, FPR64Op, "ldr", f64, load>; defm LDRQ : Load128RO<0b00, 1, 0b11, FPR128Op, "ldr", f128, load>; +} // Load sign-extended half-word defm LDRSHW : Load16RO<0b01, 0, 0b11, GPR32, "ldrsh", i32, sextloadi16>; @@ -3147,6 +3167,7 @@ defm LDRX : LoadUI<0b11, 0, 0b01, GPR64z, uimm12s8, "ldr", defm LDRW : LoadUI<0b10, 0, 0b01, GPR32z, uimm12s4, "ldr", [(set GPR32z:$Rt, (load (am_indexed32 GPR64sp:$Rn, uimm12s4:$offset)))]>; +let Predicates = [HasFPARMv8] in { defm LDRB : LoadUI<0b00, 1, 0b01, FPR8Op, uimm12s1, "ldr", [(set FPR8Op:$Rt, (load (am_indexed8 GPR64sp:$Rn, uimm12s1:$offset)))]>; @@ -3162,6 +3183,7 @@ defm LDRD : LoadUI<0b11, 1, 0b01, FPR64Op, uimm12s8, "ldr", defm LDRQ : LoadUI<0b00, 1, 0b11, FPR128Op, uimm12s16, "ldr", [(set (f128 FPR128Op:$Rt), (load (am_indexed128 GPR64sp:$Rn, uimm12s16:$offset)))]>; +} // bf16 load pattern def : Pat <(bf16 (load (am_indexed16 GPR64sp:$Rn, uimm12s2:$offset))), @@ -3339,12 +3361,14 @@ def LDRWl : LoadLiteral<0b00, 0, GPR32z, "ldr", [(set GPR32z:$Rt, (load (AArch64adr alignedglobal:$label)))]>; def LDRXl : LoadLiteral<0b01, 0, GPR64z, "ldr", [(set GPR64z:$Rt, (load (AArch64adr alignedglobal:$label)))]>; +let Predicates = [HasFPARMv8] in { def LDRSl : LoadLiteral<0b00, 1, FPR32Op, "ldr", [(set (f32 FPR32Op:$Rt), (load (AArch64adr alignedglobal:$label)))]>; def LDRDl : LoadLiteral<0b01, 1, FPR64Op, "ldr", [(set (f64 FPR64Op:$Rt), (load (AArch64adr alignedglobal:$label)))]>; def LDRQl : LoadLiteral<0b10, 1, FPR128Op, "ldr", [(set (f128 FPR128Op:$Rt), (load (AArch64adr alignedglobal:$label)))]>; +} // load sign-extended word def LDRSWl : LoadLiteral<0b10, 0, GPR64z, "ldrsw", @@ -3367,6 +3391,7 @@ defm LDURX : LoadUnscaled<0b11, 0, 0b01, GPR64z, "ldur", defm LDURW : LoadUnscaled<0b10, 0, 0b01, GPR32z, "ldur", [(set GPR32z:$Rt, (load (am_unscaled32 GPR64sp:$Rn, simm9:$offset)))]>; +let Predicates = [HasFPARMv8] in { defm LDURB : LoadUnscaled<0b00, 1, 0b01, FPR8Op, "ldur", [(set FPR8Op:$Rt, (load (am_unscaled8 GPR64sp:$Rn, simm9:$offset)))]>; @@ -3382,6 +3407,7 @@ defm LDURD : LoadUnscaled<0b11, 1, 0b01, FPR64Op, "ldur", defm LDURQ : LoadUnscaled<0b00, 1, 0b11, FPR128Op, "ldur", [(set (f128 FPR128Op:$Rt), (load (am_unscaled128 GPR64sp:$Rn, simm9:$offset)))]>; +} defm LDURHH : LoadUnscaled<0b01, 0, 0b01, GPR32, "ldurh", @@ -3641,11 +3667,13 @@ defm LDTRSW : LoadUnprivileged<0b10, 0, 0b10, GPR64, "ldtrsw">; // (immediate pre-indexed) def LDRWpre : LoadPreIdx<0b10, 0, 0b01, GPR32z, "ldr">; def LDRXpre : LoadPreIdx<0b11, 0, 0b01, GPR64z, "ldr">; +let Predicates = [HasFPARMv8] in { def LDRBpre : LoadPreIdx<0b00, 1, 0b01, FPR8Op, "ldr">; def LDRHpre : LoadPreIdx<0b01, 1, 0b01, FPR16Op, "ldr">; def LDRSpre : LoadPreIdx<0b10, 1, 0b01, FPR32Op, "ldr">; def LDRDpre : LoadPreIdx<0b11, 1, 0b01, FPR64Op, "ldr">; def LDRQpre : LoadPreIdx<0b00, 1, 0b11, FPR128Op, "ldr">; +} // load sign-extended half-word def LDRSHWpre : LoadPreIdx<0b01, 0, 0b11, GPR32z, "ldrsh">; @@ -3666,11 +3694,13 @@ def LDRSWpre : LoadPreIdx<0b10, 0, 0b10, GPR64z, "ldrsw">; // (immediate post-indexed) def LDRWpost : LoadPostIdx<0b10, 0, 0b01, GPR32z, "ldr">; def LDRXpost : LoadPostIdx<0b11, 0, 0b01, GPR64z, "ldr">; +let Predicates = [HasFPARMv8] in { def LDRBpost : LoadPostIdx<0b00, 1, 0b01, FPR8Op, "ldr">; def LDRHpost : LoadPostIdx<0b01, 1, 0b01, FPR16Op, "ldr">; def LDRSpost : LoadPostIdx<0b10, 1, 0b01, FPR32Op, "ldr">; def LDRDpost : LoadPostIdx<0b11, 1, 0b01, FPR64Op, "ldr">; def LDRQpost : LoadPostIdx<0b00, 1, 0b11, FPR128Op, "ldr">; +} // load sign-extended half-word def LDRSHWpost : LoadPostIdx<0b01, 0, 0b11, GPR32z, "ldrsh">; @@ -3695,30 +3725,38 @@ def LDRSWpost : LoadPostIdx<0b10, 0, 0b10, GPR64z, "ldrsw">; // FIXME: Use dedicated range-checked addressing mode operand here. defm STPW : StorePairOffset<0b00, 0, GPR32z, simm7s4, "stp">; defm STPX : StorePairOffset<0b10, 0, GPR64z, simm7s8, "stp">; +let Predicates = [HasFPARMv8] in { defm STPS : StorePairOffset<0b00, 1, FPR32Op, simm7s4, "stp">; defm STPD : StorePairOffset<0b01, 1, FPR64Op, simm7s8, "stp">; defm STPQ : StorePairOffset<0b10, 1, FPR128Op, simm7s16, "stp">; +} // Pair (pre-indexed) def STPWpre : StorePairPreIdx<0b00, 0, GPR32z, simm7s4, "stp">; def STPXpre : StorePairPreIdx<0b10, 0, GPR64z, simm7s8, "stp">; +let Predicates = [HasFPARMv8] in { def STPSpre : StorePairPreIdx<0b00, 1, FPR32Op, simm7s4, "stp">; def STPDpre : StorePairPreIdx<0b01, 1, FPR64Op, simm7s8, "stp">; def STPQpre : StorePairPreIdx<0b10, 1, FPR128Op, simm7s16, "stp">; +} // Pair (post-indexed) def STPWpost : StorePairPostIdx<0b00, 0, GPR32z, simm7s4, "stp">; def STPXpost : StorePairPostIdx<0b10, 0, GPR64z, simm7s8, "stp">; +let Predicates = [HasFPARMv8] in { def STPSpost : StorePairPostIdx<0b00, 1, FPR32Op, simm7s4, "stp">; def STPDpost : StorePairPostIdx<0b01, 1, FPR64Op, simm7s8, "stp">; def STPQpost : StorePairPostIdx<0b10, 1, FPR128Op, simm7s16, "stp">; +} // Pair (no allocate) defm STNPW : StorePairNoAlloc<0b00, 0, GPR32z, simm7s4, "stnp">; defm STNPX : StorePairNoAlloc<0b10, 0, GPR64z, simm7s8, "stnp">; +let Predicates = [HasFPARMv8] in { defm STNPS : StorePairNoAlloc<0b00, 1, FPR32Op, simm7s4, "stnp">; defm STNPD : StorePairNoAlloc<0b01, 1, FPR64Op, simm7s8, "stnp">; defm STNPQ : StorePairNoAlloc<0b10, 1, FPR128Op, simm7s16, "stnp">; +} def : Pat<(AArch64stp GPR64z:$Rt, GPR64z:$Rt2, (am_indexed7s64 GPR64sp:$Rn, simm7s8:$offset)), (STPXi GPR64z:$Rt, GPR64z:$Rt2, GPR64sp:$Rn, simm7s8:$offset)>; @@ -3738,11 +3776,13 @@ defm STRX : Store64RO<0b11, 0, 0b00, GPR64, "str", i64, store>; // Floating-point +let Predicates = [HasFPARMv8] in { defm STRB : Store8RO< 0b00, 1, 0b00, FPR8Op, "str", i8, store>; defm STRH : Store16RO<0b01, 1, 0b00, FPR16Op, "str", f16, store>; defm STRS : Store32RO<0b10, 1, 0b00, FPR32Op, "str", f32, store>; defm STRD : Store64RO<0b11, 1, 0b00, FPR64Op, "str", f64, store>; defm STRQ : Store128RO<0b00, 1, 0b10, FPR128Op, "str">; +} let Predicates = [UseSTRQro], AddedComplexity = 10 in { def : Pat<(store (f128 FPR128:$Rt), @@ -3851,6 +3891,7 @@ defm STRX : StoreUIz<0b11, 0, 0b00, GPR64z, uimm12s8, "str", defm STRW : StoreUIz<0b10, 0, 0b00, GPR32z, uimm12s4, "str", [(store GPR32z:$Rt, (am_indexed32 GPR64sp:$Rn, uimm12s4:$offset))]>; +let Predicates = [HasFPARMv8] in { defm STRB : StoreUI<0b00, 1, 0b00, FPR8Op, uimm12s1, "str", [(store FPR8Op:$Rt, (am_indexed8 GPR64sp:$Rn, uimm12s1:$offset))]>; @@ -3864,6 +3905,7 @@ defm STRD : StoreUI<0b11, 1, 0b00, FPR64Op, uimm12s8, "str", [(store (f64 FPR64Op:$Rt), (am_indexed64 GPR64sp:$Rn, uimm12s8:$offset))]>; defm STRQ : StoreUI<0b00, 1, 0b10, FPR128Op, uimm12s16, "str", []>; +} defm STRHH : StoreUIz<0b01, 0, 0b00, GPR32z, uimm12s2, "strh", [(truncstorei16 GPR32z:$Rt, @@ -3985,6 +4027,7 @@ defm STURX : StoreUnscaled<0b11, 0, 0b00, GPR64z, "stur", defm STURW : StoreUnscaled<0b10, 0, 0b00, GPR32z, "stur", [(store GPR32z:$Rt, (am_unscaled32 GPR64sp:$Rn, simm9:$offset))]>; +let Predicates = [HasFPARMv8] in { defm STURB : StoreUnscaled<0b00, 1, 0b00, FPR8Op, "stur", [(store FPR8Op:$Rt, (am_unscaled8 GPR64sp:$Rn, simm9:$offset))]>; @@ -4000,6 +4043,7 @@ defm STURD : StoreUnscaled<0b11, 1, 0b00, FPR64Op, "stur", defm STURQ : StoreUnscaled<0b00, 1, 0b10, FPR128Op, "stur", [(store (f128 FPR128Op:$Rt), (am_unscaled128 GPR64sp:$Rn, simm9:$offset))]>; +} defm STURHH : StoreUnscaled<0b01, 0, 0b00, GPR32z, "sturh", [(truncstorei16 GPR32z:$Rt, (am_unscaled16 GPR64sp:$Rn, simm9:$offset))]>; @@ -4156,11 +4200,13 @@ defm STTRB : StoreUnprivileged<0b00, 0, 0b00, GPR32, "sttrb">; // (immediate pre-indexed) def STRWpre : StorePreIdx<0b10, 0, 0b00, GPR32z, "str", pre_store, i32>; def STRXpre : StorePreIdx<0b11, 0, 0b00, GPR64z, "str", pre_store, i64>; +let Predicates = [HasFPARMv8] in { def STRBpre : StorePreIdx<0b00, 1, 0b00, FPR8Op, "str", pre_store, i8>; def STRHpre : StorePreIdx<0b01, 1, 0b00, FPR16Op, "str", pre_store, f16>; def STRSpre : StorePreIdx<0b10, 1, 0b00, FPR32Op, "str", pre_store, f32>; def STRDpre : StorePreIdx<0b11, 1, 0b00, FPR64Op, "str", pre_store, f64>; def STRQpre : StorePreIdx<0b00, 1, 0b10, FPR128Op, "str", pre_store, f128>; +} def STRBBpre : StorePreIdx<0b00, 0, 0b00, GPR32z, "strb", pre_truncsti8, i32>; def STRHHpre : StorePreIdx<0b01, 0, 0b00, GPR32z, "strh", pre_truncsti16, i32>; @@ -4210,11 +4256,13 @@ def : Pat<(pre_store (v8f16 FPR128:$Rt), GPR64sp:$addr, simm9:$off), // (immediate post-indexed) def STRWpost : StorePostIdx<0b10, 0, 0b00, GPR32z, "str", post_store, i32>; def STRXpost : StorePostIdx<0b11, 0, 0b00, GPR64z, "str", post_store, i64>; +let Predicates = [HasFPARMv8] in { def STRBpost : StorePostIdx<0b00, 1, 0b00, FPR8Op, "str", post_store, i8>; def STRHpost : StorePostIdx<0b01, 1, 0b00, FPR16Op, "str", post_store, f16>; def STRSpost : StorePostIdx<0b10, 1, 0b00, FPR32Op, "str", post_store, f32>; def STRDpost : StorePostIdx<0b11, 1, 0b00, FPR64Op, "str", post_store, f64>; def STRQpost : StorePostIdx<0b00, 1, 0b10, FPR128Op, "str", post_store, f128>; +} def STRBBpost : StorePostIdx<0b00, 0, 0b00, GPR32z, "strb", post_truncsti8, i32>; def STRHHpost : StorePostIdx<0b01, 0, 0b00, GPR32z, "strh", post_truncsti16, i32>; @@ -4531,7 +4579,8 @@ def : Pat<(f64 (fdiv (f64 (any_uint_to_fp (i32 GPR32:$Rn))), fixedpoint_f64_i32: defm FMOV : UnscaledConversion<"fmov">; // Add pseudo ops for FMOV 0 so we can mark them as isReMaterializable -let isReMaterializable = 1, isCodeGenOnly = 1, isAsCheapAsAMove = 1 in { +let isReMaterializable = 1, isCodeGenOnly = 1, isAsCheapAsAMove = 1, + Predicates = [HasFPARMv8] in { def FMOVH0 : Pseudo<(outs FPR16:$Rd), (ins), [(set f16:$Rd, (fpimm0))]>, Sched<[WriteF]>; def FMOVS0 : Pseudo<(outs FPR32:$Rd), (ins), [(set f32:$Rd, (fpimm0))]>, @@ -4758,6 +4807,7 @@ def : Pat<(bf16 (AArch64csel (bf16 FPR16:$Rn), (bf16 FPR16:$Rm), (i32 imm:$cond) // CSEL instructions providing f128 types need to be handled by a // pseudo-instruction since the eventual code will need to introduce basic // blocks and control flow. +let Predicates = [HasFPARMv8] in def F128CSEL : Pseudo<(outs FPR128:$Rd), (ins FPR128:$Rn, FPR128:$Rm, ccode:$cond), [(set (f128 FPR128:$Rd), @@ -4790,6 +4840,8 @@ let isPseudo = 1 in { def SEH_EpilogStart : Pseudo<(outs), (ins), []>, Sched<[]>; def SEH_EpilogEnd : Pseudo<(outs), (ins), []>, Sched<[]>; def SEH_PACSignLR : Pseudo<(outs), (ins), []>, Sched<[]>; + def SEH_SaveAnyRegQP : Pseudo<(outs), (ins i32imm:$reg0, i32imm:$reg1, i32imm:$offs), []>, Sched<[]>; + def SEH_SaveAnyRegQPX : Pseudo<(outs), (ins i32imm:$reg0, i32imm:$reg1, i32imm:$offs), []>, Sched<[]>; } // Pseudo instructions for Windows EH @@ -6623,6 +6675,26 @@ multiclass SIMDAcrossLaneLongPairIntrinsic defm : SIMDAcrossLaneLongPairIntrinsic<"UADDLV", AArch64uaddlp>; defm : SIMDAcrossLaneLongPairIntrinsic<"SADDLV", AArch64saddlp>; +// Pattern is used for GlobalISel +multiclass SIMDAcrossLaneLongPairIntrinsicGISel { + // Patterns for addv(addlp(x)) ==> addlv + def : Pat<(i16 (vecreduce_add (v4i16 (addlp (v8i8 V64:$Rn))))), + (!cast(Opc#"v8i8v") V64:$Rn)>; + def : Pat<(i16 (vecreduce_add (v8i16 (addlp (v16i8 V128:$Rn))))), + (!cast(Opc#"v16i8v") V128:$Rn)>; + def : Pat<(i32 (vecreduce_add (v4i32 (addlp (v8i16 V128:$Rn))))), + (!cast(Opc#"v8i16v") V128:$Rn)>; + + // Patterns for addp(addlp(x))) ==> addlv + def : Pat<(i32 (vecreduce_add (v2i32 (addlp (v4i16 V64:$Rn))))), + (!cast(Opc#"v4i16v") V64:$Rn)>; + def : Pat<(i64 (vecreduce_add (v2i64 (addlp (v4i32 V128:$Rn))))), + (!cast(Opc#"v4i32v") V128:$Rn)>; +} + +defm : SIMDAcrossLaneLongPairIntrinsicGISel<"UADDLV", AArch64uaddlp>; +defm : SIMDAcrossLaneLongPairIntrinsicGISel<"SADDLV", AArch64saddlp>; + // Patterns for uaddlv(uaddlp(x)) ==> uaddlv def : Pat<(i64 (int_aarch64_neon_uaddlv (v4i32 (AArch64uaddlp (v8i16 V128:$op))))), (i64 (EXTRACT_SUBREG @@ -6634,23 +6706,34 @@ def : Pat<(i32 (int_aarch64_neon_uaddlv (v8i16 (AArch64uaddlp (v16i8 V128:$op))) (v8i16 (SUBREG_TO_REG (i64 0), (UADDLVv16i8v V128:$op), hsub)), ssub))>; +def : Pat<(v2i64 (AArch64uaddlv (v4i32 (AArch64uaddlp (v8i16 V128:$op))))), + (v2i64 (SUBREG_TO_REG (i64 0), (UADDLVv8i16v V128:$op), ssub))>; + def : Pat<(v4i32 (AArch64uaddlv (v8i16 (AArch64uaddlp (v16i8 V128:$op))))), (v4i32 (SUBREG_TO_REG (i64 0), (UADDLVv16i8v V128:$op), hsub))>; def : Pat<(v4i32 (AArch64uaddlv (v4i16 (AArch64uaddlp (v8i8 V64:$op))))), (v4i32 (SUBREG_TO_REG (i64 0), (UADDLVv8i8v V64:$op), hsub))>; -def : Pat<(v4i32 (AArch64uaddlv (v8i8 V64:$Rn))), - (v4i32 (SUBREG_TO_REG (i64 0), (UADDLVv8i8v V64:$Rn), hsub))>; +multiclass SIMDAcrossLaneLongReductionIntrinsic { + def : Pat<(v4i32 (addlv (v8i8 V64:$Rn))), + (v4i32 (SUBREG_TO_REG (i64 0), (!cast(Opc#"v8i8v") V64:$Rn), hsub))>; -def : Pat<(v4i32 (AArch64uaddlv (v4i16 V64:$Rn))), - (v4i32 (SUBREG_TO_REG (i64 0), (UADDLVv4i16v V64:$Rn), ssub))>; + def : Pat<(v4i32 (addlv (v4i16 V64:$Rn))), + (v4i32 (SUBREG_TO_REG (i64 0), (!cast(Opc#"v4i16v") V64:$Rn), ssub))>; -def : Pat<(v4i32 (AArch64uaddlv (v16i8 V128:$Rn))), - (v4i32 (SUBREG_TO_REG (i64 0), (UADDLVv16i8v V128:$Rn), hsub))>; + def : Pat<(v4i32 (addlv (v16i8 V128:$Rn))), + (v4i32 (SUBREG_TO_REG (i64 0), (!cast(Opc#"v16i8v") V128:$Rn), hsub))>; -def : Pat<(v4i32 (AArch64uaddlv (v8i16 V128:$Rn))), - (v4i32 (SUBREG_TO_REG (i64 0), (UADDLVv8i16v V128:$Rn), ssub))>; + def : Pat<(v4i32 (addlv (v8i16 V128:$Rn))), + (v4i32 (SUBREG_TO_REG (i64 0), (!cast(Opc#"v8i16v") V128:$Rn), ssub))>; + + def : Pat<(v2i64 (addlv (v4i32 V128:$Rn))), + (v2i64 (SUBREG_TO_REG (i64 0), (!cast(Opc#"v4i32v") V128:$Rn), dsub))>; +} + +defm : SIMDAcrossLaneLongReductionIntrinsic<"UADDLV", AArch64uaddlv>; +defm : SIMDAcrossLaneLongReductionIntrinsic<"SADDLV", AArch64saddlv>; // Patterns for across-vector intrinsics, that have a node equivalent, that // returns a vector (with only the low lane defined) instead of a scalar. @@ -9331,15 +9414,15 @@ let Predicates = [HasLSE128] in { //===----------------------------------------------------------------------===// let Predicates = [HasRCPC3] in { - // size opc opc2 - def STILPWpre: BaseLRCPC3IntegerLoadStorePair<0b10, 0b00, 0b0000, (outs GPR64sp:$wback), (ins GPR32:$Rt, GPR32:$Rt2, GPR64sp:$Rn), "stilp", "\t$Rt, $Rt2, [$Rn, #-8]!", "$Rn = $wback">; - def STILPXpre: BaseLRCPC3IntegerLoadStorePair<0b11, 0b00, 0b0000, (outs GPR64sp:$wback), (ins GPR64:$Rt, GPR64:$Rt2, GPR64sp:$Rn), "stilp", "\t$Rt, $Rt2, [$Rn, #-16]!", "$Rn = $wback">; - def STILPW: BaseLRCPC3IntegerLoadStorePair<0b10, 0b00, 0b0001, (outs), (ins GPR32:$Rt, GPR32:$Rt2, GPR64sp:$Rn), "stilp", "\t$Rt, $Rt2, [$Rn]", "">; - def STILPX: BaseLRCPC3IntegerLoadStorePair<0b11, 0b00, 0b0001, (outs), (ins GPR64:$Rt, GPR64:$Rt2, GPR64sp:$Rn), "stilp", "\t$Rt, $Rt2, [$Rn]", "">; - def LDIAPPWpre: BaseLRCPC3IntegerLoadStorePair<0b10, 0b01, 0b0000, (outs GPR64sp:$wback, GPR32:$Rt, GPR32:$Rt2), (ins GPR64sp:$Rn), "ldiapp", "\t$Rt, $Rt2, [$Rn], #8", "$Rn = $wback">; - def LDIAPPXpre: BaseLRCPC3IntegerLoadStorePair<0b11, 0b01, 0b0000, (outs GPR64sp:$wback, GPR64:$Rt, GPR64:$Rt2), (ins GPR64sp:$Rn), "ldiapp", "\t$Rt, $Rt2, [$Rn], #16", "$Rn = $wback">; - def LDIAPPW: BaseLRCPC3IntegerLoadStorePair<0b10, 0b01, 0b0001, (outs GPR32:$Rt, GPR32:$Rt2), (ins GPR64sp0:$Rn), "ldiapp", "\t$Rt, $Rt2, [$Rn]", "">; - def LDIAPPX: BaseLRCPC3IntegerLoadStorePair<0b11, 0b01, 0b0001, (outs GPR64:$Rt, GPR64:$Rt2), (ins GPR64sp0:$Rn), "ldiapp", "\t$Rt, $Rt2, [$Rn]", "">; + // size opc opc2 + def STILPWpre: BaseLRCPC3IntegerLoadStorePair<0b10, 0b00, 0b0000, (outs GPR64sp:$wback), (ins GPR32:$Rt, GPR32:$Rt2, GPR64sp:$Rn), "stilp", "\t$Rt, $Rt2, [$Rn, #-8]!", "$Rn = $wback">; + def STILPXpre: BaseLRCPC3IntegerLoadStorePair<0b11, 0b00, 0b0000, (outs GPR64sp:$wback), (ins GPR64:$Rt, GPR64:$Rt2, GPR64sp:$Rn), "stilp", "\t$Rt, $Rt2, [$Rn, #-16]!", "$Rn = $wback">; + def STILPW: BaseLRCPC3IntegerLoadStorePair<0b10, 0b00, 0b0001, (outs), (ins GPR32:$Rt, GPR32:$Rt2, GPR64sp:$Rn), "stilp", "\t$Rt, $Rt2, [$Rn]", "">; + def STILPX: BaseLRCPC3IntegerLoadStorePair<0b11, 0b00, 0b0001, (outs), (ins GPR64:$Rt, GPR64:$Rt2, GPR64sp:$Rn), "stilp", "\t$Rt, $Rt2, [$Rn]", "">; + def LDIAPPWpost: BaseLRCPC3IntegerLoadStorePair<0b10, 0b01, 0b0000, (outs GPR64sp:$wback, GPR32:$Rt, GPR32:$Rt2), (ins GPR64sp:$Rn), "ldiapp", "\t$Rt, $Rt2, [$Rn], #8", "$Rn = $wback">; + def LDIAPPXpost: BaseLRCPC3IntegerLoadStorePair<0b11, 0b01, 0b0000, (outs GPR64sp:$wback, GPR64:$Rt, GPR64:$Rt2), (ins GPR64sp:$Rn), "ldiapp", "\t$Rt, $Rt2, [$Rn], #16", "$Rn = $wback">; + def LDIAPPW: BaseLRCPC3IntegerLoadStorePair<0b10, 0b01, 0b0001, (outs GPR32:$Rt, GPR32:$Rt2), (ins GPR64sp0:$Rn), "ldiapp", "\t$Rt, $Rt2, [$Rn]", "">; + def LDIAPPX: BaseLRCPC3IntegerLoadStorePair<0b11, 0b01, 0b0001, (outs GPR64:$Rt, GPR64:$Rt2), (ins GPR64sp0:$Rn), "ldiapp", "\t$Rt, $Rt2, [$Rn]", "">; def : Pat<(AArch64ldiapp GPR64sp:$Rn), (LDIAPPX GPR64sp:$Rn)>; def : Pat<(AArch64stilp GPR64:$Rt, GPR64:$Rt2, GPR64sp:$Rn), (STILPX GPR64:$Rt, GPR64:$Rt2, GPR64sp:$Rn)>; @@ -9348,11 +9431,11 @@ let Predicates = [HasRCPC3] in { def : InstAlias<"stilp\t$Rt, $Rt2, [$Rn, #0]", (STILPW GPR32: $Rt, GPR32: $Rt2, GPR64sp:$Rn)>; def : InstAlias<"stilp\t$Rt, $Rt2, [$Rn, #0]", (STILPX GPR64: $Rt, GPR64: $Rt2, GPR64sp:$Rn)>; - // size opc - def STLRWpre: BaseLRCPC3IntegerLoadStore<0b10, 0b10, (outs GPR64sp:$wback), (ins GPR32:$Rt, GPR64sp:$Rn), "stlr", "\t$Rt, [$Rn, #-4]!", "$Rn = $wback">; - def STLRXpre: BaseLRCPC3IntegerLoadStore<0b11, 0b10, (outs GPR64sp:$wback), (ins GPR64:$Rt, GPR64sp:$Rn), "stlr", "\t$Rt, [$Rn, #-8]!", "$Rn = $wback">; - def LDAPRWpre: BaseLRCPC3IntegerLoadStore<0b10, 0b11, (outs GPR64sp:$wback, GPR32:$Rt), (ins GPR64sp:$Rn), "ldapr", "\t$Rt, [$Rn], #4", "$Rn = $wback">; - def LDAPRXpre: BaseLRCPC3IntegerLoadStore<0b11, 0b11, (outs GPR64sp:$wback, GPR64:$Rt), (ins GPR64sp:$Rn), "ldapr", "\t$Rt, [$Rn], #8", "$Rn = $wback">; + // size opc + def STLRWpre: BaseLRCPC3IntegerLoadStore<0b10, 0b10, (outs GPR64sp:$wback), (ins GPR32:$Rt, GPR64sp:$Rn), "stlr", "\t$Rt, [$Rn, #-4]!", "$Rn = $wback">; + def STLRXpre: BaseLRCPC3IntegerLoadStore<0b11, 0b10, (outs GPR64sp:$wback), (ins GPR64:$Rt, GPR64sp:$Rn), "stlr", "\t$Rt, [$Rn, #-8]!", "$Rn = $wback">; + def LDAPRWpost: BaseLRCPC3IntegerLoadStore<0b10, 0b11, (outs GPR64sp:$wback, GPR32:$Rt), (ins GPR64sp:$Rn), "ldapr", "\t$Rt, [$Rn], #4", "$Rn = $wback">; + def LDAPRXpost: BaseLRCPC3IntegerLoadStore<0b11, 0b11, (outs GPR64sp:$wback, GPR64:$Rt), (ins GPR64sp:$Rn), "ldapr", "\t$Rt, [$Rn], #8", "$Rn = $wback">; } let Predicates = [HasRCPC3, HasNEON] in { diff --git a/llvm/lib/Target/AArch64/AArch64LoopIdiomTransform.cpp b/llvm/lib/Target/AArch64/AArch64LoopIdiomTransform.cpp index 6c6cd120b03..6dfb2b9df71 100644 --- a/llvm/lib/Target/AArch64/AArch64LoopIdiomTransform.cpp +++ b/llvm/lib/Target/AArch64/AArch64LoopIdiomTransform.cpp @@ -367,11 +367,12 @@ bool AArch64LoopIdiomTransform::recognizeByteCompare() { Value *WhileBodyVal = EndPN.getIncomingValueForBlock(WhileBB); // The value of the index when leaving the while.cond block is always the - // same as the end value (MaxLen) so we permit either. Otherwise for any - // other value defined outside the loop we only allow values that are the - // same as the exit value for while.body. - if (WhileCondVal != Index && WhileCondVal != MaxLen && - WhileCondVal != WhileBodyVal) + // same as the end value (MaxLen) so we permit either. The value when + // leaving the while.body block should only be the index. Otherwise for + // any other values we only allow ones that are same for both blocks. + if (WhileCondVal != WhileBodyVal && + ((WhileCondVal != Index && WhileCondVal != MaxLen) || + (WhileBodyVal != Index))) return false; } } diff --git a/llvm/lib/Target/AArch64/AArch64MCInstLower.cpp b/llvm/lib/Target/AArch64/AArch64MCInstLower.cpp index 59969f9dc31..1e12cf545fa 100644 --- a/llvm/lib/Target/AArch64/AArch64MCInstLower.cpp +++ b/llvm/lib/Target/AArch64/AArch64MCInstLower.cpp @@ -36,8 +36,11 @@ AArch64MCInstLower::AArch64MCInstLower(MCContext &ctx, AsmPrinter &printer) MCSymbol * AArch64MCInstLower::GetGlobalAddressSymbol(const MachineOperand &MO) const { - const GlobalValue *GV = MO.getGlobal(); - unsigned TargetFlags = MO.getTargetFlags(); + return GetGlobalValueSymbol(MO.getGlobal(), MO.getTargetFlags()); +} + +MCSymbol *AArch64MCInstLower::GetGlobalValueSymbol(const GlobalValue *GV, + unsigned TargetFlags) const { const Triple &TheTriple = Printer.TM.getTargetTriple(); if (!TheTriple.isOSBinFormatCOFF()) return Printer.getSymbolPreferLocal(*GV); @@ -46,14 +49,54 @@ AArch64MCInstLower::GetGlobalAddressSymbol(const MachineOperand &MO) const { "Windows is the only supported COFF target"); bool IsIndirect = - (TargetFlags & (AArch64II::MO_DLLIMPORT | AArch64II::MO_DLLIMPORTAUX | - AArch64II::MO_COFFSTUB)); - if (!IsIndirect) + (TargetFlags & (AArch64II::MO_DLLIMPORT | AArch64II::MO_COFFSTUB)); + if (!IsIndirect) { + // For ARM64EC, symbol lookup in the MSVC linker has limited awareness + // of ARM64EC mangling ("#"/"$$h"). So object files need to refer to both + // the mangled and unmangled names of ARM64EC symbols, even if they aren't + // actually used by any relocations. Emit the necessary references here. + if (!TheTriple.isWindowsArm64EC() || !isa(GV) || + !GV->hasExternalLinkage()) + return Printer.getSymbol(GV); + + StringRef Name = Printer.getSymbol(GV)->getName(); + // Don't mangle ARM64EC runtime functions. + static constexpr StringLiteral ExcludedFns[] = { + "__os_arm64x_check_icall_cfg", "__os_arm64x_dispatch_call_no_redirect", + "__os_arm64x_check_icall"}; + if (is_contained(ExcludedFns, Name)) + return Printer.getSymbol(GV); + + if (std::optional MangledName = + getArm64ECMangledFunctionName(Name.str())) { + MCSymbol *MangledSym = Ctx.getOrCreateSymbol(MangledName.value()); + if (!cast(GV)->hasMetadata("arm64ec_hasguestexit")) { + Printer.OutStreamer->emitSymbolAttribute(Printer.getSymbol(GV), + MCSA_WeakAntiDep); + Printer.OutStreamer->emitAssignment( + Printer.getSymbol(GV), + MCSymbolRefExpr::create(MangledSym, MCSymbolRefExpr::VK_WEAKREF, + Ctx)); + Printer.OutStreamer->emitSymbolAttribute(MangledSym, MCSA_WeakAntiDep); + Printer.OutStreamer->emitAssignment( + MangledSym, + MCSymbolRefExpr::create(Printer.getSymbol(GV), + MCSymbolRefExpr::VK_WEAKREF, Ctx)); + } + + if (TargetFlags & AArch64II::MO_ARM64EC_CALLMANGLE) + return MangledSym; + } + return Printer.getSymbol(GV); + } SmallString<128> Name; - if (TargetFlags & AArch64II::MO_DLLIMPORTAUX) { + if ((TargetFlags & AArch64II::MO_DLLIMPORT) && + TheTriple.isWindowsArm64EC() && + !(TargetFlags & AArch64II::MO_ARM64EC_CALLMANGLE) && + isa(GV)) { // __imp_aux is specific to arm64EC; it represents the actual address of // an imported function without any thunks. // diff --git a/llvm/lib/Target/AArch64/AArch64MCInstLower.h b/llvm/lib/Target/AArch64/AArch64MCInstLower.h index e4f8a1bc1a3..474ccff7d65 100644 --- a/llvm/lib/Target/AArch64/AArch64MCInstLower.h +++ b/llvm/lib/Target/AArch64/AArch64MCInstLower.h @@ -9,6 +9,7 @@ #ifndef LLVM_LIB_TARGET_AARCH64_AARCH64MCINSTLOWER_H #define LLVM_LIB_TARGET_AARCH64_AARCH64MCINSTLOWER_H +#include "llvm/IR/GlobalValue.h" #include "llvm/Support/Compiler.h" #include "llvm/TargetParser/Triple.h" @@ -42,6 +43,8 @@ public: MCSymbol *Sym) const; MCOperand LowerSymbolOperand(const MachineOperand &MO, MCSymbol *Sym) const; + MCSymbol *GetGlobalValueSymbol(const GlobalValue *GV, + unsigned TargetFlags) const; MCSymbol *GetGlobalAddressSymbol(const MachineOperand &MO) const; MCSymbol *GetExternalSymbolSymbol(const MachineOperand &MO) const; }; diff --git a/llvm/lib/Target/AArch64/AArch64MachineFunctionInfo.h b/llvm/lib/Target/AArch64/AArch64MachineFunctionInfo.h index cd4a18bfbc2..d5941e62841 100644 --- a/llvm/lib/Target/AArch64/AArch64MachineFunctionInfo.h +++ b/llvm/lib/Target/AArch64/AArch64MachineFunctionInfo.h @@ -208,6 +208,10 @@ class AArch64FunctionInfo final : public MachineFunctionInfo { int64_t StackProbeSize = 0; + // Holds a register containing pstate.sm. This is set + // on function entry to record the initial pstate of a function. + Register PStateSMReg = MCRegister::NoRegister; + public: AArch64FunctionInfo(const Function &F, const AArch64Subtarget *STI); @@ -216,6 +220,9 @@ public: const DenseMap &Src2DstMBB) const override; + Register getPStateSMReg() const { return PStateSMReg; }; + void setPStateSMReg(Register Reg) { PStateSMReg = Reg; }; + bool isSVECC() const { return IsSVECC; }; void setIsSVECC(bool s) { IsSVECC = s; }; diff --git a/llvm/lib/Target/AArch64/AArch64RegisterInfo.cpp b/llvm/lib/Target/AArch64/AArch64RegisterInfo.cpp index 24ba9dd9500..ea9882160d6 100644 --- a/llvm/lib/Target/AArch64/AArch64RegisterInfo.cpp +++ b/llvm/lib/Target/AArch64/AArch64RegisterInfo.cpp @@ -78,6 +78,9 @@ AArch64RegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const { if (MF->getFunction().getCallingConv() == CallingConv::AnyReg) return CSR_AArch64_AllRegs_SaveList; + if (MF->getFunction().getCallingConv() == CallingConv::ARM64EC_Thunk_X64) + return CSR_Win_AArch64_Arm64EC_Thunk_SaveList; + // Darwin has its own CSR_AArch64_AAPCS_SaveList, which means most CSR save // lists depending on that will need to have their Darwin variant as well. if (MF->getSubtarget().isTargetDarwin()) diff --git a/llvm/lib/Target/AArch64/AArch64SMEInstrInfo.td b/llvm/lib/Target/AArch64/AArch64SMEInstrInfo.td index 380f6e1fcfd..eeae5303a3f 100644 --- a/llvm/lib/Target/AArch64/AArch64SMEInstrInfo.td +++ b/llvm/lib/Target/AArch64/AArch64SMEInstrInfo.td @@ -22,6 +22,12 @@ def AArch64_restore_za : SDNode<"AArch64ISD::RESTORE_ZA", SDTypeProfile<0, 3, [SDTCisInt<0>, SDTCisPtrTy<1>]>, [SDNPHasChain, SDNPSideEffect, SDNPVariadic, SDNPOptInGlue]>; +def AArch64_restore_zt : SDNode<"AArch64ISD::RESTORE_ZT", SDTypeProfile<0, 2, + [SDTCisInt<0>, SDTCisPtrTy<1>]>, + [SDNPHasChain, SDNPSideEffect, SDNPMayLoad]>; +def AArch64_save_zt : SDNode<"AArch64ISD::SAVE_ZT", SDTypeProfile<0, 2, + [SDTCisInt<0>, SDTCisPtrTy<1>]>, + [SDNPHasChain, SDNPSideEffect, SDNPMayStore]>; //===----------------------------------------------------------------------===// // Instruction naming conventions. @@ -543,8 +549,8 @@ defm UMOPS_MPPZZ_HtoS : sme2_int_mopx_tile<"umops", 0b101, int_aarch64_sme_umops defm ZERO_T : sme2_zero_zt<"zero", 0b0001>; -defm LDR_TX : sme2_spill_fill_vector<"ldr", 0b01111100, int_aarch64_sme_ldr_zt>; -defm STR_TX : sme2_spill_fill_vector<"str", 0b11111100, int_aarch64_sme_str_zt>; +defm LDR_TX : sme2_spill_fill_vector<"ldr", 0b01111100, AArch64_restore_zt>; +defm STR_TX : sme2_spill_fill_vector<"str", 0b11111100, AArch64_save_zt>; def MOVT_XTI : sme2_movt_zt_to_scalar<"movt", 0b0011111>; def MOVT_TIX : sme2_movt_scalar_to_zt<"movt", 0b0011111>; diff --git a/llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td b/llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td index 4782ad076c6..c4d69232c9e 100644 --- a/llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td +++ b/llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td @@ -3577,8 +3577,8 @@ let Predicates = [HasSVE2orSME] in { defm PMULLT_ZZZ : sve2_pmul_long<0b1, "pmullt", int_aarch64_sve_pmullt_pair>; // SVE2 bitwise shift and insert - defm SRI_ZZI : sve2_int_bin_shift_imm_right<0b0, "sri", int_aarch64_sve_sri>; - defm SLI_ZZI : sve2_int_bin_shift_imm_left< 0b1, "sli", int_aarch64_sve_sli>; + defm SRI_ZZI : sve2_int_bin_shift_imm_right<0b0, "sri", AArch64vsri>; + defm SLI_ZZI : sve2_int_bin_shift_imm_left< 0b1, "sli", AArch64vsli>; // SVE2 bitwise shift right and accumulate defm SSRA_ZZI : sve2_int_bin_accum_shift_imm_right<0b00, "ssra", AArch64ssra>; diff --git a/llvm/lib/Target/AArch64/AArch64Subtarget.cpp b/llvm/lib/Target/AArch64/AArch64Subtarget.cpp index cf57d950ae8..e3a0606331d 100644 --- a/llvm/lib/Target/AArch64/AArch64Subtarget.cpp +++ b/llvm/lib/Target/AArch64/AArch64Subtarget.cpp @@ -398,8 +398,6 @@ AArch64Subtarget::ClassifyGlobalReference(const GlobalValue *GV, if (!TM.shouldAssumeDSOLocal(*GV->getParent(), GV)) { if (GV->hasDLLImportStorageClass()) { - if (isWindowsArm64EC() && GV->getValueType()->isFunctionTy()) - return AArch64II::MO_GOT | AArch64II::MO_DLLIMPORTAUX; return AArch64II::MO_GOT | AArch64II::MO_DLLIMPORT; } if (getTargetTriple().isOSWindows()) @@ -439,11 +437,18 @@ unsigned AArch64Subtarget::classifyGlobalFunctionReference( return AArch64II::MO_GOT; if (getTargetTriple().isOSWindows()) { - if (isWindowsArm64EC() && GV->getValueType()->isFunctionTy() && - GV->hasDLLImportStorageClass()) { - // On Arm64EC, if we're calling a function directly, use MO_DLLIMPORT, - // not MO_DLLIMPORTAUX. - return AArch64II::MO_GOT | AArch64II::MO_DLLIMPORT; + if (isWindowsArm64EC() && GV->getValueType()->isFunctionTy()) { + if (GV->hasDLLImportStorageClass()) { + // On Arm64EC, if we're calling a symbol from the import table + // directly, use MO_ARM64EC_CALLMANGLE. + return AArch64II::MO_GOT | AArch64II::MO_DLLIMPORT | + AArch64II::MO_ARM64EC_CALLMANGLE; + } + if (GV->hasExternalLinkage()) { + // If we're calling a symbol directly, use the mangled form in the + // call instruction. + return AArch64II::MO_ARM64EC_CALLMANGLE; + } } // Use ClassifyGlobalReference for setting MO_DLLIMPORT/MO_COFFSTUB. diff --git a/llvm/lib/Target/AArch64/AArch64Subtarget.h b/llvm/lib/Target/AArch64/AArch64Subtarget.h index b17e215e200..16864102df5 100644 --- a/llvm/lib/Target/AArch64/AArch64Subtarget.h +++ b/llvm/lib/Target/AArch64/AArch64Subtarget.h @@ -394,6 +394,7 @@ public: void mirFileLoaded(MachineFunction &MF) const override; bool hasSVEorSME() const { return hasSVE() || hasSME(); } + bool hasSVE2orSME() const { return hasSVE2() || hasSME(); } // Return the known range for the bit length of SVE data registers. A value // of 0 means nothing is known about that particular limit beyong what's @@ -433,13 +434,13 @@ public: const char* getChkStkName() const { if (isWindowsArm64EC()) - return "__chkstk_arm64ec"; + return "#__chkstk_arm64ec"; return "__chkstk"; } const char* getSecurityCheckCookieName() const { if (isWindowsArm64EC()) - return "__security_check_cookie_arm64ec"; + return "#__security_check_cookie_arm64ec"; return "__security_check_cookie"; } diff --git a/llvm/lib/Target/AArch64/AArch64SystemOperands.td b/llvm/lib/Target/AArch64/AArch64SystemOperands.td index 0b80f263e12..0564741c497 100644 --- a/llvm/lib/Target/AArch64/AArch64SystemOperands.td +++ b/llvm/lib/Target/AArch64/AArch64SystemOperands.td @@ -986,8 +986,10 @@ def : RWSysReg<"SPSR_irq", 0b11, 0b100, 0b0100, 0b0011, 0b000>; def : RWSysReg<"SPSR_abt", 0b11, 0b100, 0b0100, 0b0011, 0b001>; def : RWSysReg<"SPSR_und", 0b11, 0b100, 0b0100, 0b0011, 0b010>; def : RWSysReg<"SPSR_fiq", 0b11, 0b100, 0b0100, 0b0011, 0b011>; +let Requires = [{ {AArch64::FeatureFPARMv8} }] in { def : RWSysReg<"FPCR", 0b11, 0b011, 0b0100, 0b0100, 0b000>; def : RWSysReg<"FPSR", 0b11, 0b011, 0b0100, 0b0100, 0b001>; +} def : RWSysReg<"DSPSR_EL0", 0b11, 0b011, 0b0100, 0b0101, 0b000>; def : RWSysReg<"DLR_EL0", 0b11, 0b011, 0b0100, 0b0101, 0b001>; def : RWSysReg<"IFSR32_EL2", 0b11, 0b100, 0b0101, 0b0000, 0b001>; diff --git a/llvm/lib/Target/AArch64/AArch64TargetMachine.cpp b/llvm/lib/Target/AArch64/AArch64TargetMachine.cpp index 144610e021c..6fbc13d8904 100644 --- a/llvm/lib/Target/AArch64/AArch64TargetMachine.cpp +++ b/llvm/lib/Target/AArch64/AArch64TargetMachine.cpp @@ -632,8 +632,12 @@ void AArch64PassConfig::addIRPasses() { addPass(createSMEABIPass()); // Add Control Flow Guard checks. - if (TM->getTargetTriple().isOSWindows()) - addPass(createCFGuardCheckPass()); + if (TM->getTargetTriple().isOSWindows()) { + if (TM->getTargetTriple().isWindowsArm64EC()) + addPass(createAArch64Arm64ECCallLoweringPass()); + else + addPass(createCFGuardCheckPass()); + } if (TM->Options.JMCInstrument) addPass(createJMCInstrumenterPass()); diff --git a/llvm/lib/Target/AArch64/AArch64TargetObjectFile.cpp b/llvm/lib/Target/AArch64/AArch64TargetObjectFile.cpp index 7ed934cfabc..e5c6b6d60d0 100644 --- a/llvm/lib/Target/AArch64/AArch64TargetObjectFile.cpp +++ b/llvm/lib/Target/AArch64/AArch64TargetObjectFile.cpp @@ -25,6 +25,16 @@ void AArch64_ELFTargetObjectFile::Initialize(MCContext &Ctx, SupportDebugThreadLocalLocation = false; } +const MCExpr *AArch64_ELFTargetObjectFile::getIndirectSymViaGOTPCRel( + const GlobalValue *GV, const MCSymbol *Sym, const MCValue &MV, + int64_t Offset, MachineModuleInfo *MMI, MCStreamer &Streamer) const { + int64_t FinalOffset = Offset + MV.getConstant(); + const MCExpr *Res = + MCSymbolRefExpr::create(Sym, MCSymbolRefExpr::VK_GOTPCREL, getContext()); + const MCExpr *Off = MCConstantExpr::create(FinalOffset, getContext()); + return MCBinaryExpr::createAdd(Res, Off, getContext()); +} + AArch64_MachoTargetObjectFile::AArch64_MachoTargetObjectFile() { SupportGOTPCRelWithOffset = false; } diff --git a/llvm/lib/Target/AArch64/AArch64TargetObjectFile.h b/llvm/lib/Target/AArch64/AArch64TargetObjectFile.h index 9f098230bbd..7cd56fc9a18 100644 --- a/llvm/lib/Target/AArch64/AArch64TargetObjectFile.h +++ b/llvm/lib/Target/AArch64/AArch64TargetObjectFile.h @@ -21,7 +21,14 @@ class AArch64_ELFTargetObjectFile : public TargetLoweringObjectFileELF { public: AArch64_ELFTargetObjectFile() { PLTRelativeVariantKind = MCSymbolRefExpr::VK_PLT; + SupportIndirectSymViaGOTPCRel = true; } + + const MCExpr *getIndirectSymViaGOTPCRel(const GlobalValue *GV, + const MCSymbol *Sym, + const MCValue &MV, int64_t Offset, + MachineModuleInfo *MMI, + MCStreamer &Streamer) const override; }; /// AArch64_MachoTargetObjectFile - This TLOF implementation is used for Darwin. diff --git a/llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp b/llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp index 13b5e578391..d611338fc26 100644 --- a/llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp +++ b/llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp @@ -55,6 +55,9 @@ static cl::opt InlineCallPenaltyChangeSM( "inline-call-penalty-sm-change", cl::init(10), cl::Hidden, cl::desc("Penalty of inlining a call that requires a change to PSTATE.SM")); +static cl::opt EnableOrLikeSelectOpt("enable-aarch64-or-like-select", + cl::init(true), cl::Hidden); + namespace { class TailFoldingOption { // These bitfields will only ever be set to something non-zero in operator=, @@ -236,8 +239,9 @@ bool AArch64TTIImpl::areInlineCompatible(const Function *Caller, return false; if (CallerAttrs.requiresLazySave(CalleeAttrs) || - CallerAttrs.requiresSMChange(CalleeAttrs, - /*BodyOverridesInterface=*/true)) { + (CallerAttrs.requiresSMChange(CalleeAttrs) && + (!CallerAttrs.hasStreamingInterfaceOrBody() || + !CalleeAttrs.hasStreamingBody()))) { if (hasPossibleIncompatibleOps(Callee)) return false; } @@ -3176,14 +3180,47 @@ InstructionCost AArch64TTIImpl::getMemoryOpCost(unsigned Opcode, Type *Ty, if (Ty->isPtrOrPtrVectorTy()) return LT.first; - // Check truncating stores and extending loads. - if (useNeonVector(Ty) && - Ty->getScalarSizeInBits() != LT.second.getScalarSizeInBits()) { - // v4i8 types are lowered to scalar a load/store and sshll/xtn. - if (VT == MVT::v4i8) - return 2; - // Otherwise we need to scalarize. - return cast(Ty)->getNumElements() * 2; + if (useNeonVector(Ty)) { + // Check truncating stores and extending loads. + if (Ty->getScalarSizeInBits() != LT.second.getScalarSizeInBits()) { + // v4i8 types are lowered to scalar a load/store and sshll/xtn. + if (VT == MVT::v4i8) + return 2; + // Otherwise we need to scalarize. + return cast(Ty)->getNumElements() * 2; + } + EVT EltVT = VT.getVectorElementType(); + unsigned EltSize = EltVT.getScalarSizeInBits(); + if (!isPowerOf2_32(EltSize) || EltSize < 8 || EltSize > 64 || + VT.getVectorNumElements() >= (128 / EltSize) || !Alignment || + *Alignment != Align(1)) + return LT.first; + // FIXME: v3i8 lowering currently is very inefficient, due to automatic + // widening to v4i8, which produces suboptimal results. + if (VT.getVectorNumElements() == 3 && EltVT == MVT::i8) + return LT.first; + + // Check non-power-of-2 loads/stores for legal vector element types with + // NEON. Non-power-of-2 memory ops will get broken down to a set of + // operations on smaller power-of-2 ops, including ld1/st1. + LLVMContext &C = Ty->getContext(); + InstructionCost Cost(0); + SmallVector TypeWorklist; + TypeWorklist.push_back(VT); + while (!TypeWorklist.empty()) { + EVT CurrVT = TypeWorklist.pop_back_val(); + unsigned CurrNumElements = CurrVT.getVectorNumElements(); + if (isPowerOf2_32(CurrNumElements)) { + Cost += 1; + continue; + } + + unsigned PrevPow2 = NextPowerOf2(CurrNumElements) / 2; + TypeWorklist.push_back(EVT::getVectorVT(C, EltVT, PrevPow2)); + TypeWorklist.push_back( + EVT::getVectorVT(C, EltVT, CurrNumElements - PrevPow2)); + } + return Cost; } return LT.first; @@ -4014,3 +4051,15 @@ AArch64TTIImpl::getScalingFactorCost(Type *Ty, GlobalValue *BaseGV, return AM.Scale != 0 && AM.Scale != 1; return -1; } + +bool AArch64TTIImpl::shouldTreatInstructionLikeSelect(const Instruction *I) { + // For the binary operators (e.g. or) we need to be more careful than + // selects, here we only transform them if they are already at a natural + // break point in the code - the end of a block with an unconditional + // terminator. + if (EnableOrLikeSelectOpt && I->getOpcode() == Instruction::Or && + isa(I->getNextNode()) && + cast(I->getNextNode())->isUnconditional()) + return true; + return BaseT::shouldTreatInstructionLikeSelect(I); +} \ No newline at end of file diff --git a/llvm/lib/Target/AArch64/AArch64TargetTransformInfo.h b/llvm/lib/Target/AArch64/AArch64TargetTransformInfo.h index f471294ffc2..de39dea2be4 100644 --- a/llvm/lib/Target/AArch64/AArch64TargetTransformInfo.h +++ b/llvm/lib/Target/AArch64/AArch64TargetTransformInfo.h @@ -412,6 +412,8 @@ public: bool enableSelectOptimize() { return ST->enableSelectOptimize(); } + bool shouldTreatInstructionLikeSelect(const Instruction *I); + unsigned getStoreMinimumVF(unsigned VF, Type *ScalarMemTy, Type *ScalarValTy) const { // We can vectorize store v4i8. diff --git a/llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp b/llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp index be66790c427..e9d96f3b838 100644 --- a/llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp +++ b/llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp @@ -3858,7 +3858,7 @@ bool AArch64AsmParser::parseSysAlias(StringRef Name, SMLoc NameLoc, Lex(); // Eat operand. - bool ExpectRegister = (Op.lower().find("all") == StringRef::npos); + bool ExpectRegister = !Op.contains_insensitive("all"); bool HasRegister = false; // Check for the optional register operand. @@ -6110,6 +6110,9 @@ bool AArch64AsmParser::showMatchError(SMLoc Loc, unsigned ErrCode, case Match_AddSubLSLImm3ShiftLarge: return Error(Loc, "expected 'lsl' with optional integer in range [0, 7]"); + case Match_InvalidSVEPNRasPPRPredicateBReg: + return Error(Loc, + "Expected predicate-as-counter register name with .B suffix"); default: llvm_unreachable("unexpected error code!"); } @@ -6690,6 +6693,7 @@ bool AArch64AsmParser::MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode, case Match_InvalidSVEVectorListStrided4x16: case Match_InvalidSVEVectorListStrided4x32: case Match_InvalidSVEVectorListStrided4x64: + case Match_InvalidSVEPNRasPPRPredicateBReg: case Match_MSR: case Match_MRS: { if (ErrorInfo >= Operands.size()) @@ -6864,7 +6868,7 @@ bool AArch64AsmParser::parseDirectiveArch(SMLoc L) { std::tie(Arch, ExtensionString) = getParser().parseStringToEndOfStatement().trim().split('+'); - std::optional ArchInfo = AArch64::parseArch(Arch); + const AArch64::ArchInfo *ArchInfo = AArch64::parseArch(Arch); if (!ArchInfo) return Error(ArchLoc, "unknown arch name"); @@ -6890,12 +6894,7 @@ bool AArch64AsmParser::parseDirectiveArch(SMLoc L) { FeatureBitset Features = STI.getFeatureBits(); setAvailableFeatures(ComputeAvailableFeatures(Features)); for (auto Name : RequestedExtensions) { - bool EnableFeature = true; - - if (Name.starts_with_insensitive("no")) { - EnableFeature = false; - Name = Name.substr(2); - } + bool EnableFeature = !Name.consume_front_insensitive("no"); for (const auto &Extension : ExtensionMap) { if (Extension.Name != Name) @@ -6971,7 +6970,7 @@ bool AArch64AsmParser::parseDirectiveCPU(SMLoc L) { if (!ExtensionString.empty()) ExtensionString.split(RequestedExtensions, '+'); - const std::optional CpuArch = llvm::AArch64::getArchForCpu(CPU); + const llvm::AArch64::ArchInfo *CpuArch = llvm::AArch64::getArchForCpu(CPU); if (!CpuArch) { Error(CurLoc, "unknown CPU name"); return false; @@ -6986,12 +6985,7 @@ bool AArch64AsmParser::parseDirectiveCPU(SMLoc L) { // Advance source location past '+'. CurLoc = incrementLoc(CurLoc, 1); - bool EnableFeature = true; - - if (Name.starts_with_insensitive("no")) { - EnableFeature = false; - Name = Name.substr(2); - } + bool EnableFeature = !Name.consume_front_insensitive("no"); bool FoundExtension = false; for (const auto &Extension : ExtensionMap) { diff --git a/llvm/lib/Target/AArch64/GISel/AArch64CallLowering.cpp b/llvm/lib/Target/AArch64/GISel/AArch64CallLowering.cpp index 84057ea8d22..ba70187994a 100644 --- a/llvm/lib/Target/AArch64/GISel/AArch64CallLowering.cpp +++ b/llvm/lib/Target/AArch64/GISel/AArch64CallLowering.cpp @@ -637,7 +637,18 @@ bool AArch64CallLowering::lowerFormalArguments( MachineRegisterInfo &MRI = MF.getRegInfo(); auto &DL = F.getParent()->getDataLayout(); auto &Subtarget = MF.getSubtarget(); - // TODO: Support Arm64EC + + // Arm64EC has extra requirements for varargs calls which are only implemented + // in SelectionDAG; bail out for now. + if (F.isVarArg() && Subtarget.isWindowsArm64EC()) + return false; + + // Arm64EC thunks have a special calling convention which is only implemented + // in SelectionDAG; bail out for now. + if (F.getCallingConv() == CallingConv::ARM64EC_Thunk_Native || + F.getCallingConv() == CallingConv::ARM64EC_Thunk_X64) + return false; + bool IsWin64 = Subtarget.isCallingConvWin64(F.getCallingConv()) && !Subtarget.isWindowsArm64EC(); SmallVector SplitArgs; @@ -1205,7 +1216,16 @@ bool AArch64CallLowering::lowerCall(MachineIRBuilder &MIRBuilder, const AArch64Subtarget &Subtarget = MF.getSubtarget(); // Arm64EC has extra requirements for varargs calls; bail out for now. - if (Info.IsVarArg && Subtarget.isWindowsArm64EC()) + // + // Arm64EC has special mangling rules for calls; bail out on all calls for + // now. + if (Subtarget.isWindowsArm64EC()) + return false; + + // Arm64EC thunks have a special calling convention which is only implemented + // in SelectionDAG; bail out for now. + if (Info.CallConv == CallingConv::ARM64EC_Thunk_Native || + Info.CallConv == CallingConv::ARM64EC_Thunk_X64) return false; SmallVector OutArgs; diff --git a/llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp b/llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp index a4ace6cce46..8344e79f78e 100644 --- a/llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp +++ b/llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp @@ -5610,7 +5610,7 @@ MachineInstr *AArch64InstructionSelector::tryAdvSIMDModImmFP( bool AArch64InstructionSelector::selectIndexedExtLoad( MachineInstr &MI, MachineRegisterInfo &MRI) { - auto &ExtLd = cast(MI); + auto &ExtLd = cast(MI); Register Dst = ExtLd.getDstReg(); Register WriteBack = ExtLd.getWritebackReg(); Register Base = ExtLd.getBaseReg(); @@ -5697,10 +5697,6 @@ bool AArch64InstructionSelector::selectIndexedExtLoad( bool AArch64InstructionSelector::selectIndexedLoad(MachineInstr &MI, MachineRegisterInfo &MRI) { - // TODO: extending loads. - if (isa(MI)) - return false; - auto &Ld = cast(MI); Register Dst = Ld.getDstReg(); Register WriteBack = Ld.getWritebackReg(); @@ -5710,6 +5706,9 @@ bool AArch64InstructionSelector::selectIndexedLoad(MachineInstr &MI, "Unexpected type for indexed load"); unsigned MemSize = Ld.getMMO().getMemoryType().getSizeInBytes(); + if (MemSize < MRI.getType(Dst).getSizeInBytes()) + return selectIndexedExtLoad(MI, MRI); + unsigned Opc = 0; if (Ld.isPre()) { static constexpr unsigned GPROpcodes[] = { diff --git a/llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp b/llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp index 302116447ef..fd69a7d6c33 100644 --- a/llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp +++ b/llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp @@ -169,6 +169,8 @@ AArch64LegalizerInfo::AArch64LegalizerInfo(const AArch64Subtarget &ST) .widenScalarToNextPow2(0) .clampScalar(1, s32, s64) .clampScalar(0, s32, s64) + .clampNumElements(0, v8s8, v16s8) + .clampNumElements(0, v4s16, v8s16) .clampNumElements(0, v2s32, v4s32) .clampNumElements(0, v2s64, v2s64) .moreElementsToNextPow2(0) @@ -449,10 +451,8 @@ AArch64LegalizerInfo::AArch64LegalizerInfo(const AArch64Subtarget &ST) auto IndexedLoadBasicPred = [=](const LegalityQuery &Query) { LLT LdTy = Query.Types[0]; LLT PtrTy = Query.Types[1]; - if (llvm::find(PackedVectorAllTypesVec, LdTy) == - PackedVectorAllTypesVec.end() && - llvm::find(ScalarAndPtrTypesVec, LdTy) == ScalarAndPtrTypesVec.end() && - LdTy != s128) + if (!llvm::is_contained(PackedVectorAllTypesVec, LdTy) && + !llvm::is_contained(ScalarAndPtrTypesVec, LdTy) && LdTy != s128) return false; if (PtrTy != p0) return false; @@ -497,6 +497,7 @@ AArch64LegalizerInfo::AArch64LegalizerInfo(const AArch64Subtarget &ST) }) .clampScalar(0, MinFPScalar, s128); + // FIXME: fix moreElementsToNextPow2 getActionDefinitionsBuilder(G_ICMP) .legalFor({{s32, s32}, {s32, s64}, @@ -526,7 +527,11 @@ AArch64LegalizerInfo::AArch64LegalizerInfo(const AArch64Subtarget &ST) .minScalarOrEltIf( [=](const LegalityQuery &Query) { return Query.Types[1] == v2p0; }, 0, s64) - .clampNumElements(0, v2s32, v4s32); + .moreElementsToNextPow2(0) + .clampNumElements(0, v8s8, v16s8) + .clampNumElements(0, v4s16, v8s16) + .clampNumElements(0, v2s32, v4s32) + .clampNumElements(0, v2s64, v2s64); getActionDefinitionsBuilder(G_FCMP) // If we don't have full FP16 support, then scalarize the elements of @@ -865,6 +870,7 @@ AArch64LegalizerInfo::AArch64LegalizerInfo(const AArch64Subtarget &ST) }, 0, s8) .minScalarOrElt(0, s8) // Worst case, we need at least s8. + .moreElementsToNextPow2(1) .clampMaxNumElements(1, s64, 2) .clampMaxNumElements(1, s32, 4) .clampMaxNumElements(1, s16, 8) @@ -1447,6 +1453,56 @@ bool AArch64LegalizerInfo::legalizeIntrinsic(LegalizerHelper &Helper, return true; } + case Intrinsic::aarch64_neon_uaddlp: + case Intrinsic::aarch64_neon_saddlp: { + MachineIRBuilder MIB(MI); + + unsigned Opc = IntrinsicID == Intrinsic::aarch64_neon_uaddlp + ? AArch64::G_UADDLP + : AArch64::G_SADDLP; + MIB.buildInstr(Opc, {MI.getOperand(0)}, {MI.getOperand(2)}); + MI.eraseFromParent(); + + return true; + } + case Intrinsic::aarch64_neon_uaddlv: + case Intrinsic::aarch64_neon_saddlv: { + MachineIRBuilder MIB(MI); + MachineRegisterInfo &MRI = *MIB.getMRI(); + + unsigned Opc = IntrinsicID == Intrinsic::aarch64_neon_uaddlv + ? AArch64::G_UADDLV + : AArch64::G_SADDLV; + Register DstReg = MI.getOperand(0).getReg(); + Register SrcReg = MI.getOperand(2).getReg(); + LLT DstTy = MRI.getType(DstReg); + + LLT MidTy, ExtTy; + if (DstTy.isScalar() && DstTy.getScalarSizeInBits() <= 32) { + MidTy = LLT::fixed_vector(4, 32); + ExtTy = LLT::scalar(32); + } else { + MidTy = LLT::fixed_vector(2, 64); + ExtTy = LLT::scalar(64); + } + + Register MidReg = + MIB.buildInstr(Opc, {MidTy}, {SrcReg})->getOperand(0).getReg(); + Register ZeroReg = + MIB.buildConstant(LLT::scalar(64), 0)->getOperand(0).getReg(); + Register ExtReg = MIB.buildInstr(AArch64::G_EXTRACT_VECTOR_ELT, {ExtTy}, + {MidReg, ZeroReg}) + .getReg(0); + + if (DstTy.getScalarSizeInBits() < 32) + MIB.buildTrunc(DstReg, ExtReg); + else + MIB.buildCopy(DstReg, ExtReg); + + MI.eraseFromParent(); + + return true; + } case Intrinsic::aarch64_neon_smax: case Intrinsic::aarch64_neon_smin: case Intrinsic::aarch64_neon_umax: diff --git a/llvm/lib/Target/AArch64/GISel/AArch64PreLegalizerCombiner.cpp b/llvm/lib/Target/AArch64/GISel/AArch64PreLegalizerCombiner.cpp index 71632718857..574d065ab01 100644 --- a/llvm/lib/Target/AArch64/GISel/AArch64PreLegalizerCombiner.cpp +++ b/llvm/lib/Target/AArch64/GISel/AArch64PreLegalizerCombiner.cpp @@ -21,6 +21,7 @@ #include "llvm/CodeGen/GlobalISel/GISelKnownBits.h" #include "llvm/CodeGen/GlobalISel/MIPatternMatch.h" #include "llvm/CodeGen/GlobalISel/MachineIRBuilder.h" +#include "llvm/CodeGen/GlobalISel/Utils.h" #include "llvm/CodeGen/MachineDominators.h" #include "llvm/CodeGen/MachineFunction.h" #include "llvm/CodeGen/MachineFunctionPass.h" @@ -335,53 +336,44 @@ void applyExtAddvToUdotAddv(MachineInstr &MI, MachineRegisterInfo &MRI, SmallVector Ext1UnmergeReg; SmallVector Ext2UnmergeReg; if (SrcTy.getNumElements() % 16 != 0) { - // Unmerge source to v8i8, append a new v8i8 of 0s and the merge to v16s - SmallVector PadUnmergeDstReg1; - SmallVector PadUnmergeDstReg2; - unsigned NumOfVec = SrcTy.getNumElements() / 8; + SmallVector Leftover1; + SmallVector Leftover2; - // Unmerge the source to v8i8 - MachineInstr *PadUnmerge1 = - Builder.buildUnmerge(LLT::fixed_vector(8, 8), Ext1SrcReg); - MachineInstr *PadUnmerge2 = - Builder.buildUnmerge(LLT::fixed_vector(8, 8), Ext2SrcReg); - for (unsigned i = 0; i < NumOfVec; i++) { - PadUnmergeDstReg1.push_back(PadUnmerge1->getOperand(i).getReg()); - PadUnmergeDstReg2.push_back(PadUnmerge2->getOperand(i).getReg()); + // Split the elements into v16i8 and v8i8 + LLT MainTy = LLT::fixed_vector(16, 8); + LLT LeftoverTy1, LeftoverTy2; + if ((!extractParts(Ext1SrcReg, MRI.getType(Ext1SrcReg), MainTy, + LeftoverTy1, Ext1UnmergeReg, Leftover1, Builder, + MRI)) || + (!extractParts(Ext2SrcReg, MRI.getType(Ext2SrcReg), MainTy, + LeftoverTy2, Ext2UnmergeReg, Leftover2, Builder, + MRI))) { + llvm_unreachable("Unable to split this vector properly"); } - // Pad the vectors with a v8i8 constant of 0s - MachineInstr *v8Zeroes = - Builder.buildConstant(LLT::fixed_vector(8, 8), 0); - PadUnmergeDstReg1.push_back(v8Zeroes->getOperand(0).getReg()); - PadUnmergeDstReg2.push_back(v8Zeroes->getOperand(0).getReg()); + // Pad the leftover v8i8 vector with register of 0s of type v8i8 + Register v8Zeroes = Builder.buildConstant(LLT::fixed_vector(8, 8), 0) + ->getOperand(0) + .getReg(); + + Ext1UnmergeReg.push_back( + Builder + .buildMergeLikeInstr(LLT::fixed_vector(16, 8), + {Leftover1[0], v8Zeroes}) + .getReg(0)); + Ext2UnmergeReg.push_back( + Builder + .buildMergeLikeInstr(LLT::fixed_vector(16, 8), + {Leftover2[0], v8Zeroes}) + .getReg(0)); - // Merge them all back to v16i8 - NumOfVec = (NumOfVec + 1) / 2; - for (unsigned i = 0; i < NumOfVec; i++) { - Ext1UnmergeReg.push_back( - Builder - .buildMergeLikeInstr( - LLT::fixed_vector(16, 8), - {PadUnmergeDstReg1[i * 2], PadUnmergeDstReg1[(i * 2) + 1]}) - .getReg(0)); - Ext2UnmergeReg.push_back( - Builder - .buildMergeLikeInstr( - LLT::fixed_vector(16, 8), - {PadUnmergeDstReg2[i * 2], PadUnmergeDstReg2[(i * 2) + 1]}) - .getReg(0)); - } } else { // Unmerge the source vectors to v16i8 - MachineInstr *Ext1Unmerge = - Builder.buildUnmerge(LLT::fixed_vector(16, 8), Ext1SrcReg); - MachineInstr *Ext2Unmerge = - Builder.buildUnmerge(LLT::fixed_vector(16, 8), Ext2SrcReg); - for (unsigned i = 0, e = SrcTy.getNumElements() / 16; i < e; i++) { - Ext1UnmergeReg.push_back(Ext1Unmerge->getOperand(i).getReg()); - Ext2UnmergeReg.push_back(Ext2Unmerge->getOperand(i).getReg()); - } + unsigned SrcNumElts = SrcTy.getNumElements(); + extractParts(Ext1SrcReg, LLT::fixed_vector(16, 8), SrcNumElts / 16, + Ext1UnmergeReg, Builder, MRI); + extractParts(Ext2SrcReg, LLT::fixed_vector(16, 8), SrcNumElts / 16, + Ext2UnmergeReg, Builder, MRI); } // Build the UDOT instructions @@ -418,6 +410,150 @@ void applyExtAddvToUdotAddv(MachineInstr &MI, MachineRegisterInfo &MRI, MI.eraseFromParent(); } +// Matches {U/S}ADDV(ext(x)) => {U/S}ADDLV(x) +// Ensure that the type coming from the extend instruction is the right size +bool matchExtUaddvToUaddlv(MachineInstr &MI, MachineRegisterInfo &MRI, + std::pair &MatchInfo) { + assert(MI.getOpcode() == TargetOpcode::G_VECREDUCE_ADD && + "Expected G_VECREDUCE_ADD Opcode"); + + // Check if the last instruction is an extend + MachineInstr *ExtMI = getDefIgnoringCopies(MI.getOperand(1).getReg(), MRI); + auto ExtOpc = ExtMI->getOpcode(); + + if (ExtOpc == TargetOpcode::G_ZEXT) + std::get<1>(MatchInfo) = 0; + else if (ExtOpc == TargetOpcode::G_SEXT) + std::get<1>(MatchInfo) = 1; + else + return false; + + // Check if the source register is a valid type + Register ExtSrcReg = ExtMI->getOperand(1).getReg(); + LLT ExtSrcTy = MRI.getType(ExtSrcReg); + LLT DstTy = MRI.getType(MI.getOperand(0).getReg()); + if ((DstTy.getScalarSizeInBits() == 16 && + ExtSrcTy.getNumElements() % 8 == 0 && ExtSrcTy.getNumElements() < 256) || + (DstTy.getScalarSizeInBits() == 32 && + ExtSrcTy.getNumElements() % 4 == 0) || + (DstTy.getScalarSizeInBits() == 64 && + ExtSrcTy.getNumElements() % 4 == 0)) { + std::get<0>(MatchInfo) = ExtSrcReg; + return true; + } + return false; +} + +void applyExtUaddvToUaddlv(MachineInstr &MI, MachineRegisterInfo &MRI, + MachineIRBuilder &B, GISelChangeObserver &Observer, + std::pair &MatchInfo) { + assert(MI.getOpcode() == TargetOpcode::G_VECREDUCE_ADD && + "Expected G_VECREDUCE_ADD Opcode"); + + unsigned Opc = std::get<1>(MatchInfo) ? AArch64::G_SADDLV : AArch64::G_UADDLV; + Register SrcReg = std::get<0>(MatchInfo); + Register DstReg = MI.getOperand(0).getReg(); + LLT SrcTy = MRI.getType(SrcReg); + LLT DstTy = MRI.getType(DstReg); + + // If SrcTy has more elements than expected, split them into multiple + // insructions and sum the results + LLT MainTy; + SmallVector WorkingRegisters; + unsigned SrcScalSize = SrcTy.getScalarSizeInBits(); + unsigned SrcNumElem = SrcTy.getNumElements(); + if ((SrcScalSize == 8 && SrcNumElem > 16) || + (SrcScalSize == 16 && SrcNumElem > 8) || + (SrcScalSize == 32 && SrcNumElem > 4)) { + + LLT LeftoverTy; + SmallVector LeftoverRegs; + if (SrcScalSize == 8) + MainTy = LLT::fixed_vector(16, 8); + else if (SrcScalSize == 16) + MainTy = LLT::fixed_vector(8, 16); + else if (SrcScalSize == 32) + MainTy = LLT::fixed_vector(4, 32); + else + llvm_unreachable("Source's Scalar Size not supported"); + + // Extract the parts and put each extracted sources through U/SADDLV and put + // the values inside a small vec + extractParts(SrcReg, SrcTy, MainTy, LeftoverTy, WorkingRegisters, + LeftoverRegs, B, MRI); + for (unsigned I = 0; I < LeftoverRegs.size(); I++) { + WorkingRegisters.push_back(LeftoverRegs[I]); + } + } else { + WorkingRegisters.push_back(SrcReg); + MainTy = SrcTy; + } + + unsigned MidScalarSize = MainTy.getScalarSizeInBits() * 2; + LLT MidScalarLLT = LLT::scalar(MidScalarSize); + Register zeroReg = B.buildConstant(LLT::scalar(64), 0).getReg(0); + for (unsigned I = 0; I < WorkingRegisters.size(); I++) { + // If the number of elements is too small to build an instruction, extend + // its size before applying addlv + LLT WorkingRegTy = MRI.getType(WorkingRegisters[I]); + if ((WorkingRegTy.getScalarSizeInBits() == 8) && + (WorkingRegTy.getNumElements() == 4)) { + WorkingRegisters[I] = + B.buildInstr(std::get<1>(MatchInfo) ? TargetOpcode::G_SEXT + : TargetOpcode::G_ZEXT, + {LLT::fixed_vector(4, 16)}, {WorkingRegisters[I]}) + .getReg(0); + } + + // Generate the {U/S}ADDLV instruction, whose output is always double of the + // Src's Scalar size + LLT addlvTy = MidScalarSize <= 32 ? LLT::fixed_vector(4, 32) + : LLT::fixed_vector(2, 64); + Register addlvReg = + B.buildInstr(Opc, {addlvTy}, {WorkingRegisters[I]}).getReg(0); + + // The output from {U/S}ADDLV gets placed in the lowest lane of a v4i32 or + // v2i64 register. + // i16, i32 results uses v4i32 registers + // i64 results uses v2i64 registers + // Therefore we have to extract/truncate the the value to the right type + if (MidScalarSize == 32 || MidScalarSize == 64) { + WorkingRegisters[I] = B.buildInstr(AArch64::G_EXTRACT_VECTOR_ELT, + {MidScalarLLT}, {addlvReg, zeroReg}) + .getReg(0); + } else { + Register extractReg = B.buildInstr(AArch64::G_EXTRACT_VECTOR_ELT, + {LLT::scalar(32)}, {addlvReg, zeroReg}) + .getReg(0); + WorkingRegisters[I] = + B.buildTrunc({MidScalarLLT}, {extractReg}).getReg(0); + } + } + + Register outReg; + if (WorkingRegisters.size() > 1) { + outReg = B.buildAdd(MidScalarLLT, WorkingRegisters[0], WorkingRegisters[1]) + .getReg(0); + for (unsigned I = 2; I < WorkingRegisters.size(); I++) { + outReg = B.buildAdd(MidScalarLLT, outReg, WorkingRegisters[I]).getReg(0); + } + } else { + outReg = WorkingRegisters[0]; + } + + if (DstTy.getScalarSizeInBits() > MidScalarSize) { + // Handle the scalar value if the DstTy's Scalar Size is more than double + // Src's ScalarType + B.buildInstr(std::get<1>(MatchInfo) ? TargetOpcode::G_SEXT + : TargetOpcode::G_ZEXT, + {DstReg}, {outReg}); + } else { + B.buildCopy(DstReg, outReg); + } + + MI.eraseFromParent(); +} + bool tryToSimplifyUADDO(MachineInstr &MI, MachineIRBuilder &B, CombinerHelper &Helper, GISelChangeObserver &Observer) { // Try simplify G_UADDO with 8 or 16 bit operands to wide G_ADD and TBNZ if diff --git a/llvm/lib/Target/AArch64/SMEABIPass.cpp b/llvm/lib/Target/AArch64/SMEABIPass.cpp index 3315171798d..0247488ce93 100644 --- a/llvm/lib/Target/AArch64/SMEABIPass.cpp +++ b/llvm/lib/Target/AArch64/SMEABIPass.cpp @@ -40,7 +40,8 @@ struct SMEABI : public FunctionPass { bool runOnFunction(Function &F) override; private: - bool updateNewZAFunctions(Module *M, Function *F, IRBuilder<> &Builder); + bool updateNewStateFunctions(Module *M, Function *F, IRBuilder<> &Builder, + SMEAttrs FnAttrs); }; } // end anonymous namespace @@ -76,56 +77,87 @@ void emitTPIDR2Save(Module *M, IRBuilder<> &Builder) { Builder.getInt64(0)); } -/// This function generates code to commit a lazy save at the beginning of a -/// function marked with `aarch64_pstate_za_new`. If the value read from -/// TPIDR2_EL0 is not null on entry to the function then the lazy-saving scheme -/// is active and we should call __arm_tpidr2_save to commit the lazy save. -/// Additionally, PSTATE.ZA should be enabled at the beginning of the function -/// and disabled before returning. -bool SMEABI::updateNewZAFunctions(Module *M, Function *F, - IRBuilder<> &Builder) { +/// This function generates code at the beginning and end of a function marked +/// with either `aarch64_pstate_za_new` or `aarch64_new_zt0`. +/// At the beginning of the function, the following code is generated: +/// - Commit lazy-save if active [Private-ZA Interface*] +/// - Enable PSTATE.ZA [Private-ZA Interface] +/// - Zero ZA [Has New ZA State] +/// - Zero ZT0 [Has New ZT0 State] +/// +/// * A function with new ZT0 state will not change ZA, so committing the +/// lazy-save is not strictly necessary. However, the lazy-save mechanism +/// may be active on entry to the function, with PSTATE.ZA set to 1. If +/// the new ZT0 function calls a function that does not share ZT0, we will +/// need to conditionally SMSTOP ZA before the call, setting PSTATE.ZA to 0. +/// For this reason, it's easier to always commit the lazy-save at the +/// beginning of the function regardless of whether it has ZA state. +/// +/// At the end of the function, PSTATE.ZA is disabled if the function has a +/// Private-ZA Interface. A function is considered to have a Private-ZA +/// interface if it does not share ZA or ZT0. +/// +bool SMEABI::updateNewStateFunctions(Module *M, Function *F, + IRBuilder<> &Builder, SMEAttrs FnAttrs) { LLVMContext &Context = F->getContext(); BasicBlock *OrigBB = &F->getEntryBlock(); - - // Create the new blocks for reading TPIDR2_EL0 & enabling ZA state. - auto *SaveBB = OrigBB->splitBasicBlock(OrigBB->begin(), "save.za", true); - auto *PreludeBB = BasicBlock::Create(Context, "prelude", F, SaveBB); - - // Read TPIDR2_EL0 in PreludeBB & branch to SaveBB if not 0. - Builder.SetInsertPoint(PreludeBB); - Function *TPIDR2Intr = - Intrinsic::getDeclaration(M, Intrinsic::aarch64_sme_get_tpidr2); - auto *TPIDR2 = Builder.CreateCall(TPIDR2Intr->getFunctionType(), TPIDR2Intr, - {}, "tpidr2"); - auto *Cmp = - Builder.CreateCmp(ICmpInst::ICMP_NE, TPIDR2, Builder.getInt64(0), "cmp"); - Builder.CreateCondBr(Cmp, SaveBB, OrigBB); - - // Create a call __arm_tpidr2_save, which commits the lazy save. - Builder.SetInsertPoint(&SaveBB->back()); - emitTPIDR2Save(M, Builder); - - // Enable pstate.za at the start of the function. Builder.SetInsertPoint(&OrigBB->front()); - Function *EnableZAIntr = - Intrinsic::getDeclaration(M, Intrinsic::aarch64_sme_za_enable); - Builder.CreateCall(EnableZAIntr->getFunctionType(), EnableZAIntr); - // ZA state must be zeroed upon entry to a function with NewZA - Function *ZeroIntr = - Intrinsic::getDeclaration(M, Intrinsic::aarch64_sme_zero); - Builder.CreateCall(ZeroIntr->getFunctionType(), ZeroIntr, - Builder.getInt32(0xff)); + // Commit any active lazy-saves if this is a Private-ZA function. If the + // value read from TPIDR2_EL0 is not null on entry to the function then + // the lazy-saving scheme is active and we should call __arm_tpidr2_save + // to commit the lazy save. + if (FnAttrs.hasPrivateZAInterface()) { + // Create the new blocks for reading TPIDR2_EL0 & enabling ZA state. + auto *SaveBB = OrigBB->splitBasicBlock(OrigBB->begin(), "save.za", true); + auto *PreludeBB = BasicBlock::Create(Context, "prelude", F, SaveBB); - // Before returning, disable pstate.za - for (BasicBlock &BB : *F) { - Instruction *T = BB.getTerminator(); - if (!T || !isa(T)) - continue; - Builder.SetInsertPoint(T); - Function *DisableZAIntr = - Intrinsic::getDeclaration(M, Intrinsic::aarch64_sme_za_disable); - Builder.CreateCall(DisableZAIntr->getFunctionType(), DisableZAIntr); + // Read TPIDR2_EL0 in PreludeBB & branch to SaveBB if not 0. + Builder.SetInsertPoint(PreludeBB); + Function *TPIDR2Intr = + Intrinsic::getDeclaration(M, Intrinsic::aarch64_sme_get_tpidr2); + auto *TPIDR2 = Builder.CreateCall(TPIDR2Intr->getFunctionType(), TPIDR2Intr, + {}, "tpidr2"); + auto *Cmp = Builder.CreateCmp(ICmpInst::ICMP_NE, TPIDR2, + Builder.getInt64(0), "cmp"); + Builder.CreateCondBr(Cmp, SaveBB, OrigBB); + + // Create a call __arm_tpidr2_save, which commits the lazy save. + Builder.SetInsertPoint(&SaveBB->back()); + emitTPIDR2Save(M, Builder); + + // Enable pstate.za at the start of the function. + Builder.SetInsertPoint(&OrigBB->front()); + Function *EnableZAIntr = + Intrinsic::getDeclaration(M, Intrinsic::aarch64_sme_za_enable); + Builder.CreateCall(EnableZAIntr->getFunctionType(), EnableZAIntr); + } + + if (FnAttrs.hasNewZABody()) { + Function *ZeroIntr = + Intrinsic::getDeclaration(M, Intrinsic::aarch64_sme_zero); + Builder.CreateCall(ZeroIntr->getFunctionType(), ZeroIntr, + Builder.getInt32(0xff)); + } + + if (FnAttrs.isNewZT0()) { + Function *ClearZT0Intr = + Intrinsic::getDeclaration(M, Intrinsic::aarch64_sme_zero_zt); + Builder.CreateCall(ClearZT0Intr->getFunctionType(), ClearZT0Intr, + {Builder.getInt32(0)}); + } + + if (FnAttrs.hasPrivateZAInterface()) { + // Before returning, disable pstate.za + for (BasicBlock &BB : *F) { + Instruction *T = BB.getTerminator(); + if (!T || !isa(T)) + continue; + Builder.SetInsertPoint(T); + Function *DisableZAIntr = + Intrinsic::getDeclaration(M, Intrinsic::aarch64_sme_za_disable); + Builder.CreateCall(DisableZAIntr->getFunctionType(), DisableZAIntr); + } } F->addFnAttr("aarch64_expanded_pstate_za"); @@ -142,8 +174,8 @@ bool SMEABI::runOnFunction(Function &F) { bool Changed = false; SMEAttrs FnAttrs(F); - if (FnAttrs.hasNewZABody()) - Changed |= updateNewZAFunctions(M, &F, Builder); + if (FnAttrs.hasNewZABody() || FnAttrs.isNewZT0()) + Changed |= updateNewStateFunctions(M, &F, Builder, FnAttrs); return Changed; } diff --git a/llvm/lib/Target/AArch64/Utils/AArch64BaseInfo.h b/llvm/lib/Target/AArch64/Utils/AArch64BaseInfo.h index 976e72e8aae..10e69655f77 100644 --- a/llvm/lib/Target/AArch64/Utils/AArch64BaseInfo.h +++ b/llvm/lib/Target/AArch64/Utils/AArch64BaseInfo.h @@ -248,6 +248,34 @@ static inline bool atomicBarrierDroppedOnZero(unsigned Opcode) { return false; } +static inline std::optional +getArm64ECMangledFunctionName(std::string Name) { + bool IsCppFn = Name[0] == '?'; + if (IsCppFn && Name.find("$$h") != std::string::npos) + return std::nullopt; + if (!IsCppFn && Name[0] == '#') + return std::nullopt; + + StringRef Prefix = "$$h"; + size_t InsertIdx = 0; + if (IsCppFn) { + InsertIdx = Name.find("@@"); + size_t ThreeAtSignsIdx = Name.find("@@@"); + if (InsertIdx != std::string::npos && InsertIdx != ThreeAtSignsIdx) { + InsertIdx += 2; + } else { + InsertIdx = Name.find("@"); + if (InsertIdx != std::string::npos) + InsertIdx++; + } + } else { + Prefix = "#"; + } + + Name.insert(Name.begin() + InsertIdx, Prefix.begin(), Prefix.end()); + return std::optional(Name); +} + namespace AArch64CC { // The CondCodes constants map directly to the 4-bit encoding of the condition @@ -795,12 +823,11 @@ namespace AArch64II { /// an LDG instruction to obtain the tag value. MO_TAGGED = 0x400, - /// MO_DLLIMPORTAUX - Symbol refers to "auxilliary" import stub. On - /// Arm64EC, there are two kinds of import stubs used for DLL import of - /// functions: MO_DLLIMPORT refers to natively callable Arm64 code, and - /// MO_DLLIMPORTAUX refers to the original address which can be compared - /// for equality. - MO_DLLIMPORTAUX = 0x800, + /// MO_ARM64EC_CALLMANGLE - Operand refers to the Arm64EC-mangled version + /// of a symbol, not the original. For dllimport symbols, this means it + /// uses "__imp_aux". For other symbols, this means it uses the mangled + /// ("#" prefix for C) name. + MO_ARM64EC_CALLMANGLE = 0x800, }; } // end namespace AArch64II diff --git a/llvm/lib/Target/AArch64/Utils/AArch64SMEAttributes.cpp b/llvm/lib/Target/AArch64/Utils/AArch64SMEAttributes.cpp index 0082b401798..3ee54e5df0a 100644 --- a/llvm/lib/Target/AArch64/Utils/AArch64SMEAttributes.cpp +++ b/llvm/lib/Target/AArch64/Utils/AArch64SMEAttributes.cpp @@ -18,16 +18,24 @@ void SMEAttrs::set(unsigned M, bool Enable) { else Bitmask &= ~M; + // Streaming Mode Attrs assert(!(hasStreamingInterface() && hasStreamingCompatibleInterface()) && "SM_Enabled and SM_Compatible are mutually exclusive"); - assert(!(hasNewZABody() && hasSharedZAInterface()) && + + // ZA Attrs + assert(!(hasNewZABody() && sharesZA()) && "ZA_New and ZA_Shared are mutually exclusive"); assert(!(hasNewZABody() && preservesZA()) && "ZA_New and ZA_Preserved are mutually exclusive"); - assert(!(hasNewZABody() && (Bitmask & ZA_NoLazySave)) && - "ZA_New and ZA_NoLazySave are mutually exclusive"); - assert(!(hasSharedZAInterface() && (Bitmask & ZA_NoLazySave)) && - "ZA_Shared and ZA_NoLazySave are mutually exclusive"); + assert(!(hasNewZABody() && (Bitmask & SME_ABI_Routine)) && + "ZA_New and SME_ABI_Routine are mutually exclusive"); + + // ZT0 Attrs + assert( + (!sharesZT0() || (isNewZT0() ^ isInZT0() ^ isInOutZT0() ^ isOutZT0() ^ + isPreservesZT0())) && + "Attributes 'aarch64_new_zt0', 'aarch64_in_zt0', 'aarch64_out_zt0', " + "'aarch64_inout_zt0' and 'aarch64_preserves_zt0' are mutually exclusive"); } SMEAttrs::SMEAttrs(const CallBase &CB) { @@ -39,11 +47,10 @@ SMEAttrs::SMEAttrs(const CallBase &CB) { SMEAttrs::SMEAttrs(StringRef FuncName) : Bitmask(0) { if (FuncName == "__arm_tpidr2_save" || FuncName == "__arm_sme_state") - Bitmask |= (SMEAttrs::SM_Compatible | SMEAttrs::ZA_Preserved | - SMEAttrs::ZA_NoLazySave); + Bitmask |= (SMEAttrs::SM_Compatible | SMEAttrs::SME_ABI_Routine); if (FuncName == "__arm_tpidr2_restore") Bitmask |= (SMEAttrs::SM_Compatible | SMEAttrs::ZA_Shared | - SMEAttrs::ZA_NoLazySave); + SMEAttrs::SME_ABI_Routine); } SMEAttrs::SMEAttrs(const AttributeList &Attrs) { @@ -60,29 +67,29 @@ SMEAttrs::SMEAttrs(const AttributeList &Attrs) { Bitmask |= ZA_New; if (Attrs.hasFnAttr("aarch64_pstate_za_preserved")) Bitmask |= ZA_Preserved; + if (Attrs.hasFnAttr("aarch64_in_zt0")) + Bitmask |= encodeZT0State(StateValue::In); + if (Attrs.hasFnAttr("aarch64_out_zt0")) + Bitmask |= encodeZT0State(StateValue::Out); + if (Attrs.hasFnAttr("aarch64_inout_zt0")) + Bitmask |= encodeZT0State(StateValue::InOut); + if (Attrs.hasFnAttr("aarch64_preserves_zt0")) + Bitmask |= encodeZT0State(StateValue::Preserved); + if (Attrs.hasFnAttr("aarch64_new_zt0")) + Bitmask |= encodeZT0State(StateValue::New); } -std::optional -SMEAttrs::requiresSMChange(const SMEAttrs &Callee, - bool BodyOverridesInterface) const { - // If the transition is not through a call (e.g. when considering inlining) - // and Callee has a streaming body, then we can ignore the interface of - // Callee. - if (BodyOverridesInterface && Callee.hasStreamingBody()) { - return hasStreamingInterfaceOrBody() ? std::nullopt - : std::optional(true); - } - +bool SMEAttrs::requiresSMChange(const SMEAttrs &Callee) const { if (Callee.hasStreamingCompatibleInterface()) - return std::nullopt; + return false; // Both non-streaming if (hasNonStreamingInterfaceAndBody() && Callee.hasNonStreamingInterface()) - return std::nullopt; + return false; // Both streaming if (hasStreamingInterfaceOrBody() && Callee.hasStreamingInterface()) - return std::nullopt; + return false; - return Callee.hasStreamingInterface(); + return true; } diff --git a/llvm/lib/Target/AArch64/Utils/AArch64SMEAttributes.h b/llvm/lib/Target/AArch64/Utils/AArch64SMEAttributes.h index e766b778b54..27b7075a094 100644 --- a/llvm/lib/Target/AArch64/Utils/AArch64SMEAttributes.h +++ b/llvm/lib/Target/AArch64/Utils/AArch64SMEAttributes.h @@ -26,17 +26,27 @@ class SMEAttrs { unsigned Bitmask; public: + enum class StateValue { + None = 0, + In = 1, // aarch64_in_zt0 + Out = 2, // aarch64_out_zt0 + InOut = 3, // aarch64_inout_zt0 + Preserved = 4, // aarch64_preserves_zt0 + New = 5 // aarch64_new_zt0 + }; + // Enum with bitmasks for each individual SME feature. enum Mask { Normal = 0, - SM_Enabled = 1 << 0, // aarch64_pstate_sm_enabled - SM_Compatible = 1 << 1, // aarch64_pstate_sm_compatible - SM_Body = 1 << 2, // aarch64_pstate_sm_body - ZA_Shared = 1 << 3, // aarch64_pstate_sm_shared - ZA_New = 1 << 4, // aarch64_pstate_sm_new - ZA_Preserved = 1 << 5, // aarch64_pstate_sm_preserved - ZA_NoLazySave = 1 << 6, // Used for SME ABI routines to avoid lazy saves - All = ZA_Preserved - 1 + SM_Enabled = 1 << 0, // aarch64_pstate_sm_enabled + SM_Compatible = 1 << 1, // aarch64_pstate_sm_compatible + SM_Body = 1 << 2, // aarch64_pstate_sm_body + ZA_Shared = 1 << 3, // aarch64_pstate_sm_shared + ZA_New = 1 << 4, // aarch64_pstate_sm_new + ZA_Preserved = 1 << 5, // aarch64_pstate_sm_preserved + SME_ABI_Routine = 1 << 6, // Used for SME ABI routines to avoid lazy saves + ZT0_Shift = 7, + ZT0_Mask = 0b111 << ZT0_Shift }; SMEAttrs(unsigned Mask = Normal) : Bitmask(0) { set(Mask); } @@ -65,26 +75,52 @@ public: /// \return true if a call from Caller -> Callee requires a change in /// streaming mode. - /// If \p BodyOverridesInterface is true and Callee has a streaming body, - /// then requiresSMChange considers a call to Callee as having a Streaming - /// interface. This can be useful when considering e.g. inlining, where we - /// explicitly want the body to overrule the interface (because after inlining - /// the interface is no longer relevant). - std::optional - requiresSMChange(const SMEAttrs &Callee, - bool BodyOverridesInterface = false) const; + bool requiresSMChange(const SMEAttrs &Callee) const; // Interfaces to query PSTATE.ZA bool hasNewZABody() const { return Bitmask & ZA_New; } - bool hasSharedZAInterface() const { return Bitmask & ZA_Shared; } + bool sharesZA() const { return Bitmask & ZA_Shared; } + bool hasSharedZAInterface() const { return sharesZA() || sharesZT0(); } bool hasPrivateZAInterface() const { return !hasSharedZAInterface(); } bool preservesZA() const { return Bitmask & ZA_Preserved; } - bool hasZAState() const { - return hasNewZABody() || hasSharedZAInterface(); - } + bool hasZAState() const { return hasNewZABody() || sharesZA(); } bool requiresLazySave(const SMEAttrs &Callee) const { return hasZAState() && Callee.hasPrivateZAInterface() && - !(Callee.Bitmask & ZA_NoLazySave); + !(Callee.Bitmask & SME_ABI_Routine); + } + + // Interfaces to query ZT0 State + static StateValue decodeZT0State(unsigned Bitmask) { + return static_cast((Bitmask & ZT0_Mask) >> ZT0_Shift); + } + static unsigned encodeZT0State(StateValue S) { + return static_cast(S) << ZT0_Shift; + } + + bool isNewZT0() const { return decodeZT0State(Bitmask) == StateValue::New; } + bool isInZT0() const { return decodeZT0State(Bitmask) == StateValue::In; } + bool isOutZT0() const { return decodeZT0State(Bitmask) == StateValue::Out; } + bool isInOutZT0() const { + return decodeZT0State(Bitmask) == StateValue::InOut; + } + bool isPreservesZT0() const { + return decodeZT0State(Bitmask) == StateValue::Preserved; + } + bool sharesZT0() const { + StateValue State = decodeZT0State(Bitmask); + return State == StateValue::In || State == StateValue::Out || + State == StateValue::InOut || State == StateValue::Preserved; + } + bool hasZT0State() const { return isNewZT0() || sharesZT0(); } + bool requiresPreservingZT0(const SMEAttrs &Callee) const { + return hasZT0State() && !Callee.sharesZT0(); + } + bool requiresDisablingZABeforeCall(const SMEAttrs &Callee) const { + return hasZT0State() && !hasZAState() && Callee.hasPrivateZAInterface() && + !(Callee.Bitmask & SME_ABI_Routine); + } + bool requiresEnablingZAAfterCall(const SMEAttrs &Callee) const { + return requiresLazySave(Callee) || requiresDisablingZABeforeCall(Callee); } }; diff --git a/llvm/lib/Target/AMDGPU/AMDGPU.h b/llvm/lib/Target/AMDGPU/AMDGPU.h index 35d33cb60bc..36af767a70b 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPU.h +++ b/llvm/lib/Target/AMDGPU/AMDGPU.h @@ -166,6 +166,9 @@ extern char &SILowerI1CopiesID; void initializeAMDGPUGlobalISelDivergenceLoweringPass(PassRegistry &); extern char &AMDGPUGlobalISelDivergenceLoweringID; +void initializeAMDGPUMarkLastScratchLoadPass(PassRegistry &); +extern char &AMDGPUMarkLastScratchLoadID; + void initializeSILowerSGPRSpillsPass(PassRegistry &); extern char &SILowerSGPRSpillsID; diff --git a/llvm/lib/Target/AMDGPU/AMDGPU.td b/llvm/lib/Target/AMDGPU/AMDGPU.td index df8c35ffd45..cb29d5d9475 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPU.td +++ b/llvm/lib/Target/AMDGPU/AMDGPU.td @@ -646,6 +646,12 @@ def FeatureFP8Insts : SubtargetFeature<"fp8-insts", "Has fp8 and bf8 instructions" >; +def FeatureFP8ConversionInsts : SubtargetFeature<"fp8-conversion-insts", + "HasFP8ConversionInsts", + "true", + "Has fp8 and bf8 conversion instructions" +>; + def FeaturePkFmacF16Inst : SubtargetFeature<"pk-fmac-f16-inst", "HasPkFmacF16Inst", "true", @@ -719,6 +725,18 @@ def FeatureFlatAtomicFaddF32Inst "Has flat_atomic_add_f32 instruction" >; +def FeatureDefaultComponentZero : SubtargetFeature<"default-component-zero", + "HasDefaultComponentZero", + "true", + "BUFFER/IMAGE store instructions set unspecified components to zero (before GFX12)" +>; + +def FeatureDefaultComponentBroadcast : SubtargetFeature<"default-component-broadcast", + "HasDefaultComponentBroadcast", + "true", + "BUFFER/IMAGE store instructions set unspecified components to x component (GFX12)" +>; + def FeatureSupportsSRAMECC : SubtargetFeature<"sramecc-support", "SupportsSRAMECC", "true", @@ -1003,7 +1021,7 @@ def FeatureSouthernIslands : GCNSubtargetFeatureGeneration<"SOUTHERN_ISLANDS", FeatureWavefrontSize64, FeatureSMemTimeInst, FeatureMadMacF32Insts, FeatureDsSrc2Insts, FeatureLDSBankCount32, FeatureMovrel, FeatureTrigReducedRange, FeatureExtendedImageInsts, FeatureImageInsts, - FeatureGDS, FeatureGWS + FeatureGDS, FeatureGWS, FeatureDefaultComponentZero ] >; @@ -1014,7 +1032,7 @@ def FeatureSeaIslands : GCNSubtargetFeatureGeneration<"SEA_ISLANDS", FeatureCIInsts, FeatureMovrel, FeatureTrigReducedRange, FeatureGFX7GFX8GFX9Insts, FeatureSMemTimeInst, FeatureMadMacF32Insts, FeatureDsSrc2Insts, FeatureExtendedImageInsts, FeatureUnalignedBufferAccess, - FeatureImageInsts, FeatureGDS, FeatureGWS + FeatureImageInsts, FeatureGDS, FeatureGWS, FeatureDefaultComponentZero ] >; @@ -1029,7 +1047,8 @@ def FeatureVolcanicIslands : GCNSubtargetFeatureGeneration<"VOLCANIC_ISLANDS", FeatureIntClamp, FeatureTrigReducedRange, FeatureGFX8Insts, FeatureGFX7GFX8GFX9Insts, FeatureSMemTimeInst, FeatureMadMacF32Insts, FeatureDsSrc2Insts, FeatureExtendedImageInsts, FeatureFastDenormalF32, - FeatureUnalignedBufferAccess, FeatureImageInsts, FeatureGDS, FeatureGWS + FeatureUnalignedBufferAccess, FeatureImageInsts, FeatureGDS, FeatureGWS, + FeatureDefaultComponentZero ] >; @@ -1047,7 +1066,7 @@ def FeatureGFX9 : GCNSubtargetFeatureGeneration<"GFX9", FeatureScalarFlatScratchInsts, FeatureScalarAtomics, FeatureR128A16, FeatureA16, FeatureSMemTimeInst, FeatureFastDenormalF32, FeatureSupportsXNACK, FeatureUnalignedBufferAccess, FeatureUnalignedDSAccess, - FeatureNegativeScratchOffsetBug, FeatureGWS + FeatureNegativeScratchOffsetBug, FeatureGWS, FeatureDefaultComponentZero ] >; @@ -1067,7 +1086,7 @@ def FeatureGFX10 : GCNSubtargetFeatureGeneration<"GFX10", FeatureNoDataDepHazard, FeaturePkFmacF16Inst, FeatureA16, FeatureSMemTimeInst, FeatureFastDenormalF32, FeatureG16, FeatureUnalignedBufferAccess, FeatureUnalignedDSAccess, FeatureImageInsts, - FeatureGDS, FeatureGWS + FeatureGDS, FeatureGWS, FeatureDefaultComponentZero ] >; @@ -1087,7 +1106,7 @@ def FeatureGFX11 : GCNSubtargetFeatureGeneration<"GFX11", FeatureNoDataDepHazard, FeaturePkFmacF16Inst, FeatureA16, FeatureFastDenormalF32, FeatureG16, FeatureUnalignedBufferAccess, FeatureUnalignedDSAccess, FeatureGDS, - FeatureGWS + FeatureGWS, FeatureDefaultComponentZero ] >; @@ -1107,7 +1126,7 @@ def FeatureGFX12 : GCNSubtargetFeatureGeneration<"GFX12", FeatureNoDataDepHazard, FeaturePkFmacF16Inst, FeatureA16, FeatureFastDenormalF32, FeatureG16, FeatureUnalignedBufferAccess, FeatureUnalignedDSAccess, - FeatureTrue16BitInsts + FeatureTrue16BitInsts, FeatureDefaultComponentBroadcast ] >; @@ -1311,6 +1330,7 @@ def FeatureISAVersion9_4_Common : FeatureSet< FeaturePackedFP32Ops, FeatureMAIInsts, FeatureFP8Insts, + FeatureFP8ConversionInsts, FeaturePkFmacF16Inst, FeatureAtomicFaddRtnInsts, FeatureAtomicFaddNoRtnInsts, @@ -1467,7 +1487,6 @@ def FeatureISAVersion12 : FeatureSet< [FeatureGFX12, FeatureLDSBankCount32, FeatureDLInsts, - FeatureDot5Insts, FeatureDot7Insts, FeatureDot8Insts, FeatureDot9Insts, @@ -1477,8 +1496,13 @@ def FeatureISAVersion12 : FeatureSet< FeatureWavefrontSize32, FeatureShaderCyclesHiLoRegisters, FeatureArchitectedFlatScratch, + FeatureArchitectedSGPRs, FeatureAtomicFaddRtnInsts, FeatureAtomicFaddNoRtnInsts, + FeatureAtomicDsPkAdd16Insts, + FeatureAtomicFlatPkAdd16Insts, + FeatureAtomicBufferGlobalPkAddF16Insts, + FeatureAtomicGlobalPkAddBF16Inst, FeatureFlatAtomicFaddF32Inst, FeatureImageInsts, FeatureExtendedImageInsts, @@ -1488,8 +1512,8 @@ def FeatureISAVersion12 : FeatureSet< FeaturePseudoScalarTrans, FeatureHasRestrictedSOffset, FeatureVGPRSingleUseHintInsts, - FeatureMADIntraFwdBug, - FeatureScalarDwordx3Loads]>; + FeatureScalarDwordx3Loads, + FeatureDPPSrc1SGPR]>; //===----------------------------------------------------------------------===// @@ -1981,6 +2005,9 @@ def HasShaderCyclesHiLoRegisters : Predicate<"Subtarget->hasShaderCyclesHiLoRegi def HasFP8Insts : Predicate<"Subtarget->hasFP8Insts()">, AssemblerPredicate<(all_of FeatureFP8Insts)>; +def HasFP8ConversionInsts : Predicate<"Subtarget->hasFP8ConversionInsts()">, + AssemblerPredicate<(all_of FeatureFP8ConversionInsts)>; + def HasPkFmacF16Inst : Predicate<"Subtarget->hasPkFmacF16Inst()">, AssemblerPredicate<(all_of FeaturePkFmacF16Inst)>; @@ -2013,6 +2040,13 @@ def HasFlatAtomicFaddF32Inst : Predicate<"Subtarget->hasFlatAtomicFaddF32Inst()">, AssemblerPredicate<(all_of FeatureFlatAtomicFaddF32Inst)>; +def HasDefaultComponentZero + : Predicate<"Subtarget->hasDefaultComponentZero()">, + AssemblerPredicate<(all_of FeatureDefaultComponentZero)>; +def HasDefaultComponentBroadcast + : Predicate<"Subtarget->hasDefaultComponentBroadcast()">, + AssemblerPredicate<(all_of FeatureDefaultComponentBroadcast)>; + def HasDsSrc2Insts : Predicate<"!Subtarget->hasDsSrc2Insts()">, AssemblerPredicate<(all_of FeatureDsSrc2Insts)>; diff --git a/llvm/lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp b/llvm/lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp index d317a733d43..279ef8ca275 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp +++ b/llvm/lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp @@ -123,8 +123,11 @@ void AMDGPUAsmPrinter::initTargetStreamer(Module &M) { getTargetStreamer()->EmitDirectiveAMDGCNTarget(); - if (TM.getTargetTriple().getOS() == Triple::AMDHSA) + if (TM.getTargetTriple().getOS() == Triple::AMDHSA) { + getTargetStreamer()->EmitDirectiveAMDHSACodeObjectVersion( + CodeObjectVersion); HSAMetadataStream->begin(M, *getTargetStreamer()->getTargetID()); + } if (TM.getTargetTriple().getOS() == Triple::AMDPAL) getTargetStreamer()->getPALMetadata()->readFromIR(M); @@ -230,8 +233,7 @@ void AMDGPUAsmPrinter::emitFunctionBodyEnd() { IsaInfo::getNumExtraSGPRs( &STM, CurrentProgramInfo.VCCUsed, CurrentProgramInfo.FlatUsed, getTargetStreamer()->getTargetID()->isXnackOnOrAny()), - CurrentProgramInfo.VCCUsed, CurrentProgramInfo.FlatUsed, - CodeObjectVersion); + CurrentProgramInfo.VCCUsed, CurrentProgramInfo.FlatUsed); Streamer.popSection(); } @@ -323,7 +325,7 @@ void AMDGPUAsmPrinter::emitGlobalVariable(const GlobalVariable *GV) { } bool AMDGPUAsmPrinter::doInitialization(Module &M) { - CodeObjectVersion = AMDGPU::getCodeObjectVersion(M); + CodeObjectVersion = AMDGPU::getAMDHSACodeObjectVersion(M); if (TM.getTargetTriple().getOS() == Triple::AMDHSA) { switch (CodeObjectVersion) { @@ -631,8 +633,8 @@ bool AMDGPUAsmPrinter::runOnMachineFunction(MachineFunction &MF) { void AMDGPUAsmPrinter::initializeTargetID(const Module &M) { // In the beginning all features are either 'Any' or 'NotSupported', // depending on global target features. This will cover empty modules. - getTargetStreamer()->initializeTargetID( - *getGlobalSTI(), getGlobalSTI()->getFeatureString(), CodeObjectVersion); + getTargetStreamer()->initializeTargetID(*getGlobalSTI(), + getGlobalSTI()->getFeatureString()); // If module is empty, we are done. if (M.empty()) @@ -981,8 +983,10 @@ void AMDGPUAsmPrinter::EmitProgramInfoSI(const MachineFunction &MF, OutStreamer->emitInt32(R_00B860_COMPUTE_TMPRING_SIZE); OutStreamer->emitInt32( - STM.getGeneration() >= AMDGPUSubtarget::GFX11 - ? S_00B860_WAVESIZE_GFX11Plus(CurrentProgramInfo.ScratchBlocks) + STM.getGeneration() >= AMDGPUSubtarget::GFX12 + ? S_00B860_WAVESIZE_GFX12Plus(CurrentProgramInfo.ScratchBlocks) + : STM.getGeneration() == AMDGPUSubtarget::GFX11 + ? S_00B860_WAVESIZE_GFX11(CurrentProgramInfo.ScratchBlocks) : S_00B860_WAVESIZE_PreGFX11(CurrentProgramInfo.ScratchBlocks)); // TODO: Should probably note flat usage somewhere. SC emits a "FlatPtr32 = @@ -993,8 +997,10 @@ void AMDGPUAsmPrinter::EmitProgramInfoSI(const MachineFunction &MF, S_00B028_SGPRS(CurrentProgramInfo.SGPRBlocks), 4); OutStreamer->emitInt32(R_0286E8_SPI_TMPRING_SIZE); OutStreamer->emitInt32( - STM.getGeneration() >= AMDGPUSubtarget::GFX11 - ? S_0286E8_WAVESIZE_GFX11Plus(CurrentProgramInfo.ScratchBlocks) + STM.getGeneration() >= AMDGPUSubtarget::GFX12 + ? S_0286E8_WAVESIZE_GFX12Plus(CurrentProgramInfo.ScratchBlocks) + : STM.getGeneration() == AMDGPUSubtarget::GFX11 + ? S_0286E8_WAVESIZE_GFX11(CurrentProgramInfo.ScratchBlocks) : S_0286E8_WAVESIZE_PreGFX11(CurrentProgramInfo.ScratchBlocks)); } diff --git a/llvm/lib/Target/AMDGPU/AMDGPUAttributor.cpp b/llvm/lib/Target/AMDGPU/AMDGPUAttributor.cpp index 5fd9e571282..d7f5110427e 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPUAttributor.cpp +++ b/llvm/lib/Target/AMDGPU/AMDGPUAttributor.cpp @@ -144,7 +144,7 @@ public: BumpPtrAllocator &Allocator, SetVector *CGSCC, TargetMachine &TM) : InformationCache(M, AG, Allocator, CGSCC), TM(TM), - CodeObjectVersion(AMDGPU::getCodeObjectVersion(M)) {} + CodeObjectVersion(AMDGPU::getAMDHSACodeObjectVersion(M)) {} TargetMachine &TM; diff --git a/llvm/lib/Target/AMDGPU/AMDGPUCallLowering.cpp b/llvm/lib/Target/AMDGPU/AMDGPUCallLowering.cpp index cf2896f80f1..6d05c3678bf 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPUCallLowering.cpp +++ b/llvm/lib/Target/AMDGPU/AMDGPUCallLowering.cpp @@ -474,7 +474,7 @@ static void allocateHSAUserSGPRs(CCState &CCInfo, const Module *M = MF.getFunction().getParent(); if (UserSGPRInfo.hasQueuePtr() && - AMDGPU::getCodeObjectVersion(*M) < AMDGPU::AMDHSA_COV5) { + AMDGPU::getAMDHSACodeObjectVersion(*M) < AMDGPU::AMDHSA_COV5) { Register QueuePtrReg = Info.addQueuePtr(TRI); MF.addLiveIn(QueuePtrReg, &AMDGPU::SGPR_64RegClass); CCInfo.AllocateReg(QueuePtrReg); @@ -632,10 +632,6 @@ bool AMDGPUCallLowering::lowerFormalArguments( const bool InReg = Arg.hasAttribute(Attribute::InReg); - // SGPR arguments to functions not implemented. - if (!IsGraphics && InReg) - return false; - if (Arg.hasAttribute(Attribute::SwiftSelf) || Arg.hasAttribute(Attribute::SwiftError) || Arg.hasAttribute(Attribute::Nest)) @@ -719,6 +715,10 @@ bool AMDGPUCallLowering::lowerFormalArguments( if (!IsEntryFunc && !IsGraphics) { // For the fixed ABI, pass workitem IDs in the last argument register. TLI.allocateSpecialInputVGPRsFixed(CCInfo, MF, *TRI, *Info); + + if (!Subtarget.enableFlatScratch()) + CCInfo.AllocateReg(Info->getScratchRSrcReg()); + TLI.allocateSpecialInputSGPRs(CCInfo, MF, *TRI, *Info); } IncomingValueAssigner Assigner(AssignFn); @@ -732,13 +732,8 @@ bool AMDGPUCallLowering::lowerFormalArguments( uint64_t StackSize = Assigner.StackSize; // Start adding system SGPRs. - if (IsEntryFunc) { + if (IsEntryFunc) TLI.allocateSystemSGPRs(CCInfo, MF, *Info, CC, IsGraphics); - } else { - if (!Subtarget.enableFlatScratch()) - CCInfo.AllocateReg(Info->getScratchRSrcReg()); - TLI.allocateSpecialInputSGPRs(CCInfo, MF, *TRI, *Info); - } // When we tail call, we need to check if the callee's arguments will fit on // the caller's stack. So, whenever we lower formal arguments, we should keep diff --git a/llvm/lib/Target/AMDGPU/AMDGPUGISel.td b/llvm/lib/Target/AMDGPU/AMDGPUGISel.td index 2b85024a9b4..a19b03b9292 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPUGISel.td +++ b/llvm/lib/Target/AMDGPU/AMDGPUGISel.td @@ -51,9 +51,9 @@ def gi_vop3pmodsdot : GIComplexOperandMatcher, GIComplexPatternEquiv; -def gi_dotiuvop3pmods : - GIComplexOperandMatcher, - GIComplexPatternEquiv; +def gi_vop3pmodsneg : + GIComplexOperandMatcher, + GIComplexPatternEquiv; def gi_wmmaopselvop3pmods : GIComplexOperandMatcher, @@ -261,10 +261,16 @@ def : GINodeEquiv; def : GINodeEquiv; def : GINodeEquiv; def : GINodeEquiv; +def : GINodeEquiv; def : GINodeEquiv; def : GINodeEquiv; def : GINodeEquiv; +def : GINodeEquiv; def : GINodeEquiv; +def : GINodeEquiv; +def : GINodeEquiv; +def : GINodeEquiv; +def : GINodeEquiv; def : GINodeEquiv; def : GINodeEquiv; @@ -379,8 +385,8 @@ def gi_extract_cpol : GICustomOperandRenderer<"renderExtractCPol">, def gi_extract_swz : GICustomOperandRenderer<"renderExtractSWZ">, GISDNodeXFormEquiv; -def gi_set_glc : GICustomOperandRenderer<"renderSetGLC">, - GISDNodeXFormEquiv; +def gi_extract_cpol_set_glc : GICustomOperandRenderer<"renderExtractCpolSetGLC">, + GISDNodeXFormEquiv; def gi_frameindex_to_targetframeindex : GICustomOperandRenderer<"renderFrameIndex">, GISDNodeXFormEquiv; diff --git a/llvm/lib/Target/AMDGPU/AMDGPUHSAMetadataStreamer.cpp b/llvm/lib/Target/AMDGPU/AMDGPUHSAMetadataStreamer.cpp index 74e9cd7d096..186fa58524b 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPUHSAMetadataStreamer.cpp +++ b/llvm/lib/Target/AMDGPU/AMDGPUHSAMetadataStreamer.cpp @@ -532,7 +532,8 @@ void MetadataStreamerMsgPackV4::emitKernel(const MachineFunction &MF, Func.getCallingConv() != CallingConv::SPIR_KERNEL) return; - auto CodeObjectVersion = AMDGPU::getCodeObjectVersion(*Func.getParent()); + auto CodeObjectVersion = + AMDGPU::getAMDHSACodeObjectVersion(*Func.getParent()); auto Kern = getHSAKernelProps(MF, ProgramInfo, CodeObjectVersion); auto Kernels = diff --git a/llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp b/llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp index 41462d7a133..4c35649cec6 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp +++ b/llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp @@ -1159,7 +1159,7 @@ bool AMDGPUDAGToDAGISel::isFlatScratchBaseLegal(SDValue Addr) const { // Starting with GFX12, VADDR and SADDR fields in VSCRATCH can use negative // values. - if (AMDGPU::isGFX12Plus(*Subtarget)) + if (Subtarget->hasSignedScratchOffsets()) return true; auto LHS = Addr.getOperand(0); @@ -1184,6 +1184,11 @@ bool AMDGPUDAGToDAGISel::isFlatScratchBaseLegalSV(SDValue Addr) const { if (isNoUnsignedWrap(Addr)) return true; + // Starting with GFX12, VADDR and SADDR fields in VSCRATCH can use negative + // values. + if (Subtarget->hasSignedScratchOffsets()) + return true; + auto LHS = Addr.getOperand(0); auto RHS = Addr.getOperand(1); return CurDAG->SignBitIsZero(RHS) && CurDAG->SignBitIsZero(LHS); @@ -1192,6 +1197,11 @@ bool AMDGPUDAGToDAGISel::isFlatScratchBaseLegalSV(SDValue Addr) const { // Check address value in SGPR/VGPR are legal for flat scratch in the form // of: SGPR + VGPR + Imm. bool AMDGPUDAGToDAGISel::isFlatScratchBaseLegalSVImm(SDValue Addr) const { + // Starting with GFX12, VADDR and SADDR fields in VSCRATCH can use negative + // values. + if (AMDGPU::isGFX12Plus(*Subtarget)) + return true; + auto Base = Addr.getOperand(0); auto *RHSImm = cast(Addr.getOperand(1)); // If the immediate offset is negative and within certain range, the base @@ -3009,7 +3019,7 @@ bool AMDGPUDAGToDAGISel::SelectVOP3PModsDOT(SDValue In, SDValue &Src, return SelectVOP3PMods(In, Src, SrcMods, true); } -bool AMDGPUDAGToDAGISel::SelectDotIUVOP3PMods(SDValue In, SDValue &Src) const { +bool AMDGPUDAGToDAGISel::SelectVOP3PModsNeg(SDValue In, SDValue &Src) const { const ConstantSDNode *C = cast(In); // Literal i1 value set in intrinsic, represents SrcMods for the next operand. // 1 promotes packed values to signed, 0 treats them as unsigned. @@ -3183,13 +3193,14 @@ bool AMDGPUDAGToDAGISel::isVGPRImm(const SDNode * N) const { return !AllUsesAcceptSReg && (Limit < 10); } -bool AMDGPUDAGToDAGISel::isUniformLoad(const SDNode * N) const { +bool AMDGPUDAGToDAGISel::isUniformLoad(const SDNode *N) const { auto Ld = cast(N); - if (N->isDivergent() && !AMDGPUInstrInfo::isUniformMMO(Ld->getMemOperand())) + const MachineMemOperand *MMO = Ld->getMemOperand(); + if (N->isDivergent() && !AMDGPUInstrInfo::isUniformMMO(MMO)) return false; - return Ld->getAlign() >= Align(4) && + return Ld->getAlign() >= Align(std::min(MMO->getSize(), uint64_t(4))) && ((Ld->getAddressSpace() == AMDGPUAS::CONSTANT_ADDRESS || Ld->getAddressSpace() == AMDGPUAS::CONSTANT_ADDRESS_32BIT) || (Subtarget->getScalarizeGlobalBehavior() && diff --git a/llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.h b/llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.h index df4a211d42a..8645490f0b1 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.h +++ b/llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.h @@ -237,7 +237,7 @@ private: bool IsDOT = false) const; bool SelectVOP3PModsDOT(SDValue In, SDValue &Src, SDValue &SrcMods) const; - bool SelectDotIUVOP3PMods(SDValue In, SDValue &Src) const; + bool SelectVOP3PModsNeg(SDValue In, SDValue &Src) const; bool SelectWMMAOpSelVOP3PMods(SDValue In, SDValue &Src) const; bool SelectVOP3OpSel(SDValue In, SDValue &Src, SDValue &SrcMods) const; diff --git a/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp b/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp index 0dbcaf5a1b1..55d95154c75 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp +++ b/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp @@ -446,6 +446,9 @@ AMDGPUTargetLowering::AMDGPUTargetLowering(const TargetMachine &TM, {ISD::CTTZ, ISD::CTTZ_ZERO_UNDEF, ISD::CTLZ, ISD::CTLZ_ZERO_UNDEF}, MVT::i64, Custom); + for (auto VT : {MVT::i8, MVT::i16}) + setOperationAction({ISD::CTLZ, ISD::CTLZ_ZERO_UNDEF}, VT, Custom); + static const MVT::SimpleValueType VectorIntTypes[] = { MVT::v2i32, MVT::v3i32, MVT::v4i32, MVT::v5i32, MVT::v6i32, MVT::v7i32, MVT::v9i32, MVT::v10i32, MVT::v11i32, MVT::v12i32}; @@ -784,6 +787,7 @@ bool AMDGPUTargetLowering::shouldReduceLoadWidth(SDNode *N, unsigned AS = MN->getAddressSpace(); // Do not shrink an aligned scalar load to sub-dword. // Scalar engine cannot do sub-dword loads. + // TODO: Update this for GFX12 which does have scalar sub-dword loads. if (OldSize >= 32 && NewSize < 32 && MN->getAlign() >= Align(4) && (AS == AMDGPUAS::CONSTANT_ADDRESS || AS == AMDGPUAS::CONSTANT_ADDRESS_32BIT || @@ -1397,6 +1401,11 @@ void AMDGPUTargetLowering::ReplaceNodeResults(SDNode *N, if (SDValue Lowered = lowerFEXP(SDValue(N, 0), DAG)) Results.push_back(Lowered); return; + case ISD::CTLZ: + case ISD::CTLZ_ZERO_UNDEF: + if (auto Lowered = lowerCTLZResults(SDValue(N, 0u), DAG)) + Results.push_back(Lowered); + return; default: return; } @@ -3062,6 +3071,26 @@ static bool isCttzOpc(unsigned Opc) { return Opc == ISD::CTTZ || Opc == ISD::CTTZ_ZERO_UNDEF; } +SDValue AMDGPUTargetLowering::lowerCTLZResults(SDValue Op, + SelectionDAG &DAG) const { + auto SL = SDLoc(Op); + auto Arg = Op.getOperand(0u); + auto ResultVT = Op.getValueType(); + + if (ResultVT != MVT::i8 && ResultVT != MVT::i16) + return {}; + + assert(isCtlzOpc(Op.getOpcode())); + assert(ResultVT == Arg.getValueType()); + + auto const LeadingZeroes = 32u - ResultVT.getFixedSizeInBits(); + auto NewOp = DAG.getNode(ISD::ZERO_EXTEND, SL, MVT::i32, Arg); + auto ShiftVal = DAG.getConstant(LeadingZeroes, SL, MVT::i32); + NewOp = DAG.getNode(ISD::SHL, SL, MVT::i32, NewOp, ShiftVal); + NewOp = DAG.getNode(Op.getOpcode(), SL, MVT::i32, NewOp); + return DAG.getNode(ISD::TRUNCATE, SL, ResultVT, NewOp); +} + SDValue AMDGPUTargetLowering::LowerCTLZ_CTTZ(SDValue Op, SelectionDAG &DAG) const { SDLoc SL(Op); SDValue Src = Op.getOperand(0); @@ -5453,6 +5482,10 @@ const char* AMDGPUTargetLowering::getTargetNodeName(unsigned Opcode) const { NODE_NAME_CASE(BUFFER_LOAD_FORMAT_TFE) NODE_NAME_CASE(BUFFER_LOAD_FORMAT_D16) NODE_NAME_CASE(SBUFFER_LOAD) + NODE_NAME_CASE(SBUFFER_LOAD_BYTE) + NODE_NAME_CASE(SBUFFER_LOAD_UBYTE) + NODE_NAME_CASE(SBUFFER_LOAD_SHORT) + NODE_NAME_CASE(SBUFFER_LOAD_USHORT) NODE_NAME_CASE(BUFFER_STORE) NODE_NAME_CASE(BUFFER_STORE_BYTE) NODE_NAME_CASE(BUFFER_STORE_SHORT) @@ -5473,8 +5506,10 @@ const char* AMDGPUTargetLowering::getTargetNodeName(unsigned Opcode) const { NODE_NAME_CASE(BUFFER_ATOMIC_CMPSWAP) NODE_NAME_CASE(BUFFER_ATOMIC_CSUB) NODE_NAME_CASE(BUFFER_ATOMIC_FADD) + NODE_NAME_CASE(BUFFER_ATOMIC_FADD_BF16) NODE_NAME_CASE(BUFFER_ATOMIC_FMIN) NODE_NAME_CASE(BUFFER_ATOMIC_FMAX) + NODE_NAME_CASE(BUFFER_ATOMIC_COND_SUB_U32) case AMDGPUISD::LAST_AMDGPU_ISD_NUMBER: break; } diff --git a/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.h b/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.h index 827fb106b55..f10a357125e 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.h +++ b/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.h @@ -84,6 +84,8 @@ protected: SDNodeFlags Flags) const; SDValue lowerFEXP(SDValue Op, SelectionDAG &DAG) const; + SDValue lowerCTLZResults(SDValue Op, SelectionDAG &DAG) const; + SDValue LowerCTLZ_CTTZ(SDValue Op, SelectionDAG &DAG) const; SDValue LowerINT_TO_FP32(SDValue Op, SelectionDAG &DAG, bool Signed) const; @@ -567,6 +569,10 @@ enum NodeType : unsigned { BUFFER_LOAD_FORMAT_TFE, BUFFER_LOAD_FORMAT_D16, SBUFFER_LOAD, + SBUFFER_LOAD_BYTE, + SBUFFER_LOAD_UBYTE, + SBUFFER_LOAD_SHORT, + SBUFFER_LOAD_USHORT, BUFFER_STORE, BUFFER_STORE_BYTE, BUFFER_STORE_SHORT, @@ -587,8 +593,10 @@ enum NodeType : unsigned { BUFFER_ATOMIC_CMPSWAP, BUFFER_ATOMIC_CSUB, BUFFER_ATOMIC_FADD, + BUFFER_ATOMIC_FADD_BF16, BUFFER_ATOMIC_FMIN, BUFFER_ATOMIC_FMAX, + BUFFER_ATOMIC_COND_SUB_U32, LAST_AMDGPU_ISD_NUMBER }; diff --git a/llvm/lib/Target/AMDGPU/AMDGPUInstCombineIntrinsic.cpp b/llvm/lib/Target/AMDGPU/AMDGPUInstCombineIntrinsic.cpp index 2bb7b6bd067..898289019c7 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPUInstCombineIntrinsic.cpp +++ b/llvm/lib/Target/AMDGPU/AMDGPUInstCombineIntrinsic.cpp @@ -402,6 +402,35 @@ static APInt trimTrailingZerosInVector(InstCombiner &IC, Value *UseV, return DemandedElts; } +// Trim elements of the end of the vector \p V, if they are +// equal to the first element of the vector. +static APInt defaultComponentBroadcast(Value *V) { + auto *VTy = cast(V->getType()); + unsigned VWidth = VTy->getNumElements(); + APInt DemandedElts = APInt::getAllOnes(VWidth); + Value *FirstComponent = findScalarElement(V, 0); + + SmallVector ShuffleMask; + if (auto *SVI = dyn_cast(V)) + SVI->getShuffleMask(ShuffleMask); + + for (int I = VWidth - 1; I > 0; --I) { + if (ShuffleMask.empty()) { + auto *Elt = findScalarElement(V, I); + if (!Elt || (Elt != FirstComponent && !isa(Elt))) + break; + } else { + // Detect identical elements in the shufflevector result, even though + // findScalarElement cannot tell us what that element is. + if (ShuffleMask[I] != ShuffleMask[0] && ShuffleMask[I] != PoisonMaskElem) + break; + } + DemandedElts.clearBit(I); + } + + return DemandedElts; +} + static Value *simplifyAMDGCNMemoryIntrinsicDemanded(InstCombiner &IC, IntrinsicInst &II, APInt DemandedElts, @@ -1140,8 +1169,13 @@ GCNTTIImpl::instCombineIntrinsic(InstCombiner &IC, IntrinsicInst &II) const { if (!isa(II.getArgOperand(0)->getType())) break; - APInt DemandedElts = - trimTrailingZerosInVector(IC, II.getArgOperand(0), &II); + APInt DemandedElts; + if (ST->hasDefaultComponentBroadcast()) + DemandedElts = defaultComponentBroadcast(II.getArgOperand(0)); + else if (ST->hasDefaultComponentZero()) + DemandedElts = trimTrailingZerosInVector(IC, II.getArgOperand(0), &II); + else + break; int DMaskIdx = getAMDGPUImageDMaskIntrinsic(II.getIntrinsicID()) ? 1 : -1; if (simplifyAMDGCNMemoryIntrinsicDemanded(IC, II, DemandedElts, DMaskIdx, diff --git a/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp b/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp index ad8dcda93c3..fdee74d58d2 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp +++ b/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp @@ -1917,7 +1917,8 @@ bool AMDGPUInstructionSelector::selectImageIntrinsic( unsigned CPol = MI.getOperand(ArgOffset + Intr->CachePolicyIndex).getImm(); if (BaseOpcode->Atomic) CPol |= AMDGPU::CPol::GLC; // TODO no-return optimization - if (CPol & ~(IsGFX12Plus ? AMDGPU::CPol::ALL : AMDGPU::CPol::ALL_pregfx12)) + if (CPol & ~((IsGFX12Plus ? AMDGPU::CPol::ALL : AMDGPU::CPol::ALL_pregfx12) | + AMDGPU::CPol::VOLATILE)) return false; int NumVAddrRegs = 0; @@ -3927,7 +3928,7 @@ AMDGPUInstructionSelector::selectVOP3PModsDOT(MachineOperand &Root) const { } InstructionSelector::ComplexRendererFns -AMDGPUInstructionSelector::selectDotIUVOP3PMods(MachineOperand &Root) const { +AMDGPUInstructionSelector::selectVOP3PModsNeg(MachineOperand &Root) const { // Literal i1 value set in intrinsic, represents SrcMods for the next operand. // Value is in Imm operand as i1 sign extended to int64_t. // 1(-1) promotes packed values to signed, 0 treats them as unsigned. @@ -4556,7 +4557,7 @@ bool AMDGPUInstructionSelector::isFlatScratchBaseLegal(Register Addr) const { // Starting with GFX12, VADDR and SADDR fields in VSCRATCH can use negative // values. - if (AMDGPU::isGFX12Plus(STI)) + if (STI.hasSignedScratchOffsets()) return true; Register LHS = AddrMI->getOperand(1).getReg(); @@ -4585,6 +4586,11 @@ bool AMDGPUInstructionSelector::isFlatScratchBaseLegalSV(Register Addr) const { if (isNoUnsignedWrap(AddrMI)) return true; + // Starting with GFX12, VADDR and SADDR fields in VSCRATCH can use negative + // values. + if (STI.hasSignedScratchOffsets()) + return true; + Register LHS = AddrMI->getOperand(1).getReg(); Register RHS = AddrMI->getOperand(2).getReg(); return KB->signBitIsZero(RHS) && KB->signBitIsZero(LHS); @@ -4594,6 +4600,11 @@ bool AMDGPUInstructionSelector::isFlatScratchBaseLegalSV(Register Addr) const { // of: SGPR + VGPR + Imm. bool AMDGPUInstructionSelector::isFlatScratchBaseLegalSVImm( Register Addr) const { + // Starting with GFX12, VADDR and SADDR fields in VSCRATCH can use negative + // values. + if (STI.hasSignedScratchOffsets()) + return true; + MachineInstr *AddrMI = getDefIgnoringCopies(Addr, *MRI); Register Base = AddrMI->getOperand(1).getReg(); std::optional BaseDef = @@ -5411,6 +5422,7 @@ bool AMDGPUInstructionSelector::selectNamedBarrierInst( I.eraseFromParent(); return true; } + bool AMDGPUInstructionSelector::selectSBarrierLeave(MachineInstr &I) const { MachineBasicBlock *BB = I.getParent(); const DebugLoc &DL = I.getDebugLoc(); @@ -5496,11 +5508,13 @@ void AMDGPUInstructionSelector::renderExtractSWZ(MachineInstrBuilder &MIB, MIB.addImm(Swizzle); } -void AMDGPUInstructionSelector::renderSetGLC(MachineInstrBuilder &MIB, - const MachineInstr &MI, - int OpIdx) const { +void AMDGPUInstructionSelector::renderExtractCpolSetGLC( + MachineInstrBuilder &MIB, const MachineInstr &MI, int OpIdx) const { assert(OpIdx >= 0 && "expected to match an immediate operand"); - MIB.addImm(MI.getOperand(OpIdx).getImm() | AMDGPU::CPol::GLC); + const uint32_t Cpol = MI.getOperand(OpIdx).getImm() & + (AMDGPU::isGFX12Plus(STI) ? AMDGPU::CPol::ALL + : AMDGPU::CPol::ALL_pregfx12); + MIB.addImm(Cpol | AMDGPU::CPol::GLC); } void AMDGPUInstructionSelector::renderFrameIndex(MachineInstrBuilder &MIB, diff --git a/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.h b/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.h index ab7cc0a6beb..12ea46c2895 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.h +++ b/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.h @@ -194,7 +194,7 @@ private: selectVOP3PModsDOT(MachineOperand &Root) const; InstructionSelector::ComplexRendererFns - selectDotIUVOP3PMods(MachineOperand &Root) const; + selectVOP3PModsNeg(MachineOperand &Root) const; InstructionSelector::ComplexRendererFns selectWMMAOpSelVOP3PMods(MachineOperand &Root) const; @@ -331,8 +331,8 @@ private: int OpIdx) const; void renderExtractSWZ(MachineInstrBuilder &MIB, const MachineInstr &MI, int OpIdx) const; - void renderSetGLC(MachineInstrBuilder &MIB, const MachineInstr &MI, - int OpIdx) const; + void renderExtractCpolSetGLC(MachineInstrBuilder &MIB, const MachineInstr &MI, + int OpIdx) const; void renderFrameIndex(MachineInstrBuilder &MIB, const MachineInstr &MI, int OpIdx) const; diff --git a/llvm/lib/Target/AMDGPU/AMDGPUInstructions.td b/llvm/lib/Target/AMDGPU/AMDGPUInstructions.td index 36e07d944c9..360aafedc52 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPUInstructions.td +++ b/llvm/lib/Target/AMDGPU/AMDGPUInstructions.td @@ -647,6 +647,9 @@ defm int_amdgcn_flat_atomic_fmin_num : noret_op; defm int_amdgcn_flat_atomic_fmax_num : noret_op; defm int_amdgcn_global_atomic_fmin_num : noret_op; defm int_amdgcn_global_atomic_fmax_num : noret_op; +defm int_amdgcn_atomic_cond_sub_u32 : local_addr_space_atomic_op; +defm int_amdgcn_atomic_cond_sub_u32 : flat_addr_space_atomic_op; +defm int_amdgcn_atomic_cond_sub_u32 : global_addr_space_atomic_op; multiclass noret_binary_atomic_op { let HasNoUse = true in diff --git a/llvm/lib/Target/AMDGPU/AMDGPULateCodeGenPrepare.cpp b/llvm/lib/Target/AMDGPU/AMDGPULateCodeGenPrepare.cpp index fb7148ba10a..69fdeaebe0a 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPULateCodeGenPrepare.cpp +++ b/llvm/lib/Target/AMDGPU/AMDGPULateCodeGenPrepare.cpp @@ -13,9 +13,11 @@ //===----------------------------------------------------------------------===// #include "AMDGPU.h" +#include "AMDGPUTargetMachine.h" #include "llvm/Analysis/AssumptionCache.h" #include "llvm/Analysis/UniformityAnalysis.h" #include "llvm/Analysis/ValueTracking.h" +#include "llvm/CodeGen/TargetPassConfig.h" #include "llvm/IR/IRBuilder.h" #include "llvm/IR/InstVisitor.h" #include "llvm/InitializePasses.h" @@ -58,6 +60,7 @@ public: } void getAnalysisUsage(AnalysisUsage &AU) const override { + AU.addRequired(); AU.addRequired(); AU.addRequired(); AU.setPreservesAll(); @@ -90,6 +93,12 @@ bool AMDGPULateCodeGenPrepare::runOnFunction(Function &F) { if (skipFunction(F)) return false; + const TargetPassConfig &TPC = getAnalysis(); + const TargetMachine &TM = TPC.getTM(); + const GCNSubtarget &ST = TM.getSubtarget(F); + if (ST.hasScalarSubwordLoads()) + return false; + AC = &getAnalysis().getAssumptionCache(F); UA = &getAnalysis().getUniformityInfo(); @@ -179,6 +188,7 @@ bool AMDGPULateCodeGenPrepare::visitLoadInst(LoadInst &LI) { INITIALIZE_PASS_BEGIN(AMDGPULateCodeGenPrepare, DEBUG_TYPE, "AMDGPU IR late optimizations", false, false) +INITIALIZE_PASS_DEPENDENCY(TargetPassConfig) INITIALIZE_PASS_DEPENDENCY(AssumptionCacheTracker) INITIALIZE_PASS_DEPENDENCY(UniformityInfoWrapperPass) INITIALIZE_PASS_END(AMDGPULateCodeGenPrepare, DEBUG_TYPE, diff --git a/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp b/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp index aa235c07e99..8e74d4c0e94 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp +++ b/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp @@ -2139,7 +2139,7 @@ Register AMDGPULegalizerInfo::getSegmentAperture( LLT::pointer(AMDGPUAS::CONSTANT_ADDRESS, 64)); // For code object version 5, private_base and shared_base are passed through // implicit kernargs. - if (AMDGPU::getCodeObjectVersion(*MF.getFunction().getParent()) >= + if (AMDGPU::getAMDHSACodeObjectVersion(*MF.getFunction().getParent()) >= AMDGPU::AMDHSA_COV5) { AMDGPUTargetLowering::ImplicitParameter Param = AS == AMDGPUAS::LOCAL_ADDRESS ? AMDGPUTargetLowering::SHARED_BASE @@ -5883,6 +5883,9 @@ static unsigned getBufferAtomicPseudo(Intrinsic::ID IntrID) { case Intrinsic::amdgcn_struct_buffer_atomic_fadd: case Intrinsic::amdgcn_struct_ptr_buffer_atomic_fadd: return AMDGPU::G_AMDGPU_BUFFER_ATOMIC_FADD; + case Intrinsic::amdgcn_raw_buffer_atomic_fadd_v2bf16: + case Intrinsic::amdgcn_struct_buffer_atomic_fadd_v2bf16: + return AMDGPU::G_AMDGPU_BUFFER_ATOMIC_FADD_BF16; case Intrinsic::amdgcn_raw_buffer_atomic_fmin: case Intrinsic::amdgcn_raw_ptr_buffer_atomic_fmin: case Intrinsic::amdgcn_struct_buffer_atomic_fmin: @@ -5893,6 +5896,9 @@ static unsigned getBufferAtomicPseudo(Intrinsic::ID IntrID) { case Intrinsic::amdgcn_struct_buffer_atomic_fmax: case Intrinsic::amdgcn_struct_ptr_buffer_atomic_fmax: return AMDGPU::G_AMDGPU_BUFFER_ATOMIC_FMAX; + case Intrinsic::amdgcn_raw_buffer_atomic_cond_sub_u32: + case Intrinsic::amdgcn_struct_buffer_atomic_cond_sub_u32: + return AMDGPU::G_AMDGPU_BUFFER_ATOMIC_COND_SUB_U32; default: llvm_unreachable("unhandled atomic opcode"); } @@ -6090,6 +6096,10 @@ bool AMDGPULegalizerInfo::legalizeImageIntrinsic( Register VData = MI.getOperand(NumDefs == 0 ? 1 : 0).getReg(); LLT Ty = MRI->getType(VData); + const bool IsAtomicPacked16Bit = + (BaseOpcode->BaseOpcode == AMDGPU::IMAGE_ATOMIC_PK_ADD_F16 || + BaseOpcode->BaseOpcode == AMDGPU::IMAGE_ATOMIC_PK_ADD_BF16); + // Check for 16 bit addresses and pack if true. LLT GradTy = MRI->getType(MI.getOperand(ArgOffset + Intr->GradientStart).getReg()); @@ -6098,7 +6108,7 @@ bool AMDGPULegalizerInfo::legalizeImageIntrinsic( const bool IsG16 = ST.hasG16() ? (BaseOpcode->Gradients && GradTy == S16) : GradTy == S16; const bool IsA16 = AddrTy == S16; - const bool IsD16 = Ty.getScalarType() == S16; + const bool IsD16 = !IsAtomicPacked16Bit && Ty.getScalarType() == S16; int DMaskLanes = 0; if (!BaseOpcode->Atomic) { @@ -6140,7 +6150,7 @@ bool AMDGPULegalizerInfo::legalizeImageIntrinsic( LLT Ty = MRI->getType(VData0); // TODO: Allow atomic swap and bit ops for v2s16/v4s16 - if (Ty.isVector()) + if (Ty.isVector() && !IsAtomicPacked16Bit) return false; if (BaseOpcode->AtomicX2) { @@ -6276,9 +6286,18 @@ bool AMDGPULegalizerInfo::legalizeImageIntrinsic( if (NumElts > 4 || DMaskLanes > 4) return false; + // Image atomic instructions are using DMask to specify how many bits + // input/output data will have. 32-bits (s32, v2s16) or 64-bits (s64, v4s16). + // DMaskLanes for image atomic has default value '0'. + // We must be sure that atomic variants (especially packed) will not be + // truncated from v2s16 or v4s16 to s16 type. + // + // ChangeElementCount will be needed for image load where Ty is always scalar. const unsigned AdjustedNumElts = DMaskLanes == 0 ? 1 : DMaskLanes; const LLT AdjustedTy = - Ty.changeElementCount(ElementCount::getFixed(AdjustedNumElts)); + DMaskLanes == 0 + ? Ty + : Ty.changeElementCount(ElementCount::getFixed(AdjustedNumElts)); // The raw dword aligned data component of the load. The only legal cases // where this matters should be when using the packed D16 format, for @@ -6443,15 +6462,28 @@ bool AMDGPULegalizerInfo::legalizeImageIntrinsic( return true; } -bool AMDGPULegalizerInfo::legalizeSBufferLoad( - LegalizerHelper &Helper, MachineInstr &MI) const { +bool AMDGPULegalizerInfo::legalizeSBufferLoad(LegalizerHelper &Helper, + MachineInstr &MI) const { MachineIRBuilder &B = Helper.MIRBuilder; GISelChangeObserver &Observer = Helper.Observer; - Register Dst = MI.getOperand(0).getReg(); - LLT Ty = B.getMRI()->getType(Dst); + Register OrigDst = MI.getOperand(0).getReg(); + Register Dst; + LLT Ty = B.getMRI()->getType(OrigDst); unsigned Size = Ty.getSizeInBits(); MachineFunction &MF = B.getMF(); + unsigned Opc = 0; + if (Size < 32 && ST.hasScalarSubwordLoads()) { + assert(Size == 8 || Size == 16); + Opc = Size == 8 ? AMDGPU::G_AMDGPU_S_BUFFER_LOAD_UBYTE + : AMDGPU::G_AMDGPU_S_BUFFER_LOAD_USHORT; + // The 8-bit and 16-bit scalar buffer load instructions have 32-bit + // destination register. + Dst = B.getMRI()->createGenericVirtualRegister(LLT::scalar(32)); + } else { + Opc = AMDGPU::G_AMDGPU_S_BUFFER_LOAD; + Dst = OrigDst; + } Observer.changingInstr(MI); @@ -6469,19 +6501,24 @@ bool AMDGPULegalizerInfo::legalizeSBufferLoad( // FIXME: We don't really need this intermediate instruction. The intrinsic // should be fixed to have a memory operand. Since it's readnone, we're not // allowed to add one. - MI.setDesc(B.getTII().get(AMDGPU::G_AMDGPU_S_BUFFER_LOAD)); + MI.setDesc(B.getTII().get(Opc)); MI.removeOperand(1); // Remove intrinsic ID // FIXME: When intrinsic definition is fixed, this should have an MMO already. // TODO: Should this use datalayout alignment? const unsigned MemSize = (Size + 7) / 8; - const Align MemAlign(4); + const Align MemAlign(std::min(MemSize, 4u)); MachineMemOperand *MMO = MF.getMachineMemOperand( MachinePointerInfo(), MachineMemOperand::MOLoad | MachineMemOperand::MODereferenceable | MachineMemOperand::MOInvariant, MemSize, MemAlign); MI.addMemOperand(MF, MMO); + if (Dst != OrigDst) { + MI.getOperand(0).setReg(Dst); + B.setInsertPt(B.getMBB(), ++B.getInsertPt()); + B.buildTrunc(OrigDst, Dst); + } // If we don't have 96-bit result scalar loads, widening to 128-bit should // always be legal. We may need to restore this to a 96-bit result if it turns @@ -6545,7 +6582,7 @@ bool AMDGPULegalizerInfo::legalizeTrapHsaQueuePtr( Register SGPR01(AMDGPU::SGPR0_SGPR1); // For code object version 5, queue_ptr is passed through implicit kernarg. - if (AMDGPU::getCodeObjectVersion(*MF.getFunction().getParent()) >= + if (AMDGPU::getAMDHSACodeObjectVersion(*MF.getFunction().getParent()) >= AMDGPU::AMDHSA_COV5) { AMDGPUTargetLowering::ImplicitParameter Param = AMDGPUTargetLowering::QUEUE_PTR; @@ -7080,6 +7117,10 @@ bool AMDGPULegalizerInfo::legalizeIntrinsic(LegalizerHelper &Helper, case Intrinsic::amdgcn_raw_ptr_buffer_atomic_fadd: case Intrinsic::amdgcn_struct_buffer_atomic_fadd: case Intrinsic::amdgcn_struct_ptr_buffer_atomic_fadd: + case Intrinsic::amdgcn_raw_buffer_atomic_fadd_v2bf16: + case Intrinsic::amdgcn_raw_ptr_buffer_atomic_fadd_v2bf16: + case Intrinsic::amdgcn_struct_buffer_atomic_fadd_v2bf16: + case Intrinsic::amdgcn_struct_ptr_buffer_atomic_fadd_v2bf16: return legalizeBufferAtomic(MI, B, IntrID); case Intrinsic::trap: return legalizeTrapIntrinsic(MI, MRI, B); diff --git a/llvm/lib/Target/AMDGPU/AMDGPULowerKernelArguments.cpp b/llvm/lib/Target/AMDGPU/AMDGPULowerKernelArguments.cpp index c32303defe7..015c71080d6 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPULowerKernelArguments.cpp +++ b/llvm/lib/Target/AMDGPU/AMDGPULowerKernelArguments.cpp @@ -106,7 +106,7 @@ static bool lowerKernelArguments(Function &F, const TargetMachine &TM) { LLVMContext &Ctx = F.getParent()->getContext(); const DataLayout &DL = F.getParent()->getDataLayout(); BasicBlock &EntryBlock = *F.begin(); - IRBuilder<> Builder(&*getInsertPt(EntryBlock)); + IRBuilder<> Builder(&EntryBlock, getInsertPt(EntryBlock)); const Align KernArgBaseAlign(16); // FIXME: Increase if necessary const uint64_t BaseOffset = ST.getExplicitKernelArgOffset(); @@ -202,6 +202,7 @@ static bool lowerKernelArguments(Function &F, const TargetMachine &TM) { // Since we don't have sub-dword scalar loads, avoid doing an extload by // loading earlier than the argument address, and extracting the relevant // bits. + // TODO: Update this for GFX12 which does have scalar sub-dword loads. // // Additionally widen any sub-dword load to i32 even if suitably aligned, // so that CSE between different argument loads works easily. diff --git a/llvm/lib/Target/AMDGPU/AMDGPULowerKernelAttributes.cpp b/llvm/lib/Target/AMDGPU/AMDGPULowerKernelAttributes.cpp index 097722157d4..bf7f67c086f 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPULowerKernelAttributes.cpp +++ b/llvm/lib/Target/AMDGPU/AMDGPULowerKernelAttributes.cpp @@ -323,7 +323,8 @@ static bool processUse(CallInst *CI, bool IsV5OrAbove) { // TargetPassConfig for subtarget. bool AMDGPULowerKernelAttributes::runOnModule(Module &M) { bool MadeChange = false; - bool IsV5OrAbove = AMDGPU::getCodeObjectVersion(M) >= AMDGPU::AMDHSA_COV5; + bool IsV5OrAbove = + AMDGPU::getAMDHSACodeObjectVersion(M) >= AMDGPU::AMDHSA_COV5; Function *BasePtr = getBasePtrIntrinsic(M, IsV5OrAbove); if (!BasePtr) // ImplicitArgPtr/DispatchPtr not used. @@ -356,7 +357,7 @@ ModulePass *llvm::createAMDGPULowerKernelAttributesPass() { PreservedAnalyses AMDGPULowerKernelAttributesPass::run(Function &F, FunctionAnalysisManager &AM) { bool IsV5OrAbove = - AMDGPU::getCodeObjectVersion(*F.getParent()) >= AMDGPU::AMDHSA_COV5; + AMDGPU::getAMDHSACodeObjectVersion(*F.getParent()) >= AMDGPU::AMDHSA_COV5; Function *BasePtr = getBasePtrIntrinsic(*F.getParent(), IsV5OrAbove); if (!BasePtr) // ImplicitArgPtr/DispatchPtr not used. diff --git a/llvm/lib/Target/AMDGPU/AMDGPUMachineCFGStructurizer.cpp b/llvm/lib/Target/AMDGPU/AMDGPUMachineCFGStructurizer.cpp index d90fcac8754..289c35e11be 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPUMachineCFGStructurizer.cpp +++ b/llvm/lib/Target/AMDGPU/AMDGPUMachineCFGStructurizer.cpp @@ -1721,7 +1721,7 @@ void AMDGPUMachineCFGStructurizer::insertMergePHI(MachineBasicBlock *IfBB, unsigned CodeSourceRegister, bool IsUndefIfSource) { // If this is the function exit block, we don't need a phi. - if (MergeBB->succ_begin() == MergeBB->succ_end()) { + if (MergeBB->succ_empty()) { return; } LLVM_DEBUG(dbgs() << "Merge PHI (" << printMBBReference(*MergeBB) diff --git a/llvm/lib/Target/AMDGPU/AMDGPUMarkLastScratchLoad.cpp b/llvm/lib/Target/AMDGPU/AMDGPUMarkLastScratchLoad.cpp new file mode 100644 index 00000000000..0692a12a406 --- /dev/null +++ b/llvm/lib/Target/AMDGPU/AMDGPUMarkLastScratchLoad.cpp @@ -0,0 +1,142 @@ +//===-- AMDGPUMarkLastScratchLoad.cpp -------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// +// +// Mark scratch load/spill instructions which are guaranteed to be the last time +// this scratch slot is used so it can be evicted from caches. +// +// TODO: Handle general stack accesses not just spilling. +// +//===----------------------------------------------------------------------===// + +#include "AMDGPU.h" +#include "GCNSubtarget.h" +#include "llvm/CodeGen/LiveIntervals.h" +#include "llvm/CodeGen/LiveStacks.h" +#include "llvm/CodeGen/MachineOperand.h" + +using namespace llvm; + +#define DEBUG_TYPE "amdgpu-mark-last-scratch-load" + +namespace { + +class AMDGPUMarkLastScratchLoad : public MachineFunctionPass { +private: + LiveStacks *LS = nullptr; + LiveIntervals *LIS = nullptr; + SlotIndexes *SI = nullptr; + const SIInstrInfo *SII = nullptr; + +public: + static char ID; + + AMDGPUMarkLastScratchLoad() : MachineFunctionPass(ID) { + initializeAMDGPUMarkLastScratchLoadPass(*PassRegistry::getPassRegistry()); + } + + bool runOnMachineFunction(MachineFunction &MF) override; + + void getAnalysisUsage(AnalysisUsage &AU) const override { + AU.addRequired(); + AU.addRequired(); + AU.addRequired(); + AU.setPreservesAll(); + MachineFunctionPass::getAnalysisUsage(AU); + } + + StringRef getPassName() const override { + return "AMDGPU Mark Last Scratch Load"; + } +}; + +} // end anonymous namespace + +bool AMDGPUMarkLastScratchLoad::runOnMachineFunction(MachineFunction &MF) { + if (skipFunction(MF.getFunction())) + return false; + + const GCNSubtarget &ST = MF.getSubtarget(); + if (ST.getGeneration() < AMDGPUSubtarget::GFX12) + return false; + + LS = &getAnalysis(); + LIS = &getAnalysis(); + SI = &getAnalysis(); + SII = ST.getInstrInfo(); + SlotIndexes &Slots = *LIS->getSlotIndexes(); + + const unsigned NumSlots = LS->getNumIntervals(); + if (NumSlots == 0) { + LLVM_DEBUG(dbgs() << "No live slots, skipping\n"); + return false; + } + + LLVM_DEBUG(dbgs() << LS->getNumIntervals() << " intervals\n"); + + bool Changed = false; + + for (auto &[SS, LI] : *LS) { + for (const LiveRange::Segment &Segment : LI.segments) { + + // Ignore segments that run to the end of basic block because in this case + // slot is still live at the end of it. + if (Segment.end.isBlock()) + continue; + + const int FrameIndex = Register::stackSlot2Index(LI.reg()); + MachineInstr *LastLoad = nullptr; + + MachineInstr *MISegmentEnd = SI->getInstructionFromIndex(Segment.end); + + // If there is no instruction at this slot because it was deleted take the + // instruction from the next slot. + if (!MISegmentEnd) { + SlotIndex NextSlot = Slots.getNextNonNullIndex(Segment.end); + MISegmentEnd = SI->getInstructionFromIndex(NextSlot); + } + + MachineInstr *MISegmentStart = SI->getInstructionFromIndex(Segment.start); + MachineBasicBlock *BB = MISegmentEnd->getParent(); + + // Start iteration backwards from segment end until the start of basic + // block or start of segment if it is in the same basic block. + auto End = BB->rend(); + if (MISegmentStart && MISegmentStart->getParent() == BB) + End = MISegmentStart->getReverseIterator(); + + for (auto MI = MISegmentEnd->getReverseIterator(); MI != End; ++MI) { + int LoadFI = 0; + + if (SII->isLoadFromStackSlot(*MI, LoadFI) && LoadFI == FrameIndex) { + LastLoad = &*MI; + break; + } + } + + if (LastLoad && !LastLoad->memoperands_empty()) { + MachineMemOperand *MMO = *LastLoad->memoperands_begin(); + MMO->setFlags(MOLastUse); + Changed = true; + LLVM_DEBUG(dbgs() << " Found last load: " << *LastLoad); + } + } + } + + return Changed; +} + +char AMDGPUMarkLastScratchLoad::ID = 0; + +char &llvm::AMDGPUMarkLastScratchLoadID = AMDGPUMarkLastScratchLoad::ID; + +INITIALIZE_PASS_BEGIN(AMDGPUMarkLastScratchLoad, DEBUG_TYPE, + "AMDGPU Mark last scratch load", false, false) +INITIALIZE_PASS_DEPENDENCY(SlotIndexes) +INITIALIZE_PASS_DEPENDENCY(LiveStacks) +INITIALIZE_PASS_END(AMDGPUMarkLastScratchLoad, DEBUG_TYPE, + "AMDGPU Mark last scratch load", false, false) diff --git a/llvm/lib/Target/AMDGPU/AMDGPUPostLegalizerCombiner.cpp b/llvm/lib/Target/AMDGPU/AMDGPUPostLegalizerCombiner.cpp index bb1d6cb72e8..a1c34e92a57 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPUPostLegalizerCombiner.cpp +++ b/llvm/lib/Target/AMDGPU/AMDGPUPostLegalizerCombiner.cpp @@ -411,6 +411,12 @@ bool AMDGPUPostLegalizerCombinerImpl::matchCombineSignExtendInReg( case AMDGPU::G_AMDGPU_BUFFER_LOAD_USHORT: MatchData = {LoadMI, AMDGPU::G_AMDGPU_BUFFER_LOAD_SSHORT}; return Width == 16; + case AMDGPU::G_AMDGPU_S_BUFFER_LOAD_UBYTE: + MatchData = {LoadMI, AMDGPU::G_AMDGPU_S_BUFFER_LOAD_SBYTE}; + return Width == 8; + case AMDGPU::G_AMDGPU_S_BUFFER_LOAD_USHORT: + MatchData = {LoadMI, AMDGPU::G_AMDGPU_S_BUFFER_LOAD_SSHORT}; + return Width == 16; } return false; } diff --git a/llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp b/llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp index 391c2b9ec25..bdd4e891f15 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp +++ b/llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp @@ -449,8 +449,13 @@ bool AMDGPURegisterBankInfo::isScalarLoadLegal(const MachineInstr &MI) const { const unsigned AS = MMO->getAddrSpace(); const bool IsConst = AS == AMDGPUAS::CONSTANT_ADDRESS || AS == AMDGPUAS::CONSTANT_ADDRESS_32BIT; + const unsigned MemSize = 8 * MMO->getSize(); + // Require 4-byte alignment. - return MMO->getAlign() >= Align(4) && + return (MMO->getAlign() >= Align(4) || + (Subtarget.hasScalarSubwordLoads() && + ((MemSize == 16 && MMO->getAlign() >= Align(2)) || + (MemSize == 8 && MMO->getAlign() >= Align(1))))) && // Can't do a scalar atomic load. !MMO->isAtomic() && // Don't use scalar loads for volatile accesses to non-constant address @@ -1074,6 +1079,13 @@ bool AMDGPURegisterBankInfo::applyMappingLoad( (MemSize == 32 || LoadTy.isVector() || !isScalarLoadLegal(MI))) return false; + if (LoadSize == 32 && + ((MemSize == 8 && MMO->getAlign() >= Align(1)) || + (MemSize == 16 && MMO->getAlign() >= Align(2))) && + isScalarLoadLegal(MI) && + Subtarget.getGeneration() >= AMDGPUSubtarget::GFX12) + return false; + Register PtrReg = MI.getOperand(1).getReg(); ApplyRegBankMapping ApplyBank(B, *this, MRI, DstBank); @@ -3062,6 +3074,7 @@ void AMDGPURegisterBankInfo::applyMappingImpl( return; } case AMDGPU::G_AMDGPU_BUFFER_ATOMIC_FADD: + case AMDGPU::G_AMDGPU_BUFFER_ATOMIC_FADD_BF16: case AMDGPU::G_AMDGPU_BUFFER_ATOMIC_FMIN: case AMDGPU::G_AMDGPU_BUFFER_ATOMIC_FMAX: { applyDefaultMapping(OpdMapper); @@ -3073,7 +3086,11 @@ void AMDGPURegisterBankInfo::applyMappingImpl( executeInWaterfallLoop(B, MI, {3, 6}); return; } - case AMDGPU::G_AMDGPU_S_BUFFER_LOAD: { + case AMDGPU::G_AMDGPU_S_BUFFER_LOAD: + case AMDGPU::G_AMDGPU_S_BUFFER_LOAD_UBYTE: + case AMDGPU::G_AMDGPU_S_BUFFER_LOAD_SBYTE: + case AMDGPU::G_AMDGPU_S_BUFFER_LOAD_USHORT: + case AMDGPU::G_AMDGPU_S_BUFFER_LOAD_SSHORT: { applyMappingSBufferLoad(B, OpdMapper); return; } @@ -3765,16 +3782,16 @@ AMDGPURegisterBankInfo::getInstrMapping(const MachineInstr &MI) const { // properly. // // TODO: There are additional exec masking dependencies to analyze. - if (MI.getOpcode() == TargetOpcode::G_PHI) { + if (auto *PHI = dyn_cast(&MI)) { unsigned ResultBank = AMDGPU::InvalidRegBankID; - Register DstReg = MI.getOperand(0).getReg(); + Register DstReg = PHI->getReg(0); // Sometimes the result may have already been assigned a bank. if (const RegisterBank *DstBank = getRegBank(DstReg, MRI, *TRI)) ResultBank = DstBank->getID(); - for (unsigned I = 1, E = MI.getNumOperands(); I != E; I += 2) { - Register Reg = MI.getOperand(I).getReg(); + for (unsigned I = 0; I < PHI->getNumIncomingValues(); ++I) { + Register Reg = PHI->getIncomingValue(I); const RegisterBank *Bank = getRegBank(Reg, MRI, *TRI); // FIXME: Assuming VGPR for any undetermined inputs. @@ -4346,6 +4363,7 @@ AMDGPURegisterBankInfo::getInstrMapping(const MachineInstr &MI) const { case AMDGPU::G_AMDGPU_BUFFER_ATOMIC_INC: case AMDGPU::G_AMDGPU_BUFFER_ATOMIC_DEC: case AMDGPU::G_AMDGPU_BUFFER_ATOMIC_FADD: + case AMDGPU::G_AMDGPU_BUFFER_ATOMIC_FADD_BF16: case AMDGPU::G_AMDGPU_BUFFER_ATOMIC_FMIN: case AMDGPU::G_AMDGPU_BUFFER_ATOMIC_FMAX: { // vdata_out @@ -4396,7 +4414,11 @@ AMDGPURegisterBankInfo::getInstrMapping(const MachineInstr &MI) const { // initialized. break; } - case AMDGPU::G_AMDGPU_S_BUFFER_LOAD: { + case AMDGPU::G_AMDGPU_S_BUFFER_LOAD: + case AMDGPU::G_AMDGPU_S_BUFFER_LOAD_UBYTE: + case AMDGPU::G_AMDGPU_S_BUFFER_LOAD_SBYTE: + case AMDGPU::G_AMDGPU_S_BUFFER_LOAD_USHORT: + case AMDGPU::G_AMDGPU_S_BUFFER_LOAD_SSHORT: { // Lie and claim everything is legal, even though some need to be // SGPRs. applyMapping will have to deal with it as a waterfall loop. OpdsMapping[1] = getSGPROpMapping(MI.getOperand(1).getReg(), MRI, *TRI); @@ -4471,6 +4493,10 @@ AMDGPURegisterBankInfo::getInstrMapping(const MachineInstr &MI) const { case Intrinsic::amdgcn_fdot2_f32_bf16: case Intrinsic::amdgcn_sudot4: case Intrinsic::amdgcn_sudot8: + case Intrinsic::amdgcn_dot4_f32_fp8_bf8: + case Intrinsic::amdgcn_dot4_f32_bf8_fp8: + case Intrinsic::amdgcn_dot4_f32_fp8_fp8: + case Intrinsic::amdgcn_dot4_f32_bf8_bf8: case Intrinsic::amdgcn_wmma_bf16_16x16x16_bf16: case Intrinsic::amdgcn_wmma_f16_16x16x16_f16: case Intrinsic::amdgcn_wmma_bf16_16x16x16_bf16_tied: @@ -4836,7 +4862,9 @@ AMDGPURegisterBankInfo::getInstrMapping(const MachineInstr &MI) const { case Intrinsic::amdgcn_flat_atomic_fmax_num: case Intrinsic::amdgcn_global_atomic_fadd_v2bf16: case Intrinsic::amdgcn_flat_atomic_fadd_v2bf16: + case Intrinsic::amdgcn_atomic_cond_sub_u32: case Intrinsic::amdgcn_global_atomic_ordered_add_b64: + case Intrinsic::amdgcn_global_load_tr: return getDefaultMappingAllVGPR(MI); case Intrinsic::amdgcn_ds_ordered_add: case Intrinsic::amdgcn_ds_ordered_swap: diff --git a/llvm/lib/Target/AMDGPU/AMDGPURemoveIncompatibleFunctions.cpp b/llvm/lib/Target/AMDGPU/AMDGPURemoveIncompatibleFunctions.cpp index 552380d54df..6f1236fd3b7 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPURemoveIncompatibleFunctions.cpp +++ b/llvm/lib/Target/AMDGPU/AMDGPURemoveIncompatibleFunctions.cpp @@ -105,7 +105,8 @@ constexpr unsigned FeaturesToCheck[] = {AMDGPU::FeatureGFX11Insts, AMDGPU::FeatureDot8Insts, AMDGPU::FeatureExtendedImageInsts, AMDGPU::FeatureSMemRealTime, - AMDGPU::FeatureSMemTimeInst}; + AMDGPU::FeatureSMemTimeInst, + AMDGPU::FeatureGWS}; FeatureBitset expandImpliedFeatures(const FeatureBitset &Features) { FeatureBitset Result = Features; diff --git a/llvm/lib/Target/AMDGPU/AMDGPUResourceUsageAnalysis.cpp b/llvm/lib/Target/AMDGPU/AMDGPUResourceUsageAnalysis.cpp index fc47b02c98e..0c759e7f3b0 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPUResourceUsageAnalysis.cpp +++ b/llvm/lib/Target/AMDGPU/AMDGPUResourceUsageAnalysis.cpp @@ -112,7 +112,7 @@ bool AMDGPUResourceUsageAnalysis::runOnModule(Module &M) { // By default, for code object v5 and later, track only the minimum scratch // size - if (AMDGPU::getCodeObjectVersion(M) >= AMDGPU::AMDHSA_COV5 || + if (AMDGPU::getAMDHSACodeObjectVersion(M) >= AMDGPU::AMDHSA_COV5 || STI.getTargetTriple().getOS() == Triple::AMDPAL) { if (!AssumedStackSizeForDynamicSizeObjects.getNumOccurrences()) AssumedStackSizeForDynamicSizeObjects = 0; diff --git a/llvm/lib/Target/AMDGPU/AMDGPUSearchableTables.td b/llvm/lib/Target/AMDGPU/AMDGPUSearchableTables.td index 4cc8871a00f..67263f23b98 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPUSearchableTables.td +++ b/llvm/lib/Target/AMDGPU/AMDGPUSearchableTables.td @@ -237,6 +237,7 @@ def : SourceOfDivergence; def : SourceOfDivergence; def : SourceOfDivergence; def : SourceOfDivergence; +def : SourceOfDivergence; def : SourceOfDivergence; def : SourceOfDivergence; def : SourceOfDivergence; @@ -279,9 +280,11 @@ def : SourceOfDivergence; def : SourceOfDivergence; def : SourceOfDivergence; def : SourceOfDivergence; +def : SourceOfDivergence; def : SourceOfDivergence; def : SourceOfDivergence; def : SourceOfDivergence; +def : SourceOfDivergence; def : SourceOfDivergence; def : SourceOfDivergence; def : SourceOfDivergence; @@ -295,9 +298,11 @@ def : SourceOfDivergence; def : SourceOfDivergence; def : SourceOfDivergence; def : SourceOfDivergence; +def : SourceOfDivergence; def : SourceOfDivergence; def : SourceOfDivergence; def : SourceOfDivergence; +def : SourceOfDivergence; def : SourceOfDivergence; def : SourceOfDivergence; def : SourceOfDivergence; @@ -311,9 +316,11 @@ def : SourceOfDivergence; def : SourceOfDivergence; def : SourceOfDivergence; def : SourceOfDivergence; +def : SourceOfDivergence; def : SourceOfDivergence; def : SourceOfDivergence; def : SourceOfDivergence; +def : SourceOfDivergence; def : SourceOfDivergence; def : SourceOfDivergence; def : SourceOfDivergence; @@ -327,9 +334,11 @@ def : SourceOfDivergence; def : SourceOfDivergence; def : SourceOfDivergence; def : SourceOfDivergence; +def : SourceOfDivergence; def : SourceOfDivergence; def : SourceOfDivergence; def : SourceOfDivergence; +def : SourceOfDivergence; def : SourceOfDivergence; def : SourceOfDivergence; def : SourceOfDivergence; @@ -405,6 +414,7 @@ def : SourceOfDivergence; def : SourceOfDivergence; def : SourceOfDivergence; def : SourceOfDivergence; +def : SourceOfDivergence; // The dummy boolean output is divergent from the IR's perspective, // but the mask results are uniform. These produce a divergent and diff --git a/llvm/lib/Target/AMDGPU/AMDGPUSubtarget.cpp b/llvm/lib/Target/AMDGPU/AMDGPUSubtarget.cpp index f19c5766856..bcc7dedf322 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPUSubtarget.cpp +++ b/llvm/lib/Target/AMDGPU/AMDGPUSubtarget.cpp @@ -571,7 +571,7 @@ unsigned AMDGPUSubtarget::getImplicitArgNumBytes(const Function &F) const { // Assume all implicit inputs are used by default const Module *M = F.getParent(); unsigned NBytes = - AMDGPU::getCodeObjectVersion(*M) >= AMDGPU::AMDHSA_COV5 ? 256 : 56; + AMDGPU::getAMDHSACodeObjectVersion(*M) >= AMDGPU::AMDHSA_COV5 ? 256 : 56; return F.getFnAttributeAsParsedInteger("amdgpu-implicitarg-num-bytes", NBytes); } diff --git a/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp b/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp index 0f3bb3e7b0d..b8a7a5e2080 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp +++ b/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp @@ -382,6 +382,7 @@ extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeAMDGPUTarget() { initializeSILowerI1CopiesPass(*PR); initializeAMDGPUGlobalISelDivergenceLoweringPass(*PR); initializeSILowerWWMCopiesPass(*PR); + initializeAMDGPUMarkLastScratchLoadPass(*PR); initializeSILowerSGPRSpillsPass(*PR); initializeSIFixSGPRCopiesPass(*PR); initializeSIFixVGPRCopiesPass(*PR); @@ -1424,6 +1425,8 @@ bool GCNPassConfig::addRegAssignAndRewriteOptimized() { addPreRewrite(); addPass(&VirtRegRewriterID); + addPass(&AMDGPUMarkLastScratchLoadID); + return true; } diff --git a/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp b/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp index ba79affe683..489cf85693e 100644 --- a/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp +++ b/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp @@ -346,7 +346,7 @@ public: } bool isVRegWithInputMods() const; - bool isT16VRegWithInputMods() const; + template bool isT16VRegWithInputMods() const; bool isSDWAOperand(MVT type) const; bool isSDWAFP16Operand() const; @@ -1303,10 +1303,8 @@ private: unsigned NextFreeSGPR, SMRange SGPRRange, unsigned &VGPRBlocks, unsigned &SGPRBlocks); bool ParseDirectiveAMDGCNTarget(); + bool ParseDirectiveAMDHSACodeObjectVersion(); bool ParseDirectiveAMDHSAKernel(); - bool ParseDirectiveMajorMinor(uint32_t &Major, uint32_t &Minor); - bool ParseDirectiveHSACodeObjectVersion(); - bool ParseDirectiveHSACodeObjectISA(); bool ParseAMDKernelCodeTValue(StringRef ID, amd_kernel_code_t &Header); bool ParseDirectiveAMDKernelCodeT(); // TODO: Possibly make subtargetHasRegister const. @@ -1688,6 +1686,7 @@ private: bool validateMIMGD16(const MCInst &Inst); bool validateMIMGMSAA(const MCInst &Inst); bool validateOpSel(const MCInst &Inst); + bool validateNeg(const MCInst &Inst, int OpName); bool validateDPP(const MCInst &Inst, const OperandVector &Operands); bool validateVccOperand(unsigned Reg) const; bool validateVOPLiteral(const MCInst &Inst, const OperandVector &Operands); @@ -2055,8 +2054,9 @@ bool AMDGPUOperand::isVRegWithInputMods() const { AsmParser->getFeatureBits()[AMDGPU::FeatureDPALU_DPP]); } -bool AMDGPUOperand::isT16VRegWithInputMods() const { - return isRegClass(AMDGPU::VGPR_32_Lo128RegClassID); +template bool AMDGPUOperand::isT16VRegWithInputMods() const { + return isRegClass(IsFake16 ? AMDGPU::VGPR_32_Lo128RegClassID + : AMDGPU::VGPR_16_Lo128RegClassID); } bool AMDGPUOperand::isSDWAOperand(MVT type) const { @@ -4357,6 +4357,41 @@ bool AMDGPUAsmParser::validateOpSel(const MCInst &Inst) { return true; } +bool AMDGPUAsmParser::validateNeg(const MCInst &Inst, int OpName) { + assert(OpName == AMDGPU::OpName::neg_lo || OpName == AMDGPU::OpName::neg_hi); + + const unsigned Opc = Inst.getOpcode(); + uint64_t TSFlags = MII.get(Opc).TSFlags; + + // v_dot4 fp8/bf8 neg_lo/neg_hi not allowed on src0 and src1 (allowed on src2) + if (!(TSFlags & SIInstrFlags::IsDOT)) + return true; + + int NegIdx = AMDGPU::getNamedOperandIdx(Opc, OpName); + if (NegIdx == -1) + return true; + + unsigned Neg = Inst.getOperand(NegIdx).getImm(); + + // Instructions that have neg_lo or neg_hi operand but neg modifier is allowed + // on some src operands but not allowed on other. + // It is convenient that such instructions don't have src_modifiers operand + // for src operands that don't allow neg because they also don't allow opsel. + + int SrcMods[3] = {AMDGPU::OpName::src0_modifiers, + AMDGPU::OpName::src1_modifiers, + AMDGPU::OpName::src2_modifiers}; + + for (unsigned i = 0; i < 3; ++i) { + if (!AMDGPU::hasNamedOperand(Opc, SrcMods[i])) { + if (Neg & (1 << i)) + return false; + } + } + + return true; +} + bool AMDGPUAsmParser::validateDPP(const MCInst &Inst, const OperandVector &Operands) { const unsigned Opc = Inst.getOpcode(); @@ -4834,6 +4869,16 @@ bool AMDGPUAsmParser::validateInstruction(const MCInst &Inst, "invalid op_sel operand"); return false; } + if (!validateNeg(Inst, AMDGPU::OpName::neg_lo)) { + Error(getImmLoc(AMDGPUOperand::ImmTyNegLo, Operands), + "invalid neg_lo operand"); + return false; + } + if (!validateNeg(Inst, AMDGPU::OpName::neg_hi)) { + Error(getImmLoc(AMDGPUOperand::ImmTyNegHi, Operands), + "invalid neg_hi operand"); + return false; + } if (!validateDPP(Inst, Operands)) { return false; } @@ -5087,20 +5132,6 @@ bool AMDGPUAsmParser::ParseAsAbsoluteExpression(uint32_t &Ret) { return false; } -bool AMDGPUAsmParser::ParseDirectiveMajorMinor(uint32_t &Major, - uint32_t &Minor) { - if (ParseAsAbsoluteExpression(Major)) - return TokError("invalid major version"); - - if (!trySkipToken(AsmToken::Comma)) - return TokError("minor version number required, comma expected"); - - if (ParseAsAbsoluteExpression(Minor)) - return TokError("invalid minor version"); - - return false; -} - bool AMDGPUAsmParser::ParseDirectiveAMDGCNTarget() { if (getSTI().getTargetTriple().getArch() != Triple::amdgcn) return TokError("directive only supported for amdgcn architecture"); @@ -5566,63 +5597,18 @@ bool AMDGPUAsmParser::ParseDirectiveAMDHSAKernel() { } } - getTargetStreamer().EmitAmdhsaKernelDescriptor( - getSTI(), KernelName, KD, NextFreeVGPR, NextFreeSGPR, ReserveVCC, - ReserveFlatScr, AMDGPU::getAmdhsaCodeObjectVersion()); + getTargetStreamer().EmitAmdhsaKernelDescriptor(getSTI(), KernelName, KD, + NextFreeVGPR, NextFreeSGPR, + ReserveVCC, ReserveFlatScr); return false; } -bool AMDGPUAsmParser::ParseDirectiveHSACodeObjectVersion() { - uint32_t Major; - uint32_t Minor; - - if (ParseDirectiveMajorMinor(Major, Minor)) +bool AMDGPUAsmParser::ParseDirectiveAMDHSACodeObjectVersion() { + uint32_t Version; + if (ParseAsAbsoluteExpression(Version)) return true; - getTargetStreamer().EmitDirectiveHSACodeObjectVersion(Major, Minor); - return false; -} - -bool AMDGPUAsmParser::ParseDirectiveHSACodeObjectISA() { - uint32_t Major; - uint32_t Minor; - uint32_t Stepping; - StringRef VendorName; - StringRef ArchName; - - // If this directive has no arguments, then use the ISA version for the - // targeted GPU. - if (isToken(AsmToken::EndOfStatement)) { - AMDGPU::IsaVersion ISA = AMDGPU::getIsaVersion(getSTI().getCPU()); - getTargetStreamer().EmitDirectiveHSACodeObjectISAV2(ISA.Major, ISA.Minor, - ISA.Stepping, - "AMD", "AMDGPU"); - return false; - } - - if (ParseDirectiveMajorMinor(Major, Minor)) - return true; - - if (!trySkipToken(AsmToken::Comma)) - return TokError("stepping version number required, comma expected"); - - if (ParseAsAbsoluteExpression(Stepping)) - return TokError("invalid stepping version"); - - if (!trySkipToken(AsmToken::Comma)) - return TokError("vendor name required, comma expected"); - - if (!parseString(VendorName, "invalid vendor name")) - return true; - - if (!trySkipToken(AsmToken::Comma)) - return TokError("arch name required, comma expected"); - - if (!parseString(ArchName, "invalid arch name")) - return true; - - getTargetStreamer().EmitDirectiveHSACodeObjectISAV2(Major, Minor, Stepping, - VendorName, ArchName); + getTargetStreamer().EmitDirectiveAMDHSACodeObjectVersion(Version); return false; } @@ -5909,16 +5895,13 @@ bool AMDGPUAsmParser::ParseDirective(AsmToken DirectiveID) { if (IDVal == ".amdhsa_kernel") return ParseDirectiveAMDHSAKernel(); + if (IDVal == ".amdhsa_code_object_version") + return ParseDirectiveAMDHSACodeObjectVersion(); + // TODO: Restructure/combine with PAL metadata directive. if (IDVal == AMDGPU::HSAMD::V3::AssemblerDirectiveBegin) return ParseDirectiveHSAMetadata(); } else { - if (IDVal == ".hsa_code_object_version") - return ParseDirectiveHSACodeObjectVersion(); - - if (IDVal == ".hsa_code_object_isa") - return ParseDirectiveHSACodeObjectISA(); - if (IDVal == ".amd_kernel_code_t") return ParseDirectiveAMDKernelCodeT(); @@ -8091,9 +8074,8 @@ void AMDGPUAsmParser::onBeginOfFile() { return; if (!getTargetStreamer().getTargetID()) - getTargetStreamer().initializeTargetID(getSTI(), getSTI().getFeatureString(), - // TODO: Should try to check code object version from directive??? - AMDGPU::getAmdhsaCodeObjectVersion()); + getTargetStreamer().initializeTargetID(getSTI(), + getSTI().getFeatureString()); if (isHsaAbi(getSTI())) getTargetStreamer().EmitDirectiveAMDGCNTarget(); diff --git a/llvm/lib/Target/AMDGPU/BUFInstructions.td b/llvm/lib/Target/AMDGPU/BUFInstructions.td index 9e99d382ed9..ae0955f0cf6 100644 --- a/llvm/lib/Target/AMDGPU/BUFInstructions.td +++ b/llvm/lib/Target/AMDGPU/BUFInstructions.td @@ -485,7 +485,7 @@ class MUBUF_Load_Pseudo pattern=[], // Workaround bug bz30254 int addrKindCopy = addrKind, - RegisterClass vdata_rc = getVregSrcForVT.ret, + RegisterClass vdata_rc = getVregSrcForVT.ret.RegClass, RegisterOperand vdata_op = getLdStVDataRegisterOperand.ret> : MUBUF_Pseudo : MUBUF_Pseudo.ret], isTFE, hasGFX12Enc>.ret, + getMUBUFIns.ret.RegClass], isTFE, hasGFX12Enc>.ret, getMUBUFAsmOps.ret, pattern>, MUBUF_SetupAddr { @@ -780,9 +780,8 @@ class MUBUF_AtomicRet_Pseudo.ret> { - let FPAtomic = isFP in { + ValueType vdataType> { + let FPAtomic = vdataType.isFP in { def _OFFSET : MUBUF_AtomicNoRet_Pseudo , MUBUFAddr64Table <0, NAME>; def _ADDR64 : MUBUF_AtomicNoRet_Pseudo , @@ -804,9 +803,8 @@ multiclass MUBUF_Pseudo_Atomics_NO_RTN .ret> { - let FPAtomic = isFP in { + SDPatternOperator atomic> { + let FPAtomic = vdataType.isFP in { def _OFFSET_RTN : MUBUF_AtomicRet_Pseudo ; +let SubtargetPredicate = isGFX12Plus in { +defm BUFFER_ATOMIC_COND_SUB_U32 : MUBUF_Pseudo_Atomics < + "buffer_atomic_cond_sub_u32", VGPR_32, i32 +>; + +let FPAtomic = 1 in +defm BUFFER_ATOMIC_PK_ADD_BF16 : MUBUF_Pseudo_Atomics < + "buffer_atomic_pk_add_bf16", VGPR_32, v2bf16 +>; +} + //===----------------------------------------------------------------------===// // MTBUF Instructions //===----------------------------------------------------------------------===// @@ -1560,27 +1569,28 @@ multiclass BufferAtomicCmpSwapPat_Common.ret.RegClass; let AddedComplexity = !if(!eq(RtnMode, "ret"), 0, 1) in { defvar OffsetResDag = (!cast(Inst # "_OFFSET" # InstSuffix) - getVregSrcForVT.ret:$vdata_in, SReg_128:$srsrc, SCSrc_b32:$soffset, + data_vt_RC:$vdata_in, SReg_128:$srsrc, SCSrc_b32:$soffset, offset:$offset); def : GCNPat< (vt (Op (MUBUFOffset v4i32:$srsrc, i32:$soffset, i32:$offset), data_vt:$vdata_in)), !if(!eq(RtnMode, "ret"), - (EXTRACT_SUBREG (vt (COPY_TO_REGCLASS OffsetResDag, getVregSrcForVT.ret)), + (EXTRACT_SUBREG (vt (COPY_TO_REGCLASS OffsetResDag, data_vt_RC)), !if(!eq(vt, i32), sub0, sub0_sub1)), OffsetResDag) >; defvar Addr64ResDag = (!cast(Inst # "_ADDR64" # InstSuffix) - getVregSrcForVT.ret:$vdata_in, VReg_64:$vaddr, SReg_128:$srsrc, + data_vt_RC:$vdata_in, VReg_64:$vaddr, SReg_128:$srsrc, SCSrc_b32:$soffset, offset:$offset); def : GCNPat< (vt (Op (MUBUFAddr64 v4i32:$srsrc, i64:$vaddr, i32:$soffset, i32:$offset), data_vt:$vdata_in)), !if(!eq(RtnMode, "ret"), - (EXTRACT_SUBREG (vt (COPY_TO_REGCLASS Addr64ResDag, getVregSrcForVT.ret)), + (EXTRACT_SUBREG (vt (COPY_TO_REGCLASS Addr64ResDag, data_vt_RC)), !if(!eq(vt, i32), sub0, sub0_sub1)), Addr64ResDag) >; @@ -1628,12 +1638,12 @@ multiclass SIBufferAtomicPat_Common(Inst # "_OFFSET" # InstSuffix) getVregSrcForVT.ret:$vdata_in, SReg_128:$rsrc, SCSrc_b32:$soffset, timm:$offset, CachePolicy) @@ -1641,7 +1651,7 @@ multiclass SIBufferAtomicPat_Common(Inst # "_IDXEN" # InstSuffix) getVregSrcForVT.ret:$vdata_in, VGPR_32:$vindex, SReg_128:$rsrc, SCSrc_b32:$soffset, timm:$offset, CachePolicy) @@ -1649,7 +1659,7 @@ multiclass SIBufferAtomicPat_Common(Inst # "_OFFEN" # InstSuffix) getVregSrcForVT.ret:$vdata_in, VGPR_32:$voffset, SReg_128:$rsrc, SCSrc_b32:$soffset, timm:$offset, CachePolicy) @@ -1657,7 +1667,7 @@ multiclass SIBufferAtomicPat_Common(Inst # "_BOTHEN" # InstSuffix) getVregSrcForVT.ret:$vdata_in, (REG_SEQUENCE VReg_64, VGPR_32:$vindex, sub0, VGPR_32:$voffset, sub1), @@ -1703,9 +1713,17 @@ defm : SIBufferAtomicPat<"SIbuffer_atomic_xor", i64, "BUFFER_ATOMIC_XOR_X2">; defm : SIBufferAtomicPat<"SIbuffer_atomic_inc", i64, "BUFFER_ATOMIC_INC_X2">; defm : SIBufferAtomicPat<"SIbuffer_atomic_dec", i64, "BUFFER_ATOMIC_DEC_X2">; -let SubtargetPredicate = HasAtomicCSubNoRtnInsts in +let OtherPredicates = [HasAtomicCSubNoRtnInsts] in defm : SIBufferAtomicPat<"SIbuffer_atomic_csub", i32, "BUFFER_ATOMIC_CSUB", ["noret"]>; +let SubtargetPredicate = isGFX12Plus in { + defm : SIBufferAtomicPat_Common<"SIbuffer_atomic_fadd_bf16", v2bf16, "BUFFER_ATOMIC_PK_ADD_BF16_VBUFFER">; + defm : SIBufferAtomicPat_Common<"SIbuffer_atomic_cond_sub_u32", i32, "BUFFER_ATOMIC_COND_SUB_U32_VBUFFER", ["ret"]>; + + let OtherPredicates = [HasAtomicCSubNoRtnInsts] in + defm : SIBufferAtomicPat_Common<"SIbuffer_atomic_cond_sub_u32", i32, "BUFFER_ATOMIC_COND_SUB_U32_VBUFFER", ["noret"]>; +} + let SubtargetPredicate = isGFX6GFX7GFX10Plus in { defm : SIBufferAtomicPat<"SIbuffer_atomic_fmin", f32, "BUFFER_ATOMIC_FMIN">; defm : SIBufferAtomicPat<"SIbuffer_atomic_fmax", f32, "BUFFER_ATOMIC_FMAX">; @@ -1726,35 +1744,35 @@ multiclass BufferAtomicPatterns_NO_RTN_Common vt:$vdata_in, v4i32:$rsrc, 0, 0, (BUFSOffset i32:$soffset), timm:$offset, - timm:$cachepolicy, 0), + timm:$auxiliary, 0), (!cast(opcode # _OFFSET) getVregSrcForVT.ret:$vdata_in, SReg_128:$rsrc, SCSrc_b32:$soffset, - timm:$offset, timm:$cachepolicy) + timm:$offset, (extract_cpol $auxiliary)) >; def : GCNPat< (NoUseBufferAtomic vt:$vdata_in, v4i32:$rsrc, i32:$vindex, 0, (BUFSOffset i32:$soffset), timm:$offset, - timm:$cachepolicy, timm), + timm:$auxiliary, timm), (!cast(opcode # _IDXEN) getVregSrcForVT.ret:$vdata_in, VGPR_32:$vindex, SReg_128:$rsrc, SCSrc_b32:$soffset, - timm:$offset, timm:$cachepolicy) + timm:$offset, (extract_cpol $auxiliary)) >; def : GCNPat< (NoUseBufferAtomic vt:$vdata_in, v4i32:$rsrc, 0, i32:$voffset, (BUFSOffset i32:$soffset), timm:$offset, - timm:$cachepolicy, 0), + timm:$auxiliary, 0), (!cast(opcode # _OFFEN) getVregSrcForVT.ret:$vdata_in, VGPR_32:$voffset, SReg_128:$rsrc, SCSrc_b32:$soffset, - timm:$offset, timm:$cachepolicy) + timm:$offset, (extract_cpol $auxiliary)) >; def : GCNPat< (NoUseBufferAtomic vt:$vdata_in, v4i32:$rsrc, i32:$vindex, i32:$voffset, (BUFSOffset i32:$soffset), timm:$offset, - timm:$cachepolicy, timm), + timm:$auxiliary, timm), (!cast(opcode # _BOTHEN) getVregSrcForVT.ret:$vdata_in, (REG_SEQUENCE VReg_64, VGPR_32:$vindex, sub0, VGPR_32:$voffset, sub1), - SReg_128:$rsrc, SCSrc_b32:$soffset, timm:$offset, timm:$cachepolicy) + SReg_128:$rsrc, SCSrc_b32:$soffset, timm:$offset, (extract_cpol $auxiliary)) >; } @@ -1770,14 +1788,22 @@ let OtherPredicates = [HasAtomicFaddNoRtnInsts] in defm : SIBufferAtomicPat<"SIbuffer_atomic_fadd", f32, "BUFFER_ATOMIC_ADD_F32", ["noret"]>; let OtherPredicates = [HasAtomicBufferGlobalPkAddF16NoRtnInsts] in { + let SubtargetPredicate = isGFX9Only in defm : SIBufferAtomicPat_Common<"SIbuffer_atomic_fadd", v2f16, "BUFFER_ATOMIC_PK_ADD_F16", ["noret"]>; + + let SubtargetPredicate = isGFX12Plus in + defm : SIBufferAtomicPat_Common<"SIbuffer_atomic_fadd", v2f16, "BUFFER_ATOMIC_PK_ADD_F16_VBUFFER", ["noret"]>; } // End OtherPredicates = [HasAtomicBufferGlobalPkAddF16NoRtnInsts] let OtherPredicates = [HasAtomicFaddRtnInsts] in defm : SIBufferAtomicPat<"SIbuffer_atomic_fadd", f32, "BUFFER_ATOMIC_ADD_F32", ["ret"]>; let OtherPredicates = [HasAtomicBufferGlobalPkAddF16Insts] in { + let SubtargetPredicate = isGFX9Only in defm : SIBufferAtomicPat_Common<"SIbuffer_atomic_fadd", v2f16, "BUFFER_ATOMIC_PK_ADD_F16", ["ret"]>; + + let SubtargetPredicate = isGFX12Plus in + defm : SIBufferAtomicPat_Common<"SIbuffer_atomic_fadd", v2f16, "BUFFER_ATOMIC_PK_ADD_F16_VBUFFER", ["ret"]>; } // End OtherPredicates = [HasAtomicBufferGlobalPkAddF16Insts] let OtherPredicates = [isGFX90APlus] in { @@ -1791,10 +1817,11 @@ multiclass SIBufferAtomicCmpSwapPat_Common(SIbuffer_atomic_cmpswap # !if(!eq(RtnMode, "ret"), "", "_noret")); defvar InstSuffix = !if(!eq(RtnMode, "ret"), "_RTN", ""); - defvar CachePolicy = !if(!eq(RtnMode, "ret"), (set_glc $cachepolicy), - (timm:$cachepolicy)); + defvar CachePolicy = !if(!eq(RtnMode, "ret"), + (extract_cpol_set_glc $auxiliary), + (extract_cpol $auxiliary)); defvar SrcRC = getVregSrcForVT.ret; - defvar DataRC = getVregSrcForVT.ret; + defvar DataRC = getVregSrcForVT.ret.RegClass; defvar SubLo = !if(!eq(vt, i32), sub0, sub0_sub1); defvar SubHi = !if(!eq(vt, i32), sub1, sub2_sub3); @@ -1804,7 +1831,7 @@ multiclass SIBufferAtomicCmpSwapPat_Common; defm BUFFER_ATOMIC_CMPSWAP_X2 : MUBUF_Real_Atomic_gfx11_gfx12_Renamed<0x042, "buffer_atomic_cmpswap_b64">; defm BUFFER_ATOMIC_FCMPSWAP : MUBUF_Real_Atomic_gfx11_Renamed<0x050, "buffer_atomic_cmpswap_f32">; +defm BUFFER_ATOMIC_COND_SUB_U32 : MUBUF_Real_Atomic_gfx12<0x050>; defm BUFFER_ATOMIC_CSUB : MUBUF_Real_Atomic_gfx11_gfx12_Renamed_gfx12_Renamed<0x037, "buffer_atomic_sub_clamp_u32", "buffer_atomic_csub_u32">; def : Mnem_gfx11_gfx12<"buffer_atomic_csub", "buffer_atomic_csub_u32">; defm BUFFER_ATOMIC_DEC : MUBUF_Real_Atomic_gfx11_gfx12_Renamed<0x040, "buffer_atomic_dec_u32">; @@ -2632,6 +2660,8 @@ defm BUFFER_ATOMIC_SWAP : MUBUF_Real_Atomic_gfx11_gfx12_Renamed<0x033, defm BUFFER_ATOMIC_SWAP_X2 : MUBUF_Real_Atomic_gfx11_gfx12_Renamed<0x041, "buffer_atomic_swap_b64">; defm BUFFER_ATOMIC_XOR : MUBUF_Real_Atomic_gfx11_gfx12_Renamed<0x03E, "buffer_atomic_xor_b32">; defm BUFFER_ATOMIC_XOR_X2 : MUBUF_Real_Atomic_gfx11_gfx12_Renamed<0x04B, "buffer_atomic_xor_b64">; +defm BUFFER_ATOMIC_PK_ADD_F16 : MUBUF_Real_Atomic_gfx12<0x059>; +defm BUFFER_ATOMIC_PK_ADD_BF16 : MUBUF_Real_Atomic_gfx12<0x05a>; //===----------------------------------------------------------------------===// // MUBUF - GFX10. diff --git a/llvm/lib/Target/AMDGPU/DSInstructions.td b/llvm/lib/Target/AMDGPU/DSInstructions.td index 3cccd8c50e6..d09e1ef3bcb 100644 --- a/llvm/lib/Target/AMDGPU/DSInstructions.td +++ b/llvm/lib/Target/AMDGPU/DSInstructions.td @@ -437,6 +437,12 @@ class DS_1A1D_PERMUTE : GCNPat <(frag (DS1Addr1Offset i32:$ptr, i32:$offset), vt:$value), + (inst $ptr, getVregSrcForVT.ret:$value, offset:$offset, (i1 gds))> { + let AddedComplexity = complexity; +} + defm DS_ADD_U32 : DS_1A1D_NORET_mc<"ds_add_u32">; defm DS_SUB_U32 : DS_1A1D_NORET_mc<"ds_sub_u32">; defm DS_RSUB_U32 : DS_1A1D_NORET_mc<"ds_rsub_u32">; @@ -486,10 +492,10 @@ let SubtargetPredicate = isGFX90APlus in { } // End SubtargetPredicate = isGFX90APlus let SubtargetPredicate = HasAtomicDsPkAdd16Insts in { - defm DS_PK_ADD_F16 : DS_1A1D_NORET_mc_gfx9<"ds_pk_add_f16">; - defm DS_PK_ADD_RTN_F16 : DS_1A1D_RET_mc_gfx9<"ds_pk_add_rtn_f16", VGPR_32, "ds_pk_add_f16">; - defm DS_PK_ADD_BF16 : DS_1A1D_NORET_mc_gfx9<"ds_pk_add_bf16">; - defm DS_PK_ADD_RTN_BF16 : DS_1A1D_RET_mc_gfx9<"ds_pk_add_rtn_bf16", VGPR_32, "ds_pk_add_bf16">; + defm DS_PK_ADD_F16 : DS_1A1D_NORET_mc<"ds_pk_add_f16">; + defm DS_PK_ADD_RTN_F16 : DS_1A1D_RET_mc<"ds_pk_add_rtn_f16", VGPR_32, "ds_pk_add_f16">; + defm DS_PK_ADD_BF16 : DS_1A1D_NORET_mc<"ds_pk_add_bf16">; + defm DS_PK_ADD_RTN_BF16 : DS_1A1D_RET_mc<"ds_pk_add_rtn_bf16", VGPR_32, "ds_pk_add_bf16">; } // End SubtargetPredicate = HasAtomicDsPkAdd16Insts defm DS_CMPSTORE_B32 : DS_1A2D_NORET_mc<"ds_cmpstore_b32">; @@ -732,9 +738,22 @@ def DS_BVH_STACK_RTN_B32 : DS_BVH_STACK<"ds_bvh_stack_rtn_b32">; let SubtargetPredicate = isGFX12Plus in { +defm DS_COND_SUB_U32 : DS_1A1D_NORET_mc<"ds_cond_sub_u32">; +defm DS_COND_SUB_RTN_U32 : DS_1A1D_RET_mc<"ds_cond_sub_rtn_u32", VGPR_32, "ds_cond_sub_u32">; defm DS_SUB_CLAMP_U32 : DS_1A1D_NORET_mc<"ds_sub_clamp_u32">; defm DS_SUB_CLAMP_RTN_U32 : DS_1A1D_RET_mc<"ds_sub_clamp_rtn_u32", VGPR_32, "ds_sub_clamp_u32">; +multiclass DSAtomicRetNoRetPatIntrinsic_mc { + def : DSAtomicRetPat(frag#"_local_addrspace")>; + + let OtherPredicates = [HasAtomicCSubNoRtnInsts] in + def : DSAtomicRetPat(frag#"_noret_local_addrspace"), /* complexity */ 1>; +} + +defm : DSAtomicRetNoRetPatIntrinsic_mc; } // let SubtargetPredicate = isGFX12Plus //===----------------------------------------------------------------------===// @@ -954,12 +973,6 @@ defm : DSWritePat_mc ; } // End AddedComplexity = 100 -class DSAtomicRetPat : GCNPat <(frag (DS1Addr1Offset i32:$ptr, i32:$offset), vt:$value), - (inst $ptr, getVregSrcForVT.ret:$value, offset:$offset, (i1 gds))> { - let AddedComplexity = complexity; -} - multiclass DSAtomicRetPat_mc { let OtherPredicates = [LDSRequiresM0Init] in { def : DSAtomicRetPat(frag#"_local_m0_"#vt.Size)>; @@ -1237,8 +1250,14 @@ defm DS_MIN_NUM_F64 : DS_Real_Renamed_gfx12<0x052, DS_MIN_F64, "ds_min_num defm DS_MAX_NUM_F64 : DS_Real_Renamed_gfx12<0x053, DS_MAX_F64, "ds_max_num_f64">; defm DS_MIN_NUM_RTN_F64 : DS_Real_Renamed_gfx12<0x072, DS_MIN_RTN_F64, "ds_min_num_rtn_f64">; defm DS_MAX_NUM_RTN_F64 : DS_Real_Renamed_gfx12<0x073, DS_MAX_RTN_F64, "ds_max_num_rtn_f64">; +defm DS_COND_SUB_U32 : DS_Real_gfx12<0x098>; defm DS_SUB_CLAMP_U32 : DS_Real_gfx12<0x099>; +defm DS_COND_SUB_RTN_U32 : DS_Real_gfx12<0x0a8>; defm DS_SUB_CLAMP_RTN_U32 : DS_Real_gfx12<0x0a9>; +defm DS_PK_ADD_F16 : DS_Real_gfx12<0x09a>; +defm DS_PK_ADD_RTN_F16 : DS_Real_gfx12<0x0aa>; +defm DS_PK_ADD_BF16 : DS_Real_gfx12<0x09b>; +defm DS_PK_ADD_RTN_BF16 : DS_Real_gfx12<0x0ab>; //===----------------------------------------------------------------------===// // GFX11. @@ -1248,7 +1267,7 @@ let AssemblerPredicate = isGFX11Only, DecoderNamespace = "GFX11" in { multiclass DS_Real_gfx11 op> { def _gfx11 : Base_DS_Real_gfx6_gfx7_gfx10_gfx11_gfx12(NAME), - SIEncodingFamily.GFX11>; + SIEncodingFamily.GFX11>; } multiclass DS_Real_Renamed_gfx11 op, DS_Pseudo backing_pseudo, string real_name> { diff --git a/llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp b/llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp index 9dff3f6c2ef..86096b0d80b 100644 --- a/llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp +++ b/llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp @@ -544,6 +544,10 @@ DecodeStatus AMDGPUDisassembler::getInstruction(MCInst &MI, uint64_t &Size, Res = tryDecodeInst(DecoderTableGFX1296, MI, DecW, Address, CS); if (Res) break; + + Res = tryDecodeInst(DecoderTableGFX12W6496, MI, DecW, Address, CS); + if (Res) + break; } // Reinitialize Bytes Bytes = Bytes_.slice(0, MaxInstBytesNum); @@ -2180,7 +2184,8 @@ AMDGPUDisassembler::decodeKernelDescriptorDirective( KERNEL_CODE_PROPERTY_ENABLE_WAVEFRONT_SIZE32); } - if (AMDGPU::getAmdhsaCodeObjectVersion() >= AMDGPU::AMDHSA_COV5) + // FIXME: We should be looking at the ELF header ABI version for this. + if (AMDGPU::getDefaultAMDHSACodeObjectVersion() >= AMDGPU::AMDHSA_COV5) PRINT_DIRECTIVE(".amdhsa_uses_dynamic_stack", KERNEL_CODE_PROPERTY_USES_DYNAMIC_STACK); diff --git a/llvm/lib/Target/AMDGPU/FLATInstructions.td b/llvm/lib/Target/AMDGPU/FLATInstructions.td index 16a8b770e05..cb830b128df 100644 --- a/llvm/lib/Target/AMDGPU/FLATInstructions.td +++ b/llvm/lib/Target/AMDGPU/FLATInstructions.td @@ -535,7 +535,6 @@ multiclass FLAT_Atomic_Pseudo_NO_RTN< ValueType vt, ValueType data_vt = vt, RegisterClass data_rc = vdst_rc, - bit isFP = isFloatType.ret, RegisterOperand data_op = getLdStRegisterOperand.ret> { def "" : FLAT_AtomicNoRet_Pseudo , AtomicNoRet { let PseudoInstr = NAME; - let FPAtomic = isFP; + let FPAtomic = data_vt.isFP; let AddedComplexity = -1; // Prefer global atomics if available } } @@ -555,7 +554,6 @@ multiclass FLAT_Atomic_Pseudo_RTN< ValueType vt, ValueType data_vt = vt, RegisterClass data_rc = vdst_rc, - bit isFP = isFloatType.ret, RegisterOperand data_op = getLdStRegisterOperand.ret> { def _RTN : FLAT_AtomicRet_Pseudo .ret:$vdst), @@ -563,7 +561,7 @@ multiclass FLAT_Atomic_Pseudo_RTN< " $vdst, $vaddr, $vdata$offset$cpol">, GlobalSaddrTable<0, opName#"_rtn">, AtomicNoRet { - let FPAtomic = isFP; + let FPAtomic = data_vt.isFP; let AddedComplexity = -1; // Prefer global atomics if available } } @@ -574,10 +572,9 @@ multiclass FLAT_Atomic_Pseudo< ValueType vt, ValueType data_vt = vt, RegisterClass data_rc = vdst_rc, - bit isFP = isFloatType.ret, RegisterOperand data_op = getLdStRegisterOperand.ret> { - defm "" : FLAT_Atomic_Pseudo_NO_RTN; - defm "" : FLAT_Atomic_Pseudo_RTN; + defm "" : FLAT_Atomic_Pseudo_NO_RTN; + defm "" : FLAT_Atomic_Pseudo_RTN; } multiclass FLAT_Global_Atomic_Pseudo_NO_RTN< @@ -586,7 +583,6 @@ multiclass FLAT_Global_Atomic_Pseudo_NO_RTN< ValueType vt, ValueType data_vt = vt, RegisterClass data_rc = vdst_rc, - bit isFP = isFloatType.ret, RegisterOperand data_op = getLdStRegisterOperand.ret> { def "" : FLAT_AtomicNoRet_Pseudo { let has_saddr = 1; let PseudoInstr = NAME; - let FPAtomic = isFP; + let FPAtomic = data_vt.isFP; } def _SADDR : FLAT_AtomicNoRet_Pseudo .ret, RegisterOperand data_op = getLdStRegisterOperand.ret, RegisterOperand vdst_op = getLdStRegisterOperand.ret> { @@ -630,7 +625,7 @@ multiclass FLAT_Global_Atomic_Pseudo_RTN< GlobalSaddrTable<0, opName#"_rtn">, AtomicNoRet { let has_saddr = 1; - let FPAtomic = isFP; + let FPAtomic = data_vt.isFP; } def _SADDR_RTN : FLAT_AtomicRet_Pseudo ; + defm FLAT_ATOMIC_COND_SUB_U32 : FLAT_Atomic_Pseudo <"flat_atomic_cond_sub_u32", VGPR_32, i32>; } // End SubtargetPredicate = isGFX12Plus defm GLOBAL_LOAD_UBYTE : FLAT_Global_Load_Pseudo <"global_load_ubyte", VGPR_32>; @@ -949,6 +945,7 @@ defm GLOBAL_LOAD_LDS_SSHORT : FLAT_Global_Load_LDS_Pseudo <"global_load_lds_ssho defm GLOBAL_LOAD_LDS_DWORD : FLAT_Global_Load_LDS_Pseudo <"global_load_lds_dword">; let SubtargetPredicate = isGFX12Plus in { + defm GLOBAL_ATOMIC_COND_SUB_U32 : FLAT_Global_Atomic_Pseudo <"global_atomic_cond_sub_u32", VGPR_32, i32>; defm GLOBAL_ATOMIC_ORDERED_ADD_B64 : FLAT_Global_Atomic_Pseudo <"global_atomic_ordered_add_b64", VReg_64, i64>; def GLOBAL_INV : FLAT_Global_Invalidate_Writeback<"global_inv">; @@ -995,6 +992,17 @@ defm SCRATCH_LOAD_LDS_DWORD : FLAT_Scratch_Load_LDS_Pseudo <"scratch_load_lds_d } // End SubtargetPredicate = HasFlatScratchInsts +let SubtargetPredicate = isGFX12Plus in { + let WaveSizePredicate = isWave32 in { + defm GLOBAL_LOAD_TR_B128_w32 : FLAT_Global_Load_Pseudo <"global_load_tr_b128_w32", VReg_128>; + defm GLOBAL_LOAD_TR_B64_w32 : FLAT_Global_Load_Pseudo <"global_load_tr_b64_w32", VReg_64>; + } + let WaveSizePredicate = isWave64 in { + defm GLOBAL_LOAD_TR_B128_w64 : FLAT_Global_Load_Pseudo <"global_load_tr_b128_w64", VReg_64>; + defm GLOBAL_LOAD_TR_B64_w64 : FLAT_Global_Load_Pseudo <"global_load_tr_b64_w64", VGPR_32>; + } +} // End SubtargetPredicate = isGFX12Plus + let SubtargetPredicate = isGFX10Plus, is_flat_global = 1 in { defm GLOBAL_ATOMIC_FCMPSWAP : FLAT_Global_Atomic_Pseudo<"global_atomic_fcmpswap", VGPR_32, f32, v2f32, VReg_64>; @@ -1100,23 +1108,43 @@ class FlatStoreSignedAtomicPat .ret:$data, $offset) >; -multiclass FlatAtomicNoRtnPat { - defvar noRtnNode = !cast(node # "_noret" # !if(isIntr, "", "_"#vt.Size)); +multiclass FlatAtomicNoRtnPatBase { + + defvar noRtnNode = !cast(node); let AddedComplexity = 1 in def : GCNPat <(vt (noRtnNode (FlatOffset i64:$vaddr, i32:$offset), data_vt:$data)), (!cast(inst) VReg_64:$vaddr, getVregSrcForVT.ret:$data, $offset)>; } -multiclass FlatAtomicRtnPat { - defvar rtnNode = !cast(node # !if(isIntr, "", "_"#vt.Size)); +multiclass FlatAtomicNoRtnPatWithAddrSpace : + FlatAtomicNoRtnPatBase; + +multiclass FlatAtomicNoRtnPat : + FlatAtomicNoRtnPatBase; + + +multiclass FlatAtomicRtnPatBase { + + defvar rtnNode = !cast(node); def : GCNPat <(vt (rtnNode (FlatOffset i64:$vaddr, i32:$offset), data_vt:$data)), (!cast(inst#"_RTN") VReg_64:$vaddr, getVregSrcForVT.ret:$data, $offset)>; } +multiclass FlatAtomicRtnPatWithAddrSpace : + FlatAtomicRtnPatBase; + +multiclass FlatAtomicRtnPat : + FlatAtomicRtnPatBase; + + multiclass FlatAtomicPat : FlatAtomicRtnPat, @@ -1296,6 +1324,13 @@ defm : FlatAtomicPat <"FLAT_ATOMIC_CMPSWAP_X2", "AMDGPUatomic_cmp_swap_"#as, i64 defm : FlatAtomicPat <"FLAT_ATOMIC_XOR_X2", "atomic_load_xor_"#as, i64>; } // end foreach as +let SubtargetPredicate = isGFX12Plus in { + defm : FlatAtomicRtnPatWithAddrSpace<"FLAT_ATOMIC_COND_SUB_U32", "int_amdgcn_atomic_cond_sub_u32", "flat_addrspace", i32 >; + + let OtherPredicates = [HasAtomicCSubNoRtnInsts] in + defm : FlatAtomicNoRtnPatWithAddrSpace<"FLAT_ATOMIC_COND_SUB_U32", "int_amdgcn_atomic_cond_sub_u32", "flat_addrspace", i32>; +} + def : FlatStorePat ; def : FlatStorePat ; @@ -1557,8 +1592,28 @@ defm : GlobalFLATAtomicPats <"GLOBAL_ATOMIC_SWAP_X2", "atomic_swap_global", i64> defm : GlobalFLATAtomicPats <"GLOBAL_ATOMIC_CMPSWAP_X2", "AMDGPUatomic_cmp_swap_global", i64, v2i64>; defm : GlobalFLATAtomicPats <"GLOBAL_ATOMIC_XOR_X2", "atomic_load_xor_global", i64>; +let SubtargetPredicate = isGFX12Plus in { + defm : GlobalFLATAtomicPatsRtnWithAddrSpace <"GLOBAL_ATOMIC_COND_SUB_U32", "int_amdgcn_atomic_cond_sub_u32", "global_addrspace", i32>; + + let OtherPredicates = [HasAtomicCSubNoRtnInsts] in + defm : GlobalFLATAtomicPatsNoRtnWithAddrSpace <"GLOBAL_ATOMIC_COND_SUB_U32", "int_amdgcn_atomic_cond_sub_u32", "global_addrspace", i32>; +} + let OtherPredicates = [isGFX12Plus] in { defm : GlobalFLATAtomicPatsRtn <"GLOBAL_ATOMIC_ORDERED_ADD_B64", "int_amdgcn_global_atomic_ordered_add_b64", i64, i64, /* isIntr */ 1>; + + let WaveSizePredicate = isWave32 in { + defm : GlobalFLATLoadPats ; + defm : GlobalFLATLoadPats ; + defm : GlobalFLATLoadPats ; + defm : GlobalFLATLoadPats ; + } + let WaveSizePredicate = isWave64 in { + defm : GlobalFLATLoadPats ; + defm : GlobalFLATLoadPats ; + defm : GlobalFLATLoadPats ; + defm : GlobalFLATLoadPats ; + } } let OtherPredicates = [isGFX10Plus] in { @@ -2523,7 +2578,8 @@ multiclass VFLAT_Aliases_gfx12, Requires<[isGFX12Plus]>; } -multiclass VFLAT_Real_Base_gfx12 op, string ps, string opName, int renamed = false, string alias = ""> : +multiclass VFLAT_Real_Base_gfx12 op, string ps = NAME, string opName = !tolower(NAME), + int renamed = false, string alias = ""> : VFLAT_Aliases_gfx12 { def _gfx12 : VFLAT_Real_gfx12(ps), opName> { let Inst{6-0} = !cast(SGPR_NULL_gfx11plus.HWEncoding); @@ -2557,20 +2613,24 @@ multiclass VFLAT_Real_SVS_gfx12 op, string ps, string opName> { } } -multiclass VFLAT_Real_Atomics_gfx12 op, string ps, string opName, int renamed = false, string alias = ""> : +multiclass VFLAT_Real_Atomics_gfx12 op, string ps = NAME, string opName = !tolower(NAME), + int renamed = false, string alias = ""> : VFLAT_Real_Base_gfx12, VFLAT_Real_RTN_gfx12; -multiclass VGLOBAL_Real_AllAddr_gfx12 op, string ps, string opName, int renamed = false, string alias = ""> : +multiclass VGLOBAL_Real_AllAddr_gfx12 op, string ps = NAME, string opName = !tolower(NAME), + int renamed = false, string alias = ""> : VFLAT_Real_Base_gfx12, VFLAT_Real_SADDR_gfx12; -multiclass VGLOBAL_Real_Atomics_gfx12 op, string ps, string opName, int renamed = false, string alias = ""> : +multiclass VGLOBAL_Real_Atomics_gfx12 op, string ps = NAME, string opName = !tolower(NAME), + int renamed = false, string alias = ""> : VGLOBAL_Real_AllAddr_gfx12, VFLAT_Real_RTN_gfx12, VFLAT_Real_SADDR_RTN_gfx12; -multiclass VSCRATCH_Real_AllAddr_gfx12 op, string ps, string opName, int renamed = false> : +multiclass VSCRATCH_Real_AllAddr_gfx12 op, string ps = NAME, string opName = !tolower(NAME), + int renamed = false> : VFLAT_Real_Base_gfx12, VFLAT_Real_SADDR_gfx12, VFLAT_Real_ST_gfx12, @@ -2591,14 +2651,14 @@ defm FLAT_STORE_B32 : VFLAT_Real_Base_gfx12<0x01a, "FLAT_STORE_DW defm FLAT_STORE_B64 : VFLAT_Real_Base_gfx12<0x01b, "FLAT_STORE_DWORDX2", "flat_store_b64", true>; defm FLAT_STORE_B96 : VFLAT_Real_Base_gfx12<0x01c, "FLAT_STORE_DWORDX3", "flat_store_b96", true>; defm FLAT_STORE_B128 : VFLAT_Real_Base_gfx12<0x01d, "FLAT_STORE_DWORDX4", "flat_store_b128", true>; -defm FLAT_LOAD_D16_U8 : VFLAT_Real_Base_gfx12<0x01e, "FLAT_LOAD_UBYTE_D16", "flat_load_d16_u8">; -defm FLAT_LOAD_D16_I8 : VFLAT_Real_Base_gfx12<0x01f, "FLAT_LOAD_SBYTE_D16", "flat_load_d16_i8">; -defm FLAT_LOAD_D16_B16 : VFLAT_Real_Base_gfx12<0x020, "FLAT_LOAD_SHORT_D16", "flat_load_d16_b16">; -defm FLAT_LOAD_D16_HI_U8 : VFLAT_Real_Base_gfx12<0x021, "FLAT_LOAD_UBYTE_D16_HI", "flat_load_d16_hi_u8">; -defm FLAT_LOAD_D16_HI_I8 : VFLAT_Real_Base_gfx12<0x022, "FLAT_LOAD_SBYTE_D16_HI", "flat_load_d16_hi_i8">; -defm FLAT_LOAD_D16_HI_B16 : VFLAT_Real_Base_gfx12<0x023, "FLAT_LOAD_SHORT_D16_HI", "flat_load_d16_hi_b16">; -defm FLAT_STORE_D16_HI_B8 : VFLAT_Real_Base_gfx12<0x024, "FLAT_STORE_BYTE_D16_HI", "flat_store_d16_hi_b8">; -defm FLAT_STORE_D16_HI_B16 : VFLAT_Real_Base_gfx12<0x025, "FLAT_STORE_SHORT_D16_HI", "flat_store_d16_hi_b16">; +defm FLAT_LOAD_D16_U8 : VFLAT_Real_Base_gfx12<0x01e, "FLAT_LOAD_UBYTE_D16">; +defm FLAT_LOAD_D16_I8 : VFLAT_Real_Base_gfx12<0x01f, "FLAT_LOAD_SBYTE_D16">; +defm FLAT_LOAD_D16_B16 : VFLAT_Real_Base_gfx12<0x020, "FLAT_LOAD_SHORT_D16">; +defm FLAT_LOAD_D16_HI_U8 : VFLAT_Real_Base_gfx12<0x021, "FLAT_LOAD_UBYTE_D16_HI">; +defm FLAT_LOAD_D16_HI_I8 : VFLAT_Real_Base_gfx12<0x022, "FLAT_LOAD_SBYTE_D16_HI">; +defm FLAT_LOAD_D16_HI_B16 : VFLAT_Real_Base_gfx12<0x023, "FLAT_LOAD_SHORT_D16_HI">; +defm FLAT_STORE_D16_HI_B8 : VFLAT_Real_Base_gfx12<0x024, "FLAT_STORE_BYTE_D16_HI">; +defm FLAT_STORE_D16_HI_B16 : VFLAT_Real_Base_gfx12<0x025, "FLAT_STORE_SHORT_D16_HI">; defm FLAT_ATOMIC_SWAP_B32 : VFLAT_Real_Atomics_gfx12<0x033, "FLAT_ATOMIC_SWAP", "flat_atomic_swap_b32", true>; defm FLAT_ATOMIC_CMPSWAP_B32 : VFLAT_Real_Atomics_gfx12<0x034, "FLAT_ATOMIC_CMPSWAP", "flat_atomic_cmpswap_b32", true>; defm FLAT_ATOMIC_ADD_U32 : VFLAT_Real_Atomics_gfx12<0x035, "FLAT_ATOMIC_ADD", "flat_atomic_add_u32", true>; @@ -2626,9 +2686,12 @@ defm FLAT_ATOMIC_OR_B64 : VFLAT_Real_Atomics_gfx12<0x04a, "FLAT_ATOMI defm FLAT_ATOMIC_XOR_B64 : VFLAT_Real_Atomics_gfx12<0x04b, "FLAT_ATOMIC_XOR_X2", "flat_atomic_xor_b64", true>; defm FLAT_ATOMIC_INC_U64 : VFLAT_Real_Atomics_gfx12<0x04c, "FLAT_ATOMIC_INC_X2", "flat_atomic_inc_u64", true>; defm FLAT_ATOMIC_DEC_U64 : VFLAT_Real_Atomics_gfx12<0x04d, "FLAT_ATOMIC_DEC_X2", "flat_atomic_dec_u64", true>; +defm FLAT_ATOMIC_COND_SUB_U32 : VFLAT_Real_Atomics_gfx12<0x050, "FLAT_ATOMIC_COND_SUB_U32", "flat_atomic_cond_sub_u32">; defm FLAT_ATOMIC_MIN_NUM_F32 : VFLAT_Real_Atomics_gfx12<0x051, "FLAT_ATOMIC_FMIN", "flat_atomic_min_num_f32", true, "flat_atomic_min_f32">; defm FLAT_ATOMIC_MAX_NUM_F32 : VFLAT_Real_Atomics_gfx12<0x052, "FLAT_ATOMIC_FMAX", "flat_atomic_max_num_f32", true, "flat_atomic_max_f32">; -defm FLAT_ATOMIC_ADD_F32 : VFLAT_Real_Atomics_gfx12<0x056, "FLAT_ATOMIC_ADD_F32", "flat_atomic_add_f32">; +defm FLAT_ATOMIC_ADD_F32 : VFLAT_Real_Atomics_gfx12<0x056>; +defm FLAT_ATOMIC_PK_ADD_F16 : VFLAT_Real_Atomics_gfx12<0x059>; +defm FLAT_ATOMIC_PK_ADD_BF16 : VFLAT_Real_Atomics_gfx12<0x05a>; // ENC_VGLOBAL. defm GLOBAL_LOAD_U8 : VGLOBAL_Real_AllAddr_gfx12<0x010, "GLOBAL_LOAD_UBYTE", "global_load_u8", true>; @@ -2645,16 +2708,16 @@ defm GLOBAL_STORE_B32 : VGLOBAL_Real_AllAddr_gfx12<0x01a, "GLOBAL_S defm GLOBAL_STORE_B64 : VGLOBAL_Real_AllAddr_gfx12<0x01b, "GLOBAL_STORE_DWORDX2", "global_store_b64", true>; defm GLOBAL_STORE_B96 : VGLOBAL_Real_AllAddr_gfx12<0x01c, "GLOBAL_STORE_DWORDX3", "global_store_b96", true>; defm GLOBAL_STORE_B128 : VGLOBAL_Real_AllAddr_gfx12<0x01d, "GLOBAL_STORE_DWORDX4", "global_store_b128", true>; -defm GLOBAL_LOAD_D16_U8 : VGLOBAL_Real_AllAddr_gfx12<0x01e, "GLOBAL_LOAD_UBYTE_D16", "global_load_d16_u8">; -defm GLOBAL_LOAD_D16_I8 : VGLOBAL_Real_AllAddr_gfx12<0x01f, "GLOBAL_LOAD_SBYTE_D16", "global_load_d16_i8">; -defm GLOBAL_LOAD_D16_B16 : VGLOBAL_Real_AllAddr_gfx12<0x020, "GLOBAL_LOAD_SHORT_D16", "global_load_d16_b16">; -defm GLOBAL_LOAD_D16_HI_U8 : VGLOBAL_Real_AllAddr_gfx12<0x021, "GLOBAL_LOAD_UBYTE_D16_HI", "global_load_d16_hi_u8">; -defm GLOBAL_LOAD_D16_HI_I8 : VGLOBAL_Real_AllAddr_gfx12<0x022, "GLOBAL_LOAD_SBYTE_D16_HI", "global_load_d16_hi_i8">; -defm GLOBAL_LOAD_D16_HI_B16 : VGLOBAL_Real_AllAddr_gfx12<0x023, "GLOBAL_LOAD_SHORT_D16_HI", "global_load_d16_hi_b16">; -defm GLOBAL_STORE_D16_HI_B8 : VGLOBAL_Real_AllAddr_gfx12<0x024, "GLOBAL_STORE_BYTE_D16_HI", "global_store_d16_hi_b8">; -defm GLOBAL_STORE_D16_HI_B16 : VGLOBAL_Real_AllAddr_gfx12<0x025, "GLOBAL_STORE_SHORT_D16_HI", "global_store_d16_hi_b16">; -defm GLOBAL_LOAD_ADDTID_B32 : VGLOBAL_Real_AllAddr_gfx12<0x028, "GLOBAL_LOAD_DWORD_ADDTID", "global_load_addtid_b32">; -defm GLOBAL_STORE_ADDTID_B32 : VGLOBAL_Real_AllAddr_gfx12<0x029, "GLOBAL_STORE_DWORD_ADDTID", "global_store_addtid_b32">; +defm GLOBAL_LOAD_D16_U8 : VGLOBAL_Real_AllAddr_gfx12<0x01e, "GLOBAL_LOAD_UBYTE_D16">; +defm GLOBAL_LOAD_D16_I8 : VGLOBAL_Real_AllAddr_gfx12<0x01f, "GLOBAL_LOAD_SBYTE_D16">; +defm GLOBAL_LOAD_D16_B16 : VGLOBAL_Real_AllAddr_gfx12<0x020, "GLOBAL_LOAD_SHORT_D16">; +defm GLOBAL_LOAD_D16_HI_U8 : VGLOBAL_Real_AllAddr_gfx12<0x021, "GLOBAL_LOAD_UBYTE_D16_HI">; +defm GLOBAL_LOAD_D16_HI_I8 : VGLOBAL_Real_AllAddr_gfx12<0x022, "GLOBAL_LOAD_SBYTE_D16_HI">; +defm GLOBAL_LOAD_D16_HI_B16 : VGLOBAL_Real_AllAddr_gfx12<0x023, "GLOBAL_LOAD_SHORT_D16_HI">; +defm GLOBAL_STORE_D16_HI_B8 : VGLOBAL_Real_AllAddr_gfx12<0x024, "GLOBAL_STORE_BYTE_D16_HI">; +defm GLOBAL_STORE_D16_HI_B16 : VGLOBAL_Real_AllAddr_gfx12<0x025, "GLOBAL_STORE_SHORT_D16_HI">; +defm GLOBAL_LOAD_ADDTID_B32 : VGLOBAL_Real_AllAddr_gfx12<0x028, "GLOBAL_LOAD_DWORD_ADDTID">; +defm GLOBAL_STORE_ADDTID_B32 : VGLOBAL_Real_AllAddr_gfx12<0x029, "GLOBAL_STORE_DWORD_ADDTID">; defm GLOBAL_ATOMIC_SWAP_B32 : VGLOBAL_Real_Atomics_gfx12<0x033, "GLOBAL_ATOMIC_SWAP", "global_atomic_swap_b32", true>; defm GLOBAL_ATOMIC_CMPSWAP_B32 : VGLOBAL_Real_Atomics_gfx12<0x034, "GLOBAL_ATOMIC_CMPSWAP", "global_atomic_cmpswap_b32", true>; @@ -2683,14 +2746,28 @@ defm GLOBAL_ATOMIC_OR_B64 : VGLOBAL_Real_Atomics_gfx12<0x04a, "GLOBAL_A defm GLOBAL_ATOMIC_XOR_B64 : VGLOBAL_Real_Atomics_gfx12<0x04b, "GLOBAL_ATOMIC_XOR_X2", "global_atomic_xor_b64", true>; defm GLOBAL_ATOMIC_INC_U64 : VGLOBAL_Real_Atomics_gfx12<0x04c, "GLOBAL_ATOMIC_INC_X2", "global_atomic_inc_u64", true>; defm GLOBAL_ATOMIC_DEC_U64 : VGLOBAL_Real_Atomics_gfx12<0x04d, "GLOBAL_ATOMIC_DEC_X2", "global_atomic_dec_u64", true>; +defm GLOBAL_ATOMIC_COND_SUB_U32 : VGLOBAL_Real_Atomics_gfx12<0x050, "GLOBAL_ATOMIC_COND_SUB_U32", "global_atomic_cond_sub_u32">; defm GLOBAL_ATOMIC_MIN_NUM_F32 : VGLOBAL_Real_Atomics_gfx12<0x051, "GLOBAL_ATOMIC_FMIN", "global_atomic_min_num_f32", true, "global_atomic_min_f32">; defm GLOBAL_ATOMIC_MAX_NUM_F32 : VGLOBAL_Real_Atomics_gfx12<0x052, "GLOBAL_ATOMIC_FMAX", "global_atomic_max_num_f32", true, "global_atomic_max_f32">; -defm GLOBAL_ATOMIC_ADD_F32 : VGLOBAL_Real_Atomics_gfx12<0x056, "GLOBAL_ATOMIC_ADD_F32", "global_atomic_add_f32">; -defm GLOBAL_ATOMIC_ORDERED_ADD_B64 : VGLOBAL_Real_Atomics_gfx12<0x073, "GLOBAL_ATOMIC_ORDERED_ADD_B64", "global_atomic_ordered_add_b64">; +defm GLOBAL_ATOMIC_ADD_F32 : VGLOBAL_Real_Atomics_gfx12<0x056>; -defm GLOBAL_INV : VFLAT_Real_Base_gfx12<0x02b, "GLOBAL_INV", "global_inv">; -defm GLOBAL_WB : VFLAT_Real_Base_gfx12<0x02c, "GLOBAL_WB", "global_wb">; -defm GLOBAL_WBINV : VFLAT_Real_Base_gfx12<0x04f, "GLOBAL_WBINV", "global_wbinv">; +let WaveSizePredicate = isWave32, DecoderNamespace = "GFX12" in { + defm GLOBAL_LOAD_TR_B128_w32 : VGLOBAL_Real_AllAddr_gfx12<0x057, "GLOBAL_LOAD_TR_B128_w32", "global_load_tr_b128">; + defm GLOBAL_LOAD_TR_B64_w32 : VGLOBAL_Real_AllAddr_gfx12<0x058, "GLOBAL_LOAD_TR_B64_w32", "global_load_tr_b64">; +} + +let WaveSizePredicate = isWave64, DecoderNamespace = "GFX12W64" in { + defm GLOBAL_LOAD_TR_B128_w64 : VGLOBAL_Real_AllAddr_gfx12<0x057, "GLOBAL_LOAD_TR_B128_w64", "global_load_tr_b128">; + defm GLOBAL_LOAD_TR_B64_w64 : VGLOBAL_Real_AllAddr_gfx12<0x058, "GLOBAL_LOAD_TR_B64_w64", "global_load_tr_b64">; +} + +defm GLOBAL_ATOMIC_ORDERED_ADD_B64 : VGLOBAL_Real_Atomics_gfx12<0x073>; +defm GLOBAL_ATOMIC_PK_ADD_F16 : VGLOBAL_Real_Atomics_gfx12<0x059>; +defm GLOBAL_ATOMIC_PK_ADD_BF16 : VGLOBAL_Real_Atomics_gfx12<0x05a>; + +defm GLOBAL_INV : VFLAT_Real_Base_gfx12<0x02b>; +defm GLOBAL_WB : VFLAT_Real_Base_gfx12<0x02c>; +defm GLOBAL_WBINV : VFLAT_Real_Base_gfx12<0x04f>; // ENC_VSCRATCH. defm SCRATCH_LOAD_U8 : VSCRATCH_Real_AllAddr_gfx12<0x10, "SCRATCH_LOAD_UBYTE", "scratch_load_u8", true>; @@ -2707,11 +2784,11 @@ defm SCRATCH_STORE_B32 : VSCRATCH_Real_AllAddr_gfx12<0x1a, "SCRATCH_ defm SCRATCH_STORE_B64 : VSCRATCH_Real_AllAddr_gfx12<0x1b, "SCRATCH_STORE_DWORDX2", "scratch_store_b64", true>; defm SCRATCH_STORE_B96 : VSCRATCH_Real_AllAddr_gfx12<0x1c, "SCRATCH_STORE_DWORDX3", "scratch_store_b96", true>; defm SCRATCH_STORE_B128 : VSCRATCH_Real_AllAddr_gfx12<0x1d, "SCRATCH_STORE_DWORDX4", "scratch_store_b128", true>; -defm SCRATCH_LOAD_D16_U8 : VSCRATCH_Real_AllAddr_gfx12<0x1e, "SCRATCH_LOAD_UBYTE_D16", "scratch_load_d16_u8">; -defm SCRATCH_LOAD_D16_I8 : VSCRATCH_Real_AllAddr_gfx12<0x1f, "SCRATCH_LOAD_SBYTE_D16", "scratch_load_d16_i8">; -defm SCRATCH_LOAD_D16_B16 : VSCRATCH_Real_AllAddr_gfx12<0x20, "SCRATCH_LOAD_SHORT_D16", "scratch_load_d16_b16">; -defm SCRATCH_LOAD_D16_HI_U8 : VSCRATCH_Real_AllAddr_gfx12<0x21, "SCRATCH_LOAD_UBYTE_D16_HI", "scratch_load_d16_hi_u8">; -defm SCRATCH_LOAD_D16_HI_I8 : VSCRATCH_Real_AllAddr_gfx12<0x22, "SCRATCH_LOAD_SBYTE_D16_HI", "scratch_load_d16_hi_i8">; -defm SCRATCH_LOAD_D16_HI_B16 : VSCRATCH_Real_AllAddr_gfx12<0x23, "SCRATCH_LOAD_SHORT_D16_HI", "scratch_load_d16_hi_b16">; -defm SCRATCH_STORE_D16_HI_B8 : VSCRATCH_Real_AllAddr_gfx12<0x24, "SCRATCH_STORE_BYTE_D16_HI", "scratch_store_d16_hi_b8">; -defm SCRATCH_STORE_D16_HI_B16 : VSCRATCH_Real_AllAddr_gfx12<0x25, "SCRATCH_STORE_SHORT_D16_HI", "scratch_store_d16_hi_b16">; +defm SCRATCH_LOAD_D16_U8 : VSCRATCH_Real_AllAddr_gfx12<0x1e, "SCRATCH_LOAD_UBYTE_D16">; +defm SCRATCH_LOAD_D16_I8 : VSCRATCH_Real_AllAddr_gfx12<0x1f, "SCRATCH_LOAD_SBYTE_D16">; +defm SCRATCH_LOAD_D16_B16 : VSCRATCH_Real_AllAddr_gfx12<0x20, "SCRATCH_LOAD_SHORT_D16">; +defm SCRATCH_LOAD_D16_HI_U8 : VSCRATCH_Real_AllAddr_gfx12<0x21, "SCRATCH_LOAD_UBYTE_D16_HI">; +defm SCRATCH_LOAD_D16_HI_I8 : VSCRATCH_Real_AllAddr_gfx12<0x22, "SCRATCH_LOAD_SBYTE_D16_HI">; +defm SCRATCH_LOAD_D16_HI_B16 : VSCRATCH_Real_AllAddr_gfx12<0x23, "SCRATCH_LOAD_SHORT_D16_HI">; +defm SCRATCH_STORE_D16_HI_B8 : VSCRATCH_Real_AllAddr_gfx12<0x24, "SCRATCH_STORE_BYTE_D16_HI">; +defm SCRATCH_STORE_D16_HI_B16 : VSCRATCH_Real_AllAddr_gfx12<0x25, "SCRATCH_STORE_SHORT_D16_HI">; diff --git a/llvm/lib/Target/AMDGPU/GCNDPPCombine.cpp b/llvm/lib/Target/AMDGPU/GCNDPPCombine.cpp index a75082268c7..94d28dc0a2c 100644 --- a/llvm/lib/Target/AMDGPU/GCNDPPCombine.cpp +++ b/llvm/lib/Target/AMDGPU/GCNDPPCombine.cpp @@ -274,8 +274,8 @@ MachineInstr *GCNDPPCombine::createDPPInst(MachineInstr &OrigMI, break; } - if (auto *Mod0 = TII->getNamedOperand(OrigMI, - AMDGPU::OpName::src0_modifiers)) { + auto *Mod0 = TII->getNamedOperand(OrigMI, AMDGPU::OpName::src0_modifiers); + if (Mod0) { assert(NumOperands == AMDGPU::getNamedOperandIdx(DPPOp, AMDGPU::OpName::src0_modifiers)); assert(HasVOP3DPP || @@ -298,8 +298,8 @@ MachineInstr *GCNDPPCombine::createDPPInst(MachineInstr &OrigMI, DPPInst->getOperand(NumOperands).setIsKill(false); ++NumOperands; - if (auto *Mod1 = TII->getNamedOperand(OrigMI, - AMDGPU::OpName::src1_modifiers)) { + auto *Mod1 = TII->getNamedOperand(OrigMI, AMDGPU::OpName::src1_modifiers); + if (Mod1) { assert(NumOperands == AMDGPU::getNamedOperandIdx(DPPOp, AMDGPU::OpName::src1_modifiers)); assert(HasVOP3DPP || @@ -330,8 +330,9 @@ MachineInstr *GCNDPPCombine::createDPPInst(MachineInstr &OrigMI, DPPInst.add(*Src1); ++NumOperands; } - if (auto *Mod2 = - TII->getNamedOperand(OrigMI, AMDGPU::OpName::src2_modifiers)) { + + auto *Mod2 = TII->getNamedOperand(OrigMI, AMDGPU::OpName::src2_modifiers); + if (Mod2) { assert(NumOperands == AMDGPU::getNamedOperandIdx(DPPOp, AMDGPU::OpName::src2_modifiers)); assert(HasVOP3DPP || @@ -350,6 +351,7 @@ MachineInstr *GCNDPPCombine::createDPPInst(MachineInstr &OrigMI, DPPInst.add(*Src2); ++NumOperands; } + if (HasVOP3DPP) { auto *ClampOpr = TII->getNamedOperand(OrigMI, AMDGPU::OpName::clamp); if (ClampOpr && AMDGPU::hasNamedOperand(DPPOp, AMDGPU::OpName::clamp)) { @@ -368,7 +370,13 @@ MachineInstr *GCNDPPCombine::createDPPInst(MachineInstr &OrigMI, // all 1. if (auto *OpSelOpr = TII->getNamedOperand(OrigMI, AMDGPU::OpName::op_sel)) { - auto OpSel = OpSelOpr->getImm(); + int64_t OpSel = 0; + OpSel |= (Mod0 ? (!!(Mod0->getImm() & SISrcMods::OP_SEL_0) << 0) : 0); + OpSel |= (Mod1 ? (!!(Mod1->getImm() & SISrcMods::OP_SEL_0) << 1) : 0); + OpSel |= (Mod2 ? (!!(Mod2->getImm() & SISrcMods::OP_SEL_0) << 2) : 0); + if (Mod0 && TII->isVOP3(OrigMI) && !TII->isVOP3P(OrigMI)) + OpSel |= !!(Mod0->getImm() & SISrcMods::DST_OP_SEL) << 3; + if (OpSel != 0) { LLVM_DEBUG(dbgs() << " failed: op_sel must be zero\n"); Fail = true; @@ -379,7 +387,11 @@ MachineInstr *GCNDPPCombine::createDPPInst(MachineInstr &OrigMI, } if (auto *OpSelHiOpr = TII->getNamedOperand(OrigMI, AMDGPU::OpName::op_sel_hi)) { - auto OpSelHi = OpSelHiOpr->getImm(); + int64_t OpSelHi = 0; + OpSelHi |= (Mod0 ? (!!(Mod0->getImm() & SISrcMods::OP_SEL_1) << 0) : 0); + OpSelHi |= (Mod1 ? (!!(Mod1->getImm() & SISrcMods::OP_SEL_1) << 1) : 0); + OpSelHi |= (Mod2 ? (!!(Mod2->getImm() & SISrcMods::OP_SEL_1) << 2) : 0); + // Only vop3p has op_sel_hi, and all vop3p have 3 operands, so check // the bitmask for 3 op_sel_hi bits set assert(Src2 && "Expected vop3p with 3 operands"); diff --git a/llvm/lib/Target/AMDGPU/GCNHazardRecognizer.cpp b/llvm/lib/Target/AMDGPU/GCNHazardRecognizer.cpp index bcd93e30d6c..b6e4e65ff5b 100644 --- a/llvm/lib/Target/AMDGPU/GCNHazardRecognizer.cpp +++ b/llvm/lib/Target/AMDGPU/GCNHazardRecognizer.cpp @@ -163,6 +163,7 @@ static bool isSendMsgTraceDataOrGDS(const SIInstrInfo &TII, static bool isPermlane(const MachineInstr &MI) { unsigned Opcode = MI.getOpcode(); return Opcode == AMDGPU::V_PERMLANE16_B32_e64 || + Opcode == AMDGPU::V_PERMLANE64_B32 || Opcode == AMDGPU::V_PERMLANEX16_B32_e64 || Opcode == AMDGPU::V_PERMLANE16_VAR_B32_e64 || Opcode == AMDGPU::V_PERMLANEX16_VAR_B32_e64; @@ -1143,6 +1144,7 @@ bool GCNHazardRecognizer::fixVcmpxPermlaneHazards(MachineInstr *MI) { bool GCNHazardRecognizer::fixVMEMtoScalarWriteHazards(MachineInstr *MI) { if (!ST.hasVMEMtoScalarWriteHazard()) return false; + assert(!ST.hasExtendedWaitCounts()); if (!SIInstrInfo::isSALU(*MI) && !SIInstrInfo::isSMRD(*MI)) return false; @@ -1189,6 +1191,7 @@ bool GCNHazardRecognizer::fixVMEMtoScalarWriteHazards(MachineInstr *MI) { bool GCNHazardRecognizer::fixSMEMtoVectorWriteHazards(MachineInstr *MI) { if (!ST.hasSMEMtoVectorWriteHazard()) return false; + assert(!ST.hasExtendedWaitCounts()); if (!SIInstrInfo::isVALU(*MI)) return false; @@ -1242,7 +1245,8 @@ bool GCNHazardRecognizer::fixSMEMtoVectorWriteHazards(MachineInstr *MI) { case AMDGPU::S_WAITCNT: { const int64_t Imm = MI.getOperand(0).getImm(); AMDGPU::Waitcnt Decoded = AMDGPU::decodeWaitcnt(IV, Imm); - return (Decoded.LgkmCnt == 0); + // DsCnt corresponds to LGKMCnt here. + return (Decoded.DsCnt == 0); } default: // SOPP instructions cannot mitigate the hazard. @@ -1272,7 +1276,11 @@ bool GCNHazardRecognizer::fixSMEMtoVectorWriteHazards(MachineInstr *MI) { } bool GCNHazardRecognizer::fixVcmpxExecWARHazard(MachineInstr *MI) { - if (!ST.hasVcmpxExecWARHazard() || !SIInstrInfo::isVALU(*MI)) + if (!ST.hasVcmpxExecWARHazard()) + return false; + assert(!ST.hasExtendedWaitCounts()); + + if (!SIInstrInfo::isVALU(*MI)) return false; const SIRegisterInfo *TRI = ST.getRegisterInfo(); @@ -1342,6 +1350,7 @@ bool GCNHazardRecognizer::fixLdsBranchVmemWARHazard(MachineInstr *MI) { return false; assert(ST.hasLdsBranchVmemWARHazard()); + assert(!ST.hasExtendedWaitCounts()); auto IsHazardInst = [](const MachineInstr &MI) { if (SIInstrInfo::isDS(MI)) @@ -1451,6 +1460,8 @@ bool GCNHazardRecognizer::fixLdsDirectVMEMHazard(MachineInstr *MI) { return I.readsRegister(VDSTReg, &TRI) || I.modifiesRegister(VDSTReg, &TRI); }; bool LdsdirCanWait = ST.hasLdsWaitVMSRC(); + // TODO: On GFX12 the hazard should expire on S_WAIT_LOADCNT/SAMPLECNT/BVHCNT + // according to the type of VMEM instruction. auto IsExpiredFn = [this, LdsdirCanWait](const MachineInstr &I, int) { return SIInstrInfo::isVALU(I) || SIInstrInfo::isEXP(I) || (I.getOpcode() == AMDGPU::S_WAITCNT && !I.getOperand(0).getImm()) || @@ -1476,11 +1487,11 @@ bool GCNHazardRecognizer::fixLdsDirectVMEMHazard(MachineInstr *MI) { } bool GCNHazardRecognizer::fixVALUPartialForwardingHazard(MachineInstr *MI) { - if (!ST.isWave64()) - return false; if (!ST.hasVALUPartialForwardingHazard()) return false; - if (!SIInstrInfo::isVALU(*MI)) + assert(!ST.hasExtendedWaitCounts()); + + if (!ST.isWave64() || !SIInstrInfo::isVALU(*MI)) return false; SmallSetVector SrcVGPRs; @@ -1627,6 +1638,8 @@ bool GCNHazardRecognizer::fixVALUPartialForwardingHazard(MachineInstr *MI) { bool GCNHazardRecognizer::fixVALUTransUseHazard(MachineInstr *MI) { if (!ST.hasVALUTransUseHazard()) return false; + assert(!ST.hasExtendedWaitCounts()); + if (!SIInstrInfo::isVALU(*MI)) return false; @@ -1766,6 +1779,7 @@ bool GCNHazardRecognizer::fixWMMAHazards(MachineInstr *MI) { bool GCNHazardRecognizer::fixShift64HighRegBug(MachineInstr *MI) { if (!ST.hasShift64HighRegBug()) return false; + assert(!ST.hasExtendedWaitCounts()); switch (MI->getOpcode()) { default: @@ -1895,6 +1909,7 @@ int GCNHazardRecognizer::checkFPAtomicToDenormModeHazard(MachineInstr *MI) { if (!ST.hasFPAtomicToDenormModeHazard()) return 0; + assert(!ST.hasExtendedWaitCounts()); if (MI->getOpcode() != AMDGPU::S_DENORM_MODE) return 0; @@ -2720,11 +2735,11 @@ bool GCNHazardRecognizer::ShouldPreferAnother(SUnit *SU) { } bool GCNHazardRecognizer::fixVALUMaskWriteHazard(MachineInstr *MI) { - if (!ST.isWave64()) - return false; if (!ST.hasVALUMaskWriteHazard()) return false; - if (!SIInstrInfo::isSALU(*MI)) + assert(!ST.hasExtendedWaitCounts()); + + if (!ST.isWave64() || !SIInstrInfo::isSALU(*MI)) return false; // The hazard sequence is three instructions: diff --git a/llvm/lib/Target/AMDGPU/GCNNSAReassign.cpp b/llvm/lib/Target/AMDGPU/GCNNSAReassign.cpp index 4c9ad9b5bcf..272cc7fa6bc 100644 --- a/llvm/lib/Target/AMDGPU/GCNNSAReassign.cpp +++ b/llvm/lib/Target/AMDGPU/GCNNSAReassign.cpp @@ -237,7 +237,7 @@ GCNNSAReassign::CheckNSA(const MachineInstr &MI, bool Fast) const { bool GCNNSAReassign::runOnMachineFunction(MachineFunction &MF) { ST = &MF.getSubtarget(); - if (!ST->hasNSAEncoding()) + if (!ST->hasNSAEncoding() || !ST->hasNonNSAEncoding()) return false; MRI = &MF.getRegInfo(); diff --git a/llvm/lib/Target/AMDGPU/GCNSubtarget.h b/llvm/lib/Target/AMDGPU/GCNSubtarget.h index 85d062a9a6f..8019b98b1c6 100644 --- a/llvm/lib/Target/AMDGPU/GCNSubtarget.h +++ b/llvm/lib/Target/AMDGPU/GCNSubtarget.h @@ -155,6 +155,7 @@ protected: bool HasDot10Insts = false; bool HasMAIInsts = false; bool HasFP8Insts = false; + bool HasFP8ConversionInsts = false; bool HasPkFmacF16Inst = false; bool HasAtomicDsPkAdd16Insts = false; bool HasAtomicFlatPkAdd16Insts = false; @@ -165,6 +166,8 @@ protected: bool HasAtomicCSubNoRtnInsts = false; bool HasAtomicGlobalPkAddBF16Inst = false; bool HasFlatAtomicFaddF32Inst = false; + bool HasDefaultComponentZero = false; + bool HasDefaultComponentBroadcast = false; bool SupportsSRAMECC = false; // This should not be used directly. 'TargetID' tracks the dynamic settings @@ -295,12 +298,16 @@ public: unsigned getMaxWaveScratchSize() const { // See COMPUTE_TMPRING_SIZE.WAVESIZE. - if (getGeneration() < GFX11) { - // 13-bit field in units of 256-dword. - return (256 * 4) * ((1 << 13) - 1); + if (getGeneration() >= GFX12) { + // 18-bit field in units of 64-dword. + return (64 * 4) * ((1 << 18) - 1); } - // 15-bit field in units of 64-dword. - return (64 * 4) * ((1 << 15) - 1); + if (getGeneration() == GFX11) { + // 15-bit field in units of 64-dword. + return (64 * 4) * ((1 << 15) - 1); + } + // 13-bit field in units of 256-dword. + return (256 * 4) * ((1 << 13) - 1); } /// Return the number of high bits known to be zero for a frame index. @@ -423,6 +430,8 @@ public: return GFX9Insts; } + bool hasScalarSubwordLoads() const { return getGeneration() >= GFX12; } + TrapHandlerAbi getTrapHandlerAbi() const { return isAmdHsaOS() ? TrapHandlerAbi::AMDHSA : TrapHandlerAbi::NONE; } @@ -772,6 +781,8 @@ public: return HasFP8Insts; } + bool hasFP8ConversionInsts() const { return HasFP8ConversionInsts; } + bool hasPkFmacF16Inst() const { return HasPkFmacF16Inst; } @@ -802,6 +813,12 @@ public: bool hasFlatAtomicFaddF32Inst() const { return HasFlatAtomicFaddF32Inst; } + bool hasDefaultComponentZero() const { return HasDefaultComponentZero; } + + bool hasDefaultComponentBroadcast() const { + return HasDefaultComponentBroadcast; + } + bool hasNoSdstCMPX() const { return HasNoSdstCMPX; } @@ -838,7 +855,9 @@ public: return getGeneration() < SEA_ISLANDS; } - bool hasInstPrefetch() const { return getGeneration() >= GFX10; } + bool hasInstPrefetch() const { + return getGeneration() == GFX10 || getGeneration() == GFX11; + } bool hasPrefetch() const { return GFX12Insts; } @@ -984,6 +1003,8 @@ public: bool hasNSAEncoding() const { return HasNSAEncoding; } + bool hasNonNSAEncoding() const { return getGeneration() < GFX12; } + bool hasPartialNSAEncoding() const { return HasPartialNSAEncoding; } unsigned getNSAMaxSize(bool HasSampler = false) const { @@ -1131,14 +1152,14 @@ public: bool hasLdsWaitVMSRC() const { return getGeneration() >= GFX12; } bool hasVALUPartialForwardingHazard() const { - return getGeneration() >= GFX11; + return getGeneration() == GFX11; } bool hasVALUTransUseHazard() const { return HasVALUTransUseHazard; } bool hasForceStoreSC0SC1() const { return HasForceStoreSC0SC1; } - bool hasVALUMaskWriteHazard() const { return getGeneration() >= GFX11; } + bool hasVALUMaskWriteHazard() const { return getGeneration() == GFX11; } /// Return if operations acting on VGPR tuples require even alignment. bool needsAlignedVGPRs() const { return GFX90AInsts; } @@ -1177,6 +1198,10 @@ public: bool hasRestrictedSOffset() const { return HasRestrictedSOffset; } + /// \returns true if the target uses LOADcnt/SAMPLEcnt/BVHcnt, DScnt/KMcnt + /// and STOREcnt rather than VMcnt, LGKMcnt and VScnt respectively. + bool hasExtendedWaitCounts() const { return getGeneration() >= GFX12; } + /// Return the maximum number of waves per SIMD for kernels using \p SGPRs /// SGPRs unsigned getOccupancyWithNumSGPRs(unsigned SGPRs) const; @@ -1251,6 +1276,14 @@ public: // \returns true if the target has WG_RR_MODE kernel descriptor mode bit bool hasRrWGMode() const { return getGeneration() >= GFX12; } + /// \returns true if VADDR and SADDR fields in VSCRATCH can use negative + /// values. + bool hasSignedScratchOffsets() const { return getGeneration() >= GFX12; } + + // \returns true if S_GETPC_B64 zero-extends the result from 48 bits instead + // of sign-extending. + bool hasGetPCZeroExtension() const { return GFX12Insts; } + /// \returns SGPR allocation granularity supported by the subtarget. unsigned getSGPRAllocGranule() const { return AMDGPU::IsaInfo::getSGPRAllocGranule(this); diff --git a/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUAsmBackend.cpp b/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUAsmBackend.cpp index f91f36ed851..8eb246ef57c 100644 --- a/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUAsmBackend.cpp +++ b/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUAsmBackend.cpp @@ -232,13 +232,11 @@ class ELFAMDGPUAsmBackend : public AMDGPUAsmBackend { bool Is64Bit; bool HasRelocationAddend; uint8_t OSABI = ELF::ELFOSABI_NONE; - uint8_t ABIVersion = 0; public: - ELFAMDGPUAsmBackend(const Target &T, const Triple &TT, uint8_t ABIVersion) : - AMDGPUAsmBackend(T), Is64Bit(TT.getArch() == Triple::amdgcn), - HasRelocationAddend(TT.getOS() == Triple::AMDHSA), - ABIVersion(ABIVersion) { + ELFAMDGPUAsmBackend(const Target &T, const Triple &TT) + : AMDGPUAsmBackend(T), Is64Bit(TT.getArch() == Triple::amdgcn), + HasRelocationAddend(TT.getOS() == Triple::AMDHSA) { switch (TT.getOS()) { case Triple::AMDHSA: OSABI = ELF::ELFOSABI_AMDGPU_HSA; @@ -256,8 +254,7 @@ public: std::unique_ptr createObjectTargetWriter() const override { - return createAMDGPUELFObjectWriter(Is64Bit, OSABI, HasRelocationAddend, - ABIVersion); + return createAMDGPUELFObjectWriter(Is64Bit, OSABI, HasRelocationAddend); } }; @@ -267,6 +264,5 @@ MCAsmBackend *llvm::createAMDGPUAsmBackend(const Target &T, const MCSubtargetInfo &STI, const MCRegisterInfo &MRI, const MCTargetOptions &Options) { - return new ELFAMDGPUAsmBackend(T, STI.getTargetTriple(), - getHsaAbiVersion(&STI).value_or(0)); + return new ELFAMDGPUAsmBackend(T, STI.getTargetTriple()); } diff --git a/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUELFObjectWriter.cpp b/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUELFObjectWriter.cpp index 58eed81e075..2d960a32339 100644 --- a/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUELFObjectWriter.cpp +++ b/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUELFObjectWriter.cpp @@ -18,8 +18,7 @@ namespace { class AMDGPUELFObjectWriter : public MCELFObjectTargetWriter { public: - AMDGPUELFObjectWriter(bool Is64Bit, uint8_t OSABI, bool HasRelocationAddend, - uint8_t ABIVersion); + AMDGPUELFObjectWriter(bool Is64Bit, uint8_t OSABI, bool HasRelocationAddend); protected: unsigned getRelocType(MCContext &Ctx, const MCValue &Target, @@ -29,12 +28,10 @@ protected: } // end anonymous namespace -AMDGPUELFObjectWriter::AMDGPUELFObjectWriter(bool Is64Bit, - uint8_t OSABI, - bool HasRelocationAddend, - uint8_t ABIVersion) - : MCELFObjectTargetWriter(Is64Bit, OSABI, ELF::EM_AMDGPU, - HasRelocationAddend, ABIVersion) {} +AMDGPUELFObjectWriter::AMDGPUELFObjectWriter(bool Is64Bit, uint8_t OSABI, + bool HasRelocationAddend) + : MCELFObjectTargetWriter(Is64Bit, OSABI, ELF::EM_AMDGPU, + HasRelocationAddend) {} unsigned AMDGPUELFObjectWriter::getRelocType(MCContext &Ctx, const MCValue &Target, @@ -100,9 +97,7 @@ unsigned AMDGPUELFObjectWriter::getRelocType(MCContext &Ctx, std::unique_ptr llvm::createAMDGPUELFObjectWriter(bool Is64Bit, uint8_t OSABI, - bool HasRelocationAddend, - uint8_t ABIVersion) { + bool HasRelocationAddend) { return std::make_unique(Is64Bit, OSABI, - HasRelocationAddend, - ABIVersion); + HasRelocationAddend); } diff --git a/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.cpp b/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.cpp index 6c7977e2259..e73e53aa270 100644 --- a/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.cpp +++ b/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.cpp @@ -1260,14 +1260,19 @@ void AMDGPUInstPrinter::printPackedModifier(const MCInst *MI, int NumOps = 0; int Ops[3]; - for (int OpName : { AMDGPU::OpName::src0_modifiers, - AMDGPU::OpName::src1_modifiers, - AMDGPU::OpName::src2_modifiers }) { - int Idx = AMDGPU::getNamedOperandIdx(Opc, OpName); - if (Idx == -1) + std::pair MOps[] = { + {AMDGPU::OpName::src0_modifiers, AMDGPU::OpName::src0}, + {AMDGPU::OpName::src1_modifiers, AMDGPU::OpName::src1}, + {AMDGPU::OpName::src2_modifiers, AMDGPU::OpName::src2}}; + int DefaultValue = (Mod == SISrcMods::OP_SEL_1); + + for (auto [SrcMod, Src] : MOps) { + if (!AMDGPU::hasNamedOperand(Opc, Src)) break; - Ops[NumOps++] = MI->getOperand(Idx).getImm(); + int ModIdx = AMDGPU::getNamedOperandIdx(Opc, SrcMod); + Ops[NumOps++] = + (ModIdx != -1) ? MI->getOperand(ModIdx).getImm() : DefaultValue; } const bool HasDstSel = diff --git a/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCCodeEmitter.cpp b/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCCodeEmitter.cpp index de1abaf29c5..c3e87244c0c 100644 --- a/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCCodeEmitter.cpp +++ b/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCCodeEmitter.cpp @@ -562,7 +562,48 @@ void AMDGPUMCCodeEmitter::getMachineOpValue(const MCInst &MI, void AMDGPUMCCodeEmitter::getMachineOpValueT16( const MCInst &MI, unsigned OpNo, APInt &Op, SmallVectorImpl &Fixups, const MCSubtargetInfo &STI) const { - llvm_unreachable("TODO: Implement getMachineOpValueT16()."); + const MCOperand &MO = MI.getOperand(OpNo); + if (MO.isReg()) { + unsigned Enc = MRI.getEncodingValue(MO.getReg()); + unsigned Idx = Enc & AMDGPU::HWEncoding::REG_IDX_MASK; + bool IsVGPR = Enc & AMDGPU::HWEncoding::IS_VGPR_OR_AGPR; + Op = Idx | (IsVGPR << 8); + return; + } + getMachineOpValueCommon(MI, MO, OpNo, Op, Fixups, STI); + // VGPRs include the suffix/op_sel bit in the register encoding, but + // immediates and SGPRs include it in src_modifiers. Therefore, copy the + // op_sel bit from the src operands into src_modifier operands if Op is + // src_modifiers and the corresponding src is a VGPR + int SrcMOIdx = -1; + assert(OpNo < INT_MAX); + if ((int)OpNo == AMDGPU::getNamedOperandIdx(MI.getOpcode(), + AMDGPU::OpName::src0_modifiers)) { + SrcMOIdx = AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::src0); + int VDstMOIdx = + AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::vdst); + if (VDstMOIdx != -1) { + auto DstReg = MI.getOperand(VDstMOIdx).getReg(); + if (AMDGPU::isHi(DstReg, MRI)) + Op |= SISrcMods::DST_OP_SEL; + } + } else if ((int)OpNo == AMDGPU::getNamedOperandIdx( + MI.getOpcode(), AMDGPU::OpName::src1_modifiers)) + SrcMOIdx = AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::src1); + else if ((int)OpNo == AMDGPU::getNamedOperandIdx( + MI.getOpcode(), AMDGPU::OpName::src2_modifiers)) + SrcMOIdx = AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::src2); + if (SrcMOIdx == -1) + return; + + const MCOperand &SrcMO = MI.getOperand(SrcMOIdx); + if (!SrcMO.isReg()) + return; + auto SrcReg = SrcMO.getReg(); + if (AMDGPU::isSGPR(SrcReg, &MRI)) + return; + if (AMDGPU::isHi(SrcReg, MRI)) + Op |= SISrcMods::OP_SEL_0; } void AMDGPUMCCodeEmitter::getMachineOpValueT16Lo128( diff --git a/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCTargetDesc.h b/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCTargetDesc.h index 006115ba14f..3ef00f75735 100644 --- a/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCTargetDesc.h +++ b/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCTargetDesc.h @@ -42,8 +42,8 @@ MCAsmBackend *createAMDGPUAsmBackend(const Target &T, std::unique_ptr createAMDGPUELFObjectWriter(bool Is64Bit, uint8_t OSABI, - bool HasRelocationAddend, uint8_t ABIVersion); -} // End llvm namespace + bool HasRelocationAddend); +} // namespace llvm #define GET_REGINFO_ENUM #include "AMDGPUGenRegisterInfo.inc" diff --git a/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUTargetStreamer.cpp b/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUTargetStreamer.cpp index e135a4e25dd..d7e8ab76d5f 100644 --- a/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUTargetStreamer.cpp +++ b/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUTargetStreamer.cpp @@ -20,6 +20,7 @@ #include "llvm/MC/MCAssembler.h" #include "llvm/MC/MCContext.h" #include "llvm/MC/MCELFStreamer.h" +#include "llvm/MC/MCObjectWriter.h" #include "llvm/MC/MCSectionELF.h" #include "llvm/MC/MCSubtargetInfo.h" #include "llvm/Support/AMDGPUMetadata.h" @@ -35,27 +36,6 @@ using namespace llvm::AMDGPU; // AMDGPUTargetStreamer //===----------------------------------------------------------------------===// -static void convertIsaVersionV2(uint32_t &Major, uint32_t &Minor, - uint32_t &Stepping, bool Sramecc, bool Xnack) { - if (Major == 9 && Minor == 0) { - switch (Stepping) { - case 0: - case 2: - case 4: - case 6: - if (Xnack) - Stepping++; - } - } -} - -bool AMDGPUTargetStreamer::EmitHSAMetadataV2(StringRef HSAMetadataString) { - HSAMD::Metadata HSAMetadata; - if (HSAMD::fromString(HSAMetadataString, HSAMetadata)) - return false; - return EmitHSAMetadata(HSAMetadata); -} - bool AMDGPUTargetStreamer::EmitHSAMetadataV3(StringRef HSAMetadataString) { msgpack::Document HSAMetadataDoc; if (!HSAMetadataDoc.fromYAML(HSAMetadataString)) @@ -238,21 +218,10 @@ void AMDGPUTargetAsmStreamer::EmitDirectiveAMDGCNTarget() { OS << "\t.amdgcn_target \"" << getTargetID()->toString() << "\"\n"; } -void AMDGPUTargetAsmStreamer::EmitDirectiveHSACodeObjectVersion( - uint32_t Major, uint32_t Minor) { - OS << "\t.hsa_code_object_version " << - Twine(Major) << "," << Twine(Minor) << '\n'; -} - -void -AMDGPUTargetAsmStreamer::EmitDirectiveHSACodeObjectISAV2(uint32_t Major, - uint32_t Minor, - uint32_t Stepping, - StringRef VendorName, - StringRef ArchName) { - convertIsaVersionV2(Major, Minor, Stepping, TargetID->isSramEccOnOrAny(), TargetID->isXnackOnOrAny()); - OS << "\t.hsa_code_object_isa " << Twine(Major) << "," << Twine(Minor) << "," - << Twine(Stepping) << ",\"" << VendorName << "\",\"" << ArchName << "\"\n"; +void AMDGPUTargetAsmStreamer::EmitDirectiveAMDHSACodeObjectVersion( + unsigned COV) { + AMDGPUTargetStreamer::EmitDirectiveAMDHSACodeObjectVersion(COV); + OS << "\t.amdhsa_code_object_version " << COV << '\n'; } void @@ -283,18 +252,6 @@ bool AMDGPUTargetAsmStreamer::EmitISAVersion() { return true; } -bool AMDGPUTargetAsmStreamer::EmitHSAMetadata( - const AMDGPU::HSAMD::Metadata &HSAMetadata) { - std::string HSAMetadataString; - if (HSAMD::toString(HSAMetadata, HSAMetadataString)) - return false; - - OS << '\t' << HSAMD::AssemblerDirectiveBegin << '\n'; - OS << HSAMetadataString << '\n'; - OS << '\t' << HSAMD::AssemblerDirectiveEnd << '\n'; - return true; -} - bool AMDGPUTargetAsmStreamer::EmitHSAMetadata( msgpack::Document &HSAMetadataDoc, bool Strict) { HSAMD::V3::MetadataVerifier Verifier(Strict); @@ -336,7 +293,7 @@ bool AMDGPUTargetAsmStreamer::EmitCodeEnd(const MCSubtargetInfo &STI) { void AMDGPUTargetAsmStreamer::EmitAmdhsaKernelDescriptor( const MCSubtargetInfo &STI, StringRef KernelName, const amdhsa::kernel_descriptor_t &KD, uint64_t NextVGPR, uint64_t NextSGPR, - bool ReserveVCC, bool ReserveFlatScr, unsigned CodeObjectVersion) { + bool ReserveVCC, bool ReserveFlatScr) { IsaVersion IVersion = getIsaVersion(STI.getCPU()); OS << "\t.amdhsa_kernel " << KernelName << '\n'; @@ -529,6 +486,8 @@ MCELFStreamer &AMDGPUTargetELFStreamer::getStreamer() { void AMDGPUTargetELFStreamer::finish() { MCAssembler &MCA = getStreamer().getAssembler(); MCA.setELFHeaderEFlags(getEFlags()); + MCA.getWriter().setOverrideABIVersion( + getELFABIVersion(STI.getTargetTriple(), CodeObjectVersion)); std::string Blob; const char *Vendor = getPALMetadata()->getVendor(); @@ -616,17 +575,7 @@ unsigned AMDGPUTargetELFStreamer::getEFlagsUnknownOS() { unsigned AMDGPUTargetELFStreamer::getEFlagsAMDHSA() { assert(isHsaAbi(STI)); - if (std::optional HsaAbiVer = getHsaAbiVersion(&STI)) { - switch (*HsaAbiVer) { - case ELF::ELFABIVERSION_AMDGPU_HSA_V3: - return getEFlagsV3(); - case ELF::ELFABIVERSION_AMDGPU_HSA_V4: - case ELF::ELFABIVERSION_AMDGPU_HSA_V5: - return getEFlagsV4(); - } - } - - llvm_unreachable("HSA OS ABI Version identification must be defined"); + return getEFlagsV4(); } unsigned AMDGPUTargetELFStreamer::getEFlagsAMDPAL() { @@ -699,44 +648,6 @@ unsigned AMDGPUTargetELFStreamer::getEFlagsV4() { void AMDGPUTargetELFStreamer::EmitDirectiveAMDGCNTarget() {} -void AMDGPUTargetELFStreamer::EmitDirectiveHSACodeObjectVersion( - uint32_t Major, uint32_t Minor) { - - EmitNote(ElfNote::NoteNameV2, MCConstantExpr::create(8, getContext()), - ELF::NT_AMD_HSA_CODE_OBJECT_VERSION, [&](MCELFStreamer &OS) { - OS.emitInt32(Major); - OS.emitInt32(Minor); - }); -} - -void -AMDGPUTargetELFStreamer::EmitDirectiveHSACodeObjectISAV2(uint32_t Major, - uint32_t Minor, - uint32_t Stepping, - StringRef VendorName, - StringRef ArchName) { - uint16_t VendorNameSize = VendorName.size() + 1; - uint16_t ArchNameSize = ArchName.size() + 1; - - unsigned DescSZ = sizeof(VendorNameSize) + sizeof(ArchNameSize) + - sizeof(Major) + sizeof(Minor) + sizeof(Stepping) + - VendorNameSize + ArchNameSize; - - convertIsaVersionV2(Major, Minor, Stepping, TargetID->isSramEccOnOrAny(), TargetID->isXnackOnOrAny()); - EmitNote(ElfNote::NoteNameV2, MCConstantExpr::create(DescSZ, getContext()), - ELF::NT_AMD_HSA_ISA_VERSION, [&](MCELFStreamer &OS) { - OS.emitInt16(VendorNameSize); - OS.emitInt16(ArchNameSize); - OS.emitInt32(Major); - OS.emitInt32(Minor); - OS.emitInt32(Stepping); - OS.emitBytes(VendorName); - OS.emitInt8(0); // NULL terminate VendorName - OS.emitBytes(ArchName); - OS.emitInt8(0); // NULL terminate ArchName - }); -} - void AMDGPUTargetELFStreamer::EmitAMDKernelCodeT(const amd_kernel_code_t &Header) { @@ -818,30 +729,6 @@ bool AMDGPUTargetELFStreamer::EmitHSAMetadata(msgpack::Document &HSAMetadataDoc, return true; } -bool AMDGPUTargetELFStreamer::EmitHSAMetadata( - const AMDGPU::HSAMD::Metadata &HSAMetadata) { - std::string HSAMetadataString; - if (HSAMD::toString(HSAMetadata, HSAMetadataString)) - return false; - - // Create two labels to mark the beginning and end of the desc field - // and a MCExpr to calculate the size of the desc field. - auto &Context = getContext(); - auto *DescBegin = Context.createTempSymbol(); - auto *DescEnd = Context.createTempSymbol(); - auto *DescSZ = MCBinaryExpr::createSub( - MCSymbolRefExpr::create(DescEnd, Context), - MCSymbolRefExpr::create(DescBegin, Context), Context); - - EmitNote(ElfNote::NoteNameV2, DescSZ, ELF::NT_AMD_HSA_METADATA, - [&](MCELFStreamer &OS) { - OS.emitLabel(DescBegin); - OS.emitBytes(HSAMetadataString); - OS.emitLabel(DescEnd); - }); - return true; -} - bool AMDGPUTargetAsmStreamer::EmitKernargPreloadHeader( const MCSubtargetInfo &STI) { for (int i = 0; i < 64; ++i) { @@ -889,8 +776,7 @@ bool AMDGPUTargetELFStreamer::EmitCodeEnd(const MCSubtargetInfo &STI) { void AMDGPUTargetELFStreamer::EmitAmdhsaKernelDescriptor( const MCSubtargetInfo &STI, StringRef KernelName, const amdhsa::kernel_descriptor_t &KernelDescriptor, uint64_t NextVGPR, - uint64_t NextSGPR, bool ReserveVCC, bool ReserveFlatScr, - unsigned CodeObjectVersion) { + uint64_t NextSGPR, bool ReserveVCC, bool ReserveFlatScr) { auto &Streamer = getStreamer(); auto &Context = Streamer.getContext(); diff --git a/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUTargetStreamer.h b/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUTargetStreamer.h index 55b5246c921..7f8ddc42b2e 100644 --- a/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUTargetStreamer.h +++ b/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUTargetStreamer.h @@ -37,23 +37,24 @@ class AMDGPUTargetStreamer : public MCTargetStreamer { protected: // TODO: Move HSAMetadataStream to AMDGPUTargetStreamer. std::optional TargetID; + unsigned CodeObjectVersion; MCContext &getContext() const { return Streamer.getContext(); } public: - AMDGPUTargetStreamer(MCStreamer &S) : MCTargetStreamer(S) {} + AMDGPUTargetStreamer(MCStreamer &S) + : MCTargetStreamer(S), + // Assume the default COV for now, EmitDirectiveAMDHSACodeObjectVersion + // will update this if it is encountered. + CodeObjectVersion(AMDGPU::getDefaultAMDHSACodeObjectVersion()) {} AMDGPUPALMetadata *getPALMetadata() { return &PALMetadata; } virtual void EmitDirectiveAMDGCNTarget(){}; - virtual void EmitDirectiveHSACodeObjectVersion(uint32_t Major, - uint32_t Minor){}; - - virtual void EmitDirectiveHSACodeObjectISAV2(uint32_t Major, uint32_t Minor, - uint32_t Stepping, - StringRef VendorName, - StringRef ArchName){}; + virtual void EmitDirectiveAMDHSACodeObjectVersion(unsigned COV) { + CodeObjectVersion = COV; + } virtual void EmitAMDKernelCodeT(const amd_kernel_code_t &Header){}; @@ -65,9 +66,6 @@ public: /// \returns True on success, false on failure. virtual bool EmitISAVersion() { return true; } - /// \returns True on success, false on failure. - virtual bool EmitHSAMetadataV2(StringRef HSAMetadataString); - /// \returns True on success, false on failure. virtual bool EmitHSAMetadataV3(StringRef HSAMetadataString); @@ -98,8 +96,7 @@ public: virtual void EmitAmdhsaKernelDescriptor( const MCSubtargetInfo &STI, StringRef KernelName, const amdhsa::kernel_descriptor_t &KernelDescriptor, uint64_t NextVGPR, - uint64_t NextSGPR, bool ReserveVCC, bool ReserveFlatScr, - unsigned CodeObjectVersion){}; + uint64_t NextSGPR, bool ReserveVCC, bool ReserveFlatScr) {} static StringRef getArchNameFromElfMach(unsigned ElfMach); static unsigned getElfMach(StringRef GPU); @@ -110,15 +107,12 @@ public: std::optional &getTargetID() { return TargetID; } - void initializeTargetID(const MCSubtargetInfo &STI, - unsigned CodeObjectVersion) { + void initializeTargetID(const MCSubtargetInfo &STI) { assert(TargetID == std::nullopt && "TargetID can only be initialized once"); TargetID.emplace(STI); - getTargetID()->setCodeObjectVersion(CodeObjectVersion); } - void initializeTargetID(const MCSubtargetInfo &STI, StringRef FeatureString, - unsigned CodeObjectVersion) { - initializeTargetID(STI, CodeObjectVersion); + void initializeTargetID(const MCSubtargetInfo &STI, StringRef FeatureString) { + initializeTargetID(STI); assert(getTargetID() != std::nullopt && "TargetID is None"); getTargetID()->setTargetIDFromFeaturesString(FeatureString); @@ -134,12 +128,7 @@ public: void EmitDirectiveAMDGCNTarget() override; - void EmitDirectiveHSACodeObjectVersion(uint32_t Major, - uint32_t Minor) override; - - void EmitDirectiveHSACodeObjectISAV2(uint32_t Major, uint32_t Minor, - uint32_t Stepping, StringRef VendorName, - StringRef ArchName) override; + void EmitDirectiveAMDHSACodeObjectVersion(unsigned COV) override; void EmitAMDKernelCodeT(const amd_kernel_code_t &Header) override; @@ -153,9 +142,6 @@ public: /// \returns True on success, false on failure. bool EmitHSAMetadata(msgpack::Document &HSAMetadata, bool Strict) override; - /// \returns True on success, false on failure. - bool EmitHSAMetadata(const AMDGPU::HSAMD::Metadata &HSAMetadata) override; - /// \returns True on success, false on failure. bool EmitCodeEnd(const MCSubtargetInfo &STI) override; @@ -165,8 +151,7 @@ public: void EmitAmdhsaKernelDescriptor( const MCSubtargetInfo &STI, StringRef KernelName, const amdhsa::kernel_descriptor_t &KernelDescriptor, uint64_t NextVGPR, - uint64_t NextSGPR, bool ReserveVCC, bool ReserveFlatScr, - unsigned CodeObjectVersion) override; + uint64_t NextSGPR, bool ReserveVCC, bool ReserveFlatScr) override; }; class AMDGPUTargetELFStreamer final : public AMDGPUTargetStreamer { @@ -198,13 +183,6 @@ public: void EmitDirectiveAMDGCNTarget() override; - void EmitDirectiveHSACodeObjectVersion(uint32_t Major, - uint32_t Minor) override; - - void EmitDirectiveHSACodeObjectISAV2(uint32_t Major, uint32_t Minor, - uint32_t Stepping, StringRef VendorName, - StringRef ArchName) override; - void EmitAMDKernelCodeT(const amd_kernel_code_t &Header) override; void EmitAMDGPUSymbolType(StringRef SymbolName, unsigned Type) override; @@ -217,9 +195,6 @@ public: /// \returns True on success, false on failure. bool EmitHSAMetadata(msgpack::Document &HSAMetadata, bool Strict) override; - /// \returns True on success, false on failure. - bool EmitHSAMetadata(const AMDGPU::HSAMD::Metadata &HSAMetadata) override; - /// \returns True on success, false on failure. bool EmitCodeEnd(const MCSubtargetInfo &STI) override; @@ -229,9 +204,7 @@ public: void EmitAmdhsaKernelDescriptor( const MCSubtargetInfo &STI, StringRef KernelName, const amdhsa::kernel_descriptor_t &KernelDescriptor, uint64_t NextVGPR, - uint64_t NextSGPR, bool ReserveVCC, bool ReserveFlatScr, - unsigned CodeObjectVersion) override; + uint64_t NextSGPR, bool ReserveVCC, bool ReserveFlatScr) override; }; - } #endif diff --git a/llvm/lib/Target/AMDGPU/MIMGInstructions.td b/llvm/lib/Target/AMDGPU/MIMGInstructions.td index 240366c8e7d..3c7cd61444f 100644 --- a/llvm/lib/Target/AMDGPU/MIMGInstructions.td +++ b/llvm/lib/Target/AMDGPU/MIMGInstructions.td @@ -1553,6 +1553,11 @@ defm IMAGE_ATOMIC_DEC : MIMG_Atomic_Renamed defm IMAGE_ATOMIC_FCMPSWAP : MIMG_Atomic , "image_atomic_fcmpswap", 1, 1>; defm IMAGE_ATOMIC_FMIN : MIMG_Atomic , "image_atomic_fmin", 0, 1>; defm IMAGE_ATOMIC_FMAX : MIMG_Atomic , "image_atomic_fmax", 0, 1>; +defm IMAGE_ATOMIC_PK_ADD_F16 : MIMG_Atomic , "image_atomic_pk_add_f16", 0, 1>; +defm IMAGE_ATOMIC_PK_ADD_BF16 : MIMG_Atomic , "image_atomic_pk_add_bf16", 0, 1>; +defm IMAGE_ATOMIC_ADD_FLT : MIMG_Atomic , "image_atomic_add_flt", 0, 1>; +defm IMAGE_ATOMIC_MIN_FLT : MIMG_Atomic , "image_atomic_min_num_flt", 0, 1, "image_atomic_min_flt">; +defm IMAGE_ATOMIC_MAX_FLT : MIMG_Atomic , "image_atomic_max_num_flt", 0, 1, "image_atomic_max_flt">; defm IMAGE_SAMPLE : MIMG_Sampler_WQM , AMDGPUSample>; let OtherPredicates = [HasExtendedImageInsts] in { diff --git a/llvm/lib/Target/AMDGPU/R600ISelLowering.cpp b/llvm/lib/Target/AMDGPU/R600ISelLowering.cpp index 674fd04f2fc..159b2d440b3 100644 --- a/llvm/lib/Target/AMDGPU/R600ISelLowering.cpp +++ b/llvm/lib/Target/AMDGPU/R600ISelLowering.cpp @@ -1619,8 +1619,7 @@ static SDValue ReorganizeVector(SelectionDAG &DAG, SDValue VectorEntry, for (unsigned i = 0; i < 4; i++) { RemapSwizzle[i] = i; if (NewBldVec[i].getOpcode() == ISD::EXTRACT_VECTOR_ELT) { - unsigned Idx = cast(NewBldVec[i].getOperand(1)) - ->getZExtValue(); + unsigned Idx = NewBldVec[i].getConstantOperandVal(1); if (i == Idx) isUnmovable[Idx] = true; } @@ -1628,8 +1627,7 @@ static SDValue ReorganizeVector(SelectionDAG &DAG, SDValue VectorEntry, for (unsigned i = 0; i < 4; i++) { if (NewBldVec[i].getOpcode() == ISD::EXTRACT_VECTOR_ELT) { - unsigned Idx = cast(NewBldVec[i].getOperand(1)) - ->getZExtValue(); + unsigned Idx = NewBldVec[i].getConstantOperandVal(1); if (isUnmovable[Idx]) continue; // Swap i and Idx @@ -2002,9 +2000,7 @@ bool R600TargetLowering::FoldOperand(SDNode *ParentNode, unsigned SrcIdx, if (RegisterSDNode *Reg = dyn_cast(ParentNode->getOperand(OtherSrcIdx))) { if (Reg->getReg() == R600::ALU_CONST) { - ConstantSDNode *Cst - = cast(ParentNode->getOperand(OtherSelIdx)); - Consts.push_back(Cst->getZExtValue()); + Consts.push_back(ParentNode->getConstantOperandVal(OtherSelIdx)); } } } @@ -2044,8 +2040,7 @@ bool R600TargetLowering::FoldOperand(SDNode *ParentNode, unsigned SrcIdx, ImmValue = FPC->getValueAPF().bitcastToAPInt().getZExtValue(); } } else { - ConstantSDNode *C = cast(Src.getOperand(0)); - uint64_t Value = C->getZExtValue(); + uint64_t Value = Src.getConstantOperandVal(0); if (Value == 0) { ImmReg = R600::ZERO; } else if (Value == 1) { diff --git a/llvm/lib/Target/AMDGPU/SIAnnotateControlFlow.cpp b/llvm/lib/Target/AMDGPU/SIAnnotateControlFlow.cpp index 932c0d6216c..c921e5a35d2 100644 --- a/llvm/lib/Target/AMDGPU/SIAnnotateControlFlow.cpp +++ b/llvm/lib/Target/AMDGPU/SIAnnotateControlFlow.cpp @@ -329,15 +329,16 @@ bool SIAnnotateControlFlow::closeControlFlow(BasicBlock *BB) { } Value *Exec = popSaved(); - Instruction *FirstInsertionPt = &*BB->getFirstInsertionPt(); + BasicBlock::iterator FirstInsertionPt = BB->getFirstInsertionPt(); if (!isa(Exec) && !isa(FirstInsertionPt)) { Instruction *ExecDef = cast(Exec); BasicBlock *DefBB = ExecDef->getParent(); if (!DT->dominates(DefBB, BB)) { // Split edge to make Def dominate Use - FirstInsertionPt = &*SplitEdge(DefBB, BB, DT, LI)->getFirstInsertionPt(); + FirstInsertionPt = SplitEdge(DefBB, BB, DT, LI)->getFirstInsertionPt(); } - IRBuilder<>(FirstInsertionPt).CreateCall(EndCf, {Exec}); + IRBuilder<>(FirstInsertionPt->getParent(), FirstInsertionPt) + .CreateCall(EndCf, {Exec}); } return true; diff --git a/llvm/lib/Target/AMDGPU/SIDefines.h b/llvm/lib/Target/AMDGPU/SIDefines.h index b291400a947..8ab66d4fd5b 100644 --- a/llvm/lib/Target/AMDGPU/SIDefines.h +++ b/llvm/lib/Target/AMDGPU/SIDefines.h @@ -400,6 +400,10 @@ enum CPol { TH_TYPE_STORE = 1 << 8, // TH_STORE policy TH_TYPE_ATOMIC = 1 << 9, // TH_ATOMIC policy TH_REAL_BYPASS = 1 << 10, // is TH=3 bypass policy or not + + // Volatile (used to preserve/signal operation volatility for buffer + // operations not a real instruction bit) + VOLATILE = 1 << 31, }; } // namespace CPol @@ -1172,11 +1176,13 @@ enum Type { TRAP = -2, WORKGROUP = -1 }; #define R_00B860_COMPUTE_TMPRING_SIZE 0x00B860 #define S_00B860_WAVESIZE_PreGFX11(x) (((x) & 0x1FFF) << 12) -#define S_00B860_WAVESIZE_GFX11Plus(x) (((x) & 0x7FFF) << 12) +#define S_00B860_WAVESIZE_GFX11(x) (((x) & 0x7FFF) << 12) +#define S_00B860_WAVESIZE_GFX12Plus(x) (((x) & 0x3FFFF) << 12) #define R_0286E8_SPI_TMPRING_SIZE 0x0286E8 #define S_0286E8_WAVESIZE_PreGFX11(x) (((x) & 0x1FFF) << 12) -#define S_0286E8_WAVESIZE_GFX11Plus(x) (((x) & 0x7FFF) << 12) +#define S_0286E8_WAVESIZE_GFX11(x) (((x) & 0x7FFF) << 12) +#define S_0286E8_WAVESIZE_GFX12Plus(x) (((x) & 0x3FFFF) << 12) #define R_028B54_VGT_SHADER_STAGES_EN 0x028B54 #define S_028B54_HS_W32_EN(x) (((x) & 0x1) << 21) diff --git a/llvm/lib/Target/AMDGPU/SIFoldOperands.cpp b/llvm/lib/Target/AMDGPU/SIFoldOperands.cpp index aa7639a0f18..2862a7787e7 100644 --- a/llvm/lib/Target/AMDGPU/SIFoldOperands.cpp +++ b/llvm/lib/Target/AMDGPU/SIFoldOperands.cpp @@ -1498,6 +1498,7 @@ const MachineOperand *SIFoldOperands::isClamp(const MachineInstr &MI) const { case AMDGPU::V_MAX_F16_t16_e64: case AMDGPU::V_MAX_F16_fake16_e64: case AMDGPU::V_MAX_F64_e64: + case AMDGPU::V_MAX_NUM_F64_e64: case AMDGPU::V_PK_MAX_F16: { if (!TII->getNamedOperand(MI, AMDGPU::OpName::clamp)->getImm()) return nullptr; @@ -1567,7 +1568,8 @@ bool SIFoldOperands::tryFoldClamp(MachineInstr &MI) { static int getOModValue(unsigned Opc, int64_t Val) { switch (Opc) { - case AMDGPU::V_MUL_F64_e64: { + case AMDGPU::V_MUL_F64_e64: + case AMDGPU::V_MUL_F64_pseudo_e64: { switch (Val) { case 0x3fe0000000000000: // 0.5 return SIOutMods::DIV2; @@ -1618,6 +1620,7 @@ SIFoldOperands::isOMod(const MachineInstr &MI) const { unsigned Op = MI.getOpcode(); switch (Op) { case AMDGPU::V_MUL_F64_e64: + case AMDGPU::V_MUL_F64_pseudo_e64: case AMDGPU::V_MUL_F32_e64: case AMDGPU::V_MUL_F16_t16_e64: case AMDGPU::V_MUL_F16_fake16_e64: @@ -1625,8 +1628,8 @@ SIFoldOperands::isOMod(const MachineInstr &MI) const { // If output denormals are enabled, omod is ignored. if ((Op == AMDGPU::V_MUL_F32_e64 && MFI->getMode().FP32Denormals.Output != DenormalMode::PreserveSign) || - ((Op == AMDGPU::V_MUL_F64_e64 || Op == AMDGPU::V_MUL_F16_e64 || - Op == AMDGPU::V_MUL_F16_t16_e64 || + ((Op == AMDGPU::V_MUL_F64_e64 || Op == AMDGPU::V_MUL_F64_pseudo_e64 || + Op == AMDGPU::V_MUL_F16_e64 || Op == AMDGPU::V_MUL_F16_t16_e64 || Op == AMDGPU::V_MUL_F16_fake16_e64) && MFI->getMode().FP64FP16Denormals.Output != DenormalMode::PreserveSign)) return std::pair(nullptr, SIOutMods::NONE); @@ -1655,6 +1658,7 @@ SIFoldOperands::isOMod(const MachineInstr &MI) const { return std::pair(RegOp, OMod); } case AMDGPU::V_ADD_F64_e64: + case AMDGPU::V_ADD_F64_pseudo_e64: case AMDGPU::V_ADD_F32_e64: case AMDGPU::V_ADD_F16_e64: case AMDGPU::V_ADD_F16_t16_e64: @@ -1662,8 +1666,8 @@ SIFoldOperands::isOMod(const MachineInstr &MI) const { // If output denormals are enabled, omod is ignored. if ((Op == AMDGPU::V_ADD_F32_e64 && MFI->getMode().FP32Denormals.Output != DenormalMode::PreserveSign) || - ((Op == AMDGPU::V_ADD_F64_e64 || Op == AMDGPU::V_ADD_F16_e64 || - Op == AMDGPU::V_ADD_F16_t16_e64 || + ((Op == AMDGPU::V_ADD_F64_e64 || Op == AMDGPU::V_ADD_F64_pseudo_e64 || + Op == AMDGPU::V_ADD_F16_e64 || Op == AMDGPU::V_ADD_F16_t16_e64 || Op == AMDGPU::V_ADD_F16_fake16_e64) && MFI->getMode().FP64FP16Denormals.Output != DenormalMode::PreserveSign)) return std::pair(nullptr, SIOutMods::NONE); diff --git a/llvm/lib/Target/AMDGPU/SIFrameLowering.cpp b/llvm/lib/Target/AMDGPU/SIFrameLowering.cpp index 0f89df14448..9d062eb156d 100644 --- a/llvm/lib/Target/AMDGPU/SIFrameLowering.cpp +++ b/llvm/lib/Target/AMDGPU/SIFrameLowering.cpp @@ -95,7 +95,8 @@ static void getVGPRSpillLaneOrTempRegister( TargetStackID::SGPRSpill); if (TRI->spillSGPRToVGPR() && - MFI->allocateSGPRSpillToVGPRLane(MF, FI, /* IsPrologEpilog */ true)) { + MFI->allocateSGPRSpillToVGPRLane(MF, FI, /*SpillToPhysVGPRLane=*/true, + /*IsPrologEpilog=*/true)) { // 2: There's no free lane to spill, and no free register to save the // SGPR, so we're forced to take another VGPR to use for the spill. MFI->addToPrologEpilogSGPRSpills( @@ -188,7 +189,7 @@ static void buildGitPtr(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, .addImm(MFI->getGITPtrHigh()) .addReg(TargetReg, RegState::ImplicitDefine); } else { - const MCInstrDesc &GetPC64 = TII->get(AMDGPU::S_GETPC_B64); + const MCInstrDesc &GetPC64 = TII->get(AMDGPU::S_GETPC_B64_pseudo); BuildMI(MBB, I, DL, GetPC64, TargetReg); } Register GitPtrLo = MFI->getGITPtrLoReg(*MF); @@ -1560,6 +1561,8 @@ void SIFrameLowering::determineCalleeSaves(MachineFunction &MF, if (MFI->isChainFunction() && !MF.getFrameInfo().hasTailCall()) return; + MFI->shiftSpillPhysVGPRsToLowestRange(MF); + TargetFrameLowering::determineCalleeSaves(MF, SavedVGPRs, RS); if (MFI->isEntryFunction()) return; diff --git a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp index 5a9222e9158..cf947dccafa 100644 --- a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp +++ b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp @@ -855,7 +855,7 @@ SITargetLowering::SITargetLowering(const TargetMachine &TM, setOperationAction(ISD::INTRINSIC_WO_CHAIN, {MVT::Other, MVT::f32, MVT::v4f32, MVT::i16, MVT::f16, - MVT::v2i16, MVT::v2f16, MVT::i128}, + MVT::v2i16, MVT::v2f16, MVT::i128, MVT::i8}, Custom); setOperationAction(ISD::INTRINSIC_W_CHAIN, @@ -1183,6 +1183,9 @@ bool SITargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info, Info.ptrVal = RsrcArg; } + auto *Aux = cast(CI.getArgOperand(CI.arg_size() - 1)); + if (Aux->getZExtValue() & AMDGPU::CPol::VOLATILE) + Info.flags |= MachineMemOperand::MOVolatile; Info.flags |= MachineMemOperand::MODereferenceable; if (ME.onlyReadsMemory()) { unsigned MaxNumLanes = 4; @@ -1333,6 +1336,7 @@ bool SITargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info, case Intrinsic::amdgcn_flat_atomic_fmin_num: case Intrinsic::amdgcn_flat_atomic_fmax_num: case Intrinsic::amdgcn_global_atomic_fadd_v2bf16: + case Intrinsic::amdgcn_atomic_cond_sub_u32: case Intrinsic::amdgcn_flat_atomic_fadd_v2bf16: { Info.opc = ISD::INTRINSIC_W_CHAIN; Info.memVT = MVT::getVT(CI.getType()); @@ -1344,6 +1348,14 @@ bool SITargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info, MachineMemOperand::MOVolatile; return true; } + case Intrinsic::amdgcn_global_load_tr: { + Info.opc = ISD::INTRINSIC_W_CHAIN; + Info.memVT = MVT::getVT(CI.getType()); + Info.ptrVal = CI.getOperand(0); + Info.align.reset(); + Info.flags |= MachineMemOperand::MOLoad; + return true; + } case Intrinsic::amdgcn_ds_gws_init: case Intrinsic::amdgcn_ds_gws_barrier: case Intrinsic::amdgcn_ds_gws_sema_v: @@ -1403,6 +1415,7 @@ bool SITargetLowering::getAddrModeArguments(IntrinsicInst *II, SmallVectorImpl &Ops, Type *&AccessTy) const { switch (II->getIntrinsicID()) { + case Intrinsic::amdgcn_global_load_tr: case Intrinsic::amdgcn_ds_ordered_add: case Intrinsic::amdgcn_ds_ordered_swap: case Intrinsic::amdgcn_ds_append: @@ -1525,6 +1538,7 @@ bool SITargetLowering::isLegalAddressingMode(const DataLayout &DL, // will use a MUBUF load. // FIXME?: We also need to do this if unaligned, but we don't know the // alignment here. + // TODO: Update this for GFX12 which does have scalar sub-dword loads. if (Ty->isSized() && DL.getTypeStoreSize(Ty) < 4) return isLegalGlobalAddressingMode(AM); @@ -2297,7 +2311,7 @@ void SITargetLowering::allocateSpecialInputSGPRs( const Module *M = MF.getFunction().getParent(); if (UserSGPRInfo.hasQueuePtr() && - AMDGPU::getCodeObjectVersion(*M) < AMDGPU::AMDHSA_COV5) + AMDGPU::getAMDHSACodeObjectVersion(*M) < AMDGPU::AMDHSA_COV5) allocateSGPR64Input(CCInfo, ArgInfo.QueuePtr); // Implicit arg ptr takes the place of the kernarg segment pointer. This is a @@ -2350,7 +2364,7 @@ void SITargetLowering::allocateHSAUserSGPRs(CCState &CCInfo, const Module *M = MF.getFunction().getParent(); if (UserSGPRInfo.hasQueuePtr() && - AMDGPU::getCodeObjectVersion(*M) < AMDGPU::AMDHSA_COV5) { + AMDGPU::getAMDHSACodeObjectVersion(*M) < AMDGPU::AMDHSA_COV5) { Register QueuePtrReg = Info.addQueuePtr(TRI); MF.addLiveIn(QueuePtrReg, &AMDGPU::SGPR_64RegClass); CCInfo.AllocateReg(QueuePtrReg); @@ -2779,15 +2793,16 @@ SDValue SITargetLowering::LowerFormalArguments( } else if (!IsGraphics) { // For the fixed ABI, pass workitem IDs in the last argument register. allocateSpecialInputVGPRsFixed(CCInfo, MF, *TRI, *Info); + + // FIXME: Sink this into allocateSpecialInputSGPRs + if (!Subtarget->enableFlatScratch()) + CCInfo.AllocateReg(Info->getScratchRSrcReg()); + + allocateSpecialInputSGPRs(CCInfo, MF, *TRI, *Info); } if (!IsKernel) { CCAssignFn *AssignFn = CCAssignFnForCall(CallConv, isVarArg); - if (!IsGraphics && !Subtarget->enableFlatScratch()) { - CCInfo.AllocateRegBlock(ArrayRef{AMDGPU::SGPR0, AMDGPU::SGPR1, - AMDGPU::SGPR2, AMDGPU::SGPR3}, - 4); - } CCInfo.AnalyzeFormalArguments(Splits, AssignFn); } @@ -2987,13 +3002,8 @@ SDValue SITargetLowering::LowerFormalArguments( } // Start adding system SGPRs. - if (IsEntryFunc) { + if (IsEntryFunc) allocateSystemSGPRs(CCInfo, MF, *Info, CallConv, IsGraphics); - } else { - CCInfo.AllocateReg(Info->getScratchRSrcReg()); - if (!IsGraphics) - allocateSpecialInputSGPRs(CCInfo, MF, *TRI, *Info); - } auto &ArgUsageInfo = DAG.getPass()->getAnalysis(); @@ -5720,7 +5730,7 @@ SDValue SITargetLowering::lowerIntrinsicLoad(MemSDNode *M, bool IsFormat, // Handle BUFFER_LOAD_BYTE/UBYTE/SHORT/USHORT overloaded intrinsics if (!IsD16 && !LoadVT.isVector() && EltType.getSizeInBits() < 32) - return handleByteShortBufferLoads(DAG, LoadVT, DL, Ops, M); + return handleByteShortBufferLoads(DAG, LoadVT, DL, Ops, M->getMemOperand()); if (isTypeLegal(LoadVT)) { return getMemIntrinsicNode(Opc, DL, M->getVTList(), Ops, IntVT, @@ -5739,8 +5749,7 @@ SDValue SITargetLowering::lowerIntrinsicLoad(MemSDNode *M, bool IsFormat, static SDValue lowerICMPIntrinsic(const SITargetLowering &TLI, SDNode *N, SelectionDAG &DAG) { EVT VT = N->getValueType(0); - const auto *CD = cast(N->getOperand(3)); - unsigned CondCode = CD->getZExtValue(); + unsigned CondCode = N->getConstantOperandVal(3); if (!ICmpInst::isIntPredicate(static_cast(CondCode))) return DAG.getUNDEF(VT); @@ -5774,9 +5783,8 @@ static SDValue lowerICMPIntrinsic(const SITargetLowering &TLI, static SDValue lowerFCMPIntrinsic(const SITargetLowering &TLI, SDNode *N, SelectionDAG &DAG) { EVT VT = N->getValueType(0); - const auto *CD = cast(N->getOperand(3)); - unsigned CondCode = CD->getZExtValue(); + unsigned CondCode = N->getConstantOperandVal(3); if (!FCmpInst::isFPPredicate(static_cast(CondCode))) return DAG.getUNDEF(VT); @@ -5894,6 +5902,55 @@ void SITargetLowering::ReplaceNodeResults(SDNode *N, } return; } + case Intrinsic::amdgcn_s_buffer_load: { + // Lower llvm.amdgcn.s.buffer.load.(i8, u8) intrinsics. First, we generate + // s_buffer_load_u8 for signed and unsigned load instructions. Next, DAG + // combiner tries to merge the s_buffer_load_u8 with a sext instruction + // (performSignExtendInRegCombine()) and it replaces s_buffer_load_u8 with + // s_buffer_load_i8. + if (!Subtarget->hasScalarSubwordLoads()) + return; + SDValue Op = SDValue(N, 0); + SDValue Rsrc = Op.getOperand(1); + SDValue Offset = Op.getOperand(2); + SDValue CachePolicy = Op.getOperand(3); + EVT VT = Op.getValueType(); + assert(VT == MVT::i8 && "Expected 8-bit s_buffer_load intrinsics.\n"); + SDLoc DL(Op); + MachineFunction &MF = DAG.getMachineFunction(); + const DataLayout &DataLayout = DAG.getDataLayout(); + Align Alignment = + DataLayout.getABITypeAlign(VT.getTypeForEVT(*DAG.getContext())); + MachineMemOperand *MMO = MF.getMachineMemOperand( + MachinePointerInfo(), + MachineMemOperand::MOLoad | MachineMemOperand::MODereferenceable | + MachineMemOperand::MOInvariant, + VT.getStoreSize(), Alignment); + SDValue LoadVal; + if (!Offset->isDivergent()) { + SDValue Ops[] = {Rsrc, // source register + Offset, CachePolicy}; + SDValue BufferLoad = + DAG.getMemIntrinsicNode(AMDGPUISD::SBUFFER_LOAD_UBYTE, DL, + DAG.getVTList(MVT::i32), Ops, VT, MMO); + LoadVal = DAG.getNode(ISD::TRUNCATE, DL, VT, BufferLoad); + } else { + SDValue Ops[] = { + DAG.getEntryNode(), // Chain + Rsrc, // rsrc + DAG.getConstant(0, DL, MVT::i32), // vindex + {}, // voffset + {}, // soffset + {}, // offset + CachePolicy, // cachepolicy + DAG.getTargetConstant(0, DL, MVT::i1), // idxen + }; + setBufferOffsets(Offset, DAG, &Ops[3], Align(4)); + LoadVal = handleByteShortBufferLoads(DAG, VT, DL, Ops, MMO); + } + Results.push_back(LoadVal); + return; + } } break; } @@ -6390,7 +6447,7 @@ SDValue SITargetLowering::lowerTrapHsaQueuePtr( SDValue QueuePtr; // For code object version 5, QueuePtr is passed through implicit kernarg. const Module *M = DAG.getMachineFunction().getFunction().getParent(); - if (AMDGPU::getCodeObjectVersion(*M) >= AMDGPU::AMDHSA_COV5) { + if (AMDGPU::getAMDHSACodeObjectVersion(*M) >= AMDGPU::AMDHSA_COV5) { QueuePtr = loadImplicitKernelArgument(DAG, MVT::i64, SL, Align(8), QUEUE_PTR); } else { @@ -6494,7 +6551,7 @@ SDValue SITargetLowering::getSegmentAperture(unsigned AS, const SDLoc &DL, // For code object version 5, private_base and shared_base are passed through // implicit kernargs. const Module *M = DAG.getMachineFunction().getFunction().getParent(); - if (AMDGPU::getCodeObjectVersion(*M) >= AMDGPU::AMDHSA_COV5) { + if (AMDGPU::getAMDHSACodeObjectVersion(*M) >= AMDGPU::AMDHSA_COV5) { ImplicitParameter Param = (AS == AMDGPUAS::LOCAL_ADDRESS) ? SHARED_BASE : PRIVATE_BASE; return loadImplicitKernelArgument(DAG, MVT::i32, DL, Align(4), Param); @@ -7248,17 +7305,17 @@ static SDValue padEltsToUndef(SelectionDAG &DAG, const SDLoc &DL, EVT CastVT, // Re-construct the required return value for a image load intrinsic. // This is more complicated due to the optional use TexFailCtrl which means the required // return type is an aggregate -static SDValue constructRetValue(SelectionDAG &DAG, - MachineSDNode *Result, - ArrayRef ResultTypes, - bool IsTexFail, bool Unpacked, bool IsD16, - int DMaskPop, int NumVDataDwords, +static SDValue constructRetValue(SelectionDAG &DAG, MachineSDNode *Result, + ArrayRef ResultTypes, bool IsTexFail, + bool Unpacked, bool IsD16, int DMaskPop, + int NumVDataDwords, bool IsAtomicPacked16Bit, const SDLoc &DL) { // Determine the required return type. This is the same regardless of IsTexFail flag EVT ReqRetVT = ResultTypes[0]; int ReqRetNumElts = ReqRetVT.isVector() ? ReqRetVT.getVectorNumElements() : 1; - int NumDataDwords = (!IsD16 || (IsD16 && Unpacked)) ? - ReqRetNumElts : (ReqRetNumElts + 1) / 2; + int NumDataDwords = ((IsD16 && !Unpacked) || IsAtomicPacked16Bit) + ? (ReqRetNumElts + 1) / 2 + : ReqRetNumElts; int MaskPopDwords = (!IsD16 || (IsD16 && Unpacked)) ? DMaskPop : (DMaskPop + 1) / 2; @@ -7283,7 +7340,7 @@ static SDValue constructRetValue(SelectionDAG &DAG, } } - if (DataDwordVT.isVector()) + if (DataDwordVT.isVector() && !IsAtomicPacked16Bit) Data = padEltsToUndef(DAG, DL, DataDwordVT, Data, NumDataDwords - MaskPopDwords); @@ -7390,6 +7447,7 @@ SDValue SITargetLowering::lowerImage(SDValue Op, SDValue VData; int NumVDataDwords; bool AdjustRetType = false; + bool IsAtomicPacked16Bit = false; // Offset of intrinsic arguments const unsigned ArgOffset = WithChain ? 2 : 1; @@ -7400,6 +7458,10 @@ SDValue SITargetLowering::lowerImage(SDValue Op, if (BaseOpcode->Atomic) { VData = Op.getOperand(2); + IsAtomicPacked16Bit = + (Intr->BaseOpcode == AMDGPU::IMAGE_ATOMIC_PK_ADD_F16 || + Intr->BaseOpcode == AMDGPU::IMAGE_ATOMIC_PK_ADD_BF16); + bool Is64Bit = VData.getValueSizeInBits() == 64; if (BaseOpcode->AtomicX2) { SDValue VData2 = Op.getOperand(3); @@ -7416,9 +7478,7 @@ SDValue SITargetLowering::lowerImage(SDValue Op, NumVDataDwords = Is64Bit ? 2 : 1; } } else { - auto *DMaskConst = - cast(Op.getOperand(ArgOffset + Intr->DMaskIndex)); - DMask = DMaskConst->getZExtValue(); + DMask = Op->getConstantOperandVal(ArgOffset + Intr->DMaskIndex); DMaskLanes = BaseOpcode->Gather4 ? 4 : llvm::popcount(DMask); if (BaseOpcode->Store) { @@ -7639,7 +7699,8 @@ SDValue SITargetLowering::lowerImage(SDValue Op, Op.getOperand(ArgOffset + Intr->CachePolicyIndex))->getZExtValue(); if (BaseOpcode->Atomic) CPol |= AMDGPU::CPol::GLC; // TODO no-return optimization - if (CPol & ~(IsGFX12Plus ? AMDGPU::CPol::ALL : AMDGPU::CPol::ALL_pregfx12)) + if (CPol & ~((IsGFX12Plus ? AMDGPU::CPol::ALL : AMDGPU::CPol::ALL_pregfx12) | + AMDGPU::CPol::VOLATILE)) return Op; SmallVector Ops; @@ -7729,10 +7790,9 @@ SDValue SITargetLowering::lowerImage(SDValue Op, } if (BaseOpcode->Store) return SDValue(NewNode, 0); - return constructRetValue(DAG, NewNode, - OrigResultTypes, IsTexFail, - Subtarget->hasUnpackedD16VMem(), IsD16, - DMaskLanes, NumVDataDwords, DL); + return constructRetValue(DAG, NewNode, OrigResultTypes, IsTexFail, + Subtarget->hasUnpackedD16VMem(), IsD16, DMaskLanes, + NumVDataDwords, IsAtomicPacked16Bit, DL); } SDValue SITargetLowering::lowerSBuffer(EVT VT, SDLoc DL, SDValue Rsrc, @@ -7751,11 +7811,18 @@ SDValue SITargetLowering::lowerSBuffer(EVT VT, SDLoc DL, SDValue Rsrc, VT.getStoreSize(), Alignment); if (!Offset->isDivergent()) { - SDValue Ops[] = { - Rsrc, - Offset, // Offset - CachePolicy - }; + SDValue Ops[] = {Rsrc, Offset, CachePolicy}; + + // Lower llvm.amdgcn.s.buffer.load.{i16, u16} intrinsics. Initially, the + // s_buffer_load_u16 instruction is emitted for both signed and unsigned + // loads. Later, DAG combiner tries to combine s_buffer_load_u16 with sext + // and generates s_buffer_load_i16 (performSignExtendInRegCombine). + if (VT == MVT::i16 && Subtarget->hasScalarSubwordLoads()) { + SDValue BufferLoad = + DAG.getMemIntrinsicNode(AMDGPUISD::SBUFFER_LOAD_USHORT, DL, + DAG.getVTList(MVT::i32), Ops, VT, MMO); + return DAG.getNode(ISD::TRUNCATE, DL, VT, BufferLoad); + } // Widen vec3 load to vec4. if (VT.isVector() && VT.getVectorNumElements() == 3 && @@ -7776,6 +7843,21 @@ SDValue SITargetLowering::lowerSBuffer(EVT VT, SDLoc DL, SDValue Rsrc, // We have a divergent offset. Emit a MUBUF buffer load instead. We can // assume that the buffer is unswizzled. + SDValue Ops[] = { + DAG.getEntryNode(), // Chain + Rsrc, // rsrc + DAG.getConstant(0, DL, MVT::i32), // vindex + {}, // voffset + {}, // soffset + {}, // offset + CachePolicy, // cachepolicy + DAG.getTargetConstant(0, DL, MVT::i1), // idxen + }; + if (VT == MVT::i16 && Subtarget->hasScalarSubwordLoads()) { + setBufferOffsets(Offset, DAG, &Ops[3], Align(4)); + return handleByteShortBufferLoads(DAG, VT, DL, Ops, MMO); + } + SmallVector Loads; unsigned NumLoads = 1; MVT LoadVT = VT.getSimpleVT(); @@ -7789,16 +7871,6 @@ SDValue SITargetLowering::lowerSBuffer(EVT VT, SDLoc DL, SDValue Rsrc, } SDVTList VTList = DAG.getVTList({LoadVT, MVT::Glue}); - SDValue Ops[] = { - DAG.getEntryNode(), // Chain - Rsrc, // rsrc - DAG.getConstant(0, DL, MVT::i32), // vindex - {}, // voffset - {}, // soffset - {}, // offset - CachePolicy, // cachepolicy - DAG.getTargetConstant(0, DL, MVT::i1), // idxen - }; // Use the alignment to ensure that the required offsets will fit into the // immediate offsets. @@ -8005,6 +8077,8 @@ SDValue SITargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op, SDLoc(Op), MVT::i32); case Intrinsic::amdgcn_s_buffer_load: { unsigned CPol = Op.getConstantOperandVal(3); + // s_buffer_load, because of how it's optimized, can't be volatile + // so reject ones with the volatile bit set. if (CPol & ~((Subtarget->getGeneration() >= AMDGPUSubtarget::GFX12) ? AMDGPU::CPol::ALL : AMDGPU::CPol::ALL_pregfx12)) @@ -8374,9 +8448,9 @@ SDValue SITargetLowering::LowerINTRINSIC_W_CHAIN(SDValue Op, M, DAG, Ops); // Handle BUFFER_LOAD_BYTE/UBYTE/SHORT/USHORT overloaded intrinsics - if (LoadVT.getScalarType() == MVT::i8 || - LoadVT.getScalarType() == MVT::i16) - return handleByteShortBufferLoads(DAG, LoadVT, DL, Ops, M); + if (LoadVT.getScalarType() == MVT::i8 || LoadVT.getScalarType() == MVT::i16) + return handleByteShortBufferLoads(DAG, LoadVT, DL, Ops, + M->getMemOperand()); return getMemIntrinsicNode(Opc, DL, Op->getVTList(), Ops, IntVT, M->getMemOperand(), DAG); @@ -8592,9 +8666,15 @@ SDValue SITargetLowering::LowerINTRINSIC_W_CHAIN(SDValue Op, case Intrinsic::amdgcn_raw_buffer_atomic_fadd: case Intrinsic::amdgcn_raw_ptr_buffer_atomic_fadd: return lowerRawBufferAtomicIntrin(Op, DAG, AMDGPUISD::BUFFER_ATOMIC_FADD); + case Intrinsic::amdgcn_raw_buffer_atomic_fadd_v2bf16: + return lowerRawBufferAtomicIntrin(Op, DAG, + AMDGPUISD::BUFFER_ATOMIC_FADD_BF16); case Intrinsic::amdgcn_struct_buffer_atomic_fadd: case Intrinsic::amdgcn_struct_ptr_buffer_atomic_fadd: return lowerStructBufferAtomicIntrin(Op, DAG, AMDGPUISD::BUFFER_ATOMIC_FADD); + case Intrinsic::amdgcn_struct_buffer_atomic_fadd_v2bf16: + return lowerStructBufferAtomicIntrin(Op, DAG, + AMDGPUISD::BUFFER_ATOMIC_FADD_BF16); case Intrinsic::amdgcn_raw_buffer_atomic_fmin: case Intrinsic::amdgcn_raw_ptr_buffer_atomic_fmin: return lowerRawBufferAtomicIntrin(Op, DAG, AMDGPUISD::BUFFER_ATOMIC_FMIN); @@ -8643,6 +8723,9 @@ SDValue SITargetLowering::LowerINTRINSIC_W_CHAIN(SDValue Op, case Intrinsic::amdgcn_raw_buffer_atomic_dec: case Intrinsic::amdgcn_raw_ptr_buffer_atomic_dec: return lowerRawBufferAtomicIntrin(Op, DAG, AMDGPUISD::BUFFER_ATOMIC_DEC); + case Intrinsic::amdgcn_raw_buffer_atomic_cond_sub_u32: + return lowerRawBufferAtomicIntrin(Op, DAG, + AMDGPUISD::BUFFER_ATOMIC_COND_SUB_U32); case Intrinsic::amdgcn_struct_buffer_atomic_swap: case Intrinsic::amdgcn_struct_ptr_buffer_atomic_swap: return lowerStructBufferAtomicIntrin(Op, DAG, @@ -8684,6 +8767,9 @@ SDValue SITargetLowering::LowerINTRINSIC_W_CHAIN(SDValue Op, case Intrinsic::amdgcn_struct_buffer_atomic_dec: case Intrinsic::amdgcn_struct_ptr_buffer_atomic_dec: return lowerStructBufferAtomicIntrin(Op, DAG, AMDGPUISD::BUFFER_ATOMIC_DEC); + case Intrinsic::amdgcn_struct_buffer_atomic_cond_sub_u32: + return lowerStructBufferAtomicIntrin(Op, DAG, + AMDGPUISD::BUFFER_ATOMIC_COND_SUB_U32); case Intrinsic::amdgcn_buffer_atomic_cmpswap: { unsigned Slc = Op.getConstantOperandVal(7); @@ -9376,6 +9462,7 @@ SDValue SITargetLowering::LowerINTRINSIC_VOID(SDValue Op, case Intrinsic::amdgcn_raw_ptr_buffer_load_lds: case Intrinsic::amdgcn_struct_buffer_load_lds: case Intrinsic::amdgcn_struct_ptr_buffer_load_lds: { + assert(!AMDGPU::isGFX12Plus(*Subtarget)); unsigned Opc; bool HasVIndex = IntrinsicID == Intrinsic::amdgcn_struct_buffer_load_lds || @@ -9428,8 +9515,8 @@ SDValue SITargetLowering::LowerINTRINSIC_VOID(SDValue Op, unsigned Aux = Op.getConstantOperandVal(8 + OpOffset); Ops.push_back( DAG.getTargetConstant(Aux & AMDGPU::CPol::ALL, DL, MVT::i8)); // cpol - Ops.push_back( - DAG.getTargetConstant((Aux >> 3) & 1, DL, MVT::i8)); // swz + Ops.push_back(DAG.getTargetConstant( + Aux & AMDGPU::CPol::SWZ_pregfx12 ? 1 : 0, DL, MVT::i8)); // swz Ops.push_back(M0Val.getValue(0)); // Chain Ops.push_back(M0Val.getValue(1)); // Glue @@ -9766,18 +9853,17 @@ SDValue SITargetLowering::lowerPointerAsRsrcIntrin(SDNode *Op, } // Handle 8 bit and 16 bit buffer loads -SDValue SITargetLowering::handleByteShortBufferLoads(SelectionDAG &DAG, - EVT LoadVT, SDLoc DL, - ArrayRef Ops, - MemSDNode *M) const { +SDValue +SITargetLowering::handleByteShortBufferLoads(SelectionDAG &DAG, EVT LoadVT, + SDLoc DL, ArrayRef Ops, + MachineMemOperand *MMO) const { EVT IntVT = LoadVT.changeTypeToInteger(); unsigned Opc = (LoadVT.getScalarType() == MVT::i8) ? AMDGPUISD::BUFFER_LOAD_UBYTE : AMDGPUISD::BUFFER_LOAD_USHORT; SDVTList ResList = DAG.getVTList(MVT::i32, MVT::Other); - SDValue BufferLoad = DAG.getMemIntrinsicNode(Opc, DL, ResList, - Ops, IntVT, - M->getMemOperand()); + SDValue BufferLoad = + DAG.getMemIntrinsicNode(Opc, DL, ResList, Ops, IntVT, MMO); SDValue LoadVal = DAG.getNode(ISD::TRUNCATE, DL, IntVT, BufferLoad); LoadVal = DAG.getNode(ISD::BITCAST, DL, LoadVT, LoadVal); @@ -9821,6 +9907,8 @@ static SDValue getLoadExtOrTrunc(SelectionDAG &DAG, llvm_unreachable("invalid ext type"); } +// Try to turn 8 and 16-bit scalar loads into SMEM eligible 32-bit loads. +// TODO: Skip this on GFX12 which does have scalar sub-dword loads. SDValue SITargetLowering::widenLoad(LoadSDNode *Ld, DAGCombinerInfo &DCI) const { SelectionDAG &DAG = DCI.DAG; if (Ld->getAlign() < Align(4) || Ld->isDivergent()) @@ -12058,17 +12146,42 @@ SDValue SITargetLowering::performZeroExtendCombine(SDNode *N, return SDValue(); } -SDValue SITargetLowering::performSignExtendInRegCombine(SDNode *N, - DAGCombinerInfo &DCI) - const { +SDValue +SITargetLowering::performSignExtendInRegCombine(SDNode *N, + DAGCombinerInfo &DCI) const { SDValue Src = N->getOperand(0); auto *VTSign = cast(N->getOperand(1)); - if (((Src.getOpcode() == AMDGPUISD::BUFFER_LOAD_UBYTE && - VTSign->getVT() == MVT::i8) || - (Src.getOpcode() == AMDGPUISD::BUFFER_LOAD_USHORT && - VTSign->getVT() == MVT::i16)) && - Src.hasOneUse()) { + // Combine s_buffer_load_u8 or s_buffer_load_u16 with sext and replace them + // with s_buffer_load_i8 and s_buffer_load_i16 respectively. + if (((Src.getOpcode() == AMDGPUISD::SBUFFER_LOAD_UBYTE && + VTSign->getVT() == MVT::i8) || + (Src.getOpcode() == AMDGPUISD::SBUFFER_LOAD_USHORT && + VTSign->getVT() == MVT::i16))) { + assert(Subtarget->hasScalarSubwordLoads() && + "s_buffer_load_{u8, i8} are supported " + "in GFX12 (or newer) architectures."); + EVT VT = Src.getValueType(); + unsigned Opc = (Src.getOpcode() == AMDGPUISD::SBUFFER_LOAD_UBYTE) + ? AMDGPUISD::SBUFFER_LOAD_BYTE + : AMDGPUISD::SBUFFER_LOAD_SHORT; + SDLoc DL(N); + SDVTList ResList = DCI.DAG.getVTList(MVT::i32); + SDValue Ops[] = { + Src.getOperand(0), // source register + Src.getOperand(1), // offset + Src.getOperand(2) // cachePolicy + }; + auto *M = cast(Src); + SDValue BufferLoad = DCI.DAG.getMemIntrinsicNode( + Opc, DL, ResList, Ops, M->getMemoryVT(), M->getMemOperand()); + SDValue LoadVal = DCI.DAG.getNode(ISD::TRUNCATE, DL, VT, BufferLoad); + return LoadVal; + } else if (((Src.getOpcode() == AMDGPUISD::BUFFER_LOAD_UBYTE && + VTSign->getVT() == MVT::i8) || + (Src.getOpcode() == AMDGPUISD::BUFFER_LOAD_USHORT && + VTSign->getVT() == MVT::i16)) && + Src.hasOneUse()) { auto *M = cast(Src); SDValue Ops[] = { Src.getOperand(0), // Chain @@ -14283,8 +14396,8 @@ SDValue SITargetLowering::PerformDAGCombine(SDNode *N, case ISD::FP_ROUND: return performFPRoundCombine(N, DCI); case ISD::LOAD: { - if (SDValue Widended = widenLoad(cast(N), DCI)) - return Widended; + if (SDValue Widened = widenLoad(cast(N), DCI)) + return Widened; [[fallthrough]]; } default: { @@ -15483,6 +15596,7 @@ bool SITargetLowering::isSDNodeSourceOfDivergence(const SDNode *N, case AMDGPUISD::BUFFER_ATOMIC_CMPSWAP: case AMDGPUISD::BUFFER_ATOMIC_CSUB: case AMDGPUISD::BUFFER_ATOMIC_FADD: + case AMDGPUISD::BUFFER_ATOMIC_FADD_BF16: case AMDGPUISD::BUFFER_ATOMIC_FMIN: case AMDGPUISD::BUFFER_ATOMIC_FMAX: // Target-specific read-modify-write atomics are sources of divergence. diff --git a/llvm/lib/Target/AMDGPU/SIISelLowering.h b/llvm/lib/Target/AMDGPU/SIISelLowering.h index 92b38ebade6..d66ba0b59ba 100644 --- a/llvm/lib/Target/AMDGPU/SIISelLowering.h +++ b/llvm/lib/Target/AMDGPU/SIISelLowering.h @@ -273,7 +273,8 @@ private: // Handle 8 bit and 16 bit buffer loads SDValue handleByteShortBufferLoads(SelectionDAG &DAG, EVT LoadVT, SDLoc DL, - ArrayRef Ops, MemSDNode *M) const; + ArrayRef Ops, + MachineMemOperand *MMO) const; // Handle 8 bit and 16 bit buffer stores SDValue handleByteShortBufferStores(SelectionDAG &DAG, EVT VDataType, diff --git a/llvm/lib/Target/AMDGPU/SIInsertWaitcnts.cpp b/llvm/lib/Target/AMDGPU/SIInsertWaitcnts.cpp index 1f480c24815..6ecb1c8bf6e 100644 --- a/llvm/lib/Target/AMDGPU/SIInsertWaitcnts.cpp +++ b/llvm/lib/Target/AMDGPU/SIInsertWaitcnts.cpp @@ -31,6 +31,7 @@ #include "llvm/ADT/MapVector.h" #include "llvm/ADT/PostOrderIterator.h" #include "llvm/ADT/Sequence.h" +#include "llvm/Analysis/AliasAnalysis.h" #include "llvm/CodeGen/MachineLoopInfo.h" #include "llvm/CodeGen/MachinePostDominators.h" #include "llvm/InitializePasses.h" @@ -57,7 +58,18 @@ namespace { // associated with the operand. Used for determining whether // s_waitcnt instruction needs to be emitted. -enum InstCounterType { VM_CNT = 0, LGKM_CNT, EXP_CNT, VS_CNT, NUM_INST_CNTS }; +enum InstCounterType { + LOAD_CNT = 0, // VMcnt prior to gfx12. + DS_CNT, // LKGMcnt prior to gfx12. + EXP_CNT, // + STORE_CNT, // VScnt in gfx10/gfx11. + NUM_NORMAL_INST_CNTS, + SAMPLE_CNT = NUM_NORMAL_INST_CNTS, // gfx12+ only. + BVH_CNT, // gfx12+ only. + KM_CNT, // gfx12+ only. + NUM_EXTENDED_INST_CNTS, + NUM_INST_CNTS = NUM_EXTENDED_INST_CNTS +}; } // namespace namespace llvm { @@ -67,15 +79,23 @@ template <> struct enum_iteration_traits { } // namespace llvm namespace { -auto inst_counter_types() { return enum_seq(VM_CNT, NUM_INST_CNTS); } +// Return an iterator over all counters between LOAD_CNT (the first counter) +// and \c MaxCounter (exclusive, default value yields an enumeration over +// all counters). +auto inst_counter_types(InstCounterType MaxCounter = NUM_INST_CNTS) { + return enum_seq(LOAD_CNT, MaxCounter); +} using RegInterval = std::pair; struct HardwareLimits { - unsigned VmcntMax; + unsigned LoadcntMax; // Corresponds to VMcnt prior to gfx12. unsigned ExpcntMax; - unsigned LgkmcntMax; - unsigned VscntMax; + unsigned DscntMax; // Corresponds to LGKMcnt prior to gfx12. + unsigned StorecntMax; // Corresponds to VScnt in gfx10/gfx11. + unsigned SamplecntMax; // gfx12+ only. + unsigned BvhcntMax; // gfx12+ only. + unsigned KmcntMax; // gfx12+ only. }; struct RegisterEncoding { @@ -86,31 +106,25 @@ struct RegisterEncoding { }; enum WaitEventType { - VMEM_ACCESS, // vector-memory read & write - VMEM_READ_ACCESS, // vector-memory read - VMEM_WRITE_ACCESS, // vector-memory write that is not scratch - SCRATCH_WRITE_ACCESS, // vector-memory write that may be scratch - LDS_ACCESS, // lds read & write - GDS_ACCESS, // gds read & write - SQ_MESSAGE, // send message - SMEM_ACCESS, // scalar-memory read & write - EXP_GPR_LOCK, // export holding on its data src - GDS_GPR_LOCK, // GDS holding on its data and addr src - EXP_POS_ACCESS, // write to export position - EXP_PARAM_ACCESS, // write to export parameter - VMW_GPR_LOCK, // vector-memory write holding on its data src - EXP_LDS_ACCESS, // read by ldsdir counting as export + VMEM_ACCESS, // vector-memory read & write + VMEM_READ_ACCESS, // vector-memory read + VMEM_SAMPLER_READ_ACCESS, // vector-memory SAMPLER read (gfx12+ only) + VMEM_BVH_READ_ACCESS, // vector-memory BVH read (gfx12+ only) + VMEM_WRITE_ACCESS, // vector-memory write that is not scratch + SCRATCH_WRITE_ACCESS, // vector-memory write that may be scratch + LDS_ACCESS, // lds read & write + GDS_ACCESS, // gds read & write + SQ_MESSAGE, // send message + SMEM_ACCESS, // scalar-memory read & write + EXP_GPR_LOCK, // export holding on its data src + GDS_GPR_LOCK, // GDS holding on its data and addr src + EXP_POS_ACCESS, // write to export position + EXP_PARAM_ACCESS, // write to export parameter + VMW_GPR_LOCK, // vector-memory write holding on its data src + EXP_LDS_ACCESS, // read by ldsdir counting as export NUM_WAIT_EVENTS, }; -static const unsigned WaitEventMaskForInst[NUM_INST_CNTS] = { - (1 << VMEM_ACCESS) | (1 << VMEM_READ_ACCESS), - (1 << SMEM_ACCESS) | (1 << LDS_ACCESS) | (1 << GDS_ACCESS) | - (1 << SQ_MESSAGE), - (1 << EXP_GPR_LOCK) | (1 << GDS_GPR_LOCK) | (1 << VMW_GPR_LOCK) | - (1 << EXP_PARAM_ACCESS) | (1 << EXP_POS_ACCESS) | (1 << EXP_LDS_ACCESS), - (1 << VMEM_WRITE_ACCESS) | (1 << SCRATCH_WRITE_ACCESS)}; - // The mapping is: // 0 .. SQ_MAX_PGM_VGPRS-1 real VGPRs // SQ_MAX_PGM_VGPRS .. NUM_ALL_VGPRS-1 extra VGPR-like slots @@ -121,8 +135,13 @@ enum RegisterMapping { SQ_MAX_PGM_VGPRS = 512, // Maximum programmable VGPRs across all targets. AGPR_OFFSET = 256, // Maximum programmable ArchVGPRs across all targets. SQ_MAX_PGM_SGPRS = 256, // Maximum programmable SGPRs across all targets. - NUM_EXTRA_VGPRS = 1, // A reserved slot for DS. - EXTRA_VGPR_LDS = 0, // An artificial register to track LDS writes. + NUM_EXTRA_VGPRS = 9, // Reserved slots for DS. + // Artificial register slots to track LDS writes into specific LDS locations + // if a location is known. When slots are exhausted or location is + // unknown use the first slot. The first slot is also always updated in + // addition to known location's slot to properly generate waits if dependent + // instruction's location is unknown. + EXTRA_VGPR_LDS = 0, NUM_ALL_VGPRS = SQ_MAX_PGM_VGPRS + NUM_EXTRA_VGPRS, // Where SGPR starts. }; @@ -137,17 +156,33 @@ enum VmemType { // MIMG instructions with a sampler. VMEM_SAMPLER, // BVH instructions - VMEM_BVH + VMEM_BVH, + NUM_VMEM_TYPES }; +// Maps values of InstCounterType to the instruction that waits on that +// counter. Only used if GCNSubtarget::hasExtendedWaitCounts() +// returns true. +static const unsigned instrsForExtendedCounterTypes[NUM_EXTENDED_INST_CNTS] = { + AMDGPU::S_WAIT_LOADCNT, AMDGPU::S_WAIT_DSCNT, AMDGPU::S_WAIT_EXPCNT, + AMDGPU::S_WAIT_STORECNT, AMDGPU::S_WAIT_SAMPLECNT, AMDGPU::S_WAIT_BVHCNT, + AMDGPU::S_WAIT_KMCNT}; + static bool updateVMCntOnly(const MachineInstr &Inst) { return SIInstrInfo::isVMEM(Inst) || SIInstrInfo::isFLATGlobal(Inst) || SIInstrInfo::isFLATScratch(Inst); } +#ifndef NDEBUG +static bool isNormalMode(InstCounterType MaxCounter) { + return MaxCounter == NUM_NORMAL_INST_CNTS; +} +#endif // NDEBUG + VmemType getVmemType(const MachineInstr &Inst) { assert(updateVMCntOnly(Inst)); - if (!SIInstrInfo::isMIMG(Inst)) + if (!SIInstrInfo::isMIMG(Inst) && !SIInstrInfo::isVIMAGE(Inst) && + !SIInstrInfo::isVSAMPLE(Inst)) return VMEM_NOSAMPLER; const AMDGPU::MIMGInfo *Info = AMDGPU::getMIMGInfo(Inst.getOpcode()); const AMDGPU::MIMGBaseOpcodeInfo *BaseInfo = @@ -156,25 +191,49 @@ VmemType getVmemType(const MachineInstr &Inst) { : BaseInfo->Sampler ? VMEM_SAMPLER : VMEM_NOSAMPLER; } -void addWait(AMDGPU::Waitcnt &Wait, InstCounterType T, unsigned Count) { +unsigned &getCounterRef(AMDGPU::Waitcnt &Wait, InstCounterType T) { switch (T) { - case VM_CNT: - Wait.VmCnt = std::min(Wait.VmCnt, Count); - break; + case LOAD_CNT: + return Wait.LoadCnt; case EXP_CNT: - Wait.ExpCnt = std::min(Wait.ExpCnt, Count); - break; - case LGKM_CNT: - Wait.LgkmCnt = std::min(Wait.LgkmCnt, Count); - break; - case VS_CNT: - Wait.VsCnt = std::min(Wait.VsCnt, Count); - break; + return Wait.ExpCnt; + case DS_CNT: + return Wait.DsCnt; + case STORE_CNT: + return Wait.StoreCnt; + case SAMPLE_CNT: + return Wait.SampleCnt; + case BVH_CNT: + return Wait.BvhCnt; + case KM_CNT: + return Wait.KmCnt; default: llvm_unreachable("bad InstCounterType"); } } +void addWait(AMDGPU::Waitcnt &Wait, InstCounterType T, unsigned Count) { + unsigned &WC = getCounterRef(Wait, T); + WC = std::min(WC, Count); +} + +void setNoWait(AMDGPU::Waitcnt &Wait, InstCounterType T) { + getCounterRef(Wait, T) = ~0u; +} + +unsigned getWait(AMDGPU::Waitcnt &Wait, InstCounterType T) { + return getCounterRef(Wait, T); +} + +// Mapping from event to counter according to the table masks. +InstCounterType eventCounter(const unsigned *masks, WaitEventType E) { + for (auto T : inst_counter_types()) { + if (masks[T] & (1 << E)) + return T; + } + llvm_unreachable("event type has no associated counter"); +} + // This objects maintains the current score brackets of each wait counter, and // a per-register scoreboard for each wait counter. // @@ -185,20 +244,30 @@ void addWait(AMDGPU::Waitcnt &Wait, InstCounterType T, unsigned Count) { // "s_waitcnt 0" before use. class WaitcntBrackets { public: - WaitcntBrackets(const GCNSubtarget *SubTarget, HardwareLimits Limits, - RegisterEncoding Encoding) - : ST(SubTarget), Limits(Limits), Encoding(Encoding) {} + WaitcntBrackets(const GCNSubtarget *SubTarget, InstCounterType MaxCounter, + HardwareLimits Limits, RegisterEncoding Encoding, + const unsigned *WaitEventMaskForInst, + InstCounterType SmemAccessCounter) + : ST(SubTarget), MaxCounter(MaxCounter), Limits(Limits), + Encoding(Encoding), WaitEventMaskForInst(WaitEventMaskForInst), + SmemAccessCounter(SmemAccessCounter) {} unsigned getWaitCountMax(InstCounterType T) const { switch (T) { - case VM_CNT: - return Limits.VmcntMax; - case LGKM_CNT: - return Limits.LgkmcntMax; + case LOAD_CNT: + return Limits.LoadcntMax; + case DS_CNT: + return Limits.DscntMax; case EXP_CNT: return Limits.ExpcntMax; - case VS_CNT: - return Limits.VscntMax; + case STORE_CNT: + return Limits.StorecntMax; + case SAMPLE_CNT: + return Limits.SamplecntMax; + case BVH_CNT: + return Limits.BvhcntMax; + case KM_CNT: + return Limits.KmcntMax; default: break; } @@ -219,20 +288,11 @@ public: return getScoreUB(T) - getScoreLB(T); } - // Mapping from event to counter. - InstCounterType eventCounter(WaitEventType E) const { - for (auto T : inst_counter_types()) { - if (WaitEventMaskForInst[T] & (1 << E)) - return T; - } - llvm_unreachable("event type has no associated counter"); - } - unsigned getRegScore(int GprNo, InstCounterType T) const { if (GprNo < NUM_ALL_VGPRS) { return VgprScores[T][GprNo]; } - assert(T == LGKM_CNT); + assert(T == SmemAccessCounter); return SgprScores[GprNo - NUM_ALL_VGPRS]; } @@ -269,15 +329,15 @@ public: } bool hasPendingFlat() const { - return ((LastFlat[LGKM_CNT] > ScoreLBs[LGKM_CNT] && - LastFlat[LGKM_CNT] <= ScoreUBs[LGKM_CNT]) || - (LastFlat[VM_CNT] > ScoreLBs[VM_CNT] && - LastFlat[VM_CNT] <= ScoreUBs[VM_CNT])); + return ((LastFlat[DS_CNT] > ScoreLBs[DS_CNT] && + LastFlat[DS_CNT] <= ScoreUBs[DS_CNT]) || + (LastFlat[LOAD_CNT] > ScoreLBs[LOAD_CNT] && + LastFlat[LOAD_CNT] <= ScoreUBs[LOAD_CNT])); } void setPendingFlat() { - LastFlat[VM_CNT] = ScoreUBs[VM_CNT]; - LastFlat[LGKM_CNT] = ScoreUBs[LGKM_CNT]; + LastFlat[LOAD_CNT] = ScoreUBs[LOAD_CNT]; + LastFlat[DS_CNT] = ScoreUBs[DS_CNT]; } // Return true if there might be pending writes to the specified vgpr by VMEM @@ -293,8 +353,12 @@ public: } void setStateOnFunctionEntryOrReturn() { - setScoreUB(VS_CNT, getWaitCountMax(VS_CNT)); - PendingEvents |= WaitEventMaskForInst[VS_CNT]; + setScoreUB(STORE_CNT, getScoreUB(STORE_CNT) + getWaitCountMax(STORE_CNT)); + PendingEvents |= WaitEventMaskForInst[STORE_CNT]; + } + + ArrayRef getLDSDMAStores() const { + return LDSDMAStores; } void print(raw_ostream &); @@ -331,7 +395,7 @@ private: VgprUB = std::max(VgprUB, GprNo); VgprScores[T][GprNo] = Val; } else { - assert(T == LGKM_CNT); + assert(T == SmemAccessCounter); SgprUB = std::max(SgprUB, GprNo - NUM_ALL_VGPRS); SgprScores[GprNo - NUM_ALL_VGPRS] = Val; } @@ -342,8 +406,11 @@ private: unsigned OpNo, unsigned Val); const GCNSubtarget *ST = nullptr; + InstCounterType MaxCounter = NUM_EXTENDED_INST_CNTS; HardwareLimits Limits = {}; RegisterEncoding Encoding = {}; + const unsigned *WaitEventMaskForInst; + InstCounterType SmemAccessCounter; unsigned ScoreLBs[NUM_INST_CNTS] = {0}; unsigned ScoreUBs[NUM_INST_CNTS] = {0}; unsigned PendingEvents = 0; @@ -354,11 +421,134 @@ private: int VgprUB = -1; int SgprUB = -1; unsigned VgprScores[NUM_INST_CNTS][NUM_ALL_VGPRS] = {{0}}; - // Wait cnt scores for every sgpr, only lgkmcnt is relevant. + // Wait cnt scores for every sgpr, only DS_CNT (corresponding to LGKMcnt + // pre-gfx12) or KM_CNT (gfx12+ only) are relevant. unsigned SgprScores[SQ_MAX_PGM_SGPRS] = {0}; // Bitmask of the VmemTypes of VMEM instructions that might have a pending // write to each vgpr. unsigned char VgprVmemTypes[NUM_ALL_VGPRS] = {0}; + // Store representative LDS DMA operations. The only useful info here is + // alias info. One store is kept per unique AAInfo. + SmallVector LDSDMAStores; +}; + +// This abstracts the logic for generating and updating S_WAIT* instructions +// away from the analysis that determines where they are needed. This was +// done because the set of counters and instructions for waiting on them +// underwent a major shift with gfx12, sufficiently so that having this +// abstraction allows the main analysis logic to be simpler than it would +// otherwise have had to become. +class WaitcntGenerator { +protected: + const GCNSubtarget *ST = nullptr; + const SIInstrInfo *TII = nullptr; + AMDGPU::IsaVersion IV; + InstCounterType MaxCounter; + +public: + WaitcntGenerator() {} + WaitcntGenerator(const GCNSubtarget *ST, InstCounterType MaxCounter) + : ST(ST), TII(ST->getInstrInfo()), + IV(AMDGPU::getIsaVersion(ST->getCPU())), MaxCounter(MaxCounter) {} + + // Edits an existing sequence of wait count instructions according + // to an incoming Waitcnt value, which is itself updated to reflect + // any new wait count instructions which may need to be generated by + // WaitcntGenerator::createNewWaitcnt(). It will return true if any edits + // were made. + // + // This editing will usually be merely updated operands, but it may also + // delete instructions if the incoming Wait value indicates they are not + // needed. It may also remove existing instructions for which a wait + // is needed if it can be determined that it is better to generate new + // instructions later, as can happen on gfx12. + virtual bool + applyPreexistingWaitcnt(WaitcntBrackets &ScoreBrackets, + MachineInstr &OldWaitcntInstr, AMDGPU::Waitcnt &Wait, + MachineBasicBlock::instr_iterator It) const = 0; + + // Transform a soft waitcnt into a normal one. + bool promoteSoftWaitCnt(MachineInstr *Waitcnt) const; + + // Generates new wait count instructions according to the value of + // Wait, returning true if any new instructions were created. + virtual bool createNewWaitcnt(MachineBasicBlock &Block, + MachineBasicBlock::instr_iterator It, + AMDGPU::Waitcnt Wait) = 0; + + // Returns an array of bit masks which can be used to map values in + // WaitEventType to corresponding counter values in InstCounterType. + virtual const unsigned *getWaitEventMask() const = 0; + + virtual ~WaitcntGenerator() = default; +}; + +class WaitcntGeneratorPreGFX12 : public WaitcntGenerator { +public: + WaitcntGeneratorPreGFX12() {} + WaitcntGeneratorPreGFX12(const GCNSubtarget *ST) + : WaitcntGenerator(ST, NUM_NORMAL_INST_CNTS) {} + + bool + applyPreexistingWaitcnt(WaitcntBrackets &ScoreBrackets, + MachineInstr &OldWaitcntInstr, AMDGPU::Waitcnt &Wait, + MachineBasicBlock::instr_iterator It) const override; + + bool createNewWaitcnt(MachineBasicBlock &Block, + MachineBasicBlock::instr_iterator It, + AMDGPU::Waitcnt Wait) override; + + const unsigned *getWaitEventMask() const override { + assert(ST); + + static const unsigned WaitEventMaskForInstPreGFX12[NUM_INST_CNTS] = { + (1 << VMEM_ACCESS) | (1 << VMEM_READ_ACCESS) | + (1 << VMEM_SAMPLER_READ_ACCESS) | (1 << VMEM_BVH_READ_ACCESS), + (1 << SMEM_ACCESS) | (1 << LDS_ACCESS) | (1 << GDS_ACCESS) | + (1 << SQ_MESSAGE), + (1 << EXP_GPR_LOCK) | (1 << GDS_GPR_LOCK) | (1 << VMW_GPR_LOCK) | + (1 << EXP_PARAM_ACCESS) | (1 << EXP_POS_ACCESS) | + (1 << EXP_LDS_ACCESS), + (1 << VMEM_WRITE_ACCESS) | (1 << SCRATCH_WRITE_ACCESS), + 0, + 0, + 0}; + + return WaitEventMaskForInstPreGFX12; + } +}; + +class WaitcntGeneratorGFX12Plus : public WaitcntGenerator { +public: + WaitcntGeneratorGFX12Plus() {} + WaitcntGeneratorGFX12Plus(const GCNSubtarget *ST, InstCounterType MaxCounter) + : WaitcntGenerator(ST, MaxCounter) {} + + bool + applyPreexistingWaitcnt(WaitcntBrackets &ScoreBrackets, + MachineInstr &OldWaitcntInstr, AMDGPU::Waitcnt &Wait, + MachineBasicBlock::instr_iterator It) const override; + + bool createNewWaitcnt(MachineBasicBlock &Block, + MachineBasicBlock::instr_iterator It, + AMDGPU::Waitcnt Wait) override; + + const unsigned *getWaitEventMask() const override { + assert(ST); + + static const unsigned WaitEventMaskForInstGFX12Plus[NUM_INST_CNTS] = { + (1 << VMEM_ACCESS) | (1 << VMEM_READ_ACCESS), + (1 << LDS_ACCESS) | (1 << GDS_ACCESS), + (1 << EXP_GPR_LOCK) | (1 << GDS_GPR_LOCK) | (1 << VMW_GPR_LOCK) | + (1 << EXP_PARAM_ACCESS) | (1 << EXP_POS_ACCESS) | + (1 << EXP_LDS_ACCESS), + (1 << VMEM_WRITE_ACCESS) | (1 << SCRATCH_WRITE_ACCESS), + (1 << VMEM_SAMPLER_READ_ACCESS), + (1 << VMEM_BVH_READ_ACCESS), + (1 << SMEM_ACCESS) | (1 << SQ_MESSAGE)}; + + return WaitEventMaskForInstGFX12Plus; + } }; class SIInsertWaitcnts : public MachineFunctionPass { @@ -367,18 +557,20 @@ private: const SIInstrInfo *TII = nullptr; const SIRegisterInfo *TRI = nullptr; const MachineRegisterInfo *MRI = nullptr; - AMDGPU::IsaVersion IV; DenseMap SLoadAddresses; DenseMap PreheadersToFlush; MachineLoopInfo *MLI; MachinePostDominatorTree *PDT; + AliasAnalysis *AA = nullptr; struct BlockInfo { std::unique_ptr Incoming; bool Dirty = true; }; + InstCounterType SmemAccessCounter; + MapVector BlockInfos; // ForceEmitZeroWaitcnts: force all waitcnts insts to be s_waitcnt 0 @@ -388,10 +580,20 @@ private: bool OptNone; + // In any given run of this pass, WCG will point to one of these two + // generator objects, which must have been re-initialised before use + // from a value made using a subtarget constructor. + WaitcntGeneratorPreGFX12 WCGPreGFX12; + WaitcntGeneratorGFX12Plus WCGGFX12Plus; + + WaitcntGenerator *WCG = nullptr; + // S_ENDPGM instructions before which we should insert a DEALLOC_VGPRS // message. DenseSet ReleaseVGPRInsts; + InstCounterType MaxCounter = NUM_NORMAL_INST_CNTS; + public: static char ID; @@ -415,6 +617,8 @@ public: AU.setPreservesCFG(); AU.addRequired(); AU.addRequired(); + AU.addUsedIfAvailable(); + AU.addPreserved(); MachineFunctionPass::getAnalysisUsage(AU); } @@ -438,16 +642,22 @@ public: if (DebugCounter::isCounterSet(ForceLgkmCounter) && DebugCounter::shouldExecute(ForceLgkmCounter)) { - ForceEmitWaitcnt[LGKM_CNT] = true; + ForceEmitWaitcnt[DS_CNT] = true; + ForceEmitWaitcnt[KM_CNT] = true; } else { - ForceEmitWaitcnt[LGKM_CNT] = false; + ForceEmitWaitcnt[DS_CNT] = false; + ForceEmitWaitcnt[KM_CNT] = false; } if (DebugCounter::isCounterSet(ForceVMCounter) && DebugCounter::shouldExecute(ForceVMCounter)) { - ForceEmitWaitcnt[VM_CNT] = true; + ForceEmitWaitcnt[LOAD_CNT] = true; + ForceEmitWaitcnt[SAMPLE_CNT] = true; + ForceEmitWaitcnt[BVH_CNT] = true; } else { - ForceEmitWaitcnt[VM_CNT] = false; + ForceEmitWaitcnt[LOAD_CNT] = false; + ForceEmitWaitcnt[SAMPLE_CNT] = false; + ForceEmitWaitcnt[BVH_CNT] = false; } #endif // NDEBUG } @@ -455,6 +665,10 @@ public: // Return the appropriate VMEM_*_ACCESS type for Inst, which must be a VMEM or // FLAT instruction. WaitEventType getVmemWaitEventType(const MachineInstr &Inst) const { + // Maps VMEM access types to their corresponding WaitEventType. + static const WaitEventType VmemReadMapping[NUM_VMEM_TYPES] = { + VMEM_READ_ACCESS, VMEM_SAMPLER_READ_ACCESS, VMEM_BVH_READ_ACCESS}; + assert(SIInstrInfo::isVMEM(Inst) || SIInstrInfo::isFLAT(Inst)); // LDS DMA loads are also stores, but on the LDS side. On the VMEM side // these should use VM_CNT. @@ -467,7 +681,9 @@ public: return SCRATCH_WRITE_ACCESS; return VMEM_WRITE_ACCESS; } - return VMEM_READ_ACCESS; + if (!ST->hasExtendedWaitCounts() || SIInstrInfo::isFLAT(Inst)) + return VMEM_READ_ACCESS; + return VmemReadMapping[getVmemType(Inst)]; } bool mayAccessVMEMThroughFlat(const MachineInstr &MI) const; @@ -488,13 +704,6 @@ public: WaitcntBrackets *ScoreBrackets); bool insertWaitcntInBlock(MachineFunction &MF, MachineBasicBlock &Block, WaitcntBrackets &ScoreBrackets); - bool applyPreexistingWaitcnt(WaitcntBrackets &ScoreBrackets, - MachineInstr &OldWaitcntInstr, - AMDGPU::Waitcnt &Wait, - MachineBasicBlock::instr_iterator It) const; - - // Transform a soft waitcnt into a normal one. - bool promoteSoftWaitCnt(MachineInstr *Waitcnt) const; }; } // end anonymous namespace @@ -556,8 +765,10 @@ void WaitcntBrackets::updateByEvent(const SIInstrInfo *TII, const SIRegisterInfo *TRI, const MachineRegisterInfo *MRI, WaitEventType E, MachineInstr &Inst) { - InstCounterType T = eventCounter(E); - unsigned CurrScore = getScoreUB(T) + 1; + InstCounterType T = eventCounter(WaitEventMaskForInst, E); + + unsigned UB = getScoreUB(T); + unsigned CurrScore = UB + 1; if (CurrScore == 0) report_fatal_error("InsertWaitcnt score wraparound"); // PendingEvents and ScoreUB need to be update regardless if this event @@ -686,7 +897,7 @@ void WaitcntBrackets::updateByEvent(const SIInstrInfo *TII, if (!Op.isReg() || !Op.isDef()) continue; RegInterval Interval = getRegInterval(&Inst, MRI, TRI, I); - if (T == VM_CNT) { + if (T == LOAD_CNT || T == SAMPLE_CNT || T == BVH_CNT) { if (Interval.first >= NUM_ALL_VGPRS) continue; if (updateVMCntOnly(Inst)) { @@ -707,28 +918,73 @@ void WaitcntBrackets::updateByEvent(const SIInstrInfo *TII, (TII->isDS(Inst) || TII->mayWriteLDSThroughDMA(Inst))) { // MUBUF and FLAT LDS DMA operations need a wait on vmcnt before LDS // written can be accessed. A load from LDS to VMEM does not need a wait. - setRegScore(SQ_MAX_PGM_VGPRS + EXTRA_VGPR_LDS, T, CurrScore); + unsigned Slot = 0; + for (const auto *MemOp : Inst.memoperands()) { + if (!MemOp->isStore() || + MemOp->getAddrSpace() != AMDGPUAS::LOCAL_ADDRESS) + continue; + // Comparing just AA info does not guarantee memoperands are equal + // in general, but this is so for LDS DMA in practice. + auto AAI = MemOp->getAAInfo(); + // Alias scope information gives a way to definitely identify an + // original memory object and practically produced in the module LDS + // lowering pass. If there is no scope available we will not be able + // to disambiguate LDS aliasing as after the module lowering all LDS + // is squashed into a single big object. Do not attempt to use one of + // the limited LDSDMAStores for something we will not be able to use + // anyway. + if (!AAI || !AAI.Scope) + break; + for (unsigned I = 0, E = LDSDMAStores.size(); I != E && !Slot; ++I) { + for (const auto *MemOp : LDSDMAStores[I]->memoperands()) { + if (MemOp->isStore() && AAI == MemOp->getAAInfo()) { + Slot = I + 1; + break; + } + } + } + if (Slot || LDSDMAStores.size() == NUM_EXTRA_VGPRS - 1) + break; + LDSDMAStores.push_back(&Inst); + Slot = LDSDMAStores.size(); + break; + } + setRegScore(SQ_MAX_PGM_VGPRS + EXTRA_VGPR_LDS + Slot, T, CurrScore); + if (Slot) + setRegScore(SQ_MAX_PGM_VGPRS + EXTRA_VGPR_LDS, T, CurrScore); } } } void WaitcntBrackets::print(raw_ostream &OS) { OS << '\n'; - for (auto T : inst_counter_types()) { + for (auto T : inst_counter_types(MaxCounter)) { unsigned SR = getScoreRange(T); switch (T) { - case VM_CNT: - OS << " VM_CNT(" << SR << "): "; + case LOAD_CNT: + OS << " " << (ST->hasExtendedWaitCounts() ? "LOAD" : "VM") << "_CNT(" + << SR << "): "; break; - case LGKM_CNT: - OS << " LGKM_CNT(" << SR << "): "; + case DS_CNT: + OS << " " << (ST->hasExtendedWaitCounts() ? "DS" : "LGKM") << "_CNT(" + << SR << "): "; break; case EXP_CNT: OS << " EXP_CNT(" << SR << "): "; break; - case VS_CNT: - OS << " VS_CNT(" << SR << "): "; + case STORE_CNT: + OS << " " << (ST->hasExtendedWaitCounts() ? "STORE" : "VS") << "_CNT(" + << SR << "): "; + break; + case SAMPLE_CNT: + OS << " SAMPLE_CNT(" << SR << "): "; + break; + case BVH_CNT: + OS << " BVH_CNT(" << SR << "): "; + break; + case KM_CNT: + OS << " KM_CNT(" << SR << "): "; break; default: OS << " UNKNOWN(" << SR << "): "; @@ -751,9 +1007,9 @@ void WaitcntBrackets::print(raw_ostream &OS) { } } // Also need to print sgpr scores for lgkm_cnt. - if (T == LGKM_CNT) { + if (T == SmemAccessCounter) { for (int J = 0; J <= SgprUB; J++) { - unsigned RegScore = getRegScore(J + NUM_ALL_VGPRS, LGKM_CNT); + unsigned RegScore = getRegScore(J + NUM_ALL_VGPRS, T); if (RegScore <= LB) continue; unsigned RelScore = RegScore - LB - 1; @@ -769,10 +1025,13 @@ void WaitcntBrackets::print(raw_ostream &OS) { /// Simplify the waitcnt, in the sense of removing redundant counts, and return /// whether a waitcnt instruction is needed at all. void WaitcntBrackets::simplifyWaitcnt(AMDGPU::Waitcnt &Wait) const { - simplifyWaitcnt(VM_CNT, Wait.VmCnt); + simplifyWaitcnt(LOAD_CNT, Wait.LoadCnt); simplifyWaitcnt(EXP_CNT, Wait.ExpCnt); - simplifyWaitcnt(LGKM_CNT, Wait.LgkmCnt); - simplifyWaitcnt(VS_CNT, Wait.VsCnt); + simplifyWaitcnt(DS_CNT, Wait.DsCnt); + simplifyWaitcnt(STORE_CNT, Wait.StoreCnt); + simplifyWaitcnt(SAMPLE_CNT, Wait.SampleCnt); + simplifyWaitcnt(BVH_CNT, Wait.BvhCnt); + simplifyWaitcnt(KM_CNT, Wait.KmCnt); } void WaitcntBrackets::simplifyWaitcnt(InstCounterType T, @@ -793,8 +1052,7 @@ void WaitcntBrackets::determineWait(InstCounterType T, int RegNo, const unsigned LB = getScoreLB(T); const unsigned UB = getScoreUB(T); if ((UB >= ScoreToWait) && (ScoreToWait > LB)) { - if ((T == VM_CNT || T == LGKM_CNT) && - hasPendingFlat() && + if ((T == LOAD_CNT || T == DS_CNT) && hasPendingFlat() && !ST->hasFlatLgkmVMemCountInOrder()) { // If there is a pending FLAT operation, and this is a VMem or LGKM // waitcnt and the target can report early completion, then we need @@ -815,10 +1073,13 @@ void WaitcntBrackets::determineWait(InstCounterType T, int RegNo, } void WaitcntBrackets::applyWaitcnt(const AMDGPU::Waitcnt &Wait) { - applyWaitcnt(VM_CNT, Wait.VmCnt); + applyWaitcnt(LOAD_CNT, Wait.LoadCnt); applyWaitcnt(EXP_CNT, Wait.ExpCnt); - applyWaitcnt(LGKM_CNT, Wait.LgkmCnt); - applyWaitcnt(VS_CNT, Wait.VsCnt); + applyWaitcnt(DS_CNT, Wait.DsCnt); + applyWaitcnt(STORE_CNT, Wait.StoreCnt); + applyWaitcnt(SAMPLE_CNT, Wait.SampleCnt); + applyWaitcnt(BVH_CNT, Wait.BvhCnt); + applyWaitcnt(KM_CNT, Wait.KmCnt); } void WaitcntBrackets::applyWaitcnt(InstCounterType T, unsigned Count) { @@ -839,7 +1100,7 @@ void WaitcntBrackets::applyWaitcnt(InstCounterType T, unsigned Count) { // the decrement may go out of order. bool WaitcntBrackets::counterOutOfOrder(InstCounterType T) const { // Scalar memory read always can go out of order. - if (T == LGKM_CNT && hasPendingEvent(SMEM_ACCESS)) + if (T == SmemAccessCounter && hasPendingEvent(SMEM_ACCESS)) return true; return hasMixedPendingEvents(T); } @@ -873,22 +1134,49 @@ static bool updateOperandIfDifferent(MachineInstr &MI, uint16_t OpName, return true; } -bool SIInsertWaitcnts::promoteSoftWaitCnt(MachineInstr *Waitcnt) const { - unsigned Opcode = Waitcnt->getOpcode(); - if (!SIInstrInfo::isSoftWaitcnt(Opcode)) +/// Determine if \p MI is a gfx12+ single-counter S_WAIT_*CNT instruction, +/// and if so, which counter it is waiting on. +static std::optional counterTypeForInstr(unsigned Opcode) { + switch (Opcode) { + case AMDGPU::S_WAIT_LOADCNT: + return LOAD_CNT; + case AMDGPU::S_WAIT_EXPCNT: + return EXP_CNT; + case AMDGPU::S_WAIT_STORECNT: + return STORE_CNT; + case AMDGPU::S_WAIT_SAMPLECNT: + return SAMPLE_CNT; + case AMDGPU::S_WAIT_BVHCNT: + return BVH_CNT; + case AMDGPU::S_WAIT_DSCNT: + return DS_CNT; + case AMDGPU::S_WAIT_KMCNT: + return KM_CNT; + default: + return {}; + } +} + +bool WaitcntGenerator::promoteSoftWaitCnt(MachineInstr *Waitcnt) const { + unsigned Opcode = SIInstrInfo::getNonSoftWaitcntOpcode(Waitcnt->getOpcode()); + if (Opcode == Waitcnt->getOpcode()) return false; - Waitcnt->setDesc(TII->get(SIInstrInfo::getNonSoftWaitcntOpcode(Opcode))); + Waitcnt->setDesc(TII->get(Opcode)); return true; } -/// Combine consecutive waitcnt instructions that precede \p It and follow -/// \p OldWaitcntInstr and apply any extra wait from waitcnt that were added -/// by previous passes. Currently this pass conservatively assumes that these -/// preexisting waitcnt are required for correctness. -bool SIInsertWaitcnts::applyPreexistingWaitcnt( +/// Combine consecutive S_WAITCNT and S_WAITCNT_VSCNT instructions that +/// precede \p It and follow \p OldWaitcntInstr and apply any extra waits +/// from \p Wait that were added by previous passes. Currently this pass +/// conservatively assumes that these preexisting waits are required for +/// correctness. +bool WaitcntGeneratorPreGFX12::applyPreexistingWaitcnt( WaitcntBrackets &ScoreBrackets, MachineInstr &OldWaitcntInstr, AMDGPU::Waitcnt &Wait, MachineBasicBlock::instr_iterator It) const { + assert(ST); + assert(isNormalMode(MaxCounter)); + bool Modified = false; MachineInstr *WaitcntInstr = nullptr; MachineInstr *WaitcntVsCntInstr = nullptr; @@ -898,12 +1186,12 @@ bool SIInsertWaitcnts::applyPreexistingWaitcnt( if (II.isMetaInstruction()) continue; - unsigned Opcode = II.getOpcode(); - bool IsSoft = SIInstrInfo::isSoftWaitcnt(Opcode); + unsigned Opcode = SIInstrInfo::getNonSoftWaitcntOpcode(II.getOpcode()); + bool IsSoft = Opcode != II.getOpcode(); - if (SIInstrInfo::isWaitcnt(Opcode)) { - // Update required wait count. If this is a soft waitcnt (= it was added - // by an earlier pass), it may be entirely removed. + // Update required wait count. If this is a soft waitcnt (= it was added + // by an earlier pass), it may be entirely removed. + if (Opcode == AMDGPU::S_WAITCNT) { unsigned IEnc = II.getOperand(0).getImm(); AMDGPU::Waitcnt OldWait = AMDGPU::decodeWaitcnt(IV, IEnc); if (IsSoft) @@ -911,23 +1199,22 @@ bool SIInsertWaitcnts::applyPreexistingWaitcnt( Wait = Wait.combined(OldWait); // Merge consecutive waitcnt of the same type by erasing multiples. - if (WaitcntInstr || (!Wait.hasWaitExceptVsCnt() && IsSoft)) { + if (WaitcntInstr || (!Wait.hasWaitExceptStoreCnt() && IsSoft)) { II.eraseFromParent(); Modified = true; } else WaitcntInstr = &II; - } else { - assert(SIInstrInfo::isWaitcntVsCnt(Opcode)); + assert(Opcode == AMDGPU::S_WAITCNT_VSCNT); assert(II.getOperand(0).getReg() == AMDGPU::SGPR_NULL); unsigned OldVSCnt = TII->getNamedOperand(II, AMDGPU::OpName::simm16)->getImm(); if (IsSoft) - ScoreBrackets.simplifyWaitcnt(InstCounterType::VS_CNT, OldVSCnt); - Wait.VsCnt = std::min(Wait.VsCnt, OldVSCnt); + ScoreBrackets.simplifyWaitcnt(InstCounterType::STORE_CNT, OldVSCnt); + Wait.StoreCnt = std::min(Wait.StoreCnt, OldVSCnt); - if (WaitcntVsCntInstr || (!Wait.hasWaitVsCnt() && IsSoft)) { + if (WaitcntVsCntInstr || (!Wait.hasWaitStoreCnt() && IsSoft)) { II.eraseFromParent(); Modified = true; } else @@ -935,18 +1222,19 @@ bool SIInsertWaitcnts::applyPreexistingWaitcnt( } } - // Updated encoding of merged waitcnt with the required wait. if (WaitcntInstr) { Modified |= updateOperandIfDifferent(*WaitcntInstr, AMDGPU::OpName::simm16, AMDGPU::encodeWaitcnt(IV, Wait)); Modified |= promoteSoftWaitCnt(WaitcntInstr); - ScoreBrackets.applyWaitcnt(Wait); - Wait.VmCnt = ~0u; - Wait.LgkmCnt = ~0u; + ScoreBrackets.applyWaitcnt(LOAD_CNT, Wait.LoadCnt); + ScoreBrackets.applyWaitcnt(EXP_CNT, Wait.ExpCnt); + ScoreBrackets.applyWaitcnt(DS_CNT, Wait.DsCnt); + Wait.LoadCnt = ~0u; Wait.ExpCnt = ~0u; + Wait.DsCnt = ~0u; - LLVM_DEBUG(It == OldWaitcntInstr.getParent()->end() + LLVM_DEBUG(It == WaitcntInstr->getParent()->end() ? dbgs() << "applyPreexistingWaitcnt\n" << "New Instr at block end: " << *WaitcntInstr << '\n' @@ -957,12 +1245,13 @@ bool SIInsertWaitcnts::applyPreexistingWaitcnt( if (WaitcntVsCntInstr) { Modified |= updateOperandIfDifferent(*WaitcntVsCntInstr, - AMDGPU::OpName::simm16, Wait.VsCnt); + AMDGPU::OpName::simm16, Wait.StoreCnt); Modified |= promoteSoftWaitCnt(WaitcntVsCntInstr); - ScoreBrackets.applyWaitcnt(Wait); - Wait.VsCnt = ~0u; - LLVM_DEBUG(It == OldWaitcntInstr.getParent()->end() + ScoreBrackets.applyWaitcnt(STORE_CNT, Wait.StoreCnt); + Wait.StoreCnt = ~0u; + + LLVM_DEBUG(It == WaitcntVsCntInstr->getParent()->end() ? dbgs() << "applyPreexistingWaitcnt\n" << "New Instr at block end: " << *WaitcntVsCntInstr << '\n' @@ -974,6 +1263,293 @@ bool SIInsertWaitcnts::applyPreexistingWaitcnt( return Modified; } +/// Generate S_WAITCNT and/or S_WAITCNT_VSCNT instructions for any +/// required counters in \p Wait +bool WaitcntGeneratorPreGFX12::createNewWaitcnt( + MachineBasicBlock &Block, MachineBasicBlock::instr_iterator It, + AMDGPU::Waitcnt Wait) { + assert(ST); + assert(isNormalMode(MaxCounter)); + + bool Modified = false; + const DebugLoc &DL = Block.findDebugLoc(It); + + // Waits for VMcnt, LKGMcnt and/or EXPcnt are encoded together into a + // single instruction while VScnt has its own instruction. + if (Wait.hasWaitExceptStoreCnt()) { + unsigned Enc = AMDGPU::encodeWaitcnt(IV, Wait); + [[maybe_unused]] auto SWaitInst = + BuildMI(Block, It, DL, TII->get(AMDGPU::S_WAITCNT)).addImm(Enc); + Modified = true; + + LLVM_DEBUG(dbgs() << "generateWaitcnt\n"; + if (It != Block.instr_end()) dbgs() << "Old Instr: " << *It; + dbgs() << "New Instr: " << *SWaitInst << '\n'); + } + + if (Wait.hasWaitStoreCnt()) { + assert(ST->hasVscnt()); + + [[maybe_unused]] auto SWaitInst = + BuildMI(Block, It, DL, TII->get(AMDGPU::S_WAITCNT_VSCNT)) + .addReg(AMDGPU::SGPR_NULL, RegState::Undef) + .addImm(Wait.StoreCnt); + Modified = true; + + LLVM_DEBUG(dbgs() << "generateWaitcnt\n"; + if (It != Block.instr_end()) dbgs() << "Old Instr: " << *It; + dbgs() << "New Instr: " << *SWaitInst << '\n'); + } + + return Modified; +} + +/// Combine consecutive S_WAIT_*CNT instructions that precede \p It and +/// follow \p OldWaitcntInstr and apply any extra waits from \p Wait that +/// were added by previous passes. Currently this pass conservatively +/// assumes that these preexisting waits are required for correctness. +bool WaitcntGeneratorGFX12Plus::applyPreexistingWaitcnt( + WaitcntBrackets &ScoreBrackets, MachineInstr &OldWaitcntInstr, + AMDGPU::Waitcnt &Wait, MachineBasicBlock::instr_iterator It) const { + assert(ST); + assert(!isNormalMode(MaxCounter)); + + bool Modified = false; + MachineInstr *CombinedLoadDsCntInstr = nullptr; + MachineInstr *CombinedStoreDsCntInstr = nullptr; + MachineInstr *WaitInstrs[NUM_EXTENDED_INST_CNTS] = {}; + + for (auto &II : + make_early_inc_range(make_range(OldWaitcntInstr.getIterator(), It))) { + if (II.isMetaInstruction()) + continue; + + MachineInstr **UpdatableInstr; + + // Update required wait count. If this is a soft waitcnt (= it was added + // by an earlier pass), it may be entirely removed. + + unsigned Opcode = SIInstrInfo::getNonSoftWaitcntOpcode(II.getOpcode()); + bool IsSoft = Opcode != II.getOpcode(); + + if (Opcode == AMDGPU::S_WAIT_LOADCNT_DSCNT) { + unsigned OldEnc = + TII->getNamedOperand(II, AMDGPU::OpName::simm16)->getImm(); + AMDGPU::Waitcnt OldWait = AMDGPU::decodeLoadcntDscnt(IV, OldEnc); + if (IsSoft) + ScoreBrackets.simplifyWaitcnt(OldWait); + Wait = Wait.combined(OldWait); + UpdatableInstr = &CombinedLoadDsCntInstr; + } else if (Opcode == AMDGPU::S_WAIT_STORECNT_DSCNT) { + unsigned OldEnc = + TII->getNamedOperand(II, AMDGPU::OpName::simm16)->getImm(); + AMDGPU::Waitcnt OldWait = AMDGPU::decodeStorecntDscnt(IV, OldEnc); + if (IsSoft) + ScoreBrackets.simplifyWaitcnt(OldWait); + Wait = Wait.combined(OldWait); + UpdatableInstr = &CombinedStoreDsCntInstr; + } else { + std::optional CT = counterTypeForInstr(Opcode); + assert(CT.has_value()); + unsigned OldCnt = + TII->getNamedOperand(II, AMDGPU::OpName::simm16)->getImm(); + if (IsSoft) + ScoreBrackets.simplifyWaitcnt(CT.value(), OldCnt); + addWait(Wait, CT.value(), OldCnt); + UpdatableInstr = &WaitInstrs[CT.value()]; + } + + // Merge consecutive waitcnt of the same type by erasing multiples. + if (!*UpdatableInstr) { + *UpdatableInstr = &II; + } else { + II.eraseFromParent(); + Modified = true; + } + } + + if (CombinedLoadDsCntInstr) { + // Only keep an S_WAIT_LOADCNT_DSCNT if both counters actually need + // to be waited for. Otherwise, let the instruction be deleted so + // the appropriate single counter wait instruction can be inserted + // instead, when new S_WAIT_*CNT instructions are inserted by + // createNewWaitcnt(). As a side effect, resetting the wait counts will + // cause any redundant S_WAIT_LOADCNT or S_WAIT_DSCNT to be removed by + // the loop below that deals with single counter instructions. + if (Wait.LoadCnt != ~0u && Wait.DsCnt != ~0u) { + unsigned NewEnc = AMDGPU::encodeLoadcntDscnt(IV, Wait); + Modified |= updateOperandIfDifferent(*CombinedLoadDsCntInstr, + AMDGPU::OpName::simm16, NewEnc); + Modified |= promoteSoftWaitCnt(CombinedLoadDsCntInstr); + ScoreBrackets.applyWaitcnt(LOAD_CNT, Wait.LoadCnt); + ScoreBrackets.applyWaitcnt(DS_CNT, Wait.DsCnt); + Wait.LoadCnt = ~0u; + Wait.DsCnt = ~0u; + + LLVM_DEBUG(It == OldWaitcntInstr.getParent()->end() + ? dbgs() << "applyPreexistingWaitcnt\n" + << "New Instr at block end: " + << *CombinedLoadDsCntInstr << '\n' + : dbgs() << "applyPreexistingWaitcnt\n" + << "Old Instr: " << *It << "New Instr: " + << *CombinedLoadDsCntInstr << '\n'); + } else { + CombinedLoadDsCntInstr->eraseFromParent(); + Modified = true; + } + } + + if (CombinedStoreDsCntInstr) { + // Similarly for S_WAIT_STORECNT_DSCNT. + if (Wait.StoreCnt != ~0u && Wait.DsCnt != ~0u) { + unsigned NewEnc = AMDGPU::encodeStorecntDscnt(IV, Wait); + Modified |= updateOperandIfDifferent(*CombinedStoreDsCntInstr, + AMDGPU::OpName::simm16, NewEnc); + Modified |= promoteSoftWaitCnt(CombinedStoreDsCntInstr); + ScoreBrackets.applyWaitcnt(STORE_CNT, Wait.StoreCnt); + ScoreBrackets.applyWaitcnt(DS_CNT, Wait.DsCnt); + Wait.StoreCnt = ~0u; + Wait.DsCnt = ~0u; + + LLVM_DEBUG(It == OldWaitcntInstr.getParent()->end() + ? dbgs() << "applyPreexistingWaitcnt\n" + << "New Instr at block end: " + << *CombinedStoreDsCntInstr << '\n' + : dbgs() << "applyPreexistingWaitcnt\n" + << "Old Instr: " << *It << "New Instr: " + << *CombinedStoreDsCntInstr << '\n'); + } else { + CombinedStoreDsCntInstr->eraseFromParent(); + Modified = true; + } + } + + // Look for an opportunity to convert existing S_WAIT_LOADCNT, + // S_WAIT_STORECNT and S_WAIT_DSCNT into new S_WAIT_LOADCNT_DSCNT + // or S_WAIT_STORECNT_DSCNT. This is achieved by selectively removing + // instructions so that createNewWaitcnt() will create new combined + // instructions to replace them. + + if (Wait.DsCnt != ~0u) { + // This is a vector of addresses in WaitInstrs pointing to instructions + // that should be removed if they are present. + SmallVector WaitsToErase; + + // If it's known that both DScnt and either LOADcnt or STOREcnt (but not + // both) need to be waited for, ensure that there are no existing + // individual wait count instructions for these. + + if (Wait.LoadCnt != ~0u) { + WaitsToErase.push_back(&WaitInstrs[LOAD_CNT]); + WaitsToErase.push_back(&WaitInstrs[DS_CNT]); + } else if (Wait.StoreCnt != ~0u) { + WaitsToErase.push_back(&WaitInstrs[STORE_CNT]); + WaitsToErase.push_back(&WaitInstrs[DS_CNT]); + } + + for (MachineInstr **WI : WaitsToErase) { + if (!*WI) + continue; + + (*WI)->eraseFromParent(); + *WI = nullptr; + Modified = true; + } + } + + for (auto CT : inst_counter_types(NUM_EXTENDED_INST_CNTS)) { + if (!WaitInstrs[CT]) + continue; + + unsigned NewCnt = getWait(Wait, CT); + if (NewCnt != ~0u) { + Modified |= updateOperandIfDifferent(*WaitInstrs[CT], + AMDGPU::OpName::simm16, NewCnt); + Modified |= promoteSoftWaitCnt(WaitInstrs[CT]); + + ScoreBrackets.applyWaitcnt(CT, NewCnt); + setNoWait(Wait, CT); + + LLVM_DEBUG(It == OldWaitcntInstr.getParent()->end() + ? dbgs() << "applyPreexistingWaitcnt\n" + << "New Instr at block end: " << *WaitInstrs[CT] + << '\n' + : dbgs() << "applyPreexistingWaitcnt\n" + << "Old Instr: " << *It + << "New Instr: " << *WaitInstrs[CT] << '\n'); + } else { + WaitInstrs[CT]->eraseFromParent(); + Modified = true; + } + } + + return Modified; +} + +/// Generate S_WAIT_*CNT instructions for any required counters in \p Wait +bool WaitcntGeneratorGFX12Plus::createNewWaitcnt( + MachineBasicBlock &Block, MachineBasicBlock::instr_iterator It, + AMDGPU::Waitcnt Wait) { + assert(ST); + assert(!isNormalMode(MaxCounter)); + + bool Modified = false; + const DebugLoc &DL = Block.findDebugLoc(It); + + // Check for opportunities to use combined wait instructions. + if (Wait.DsCnt != ~0u) { + MachineInstr *SWaitInst = nullptr; + + if (Wait.LoadCnt != ~0u) { + unsigned Enc = AMDGPU::encodeLoadcntDscnt(IV, Wait); + + SWaitInst = BuildMI(Block, It, DL, TII->get(AMDGPU::S_WAIT_LOADCNT_DSCNT)) + .addImm(Enc); + + Wait.LoadCnt = ~0u; + Wait.DsCnt = ~0u; + } else if (Wait.StoreCnt != ~0u) { + unsigned Enc = AMDGPU::encodeStorecntDscnt(IV, Wait); + + SWaitInst = + BuildMI(Block, It, DL, TII->get(AMDGPU::S_WAIT_STORECNT_DSCNT)) + .addImm(Enc); + + Wait.StoreCnt = ~0u; + Wait.DsCnt = ~0u; + } + + if (SWaitInst) { + Modified = true; + + LLVM_DEBUG(dbgs() << "generateWaitcnt\n"; + if (It != Block.instr_end()) dbgs() << "Old Instr: " << *It; + dbgs() << "New Instr: " << *SWaitInst << '\n'); + } + } + + // Generate an instruction for any remaining counter that needs + // waiting for. + + for (auto CT : inst_counter_types(NUM_EXTENDED_INST_CNTS)) { + unsigned Count = getWait(Wait, CT); + if (Count == ~0u) + continue; + + [[maybe_unused]] auto SWaitInst = + BuildMI(Block, It, DL, TII->get(instrsForExtendedCounterTypes[CT])) + .addImm(Count); + + Modified = true; + + LLVM_DEBUG(dbgs() << "generateWaitcnt\n"; + if (It != Block.instr_end()) dbgs() << "Old Instr: " << *It; + dbgs() << "New Instr: " << *SWaitInst << '\n'); + } + + return Modified; +} + static bool readsVCCZ(const MachineInstr &MI) { unsigned Opc = MI.getOpcode(); return (Opc == AMDGPU::S_CBRANCH_VCCNZ || Opc == AMDGPU::S_CBRANCH_VCCZ) && @@ -1027,7 +1603,7 @@ bool SIInsertWaitcnts::generateWaitcntInstBefore(MachineInstr &MI, MI.getOpcode() == AMDGPU::BUFFER_WBINVL1_VOL || MI.getOpcode() == AMDGPU::BUFFER_GL0_INV || MI.getOpcode() == AMDGPU::BUFFER_GL1_INV) { - Wait.VmCnt = 0; + Wait.LoadCnt = 0; } // All waits must be resolved at call return. @@ -1037,16 +1613,19 @@ bool SIInsertWaitcnts::generateWaitcntInstBefore(MachineInstr &MI, MI.getOpcode() == AMDGPU::SI_RETURN || MI.getOpcode() == AMDGPU::S_SETPC_B64_return || (MI.isReturn() && MI.isCall() && !callWaitsOnFunctionEntry(MI))) { - Wait = Wait.combined(AMDGPU::Waitcnt::allZeroExceptVsCnt()); + Wait = Wait.combined( + AMDGPU::Waitcnt::allZeroExceptVsCnt(ST->hasExtendedWaitCounts())); } // Identify S_ENDPGM instructions which may have to wait for outstanding VMEM // stores. In this case it can be useful to send a message to explicitly // release all VGPRs before the stores have completed, but it is only safe to - // do this if there are no outstanding scratch stores. + // do this if: + // * there are no outstanding scratch stores + // * we are not in Dynamic VGPR mode else if (MI.getOpcode() == AMDGPU::S_ENDPGM || MI.getOpcode() == AMDGPU::S_ENDPGM_SAVED) { if (ST->getGeneration() >= AMDGPUSubtarget::GFX11 && !OptNone && - ScoreBrackets.getScoreRange(VS_CNT) != 0 && + ScoreBrackets.getScoreRange(STORE_CNT) != 0 && !ScoreBrackets.hasPendingEvent(SCRATCH_WRITE_ACCESS)) ReleaseVGPRInsts.insert(&MI); } @@ -1056,7 +1635,7 @@ bool SIInsertWaitcnts::generateWaitcntInstBefore(MachineInstr &MI, ST->hasLegacyGeometry() && ((MI.getOperand(0).getImm() & AMDGPU::SendMsg::ID_MASK_PreGFX11_) == AMDGPU::SendMsg::ID_GS_DONE_PreGFX11)) { - Wait.VmCnt = 0; + Wait.LoadCnt = 0; } #if 0 // TODO: the following blocks of logic when we have fence. else if (MI.getOpcode() == SC_FENCE) { @@ -1073,12 +1652,12 @@ bool SIInsertWaitcnts::generateWaitcntInstBefore(MachineInstr &MI, case SCMEM_LDS: if (group_is_multi_wave || context->OptFlagIsOn(OPT_R1100_LDSMEM_FENCE_CHICKEN_BIT)) { - EmitWaitcnt |= ScoreBrackets->updateByWait(LGKM_CNT, - ScoreBrackets->getScoreUB(LGKM_CNT)); - // LDS may have to wait for VM_CNT after buffer load to LDS + EmitWaitcnt |= ScoreBrackets->updateByWait(DS_CNT, + ScoreBrackets->getScoreUB(DS_CNT)); + // LDS may have to wait for VMcnt after buffer load to LDS if (target_info->HasBufferLoadToLDS()) { - EmitWaitcnt |= ScoreBrackets->updateByWait(VM_CNT, - ScoreBrackets->getScoreUB(VM_CNT)); + EmitWaitcnt |= ScoreBrackets->updateByWait(LOAD_CNT, + ScoreBrackets->getScoreUB(LOAD_CNT)); } } break; @@ -1087,8 +1666,8 @@ bool SIInsertWaitcnts::generateWaitcntInstBefore(MachineInstr &MI, if (group_is_multi_wave || fence_is_global) { EmitWaitcnt |= ScoreBrackets->updateByWait(EXP_CNT, ScoreBrackets->getScoreUB(EXP_CNT)); - EmitWaitcnt |= ScoreBrackets->updateByWait(LGKM_CNT, - ScoreBrackets->getScoreUB(LGKM_CNT)); + EmitWaitcnt |= ScoreBrackets->updateByWait(DS_CNT, + ScoreBrackets->getScoreUB(DS_CNT)); } break; @@ -1099,8 +1678,8 @@ bool SIInsertWaitcnts::generateWaitcntInstBefore(MachineInstr &MI, if (group_is_multi_wave || fence_is_global) { EmitWaitcnt |= ScoreBrackets->updateByWait(EXP_CNT, ScoreBrackets->getScoreUB(EXP_CNT)); - EmitWaitcnt |= ScoreBrackets->updateByWait(VM_CNT, - ScoreBrackets->getScoreUB(VM_CNT)); + EmitWaitcnt |= ScoreBrackets->updateByWait(LOAD_CNT, + ScoreBrackets->getScoreUB(LOAD_CNT)); } break; @@ -1143,7 +1722,7 @@ bool SIInsertWaitcnts::generateWaitcntInstBefore(MachineInstr &MI, for (int RegNo = CallAddrOpInterval.first; RegNo < CallAddrOpInterval.second; ++RegNo) - ScoreBrackets.determineWait(LGKM_CNT, RegNo, Wait); + ScoreBrackets.determineWait(SmemAccessCounter, RegNo, Wait); int RtnAddrOpIdx = AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::dst); @@ -1153,7 +1732,7 @@ bool SIInsertWaitcnts::generateWaitcntInstBefore(MachineInstr &MI, for (int RegNo = RtnAddrOpInterval.first; RegNo < RtnAddrOpInterval.second; ++RegNo) - ScoreBrackets.determineWait(LGKM_CNT, RegNo, Wait); + ScoreBrackets.determineWait(SmemAccessCounter, RegNo, Wait); } } } else { @@ -1170,10 +1749,11 @@ bool SIInsertWaitcnts::generateWaitcntInstBefore(MachineInstr &MI, // instruction to guarantee the right WAW order. // 2) If a destination operand that was used by a recent export/store ins, // add s_waitcnt on exp_cnt to guarantee the WAR order. + for (const MachineMemOperand *Memop : MI.memoperands()) { const Value *Ptr = Memop->getValue(); if (Memop->isStore() && SLoadAddresses.count(Ptr)) { - addWait(Wait, LGKM_CNT, 0); + addWait(Wait, SmemAccessCounter, 0); if (PDT->dominates(MI.getParent(), SLoadAddresses.find(Ptr)->second)) SLoadAddresses.erase(Ptr); } @@ -1183,9 +1763,27 @@ bool SIInsertWaitcnts::generateWaitcntInstBefore(MachineInstr &MI, // No need to wait before load from VMEM to LDS. if (TII->mayWriteLDSThroughDMA(MI)) continue; + + // LOAD_CNT is only relevant to vgpr or LDS. unsigned RegNo = SQ_MAX_PGM_VGPRS + EXTRA_VGPR_LDS; - // VM_CNT is only relevant to vgpr or LDS. - ScoreBrackets.determineWait(VM_CNT, RegNo, Wait); + bool FoundAliasingStore = false; + // Only objects with alias scope info were added to LDSDMAScopes array. + // In the absense of the scope info we will not be able to disambiguate + // aliasing here. There is no need to try searching for a corresponding + // store slot. This is conservatively correct because in that case we + // will produce a wait using the first (general) LDS DMA wait slot which + // will wait on all of them anyway. + if (Ptr && Memop->getAAInfo() && Memop->getAAInfo().Scope) { + const auto &LDSDMAStores = ScoreBrackets.getLDSDMAStores(); + for (unsigned I = 0, E = LDSDMAStores.size(); I != E; ++I) { + if (MI.mayAlias(AA, *LDSDMAStores[I], true)) { + FoundAliasingStore = true; + ScoreBrackets.determineWait(LOAD_CNT, RegNo + I + 1, Wait); + } + } + } + if (!FoundAliasingStore) + ScoreBrackets.determineWait(LOAD_CNT, RegNo, Wait); if (Memop->isStore()) { ScoreBrackets.determineWait(EXP_CNT, RegNo, Wait); } @@ -1213,14 +1811,18 @@ bool SIInsertWaitcnts::generateWaitcntInstBefore(MachineInstr &MI, if (Op.isUse() || !updateVMCntOnly(MI) || ScoreBrackets.hasOtherPendingVmemTypes(RegNo, getVmemType(MI))) { - ScoreBrackets.determineWait(VM_CNT, RegNo, Wait); + ScoreBrackets.determineWait(LOAD_CNT, RegNo, Wait); + ScoreBrackets.determineWait(SAMPLE_CNT, RegNo, Wait); + ScoreBrackets.determineWait(BVH_CNT, RegNo, Wait); ScoreBrackets.clearVgprVmemTypes(RegNo); } if (Op.isDef() || ScoreBrackets.hasPendingEvent(EXP_LDS_ACCESS)) { ScoreBrackets.determineWait(EXP_CNT, RegNo, Wait); } + ScoreBrackets.determineWait(DS_CNT, RegNo, Wait); + } else { + ScoreBrackets.determineWait(SmemAccessCounter, RegNo, Wait); } - ScoreBrackets.determineWait(LGKM_CNT, RegNo, Wait); } } } @@ -1232,7 +1834,8 @@ bool SIInsertWaitcnts::generateWaitcntInstBefore(MachineInstr &MI, // cause an exception. Otherwise, insert an explicit S_WAITCNT 0 here. if (MI.getOpcode() == AMDGPU::S_BARRIER && !ST->hasAutoWaitcntBeforeBarrier() && !ST->supportsBackOffBarrier()) { - Wait = Wait.combined(AMDGPU::Waitcnt::allZero(ST->hasVscnt())); + Wait = Wait.combined( + AMDGPU::Waitcnt::allZero(ST->hasExtendedWaitCounts(), ST->hasVscnt())); } // TODO: Remove this work-around, enable the assert for Bug 457939 @@ -1240,7 +1843,7 @@ bool SIInsertWaitcnts::generateWaitcntInstBefore(MachineInstr &MI, // independent of target. if (readsVCCZ(MI) && ST->hasReadVCCZBug()) { if (ScoreBrackets.hasPendingEvent(SMEM_ACCESS)) { - Wait.LgkmCnt = 0; + Wait.DsCnt = 0; } } @@ -1248,35 +1851,54 @@ bool SIInsertWaitcnts::generateWaitcntInstBefore(MachineInstr &MI, ScoreBrackets.simplifyWaitcnt(Wait); if (ForceEmitZeroWaitcnts) - Wait = AMDGPU::Waitcnt::allZeroExceptVsCnt(); + Wait = AMDGPU::Waitcnt::allZeroExceptVsCnt(ST->hasExtendedWaitCounts()); - if (ForceEmitWaitcnt[VM_CNT]) - Wait.VmCnt = 0; + if (ForceEmitWaitcnt[LOAD_CNT]) + Wait.LoadCnt = 0; if (ForceEmitWaitcnt[EXP_CNT]) Wait.ExpCnt = 0; - if (ForceEmitWaitcnt[LGKM_CNT]) - Wait.LgkmCnt = 0; + if (ForceEmitWaitcnt[DS_CNT]) + Wait.DsCnt = 0; + if (ForceEmitWaitcnt[SAMPLE_CNT]) + Wait.SampleCnt = 0; + if (ForceEmitWaitcnt[BVH_CNT]) + Wait.BvhCnt = 0; + if (ForceEmitWaitcnt[KM_CNT]) + Wait.KmCnt = 0; if (FlushVmCnt) { - if (ScoreBrackets.hasPendingEvent(VM_CNT)) - Wait.VmCnt = 0; + if (ScoreBrackets.hasPendingEvent(LOAD_CNT)) + Wait.LoadCnt = 0; + if (ScoreBrackets.hasPendingEvent(SAMPLE_CNT)) + Wait.SampleCnt = 0; + if (ScoreBrackets.hasPendingEvent(BVH_CNT)) + Wait.BvhCnt = 0; } return generateWaitcnt(Wait, MI.getIterator(), *MI.getParent(), ScoreBrackets, OldWaitcntInstr); } -// Add a waitcnt to flush the vmcnt counter at the end of the given block if -// needed. +// Add a waitcnt to flush the LOADcnt, SAMPLEcnt and BVHcnt counters at the +// end of the given block if needed. bool SIInsertWaitcnts::generateWaitcntBlockEnd(MachineBasicBlock &Block, WaitcntBrackets &ScoreBrackets, MachineInstr *OldWaitcntInstr) { AMDGPU::Waitcnt Wait; - if (!ScoreBrackets.hasPendingEvent(VM_CNT)) + unsigned LoadCntPending = ScoreBrackets.hasPendingEvent(LOAD_CNT); + unsigned SampleCntPending = ScoreBrackets.hasPendingEvent(SAMPLE_CNT); + unsigned BvhCntPending = ScoreBrackets.hasPendingEvent(BVH_CNT); + + if (LoadCntPending == 0 && SampleCntPending == 0 && BvhCntPending == 0) return false; - Wait.VmCnt = 0; + if (LoadCntPending != 0) + Wait.LoadCnt = 0; + if (SampleCntPending != 0) + Wait.SampleCnt = 0; + if (BvhCntPending != 0) + Wait.BvhCnt = 0; return generateWaitcnt(Wait, Block.instr_end(), Block, ScoreBrackets, OldWaitcntInstr); @@ -1288,15 +1910,16 @@ bool SIInsertWaitcnts::generateWaitcnt(AMDGPU::Waitcnt Wait, WaitcntBrackets &ScoreBrackets, MachineInstr *OldWaitcntInstr) { bool Modified = false; - const DebugLoc &DL = Block.findDebugLoc(It); if (OldWaitcntInstr) // Try to merge the required wait with preexisting waitcnt instructions. // Also erase redundant waitcnt. Modified = - applyPreexistingWaitcnt(ScoreBrackets, *OldWaitcntInstr, Wait, It); - else - ScoreBrackets.applyWaitcnt(Wait); + WCG->applyPreexistingWaitcnt(ScoreBrackets, *OldWaitcntInstr, Wait, It); + + // Any counts that could have been applied to any existing waitcnt + // instructions will have been done so, now deal with any remaining. + ScoreBrackets.applyWaitcnt(Wait); // ExpCnt can be merged into VINTERP. if (Wait.ExpCnt != ~0u && It != Block.instr_end() && @@ -1309,35 +1932,13 @@ bool SIInsertWaitcnts::generateWaitcnt(AMDGPU::Waitcnt Wait, } Wait.ExpCnt = ~0u; - LLVM_DEBUG(dbgs() << "generateWaitcntInstBefore\n" + LLVM_DEBUG(dbgs() << "generateWaitcnt\n" << "Update Instr: " << *It); } - // Build new waitcnt instructions unless no wait is needed or the old waitcnt - // instruction was modified to handle the required wait. - if (Wait.hasWaitExceptVsCnt()) { - unsigned Enc = AMDGPU::encodeWaitcnt(IV, Wait); - [[maybe_unused]] auto SWaitInst = - BuildMI(Block, It, DL, TII->get(AMDGPU::S_WAITCNT)).addImm(Enc); + if (WCG->createNewWaitcnt(Block, It, Wait)) Modified = true; - LLVM_DEBUG(dbgs() << "generateWaitcnt\n"; - if (It != Block.instr_end()) dbgs() << "Old Instr: " << *It; - dbgs() << "New Instr: " << *SWaitInst << '\n'); - } - - if (Wait.hasWaitVsCnt()) { - assert(ST->hasVscnt()); - - [[maybe_unused]] auto SWaitInst = BuildMI(Block, It, DL, TII->get(AMDGPU::S_WAITCNT_VSCNT)) - .addReg(AMDGPU::SGPR_NULL, RegState::Undef) - .addImm(Wait.VsCnt); - Modified = true; - - LLVM_DEBUG(dbgs() << "generateWaitcnt\n"; - if (It != Block.instr_end()) dbgs() << "Old Instr: " << *It; - dbgs() << "New Instr: " << *SWaitInst << '\n'); - } return Modified; } @@ -1435,7 +2036,8 @@ void SIInsertWaitcnts::updateEventWaitcntAfter(MachineInstr &Inst, // Now look at the instruction opcode. If it is a memory access // instruction, update the upper-bound of the appropriate counter's // bracket and the destination operand scores. - // TODO: Use the (TSFlags & SIInstrFlags::LGKM_CNT) property everywhere. + // TODO: Use the (TSFlags & SIInstrFlags::DS_CNT) property everywhere. + if (TII->isDS(Inst) && TII->usesLGKM_CNT(Inst)) { if (TII->isAlwaysGDS(Inst.getOpcode()) || TII->hasModifiersSet(Inst, AMDGPU::OpName::gds)) { @@ -1486,7 +2088,8 @@ void SIInsertWaitcnts::updateEventWaitcntAfter(MachineInstr &Inst, } else if (Inst.isCall()) { if (callWaitsOnFunctionReturn(Inst)) { // Act as a wait on everything - ScoreBrackets->applyWaitcnt(AMDGPU::Waitcnt::allZeroExceptVsCnt()); + ScoreBrackets->applyWaitcnt( + AMDGPU::Waitcnt::allZeroExceptVsCnt(ST->hasExtendedWaitCounts())); ScoreBrackets->setStateOnFunctionEntryOrReturn(); } else { // May need to way wait for anything. @@ -1546,7 +2149,7 @@ bool WaitcntBrackets::merge(const WaitcntBrackets &Other) { VgprUB = std::max(VgprUB, Other.VgprUB); SgprUB = std::max(SgprUB, Other.SgprUB); - for (auto T : inst_counter_types()) { + for (auto T : inst_counter_types(MaxCounter)) { // Merge event flags for this counter const unsigned OldEvents = PendingEvents & WaitEventMaskForInst[T]; const unsigned OtherEvents = Other.PendingEvents & WaitEventMaskForInst[T]; @@ -1574,7 +2177,7 @@ bool WaitcntBrackets::merge(const WaitcntBrackets &Other) { for (int J = 0; J <= VgprUB; J++) StrictDom |= mergeScore(M, VgprScores[T][J], Other.VgprScores[T][J]); - if (T == LGKM_CNT) { + if (T == SmemAccessCounter) { for (int J = 0; J <= SgprUB; J++) StrictDom |= mergeScore(M, SgprScores[J], Other.SgprScores[J]); } @@ -1590,10 +2193,13 @@ bool WaitcntBrackets::merge(const WaitcntBrackets &Other) { } static bool isWaitInstr(MachineInstr &Inst) { - auto Opcode = Inst.getOpcode(); - return SIInstrInfo::isWaitcnt(Opcode) || - (SIInstrInfo::isWaitcntVsCnt(Opcode) && Inst.getOperand(0).isReg() && - Inst.getOperand(0).getReg() == AMDGPU::SGPR_NULL); + unsigned Opcode = SIInstrInfo::getNonSoftWaitcntOpcode(Inst.getOpcode()); + return Opcode == AMDGPU::S_WAITCNT || + (Opcode == AMDGPU::S_WAITCNT_VSCNT && Inst.getOperand(0).isReg() && + Inst.getOperand(0).getReg() == AMDGPU::SGPR_NULL) || + Opcode == AMDGPU::S_WAIT_LOADCNT_DSCNT || + Opcode == AMDGPU::S_WAIT_STORECNT_DSCNT || + counterTypeForInstr(Opcode).has_value(); } // Generate s_waitcnt instructions where needed. @@ -1699,8 +2305,8 @@ bool SIInsertWaitcnts::insertWaitcntInBlock(MachineFunction &MF, // an S_WAITCNT vmcnt(0) if (RequireCheckResourceType(Inst, context)) { // Force the score to as if an S_WAITCNT vmcnt(0) is emitted. - ScoreBrackets->setScoreLB(VM_CNT, - ScoreBrackets->getScoreUB(VM_CNT)); + ScoreBrackets->setScoreLB(LOAD_CNT, + ScoreBrackets->getScoreUB(LOAD_CNT)); } #endif @@ -1802,7 +2408,12 @@ bool SIInsertWaitcnts::shouldFlushVmCnt(MachineLoop *ML, VgprUse.insert(RegNo); // If at least one of Op's registers is in the score brackets, the // value is likely loaded outside of the loop. - if (Brackets.getRegScore(RegNo, VM_CNT) > Brackets.getScoreLB(VM_CNT)) { + if (Brackets.getRegScore(RegNo, LOAD_CNT) > + Brackets.getScoreLB(LOAD_CNT) || + Brackets.getRegScore(RegNo, SAMPLE_CNT) > + Brackets.getScoreLB(SAMPLE_CNT) || + Brackets.getRegScore(RegNo, BVH_CNT) > + Brackets.getScoreLB(BVH_CNT)) { UsesVgprLoadedOutside = true; break; } @@ -1830,23 +2441,48 @@ bool SIInsertWaitcnts::runOnMachineFunction(MachineFunction &MF) { TII = ST->getInstrInfo(); TRI = &TII->getRegisterInfo(); MRI = &MF.getRegInfo(); - IV = AMDGPU::getIsaVersion(ST->getCPU()); const SIMachineFunctionInfo *MFI = MF.getInfo(); MLI = &getAnalysis(); PDT = &getAnalysis(); + if (auto AAR = getAnalysisIfAvailable()) + AA = &AAR->getAAResults(); + + AMDGPU::IsaVersion IV = AMDGPU::getIsaVersion(ST->getCPU()); + + if (ST->hasExtendedWaitCounts()) { + MaxCounter = NUM_EXTENDED_INST_CNTS; + WCGGFX12Plus = WaitcntGeneratorGFX12Plus(ST, MaxCounter); + WCG = &WCGGFX12Plus; + } else { + MaxCounter = NUM_NORMAL_INST_CNTS; + WCGPreGFX12 = WaitcntGeneratorPreGFX12(ST); + WCG = &WCGPreGFX12; + } ForceEmitZeroWaitcnts = ForceEmitZeroFlag; for (auto T : inst_counter_types()) ForceEmitWaitcnt[T] = false; + const unsigned *WaitEventMaskForInst = WCG->getWaitEventMask(); + + SmemAccessCounter = eventCounter(WaitEventMaskForInst, SMEM_ACCESS); + OptNone = MF.getFunction().hasOptNone() || MF.getTarget().getOptLevel() == CodeGenOptLevel::None; HardwareLimits Limits = {}; - Limits.VmcntMax = AMDGPU::getVmcntBitMask(IV); + if (ST->hasExtendedWaitCounts()) { + Limits.LoadcntMax = AMDGPU::getLoadcntBitMask(IV); + Limits.DscntMax = AMDGPU::getDscntBitMask(IV); + } else { + Limits.LoadcntMax = AMDGPU::getVmcntBitMask(IV); + Limits.DscntMax = AMDGPU::getLgkmcntBitMask(IV); + } Limits.ExpcntMax = AMDGPU::getExpcntBitMask(IV); - Limits.LgkmcntMax = AMDGPU::getLgkmcntBitMask(IV); - Limits.VscntMax = ST->hasVscnt() ? 63 : 0; + Limits.StorecntMax = AMDGPU::getStorecntBitMask(IV); + Limits.SamplecntMax = AMDGPU::getSamplecntBitMask(IV); + Limits.BvhcntMax = AMDGPU::getBvhcntBitMask(IV); + Limits.KmcntMax = AMDGPU::getKmcntBitMask(IV); unsigned NumVGPRsMax = ST->getAddressableNumVGPRs(); unsigned NumSGPRsMax = ST->getAddressableNumSGPRs(); @@ -1864,6 +2500,9 @@ bool SIInsertWaitcnts::runOnMachineFunction(MachineFunction &MF) { BlockInfos.clear(); bool Modified = false; + MachineBasicBlock &EntryBB = MF.front(); + MachineBasicBlock::iterator I = EntryBB.begin(); + if (!MFI->isEntryFunction()) { // Wait for any outstanding memory operations that the input registers may // depend on. We can't track them and it's better to do the wait after the @@ -1871,15 +2510,28 @@ bool SIInsertWaitcnts::runOnMachineFunction(MachineFunction &MF) { // TODO: Could insert earlier and schedule more liberally with operations // that only use caller preserved registers. - MachineBasicBlock &EntryBB = MF.front(); - MachineBasicBlock::iterator I = EntryBB.begin(); for (MachineBasicBlock::iterator E = EntryBB.end(); I != E && (I->isPHI() || I->isMetaInstruction()); ++I) ; - BuildMI(EntryBB, I, DebugLoc(), TII->get(AMDGPU::S_WAITCNT)).addImm(0); - auto NonKernelInitialState = - std::make_unique(ST, Limits, Encoding); + if (ST->hasExtendedWaitCounts()) { + BuildMI(EntryBB, I, DebugLoc(), TII->get(AMDGPU::S_WAIT_LOADCNT_DSCNT)) + .addImm(0); + for (auto CT : inst_counter_types(NUM_EXTENDED_INST_CNTS)) { + if (CT == LOAD_CNT || CT == DS_CNT || CT == STORE_CNT) + continue; + + BuildMI(EntryBB, I, DebugLoc(), + TII->get(instrsForExtendedCounterTypes[CT])) + .addImm(0); + } + } else { + BuildMI(EntryBB, I, DebugLoc(), TII->get(AMDGPU::S_WAITCNT)).addImm(0); + } + + auto NonKernelInitialState = std::make_unique( + ST, MaxCounter, Limits, Encoding, WaitEventMaskForInst, + SmemAccessCounter); NonKernelInitialState->setStateOnFunctionEntryOrReturn(); BlockInfos[&EntryBB].Incoming = std::move(NonKernelInitialState); @@ -1910,9 +2562,12 @@ bool SIInsertWaitcnts::runOnMachineFunction(MachineFunction &MF) { *Brackets = *BI.Incoming; } else { if (!Brackets) - Brackets = std::make_unique(ST, Limits, Encoding); + Brackets = std::make_unique( + ST, MaxCounter, Limits, Encoding, WaitEventMaskForInst, + SmemAccessCounter); else - *Brackets = WaitcntBrackets(ST, Limits, Encoding); + *Brackets = WaitcntBrackets(ST, MaxCounter, Limits, Encoding, + WaitEventMaskForInst, SmemAccessCounter); } Modified |= insertWaitcntInBlock(MF, *MBB, *Brackets); diff --git a/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp b/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp index e50f5f28e03..f4ca27808a3 100644 --- a/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp +++ b/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp @@ -2410,13 +2410,22 @@ bool SIInstrInfo::expandPostRAPseudo(MachineInstr &MI) const { // the encoding of $symbol starts 12 bytes after the start of the s_add_u32 // instruction. + int64_t Adjust = 0; + if (ST.hasGetPCZeroExtension()) { + // Fix up hardware that does not sign-extend the 48-bit PC value by + // inserting: s_sext_i32_i16 reghi, reghi + Bundler.append( + BuildMI(MF, DL, get(AMDGPU::S_SEXT_I32_I16), RegHi).addReg(RegHi)); + Adjust += 4; + } + if (OpLo.isGlobal()) - OpLo.setOffset(OpLo.getOffset() + 4); + OpLo.setOffset(OpLo.getOffset() + Adjust + 4); Bundler.append( BuildMI(MF, DL, get(AMDGPU::S_ADD_U32), RegLo).addReg(RegLo).add(OpLo)); if (OpHi.isGlobal()) - OpHi.setOffset(OpHi.getOffset() + 12); + OpHi.setOffset(OpHi.getOffset() + Adjust + 12); Bundler.append(BuildMI(MF, DL, get(AMDGPU::S_ADDC_U32), RegHi) .addReg(RegHi) .add(OpHi)); @@ -2480,6 +2489,19 @@ bool SIInstrInfo::expandPostRAPseudo(MachineInstr &MI) const { case AMDGPU::S_MUL_I64_I32_PSEUDO: MI.setDesc(get(AMDGPU::S_MUL_U64)); break; + + case AMDGPU::S_GETPC_B64_pseudo: + MI.setDesc(get(AMDGPU::S_GETPC_B64)); + if (ST.hasGetPCZeroExtension()) { + Register Dst = MI.getOperand(0).getReg(); + Register DstHi = RI.getSubReg(Dst, AMDGPU::sub1); + // Fix up hardware that does not sign-extend the 48-bit PC value by + // inserting: s_sext_i32_i16 dsthi, dsthi + BuildMI(MBB, std::next(MI.getIterator()), DL, get(AMDGPU::S_SEXT_I32_I16), + DstHi) + .addReg(DstHi); + } + break; } return true; } @@ -5280,7 +5302,8 @@ unsigned SIInstrInfo::getVALUOp(const MachineInstr &MI) const { return ST.useRealTrue16Insts() ? AMDGPU::V_CEIL_F16_t16_e64 : AMDGPU::V_CEIL_F16_fake16_e64; case AMDGPU::S_FLOOR_F16: - return AMDGPU::V_FLOOR_F16_fake16_e64; + return ST.useRealTrue16Insts() ? AMDGPU::V_FLOOR_F16_t16_e64 + : AMDGPU::V_FLOOR_F16_fake16_e64; case AMDGPU::S_TRUNC_F16: return AMDGPU::V_TRUNC_F16_fake16_e64; case AMDGPU::S_RNDNE_F16: @@ -8756,6 +8779,7 @@ SIInstrInfo::getSerializableMachineMemOperandTargetFlags() const { static const std::pair TargetFlags[] = { {MONoClobber, "amdgpu-noclobber"}, + {MOLastUse, "amdgpu-last-use"}, }; return ArrayRef(TargetFlags); @@ -8944,8 +8968,9 @@ bool SIInstrInfo::splitMUBUFOffset(uint32_t Imm, uint32_t &SOffset, // Depending on the used address space and instructions, some immediate offsets // are allowed and some are not. -// In general, flat instruction offsets can only be non-negative, global and -// scratch instruction offsets can also be negative. +// Pre-GFX12, flat instruction offsets can only be non-negative, global and +// scratch instruction offsets can also be negative. On GFX12, offsets can be +// negative for all variants. // // There are several bugs related to these offsets: // On gfx10.1, flat instructions that go into the global address space cannot @@ -9076,8 +9101,7 @@ bool SIInstrInfo::isAsmOnlyOpcode(int MCOp) const { } int SIInstrInfo::pseudoToMCOpcode(int Opcode) const { - if (SIInstrInfo::isSoftWaitcnt(Opcode)) - Opcode = SIInstrInfo::getNonSoftWaitcntOpcode(Opcode); + Opcode = SIInstrInfo::getNonSoftWaitcntOpcode(Opcode); unsigned Gen = subtargetEncodingFamily(ST); @@ -9113,12 +9137,6 @@ int SIInstrInfo::pseudoToMCOpcode(int Opcode) const { int MCOp = AMDGPU::getMCOpcode(Opcode, Gen); - // TODO-GFX12: Remove this. - // Hack to allow some GFX12 codegen tests to run before all the encodings are - // implemented. - if (MCOp == (uint16_t)-1 && Gen == SIEncodingFamily::GFX12) - MCOp = AMDGPU::getMCOpcode(Opcode, SIEncodingFamily::GFX11); - // -1 means that Opcode is already a native instruction. if (MCOp == -1) return Opcode; diff --git a/llvm/lib/Target/AMDGPU/SIInstrInfo.h b/llvm/lib/Target/AMDGPU/SIInstrInfo.h index 37ee159362a..fc85b089aa4 100644 --- a/llvm/lib/Target/AMDGPU/SIInstrInfo.h +++ b/llvm/lib/Target/AMDGPU/SIInstrInfo.h @@ -41,6 +41,10 @@ class ScheduleHazardRecognizer; static const MachineMemOperand::Flags MONoClobber = MachineMemOperand::MOTargetFlag1; +/// Mark the MMO of a load as the last use. +static const MachineMemOperand::Flags MOLastUse = + MachineMemOperand::MOTargetFlag2; + /// Utility to store machine instructions worklist. struct SIInstrWorklist { SIInstrWorklist() = default; @@ -905,29 +909,24 @@ public: } static unsigned getNonSoftWaitcntOpcode(unsigned Opcode) { - if (isWaitcnt(Opcode)) + switch (Opcode) { + case AMDGPU::S_WAITCNT_soft: return AMDGPU::S_WAITCNT; - - if (isWaitcntVsCnt(Opcode)) + case AMDGPU::S_WAITCNT_VSCNT_soft: return AMDGPU::S_WAITCNT_VSCNT; - - llvm_unreachable("Expected opcode S_WAITCNT/S_WAITCNT_VSCNT"); - } - - static bool isWaitcnt(unsigned Opcode) { - return Opcode == AMDGPU::S_WAITCNT || Opcode == AMDGPU::S_WAITCNT_soft; - } - - static bool isWaitcntVsCnt(unsigned Opcode) { - return Opcode == AMDGPU::S_WAITCNT_VSCNT || - Opcode == AMDGPU::S_WAITCNT_VSCNT_soft; - } - - // "Soft" waitcnt instructions can be relaxed/optimized out by - // SIInsertWaitcnts. - static bool isSoftWaitcnt(unsigned Opcode) { - return Opcode == AMDGPU::S_WAITCNT_soft || - Opcode == AMDGPU::S_WAITCNT_VSCNT_soft; + case AMDGPU::S_WAIT_LOADCNT_soft: + return AMDGPU::S_WAIT_LOADCNT; + case AMDGPU::S_WAIT_STORECNT_soft: + return AMDGPU::S_WAIT_STORECNT; + case AMDGPU::S_WAIT_SAMPLECNT_soft: + return AMDGPU::S_WAIT_SAMPLECNT; + case AMDGPU::S_WAIT_BVHCNT_soft: + return AMDGPU::S_WAIT_BVHCNT; + case AMDGPU::S_WAIT_DSCNT_soft: + return AMDGPU::S_WAIT_DSCNT; + default: + return Opcode; + } } bool isVGPRCopy(const MachineInstr &MI) const { diff --git a/llvm/lib/Target/AMDGPU/SIInstrInfo.td b/llvm/lib/Target/AMDGPU/SIInstrInfo.td index 04c92155f5a..a6820544f4b 100644 --- a/llvm/lib/Target/AMDGPU/SIInstrInfo.td +++ b/llvm/lib/Target/AMDGPU/SIInstrInfo.td @@ -41,10 +41,29 @@ def SIEncodingFamily { def AMDGPUclamp : SDNode<"AMDGPUISD::CLAMP", SDTFPUnaryOp>; -def SIsbuffer_load : SDNode<"AMDGPUISD::SBUFFER_LOAD", - SDTypeProfile<1, 3, [SDTCisVT<1, v4i32>, SDTCisVT<2, i32>, SDTCisVT<3, i32>]>, - [SDNPMayLoad, SDNPMemOperand] ->; +def SDTSBufferLoad : SDTypeProfile<1, 3, + [ // vdata + SDTCisVT<1, v4i32>, // rsrc + SDTCisVT<2, i32>, // offset(imm) + SDTCisVT<3, i32>]>; // cachepolicy + +def SIsbuffer_load : SDNode<"AMDGPUISD::SBUFFER_LOAD", SDTSBufferLoad, + [SDNPMayLoad, SDNPMemOperand]>; + +def SIsbuffer_load_byte : SDNode<"AMDGPUISD::SBUFFER_LOAD_BYTE", SDTSBufferLoad, + [SDNPMayLoad, SDNPMemOperand]>; + +def SIsbuffer_load_ubyte + : SDNode<"AMDGPUISD::SBUFFER_LOAD_UBYTE", SDTSBufferLoad, + [SDNPMayLoad, SDNPMemOperand]>; + +def SIsbuffer_load_short + : SDNode<"AMDGPUISD::SBUFFER_LOAD_SHORT", SDTSBufferLoad, + [SDNPMayLoad, SDNPMemOperand]>; + +def SIsbuffer_load_ushort + : SDNode<"AMDGPUISD::SBUFFER_LOAD_USHORT", SDTSBufferLoad, + [SDNPMayLoad, SDNPMemOperand]>; def SIds_ordered_count : SDNode<"AMDGPUISD::DS_ORDERED_COUNT", SDTypeProfile<1, 2, [SDTCisVT<0, i32>, SDTCisVT<1, i32>, SDTCisVT<2, i16>]>, @@ -195,8 +214,10 @@ defm SIbuffer_atomic_inc : SDBufferAtomic <"AMDGPUISD::BUFFER_ATOMIC_INC">; defm SIbuffer_atomic_dec : SDBufferAtomic <"AMDGPUISD::BUFFER_ATOMIC_DEC">; defm SIbuffer_atomic_csub : SDBufferAtomic <"AMDGPUISD::BUFFER_ATOMIC_CSUB">; defm SIbuffer_atomic_fadd : SDBufferAtomic <"AMDGPUISD::BUFFER_ATOMIC_FADD">; +defm SIbuffer_atomic_fadd_bf16 : SDBufferAtomic <"AMDGPUISD::BUFFER_ATOMIC_FADD_BF16">; defm SIbuffer_atomic_fmin : SDBufferAtomic <"AMDGPUISD::BUFFER_ATOMIC_FMIN">; defm SIbuffer_atomic_fmax : SDBufferAtomic <"AMDGPUISD::BUFFER_ATOMIC_FMAX">; +defm SIbuffer_atomic_cond_sub_u32 : SDBufferAtomic <"AMDGPUISD::BUFFER_ATOMIC_COND_SUB_U32">; def SIbuffer_atomic_cmpswap : SDNode <"AMDGPUISD::BUFFER_ATOMIC_CMPSWAP", SDTypeProfile<1, 9, @@ -281,49 +302,10 @@ def SIfptrunc_round_downward : SDNode<"AMDGPUISD::FPTRUNC_ROUND_DOWNWARD", // ValueType helpers //===----------------------------------------------------------------------===// -// Returns 1 if the source arguments have modifiers, 0 if they do not. -class isFloatType { - bit ret = !or(!eq(SrcVT.Value, f16.Value), - !eq(SrcVT.Value, f32.Value), - !eq(SrcVT.Value, f64.Value), - !eq(SrcVT.Value, v2f16.Value), - !eq(SrcVT.Value, v4f16.Value), - !eq(SrcVT.Value, v8f16.Value), - !eq(SrcVT.Value, v16f16.Value), - !eq(SrcVT.Value, v2f32.Value), - !eq(SrcVT.Value, v4f32.Value), - !eq(SrcVT.Value, v8f32.Value), - !eq(SrcVT.Value, v2f64.Value), - !eq(SrcVT.Value, v4f64.Value)); -} - -// XXX - do v2i16 instructions? class isIntType { - bit ret = !or(!eq(SrcVT.Value, i8.Value), - !eq(SrcVT.Value, i16.Value), - !eq(SrcVT.Value, i32.Value), - !eq(SrcVT.Value, i64.Value), - !eq(SrcVT.Value, v4i16.Value), - !eq(SrcVT.Value, v8i16.Value), - !eq(SrcVT.Value, v16i16.Value), - !eq(SrcVT.Value, v2i32.Value), - !eq(SrcVT.Value, v4i32.Value), - !eq(SrcVT.Value, v8i32.Value)); + bit ret = !and(SrcVT.isInteger, !ne(SrcVT.Value, i1.Value)); } -class isPackedType { - bit ret = !or(!eq(SrcVT.Value, v2i16.Value), - !eq(SrcVT.Value, v2f16.Value), - !eq(SrcVT.Value, v4f16.Value), - !eq(SrcVT.Value, v2i32.Value), - !eq(SrcVT.Value, v2f32.Value), - !eq(SrcVT.Value, v4i32.Value), - !eq(SrcVT.Value, v4f32.Value), - !eq(SrcVT.Value, v8i32.Value), - !eq(SrcVT.Value, v8f32.Value)); -} - - //===----------------------------------------------------------------------===// // PatFrags for global memory operations //===----------------------------------------------------------------------===// @@ -806,12 +788,9 @@ class bitextract_imm : SDNodeXFormgetTargetConstant(Bit, SDLoc(N), MVT::i1); }]>; -def SIMM16bit : ImmLeaf (Imm);}] ->; - -def UIMM16bit : ImmLeaf (Imm);}] +def SIMM16bit : TImmLeaf (Imm) || isUInt<16>(Imm);}], + as_i16timm >; def i64imm_32bit : ImmLeafgetTargetConstant(Swizzle, SDLoc(N), MVT::i8); }]>; -def set_glc : SDNodeXFormgetTargetConstant(N->getZExtValue() | AMDGPU::CPol::GLC, SDLoc(N), MVT::i8); +def extract_cpol_set_glc : SDNodeXFormgetZExtValue() & (Subtarget->getGeneration() >= AMDGPUSubtarget::GFX12 + ? AMDGPU::CPol::ALL + : AMDGPU::CPol::ALL_pregfx12); + return CurDAG->getTargetConstant(cpol | AMDGPU::CPol::GLC, SDLoc(N), MVT::i8); }]>; //===----------------------------------------------------------------------===// @@ -993,7 +975,7 @@ def ExpSrc3 : RegisterOperand { class SDWASrc : RegisterOperand { let OperandNamespace = "AMDGPU"; - string Type = !if(isFloatType.ret, "FP", "INT"); + string Type = !if(vt.isFP, "FP", "INT"); let OperandType = "OPERAND_REG_INLINE_C_"#Type#vt.Size; let DecoderMethod = "decodeSDWASrc"#vt.Size; let EncoderMethod = "getSDWASrcEncoding"; @@ -1241,17 +1223,20 @@ def FPVRegInputModsMatchClass : AsmOperandClass { let PredicateMethod = "isVRegWithInputMods"; } -def FPT16VRegInputModsMatchClass : AsmOperandClass { - let Name = "T16VRegWithFPInputMods"; +class FPT16VRegInputModsMatchClass : AsmOperandClass { + let Name = !if(IsFake16, "Fake16VRegWithFPInputMods", + "T16VRegWithFPInputMods"); let ParserMethod = "parseRegWithFPInputMods"; - let PredicateMethod = "isT16VRegWithInputMods"; + let PredicateMethod = "isT16VRegWithInputMods<" # + !if(IsFake16, "true", "false") # ">"; } def FPVRegInputMods : InputMods { let PrintMethod = "printOperandAndFPInputMods"; } -def FPT16VRegInputMods : InputMods { +class FPT16VRegInputMods + : InputMods > { let PrintMethod = "printOperandAndFPInputMods"; } @@ -1283,13 +1268,16 @@ def IntVRegInputModsMatchClass : AsmOperandClass { let PredicateMethod = "isVRegWithInputMods"; } -def IntT16VRegInputModsMatchClass : AsmOperandClass { - let Name = "T16VRegWithIntInputMods"; +class IntT16VRegInputModsMatchClass : AsmOperandClass { + let Name = !if(IsFake16, "Fake16VRegWithIntInputMods", + "T16VRegWithIntInputMods"); let ParserMethod = "parseRegWithIntInputMods"; - let PredicateMethod = "isT16VRegWithInputMods"; + let PredicateMethod = "isT16VRegWithInputMods<" # + !if(IsFake16, "true", "false") # ">"; } -def IntT16VRegInputMods : InputMods { +class IntT16VRegInputMods + : InputMods > { let PrintMethod = "printOperandAndIntInputMods"; } @@ -1353,7 +1341,7 @@ def VOP3OMods : ComplexPattern; def VOP3PMods : ComplexPattern; def VOP3PModsDOT : ComplexPattern; -def DotIUVOP3PMods : ComplexPattern; +def VOP3PModsNeg : ComplexPattern; def WMMAOpSelVOP3PMods : ComplexPattern; def VOP3OpSel : ComplexPattern; @@ -1489,20 +1477,18 @@ class getSDWADstForVT { // Returns the register class to use for source 0 of VOP[12C] // instructions for the given VT. class getVOPSrc0ForVT { - bit isFP = isFloatType.ret; - RegisterOperand ret = - !if(isFP, + !if(VT.isFP, !if(!eq(VT.Size, 64), VSrc_f64, - !if(!eq(VT.Value, f16.Value), + !if(!or(!eq(VT.Value, f16.Value), !eq(VT.Value, bf16.Value)), !if(IsTrue16, !if(IsFake16, VSrcFake16_f16_Lo128, VSrcT_f16_Lo128), VSrc_f16 ), - !if(!eq(VT.Value, v2f16.Value), + !if(!or(!eq(VT.Value, v2f16.Value), !eq(VT.Value, v2bf16.Value)), VSrc_v2f16, - !if(!eq(VT.Value, v4f16.Value), + !if(!or(!eq(VT.Value, v4f16.Value), !eq(VT.Value, v4bf16.Value)), AVSrc_64, VSrc_f32 ) @@ -1530,43 +1516,33 @@ class getSOPSrcForVT { } // Returns the vreg register class to use for source operand given VT -class getVregSrcForVT { - RegisterClass ret = !if(!eq(VT.Size, 128), VReg_128, - !if(!eq(VT.Size, 96), VReg_96, - !if(!eq(VT.Size, 64), VReg_64, - !if(!eq(VT.Size, 48), VReg_64, - VGPR_32)))); -} - -class getVregSrcForVT_t16 { - RegisterClass ret = !if(!eq(VT.Size, 128), VReg_128, - !if(!eq(VT.Size, 96), VReg_96, - !if(!eq(VT.Size, 64), VReg_64, - !if(!eq(VT.Size, 48), VReg_64, - !if(!eq(VT.Size, 16), - !if(IsFake16, VGPR_32_Lo128, VGPR_16_Lo128), - VGPR_32))))); - - RegisterOperand op = !if (!and(!eq(VT.Size, 16), !not(IsFake16)), - VGPRSrc_16_Lo128, RegisterOperand); +class getVregSrcForVT { + RegisterOperand ret = + !if (!eq(VT.Size, 128), RegisterOperand, + !if (!eq(VT.Size, 96), RegisterOperand, + !if (!eq(VT.Size, 64), RegisterOperand, + !if (!eq(VT.Size, 48), RegisterOperand, + !if (!eq(VT.Size, 16), + !if (IsTrue16, + !if (IsFake16, VGPRSrc_32_Lo128, VGPRSrc_16_Lo128), + RegisterOperand), + RegisterOperand))))); } class getSDWASrcForVT { - bit isFP = isFloatType.ret; RegisterOperand retFlt = !if(!eq(VT.Size, 16), SDWASrc_f16, SDWASrc_f32); RegisterOperand retInt = !if(!eq(VT.Size, 16), SDWASrc_i16, SDWASrc_i32); - RegisterOperand ret = !if(isFP, retFlt, retInt); + RegisterOperand ret = !if(VT.isFP, retFlt, retInt); } // Returns the register class to use for sources of VOP3 instructions for the // given VT. class getVOP3SrcForVT { - bit isFP = isFloatType.ret; RegisterOperand ret = !if(!eq(VT.Size, 128), VRegSrc_128, !if(!eq(VT.Size, 64), - !if(isFP, + !if(VT.isFP, !if(!eq(VT.Value, v2f32.Value), VSrc_v2f32, VSrc_f64), @@ -1575,12 +1551,12 @@ class getVOP3SrcForVT { VSrc_b64)), !if(!eq(VT.Value, i1.Value), SSrc_i1, - !if(isFP, - !if(!eq(VT.Value, f16.Value), + !if(VT.isFP, + !if(!or(!eq(VT.Value, f16.Value), !eq(VT.Value, bf16.Value)), !if(IsTrue16, VSrcT_f16, VSrc_f16), - !if(!eq(VT.Value, v2f16.Value), + !if(!or(!eq(VT.Value, v2f16.Value), !eq(VT.Value, v2bf16.Value)), VSrc_v2f16, - !if(!eq(VT.Value, v4f16.Value), + !if(!or(!eq(VT.Value, v4f16.Value), !eq(VT.Value, v4bf16.Value)), AVSrc_64, VSrc_f32 ) @@ -1601,12 +1577,11 @@ class getVOP3SrcForVT { // Src2 of VOP3 DPP instructions cannot be a literal class getVOP3DPPSrcForVT { - bit isFP = isFloatType.ret; RegisterOperand ret = !if (!eq(VT.Value, i1.Value), SSrc_i1, - !if (isFP, - !if (!eq(VT.Value, f16.Value), VCSrc_f16, - !if (!eq(VT.Value, v2f16.Value), VCSrc_v2f16, VCSrc_f32)), + !if (VT.isFP, + !if (!or(!eq(VT.Value, f16.Value), !eq(VT.Value, bf16.Value)), VCSrc_f16, + !if (!or(!eq(VT.Value, v2f16.Value), !eq(VT.Value, v2bf16.Value)), VCSrc_v2f16, VCSrc_f32)), !if (!eq(VT.Value, i16.Value), VCSrc_b16, !if (!eq(VT.Value, v2i16.Value), VCSrc_v2b16, VCSrc_b32)))); @@ -1615,64 +1590,64 @@ class getVOP3DPPSrcForVT { // Float or packed int class isModifierType { bit ret = !or(!eq(SrcVT.Value, f16.Value), + !eq(SrcVT.Value, bf16.Value), !eq(SrcVT.Value, f32.Value), !eq(SrcVT.Value, f64.Value), !eq(SrcVT.Value, v2f16.Value), !eq(SrcVT.Value, v2i16.Value), + !eq(SrcVT.Value, v2bf16.Value), !eq(SrcVT.Value, v2f32.Value), !eq(SrcVT.Value, v2i32.Value), !eq(SrcVT.Value, v4f16.Value), !eq(SrcVT.Value, v4i16.Value), + !eq(SrcVT.Value, v4bf16.Value), !eq(SrcVT.Value, v4f32.Value), !eq(SrcVT.Value, v4i32.Value), !eq(SrcVT.Value, v8f16.Value), !eq(SrcVT.Value, v8i16.Value), + !eq(SrcVT.Value, v8bf16.Value), !eq(SrcVT.Value, v8f32.Value), !eq(SrcVT.Value, v8i32.Value), !eq(SrcVT.Value, v16f16.Value), - !eq(SrcVT.Value, v16i16.Value)); + !eq(SrcVT.Value, v16i16.Value), + !eq(SrcVT.Value, v16bf16.Value)); } // Return type of input modifiers operand for specified input operand class getSrcMod { - bit isFP = isFloatType.ret; - bit isPacked = isPackedType.ret; Operand ret = !if(!eq(VT.Size, 64), - !if(isFP, FP64InputMods, Int64InputMods), + !if(VT.isFP, FP64InputMods, Int64InputMods), !if(!eq(VT.Size, 16), - !if(isFP, !if(IsTrue16, FPT16InputMods, FP16InputMods), - !if(IsTrue16, IntT16InputMods, IntOpSelMods)), - !if(isFP, FP32InputMods, Int32InputMods))); + !if(VT.isFP, !if(IsTrue16, FPT16InputMods, FP16InputMods), + !if(IsTrue16, IntT16InputMods, IntOpSelMods)), + !if(VT.isFP, FP32InputMods, Int32InputMods))); } class getOpSelMod { - Operand ret = !if(!eq(VT.Value, f16.Value), FP16InputMods, IntOpSelMods); + Operand ret = !if(!or(!eq(VT.Value, f16.Value), !eq(VT.Value, bf16.Value)), + FP16InputMods, IntOpSelMods); } // Return type of input modifiers operand specified input operand for DPP class getSrcModDPP { - bit isFP = isFloatType.ret; - Operand ret = !if(isFP, FPVRegInputMods, IntVRegInputMods); + Operand ret = !if(VT.isFP, FPVRegInputMods, IntVRegInputMods); } -class getSrcModDPP_t16 { - bit isFP = isFloatType.ret; +class getSrcModDPP_t16 { Operand ret = - !if (isFP, - !if (!eq(VT.Value, f16.Value), FPT16VRegInputMods, - FPVRegInputMods), - !if (!eq(VT.Value, i16.Value), IntT16VRegInputMods, - IntVRegInputMods)); + !if (VT.isFP, + !if (!or(!eq(VT.Value, f16.Value), !eq(VT.Value, bf16.Value)), + FPT16VRegInputMods, FPVRegInputMods), + !if (!eq(VT.Value, i16.Value), + IntT16VRegInputMods, IntVRegInputMods)); } // Return type of input modifiers operand for specified input operand for DPP class getSrcModVOP3DPP { - bit isFP = isFloatType.ret; - bit isPacked = isPackedType.ret; Operand ret = - !if (isFP, - !if (!eq(VT.Value, f16.Value), FP16VCSrcInputMods, - FP32VCSrcInputMods), + !if (VT.isFP, + !if (!or(!eq(VT.Value, f16.Value), !eq(VT.Value, bf16.Value)), + FP16VCSrcInputMods, FP32VCSrcInputMods), Int32VCSrcInputMods); } @@ -1681,7 +1656,8 @@ class getSrcModSDWA { Operand ret = !if(!eq(VT.Value, f16.Value), FP16SDWAInputMods, !if(!eq(VT.Value, f32.Value), FP32SDWAInputMods, !if(!eq(VT.Value, i16.Value), Int16SDWAInputMods, - Int32SDWAInputMods))); + !if(!eq(VT.Value, bf16.Value), FP16SDWAInputMods, + Int32SDWAInputMods)))); } // Returns the input arguments for VOP[12C] instructions for the given SrcVT. @@ -1806,10 +1782,9 @@ class getInsVOP3OpSel .ret; } -class getInsDPPBase { - +class getInsDPPBase { dag ret = !if(!eq(NumSrcArgs, 0), // VOP1 without input operands (V_NOP) (ins ), @@ -1849,8 +1824,8 @@ class getInsDPPBase { dag ret = !con(getInsDPPBase.ret, @@ -1858,17 +1833,17 @@ class getInsDPP { +class getInsDPP16 { dag ret = !con(getInsDPP.ret, (ins FI:$fi)); } -class getInsDPP8 { +class getInsDPP8 { dag ret = !con(getInsDPPBase.ret, (ins dpp8:$dpp8, FI:$fi)); @@ -2273,13 +2248,13 @@ class VOPProfile _ArgVT, bit _EnableClamp = 0> { field RegisterOperand DstRCVOP3DPP = DstRC64; field RegisterOperand DstRCSDWA = getSDWADstForVT.ret; field RegisterOperand Src0RC32 = getVOPSrc0ForVT.ret; - field RegisterOperand Src1RC32 = RegisterOperand.ret>; + field RegisterOperand Src1RC32 = getVregSrcForVT.ret; field RegisterOperand Src0RC64 = getVOP3SrcForVT.ret; field RegisterOperand Src1RC64 = getVOP3SrcForVT.ret; field RegisterOperand Src2RC64 = getVOP3SrcForVT.ret; - field RegisterClass Src0DPP = getVregSrcForVT.ret; - field RegisterClass Src1DPP = getVregSrcForVT.ret; - field RegisterClass Src2DPP = getVregSrcForVT.ret; + field RegisterOperand Src0DPP = getVregSrcForVT.ret; + field RegisterOperand Src1DPP = getVregSrcForVT.ret; + field RegisterOperand Src2DPP = getVregSrcForVT.ret; field RegisterOperand Src0VOP3DPP = VGPRSrc_32; field RegisterOperand Src1VOP3DPP = getVOP3DPPSrcForVT.ret; field RegisterOperand Src2VOP3DPP = getVOP3DPPSrcForVT.ret; @@ -2313,9 +2288,9 @@ class VOPProfile _ArgVT, bit _EnableClamp = 0> { field bit HasSrc1 = !ne(Src1VT.Value, untyped.Value); field bit HasSrc2 = !ne(Src2VT.Value, untyped.Value); - field bit HasSrc0FloatMods = isFloatType.ret; - field bit HasSrc1FloatMods = isFloatType.ret; - field bit HasSrc2FloatMods = isFloatType.ret; + field bit HasSrc0FloatMods = Src0VT.isFP; + field bit HasSrc1FloatMods = Src1VT.isFP; + field bit HasSrc2FloatMods = Src2VT.isFP; field bit HasSrc0IntMods = isIntType.ret; field bit HasSrc1IntMods = isIntType.ret; @@ -2323,16 +2298,16 @@ class VOPProfile _ArgVT, bit _EnableClamp = 0> { field bit HasClamp = !or(isModifierType.ret, EnableClamp); field bit HasSDWAClamp = EmitDst; - field bit HasFPClamp = !and(isFloatType.ret, HasClamp); - field bit HasIntClamp = !if(isFloatType.ret, 0, HasClamp); + field bit HasFPClamp = !and(DstVT.isFP, HasClamp); + field bit HasIntClamp = !if(DstVT.isFP, 0, HasClamp); field bit HasClampLo = HasClamp; - field bit HasClampHi = !and(isPackedType.ret, HasClamp); + field bit HasClampHi = !and(DstVT.isVector, HasClamp); field bit HasHigh = 0; - field bit IsPacked = isPackedType.ret; + field bit IsPacked = Src0VT.isVector; field bit HasOpSel = IsPacked; - field bit HasOMod = !if(IsVOP3P, 0, isFloatType.ret); - field bit HasSDWAOMod = isFloatType.ret; + field bit HasOMod = !if(IsVOP3P, 0, DstVT.isFP); + field bit HasSDWAOMod = DstVT.isFP; field bit HasModifiers = !or(isModifierType.ret, isModifierType.ret, @@ -2465,13 +2440,13 @@ class VOPProfile_True16 : VOPProfile { let DstRC = getVALUDstForVT.ret; let DstRC64 = getVALUDstForVT.ret; let Src0RC32 = getVOPSrc0ForVT.ret; - let Src1RC32 = getVregSrcForVT_t16.op; - let Src0DPP = getVregSrcForVT_t16.ret; - let Src1DPP = getVregSrcForVT_t16.ret; - let Src2DPP = getVregSrcForVT_t16.ret; - let Src0ModDPP = getSrcModDPP_t16.ret; - let Src1ModDPP = getSrcModDPP_t16.ret; - let Src2ModDPP = getSrcModDPP_t16.ret; + let Src1RC32 = getVregSrcForVT.ret; + let Src0DPP = getVregSrcForVT.ret; + let Src1DPP = getVregSrcForVT.ret; + let Src2DPP = getVregSrcForVT.ret; + let Src0ModDPP = getSrcModDPP_t16.ret; + let Src1ModDPP = getSrcModDPP_t16.ret; + let Src2ModDPP = getSrcModDPP_t16.ret; let DstRC64 = getVALUDstForVT.ret; let Src0RC64 = getVOP3SrcForVT.ret; @@ -2487,10 +2462,10 @@ class VOPProfile_Fake16 : VOPProfile { // Most DstVT are 16-bit, but not all let DstRC = getVALUDstForVT_fake16.ret; let DstRC64 = getVALUDstForVT.ret; - let Src1RC32 = RegisterOperand.ret>; - let Src0DPP = getVregSrcForVT_t16.ret; - let Src1DPP = getVregSrcForVT_t16.ret; - let Src2DPP = getVregSrcForVT_t16.ret; + let Src1RC32 = getVregSrcForVT.ret; + let Src0DPP = getVregSrcForVT.ret; + let Src1DPP = getVregSrcForVT.ret; + let Src2DPP = getVregSrcForVT.ret; let Src0ModDPP = getSrcModDPP_t16.ret; let Src1ModDPP = getSrcModDPP_t16.ret; let Src2ModDPP = getSrcModDPP_t16.ret; diff --git a/llvm/lib/Target/AMDGPU/SIInstructions.td b/llvm/lib/Target/AMDGPU/SIInstructions.td index b4bd46d33c1..788e3162fb3 100644 --- a/llvm/lib/Target/AMDGPU/SIInstructions.td +++ b/llvm/lib/Target/AMDGPU/SIInstructions.td @@ -1862,7 +1862,10 @@ class ClampPat : GCNPat < >; def : ClampPat; +let SubtargetPredicate = isNotGFX12Plus in def : ClampPat; +let SubtargetPredicate = isGFX12Plus in +def : ClampPat; let SubtargetPredicate = NotHasTrue16BitInsts in def : ClampPat; let SubtargetPredicate = UseRealTrue16Insts in @@ -2990,10 +2993,12 @@ def : GCNPat< } // TODO: Handle fneg like other types. +let SubtargetPredicate = isNotGFX12Plus in { def : GCNPat< (fcanonicalize (f64 (VOP3Mods f64:$src, i32:$src_mods))), (V_MUL_F64_e64 0, CONST.FP64_ONE, $src_mods, $src) >; +} } // End AddedComplexity = -5 multiclass SelectCanonicalizeAsMax< @@ -3009,7 +3014,13 @@ multiclass SelectCanonicalizeAsMax< def : GCNPat< (fcanonicalize (f64 (VOP3Mods f64:$src, i32:$src_mods))), (V_MAX_F64_e64 $src_mods, $src, $src_mods, $src)> { - let OtherPredicates = f64_preds; + let OtherPredicates = !listconcat(f64_preds, [isNotGFX12Plus]); + } + + def : GCNPat< + (fcanonicalize (f64 (VOP3Mods f64:$src, i32:$src_mods))), + (V_MAX_NUM_F64_e64 $src_mods, $src, $src_mods, $src)> { + let OtherPredicates = !listconcat(f64_preds, [isGFX12Plus]); } def : GCNPat< @@ -3856,11 +3867,13 @@ def G_AMDGPU_BUFFER_ATOMIC_UMIN : BufferAtomicGenericInstruction; def G_AMDGPU_BUFFER_ATOMIC_SMAX : BufferAtomicGenericInstruction; def G_AMDGPU_BUFFER_ATOMIC_UMAX : BufferAtomicGenericInstruction; def G_AMDGPU_BUFFER_ATOMIC_AND : BufferAtomicGenericInstruction; +def G_AMDGPU_BUFFER_ATOMIC_COND_SUB_U32 : BufferAtomicGenericInstruction; def G_AMDGPU_BUFFER_ATOMIC_OR : BufferAtomicGenericInstruction; def G_AMDGPU_BUFFER_ATOMIC_XOR : BufferAtomicGenericInstruction; def G_AMDGPU_BUFFER_ATOMIC_INC : BufferAtomicGenericInstruction; def G_AMDGPU_BUFFER_ATOMIC_DEC : BufferAtomicGenericInstruction; def G_AMDGPU_BUFFER_ATOMIC_FADD : BufferAtomicGenericInstruction; +def G_AMDGPU_BUFFER_ATOMIC_FADD_BF16 : BufferAtomicGenericInstruction; def G_AMDGPU_BUFFER_ATOMIC_FMIN : BufferAtomicGenericInstruction; def G_AMDGPU_BUFFER_ATOMIC_FMAX : BufferAtomicGenericInstruction; @@ -3877,7 +3890,8 @@ def G_AMDGPU_BUFFER_ATOMIC_CMPSWAP : AMDGPUGenericInstruction { // Wrapper around llvm.amdgcn.s.buffer.load. This is mostly needed as // a workaround for the intrinsic being defined as readnone, but // really needs a memory operand. -def G_AMDGPU_S_BUFFER_LOAD : AMDGPUGenericInstruction { + +class SBufferLoadInstruction : AMDGPUGenericInstruction { let OutOperandList = (outs type0:$dst); let InOperandList = (ins type1:$rsrc, type2:$offset, untyped_imm_0:$cachepolicy); let hasSideEffects = 0; @@ -3885,6 +3899,12 @@ def G_AMDGPU_S_BUFFER_LOAD : AMDGPUGenericInstruction { let mayStore = 0; } +def G_AMDGPU_S_BUFFER_LOAD : SBufferLoadInstruction; +def G_AMDGPU_S_BUFFER_LOAD_SBYTE : SBufferLoadInstruction; +def G_AMDGPU_S_BUFFER_LOAD_UBYTE : SBufferLoadInstruction; +def G_AMDGPU_S_BUFFER_LOAD_SSHORT : SBufferLoadInstruction; +def G_AMDGPU_S_BUFFER_LOAD_USHORT : SBufferLoadInstruction; + def G_AMDGPU_S_MUL_U64_U32 : AMDGPUGenericInstruction { let OutOperandList = (outs type0:$dst); let InOperandList = (ins type0:$src0, type0:$src1); diff --git a/llvm/lib/Target/AMDGPU/SILowerSGPRSpills.cpp b/llvm/lib/Target/AMDGPU/SILowerSGPRSpills.cpp index 0ba7792ac43..4b13825040e 100644 --- a/llvm/lib/Target/AMDGPU/SILowerSGPRSpills.cpp +++ b/llvm/lib/Target/AMDGPU/SILowerSGPRSpills.cpp @@ -332,7 +332,6 @@ bool SILowerSGPRSpills::runOnMachineFunction(MachineFunction &MF) { } bool MadeChange = false; - bool NewReservedRegs = false; bool SpilledToVirtVGPRLanes = false; // TODO: CSR VGPRs will never be spilled to AGPRs. These can probably be @@ -369,8 +368,8 @@ bool SILowerSGPRSpills::runOnMachineFunction(MachineFunction &MF) { // regalloc aware CFI generation to insert new CFIs along with the // intermediate spills is implemented. There is no such support // currently exist in the LLVM compiler. - if (FuncInfo->allocateSGPRSpillToVGPRLane(MF, FI, true)) { - NewReservedRegs = true; + if (FuncInfo->allocateSGPRSpillToVGPRLane( + MF, FI, /*SpillToPhysVGPRLane=*/true)) { bool Spilled = TRI->eliminateSGPRToVGPRSpillFrameIndex( MI, FI, nullptr, Indexes, LIS, true); if (!Spilled) @@ -442,12 +441,5 @@ bool SILowerSGPRSpills::runOnMachineFunction(MachineFunction &MF) { SaveBlocks.clear(); RestoreBlocks.clear(); - // Updated the reserved registers with any physical VGPRs added for SGPR - // spills. - if (NewReservedRegs) { - for (Register Reg : FuncInfo->getWWMReservedRegs()) - MRI.reserveReg(Reg, TRI); - } - return MadeChange; } diff --git a/llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.cpp b/llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.cpp index e8142244b7d..b94d143a75e 100644 --- a/llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.cpp +++ b/llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.cpp @@ -312,6 +312,33 @@ bool SIMachineFunctionInfo::isCalleeSavedReg(const MCPhysReg *CSRegs, return false; } +void SIMachineFunctionInfo::shiftSpillPhysVGPRsToLowestRange( + MachineFunction &MF) { + const SIRegisterInfo *TRI = MF.getSubtarget().getRegisterInfo(); + MachineRegisterInfo &MRI = MF.getRegInfo(); + for (unsigned I = 0, E = SpillPhysVGPRs.size(); I < E; ++I) { + Register Reg = SpillPhysVGPRs[I]; + Register NewReg = + TRI->findUnusedRegister(MRI, &AMDGPU::VGPR_32RegClass, MF); + if (!NewReg || NewReg >= Reg) + break; + + MRI.replaceRegWith(Reg, NewReg); + + // Update various tables with the new VGPR. + SpillPhysVGPRs[I] = NewReg; + WWMReservedRegs.remove(Reg); + WWMReservedRegs.insert(NewReg); + WWMSpills.insert(std::make_pair(NewReg, WWMSpills[Reg])); + WWMSpills.erase(Reg); + + for (MachineBasicBlock &MBB : MF) { + MBB.removeLiveIn(Reg); + MBB.sortUniqueLiveIns(); + } + } +} + bool SIMachineFunctionInfo::allocateVirtualVGPRForSGPRSpills( MachineFunction &MF, int FI, unsigned LaneIndex) { MachineRegisterInfo &MRI = MF.getRegInfo(); @@ -329,13 +356,17 @@ bool SIMachineFunctionInfo::allocateVirtualVGPRForSGPRSpills( } bool SIMachineFunctionInfo::allocatePhysicalVGPRForSGPRSpills( - MachineFunction &MF, int FI, unsigned LaneIndex) { + MachineFunction &MF, int FI, unsigned LaneIndex, bool IsPrologEpilog) { const GCNSubtarget &ST = MF.getSubtarget(); const SIRegisterInfo *TRI = ST.getRegisterInfo(); MachineRegisterInfo &MRI = MF.getRegInfo(); Register LaneVGPR; if (!LaneIndex) { - LaneVGPR = TRI->findUnusedRegister(MRI, &AMDGPU::VGPR_32RegClass, MF); + // Find the highest available register if called before RA to ensure the + // lowest registers are available for allocation. The LaneVGPR, in that + // case, will be shifted back to the lowest range after VGPR allocation. + LaneVGPR = TRI->findUnusedRegister(MRI, &AMDGPU::VGPR_32RegClass, MF, + !IsPrologEpilog); if (LaneVGPR == AMDGPU::NoRegister) { // We have no VGPRs left for spilling SGPRs. Reset because we will not // partially spill the SGPR to VGPRs. @@ -359,12 +390,12 @@ bool SIMachineFunctionInfo::allocatePhysicalVGPRForSGPRSpills( return true; } -bool SIMachineFunctionInfo::allocateSGPRSpillToVGPRLane(MachineFunction &MF, - int FI, - bool IsPrologEpilog) { +bool SIMachineFunctionInfo::allocateSGPRSpillToVGPRLane( + MachineFunction &MF, int FI, bool SpillToPhysVGPRLane, + bool IsPrologEpilog) { std::vector &SpillLanes = - IsPrologEpilog ? SGPRSpillsToPhysicalVGPRLanes[FI] - : SGPRSpillsToVirtualVGPRLanes[FI]; + SpillToPhysVGPRLane ? SGPRSpillsToPhysicalVGPRLanes[FI] + : SGPRSpillsToVirtualVGPRLanes[FI]; // This has already been allocated. if (!SpillLanes.empty()) @@ -384,14 +415,15 @@ bool SIMachineFunctionInfo::allocateSGPRSpillToVGPRLane(MachineFunction &MF, assert(ST.getRegisterInfo()->spillSGPRToVGPR() && "not spilling SGPRs to VGPRs"); - unsigned &NumSpillLanes = - IsPrologEpilog ? NumPhysicalVGPRSpillLanes : NumVirtualVGPRSpillLanes; + unsigned &NumSpillLanes = SpillToPhysVGPRLane ? NumPhysicalVGPRSpillLanes + : NumVirtualVGPRSpillLanes; for (unsigned I = 0; I < NumLanes; ++I, ++NumSpillLanes) { unsigned LaneIndex = (NumSpillLanes % WaveSize); - bool Allocated = IsPrologEpilog - ? allocatePhysicalVGPRForSGPRSpills(MF, FI, LaneIndex) + bool Allocated = SpillToPhysVGPRLane + ? allocatePhysicalVGPRForSGPRSpills(MF, FI, LaneIndex, + IsPrologEpilog) : allocateVirtualVGPRForSGPRSpills(MF, FI, LaneIndex); if (!Allocated) { NumSpillLanes -= I; diff --git a/llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.h b/llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.h index dc63ae44c52..9ff66a094f9 100644 --- a/llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.h +++ b/llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.h @@ -548,7 +548,8 @@ private: bool allocateVirtualVGPRForSGPRSpills(MachineFunction &MF, int FI, unsigned LaneIndex); bool allocatePhysicalVGPRForSGPRSpills(MachineFunction &MF, int FI, - unsigned LaneIndex); + unsigned LaneIndex, + bool IsPrologEpilog); public: Register getVGPRForAGPRCopy() const { @@ -588,6 +589,7 @@ public: } ArrayRef getSGPRSpillVGPRs() const { return SpillVGPRs; } + const WWMSpillsMap &getWWMSpills() const { return WWMSpills; } const ReservedRegSet &getWWMReservedRegs() const { return WWMReservedRegs; } @@ -702,7 +704,12 @@ public: I->second.IsDead = true; } + // To bring the Physical VGPRs in the highest range allocated for CSR SGPR + // spilling into the lowest available range. + void shiftSpillPhysVGPRsToLowestRange(MachineFunction &MF); + bool allocateSGPRSpillToVGPRLane(MachineFunction &MF, int FI, + bool SpillToPhysVGPRLane = false, bool IsPrologEpilog = false); bool allocateVGPRSpillToAGPR(MachineFunction &MF, int FI, bool isAGPRtoVGPR); @@ -1041,22 +1048,6 @@ public: return WavesPerEU.second; } - /// \returns SGPR used for \p Dim's work group ID. - Register getWorkGroupIDSGPR(unsigned Dim) const { - switch (Dim) { - case 0: - assert(hasWorkGroupIDX()); - return ArgInfo.WorkGroupIDX.getRegister(); - case 1: - assert(hasWorkGroupIDY()); - return ArgInfo.WorkGroupIDY.getRegister(); - case 2: - assert(hasWorkGroupIDZ()); - return ArgInfo.WorkGroupIDZ.getRegister(); - } - llvm_unreachable("unexpected dimension"); - } - const AMDGPUGWSResourcePseudoSourceValue * getGWSPSV(const AMDGPUTargetMachine &TM) { return &GWSResourcePSV; diff --git a/llvm/lib/Target/AMDGPU/SIMemoryLegalizer.cpp b/llvm/lib/Target/AMDGPU/SIMemoryLegalizer.cpp index 6d749ad1ad2..84b9330ef96 100644 --- a/llvm/lib/Target/AMDGPU/SIMemoryLegalizer.cpp +++ b/llvm/lib/Target/AMDGPU/SIMemoryLegalizer.cpp @@ -579,11 +579,30 @@ public: }; class SIGfx12CacheControl : public SIGfx11CacheControl { +protected: + // Sets TH policy to \p Value if CPol operand is present in instruction \p MI. + // \returns Returns true if \p MI is modified, false otherwise. + bool setTH(const MachineBasicBlock::iterator MI, + AMDGPU::CPol::CPol Value) const; + // Sets Scope policy to \p Value if CPol operand is present in instruction \p + // MI. \returns Returns true if \p MI is modified, false otherwise. + bool setScope(const MachineBasicBlock::iterator MI, + AMDGPU::CPol::CPol Value) const; + public: SIGfx12CacheControl(const GCNSubtarget &ST) : SIGfx11CacheControl(ST) {} + bool insertWait(MachineBasicBlock::iterator &MI, SIAtomicScope Scope, + SIAtomicAddrSpace AddrSpace, SIMemOp Op, + bool IsCrossAddrSpaceOrdering, Position Pos) const override; + bool insertAcquire(MachineBasicBlock::iterator &MI, SIAtomicScope Scope, SIAtomicAddrSpace AddrSpace, Position Pos) const override; + + bool enableVolatileAndOrNonTemporal(MachineBasicBlock::iterator &MI, + SIAtomicAddrSpace AddrSpace, SIMemOp Op, + bool IsVolatile, + bool IsNonTemporal) const override; }; class SIMemoryLegalizer final : public MachineFunctionPass { @@ -2142,6 +2161,132 @@ bool SIGfx11CacheControl::enableVolatileAndOrNonTemporal( return Changed; } +bool SIGfx12CacheControl::setTH(const MachineBasicBlock::iterator MI, + AMDGPU::CPol::CPol Value) const { + MachineOperand *CPol = TII->getNamedOperand(*MI, OpName::cpol); + if (!CPol) + return false; + + uint64_t NewTH = Value & AMDGPU::CPol::TH; + if ((CPol->getImm() & AMDGPU::CPol::TH) != NewTH) { + CPol->setImm((CPol->getImm() & ~AMDGPU::CPol::TH) | NewTH); + return true; + } + + return false; +} + +bool SIGfx12CacheControl::setScope(const MachineBasicBlock::iterator MI, + AMDGPU::CPol::CPol Value) const { + MachineOperand *CPol = TII->getNamedOperand(*MI, OpName::cpol); + if (!CPol) + return false; + + uint64_t NewScope = Value & AMDGPU::CPol::SCOPE; + if ((CPol->getImm() & AMDGPU::CPol::SCOPE) != NewScope) { + CPol->setImm((CPol->getImm() & ~AMDGPU::CPol::SCOPE) | NewScope); + return true; + } + + return false; +} + +bool SIGfx12CacheControl::insertWait(MachineBasicBlock::iterator &MI, + SIAtomicScope Scope, + SIAtomicAddrSpace AddrSpace, SIMemOp Op, + bool IsCrossAddrSpaceOrdering, + Position Pos) const { + bool Changed = false; + + MachineBasicBlock &MBB = *MI->getParent(); + DebugLoc DL = MI->getDebugLoc(); + + bool LOADCnt = false; + bool DSCnt = false; + bool STORECnt = false; + + if (Pos == Position::AFTER) + ++MI; + + if ((AddrSpace & (SIAtomicAddrSpace::GLOBAL | SIAtomicAddrSpace::SCRATCH)) != + SIAtomicAddrSpace::NONE) { + switch (Scope) { + case SIAtomicScope::SYSTEM: + case SIAtomicScope::AGENT: + if ((Op & SIMemOp::LOAD) != SIMemOp::NONE) + LOADCnt |= true; + if ((Op & SIMemOp::STORE) != SIMemOp::NONE) + STORECnt |= true; + break; + case SIAtomicScope::WORKGROUP: + // In WGP mode the waves of a work-group can be executing on either CU of + // the WGP. Therefore need to wait for operations to complete to ensure + // they are visible to waves in the other CU as the L0 is per CU. + // Otherwise in CU mode and all waves of a work-group are on the same CU + // which shares the same L0. + if (!ST.isCuModeEnabled()) { + if ((Op & SIMemOp::LOAD) != SIMemOp::NONE) + LOADCnt |= true; + if ((Op & SIMemOp::STORE) != SIMemOp::NONE) + STORECnt |= true; + } + break; + case SIAtomicScope::WAVEFRONT: + case SIAtomicScope::SINGLETHREAD: + // The L0 cache keeps all memory operations in order for + // work-items in the same wavefront. + break; + default: + llvm_unreachable("Unsupported synchronization scope"); + } + } + + if ((AddrSpace & SIAtomicAddrSpace::LDS) != SIAtomicAddrSpace::NONE) { + switch (Scope) { + case SIAtomicScope::SYSTEM: + case SIAtomicScope::AGENT: + case SIAtomicScope::WORKGROUP: + // If no cross address space ordering then an "S_WAITCNT lgkmcnt(0)" is + // not needed as LDS operations for all waves are executed in a total + // global ordering as observed by all waves. Required if also + // synchronizing with global/GDS memory as LDS operations could be + // reordered with respect to later global/GDS memory operations of the + // same wave. + DSCnt |= IsCrossAddrSpaceOrdering; + break; + case SIAtomicScope::WAVEFRONT: + case SIAtomicScope::SINGLETHREAD: + // The LDS keeps all memory operations in order for + // the same wavefront. + break; + default: + llvm_unreachable("Unsupported synchronization scope"); + } + } + + if (LOADCnt) { + BuildMI(MBB, MI, DL, TII->get(AMDGPU::S_WAIT_BVHCNT_soft)).addImm(0); + BuildMI(MBB, MI, DL, TII->get(AMDGPU::S_WAIT_SAMPLECNT_soft)).addImm(0); + BuildMI(MBB, MI, DL, TII->get(AMDGPU::S_WAIT_LOADCNT_soft)).addImm(0); + Changed = true; + } + + if (STORECnt) { + BuildMI(MBB, MI, DL, TII->get(AMDGPU::S_WAIT_STORECNT_soft)).addImm(0); + Changed = true; + } + + if (DSCnt) { + BuildMI(MBB, MI, DL, TII->get(AMDGPU::S_WAIT_DSCNT_soft)).addImm(0); + Changed = true; + } + + if (Pos == Position::AFTER) + --MI; + + return Changed; +} + bool SIGfx12CacheControl::insertAcquire(MachineBasicBlock::iterator &MI, SIAtomicScope Scope, SIAtomicAddrSpace AddrSpace, @@ -2198,6 +2343,41 @@ bool SIGfx12CacheControl::insertAcquire(MachineBasicBlock::iterator &MI, return true; } +bool SIGfx12CacheControl::enableVolatileAndOrNonTemporal( + MachineBasicBlock::iterator &MI, SIAtomicAddrSpace AddrSpace, SIMemOp Op, + bool IsVolatile, bool IsNonTemporal) const { + + // Only handle load and store, not atomic read-modify-write instructions. + assert(MI->mayLoad() ^ MI->mayStore()); + + // Only update load and store, not LLVM IR atomic read-modify-write + // instructions. The latter are always marked as volatile so cannot sensibly + // handle it as do not want to pessimize all atomics. Also they do not support + // the nontemporal attribute. + assert(Op == SIMemOp::LOAD || Op == SIMemOp::STORE); + + bool Changed = false; + + if (IsVolatile) { + Changed |= setScope(MI, AMDGPU::CPol::SCOPE_SYS); + + // Ensure operation has completed at system scope to cause all volatile + // operations to be visible outside the program in a global order. Do not + // request cross address space as only the global address space can be + // observable outside the program, so no need to cause a waitcnt for LDS + // address space operations. + Changed |= insertWait(MI, SIAtomicScope::SYSTEM, AddrSpace, Op, false, + Position::AFTER); + } + + if (IsNonTemporal) { + // Set non-temporal hint for all cache levels. + Changed |= setTH(MI, AMDGPU::CPol::TH_NT); + } + + return Changed; +} + bool SIMemoryLegalizer::removeAtomicPseudoMIs() { if (AtomicPseudoMIs.empty()) return false; diff --git a/llvm/lib/Target/AMDGPU/SIModeRegister.cpp b/llvm/lib/Target/AMDGPU/SIModeRegister.cpp index be395d53c34..e62ad026dc5 100644 --- a/llvm/lib/Target/AMDGPU/SIModeRegister.cpp +++ b/llvm/lib/Target/AMDGPU/SIModeRegister.cpp @@ -285,7 +285,7 @@ void SIModeRegister::processBlockPhase1(MachineBasicBlock &MBB, 1; unsigned Offset = (Dst & AMDGPU::Hwreg::OFFSET_MASK_) >> AMDGPU::Hwreg::OFFSET_SHIFT_; - unsigned Mask = ((1 << Width) - 1) << Offset; + unsigned Mask = maskTrailingOnes(Width) << Offset; // If an InsertionPoint is set we will insert a setreg there. if (InsertionPoint) { diff --git a/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp b/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp index a93cf5cad41..a2cacb5cbaa 100644 --- a/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp +++ b/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp @@ -1657,8 +1657,12 @@ void SIRegisterInfo::buildSpillLoadStore( } else { MIB.addReg(SOffset, SOffsetRegState); } - MIB.addImm(Offset + RegOffset) - .addImm(0); // cpol + + MIB.addImm(Offset + RegOffset); + + bool LastUse = MMO->getFlags() & MOLastUse; + MIB.addImm(LastUse ? AMDGPU::CPol::TH_LU : 0); // cpol + if (!IsFlat) MIB.addImm(0); // swz MIB.addMemOperand(NewMMO); @@ -2241,6 +2245,7 @@ bool SIRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator MI, TII->insertScratchExecCopy(*MF, *MBB, MI, DL, MFI->getSGPRForEXECCopy(), RS->isRegUsed(AMDGPU::SCC)); } + buildSpillLoadStore( *MBB, MI, DL, Opc, Index, VData->getReg(), VData->isKill(), FrameReg, TII->getNamedOperand(*MI, AMDGPU::OpName::offset)->getImm(), diff --git a/llvm/lib/Target/AMDGPU/SMInstructions.td b/llvm/lib/Target/AMDGPU/SMInstructions.td index fc29ce8d71f..9a27d22d585 100644 --- a/llvm/lib/Target/AMDGPU/SMInstructions.td +++ b/llvm/lib/Target/AMDGPU/SMInstructions.td @@ -810,7 +810,7 @@ def S_DCACHE_INV_VOL_ci : SMRD_Real_ci <0x1d, S_DCACHE_INV_VOL>; // Scalar Memory Patterns //===----------------------------------------------------------------------===// -def smrd_load : PatFrag <(ops node:$ptr), (load node:$ptr), [{ return isUniformLoad(N);}]> { +class SMRDLoadPat : PatFrag <(ops node:$ptr), (Op node:$ptr), [{ return isUniformLoad(N);}]> { let GISelPredicateCode = [{ if (!MI.hasOneMemOperand()) return false; @@ -827,6 +827,14 @@ def smrd_load : PatFrag <(ops node:$ptr), (load node:$ptr), [{ return isUniformL }]; } +def smrd_load : SMRDLoadPat; +def smrd_extloadi8 : SMRDLoadPat; +def smrd_zextloadi8 : SMRDLoadPat; +def smrd_sextloadi8 : SMRDLoadPat; +def smrd_extloadi16 : SMRDLoadPat; +def smrd_zextloadi16 : SMRDLoadPat; +def smrd_sextloadi16 : SMRDLoadPat; + def smrd_prefetch : PatFrag <(ops node:$ptr, node:$rw, node:$loc, node:$type), (prefetch node:$ptr, node:$rw, node:$loc, node:$type), [{ return !N->getOperand(1)->isDivergent();}]> { @@ -923,11 +931,78 @@ multiclass SMLoad_Pattern { } } +multiclass ScalarLoadWithExtensionPat { + // 1. IMM offset + def : GCNPat < + (node (SMRDImm i64:$sbase, i32:$offset)), + (vt (!cast(Instr#"_IMM") $sbase, $offset, 0))>{ + let OtherPredicates = [isGFX12Plus]; + } + + // 2. SGPR offset + def : GCNPat < + (node (SMRDSgpr i64:$sbase, i32:$soffset)), + (vt (!cast(Instr#"_SGPR_IMM") $sbase, $soffset, 0, 0))>{ + let OtherPredicates = [isGFX12Plus]; + } + + // 3. SGPR+IMM offset + def : GCNPat < + (node (SMRDSgprImm i64:$sbase, i32:$soffset, i32:$offset)), + (vt (!cast(Instr#"_SGPR_IMM") $sbase, $soffset, $offset, 0))>{ + let OtherPredicates = [isGFX12Plus]; + } + + // 4. No offset + def : GCNPat < + (vt (node (i64 SReg_64:$sbase))), + (vt (!cast(Instr#"_IMM") i64:$sbase, 0, 0))>{ + let OtherPredicates = [isGFX12Plus]; + } +} + +multiclass ScalarBufferLoadIntrinsicPat { + + // 1. Offset as an immediate + def : GCNPat < + (name v4i32:$sbase, (SMRDBufferImm i32:$offset), timm:$cachepolicy), + (i32 (!cast(Instr#"_IMM") SReg_128:$sbase, i32imm:$offset, (extract_cpol $cachepolicy)))> { + let OtherPredicates = [isGFX12Plus]; + } + + // 2. Offset as an 32-bit SGPR + def : GCNPat < + (name v4i32:$sbase, i32:$soffset, timm:$cachepolicy), + (i32 (!cast(Instr#"_SGPR_IMM") SReg_128:$sbase, SReg_32:$soffset, 0, (extract_cpol $cachepolicy)))> { + let OtherPredicates = [isGFX12Plus]; + } + + // 3. Offset as an 32-bit SGPR + immediate + def : GCNPat < + (name v4i32:$sbase, (SMRDBufferSgprImm i32:$soffset, i32:$offset), + timm:$cachepolicy), + (i32 (!cast(Instr#"_SGPR_IMM") SReg_128:$sbase, SReg_32:$soffset, i32imm:$offset, + (extract_cpol $cachepolicy)))> { + let OtherPredicates = [isGFX12Plus]; + } +} + // Global and constant loads can be selected to either MUBUF or SMRD // instructions, but SMRD instructions are faster so we want the instruction // selector to prefer those. let AddedComplexity = 100 in { +defm : ScalarLoadWithExtensionPat <"S_LOAD_U8", smrd_extloadi8, i32>; +defm : ScalarLoadWithExtensionPat <"S_LOAD_U8", smrd_zextloadi8, i32>; +defm : ScalarLoadWithExtensionPat <"S_LOAD_I8", smrd_sextloadi8, i32>; +defm : ScalarLoadWithExtensionPat <"S_LOAD_U16", smrd_extloadi16, i32>; +defm : ScalarLoadWithExtensionPat <"S_LOAD_U16", smrd_zextloadi16, i32>; +defm : ScalarLoadWithExtensionPat <"S_LOAD_I16", smrd_sextloadi16, i32>; +defm : ScalarBufferLoadIntrinsicPat ; +defm : ScalarBufferLoadIntrinsicPat ; +defm : ScalarBufferLoadIntrinsicPat ; +defm : ScalarBufferLoadIntrinsicPat ; + foreach vt = Reg32Types.types in { defm : SMRD_Pattern <"S_LOAD_DWORD", vt>; } diff --git a/llvm/lib/Target/AMDGPU/SOPInstructions.td b/llvm/lib/Target/AMDGPU/SOPInstructions.td index 46fa3d57a21..ae5ef054192 100644 --- a/llvm/lib/Target/AMDGPU/SOPInstructions.td +++ b/llvm/lib/Target/AMDGPU/SOPInstructions.td @@ -292,8 +292,11 @@ def S_BITSET0_B64 : SOP1_64_32 <"s_bitset0_b64", [], 1>; def S_BITSET1_B32 : SOP1_32 <"s_bitset1_b32", [], 1>; def S_BITSET1_B64 : SOP1_64_32 <"s_bitset1_b64", [], 1>; +def S_GETPC_B64 : SOP1_64_0 <"s_getpc_b64">; +// PSEUDO includes a workaround for a hardware anomaly where some ASICs +// zero-extend the result from 48 bits instead of sign-extending. let isReMaterializable = 1 in -def S_GETPC_B64 : SOP1_64_0 <"s_getpc_b64", +def S_GETPC_B64_pseudo : SOP1_64_0 <"s_getpc_b64", [(set i64:$sdst, (int_amdgcn_s_getpc))] >; @@ -502,8 +505,6 @@ def S_WAKEUP_BARRIER_IMM : SOP1_Pseudo <"s_wakeup_barrier", (outs), (ins SplitBarrier:$src0), "$src0", []>{ let SchedRW = [WriteBarrier]; let isConvergent = 1; - - } } // End has_sdst = 0 @@ -1124,7 +1125,7 @@ class S_SETREG_B32_Pseudo pattern=[]> : SOPK_Pseudo < pattern>; def S_SETREG_B32 : S_SETREG_B32_Pseudo < - [(int_amdgcn_s_setreg (i32 timm:$simm16), i32:$sdst)]> { + [(int_amdgcn_s_setreg (i32 SIMM16bit:$simm16), i32:$sdst)]> { // Use custom inserter to optimize some cases to // S_DENORM_MODE/S_ROUND_MODE/S_SETREG_B32_mode. let usesCustomInserter = 1; @@ -1597,6 +1598,13 @@ def S_WAITCNT : SOPP_Pseudo <"s_waitcnt" , (ins SWaitCnt:$simm16), "$simm16", // that doesn't access memory. def S_WAITCNT_soft : SOPP_Pseudo <"s_soft_waitcnt" , (ins SWaitCnt:$simm16), "$simm16">; def S_WAITCNT_VSCNT_soft : SOPK_WAITCNT<"s_soft_waitcnt_vscnt">; +let SubtargetPredicate = isGFX12Plus in { + def S_WAIT_LOADCNT_soft : SOPP_Pseudo <"s_soft_wait_loadcnt", (ins s16imm:$simm16), "$simm16">; + def S_WAIT_STORECNT_soft : SOPP_Pseudo <"s_soft_wait_storecnt", (ins s16imm:$simm16), "$simm16">; + def S_WAIT_SAMPLECNT_soft : SOPP_Pseudo <"s_soft_wait_samplecnt", (ins s16imm:$simm16), "$simm16">; + def S_WAIT_BVHCNT_soft : SOPP_Pseudo <"s_soft_wait_bvhcnt", (ins s16imm:$simm16), "$simm16">; + def S_WAIT_DSCNT_soft : SOPP_Pseudo <"s_soft_wait_dscnt", (ins s16imm:$simm16), "$simm16">; +} def S_SETHALT : SOPP_Pseudo <"s_sethalt" , (ins i32imm:$simm16), "$simm16", [(int_amdgcn_s_sethalt timm:$simm16)]>; @@ -1712,23 +1720,30 @@ let SubtargetPredicate = HasVGPRSingleUseHintInsts in { let SubtargetPredicate = isGFX12Plus, hasSideEffects = 1 in { def S_WAIT_LOADCNT : - SOPP_Pseudo<"s_wait_loadcnt", (ins s16imm:$simm16), "$simm16">; + SOPP_Pseudo<"s_wait_loadcnt", (ins s16imm:$simm16), "$simm16", + [(int_amdgcn_s_wait_loadcnt timm:$simm16)]>; def S_WAIT_LOADCNT_DSCNT : SOPP_Pseudo<"s_wait_loadcnt_dscnt", (ins s16imm:$simm16), "$simm16">; def S_WAIT_STORECNT : - SOPP_Pseudo<"s_wait_storecnt", (ins s16imm:$simm16), "$simm16">; + SOPP_Pseudo<"s_wait_storecnt", (ins s16imm:$simm16), "$simm16", + [(int_amdgcn_s_wait_storecnt timm:$simm16)]>; def S_WAIT_STORECNT_DSCNT : SOPP_Pseudo<"s_wait_storecnt_dscnt", (ins s16imm:$simm16), "$simm16">; def S_WAIT_SAMPLECNT : - SOPP_Pseudo<"s_wait_samplecnt", (ins s16imm:$simm16), "$simm16">; + SOPP_Pseudo<"s_wait_samplecnt", (ins s16imm:$simm16), "$simm16", + [(int_amdgcn_s_wait_samplecnt timm:$simm16)]>; def S_WAIT_BVHCNT : - SOPP_Pseudo<"s_wait_bvhcnt", (ins s16imm:$simm16), "$simm16">; + SOPP_Pseudo<"s_wait_bvhcnt", (ins s16imm:$simm16), "$simm16", + [(int_amdgcn_s_wait_bvhcnt timm:$simm16)]>; def S_WAIT_EXPCNT : - SOPP_Pseudo<"s_wait_expcnt", (ins s16imm:$simm16), "$simm16">; + SOPP_Pseudo<"s_wait_expcnt", (ins s16imm:$simm16), "$simm16", + [(int_amdgcn_s_wait_expcnt timm:$simm16)]>; def S_WAIT_DSCNT : - SOPP_Pseudo<"s_wait_dscnt", (ins s16imm:$simm16), "$simm16">; + SOPP_Pseudo<"s_wait_dscnt", (ins s16imm:$simm16), "$simm16", + [(int_amdgcn_s_wait_dscnt timm:$simm16)]>; def S_WAIT_KMCNT : - SOPP_Pseudo<"s_wait_kmcnt", (ins s16imm:$simm16), "$simm16">; + SOPP_Pseudo<"s_wait_kmcnt", (ins s16imm:$simm16), "$simm16", + [(int_amdgcn_s_wait_kmcnt timm:$simm16)]>; } // End SubtargetPredicate = isGFX12Plus, hasSideEffects = 1 //===----------------------------------------------------------------------===// @@ -1768,10 +1783,10 @@ def : GCNPat< (S_SEXT_I32_I16 $src) >; -def : GCNPat < - (int_amdgcn_s_wait_event_export_ready), - (S_WAIT_EVENT (i16 0)) ->; +let SubtargetPredicate = isNotGFX12Plus in + def : GCNPat <(int_amdgcn_s_wait_event_export_ready), (S_WAIT_EVENT (i16 0))>; +let SubtargetPredicate = isGFX12Plus in + def : GCNPat <(int_amdgcn_s_wait_event_export_ready), (S_WAIT_EVENT (i16 1))>; // The first 10 bits of the mode register are the core FP mode on all // subtargets. @@ -2610,7 +2625,7 @@ multiclass SOPP_Real_With_Relaxation_gfx11_gfx12op> : defm S_SETKILL : SOPP_Real_32_gfx11_gfx12<0x001>; defm S_SETHALT : SOPP_Real_32_gfx11_gfx12<0x002>; defm S_SLEEP : SOPP_Real_32_gfx11_gfx12<0x003>; -defm S_SET_INST_PREFETCH_DISTANCE : SOPP_Real_32_Renamed_gfx11_gfx12<0x004, S_INST_PREFETCH, "s_set_inst_prefetch_distance">; +defm S_SET_INST_PREFETCH_DISTANCE : SOPP_Real_32_Renamed_gfx11<0x004, S_INST_PREFETCH, "s_set_inst_prefetch_distance">; defm S_CLAUSE : SOPP_Real_32_gfx11_gfx12<0x005>; defm S_DELAY_ALU : SOPP_Real_32_gfx11_gfx12<0x007>; defm S_WAITCNT_DEPCTR : SOPP_Real_32_gfx11<0x008>; diff --git a/llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp b/llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp index 26ba2575ff3..0bf9452d822 100644 --- a/llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp +++ b/llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp @@ -31,10 +31,11 @@ #define GET_INSTRMAP_INFO #include "AMDGPUGenInstrInfo.inc" -static llvm::cl::opt - AmdhsaCodeObjectVersion("amdhsa-code-object-version", llvm::cl::Hidden, - llvm::cl::desc("AMDHSA Code Object Version"), - llvm::cl::init(4)); +static llvm::cl::opt DefaultAMDHSACodeObjectVersion( + "amdhsa-code-object-version", llvm::cl::Hidden, + llvm::cl::init(llvm::AMDGPU::AMDHSA_COV5), + llvm::cl::desc("Set default AMDHSA Code Object Version (module flag " + "or asm directive still take priority if present)")); namespace { @@ -94,6 +95,44 @@ unsigned getVmcntBitWidthHi(unsigned VersionMajor) { return (VersionMajor == 9 || VersionMajor == 10) ? 2 : 0; } +/// \returns Loadcnt bit width +unsigned getLoadcntBitWidth(unsigned VersionMajor) { + return VersionMajor >= 12 ? 6 : 0; +} + +/// \returns Samplecnt bit width. +unsigned getSamplecntBitWidth(unsigned VersionMajor) { + return VersionMajor >= 12 ? 6 : 0; +} + +/// \returns Bvhcnt bit width. +unsigned getBvhcntBitWidth(unsigned VersionMajor) { + return VersionMajor >= 12 ? 3 : 0; +} + +/// \returns Dscnt bit width. +unsigned getDscntBitWidth(unsigned VersionMajor) { + return VersionMajor >= 12 ? 6 : 0; +} + +/// \returns Dscnt bit shift in combined S_WAIT instructions. +unsigned getDscntBitShift(unsigned VersionMajor) { return 0; } + +/// \returns Storecnt or Vscnt bit width, depending on VersionMajor. +unsigned getStorecntBitWidth(unsigned VersionMajor) { + return VersionMajor >= 10 ? 6 : 0; +} + +/// \returns Kmcnt bit width. +unsigned getKmcntBitWidth(unsigned VersionMajor) { + return VersionMajor >= 12 ? 5 : 0; +} + +/// \returns shift for Loadcnt/Storecnt in combined S_WAIT instructions. +unsigned getLoadcntStorecntBitShift(unsigned VersionMajor) { + return VersionMajor >= 12 ? 8 : 0; +} + /// \returns VmVsrc bit width inline unsigned getVmVsrcBitWidth() { return 3; } @@ -123,47 +162,34 @@ bool isHsaAbi(const MCSubtargetInfo &STI) { return STI.getTargetTriple().getOS() == Triple::AMDHSA; } -std::optional getHsaAbiVersion(const MCSubtargetInfo *STI) { - if (STI && STI->getTargetTriple().getOS() != Triple::AMDHSA) - return std::nullopt; +unsigned getAMDHSACodeObjectVersion(const Module &M) { + if (auto Ver = mdconst::extract_or_null( + M.getModuleFlag("amdgpu_code_object_version"))) { + return (unsigned)Ver->getZExtValue() / 100; + } - switch (AmdhsaCodeObjectVersion) { + return getDefaultAMDHSACodeObjectVersion(); +} + +unsigned getDefaultAMDHSACodeObjectVersion() { + return DefaultAMDHSACodeObjectVersion; +} + +uint8_t getELFABIVersion(const Triple &T, unsigned CodeObjectVersion) { + if (T.getOS() != Triple::AMDHSA) + return 0; + + switch (CodeObjectVersion) { case 4: return ELF::ELFABIVERSION_AMDGPU_HSA_V4; case 5: return ELF::ELFABIVERSION_AMDGPU_HSA_V5; default: - report_fatal_error(Twine("Unsupported AMDHSA Code Object Version ") + - Twine(AmdhsaCodeObjectVersion)); + report_fatal_error("Unsupported AMDHSA Code Object Version " + + Twine(CodeObjectVersion)); } } -bool isHsaAbiVersion4(const MCSubtargetInfo *STI) { - if (std::optional HsaAbiVer = getHsaAbiVersion(STI)) - return *HsaAbiVer == ELF::ELFABIVERSION_AMDGPU_HSA_V4; - return false; -} - -bool isHsaAbiVersion5(const MCSubtargetInfo *STI) { - if (std::optional HsaAbiVer = getHsaAbiVersion(STI)) - return *HsaAbiVer == ELF::ELFABIVERSION_AMDGPU_HSA_V5; - return false; -} - -unsigned getAmdhsaCodeObjectVersion() { - return AmdhsaCodeObjectVersion; -} - -unsigned getCodeObjectVersion(const Module &M) { - if (auto Ver = mdconst::extract_or_null( - M.getModuleFlag("amdgpu_code_object_version"))) { - return (unsigned)Ver->getZExtValue() / 100; - } - - // Default code object version. - return AMDHSA_COV4; -} - unsigned getMultigridSyncArgImplicitArgPosition(unsigned CodeObjectVersion) { switch (CodeObjectVersion) { case AMDHSA_COV4: @@ -667,7 +693,7 @@ namespace IsaInfo { AMDGPUTargetID::AMDGPUTargetID(const MCSubtargetInfo &STI) : STI(STI), XnackSetting(TargetIDSetting::Any), - SramEccSetting(TargetIDSetting::Any), CodeObjectVersion(0) { + SramEccSetting(TargetIDSetting::Any) { if (!STI.getFeatureBits().test(FeatureSupportsXNACK)) XnackSetting = TargetIDSetting::Unsupported; if (!STI.getFeatureBits().test(FeatureSupportsSRAMECC)) @@ -779,23 +805,16 @@ std::string AMDGPUTargetID::toString() const { std::string Features; if (STI.getTargetTriple().getOS() == Triple::AMDHSA) { - switch (CodeObjectVersion) { - case AMDGPU::AMDHSA_COV4: - case AMDGPU::AMDHSA_COV5: - // sramecc. - if (getSramEccSetting() == TargetIDSetting::Off) - Features += ":sramecc-"; - else if (getSramEccSetting() == TargetIDSetting::On) - Features += ":sramecc+"; - // xnack. - if (getXnackSetting() == TargetIDSetting::Off) - Features += ":xnack-"; - else if (getXnackSetting() == TargetIDSetting::On) - Features += ":xnack+"; - break; - default: - break; - } + // sramecc. + if (getSramEccSetting() == TargetIDSetting::Off) + Features += ":sramecc-"; + else if (getSramEccSetting() == TargetIDSetting::On) + Features += ":sramecc+"; + // xnack. + if (getXnackSetting() == TargetIDSetting::Off) + Features += ":xnack-"; + else if (getXnackSetting() == TargetIDSetting::On) + Features += ":xnack+"; } StreamRep << Processor << Features; @@ -1229,6 +1248,18 @@ unsigned getVmcntBitMask(const IsaVersion &Version) { 1; } +unsigned getLoadcntBitMask(const IsaVersion &Version) { + return (1 << getLoadcntBitWidth(Version.Major)) - 1; +} + +unsigned getSamplecntBitMask(const IsaVersion &Version) { + return (1 << getSamplecntBitWidth(Version.Major)) - 1; +} + +unsigned getBvhcntBitMask(const IsaVersion &Version) { + return (1 << getBvhcntBitWidth(Version.Major)) - 1; +} + unsigned getExpcntBitMask(const IsaVersion &Version) { return (1 << getExpcntBitWidth(Version.Major)) - 1; } @@ -1237,6 +1268,18 @@ unsigned getLgkmcntBitMask(const IsaVersion &Version) { return (1 << getLgkmcntBitWidth(Version.Major)) - 1; } +unsigned getDscntBitMask(const IsaVersion &Version) { + return (1 << getDscntBitWidth(Version.Major)) - 1; +} + +unsigned getKmcntBitMask(const IsaVersion &Version) { + return (1 << getKmcntBitWidth(Version.Major)) - 1; +} + +unsigned getStorecntBitMask(const IsaVersion &Version) { + return (1 << getStorecntBitWidth(Version.Major)) - 1; +} + unsigned getWaitcntBitMask(const IsaVersion &Version) { unsigned VmcntLo = getBitMask(getVmcntBitShiftLo(Version.Major), getVmcntBitWidthLo(Version.Major)); @@ -1276,9 +1319,9 @@ void decodeWaitcnt(const IsaVersion &Version, unsigned Waitcnt, Waitcnt decodeWaitcnt(const IsaVersion &Version, unsigned Encoded) { Waitcnt Decoded; - Decoded.VmCnt = decodeVmcnt(Version, Encoded); + Decoded.LoadCnt = decodeVmcnt(Version, Encoded); Decoded.ExpCnt = decodeExpcnt(Version, Encoded); - Decoded.LgkmCnt = decodeLgkmcnt(Version, Encoded); + Decoded.DsCnt = decodeLgkmcnt(Version, Encoded); return Decoded; } @@ -1313,7 +1356,85 @@ unsigned encodeWaitcnt(const IsaVersion &Version, } unsigned encodeWaitcnt(const IsaVersion &Version, const Waitcnt &Decoded) { - return encodeWaitcnt(Version, Decoded.VmCnt, Decoded.ExpCnt, Decoded.LgkmCnt); + return encodeWaitcnt(Version, Decoded.LoadCnt, Decoded.ExpCnt, Decoded.DsCnt); +} + +static unsigned getCombinedCountBitMask(const IsaVersion &Version, + bool IsStore) { + unsigned Dscnt = getBitMask(getDscntBitShift(Version.Major), + getDscntBitWidth(Version.Major)); + if (IsStore) { + unsigned Storecnt = getBitMask(getLoadcntStorecntBitShift(Version.Major), + getStorecntBitWidth(Version.Major)); + return Dscnt | Storecnt; + } else { + unsigned Loadcnt = getBitMask(getLoadcntStorecntBitShift(Version.Major), + getLoadcntBitWidth(Version.Major)); + return Dscnt | Loadcnt; + } +} + +Waitcnt decodeLoadcntDscnt(const IsaVersion &Version, unsigned LoadcntDscnt) { + Waitcnt Decoded; + Decoded.LoadCnt = + unpackBits(LoadcntDscnt, getLoadcntStorecntBitShift(Version.Major), + getLoadcntBitWidth(Version.Major)); + Decoded.DsCnt = unpackBits(LoadcntDscnt, getDscntBitShift(Version.Major), + getDscntBitWidth(Version.Major)); + return Decoded; +} + +Waitcnt decodeStorecntDscnt(const IsaVersion &Version, unsigned StorecntDscnt) { + Waitcnt Decoded; + Decoded.StoreCnt = + unpackBits(StorecntDscnt, getLoadcntStorecntBitShift(Version.Major), + getStorecntBitWidth(Version.Major)); + Decoded.DsCnt = unpackBits(StorecntDscnt, getDscntBitShift(Version.Major), + getDscntBitWidth(Version.Major)); + return Decoded; +} + +static unsigned encodeLoadcnt(const IsaVersion &Version, unsigned Waitcnt, + unsigned Loadcnt) { + return packBits(Loadcnt, Waitcnt, getLoadcntStorecntBitShift(Version.Major), + getLoadcntBitWidth(Version.Major)); +} + +static unsigned encodeStorecnt(const IsaVersion &Version, unsigned Waitcnt, + unsigned Storecnt) { + return packBits(Storecnt, Waitcnt, getLoadcntStorecntBitShift(Version.Major), + getStorecntBitWidth(Version.Major)); +} + +static unsigned encodeDscnt(const IsaVersion &Version, unsigned Waitcnt, + unsigned Dscnt) { + return packBits(Dscnt, Waitcnt, getDscntBitShift(Version.Major), + getDscntBitWidth(Version.Major)); +} + +static unsigned encodeLoadcntDscnt(const IsaVersion &Version, unsigned Loadcnt, + unsigned Dscnt) { + unsigned Waitcnt = getCombinedCountBitMask(Version, false); + Waitcnt = encodeLoadcnt(Version, Waitcnt, Loadcnt); + Waitcnt = encodeDscnt(Version, Waitcnt, Dscnt); + return Waitcnt; +} + +unsigned encodeLoadcntDscnt(const IsaVersion &Version, const Waitcnt &Decoded) { + return encodeLoadcntDscnt(Version, Decoded.LoadCnt, Decoded.DsCnt); +} + +static unsigned encodeStorecntDscnt(const IsaVersion &Version, + unsigned Storecnt, unsigned Dscnt) { + unsigned Waitcnt = getCombinedCountBitMask(Version, true); + Waitcnt = encodeStorecnt(Version, Waitcnt, Storecnt); + Waitcnt = encodeDscnt(Version, Waitcnt, Dscnt); + return Waitcnt; +} + +unsigned encodeStorecntDscnt(const IsaVersion &Version, + const Waitcnt &Decoded) { + return encodeStorecntDscnt(Version, Decoded.StoreCnt, Decoded.DsCnt); } //===----------------------------------------------------------------------===// diff --git a/llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h b/llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h index 50c741760d7..d3f55c79201 100644 --- a/llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h +++ b/llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h @@ -46,14 +46,18 @@ enum { AMDHSA_COV4 = 4, AMDHSA_COV5 = 5 }; /// \returns True if \p STI is AMDHSA. bool isHsaAbi(const MCSubtargetInfo &STI); -/// \returns HSA OS ABI Version identification. -std::optional getHsaAbiVersion(const MCSubtargetInfo *STI); -/// \returns True if HSA OS ABI Version identification is 4, -/// false otherwise. -bool isHsaAbiVersion4(const MCSubtargetInfo *STI); -/// \returns True if HSA OS ABI Version identification is 5, -/// false otherwise. -bool isHsaAbiVersion5(const MCSubtargetInfo *STI); + +/// \returns Code object version from the IR module flag. +unsigned getAMDHSACodeObjectVersion(const Module &M); + +/// \returns The default HSA code object version. This should only be used when +/// we lack a more accurate CodeObjectVersion value (e.g. from the IR module +/// flag or a .amdhsa_code_object_version directive) +unsigned getDefaultAMDHSACodeObjectVersion(); + +/// \returns ABIVersion suitable for use in ELF's e_ident[ABIVERSION]. \param +/// CodeObjectVersion is a value returned by getAMDHSACodeObjectVersion(). +uint8_t getELFABIVersion(const Triple &OS, unsigned CodeObjectVersion); /// \returns The offset of the multigrid_sync_arg argument from implicitarg_ptr unsigned getMultigridSyncArgImplicitArgPosition(unsigned COV); @@ -64,12 +68,6 @@ unsigned getHostcallImplicitArgPosition(unsigned COV); unsigned getDefaultQueueImplicitArgPosition(unsigned COV); unsigned getCompletionActionImplicitArgPosition(unsigned COV); -/// \returns Code object version. -unsigned getAmdhsaCodeObjectVersion(); - -/// \returns Code object version. -unsigned getCodeObjectVersion(const Module &M); - struct GcnBufferFormatInfo { unsigned Format; unsigned BitsPerComp; @@ -114,7 +112,6 @@ private: const MCSubtargetInfo &STI; TargetIDSetting XnackSetting; TargetIDSetting SramEccSetting; - unsigned CodeObjectVersion; public: explicit AMDGPUTargetID(const MCSubtargetInfo &STI); @@ -144,10 +141,6 @@ public: return XnackSetting; } - void setCodeObjectVersion(unsigned COV) { - CodeObjectVersion = COV; - } - /// Sets xnack setting to \p NewXnackSetting. void setXnackSetting(TargetIDSetting NewXnackSetting) { XnackSetting = NewXnackSetting; @@ -837,39 +830,58 @@ getIntegerPairAttribute(const Function &F, StringRef Name, /// Large values (including the maximum possible integer) can be used to /// represent "don't care" waits. struct Waitcnt { - unsigned VmCnt = ~0u; + unsigned LoadCnt = ~0u; // Corresponds to Vmcnt prior to gfx12. unsigned ExpCnt = ~0u; - unsigned LgkmCnt = ~0u; - unsigned VsCnt = ~0u; + unsigned DsCnt = ~0u; // Corresponds to LGKMcnt prior to gfx12. + unsigned StoreCnt = ~0u; // Corresponds to VScnt on gfx10/gfx11. + unsigned SampleCnt = ~0u; // gfx12+ only. + unsigned BvhCnt = ~0u; // gfx12+ only. + unsigned KmCnt = ~0u; // gfx12+ only. Waitcnt() = default; + // Pre-gfx12 constructor. Waitcnt(unsigned VmCnt, unsigned ExpCnt, unsigned LgkmCnt, unsigned VsCnt) - : VmCnt(VmCnt), ExpCnt(ExpCnt), LgkmCnt(LgkmCnt), VsCnt(VsCnt) {} + : LoadCnt(VmCnt), ExpCnt(ExpCnt), DsCnt(LgkmCnt), StoreCnt(VsCnt), + SampleCnt(~0u), BvhCnt(~0u), KmCnt(~0u) {} - static Waitcnt allZero(bool HasVscnt) { - return Waitcnt(0, 0, 0, HasVscnt ? 0 : ~0u); - } - static Waitcnt allZeroExceptVsCnt() { return Waitcnt(0, 0, 0, ~0u); } + // gfx12+ constructor. + Waitcnt(unsigned LoadCnt, unsigned ExpCnt, unsigned DsCnt, unsigned StoreCnt, + unsigned SampleCnt, unsigned BvhCnt, unsigned KmCnt) + : LoadCnt(LoadCnt), ExpCnt(ExpCnt), DsCnt(DsCnt), StoreCnt(StoreCnt), + SampleCnt(SampleCnt), BvhCnt(BvhCnt), KmCnt(KmCnt) {} - bool hasWait() const { - return VmCnt != ~0u || ExpCnt != ~0u || LgkmCnt != ~0u || VsCnt != ~0u; + static Waitcnt allZero(bool Extended, bool HasStorecnt) { + return Extended ? Waitcnt(0, 0, 0, 0, 0, 0, 0) + : Waitcnt(0, 0, 0, HasStorecnt ? 0 : ~0u); } - bool hasWaitExceptVsCnt() const { - return VmCnt != ~0u || ExpCnt != ~0u || LgkmCnt != ~0u; + static Waitcnt allZeroExceptVsCnt(bool Extended) { + return Extended ? Waitcnt(0, 0, 0, ~0u, 0, 0, 0) : Waitcnt(0, 0, 0, ~0u); } - bool hasWaitVsCnt() const { - return VsCnt != ~0u; + bool hasWait() const { return StoreCnt != ~0u || hasWaitExceptStoreCnt(); } + + bool hasWaitExceptStoreCnt() const { + return LoadCnt != ~0u || ExpCnt != ~0u || DsCnt != ~0u || + SampleCnt != ~0u || BvhCnt != ~0u || KmCnt != ~0u; } + bool hasWaitStoreCnt() const { return StoreCnt != ~0u; } + Waitcnt combined(const Waitcnt &Other) const { - return Waitcnt(std::min(VmCnt, Other.VmCnt), std::min(ExpCnt, Other.ExpCnt), - std::min(LgkmCnt, Other.LgkmCnt), - std::min(VsCnt, Other.VsCnt)); + // Does the right thing provided self and Other are either both pre-gfx12 + // or both gfx12+. + return Waitcnt( + std::min(LoadCnt, Other.LoadCnt), std::min(ExpCnt, Other.ExpCnt), + std::min(DsCnt, Other.DsCnt), std::min(StoreCnt, Other.StoreCnt), + std::min(SampleCnt, Other.SampleCnt), std::min(BvhCnt, Other.BvhCnt), + std::min(KmCnt, Other.KmCnt)); } }; +// The following methods are only meaningful on targets that support +// S_WAITCNT. + /// \returns Vmcnt bit mask for given isa \p Version. unsigned getVmcntBitMask(const IsaVersion &Version); @@ -893,17 +905,19 @@ unsigned decodeLgkmcnt(const IsaVersion &Version, unsigned Waitcnt); /// Decodes Vmcnt, Expcnt and Lgkmcnt from given \p Waitcnt for given isa /// \p Version, and writes decoded values into \p Vmcnt, \p Expcnt and -/// \p Lgkmcnt respectively. +/// \p Lgkmcnt respectively. Should not be used on gfx12+, the instruction +/// which needs it is deprecated /// /// \details \p Vmcnt, \p Expcnt and \p Lgkmcnt are decoded as follows: /// \p Vmcnt = \p Waitcnt[3:0] (pre-gfx9) /// \p Vmcnt = \p Waitcnt[15:14,3:0] (gfx9,10) -/// \p Vmcnt = \p Waitcnt[15:10] (gfx11+) +/// \p Vmcnt = \p Waitcnt[15:10] (gfx11) /// \p Expcnt = \p Waitcnt[6:4] (pre-gfx11) -/// \p Expcnt = \p Waitcnt[2:0] (gfx11+) +/// \p Expcnt = \p Waitcnt[2:0] (gfx11) /// \p Lgkmcnt = \p Waitcnt[11:8] (pre-gfx10) /// \p Lgkmcnt = \p Waitcnt[13:8] (gfx10) -/// \p Lgkmcnt = \p Waitcnt[9:4] (gfx11+) +/// \p Lgkmcnt = \p Waitcnt[9:4] (gfx11) +/// void decodeWaitcnt(const IsaVersion &Version, unsigned Waitcnt, unsigned &Vmcnt, unsigned &Expcnt, unsigned &Lgkmcnt); @@ -922,26 +936,78 @@ unsigned encodeLgkmcnt(const IsaVersion &Version, unsigned Waitcnt, unsigned Lgkmcnt); /// Encodes \p Vmcnt, \p Expcnt and \p Lgkmcnt into Waitcnt for given isa -/// \p Version. +/// \p Version. Should not be used on gfx12+, the instruction which needs +/// it is deprecated /// /// \details \p Vmcnt, \p Expcnt and \p Lgkmcnt are encoded as follows: /// Waitcnt[2:0] = \p Expcnt (gfx11+) /// Waitcnt[3:0] = \p Vmcnt (pre-gfx9) /// Waitcnt[3:0] = \p Vmcnt[3:0] (gfx9,10) /// Waitcnt[6:4] = \p Expcnt (pre-gfx11) -/// Waitcnt[9:4] = \p Lgkmcnt (gfx11+) +/// Waitcnt[9:4] = \p Lgkmcnt (gfx11) /// Waitcnt[11:8] = \p Lgkmcnt (pre-gfx10) /// Waitcnt[13:8] = \p Lgkmcnt (gfx10) -/// Waitcnt[15:10] = \p Vmcnt (gfx11+) +/// Waitcnt[15:10] = \p Vmcnt (gfx11) /// Waitcnt[15:14] = \p Vmcnt[5:4] (gfx9,10) /// /// \returns Waitcnt with encoded \p Vmcnt, \p Expcnt and \p Lgkmcnt for given /// isa \p Version. +/// unsigned encodeWaitcnt(const IsaVersion &Version, unsigned Vmcnt, unsigned Expcnt, unsigned Lgkmcnt); unsigned encodeWaitcnt(const IsaVersion &Version, const Waitcnt &Decoded); +// The following methods are only meaningful on targets that support +// S_WAIT_*CNT, introduced with gfx12. + +/// \returns Loadcnt bit mask for given isa \p Version. +/// Returns 0 for versions that do not support LOADcnt +unsigned getLoadcntBitMask(const IsaVersion &Version); + +/// \returns Samplecnt bit mask for given isa \p Version. +/// Returns 0 for versions that do not support SAMPLEcnt +unsigned getSamplecntBitMask(const IsaVersion &Version); + +/// \returns Bvhcnt bit mask for given isa \p Version. +/// Returns 0 for versions that do not support BVHcnt +unsigned getBvhcntBitMask(const IsaVersion &Version); + +/// \returns Dscnt bit mask for given isa \p Version. +/// Returns 0 for versions that do not support DScnt +unsigned getDscntBitMask(const IsaVersion &Version); + +/// \returns Dscnt bit mask for given isa \p Version. +/// Returns 0 for versions that do not support KMcnt +unsigned getKmcntBitMask(const IsaVersion &Version); + +/// \return STOREcnt or VScnt bit mask for given isa \p Version. +/// returns 0 for versions that do not support STOREcnt or VScnt. +/// STOREcnt and VScnt are the same counter, the name used +/// depends on the ISA version. +unsigned getStorecntBitMask(const IsaVersion &Version); + +// The following are only meaningful on targets that support +// S_WAIT_LOADCNT_DSCNT and S_WAIT_STORECNT_DSCNT. + +/// \returns Decoded Waitcnt structure from given \p LoadcntDscnt for given +/// isa \p Version. +Waitcnt decodeLoadcntDscnt(const IsaVersion &Version, unsigned LoadcntDscnt); + +/// \returns Decoded Waitcnt structure from given \p StorecntDscnt for given +/// isa \p Version. +Waitcnt decodeStorecntDscnt(const IsaVersion &Version, unsigned StorecntDscnt); + +/// \returns \p Loadcnt and \p Dscnt components of \p Decoded encoded as an +/// immediate that can be used with S_WAIT_LOADCNT_DSCNT for given isa +/// \p Version. +unsigned encodeLoadcntDscnt(const IsaVersion &Version, const Waitcnt &Decoded); + +/// \returns \p Storecnt and \p Dscnt components of \p Decoded encoded as an +/// immediate that can be used with S_WAIT_STORECNT_DSCNT for given isa +/// \p Version. +unsigned encodeStorecntDscnt(const IsaVersion &Version, const Waitcnt &Decoded); + namespace Hwreg { LLVM_READONLY diff --git a/llvm/lib/Target/AMDGPU/VOP1Instructions.td b/llvm/lib/Target/AMDGPU/VOP1Instructions.td index 99960c94e59..95a1d869634 100644 --- a/llvm/lib/Target/AMDGPU/VOP1Instructions.td +++ b/llvm/lib/Target/AMDGPU/VOP1Instructions.td @@ -48,7 +48,7 @@ class VOP1_Pseudo pattern=[], bit VOP1On let mayStore = 0; let hasSideEffects = 0; - let ReadsModeReg = !or(isFloatType.ret, isFloatType.ret); + let ReadsModeReg = !or(P.DstVT.isFP, P.Src0VT.isFP); let mayRaiseFPException = ReadsModeReg; @@ -585,7 +585,7 @@ class VOPProfile_Base_CVT_F32_F8 : VOPProfileI2F { def VOPProfileCVT_F32_F8 : VOPProfile_Base_CVT_F32_F8 ; def VOPProfileCVT_PK_F32_F8 : VOPProfile_Base_CVT_F32_F8 ; -let SubtargetPredicate = HasFP8Insts, mayRaiseFPException = 0, +let SubtargetPredicate = HasFP8ConversionInsts, mayRaiseFPException = 0, SchedRW = [WriteFloatCvt] in { defm V_CVT_F32_FP8 : VOP1Inst<"v_cvt_f32_fp8", VOPProfileCVT_F32_F8>; defm V_CVT_F32_BF8 : VOP1Inst<"v_cvt_f32_bf8", VOPProfileCVT_F32_F8>; @@ -705,7 +705,6 @@ class VOP1_DPP16_Gen op, VOP1_DPP_Pseudo ps, GFXGen Gen, VOPProfile p = let DecoderNamespace = "DPP"#Gen.DecoderNamespace; } - class VOP1_DPP8 op, VOP1_Pseudo ps, VOPProfile p = ps.Pfl> : VOP_DPP8 { let hasSideEffects = ps.hasSideEffects; @@ -881,6 +880,7 @@ defm V_LOG_F16_fake16 : VOP1_Real_FULL_t16_gfx11_gfx12<0x057, "v_log_f16" defm V_EXP_F16_fake16 : VOP1_Real_FULL_t16_gfx11_gfx12<0x058, "v_exp_f16">; defm V_FREXP_MANT_F16_fake16 : VOP1_Real_FULL_t16_gfx11_gfx12<0x059, "v_frexp_mant_f16">; defm V_FREXP_EXP_I16_F16_t16 : VOP1_Real_FULL_t16_gfx11_gfx12<0x05a, "v_frexp_exp_i16_f16">; +defm V_FLOOR_F16_t16 : VOP1_Real_FULL_t16_gfx11_gfx12<0x05b, "v_floor_f16">; defm V_FLOOR_F16_fake16 : VOP1_Real_FULL_t16_gfx11_gfx12<0x05b, "v_floor_f16">; defm V_CEIL_F16_t16 : VOP1_Real_FULL_t16_gfx11_gfx12<0x05c, "v_ceil_f16">; defm V_CEIL_F16_fake16 : VOP1_Real_FULL_t16_gfx11_gfx12<0x05c, "v_ceil_f16">; @@ -1357,7 +1357,7 @@ defm V_SCREEN_PARTITION_4SE_B32 : VOP1_Real_gfx9 <0x37>; let AssemblerPredicate = isGFX940Plus, DecoderNamespace = "GFX9" in defm V_MOV_B64 : VOP1_Real_gfx9 <0x38>; -let OtherPredicates = [HasFP8Insts] in { +let OtherPredicates = [HasFP8ConversionInsts] in { defm V_CVT_F32_FP8 : VOP1_Real_NoDstSel_SDWA_gfx9<0x54>; defm V_CVT_F32_BF8 : VOP1_Real_NoDstSel_SDWA_gfx9<0x55>; defm V_CVT_PK_F32_FP8 : VOP1_Real_NoDstSel_SDWA_gfx9<0x56>; diff --git a/llvm/lib/Target/AMDGPU/VOP2Instructions.td b/llvm/lib/Target/AMDGPU/VOP2Instructions.td index 48d4e259bc1..27eec64f59a 100644 --- a/llvm/lib/Target/AMDGPU/VOP2Instructions.td +++ b/llvm/lib/Target/AMDGPU/VOP2Instructions.td @@ -69,7 +69,7 @@ class VOP2_Pseudo pattern=[], string suf let mayStore = 0; let hasSideEffects = 0; - let ReadsModeReg = !or(isFloatType.ret, isFloatType.ret); + let ReadsModeReg = !or(P.DstVT.isFP, P.Src0VT.isFP); let mayRaiseFPException = ReadsModeReg; @@ -418,15 +418,11 @@ def VOP_MADMK_F16_t16 : VOP_MADMK { } def VOP_MADMK_F32 : VOP_MADMK ; -class getRegisterOperandForVT { - RegisterOperand ret = RegisterOperand.ret>; -} - // FIXME: Remove src2_modifiers. It isn't used, so is wasting memory // and processing time but it makes it easier to convert to mad. class VOP_MAC : VOPProfile <[vt0, vt1, vt1, vt0]> { let Ins32 = (ins Src0RC32:$src0, Src1RC32:$src1, getVregSrcForVT.ret:$src2); - let Ins64 = getIns64.ret, 3, + let Ins64 = getIns64.ret, 3, 0, HasModifiers, HasModifiers, HasOMod, Src0Mod, Src1Mod, Src2Mod>.ret; let InsDPP = (ins Src0ModDPP:$src0_modifiers, Src0DPP:$src0, @@ -489,21 +485,21 @@ def VOP_MAC_F16_t16 : VOP_MAC { let DstRC = VOPDstOperand; let DstRC64 = VOPDstOperand; let Src1RC32 = VGPRSrc_32_Lo128; - let Ins32 = (ins Src0RC32:$src0, Src1RC32:$src1, getVregSrcForVT_t16.ret:$src2); - let Src0DPP = getVregSrcForVT_t16.ret; - let Src1DPP = getVregSrcForVT_t16.ret; - let Src2DPP = getVregSrcForVT_t16.ret; + let Ins32 = (ins Src0RC32:$src0, Src1RC32:$src1, getVregSrcForVT.ret:$src2); + let Src0DPP = getVregSrcForVT.ret; + let Src1DPP = getVregSrcForVT.ret; + let Src2DPP = getVregSrcForVT.ret; let Src0ModDPP = getSrcModDPP_t16.ret; let Src1ModDPP = getSrcModDPP_t16.ret; let Src2ModDPP = getSrcModDPP_t16.ret; let InsDPP = (ins Src0ModDPP:$src0_modifiers, Src0DPP:$src0, Src1ModDPP:$src1_modifiers, Src1DPP:$src1, - getVregSrcForVT_t16.ret:$src2, // stub argument + getVregSrcForVT.ret:$src2, // stub argument dpp_ctrl:$dpp_ctrl, row_mask:$row_mask, bank_mask:$bank_mask, bound_ctrl:$bound_ctrl); let InsDPP8 = (ins Src0ModDPP:$src0_modifiers, Src0DPP:$src0, Src1ModDPP:$src1_modifiers, Src1DPP:$src1, - getVregSrcForVT_t16.ret:$src2, // stub argument + getVregSrcForVT.ret:$src2, // stub argument dpp8:$dpp8, FI:$fi); let Src2Mod = FP32InputMods; // dummy unused modifiers let Src2RC64 = VGPRSrc_32; // stub argument @@ -535,7 +531,7 @@ def VOP_DOT_ACC_I32_I32 : VOP_DOT_ACC { let Src0Mod = Int32InputMods; let Src1Mod = Int32InputMods; - let Ins64 = getIns64.ret, + let Ins64 = getIns64.ret, 3 /*NumSrcArgs*/, HasClamp, 1 /*HasModifiers*/, 1 /*HasSrc2Mods*/, HasOMod, Src0Mod, Src1Mod, Src2Mod>.ret; @@ -898,8 +894,8 @@ def LDEXP_F16_VOPProfile : VOPProfile <[f16, f16, f16, untyped]> { } def LDEXP_F16_VOPProfile_True16 : VOPProfile_Fake16 { let Src1RC32 = RegisterOperand; - let Src1DPP = VGPR_32_Lo128; - let Src1ModDPP = IntT16VRegInputMods; + let Src1DPP = RegisterOperand; + let Src1ModDPP = IntT16VRegInputMods; } let isReMaterializable = 1 in { @@ -2512,6 +2508,7 @@ defm V_FMAAK_F32 : VOP2_Real_MADK_gfx940 <0x18>; } multiclass VOP2_Real_DOT_ACC_gfx9 op> : Base_VOP2_Real_e32e64_vi { + let SubtargetPredicate = isGFX9Only in def _dpp_vi : VOP2_DPP(NAME#"_dpp")>; } @@ -2520,22 +2517,28 @@ multiclass VOP2_Real_DOT_ACC_gfx10 op> : VOP2_Real_dpp_gfx10, VOP2_Real_dpp8_gfx10; -let SubtargetPredicate = HasDot5Insts in { +multiclass VOP2Only_Real_DOT_ACC_gfx10 op> : VOP2_Real_dpp_gfx10, + VOP2_Real_dpp8_gfx10 { + let IsSingle = 1 in + defm NAME : VOP2_Real_e32_gfx10; +} + +let OtherPredicates = [HasDot5Insts] in { defm V_DOT2C_F32_F16 : VOP2_Real_DOT_ACC_gfx9<0x37>; // NB: Opcode conflicts with V_DOT8C_I32_I4 // This opcode exists in gfx 10.1* only - defm V_DOT2C_F32_F16 : VOP2_Real_DOT_ACC_gfx10<0x02>; + defm V_DOT2C_F32_F16 : VOP2Only_Real_DOT_ACC_gfx10<0x02>; } -let SubtargetPredicate = HasDot6Insts in { +let OtherPredicates = [HasDot6Insts] in { defm V_DOT4C_I32_I8 : VOP2_Real_DOT_ACC_gfx9<0x39>; - defm V_DOT4C_I32_I8 : VOP2_Real_DOT_ACC_gfx10<0x0d>; + defm V_DOT4C_I32_I8 : VOP2Only_Real_DOT_ACC_gfx10<0x0d>; } -let SubtargetPredicate = HasDot4Insts in { +let OtherPredicates = [HasDot4Insts] in { defm V_DOT2C_I32_I16 : VOP2_Real_DOT_ACC_gfx9<0x38>; } -let SubtargetPredicate = HasDot3Insts in { +let OtherPredicates = [HasDot3Insts] in { defm V_DOT8C_I32_I4 : VOP2_Real_DOT_ACC_gfx9<0x3a>; } diff --git a/llvm/lib/Target/AMDGPU/VOP3Instructions.td b/llvm/lib/Target/AMDGPU/VOP3Instructions.td index eebd323210f..713b4712d56 100644 --- a/llvm/lib/Target/AMDGPU/VOP3Instructions.td +++ b/llvm/lib/Target/AMDGPU/VOP3Instructions.td @@ -600,7 +600,7 @@ defm V_LSHL_OR_B32 : VOP3Inst <"v_lshl_or_b32", VOP3_Profile>; -let SubtargetPredicate = HasFP8Insts, mayRaiseFPException = 0, +let SubtargetPredicate = HasFP8ConversionInsts, mayRaiseFPException = 0, SchedRW = [WriteFloatCvt] in { let Constraints = "$vdst = $vdst_in", DisableEncoding = "$vdst_in" in { defm V_CVT_PK_FP8_F32 : VOP3Inst<"v_cvt_pk_fp8_f32", VOP3_CVT_PK_F8_F32_Profile>; @@ -1611,7 +1611,7 @@ defm V_CVT_PKNORM_U16_F16 : VOP3OpSel_Real_gfx9 <0x29a>; defm V_LSHL_ADD_U64 : VOP3_Real_vi <0x208>; -let OtherPredicates = [HasFP8Insts] in { +let OtherPredicates = [HasFP8ConversionInsts] in { defm V_CVT_PK_FP8_F32 : VOP3OpSel_Real_gfx9 <0x2a2>; defm V_CVT_PK_BF8_F32 : VOP3OpSel_Real_gfx9 <0x2a3>; defm V_CVT_SR_FP8_F32 : VOP3OpSel_Real_gfx9_forced_opsel2 <0x2a4>; diff --git a/llvm/lib/Target/AMDGPU/VOP3PInstructions.td b/llvm/lib/Target/AMDGPU/VOP3PInstructions.td index e9d6f67aee1..0c7a08cd4bc 100644 --- a/llvm/lib/Target/AMDGPU/VOP3PInstructions.td +++ b/llvm/lib/Target/AMDGPU/VOP3PInstructions.td @@ -415,8 +415,8 @@ multiclass VOP3PDOTIUInst { null_frag, 1>; // Dot-iu instructions consider input as signed if imod neg bits are set. Thus // Dot-iu Intrinsics have extra operands and require separate codegen pattern. - def : GCNPat < (intrinsic_node (DotIUVOP3PMods i32:$src0_mods), i32:$src0, - (DotIUVOP3PMods i32:$src1_mods), i32:$src1, + def : GCNPat < (intrinsic_node (VOP3PModsNeg i32:$src0_mods), i32:$src0, + (VOP3PModsNeg i32:$src1_mods), i32:$src1, i32:$src2, (i1 timm:$clamp)), (!cast(NAME) $src0_mods, i32:$src0, $src1_mods, i32:$src1, @@ -443,6 +443,48 @@ def : GCNPat < (int_amdgcn_sdot4 i32:$src0, >; } // End SubtargetPredicate = HasDot8Insts +// Does not use opsel, no src_modifiers on src0 and src1. +// src_modifiers on src2(f32) are f32 fneg(neg_lo[2]) and f32 fabs(neg_hi[2]). +def VOP3P_DOTF8_Profile : VOP3P_Profile, + VOP3_PACKED, 1> { + let HasClamp = 0; + let HasOpSel = 0; + let HasOMod = 0; + let IsDOT = 1; + let HasSrc0Mods = 0; + let HasSrc1Mods = 0; + let HasSrc2Mods = 1; + + let InsVOP3P = (ins VSrc_b32:$src0, VSrc_b32:$src1, + PackedF16InputMods:$src2_modifiers, VSrc_f32:$src2, + neg_lo0:$neg_lo, neg_hi0:$neg_hi); + + let InsVOP3DPP8 = (ins DstRC:$old, VGPR_32:$src0, VRegSrc_32:$src1, + PackedF16InputMods:$src2_modifiers, VRegSrc_32:$src2, + neg_lo0:$neg_lo, neg_hi0:$neg_hi, dpp8:$dpp8, FI:$fi); + + let InsVOP3DPP16 = (ins DstRC:$old, VGPR_32:$src0, VRegSrc_32:$src1, + PackedF16InputMods:$src2_modifiers, VRegSrc_32:$src2, + neg_lo0:$neg_lo, neg_hi0:$neg_hi, dpp_ctrl:$dpp_ctrl, + row_mask:$row_mask, bank_mask:$bank_mask, + bound_ctrl:$bound_ctrl, FI:$fi); +} + +multiclass VOP3PDOTF8Inst { + defm NAME : VOP3PInst; + + let SubtargetPredicate = isGFX12Plus in + def : GCNPat <(intrinsic_node i32:$src0, i32:$src1, + (VOP3Mods f32:$src2, i32:$src2_modifiers)), + (!cast(NAME) i32:$src0, i32:$src1, + i32:$src2_modifiers, f32:$src2)>; +} + +defm V_DOT4_F32_FP8_BF8 : VOP3PDOTF8Inst<"v_dot4_f32_fp8_bf8", int_amdgcn_dot4_f32_fp8_bf8>; +defm V_DOT4_F32_BF8_FP8 : VOP3PDOTF8Inst<"v_dot4_f32_bf8_fp8", int_amdgcn_dot4_f32_bf8_fp8>; +defm V_DOT4_F32_FP8_FP8 : VOP3PDOTF8Inst<"v_dot4_f32_fp8_fp8", int_amdgcn_dot4_f32_fp8_fp8>; +defm V_DOT4_F32_BF8_BF8 : VOP3PDOTF8Inst<"v_dot4_f32_bf8_bf8", int_amdgcn_dot4_f32_bf8_bf8>; + def : UDot2Pat; def : SDot2Pat; @@ -593,13 +635,29 @@ class MAIFrag : PatFrag < pred >; -let GISelPredicateCode = [{ return MF.getInfo()->mayNeedAGPRs(); }] in -class AgprMAIFrag : - MAIFraggetInfo()->mayNeedAGPRs(); }]>; +defvar MayNeedAGPRs = [{ + return MF->getInfo()->mayNeedAGPRs(); +}]; -let GISelPredicateCode = [{ return !MF.getInfo()->mayNeedAGPRs(); }] in -class VgprMAIFrag : - MAIFraggetInfo()->mayNeedAGPRs(); }]>; +defvar MayNeedAGPRs_gisel = [{ + return MF.getInfo()->mayNeedAGPRs(); +}]; + +defvar MayNotNeedAGPRs = [{ + return !MF->getInfo()->mayNeedAGPRs(); +}]; + +defvar MayNotNeedAGPRs_gisel = [{ + return !MF.getInfo()->mayNeedAGPRs(); +}]; + +class AgprMAIFrag : MAIFrag { + let GISelPredicateCode = MayNeedAGPRs_gisel; +} + +class VgprMAIFrag : MAIFrag { + let GISelPredicateCode = MayNotNeedAGPRs_gisel; +} let SubtargetPredicate = HasMAIInsts in { @@ -812,8 +870,8 @@ class WMMAOpSelPat : class WMMAUIClampPat : GCNPat < (P.DstVT (node - (DotIUVOP3PMods i32:$src0_modifiers), (P.Src0VT P.Src0VT:$src0), - (DotIUVOP3PMods i32:$src1_modifiers), (P.Src1VT P.Src1VT:$src1), + (VOP3PModsNeg i32:$src0_modifiers), (P.Src0VT P.Src0VT:$src0), + (VOP3PModsNeg i32:$src1_modifiers), (P.Src1VT P.Src1VT:$src1), (P.Src2VT P.Src2VT:$src2), (i1 timm:$clamp) )), (P.DstVT (Inst i32:$src0_modifiers, P.Src0VT:$src0, i32:$src1_modifiers, P.Src1VT:$src1, (i32 8), P.Src2VT:$src2, i1:$clamp)) @@ -1003,6 +1061,11 @@ defm V_PK_MAX_NUM_F16 : VOP3P_Real_with_name_gfx12<0x1c, "V_PK_MAX_F16", "v_pk_m defm V_PK_MINIMUM_F16 : VOP3P_Real_gfx12<0x1d>; defm V_PK_MAXIMUM_F16 : VOP3P_Real_gfx12<0x1e>; +defm V_DOT4_F32_FP8_BF8 : VOP3P_Realtriple; +defm V_DOT4_F32_BF8_FP8 : VOP3P_Realtriple; +defm V_DOT4_F32_FP8_FP8 : VOP3P_Realtriple; +defm V_DOT4_F32_BF8_BF8 : VOP3P_Realtriple; + //===----------------------------------------------------------------------===// // GFX11 //===----------------------------------------------------------------------===// diff --git a/llvm/lib/Target/AMDGPU/VOPCInstructions.td b/llvm/lib/Target/AMDGPU/VOPCInstructions.td index e5b801048e6..3ca97f0291e 100644 --- a/llvm/lib/Target/AMDGPU/VOPCInstructions.td +++ b/llvm/lib/Target/AMDGPU/VOPCInstructions.td @@ -61,13 +61,13 @@ class VOPC_Profile sched, ValueType vt0, ValueType vt1 = vt let AsmDPP16 = AsmDPP#"$fi"; // VOPC DPP Instructions do not need an old operand let TieRegDPP = ""; - let InsDPP = getInsDPP, Src0DPP, Src1DPP, Src2DPP, + let InsDPP = getInsDPP, Src0DPP, Src1DPP, Src2DPP, NumSrcArgs, HasModifiers, Src0ModDPP, Src1ModDPP, Src2ModDPP, 0/*HasOld*/>.ret; - let InsDPP16 = getInsDPP16, Src0DPP, Src1DPP, Src2DPP, + let InsDPP16 = getInsDPP16, Src0DPP, Src1DPP, Src2DPP, NumSrcArgs, HasModifiers, Src0ModDPP, Src1ModDPP, Src2ModDPP, 0/*HasOld*/>.ret; - let InsDPP8 = getInsDPP8, Src0DPP, Src1DPP, Src2DPP, + let InsDPP8 = getInsDPP8, Src0DPP, Src1DPP, Src2DPP, NumSrcArgs, HasModifiers, Src0ModDPP, Src1ModDPP, Src2ModDPP, 0/*HasOld*/>.ret; @@ -88,10 +88,10 @@ multiclass VOPC_Profile_t16 sched, ValueType vt0, ValueType def NAME : VOPC_Profile; def _t16 : VOPC_Profile { let IsTrue16 = 1; - let Src1RC32 = RegisterOperand.ret>; - let Src0DPP = getVregSrcForVT_t16.ret; - let Src1DPP = getVregSrcForVT_t16.ret; - let Src2DPP = getVregSrcForVT_t16.ret; + let Src1RC32 = getVregSrcForVT.ret; + let Src0DPP = getVregSrcForVT.ret; + let Src1DPP = getVregSrcForVT.ret; + let Src2DPP = getVregSrcForVT.ret; let Src0ModDPP = getSrcModDPP_t16.ret; let Src1ModDPP = getSrcModDPP_t16.ret; let Src2ModDPP = getSrcModDPP_t16.ret; @@ -108,8 +108,8 @@ class VOPC_NoSdst_Profile sched, ValueType vt0, let InsSDWA = (ins Src0ModSDWA:$src0_modifiers, Src0SDWA:$src0, Src1ModSDWA:$src1_modifiers, Src1SDWA:$src1, src0_sel:$src0_sel, src1_sel:$src1_sel); - let AsmVOP3Base = !if(isFloatType.ret, "$src0_modifiers, $src1_modifiers$clamp", - "$src0, $src1"); + let AsmVOP3Base = !if(Src0VT.isFP, "$src0_modifiers, $src1_modifiers$clamp", + "$src0, $src1"); let AsmSDWA9 = "$src0_modifiers, $src1_modifiers $src0_sel $src1_sel"; let EmitDst = 0; } @@ -118,10 +118,10 @@ multiclass VOPC_NoSdst_Profile_t16 sched, ValueType vt0, Va def NAME : VOPC_NoSdst_Profile; def _t16 : VOPC_NoSdst_Profile { let IsTrue16 = 1; - let Src1RC32 = RegisterOperand.ret>; - let Src0DPP = getVregSrcForVT_t16.ret; - let Src1DPP = getVregSrcForVT_t16.ret; - let Src2DPP = getVregSrcForVT_t16.ret; + let Src1RC32 = getVregSrcForVT.ret; + let Src0DPP = getVregSrcForVT.ret; + let Src1DPP = getVregSrcForVT.ret; + let Src2DPP = getVregSrcForVT.ret; let Src0ModDPP = getSrcModDPP_t16.ret; let Src1ModDPP = getSrcModDPP_t16.ret; let Src2ModDPP = getSrcModDPP_t16.ret; @@ -146,7 +146,7 @@ class VOPC_Pseudo pattern=[], let mayStore = 0; let hasSideEffects = 0; - let ReadsModeReg = isFloatType.ret; + let ReadsModeReg = P.Src0VT.isFP; let VALU = 1; let VOPC = 1; @@ -789,11 +789,11 @@ multiclass VOPC_Class_Profile_t16 sched> { def NAME : VOPC_Class_Profile; def _t16 : VOPC_Class_Profile { let IsTrue16 = 1; - let Src1RC32 = RegisterOperand.ret>; + let Src1RC32 = getVregSrcForVT.ret; let Src1RC64 = VSrc_b32; - let Src0DPP = getVregSrcForVT_t16.ret; - let Src1DPP = getVregSrcForVT_t16.ret; - let Src2DPP = getVregSrcForVT_t16.ret; + let Src0DPP = getVregSrcForVT.ret; + let Src1DPP = getVregSrcForVT.ret; + let Src2DPP = getVregSrcForVT.ret; let Src0ModDPP = getSrcModDPP_t16.ret; let Src1ModDPP = getSrcModDPP_t16.ret; let Src2ModDPP = getSrcModDPP_t16.ret; @@ -816,11 +816,11 @@ multiclass VOPC_Class_NoSdst_Profile_t16 sched> { def NAME : VOPC_Class_NoSdst_Profile; def _t16 : VOPC_Class_NoSdst_Profile { let IsTrue16 = 1; - let Src1RC32 = RegisterOperand.ret>; + let Src1RC32 = getVregSrcForVT.ret; let Src1RC64 = VSrc_b32; - let Src0DPP = getVregSrcForVT_t16.ret; - let Src1DPP = getVregSrcForVT_t16.ret; - let Src2DPP = getVregSrcForVT_t16.ret; + let Src0DPP = getVregSrcForVT.ret; + let Src1DPP = getVregSrcForVT.ret; + let Src2DPP = getVregSrcForVT.ret; let Src0ModDPP = getSrcModDPP_t16.ret; let Src1ModDPP = getSrcModDPP_t16.ret; let Src2ModDPP = getSrcModDPP_t16.ret; diff --git a/llvm/lib/Target/AMDGPU/VOPInstructions.td b/llvm/lib/Target/AMDGPU/VOPInstructions.td index c4b9e706309..df505c3365c 100644 --- a/llvm/lib/Target/AMDGPU/VOPInstructions.td +++ b/llvm/lib/Target/AMDGPU/VOPInstructions.td @@ -152,7 +152,7 @@ class VOP3_Pseudo pattern = [], let ClampLo = P.HasClampLo; let ClampHi = P.HasClampHi; - let ReadsModeReg = !or(isFloatType.ret, isFloatType.ret); + let ReadsModeReg = !or(P.DstVT.isFP, P.Src0VT.isFP); let mayRaiseFPException = ReadsModeReg; let Uses = !if(ReadsModeReg, [MODE, EXEC], [EXEC]); @@ -169,6 +169,7 @@ class VOP3_Pseudo pattern = [], class VOP3P_Pseudo pattern = []> : VOP3_Pseudo { let VOP3P = 1; + let IsDOT = P.IsDOT; } class VOP_Real { @@ -387,7 +388,7 @@ class VOP3Pe op, VOPProfile P> : Enc64 { let Inst{12} = !if(!and(P.HasSrc1, P.HasOpSel), src1_modifiers{2}, 0); // op_sel(1) let Inst{13} = !if(!and(P.HasSrc2, P.HasOpSel), src2_modifiers{2}, 0); // op_sel(2) - let Inst{14} = !if(!and(P.HasSrc2, P.HasOpSel), src2_modifiers{3}, ?); // op_sel_hi(2) + let Inst{14} = !if(!and(P.HasSrc2, P.HasOpSel), src2_modifiers{3}, !if(P.IsDOT, 1, ?)); // op_sel_hi(2) let Inst{15} = !if(P.HasClamp, clamp{0}, 0); @@ -396,8 +397,8 @@ class VOP3Pe op, VOPProfile P> : Enc64 { let Inst{40-32} = !if(P.HasSrc0, src0, 0); let Inst{49-41} = !if(P.HasSrc1, src1, 0); let Inst{58-50} = !if(P.HasSrc2, src2, 0); - let Inst{59} = !if(!and(P.HasSrc0, P.HasOpSel), src0_modifiers{3}, ?); // op_sel_hi(0) - let Inst{60} = !if(!and(P.HasSrc1, P.HasOpSel), src1_modifiers{3}, ?); // op_sel_hi(1) + let Inst{59} = !if(!and(P.HasSrc0, P.HasOpSel), src0_modifiers{3}, !if(P.IsDOT, 1, ?)); // op_sel_hi(0) + let Inst{60} = !if(!and(P.HasSrc1, P.HasOpSel), src1_modifiers{3}, !if(P.IsDOT, 1, ?)); // op_sel_hi(1) let Inst{61} = !if(P.HasSrc0Mods, src0_modifiers{0}, 0); // neg (lo) let Inst{62} = !if(P.HasSrc1Mods, src1_modifiers{0}, 0); // neg (lo) let Inst{63} = !if(P.HasSrc2Mods, src2_modifiers{0}, 0); // neg (lo) @@ -599,7 +600,7 @@ class VOP_SDWA_Pseudo pattern=[]> : let VALU = 1; let SDWA = 1; - let ReadsModeReg = !or(isFloatType.ret, isFloatType.ret); + let ReadsModeReg = !or(P.DstVT.isFP, P.Src0VT.isFP); let mayRaiseFPException = ReadsModeReg; let Uses = !if(ReadsModeReg, [MODE, EXEC], [EXEC]); @@ -772,12 +773,12 @@ class VOP3P_DPPe_Common_Base op, VOPProfile P> : Enc96 { let Inst{11} = !if(!and(P.HasSrc0, P.HasOpSel), src0_modifiers{2}, 0); // op_sel(0) let Inst{12} = !if(!and(P.HasSrc1, P.HasOpSel), src1_modifiers{2}, 0); // op_sel(1) let Inst{13} = !if(!and(P.HasSrc2, P.HasOpSel), src2_modifiers{2}, 0); // op_sel(2) - let Inst{14} = !if(!and(P.HasSrc2, P.HasOpSel), src2_modifiers{3}, ?); // op_sel_hi(2) + let Inst{14} = !if(!and(P.HasSrc2, P.HasOpSel), src2_modifiers{3}, !if(P.IsDOT, 1, ?)); // op_sel_hi(2) let Inst{15} = !if(P.HasClamp, clamp{0}, 0); let Inst{22-16} = op; let Inst{31-23} = 0x198; // encoding - let Inst{59} = !if(!and(P.HasSrc0, P.HasOpSel), src0_modifiers{3}, ?); // op_sel_hi(0) - let Inst{60} = !if(!and(P.HasSrc1, P.HasOpSel), src1_modifiers{3}, ?); // op_sel_hi(1) + let Inst{59} = !if(!and(P.HasSrc0, P.HasOpSel), src0_modifiers{3}, !if(P.IsDOT, 1, ?)); // op_sel_hi(0) + let Inst{60} = !if(!and(P.HasSrc1, P.HasOpSel), src1_modifiers{3}, !if(P.IsDOT, 1, ?)); // op_sel_hi(1) let Inst{61} = !if(P.HasSrc0Mods, src0_modifiers{0}, 0); // neg (lo) let Inst{62} = !if(P.HasSrc1Mods, src1_modifiers{0}, 0); // neg (lo) let Inst{63} = !if(P.HasSrc2Mods, src2_modifiers{0}, 0); // neg (lo) @@ -811,7 +812,7 @@ class VOP_DPP_Pseudo pattern=[], let DPP = 1; let Size = 8; - let ReadsModeReg = !or(isFloatType.ret, isFloatType.ret); + let ReadsModeReg = !or(P.DstVT.isFP, P.Src0VT.isFP); let mayRaiseFPException = ReadsModeReg; let Uses = !if(ReadsModeReg, [MODE, EXEC], [EXEC]); diff --git a/llvm/lib/Target/ARM/ARM.td b/llvm/lib/Target/ARM/ARM.td index 97d1444a553..87778156830 100644 --- a/llvm/lib/Target/ARM/ARM.td +++ b/llvm/lib/Target/ARM/ARM.td @@ -704,6 +704,12 @@ def HasV9_4aOps : SubtargetFeature<"v9.4a", "HasV9_4aOps", "true", "Support ARM v9.4a instructions", [HasV8_9aOps, HasV9_3aOps]>; +// Armv9.5-A is a v9-only architecture. From v9.5-A onwards there's no mapping +// to an equivalent v8.x version. +def HasV9_5aOps : SubtargetFeature<"v9.5a", "HasV9_5aOps", "true", + "Support ARM v9.5a instructions", + [HasV9_4aOps]>; + def HasV8_1MMainlineOps : SubtargetFeature< "v8.1m.main", "HasV8_1MMainlineOps", "true", "Support ARM v8-1M Mainline instructions", @@ -1139,6 +1145,18 @@ def ARMv94a : Architecture<"armv9.4-a", "ARMv94a", [HasV9_4aOps, FeatureCRC, FeatureRAS, FeatureDotProd]>; +def ARMv95a : Architecture<"armv9.5-a", "ARMv95a", [HasV9_5aOps, + FeatureAClass, + FeatureDB, + FeatureFPARMv8, + FeatureNEON, + FeatureDSP, + FeatureTrustZone, + FeatureMP, + FeatureVirtualization, + FeatureCRC, + FeatureRAS, + FeatureDotProd]>; def ARMv8r : Architecture<"armv8-r", "ARMv8r", [HasV8Ops, FeatureRClass, diff --git a/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp b/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp index ef02dc99701..4bf65be6f10 100644 --- a/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp +++ b/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp @@ -5874,11 +5874,10 @@ std::optional ARMBaseInstrInfo::getOutliningCandidateInfo( std::vector &RepeatedSequenceLocs) const { outliner::Candidate &FirstCand = RepeatedSequenceLocs[0]; - unsigned SequenceSize = - std::accumulate(FirstCand.front(), std::next(FirstCand.back()), 0, - [this](unsigned Sum, const MachineInstr &MI) { - return Sum + getInstSizeInBytes(MI); - }); + + unsigned SequenceSize = 0; + for (auto &MI : FirstCand) + SequenceSize += getInstSizeInBytes(MI); // Properties about candidate MBBs that hold for all of them. unsigned FlagsSetInAll = 0xF; @@ -5965,7 +5964,7 @@ ARMBaseInstrInfo::getOutliningCandidateInfo( // At this point, we have only "safe" candidates to outline. Figure out // frame + call instruction information. - unsigned LastInstrOpcode = RepeatedSequenceLocs[0].back()->getOpcode(); + unsigned LastInstrOpcode = RepeatedSequenceLocs[0].back().getOpcode(); // Helper lambda which sets call information for every candidate. auto SetCandidateCallInfo = @@ -5998,7 +5997,7 @@ ARMBaseInstrInfo::getOutliningCandidateInfo( // If the last instruction in any candidate is a terminator, then we should // tail call all of the candidates. - if (RepeatedSequenceLocs[0].back()->isTerminator()) { + if (RepeatedSequenceLocs[0].back().isTerminator()) { FrameID = MachineOutlinerTailCall; NumBytesToCreateFrame = Costs.FrameTailCall; SetCandidateCallInfo(MachineOutlinerTailCall, Costs.CallTailCall); @@ -6024,7 +6023,7 @@ ARMBaseInstrInfo::getOutliningCandidateInfo( const bool LRIsAvailable = C.getMBB()->isReturnBlock() && !Last->isCall() ? isLRAvailable(TRI, Last, - (MachineBasicBlock::reverse_iterator)C.front()) + (MachineBasicBlock::reverse_iterator)C.begin()) : C.isAvailableAcrossAndOutOfSeq(ARM::LR, TRI); if (LRIsAvailable) { FrameID = MachineOutlinerNoLRSave; @@ -6072,7 +6071,7 @@ ARMBaseInstrInfo::getOutliningCandidateInfo( if (FlagsSetInAll & MachineOutlinerMBBFlags::HasCalls) { // check if the range contains a call. These require a save + restore of // the link register. - if (std::any_of(FirstCand.front(), FirstCand.back(), + if (std::any_of(FirstCand.begin(), std::prev(FirstCand.end()), [](const MachineInstr &MI) { return MI.isCall(); })) NumBytesToCreateFrame += Costs.SaveRestoreLROnStack; @@ -6082,7 +6081,7 @@ ARMBaseInstrInfo::getOutliningCandidateInfo( // call without it being valid to tail call this sequence. We should // consider this as well. else if (FrameID != MachineOutlinerThunk && - FrameID != MachineOutlinerTailCall && FirstCand.back()->isCall()) + FrameID != MachineOutlinerTailCall && FirstCand.back().isCall()) NumBytesToCreateFrame += Costs.SaveRestoreLROnStack; } diff --git a/llvm/lib/Target/ARM/ARMCallLowering.cpp b/llvm/lib/Target/ARM/ARMCallLowering.cpp index f9d9930cec6..38faf5c295a 100644 --- a/llvm/lib/Target/ARM/ARMCallLowering.cpp +++ b/llvm/lib/Target/ARM/ARMCallLowering.cpp @@ -166,11 +166,11 @@ struct ARMOutgoingValueHandler : public CallLowering::OutgoingValueHandler { assignValueToReg(NewRegs[0], VA.getLocReg(), VA); assignValueToReg(NewRegs[1], NextVA.getLocReg(), NextVA); }; - return 1; + return 2; } assignValueToReg(NewRegs[0], VA.getLocReg(), VA); assignValueToReg(NewRegs[1], NextVA.getLocReg(), NextVA); - return 1; + return 2; } MachineInstrBuilder MIB; @@ -341,7 +341,7 @@ struct ARMIncomingValueHandler : public CallLowering::IncomingValueHandler { MIRBuilder.buildMergeLikeInstr(Arg.Regs[0], NewRegs); - return 1; + return 2; } /// Marking a physical register as used is different between formal diff --git a/llvm/lib/Target/ARM/ARMISelLowering.cpp b/llvm/lib/Target/ARM/ARMISelLowering.cpp index f8a281032c7..23852cf4979 100644 --- a/llvm/lib/Target/ARM/ARMISelLowering.cpp +++ b/llvm/lib/Target/ARM/ARMISelLowering.cpp @@ -4246,8 +4246,7 @@ ARMTargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG, static SDValue LowerATOMIC_FENCE(SDValue Op, SelectionDAG &DAG, const ARMSubtarget *Subtarget) { SDLoc dl(Op); - ConstantSDNode *SSIDNode = cast(Op.getOperand(2)); - auto SSID = static_cast(SSIDNode->getZExtValue()); + auto SSID = static_cast(Op.getConstantOperandVal(2)); if (SSID == SyncScope::SingleThread) return Op; @@ -4261,8 +4260,8 @@ static SDValue LowerATOMIC_FENCE(SDValue Op, SelectionDAG &DAG, DAG.getConstant(0, dl, MVT::i32)); } - ConstantSDNode *OrdN = cast(Op.getOperand(1)); - AtomicOrdering Ord = static_cast(OrdN->getZExtValue()); + AtomicOrdering Ord = + static_cast(Op.getConstantOperandVal(1)); ARM_MB::MemBOpt Domain = ARM_MB::ISH; if (Subtarget->isMClass()) { // Only a full system barrier exists in the M-class architectures. @@ -20087,8 +20086,8 @@ void ARMTargetLowering::computeKnownBitsForTargetNode(const SDValue Op, return; } case ISD::INTRINSIC_W_CHAIN: { - ConstantSDNode *CN = cast(Op->getOperand(1)); - Intrinsic::ID IntID = static_cast(CN->getZExtValue()); + Intrinsic::ID IntID = + static_cast(Op->getConstantOperandVal(1)); switch (IntID) { default: return; case Intrinsic::arm_ldaex: diff --git a/llvm/lib/Target/ARM/ARMInstrMVE.td b/llvm/lib/Target/ARM/ARMInstrMVE.td index fa25c571a9b..12c3968b9ce 100644 --- a/llvm/lib/Target/ARM/ARMInstrMVE.td +++ b/llvm/lib/Target/ARM/ARMInstrMVE.td @@ -478,7 +478,7 @@ def MVE_URSHR : MVE_ScalarShiftSRegImm<"urshr", 0b01>; class MVE_ScalarShiftSRegReg op5_4> : MVE_ScalarShiftSingleReg("int_arm_mve_" # iname) (i32 rGPR:$RdaSrc), (i32 rGPR:$Rm))))]> { diff --git a/llvm/lib/Target/ARM/ARMSubtarget.h b/llvm/lib/Target/ARM/ARMSubtarget.h index 43b4123a1b5..91f3978b041 100644 --- a/llvm/lib/Target/ARM/ARMSubtarget.h +++ b/llvm/lib/Target/ARM/ARMSubtarget.h @@ -132,6 +132,7 @@ protected: ARMv92a, ARMv93a, ARMv94a, + ARMv95a, }; public: diff --git a/llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp b/llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp index 18dccb26b87..e534f1f7146 100644 --- a/llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp +++ b/llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp @@ -8308,6 +8308,14 @@ bool ARMAsmParser::validateInstruction(MCInst &Inst, return Error (Operands[3]->getStartLoc(), "Q-register indexes must be 2 and 0 or 3 and 1"); break; } + case ARM::MVE_SQRSHR: + case ARM::MVE_UQRSHL: { + if (Operands[2]->getReg() == Operands[3]->getReg()) { + return Error(Operands[2]->getStartLoc(), + "Rda register and Rm register can't be identical"); + } + break; + } case ARM::UMAAL: case ARM::UMLAL: case ARM::UMULL: @@ -12668,11 +12676,7 @@ bool ARMAsmParser::enableArchExtFeature(StringRef Name, SMLoc &ExtLoc) { {ARM::AEK_MAVERICK, {}, {}}, {ARM::AEK_XSCALE, {}, {}}, }; - bool EnableFeature = true; - if (Name.starts_with_insensitive("no")) { - EnableFeature = false; - Name = Name.substr(2); - } + bool EnableFeature = !Name.consume_front_insensitive("no"); uint64_t FeatureKind = ARM::parseArchExt(Name); if (FeatureKind == ARM::AEK_INVALID) return Error(ExtLoc, "unknown architectural extension: " + Name); diff --git a/llvm/lib/Target/ARM/MCTargetDesc/ARMAsmBackend.cpp b/llvm/lib/Target/ARM/MCTargetDesc/ARMAsmBackend.cpp index 534434fef5a..1d17bb349f2 100644 --- a/llvm/lib/Target/ARM/MCTargetDesc/ARMAsmBackend.cpp +++ b/llvm/lib/Target/ARM/MCTargetDesc/ARMAsmBackend.cpp @@ -67,8 +67,6 @@ ARMAsmBackendELF::getFixupKind(StringRef Name) const { } const MCFixupKindInfo &ARMAsmBackend::getFixupKindInfo(MCFixupKind Kind) const { - unsigned IsPCRelConstant = - MCFixupKindInfo::FKF_IsPCRel | MCFixupKindInfo::FKF_Constant; const static MCFixupKindInfo InfosLE[ARM::NumTargetFixupKinds] = { // This table *must* be in the order that the fixup_* kinds are defined in // ARMFixupKinds.h. @@ -79,13 +77,14 @@ const MCFixupKindInfo &ARMAsmBackend::getFixupKindInfo(MCFixupKind Kind) const { MCFixupKindInfo::FKF_IsPCRel | MCFixupKindInfo::FKF_IsAlignedDownTo32Bits}, {"fixup_arm_pcrel_10_unscaled", 0, 32, MCFixupKindInfo::FKF_IsPCRel}, - {"fixup_arm_pcrel_10", 0, 32, IsPCRelConstant}, + {"fixup_arm_pcrel_10", 0, 32, MCFixupKindInfo::FKF_IsPCRel}, {"fixup_t2_pcrel_10", 0, 32, MCFixupKindInfo::FKF_IsPCRel | MCFixupKindInfo::FKF_IsAlignedDownTo32Bits}, {"fixup_arm_pcrel_9", 0, 32, MCFixupKindInfo::FKF_IsPCRel}, {"fixup_t2_pcrel_9", 0, 32, - IsPCRelConstant | MCFixupKindInfo::FKF_IsAlignedDownTo32Bits}, + MCFixupKindInfo::FKF_IsPCRel | + MCFixupKindInfo::FKF_IsAlignedDownTo32Bits}, {"fixup_arm_ldst_abs_12", 0, 32, 0}, {"fixup_thumb_adr_pcrel_10", 0, 8, MCFixupKindInfo::FKF_IsPCRel | @@ -140,19 +139,22 @@ const MCFixupKindInfo &ARMAsmBackend::getFixupKindInfo(MCFixupKind Kind) const { MCFixupKindInfo::FKF_IsPCRel | MCFixupKindInfo::FKF_IsAlignedDownTo32Bits}, {"fixup_arm_pcrel_10_unscaled", 0, 32, MCFixupKindInfo::FKF_IsPCRel}, - {"fixup_arm_pcrel_10", 0, 32, IsPCRelConstant}, + {"fixup_arm_pcrel_10", 0, 32, MCFixupKindInfo::FKF_IsPCRel}, {"fixup_t2_pcrel_10", 0, 32, MCFixupKindInfo::FKF_IsPCRel | MCFixupKindInfo::FKF_IsAlignedDownTo32Bits}, {"fixup_arm_pcrel_9", 0, 32, MCFixupKindInfo::FKF_IsPCRel}, {"fixup_t2_pcrel_9", 0, 32, - IsPCRelConstant | MCFixupKindInfo::FKF_IsAlignedDownTo32Bits}, + MCFixupKindInfo::FKF_IsPCRel | + MCFixupKindInfo::FKF_IsAlignedDownTo32Bits}, {"fixup_arm_ldst_abs_12", 0, 32, 0}, {"fixup_thumb_adr_pcrel_10", 8, 8, - IsPCRelConstant | MCFixupKindInfo::FKF_IsAlignedDownTo32Bits}, - {"fixup_arm_adr_pcrel_12", 0, 32, IsPCRelConstant}, + MCFixupKindInfo::FKF_IsPCRel | + MCFixupKindInfo::FKF_IsAlignedDownTo32Bits}, + {"fixup_arm_adr_pcrel_12", 0, 32, MCFixupKindInfo::FKF_IsPCRel}, {"fixup_t2_adr_pcrel_12", 0, 32, - IsPCRelConstant | MCFixupKindInfo::FKF_IsAlignedDownTo32Bits}, + MCFixupKindInfo::FKF_IsPCRel | + MCFixupKindInfo::FKF_IsAlignedDownTo32Bits}, {"fixup_arm_condbranch", 8, 24, MCFixupKindInfo::FKF_IsPCRel}, {"fixup_arm_uncondbranch", 8, 24, MCFixupKindInfo::FKF_IsPCRel}, {"fixup_t2_condbranch", 0, 32, MCFixupKindInfo::FKF_IsPCRel}, diff --git a/llvm/lib/Target/ARM/MCTargetDesc/ARMELFStreamer.cpp b/llvm/lib/Target/ARM/MCTargetDesc/ARMELFStreamer.cpp index 9c9af606807..1d80af590d1 100644 --- a/llvm/lib/Target/ARM/MCTargetDesc/ARMELFStreamer.cpp +++ b/llvm/lib/Target/ARM/MCTargetDesc/ARMELFStreamer.cpp @@ -898,6 +898,7 @@ void ARMTargetELFStreamer::emitArchDefaultAttributes() { case ARM::ArchKind::ARMV9_2A: case ARM::ArchKind::ARMV9_3A: case ARM::ArchKind::ARMV9_4A: + case ARM::ArchKind::ARMV9_5A: S.setAttributeItem(CPU_arch_profile, ApplicationProfile, false); S.setAttributeItem(ARM_ISA_use, Allowed, false); S.setAttributeItem(THUMB_ISA_use, AllowThumb32, false); diff --git a/llvm/lib/Target/ARM/MCTargetDesc/ARMFixupKinds.h b/llvm/lib/Target/ARM/MCTargetDesc/ARMFixupKinds.h index 3bcea577b9b..003d5414fab 100644 --- a/llvm/lib/Target/ARM/MCTargetDesc/ARMFixupKinds.h +++ b/llvm/lib/Target/ARM/MCTargetDesc/ARMFixupKinds.h @@ -28,7 +28,7 @@ enum Fixups { // immediate). fixup_arm_pcrel_10, // Equivalent to fixup_arm_pcrel_10, accounting for the short-swapped encoding - // of Thumb2 instructions. + // of Thumb2 instructions. Also used by LDRD in Thumb mode. fixup_t2_pcrel_10, // 9-bit PC relative relocation for symbol addresses used in VFP instructions // where bit 0 not encoded (so it's encoded as an 8-bit immediate). diff --git a/llvm/lib/Target/ARM/MVEGatherScatterLowering.cpp b/llvm/lib/Target/ARM/MVEGatherScatterLowering.cpp index 48e63e04b11..bcfedd34142 100644 --- a/llvm/lib/Target/ARM/MVEGatherScatterLowering.cpp +++ b/llvm/lib/Target/ARM/MVEGatherScatterLowering.cpp @@ -898,8 +898,8 @@ void MVEGatherScatterLowering::pushOutAdd(PHINode *&Phi, Phi->addIncoming(NewIndex, Phi->getIncomingBlock(StartIndex)); Phi->addIncoming(Phi->getIncomingValue(IncrementIndex), Phi->getIncomingBlock(IncrementIndex)); - Phi->removeIncomingValue(IncrementIndex); - Phi->removeIncomingValue(StartIndex); + Phi->removeIncomingValue(1); + Phi->removeIncomingValue((unsigned)0); } void MVEGatherScatterLowering::pushOutMulShl(unsigned Opcode, PHINode *&Phi, diff --git a/llvm/lib/Target/ARM/Thumb1InstrInfo.cpp b/llvm/lib/Target/ARM/Thumb1InstrInfo.cpp index e2f3fad2007..85eabdb17ad 100644 --- a/llvm/lib/Target/ARM/Thumb1InstrInfo.cpp +++ b/llvm/lib/Target/ARM/Thumb1InstrInfo.cpp @@ -135,14 +135,14 @@ void Thumb1InstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB, void Thumb1InstrInfo::expandLoadStackGuard( MachineBasicBlock::iterator MI) const { MachineFunction &MF = *MI->getParent()->getParent(); - const TargetMachine &TM = MF.getTarget(); const ARMSubtarget &ST = MF.getSubtarget(); + const auto *GV = cast((*MI->memoperands_begin())->getValue()); assert(MF.getFunction().getParent()->getStackProtectorGuard() != "tls" && "TLS stack protector not supported for Thumb1 targets"); unsigned Instr; - if (TM.isPositionIndependent()) + if (!GV->isDSOLocal()) Instr = ARM::tLDRLIT_ga_pcrel; else if (ST.genExecuteOnly() && ST.hasV8MBaselineOps()) Instr = ARM::t2MOVi32imm; diff --git a/llvm/lib/Target/ARM/Thumb2InstrInfo.cpp b/llvm/lib/Target/ARM/Thumb2InstrInfo.cpp index 2ea0eaa0aad..083f25f49de 100644 --- a/llvm/lib/Target/ARM/Thumb2InstrInfo.cpp +++ b/llvm/lib/Target/ARM/Thumb2InstrInfo.cpp @@ -261,10 +261,8 @@ void Thumb2InstrInfo::expandLoadStackGuard( return; } - const GlobalValue *GV = - cast((*MI->memoperands_begin())->getValue()); - - if (MF.getSubtarget().isGVInGOT(GV)) + const auto *GV = cast((*MI->memoperands_begin())->getValue()); + if (MF.getSubtarget().isTargetELF() && !GV->isDSOLocal()) expandLoadStackGuardBase(MI, ARM::t2LDRLIT_ga_pcrel, ARM::t2LDRi12); else if (MF.getTarget().isPositionIndependent()) expandLoadStackGuardBase(MI, ARM::t2MOV_ga_pcrel, ARM::t2LDRi12); diff --git a/llvm/lib/Target/Hexagon/Disassembler/HexagonDisassembler.cpp b/llvm/lib/Target/Hexagon/Disassembler/HexagonDisassembler.cpp index c7e22d7d308..44a5cd73c6e 100644 --- a/llvm/lib/Target/Hexagon/Disassembler/HexagonDisassembler.cpp +++ b/llvm/lib/Target/Hexagon/Disassembler/HexagonDisassembler.cpp @@ -512,6 +512,8 @@ DecodeStatus HexagonDisassembler::getSingleInstruction(MCInst &MI, MCInst &MCB, const bool Rev = HexagonMCInstrInfo::IsReverseVecRegPair(Producer); const unsigned ProdPairIndex = Rev ? Producer - Hexagon::WR0 : Producer - Hexagon::W0; + if (Rev) + SubregBit = !SubregBit; Producer = (ProdPairIndex << 1) + SubregBit + Hexagon::V0; } else if (SubregBit) // Hexagon PRM 10.11 New-value operands diff --git a/llvm/lib/Target/Hexagon/HexagonEarlyIfConv.cpp b/llvm/lib/Target/Hexagon/HexagonEarlyIfConv.cpp index f7227dca3b6..cb820e21589 100644 --- a/llvm/lib/Target/Hexagon/HexagonEarlyIfConv.cpp +++ b/llvm/lib/Target/Hexagon/HexagonEarlyIfConv.cpp @@ -601,8 +601,6 @@ bool HexagonEarlyIfConversion::visitBlock(MachineBasicBlock *B, // Visit all dominated blocks from the same loop first, then process B. MachineDomTreeNode *N = MDT->getNode(B); - using GTN = GraphTraits; - // We will change CFG/DT during this traversal, so take precautions to // avoid problems related to invalidated iterators. In fact, processing // a child C of B cannot cause another child to be removed, but it can @@ -611,7 +609,7 @@ bool HexagonEarlyIfConversion::visitBlock(MachineBasicBlock *B, // prior to processing B, so there is no need to process it again. // Simply keep a list of children of B, and traverse that list. using DTNodeVectType = SmallVector; - DTNodeVectType Cn(GTN::child_begin(N), GTN::child_end(N)); + DTNodeVectType Cn(llvm::children(N)); for (auto &I : Cn) { MachineBasicBlock *SB = I->getBlock(); if (!Deleted.count(SB)) diff --git a/llvm/lib/Target/Hexagon/HexagonISelDAGToDAG.cpp b/llvm/lib/Target/Hexagon/HexagonISelDAGToDAG.cpp index defb1f7324f..e4127b0b94c 100644 --- a/llvm/lib/Target/Hexagon/HexagonISelDAGToDAG.cpp +++ b/llvm/lib/Target/Hexagon/HexagonISelDAGToDAG.cpp @@ -701,8 +701,7 @@ void HexagonDAGToDAGISel::SelectIntrinsicWOChain(SDNode *N) { void HexagonDAGToDAGISel::SelectExtractSubvector(SDNode *N) { SDValue Inp = N->getOperand(0); MVT ResTy = N->getValueType(0).getSimpleVT(); - auto IdxN = cast(N->getOperand(1)); - unsigned Idx = IdxN->getZExtValue(); + unsigned Idx = N->getConstantOperandVal(1); [[maybe_unused]] MVT InpTy = Inp.getValueType().getSimpleVT(); [[maybe_unused]] unsigned ResLen = ResTy.getVectorNumElements(); diff --git a/llvm/lib/Target/Hexagon/HexagonISelDAGToDAGHVX.cpp b/llvm/lib/Target/Hexagon/HexagonISelDAGToDAGHVX.cpp index fb156f2583e..ec5435949ae 100644 --- a/llvm/lib/Target/Hexagon/HexagonISelDAGToDAGHVX.cpp +++ b/llvm/lib/Target/Hexagon/HexagonISelDAGToDAGHVX.cpp @@ -2573,8 +2573,7 @@ SDValue HvxSelector::getVectorConstant(ArrayRef Data, void HvxSelector::selectExtractSubvector(SDNode *N) { SDValue Inp = N->getOperand(0); MVT ResTy = N->getValueType(0).getSimpleVT(); - auto IdxN = cast(N->getOperand(1)); - unsigned Idx = IdxN->getZExtValue(); + unsigned Idx = N->getConstantOperandVal(1); [[maybe_unused]] MVT InpTy = Inp.getValueType().getSimpleVT(); [[maybe_unused]] unsigned ResLen = ResTy.getVectorNumElements(); diff --git a/llvm/lib/Target/Hexagon/HexagonVectorCombine.cpp b/llvm/lib/Target/Hexagon/HexagonVectorCombine.cpp index aa12e9d513d..7231388445d 100644 --- a/llvm/lib/Target/Hexagon/HexagonVectorCombine.cpp +++ b/llvm/lib/Target/Hexagon/HexagonVectorCombine.cpp @@ -687,8 +687,7 @@ auto AlignVectors::createAdjustedPointer(IRBuilderBase &Builder, Value *Ptr, if (auto *I = dyn_cast(Ptr)) if (Instruction *New = CloneMap.lookup(I)) Ptr = New; - return Builder.CreateGEP(Type::getInt8Ty(HVC.F.getContext()), Ptr, - HVC.getConstInt(Adjust), "gep"); + return Builder.CreatePtrAdd(Ptr, HVC.getConstInt(Adjust), "gep"); } auto AlignVectors::createAlignedPointer(IRBuilderBase &Builder, Value *Ptr, diff --git a/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCInstrInfo.cpp b/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCInstrInfo.cpp index 9cf004cf4c9..a6de2ab9c75 100644 --- a/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCInstrInfo.cpp +++ b/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCInstrInfo.cpp @@ -1036,8 +1036,10 @@ unsigned HexagonMCInstrInfo::SubregisterBit(unsigned Consumer, unsigned Producer2) { // If we're a single vector consumer of a double producer, set subreg bit // based on if we're accessing the lower or upper register component - if (IsVecRegPair(Producer) && IsVecRegSingle(Consumer)) - return (Consumer - Hexagon::V0) & 0x1; + if (IsVecRegPair(Producer) && IsVecRegSingle(Consumer)) { + unsigned Rev = IsReverseVecRegPair(Producer); + return ((Consumer - Hexagon::V0) & 0x1) ^ Rev; + } if (Producer2 != Hexagon::NoRegister) return Consumer == Producer; return 0; diff --git a/llvm/lib/Target/LoongArch/LoongArch.td b/llvm/lib/Target/LoongArch/LoongArch.td index 75b65fe69f2..c2a669931d7 100644 --- a/llvm/lib/Target/LoongArch/LoongArch.td +++ b/llvm/lib/Target/LoongArch/LoongArch.td @@ -106,6 +106,18 @@ def FeatureRelax : SubtargetFeature<"relax", "HasLinkerRelax", "true", "Enable Linker relaxation">; +// Experimental auto vectorization +def FeatureAutoVec + : SubtargetFeature<"auto-vec", "HasExpAutoVec", "true", + "Experimental auto vectorization">; + +// Floating point approximation operation +def FeatureFrecipe + : SubtargetFeature<"frecipe", "HasFrecipe", "true", + "Support frecipe.{s/d} and frsqrte.{s/d} instructions.">; +def HasFrecipe : Predicate<"Subtarget->hasFrecipe()">; + + //===----------------------------------------------------------------------===// // Registers, instruction descriptions ... //===----------------------------------------------------------------------===// diff --git a/llvm/lib/Target/LoongArch/LoongArchFloat32InstrInfo.td b/llvm/lib/Target/LoongArch/LoongArchFloat32InstrInfo.td index 808d73958ff..d6a83c0c8cd 100644 --- a/llvm/lib/Target/LoongArch/LoongArchFloat32InstrInfo.td +++ b/llvm/lib/Target/LoongArch/LoongArchFloat32InstrInfo.td @@ -50,6 +50,8 @@ def FNEG_S : FP_ALU_2R<0x01141400>; def FSQRT_S : FP_ALU_2R<0x01144400>; def FRECIP_S : FP_ALU_2R<0x01145400>; def FRSQRT_S : FP_ALU_2R<0x01146400>; +def FRECIPE_S : FP_ALU_2R<0x01147400>; +def FRSQRTE_S : FP_ALU_2R<0x01148400>; def FSCALEB_S : FP_ALU_3R<0x01108000>; def FLOGB_S : FP_ALU_2R<0x01142400>; def FCOPYSIGN_S : FP_ALU_3R<0x01128000>; @@ -280,6 +282,12 @@ def : Pat<(loongarch_ftint FPR32:$src), (FTINTRZ_W_S FPR32:$src)>; // FP reciprocal operation def : Pat<(fdiv fpimm1, FPR32:$src), (FRECIP_S $src)>; +let Predicates = [HasFrecipe] in { +// FP approximate reciprocal operation +def : Pat<(int_loongarch_frecipe_s FPR32:$src), (FRECIPE_S FPR32:$src)>; +def : Pat<(int_loongarch_frsqrte_s FPR32:$src), (FRSQRTE_S FPR32:$src)>; +} + // fmadd.s: fj * fk + fa def : Pat<(fma FPR32:$fj, FPR32:$fk, FPR32:$fa), (FMADD_S $fj, $fk, $fa)>; diff --git a/llvm/lib/Target/LoongArch/LoongArchFloat64InstrInfo.td b/llvm/lib/Target/LoongArch/LoongArchFloat64InstrInfo.td index 6e0ac286e8f..30cce843964 100644 --- a/llvm/lib/Target/LoongArch/LoongArchFloat64InstrInfo.td +++ b/llvm/lib/Target/LoongArch/LoongArchFloat64InstrInfo.td @@ -34,6 +34,8 @@ def FNEG_D : FP_ALU_2R<0x01141800, FPR64>; def FSQRT_D : FP_ALU_2R<0x01144800, FPR64>; def FRECIP_D : FP_ALU_2R<0x01145800, FPR64>; def FRSQRT_D : FP_ALU_2R<0x01146800, FPR64>; +def FRECIPE_D : FP_ALU_2R<0x01147800, FPR64>; +def FRSQRTE_D : FP_ALU_2R<0x01148800, FPR64>; def FSCALEB_D : FP_ALU_3R<0x01110000, FPR64>; def FLOGB_D : FP_ALU_2R<0x01142800, FPR64>; def FCOPYSIGN_D : FP_ALU_3R<0x01130000, FPR64>; @@ -247,6 +249,12 @@ def : Pat<(f64 (fpextend FPR32:$src)), (FCVT_D_S FPR32:$src)>; // FP reciprocal operation def : Pat<(fdiv fpimm1, FPR64:$src), (FRECIP_D $src)>; +let Predicates = [HasFrecipe] in { +// FP approximate reciprocal operation +def : Pat<(int_loongarch_frecipe_d FPR64:$src), (FRECIPE_D FPR64:$src)>; +def : Pat<(int_loongarch_frsqrte_d FPR64:$src), (FRSQRTE_D FPR64:$src)>; +} + // fmadd.d: fj * fk + fa def : Pat<(fma FPR64:$fj, FPR64:$fk, FPR64:$fa), (FMADD_D $fj, $fk, $fa)>; diff --git a/llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp b/llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp index 70f782b8127..76c1a14fe01 100644 --- a/llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp +++ b/llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp @@ -265,6 +265,10 @@ LoongArchTargetLowering::LoongArchTargetLowering(const TargetMachine &TM, {ISD::SETNE, ISD::SETGE, ISD::SETGT, ISD::SETUGE, ISD::SETUGT}, VT, Expand); } + for (MVT VT : {MVT::v4i32, MVT::v2i64}) { + setOperationAction({ISD::SINT_TO_FP, ISD::UINT_TO_FP}, VT, Legal); + setOperationAction({ISD::FP_TO_SINT, ISD::FP_TO_UINT}, VT, Legal); + } for (MVT VT : {MVT::v4f32, MVT::v2f64}) { setOperationAction({ISD::FADD, ISD::FSUB}, VT, Legal); setOperationAction({ISD::FMUL, ISD::FDIV}, VT, Legal); @@ -307,6 +311,10 @@ LoongArchTargetLowering::LoongArchTargetLowering(const TargetMachine &TM, {ISD::SETNE, ISD::SETGE, ISD::SETGT, ISD::SETUGE, ISD::SETUGT}, VT, Expand); } + for (MVT VT : {MVT::v8i32, MVT::v4i32, MVT::v4i64}) { + setOperationAction({ISD::SINT_TO_FP, ISD::UINT_TO_FP}, VT, Legal); + setOperationAction({ISD::FP_TO_SINT, ISD::FP_TO_UINT}, VT, Legal); + } for (MVT VT : {MVT::v8f32, MVT::v4f64}) { setOperationAction({ISD::FADD, ISD::FSUB}, VT, Legal); setOperationAction({ISD::FMUL, ISD::FDIV}, VT, Legal); diff --git a/llvm/lib/Target/LoongArch/LoongArchInstrInfo.td b/llvm/lib/Target/LoongArch/LoongArchInstrInfo.td index 78074c01287..ae73a8ac74c 100644 --- a/llvm/lib/Target/LoongArch/LoongArchInstrInfo.td +++ b/llvm/lib/Target/LoongArch/LoongArchInstrInfo.td @@ -694,15 +694,24 @@ class AM_3R op> : Fmt3R; -let hasSideEffects = 0, mayLoad = 1, mayStore = 0 in +let hasSideEffects = 0, mayLoad = 1, mayStore = 0 in { class LLBase op> : Fmt2RI14; +class LLBase_ACQ op> + : Fmt2R; +} -let hasSideEffects = 0, mayLoad = 0, mayStore = 1, Constraints = "$rd = $dst" in +let hasSideEffects = 0, mayLoad = 0, mayStore = 1, Constraints = "$rd = $dst" in { class SCBase op> : Fmt2RI14; +class SCBase_128 op> + : Fmt3R; +class SCBase_REL op> + : Fmt2R; +} let hasSideEffects = 1 in class IOCSRRD op> @@ -814,6 +823,8 @@ def PRELD : FmtPRELD<(outs), (ins uimm5:$imm5, GPR:$rj, simm12:$imm12), // Atomic Memory Access Instructions def LL_W : LLBase<0x20000000>; def SC_W : SCBase<0x21000000>; +def LLACQ_W : LLBase_ACQ<0x38578000>; +def SCREL_W : SCBase_REL<0x38578400>; // Barrier Instructions def DBAR : MISC_I15<0x38720000>; @@ -935,8 +946,12 @@ def STLE_W : STORE_3R<0x387f0000>; def STLE_D : STORE_3R<0x387f8000>; // Atomic Memory Access Instructions for 64-bits +def AMSWAP_B : AM_3R<0x385c0000>; +def AMSWAP_H : AM_3R<0x385c8000>; def AMSWAP_W : AM_3R<0x38600000>; def AMSWAP_D : AM_3R<0x38608000>; +def AMADD_B : AM_3R<0x385d0000>; +def AMADD_H : AM_3R<0x385d8000>; def AMADD_W : AM_3R<0x38610000>; def AMADD_D : AM_3R<0x38618000>; def AMAND_W : AM_3R<0x38620000>; @@ -953,8 +968,12 @@ def AMMAX_WU : AM_3R<0x38670000>; def AMMAX_DU : AM_3R<0x38678000>; def AMMIN_WU : AM_3R<0x38680000>; def AMMIN_DU : AM_3R<0x38688000>; +def AMSWAP__DB_B : AM_3R<0x385e0000>; +def AMSWAP__DB_H : AM_3R<0x385e8000>; def AMSWAP__DB_W : AM_3R<0x38690000>; def AMSWAP__DB_D : AM_3R<0x38698000>; +def AMADD__DB_B : AM_3R<0x385f0000>; +def AMADD__DB_H : AM_3R<0x385f8000>; def AMADD__DB_W : AM_3R<0x386a0000>; def AMADD__DB_D : AM_3R<0x386a8000>; def AMAND__DB_W : AM_3R<0x386b0000>; @@ -971,8 +990,19 @@ def AMMAX__DB_WU : AM_3R<0x38700000>; def AMMAX__DB_DU : AM_3R<0x38708000>; def AMMIN__DB_WU : AM_3R<0x38710000>; def AMMIN__DB_DU : AM_3R<0x38718000>; +def AMCAS_B : AM_3R<0x38580000>; +def AMCAS_H : AM_3R<0x38588000>; +def AMCAS_W : AM_3R<0x38590000>; +def AMCAS_D : AM_3R<0x38598000>; +def AMCAS__DB_B : AM_3R<0x385a0000>; +def AMCAS__DB_H : AM_3R<0x385a8000>; +def AMCAS__DB_W : AM_3R<0x385b0000>; +def AMCAS__DB_D : AM_3R<0x385b8000>; def LL_D : LLBase<0x22000000>; def SC_D : SCBase<0x23000000>; +def SC_Q : SCBase_128<0x38570000>; +def LLACQ_D : LLBase_ACQ<0x38578800>; +def SCREL_D : SCBase_REL<0x38578C00>; // CRC Check Instructions def CRC_W_B_W : ALU_3R<0x00240000>; diff --git a/llvm/lib/Target/LoongArch/LoongArchLASXInstrInfo.td b/llvm/lib/Target/LoongArch/LoongArchLASXInstrInfo.td index b3c11bc5423..3de1fe2b722 100644 --- a/llvm/lib/Target/LoongArch/LoongArchLASXInstrInfo.td +++ b/llvm/lib/Target/LoongArch/LoongArchLASXInstrInfo.td @@ -771,6 +771,10 @@ def XVFRECIP_S : LASX2R_XX<0x769cf400>; def XVFRECIP_D : LASX2R_XX<0x769cf800>; def XVFRSQRT_S : LASX2R_XX<0x769d0400>; def XVFRSQRT_D : LASX2R_XX<0x769d0800>; +def XVFRECIPE_S : LASX2R_XX<0x769d1400>; +def XVFRECIPE_D : LASX2R_XX<0x769d1800>; +def XVFRSQRTE_S : LASX2R_XX<0x769d2400>; +def XVFRSQRTE_D : LASX2R_XX<0x769d2800>; def XVFCVTL_S_H : LASX2R_XX<0x769de800>; def XVFCVTH_S_H : LASX2R_XX<0x769dec00>; @@ -1611,6 +1615,50 @@ foreach vt = [v32i8, v16i16, v8i32, v4i64, v8f32, v4f64] in def : Pat<(fneg (v8f32 LASX256:$xj)), (XVBITREVI_W LASX256:$xj, 31)>; def : Pat<(fneg (v4f64 LASX256:$xj)), (XVBITREVI_D LASX256:$xj, 63)>; +// XVFFINT_{S_W/D_L} +def : Pat<(v8f32 (sint_to_fp v8i32:$vj)), (XVFFINT_S_W v8i32:$vj)>; +def : Pat<(v4f64 (sint_to_fp v4i64:$vj)), (XVFFINT_D_L v4i64:$vj)>; +def : Pat<(v4f64 (sint_to_fp v4i32:$vj)), + (XVFFINT_D_L (VEXT2XV_D_W (SUBREG_TO_REG (i64 0), v4i32:$vj, + sub_128)))>; +def : Pat<(v4f32 (sint_to_fp v4i64:$vj)), + (EXTRACT_SUBREG (XVFCVT_S_D (XVPERMI_D (XVFFINT_D_L v4i64:$vj), 238), + (XVFFINT_D_L v4i64:$vj)), + sub_128)>; + +// XVFFINT_{S_WU/D_LU} +def : Pat<(v8f32 (uint_to_fp v8i32:$vj)), (XVFFINT_S_WU v8i32:$vj)>; +def : Pat<(v4f64 (uint_to_fp v4i64:$vj)), (XVFFINT_D_LU v4i64:$vj)>; +def : Pat<(v4f64 (uint_to_fp v4i32:$vj)), + (XVFFINT_D_LU (VEXT2XV_DU_WU (SUBREG_TO_REG (i64 0), v4i32:$vj, + sub_128)))>; +def : Pat<(v4f32 (uint_to_fp v4i64:$vj)), + (EXTRACT_SUBREG (XVFCVT_S_D (XVPERMI_D (XVFFINT_D_LU v4i64:$vj), 238), + (XVFFINT_D_LU v4i64:$vj)), + sub_128)>; + +// XVFTINTRZ_{W_S/L_D} +def : Pat<(v8i32 (fp_to_sint v8f32:$vj)), (XVFTINTRZ_W_S v8f32:$vj)>; +def : Pat<(v4i64 (fp_to_sint v4f64:$vj)), (XVFTINTRZ_L_D v4f64:$vj)>; +def : Pat<(v4i64 (fp_to_sint v4f32:$vj)), + (VEXT2XV_D_W (SUBREG_TO_REG (i64 0), (VFTINTRZ_W_S v4f32:$vj), + sub_128))>; +def : Pat<(v4i32 (fp_to_sint (v4f64 LASX256:$vj))), + (EXTRACT_SUBREG (XVFTINTRZ_W_S (XVFCVT_S_D (XVPERMI_D v4f64:$vj, 238), + v4f64:$vj)), + sub_128)>; + +// XVFTINTRZ_{W_SU/L_DU} +def : Pat<(v8i32 (fp_to_uint v8f32:$vj)), (XVFTINTRZ_WU_S v8f32:$vj)>; +def : Pat<(v4i64 (fp_to_uint v4f64:$vj)), (XVFTINTRZ_LU_D v4f64:$vj)>; +def : Pat<(v4i64 (fp_to_uint v4f32:$vj)), + (VEXT2XV_DU_WU (SUBREG_TO_REG (i64 0), (VFTINTRZ_WU_S v4f32:$vj), + sub_128))>; +def : Pat<(v4i32 (fp_to_uint (v4f64 LASX256:$vj))), + (EXTRACT_SUBREG (XVFTINTRZ_W_S (XVFCVT_S_D (XVPERMI_D v4f64:$vj, 238), + v4f64:$vj)), + sub_128)>; + } // Predicates = [HasExtLASX] /// Intrinsic pattern @@ -1902,6 +1950,16 @@ foreach Inst = ["XVFLOGB_D", "XVFCLASS_D", "XVFSQRT_D", "XVFRECIP_D", "XVFRSQRT_ def : Pat<(deriveLASXIntrinsic.ret (v4f64 LASX256:$xj)), (!cast(Inst) LASX256:$xj)>; +// 256-Bit vector FP approximate reciprocal operation +let Predicates = [HasFrecipe] in { +foreach Inst = ["XVFRECIPE_S", "XVFRSQRTE_S"] in + def : Pat<(deriveLASXIntrinsic.ret (v8f32 LASX256:$xj)), + (!cast(Inst) LASX256:$xj)>; +foreach Inst = ["XVFRECIPE_D", "XVFRSQRTE_D"] in + def : Pat<(deriveLASXIntrinsic.ret (v4f64 LASX256:$xj)), + (!cast(Inst) LASX256:$xj)>; +} + def : Pat<(int_loongarch_lasx_xvpickve_w_f v8f32:$xj, timm:$imm), (XVPICKVE_W v8f32:$xj, (to_valid_timm timm:$imm))>; def : Pat<(int_loongarch_lasx_xvpickve_d_f v4f64:$xj, timm:$imm), diff --git a/llvm/lib/Target/LoongArch/LoongArchLSXInstrInfo.td b/llvm/lib/Target/LoongArch/LoongArchLSXInstrInfo.td index 5569c2cd15b..39ee861cd05 100644 --- a/llvm/lib/Target/LoongArch/LoongArchLSXInstrInfo.td +++ b/llvm/lib/Target/LoongArch/LoongArchLSXInstrInfo.td @@ -892,6 +892,10 @@ def VFRECIP_S : LSX2R_VV<0x729cf400>; def VFRECIP_D : LSX2R_VV<0x729cf800>; def VFRSQRT_S : LSX2R_VV<0x729d0400>; def VFRSQRT_D : LSX2R_VV<0x729d0800>; +def VFRECIPE_S : LSX2R_VV<0x729d1400>; +def VFRECIPE_D : LSX2R_VV<0x729d1800>; +def VFRSQRTE_S : LSX2R_VV<0x729d2400>; +def VFRSQRTE_D : LSX2R_VV<0x729d2800>; def VFCVTL_S_H : LSX2R_VV<0x729de800>; def VFCVTH_S_H : LSX2R_VV<0x729dec00>; @@ -1742,6 +1746,22 @@ foreach vt = [v16i8, v8i16, v4i32, v2i64, v4f32, v2f64] in def : Pat<(fneg (v4f32 LSX128:$vj)), (VBITREVI_W LSX128:$vj, 31)>; def : Pat<(fneg (v2f64 LSX128:$vj)), (VBITREVI_D LSX128:$vj, 63)>; +// VFFINT_{S_W/D_L} +def : Pat<(v4f32 (sint_to_fp v4i32:$vj)), (VFFINT_S_W v4i32:$vj)>; +def : Pat<(v2f64 (sint_to_fp v2i64:$vj)), (VFFINT_D_L v2i64:$vj)>; + +// VFFINT_{S_WU/D_LU} +def : Pat<(v4f32 (uint_to_fp v4i32:$vj)), (VFFINT_S_WU v4i32:$vj)>; +def : Pat<(v2f64 (uint_to_fp v2i64:$vj)), (VFFINT_D_LU v2i64:$vj)>; + +// VFTINTRZ_{W_S/L_D} +def : Pat<(v4i32 (fp_to_sint v4f32:$vj)), (VFTINTRZ_W_S v4f32:$vj)>; +def : Pat<(v2i64 (fp_to_sint v2f64:$vj)), (VFTINTRZ_L_D v2f64:$vj)>; + +// VFTINTRZ_{W_SU/L_DU} +def : Pat<(v4i32 (fp_to_uint v4f32:$vj)), (VFTINTRZ_WU_S v4f32:$vj)>; +def : Pat<(v2i64 (fp_to_uint v2f64:$vj)), (VFTINTRZ_LU_D v2f64:$vj)>; + } // Predicates = [HasExtLSX] /// Intrinsic pattern @@ -2027,6 +2047,16 @@ foreach Inst = ["VFLOGB_D", "VFCLASS_D", "VFSQRT_D", "VFRECIP_D", "VFRSQRT_D", def : Pat<(deriveLSXIntrinsic.ret (v2f64 LSX128:$vj)), (!cast(Inst) LSX128:$vj)>; +// 128-Bit vector FP approximate reciprocal operation +let Predicates = [HasFrecipe] in { +foreach Inst = ["VFRECIPE_S", "VFRSQRTE_S"] in + def : Pat<(deriveLSXIntrinsic.ret (v4f32 LSX128:$vj)), + (!cast(Inst) LSX128:$vj)>; +foreach Inst = ["VFRECIPE_D", "VFRSQRTE_D"] in + def : Pat<(deriveLSXIntrinsic.ret (v2f64 LSX128:$vj)), + (!cast(Inst) LSX128:$vj)>; +} + // load def : Pat<(int_loongarch_lsx_vld GPR:$rj, timm:$imm), (VLD GPR:$rj, (to_valid_timm timm:$imm))>; diff --git a/llvm/lib/Target/LoongArch/LoongArchSubtarget.h b/llvm/lib/Target/LoongArch/LoongArchSubtarget.h index 5c173675cca..11c0b39e176 100644 --- a/llvm/lib/Target/LoongArch/LoongArchSubtarget.h +++ b/llvm/lib/Target/LoongArch/LoongArchSubtarget.h @@ -44,6 +44,8 @@ class LoongArchSubtarget : public LoongArchGenSubtargetInfo { bool HasLaLocalWithAbs = false; bool HasUAL = false; bool HasLinkerRelax = false; + bool HasExpAutoVec = false; + bool HasFrecipe = false; unsigned GRLen = 32; MVT GRLenVT = MVT::i32; LoongArchABI::ABI TargetABI = LoongArchABI::ABI_Unknown; @@ -102,6 +104,8 @@ public: bool hasLaLocalWithAbs() const { return HasLaLocalWithAbs; } bool hasUAL() const { return HasUAL; } bool hasLinkerRelax() const { return HasLinkerRelax; } + bool hasExpAutoVec() const { return HasExpAutoVec; } + bool hasFrecipe() const { return HasFrecipe; } MVT getGRLenVT() const { return GRLenVT; } unsigned getGRLen() const { return GRLen; } LoongArchABI::ABI getTargetABI() const { return TargetABI; } diff --git a/llvm/lib/Target/LoongArch/LoongArchTargetTransformInfo.cpp b/llvm/lib/Target/LoongArch/LoongArchTargetTransformInfo.cpp index a6de86eea11..04349aa52b5 100644 --- a/llvm/lib/Target/LoongArch/LoongArchTargetTransformInfo.cpp +++ b/llvm/lib/Target/LoongArch/LoongArchTargetTransformInfo.cpp @@ -19,4 +19,22 @@ using namespace llvm; #define DEBUG_TYPE "loongarchtti" +TypeSize LoongArchTTIImpl::getRegisterBitWidth( + TargetTransformInfo::RegisterKind K) const { + switch (K) { + case TargetTransformInfo::RGK_Scalar: + return TypeSize::getFixed(ST->is64Bit() ? 64 : 32); + case TargetTransformInfo::RGK_FixedWidthVector: + if (ST->hasExtLASX() && ST->hasExpAutoVec()) + return TypeSize::getFixed(256); + if (ST->hasExtLSX() && ST->hasExpAutoVec()) + return TypeSize::getFixed(128); + return TypeSize::getFixed(0); + case TargetTransformInfo::RGK_ScalableVector: + return TypeSize::getScalable(0); + } + + llvm_unreachable("Unsupported register kind"); +} + // TODO: Implement more hooks to provide TTI machinery for LoongArch. diff --git a/llvm/lib/Target/LoongArch/LoongArchTargetTransformInfo.h b/llvm/lib/Target/LoongArch/LoongArchTargetTransformInfo.h index 9e02f793ba8..d296c9ed576 100644 --- a/llvm/lib/Target/LoongArch/LoongArchTargetTransformInfo.h +++ b/llvm/lib/Target/LoongArch/LoongArchTargetTransformInfo.h @@ -39,6 +39,8 @@ public: : BaseT(TM, F.getParent()->getDataLayout()), ST(TM->getSubtargetImpl(F)), TLI(ST->getTargetLowering()) {} + TypeSize getRegisterBitWidth(TargetTransformInfo::RegisterKind K) const; + // TODO: Implement more hooks to provide TTI machinery for LoongArch. }; diff --git a/llvm/lib/Target/LoongArch/MCTargetDesc/LoongArchAsmBackend.cpp b/llvm/lib/Target/LoongArch/MCTargetDesc/LoongArchAsmBackend.cpp index 518f6b10eda..de492f2b1f0 100644 --- a/llvm/lib/Target/LoongArch/MCTargetDesc/LoongArchAsmBackend.cpp +++ b/llvm/lib/Target/LoongArch/MCTargetDesc/LoongArchAsmBackend.cpp @@ -12,12 +12,17 @@ #include "LoongArchAsmBackend.h" #include "LoongArchFixupKinds.h" +#include "llvm/MC/MCAsmInfo.h" #include "llvm/MC/MCAsmLayout.h" #include "llvm/MC/MCAssembler.h" #include "llvm/MC/MCContext.h" #include "llvm/MC/MCELFObjectWriter.h" +#include "llvm/MC/MCExpr.h" +#include "llvm/MC/MCSection.h" #include "llvm/MC/MCValue.h" #include "llvm/Support/EndianStream.h" +#include "llvm/Support/LEB128.h" +#include "llvm/Support/MathExtras.h" #define DEBUG_TYPE "loongarch-asmbackend" @@ -174,6 +179,70 @@ void LoongArchAsmBackend::applyFixup(const MCAssembler &Asm, } } +// Linker relaxation may change code size. We have to insert Nops +// for .align directive when linker relaxation enabled. So then Linker +// could satisfy alignment by removing Nops. +// The function returns the total Nops Size we need to insert. +bool LoongArchAsmBackend::shouldInsertExtraNopBytesForCodeAlign( + const MCAlignFragment &AF, unsigned &Size) { + // Calculate Nops Size only when linker relaxation enabled. + if (!AF.getSubtargetInfo()->hasFeature(LoongArch::FeatureRelax)) + return false; + + // Ignore alignment if MaxBytesToEmit is less than the minimum Nop size. + const unsigned MinNopLen = 4; + if (AF.getMaxBytesToEmit() < MinNopLen) + return false; + Size = AF.getAlignment().value() - MinNopLen; + return AF.getAlignment() > MinNopLen; +} + +// We need to insert R_LARCH_ALIGN relocation type to indicate the +// position of Nops and the total bytes of the Nops have been inserted +// when linker relaxation enabled. +// The function inserts fixup_loongarch_align fixup which eventually will +// transfer to R_LARCH_ALIGN relocation type. +// The improved R_LARCH_ALIGN requires symbol index. The lowest 8 bits of +// addend represent alignment and the other bits of addend represent the +// maximum number of bytes to emit. The maximum number of bytes is zero +// means ignore the emit limit. +bool LoongArchAsmBackend::shouldInsertFixupForCodeAlign( + MCAssembler &Asm, const MCAsmLayout &Layout, MCAlignFragment &AF) { + // Insert the fixup only when linker relaxation enabled. + if (!AF.getSubtargetInfo()->hasFeature(LoongArch::FeatureRelax)) + return false; + + // Calculate total Nops we need to insert. If there are none to insert + // then simply return. + unsigned Count; + if (!shouldInsertExtraNopBytesForCodeAlign(AF, Count)) + return false; + + MCSection *Sec = AF.getParent(); + MCContext &Ctx = Asm.getContext(); + const MCExpr *Dummy = MCConstantExpr::create(0, Ctx); + // Create fixup_loongarch_align fixup. + MCFixup Fixup = + MCFixup::create(0, Dummy, MCFixupKind(LoongArch::fixup_loongarch_align)); + const MCSymbolRefExpr *MCSym = getSecToAlignSym()[Sec]; + if (MCSym == nullptr) { + // Create a symbol and make the value of symbol is zero. + MCSymbol *Sym = Ctx.createNamedTempSymbol("la-relax-align"); + Sym->setFragment(&*Sec->getBeginSymbol()->getFragment()); + Asm.registerSymbol(*Sym); + MCSym = MCSymbolRefExpr::create(Sym, Ctx); + getSecToAlignSym()[Sec] = MCSym; + } + + uint64_t FixedValue = 0; + unsigned Lo = Log2_64(Count) + 1; + unsigned Hi = AF.getMaxBytesToEmit() >= Count ? 0 : AF.getMaxBytesToEmit(); + MCValue Value = MCValue::get(MCSym, nullptr, Hi << 8 | Lo); + Asm.getWriter().recordRelocation(Asm, Layout, &AF, Fixup, Value, FixedValue); + + return true; +} + bool LoongArchAsmBackend::shouldForceRelocation(const MCAssembler &Asm, const MCFixup &Fixup, const MCValue &Target, @@ -235,6 +304,133 @@ std::pair LoongArchAsmBackend::relaxLEB128(MCLEBFragment &LF, return std::make_pair(true, true); } +bool LoongArchAsmBackend::relaxDwarfLineAddr(MCDwarfLineAddrFragment &DF, + MCAsmLayout &Layout, + bool &WasRelaxed) const { + MCContext &C = Layout.getAssembler().getContext(); + + int64_t LineDelta = DF.getLineDelta(); + const MCExpr &AddrDelta = DF.getAddrDelta(); + SmallVectorImpl &Data = DF.getContents(); + SmallVectorImpl &Fixups = DF.getFixups(); + size_t OldSize = Data.size(); + + int64_t Value; + if (AddrDelta.evaluateAsAbsolute(Value, Layout)) + return false; + bool IsAbsolute = AddrDelta.evaluateKnownAbsolute(Value, Layout); + assert(IsAbsolute && "CFA with invalid expression"); + (void)IsAbsolute; + + Data.clear(); + Fixups.clear(); + raw_svector_ostream OS(Data); + + // INT64_MAX is a signal that this is actually a DW_LNE_end_sequence. + if (LineDelta != INT64_MAX) { + OS << uint8_t(dwarf::DW_LNS_advance_line); + encodeSLEB128(LineDelta, OS); + } + + unsigned Offset; + std::pair FK; + + // According to the DWARF specification, the `DW_LNS_fixed_advance_pc` opcode + // takes a single unsigned half (unencoded) operand. The maximum encodable + // value is therefore 65535. Set a conservative upper bound for relaxation. + if (Value > 60000) { + unsigned PtrSize = C.getAsmInfo()->getCodePointerSize(); + + OS << uint8_t(dwarf::DW_LNS_extended_op); + encodeULEB128(PtrSize + 1, OS); + + OS << uint8_t(dwarf::DW_LNE_set_address); + Offset = OS.tell(); + assert((PtrSize == 4 || PtrSize == 8) && "Unexpected pointer size"); + FK = getRelocPairForSize(PtrSize == 4 ? 32 : 64); + OS.write_zeros(PtrSize); + } else { + OS << uint8_t(dwarf::DW_LNS_fixed_advance_pc); + Offset = OS.tell(); + FK = getRelocPairForSize(16); + support::endian::write(OS, 0, llvm::endianness::little); + } + + const MCBinaryExpr &MBE = cast(AddrDelta); + Fixups.push_back(MCFixup::create(Offset, MBE.getLHS(), std::get<0>(FK))); + Fixups.push_back(MCFixup::create(Offset, MBE.getRHS(), std::get<1>(FK))); + + if (LineDelta == INT64_MAX) { + OS << uint8_t(dwarf::DW_LNS_extended_op); + OS << uint8_t(1); + OS << uint8_t(dwarf::DW_LNE_end_sequence); + } else { + OS << uint8_t(dwarf::DW_LNS_copy); + } + + WasRelaxed = OldSize != Data.size(); + return true; +} + +bool LoongArchAsmBackend::relaxDwarfCFA(MCDwarfCallFrameFragment &DF, + MCAsmLayout &Layout, + bool &WasRelaxed) const { + const MCExpr &AddrDelta = DF.getAddrDelta(); + SmallVectorImpl &Data = DF.getContents(); + SmallVectorImpl &Fixups = DF.getFixups(); + size_t OldSize = Data.size(); + + int64_t Value; + if (AddrDelta.evaluateAsAbsolute(Value, Layout)) + return false; + bool IsAbsolute = AddrDelta.evaluateKnownAbsolute(Value, Layout); + assert(IsAbsolute && "CFA with invalid expression"); + (void)IsAbsolute; + + Data.clear(); + Fixups.clear(); + raw_svector_ostream OS(Data); + + assert( + Layout.getAssembler().getContext().getAsmInfo()->getMinInstAlignment() == + 1 && + "expected 1-byte alignment"); + if (Value == 0) { + WasRelaxed = OldSize != Data.size(); + return true; + } + + auto AddFixups = [&Fixups, + &AddrDelta](unsigned Offset, + std::pair FK) { + const MCBinaryExpr &MBE = cast(AddrDelta); + Fixups.push_back(MCFixup::create(Offset, MBE.getLHS(), std::get<0>(FK))); + Fixups.push_back(MCFixup::create(Offset, MBE.getRHS(), std::get<1>(FK))); + }; + + if (isUIntN(6, Value)) { + OS << uint8_t(dwarf::DW_CFA_advance_loc); + AddFixups(0, getRelocPairForSize(6)); + } else if (isUInt<8>(Value)) { + OS << uint8_t(dwarf::DW_CFA_advance_loc1); + support::endian::write(OS, 0, llvm::endianness::little); + AddFixups(1, getRelocPairForSize(8)); + } else if (isUInt<16>(Value)) { + OS << uint8_t(dwarf::DW_CFA_advance_loc2); + support::endian::write(OS, 0, llvm::endianness::little); + AddFixups(1, getRelocPairForSize(16)); + } else if (isUInt<32>(Value)) { + OS << uint8_t(dwarf::DW_CFA_advance_loc4); + support::endian::write(OS, 0, llvm::endianness::little); + AddFixups(1, getRelocPairForSize(32)); + } else { + llvm_unreachable("unsupported CFA encoding"); + } + + WasRelaxed = OldSize != Data.size(); + return true; +} + bool LoongArchAsmBackend::writeNopData(raw_ostream &OS, uint64_t Count, const MCSubtargetInfo *STI) const { // We mostly follow binutils' convention here: align to 4-byte boundary with a diff --git a/llvm/lib/Target/LoongArch/MCTargetDesc/LoongArchAsmBackend.h b/llvm/lib/Target/LoongArch/MCTargetDesc/LoongArchAsmBackend.h index 71977217f59..9d81781fca1 100644 --- a/llvm/lib/Target/LoongArch/MCTargetDesc/LoongArchAsmBackend.h +++ b/llvm/lib/Target/LoongArch/MCTargetDesc/LoongArchAsmBackend.h @@ -17,7 +17,9 @@ #include "MCTargetDesc/LoongArchFixupKinds.h" #include "MCTargetDesc/LoongArchMCTargetDesc.h" #include "llvm/MC/MCAsmBackend.h" +#include "llvm/MC/MCExpr.h" #include "llvm/MC/MCFixupKindInfo.h" +#include "llvm/MC/MCSection.h" #include "llvm/MC/MCSubtargetInfo.h" namespace llvm { @@ -27,6 +29,7 @@ class LoongArchAsmBackend : public MCAsmBackend { uint8_t OSABI; bool Is64Bit; const MCTargetOptions &TargetOptions; + DenseMap SecToAlignSym; public: LoongArchAsmBackend(const MCSubtargetInfo &STI, uint8_t OSABI, bool Is64Bit, @@ -45,6 +48,15 @@ public: uint64_t Value, bool IsResolved, const MCSubtargetInfo *STI) const override; + // Return Size with extra Nop Bytes for alignment directive in code section. + bool shouldInsertExtraNopBytesForCodeAlign(const MCAlignFragment &AF, + unsigned &Size) override; + + // Insert target specific fixup type for alignment directive in code section. + bool shouldInsertFixupForCodeAlign(MCAssembler &Asm, + const MCAsmLayout &Layout, + MCAlignFragment &AF) override; + bool shouldForceRelocation(const MCAssembler &Asm, const MCFixup &Fixup, const MCValue &Target, const MCSubtargetInfo *STI) override; @@ -69,12 +81,20 @@ public: std::pair relaxLEB128(MCLEBFragment &LF, MCAsmLayout &Layout, int64_t &Value) const override; + bool relaxDwarfLineAddr(MCDwarfLineAddrFragment &DF, MCAsmLayout &Layout, + bool &WasRelaxed) const override; + bool relaxDwarfCFA(MCDwarfCallFrameFragment &DF, MCAsmLayout &Layout, + bool &WasRelaxed) const override; + bool writeNopData(raw_ostream &OS, uint64_t Count, const MCSubtargetInfo *STI) const override; std::unique_ptr createObjectTargetWriter() const override; const MCTargetOptions &getTargetOptions() const { return TargetOptions; } + DenseMap &getSecToAlignSym() { + return SecToAlignSym; + } }; } // end namespace llvm diff --git a/llvm/lib/Target/LoongArch/MCTargetDesc/LoongArchFixupKinds.h b/llvm/lib/Target/LoongArch/MCTargetDesc/LoongArchFixupKinds.h index e827bae1f3e..0d19d2b0fb1 100644 --- a/llvm/lib/Target/LoongArch/MCTargetDesc/LoongArchFixupKinds.h +++ b/llvm/lib/Target/LoongArch/MCTargetDesc/LoongArchFixupKinds.h @@ -109,6 +109,8 @@ enum Fixups { fixup_loongarch_tls_gd_hi20, // Generate an R_LARCH_RELAX which indicates the linker may relax here. fixup_loongarch_relax = FirstLiteralRelocationKind + ELF::R_LARCH_RELAX, + // Generate an R_LARCH_ALIGN which indicates the linker may fixup align here. + fixup_loongarch_align = FirstLiteralRelocationKind + ELF::R_LARCH_ALIGN, // 36-bit fixup corresponding to %call36(foo) for a pair instructions: // pcaddu18i+jirl. fixup_loongarch_call36 = FirstLiteralRelocationKind + ELF::R_LARCH_CALL36, diff --git a/llvm/lib/Target/Mips/MipsAsmPrinter.cpp b/llvm/lib/Target/Mips/MipsAsmPrinter.cpp index 30ff82dd911..718844bc36f 100644 --- a/llvm/lib/Target/Mips/MipsAsmPrinter.cpp +++ b/llvm/lib/Target/Mips/MipsAsmPrinter.cpp @@ -491,10 +491,7 @@ bool MipsAsmPrinter::isBlockOnlyReachableByFallthrough(const MachineBasicBlock* return false; // If there isn't exactly one predecessor, it can't be a fall through. - MachineBasicBlock::const_pred_iterator PI = MBB->pred_begin(), PI2 = PI; - ++PI2; - - if (PI2 != MBB->pred_end()) + if (MBB->pred_size() != 1) return false; // The predecessor has to be immediately before this block. diff --git a/llvm/lib/Target/Mips/MipsCallLowering.cpp b/llvm/lib/Target/Mips/MipsCallLowering.cpp index 1cd360fe30f..b8562902112 100644 --- a/llvm/lib/Target/Mips/MipsCallLowering.cpp +++ b/llvm/lib/Target/Mips/MipsCallLowering.cpp @@ -185,7 +185,7 @@ MipsIncomingValueHandler::assignCustomValue(CallLowering::ArgInfo &Arg, markPhysRegUsed(VALo.getLocReg()); markPhysRegUsed(VAHi.getLocReg()); - return 1; + return 2; } namespace { diff --git a/llvm/lib/Target/Mips/MipsRegisterBankInfo.cpp b/llvm/lib/Target/Mips/MipsRegisterBankInfo.cpp index b38ca3f09ff..db7afc3c86c 100644 --- a/llvm/lib/Target/Mips/MipsRegisterBankInfo.cpp +++ b/llvm/lib/Target/Mips/MipsRegisterBankInfo.cpp @@ -238,11 +238,11 @@ MipsRegisterBankInfo::AmbiguousRegDefUseContainer::AmbiguousRegDefUseContainer( if (MI->getOpcode() == TargetOpcode::G_STORE) addUseDef(MI->getOperand(0).getReg(), MRI); - if (MI->getOpcode() == TargetOpcode::G_PHI) { - addDefUses(MI->getOperand(0).getReg(), MRI); + if (auto *PHI = dyn_cast(MI)) { + addDefUses(PHI->getReg(0), MRI); - for (unsigned i = 1; i < MI->getNumOperands(); i += 2) - addUseDef(MI->getOperand(i).getReg(), MRI); + for (unsigned I = 1; I < PHI->getNumIncomingValues(); ++I) + addUseDef(PHI->getIncomingValue(I), MRI); } if (MI->getOpcode() == TargetOpcode::G_SELECT) { diff --git a/llvm/lib/Target/NVPTX/NVPTXISelDAGToDAG.cpp b/llvm/lib/Target/NVPTX/NVPTXISelDAGToDAG.cpp index 7abe984b34e..ded2f258401 100644 --- a/llvm/lib/Target/NVPTX/NVPTXISelDAGToDAG.cpp +++ b/llvm/lib/Target/NVPTX/NVPTXISelDAGToDAG.cpp @@ -309,6 +309,12 @@ void NVPTXDAGToDAGISel::Select(SDNode *N) { case NVPTXISD::TexUnifiedCubeArrayS32FloatLevel: case NVPTXISD::TexUnifiedCubeArrayU32Float: case NVPTXISD::TexUnifiedCubeArrayU32FloatLevel: + case NVPTXISD::TexUnifiedCubeFloatFloatGrad: + case NVPTXISD::TexUnifiedCubeS32FloatGrad: + case NVPTXISD::TexUnifiedCubeU32FloatGrad: + case NVPTXISD::TexUnifiedCubeArrayFloatFloatGrad: + case NVPTXISD::TexUnifiedCubeArrayS32FloatGrad: + case NVPTXISD::TexUnifiedCubeArrayU32FloatGrad: case NVPTXISD::Tld4UnifiedR2DFloatFloat: case NVPTXISD::Tld4UnifiedG2DFloatFloat: case NVPTXISD::Tld4UnifiedB2DFloatFloat: @@ -2763,6 +2769,24 @@ bool NVPTXDAGToDAGISel::tryTextureIntrinsic(SDNode *N) { case NVPTXISD::Tld4UnifiedA2DU64Float: Opc = NVPTX::TLD4_UNIFIED_A_2D_U32_F32_R; break; + case NVPTXISD::TexUnifiedCubeFloatFloatGrad: + Opc = NVPTX::TEX_UNIFIED_CUBE_F32_F32_GRAD_R; + break; + case NVPTXISD::TexUnifiedCubeS32FloatGrad: + Opc = NVPTX::TEX_UNIFIED_CUBE_S32_F32_GRAD_R; + break; + case NVPTXISD::TexUnifiedCubeU32FloatGrad: + Opc = NVPTX::TEX_UNIFIED_CUBE_U32_F32_GRAD_R; + break; + case NVPTXISD::TexUnifiedCubeArrayFloatFloatGrad: + Opc = NVPTX::TEX_UNIFIED_CUBE_ARRAY_F32_F32_GRAD_R; + break; + case NVPTXISD::TexUnifiedCubeArrayS32FloatGrad: + Opc = NVPTX::TEX_UNIFIED_CUBE_ARRAY_S32_F32_GRAD_R; + break; + case NVPTXISD::TexUnifiedCubeArrayU32FloatGrad: + Opc = NVPTX::TEX_UNIFIED_CUBE_ARRAY_U32_F32_GRAD_R; + break; } // Copy over operands diff --git a/llvm/lib/Target/NVPTX/NVPTXISelLowering.cpp b/llvm/lib/Target/NVPTX/NVPTXISelLowering.cpp index 34c5569b807..8080e8404e4 100644 --- a/llvm/lib/Target/NVPTX/NVPTXISelLowering.cpp +++ b/llvm/lib/Target/NVPTX/NVPTXISelLowering.cpp @@ -1257,6 +1257,18 @@ const char *NVPTXTargetLowering::getTargetNodeName(unsigned Opcode) const { return "NVPTXISD::TexUnifiedCubeArrayU32Float"; case NVPTXISD::TexUnifiedCubeArrayU32FloatLevel: return "NVPTXISD::TexUnifiedCubeArrayU32FloatLevel"; + case NVPTXISD::TexUnifiedCubeFloatFloatGrad: + return "NVPTXISD::TexUnifiedCubeFloatFloatGrad"; + case NVPTXISD::TexUnifiedCubeS32FloatGrad: + return "NVPTXISD::TexUnifiedCubeS32FloatGrad"; + case NVPTXISD::TexUnifiedCubeU32FloatGrad: + return "NVPTXISD::TexUnifiedCubeU32FloatGrad"; + case NVPTXISD::TexUnifiedCubeArrayFloatFloatGrad: + return "NVPTXISD::TexUnifiedCubeArrayFloatFloatGrad"; + case NVPTXISD::TexUnifiedCubeArrayS32FloatGrad: + return "NVPTXISD::TexUnifiedCubeArrayS32FloatGrad"; + case NVPTXISD::TexUnifiedCubeArrayU32FloatGrad: + return "NVPTXISD::TexUnifiedCubeArrayU32FloatGrad"; case NVPTXISD::Tld4UnifiedR2DFloatFloat: return "NVPTXISD::Tld4UnifiedR2DFloatFloat"; case NVPTXISD::Tld4UnifiedG2DFloatFloat: @@ -1654,8 +1666,7 @@ std::string NVPTXTargetLowering::getPrototype( return Prototype; } -Align NVPTXTargetLowering::getArgumentAlignment(SDValue Callee, - const CallBase *CB, Type *Ty, +Align NVPTXTargetLowering::getArgumentAlignment(const CallBase *CB, Type *Ty, unsigned Idx, const DataLayout &DL) const { if (!CB) { @@ -1782,7 +1793,7 @@ SDValue NVPTXTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI, if (IsVAArg) VAOffset = alignTo(VAOffset, ArgAlign); } else { - ArgAlign = getArgumentAlignment(Callee, CB, Ty, ParamCount + 1, DL); + ArgAlign = getArgumentAlignment(CB, Ty, ParamCount + 1, DL); } unsigned TypeSize = @@ -1964,7 +1975,7 @@ SDValue NVPTXTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI, DeclareRetOps); InGlue = Chain.getValue(1); } else { - retAlignment = getArgumentAlignment(Callee, CB, RetTy, 0, DL); + retAlignment = getArgumentAlignment(CB, RetTy, 0, DL); assert(retAlignment && "retAlignment is guaranteed to be set"); SDVTList DeclareRetVTs = DAG.getVTList(MVT::Other, MVT::Glue); SDValue DeclareRetOps[] = { @@ -2095,7 +2106,7 @@ SDValue NVPTXTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI, ComputePTXValueVTs(*this, DL, RetTy, VTs, &Offsets, 0); assert(VTs.size() == Ins.size() && "Bad value decomposition"); - Align RetAlign = getArgumentAlignment(Callee, CB, RetTy, 0, DL); + Align RetAlign = getArgumentAlignment(CB, RetTy, 0, DL); auto VectorInfo = VectorizePTXValueVTs(VTs, Offsets, RetAlign); SmallVector LoadVTs; @@ -2387,8 +2398,10 @@ SDValue NVPTXTargetLowering::LowerVECTOR_SHUFFLE(SDValue Op, const ShuffleVectorSDNode *SVN = cast(Op.getNode()); SDValue V2 = Op.getOperand(1); uint32_t Selector = 0; - for (auto I : llvm::enumerate(SVN->getMask())) - Selector |= (I.value() << (I.index() * 4)); + for (auto I : llvm::enumerate(SVN->getMask())) { + if (I.value() != -1) // -1 is a placeholder for undef. + Selector |= (I.value() << (I.index() * 4)); + } SDLoc DL(Op); return DAG.getNode(NVPTXISD::PRMT, DL, MVT::v4i8, V1, V2, @@ -3652,6 +3665,19 @@ static unsigned getOpcForTextureInstr(unsigned Intrinsic) { case Intrinsic::nvvm_tex_unified_cube_array_level_v4u32_f32: return NVPTXISD::TexUnifiedCubeArrayU32FloatLevel; + case Intrinsic::nvvm_tex_unified_cube_grad_v4f32_f32: + return NVPTXISD::TexUnifiedCubeFloatFloatGrad; + case Intrinsic::nvvm_tex_unified_cube_grad_v4s32_f32: + return NVPTXISD::TexUnifiedCubeS32FloatGrad; + case Intrinsic::nvvm_tex_unified_cube_grad_v4u32_f32: + return NVPTXISD::TexUnifiedCubeU32FloatGrad; + case Intrinsic::nvvm_tex_unified_cube_array_grad_v4f32_f32: + return NVPTXISD::TexUnifiedCubeArrayFloatFloatGrad; + case Intrinsic::nvvm_tex_unified_cube_array_grad_v4s32_f32: + return NVPTXISD::TexUnifiedCubeArrayS32FloatGrad; + case Intrinsic::nvvm_tex_unified_cube_array_grad_v4u32_f32: + return NVPTXISD::TexUnifiedCubeArrayU32FloatGrad; + case Intrinsic::nvvm_tld4_unified_r_2d_v4f32_f32: return NVPTXISD::Tld4UnifiedR2DFloatFloat; case Intrinsic::nvvm_tld4_unified_g_2d_v4f32_f32: @@ -4536,6 +4562,8 @@ bool NVPTXTargetLowering::getTgtMemIntrinsic( case Intrinsic::nvvm_tex_unified_cube_level_v4f32_f32: case Intrinsic::nvvm_tex_unified_cube_array_v4f32_f32: case Intrinsic::nvvm_tex_unified_cube_array_level_v4f32_f32: + case Intrinsic::nvvm_tex_unified_cube_grad_v4f32_f32: + case Intrinsic::nvvm_tex_unified_cube_array_grad_v4f32_f32: case Intrinsic::nvvm_tld4_unified_r_2d_v4f32_f32: case Intrinsic::nvvm_tld4_unified_g_2d_v4f32_f32: case Intrinsic::nvvm_tld4_unified_b_2d_v4f32_f32: @@ -4652,6 +4680,10 @@ bool NVPTXTargetLowering::getTgtMemIntrinsic( case Intrinsic::nvvm_tex_unified_cube_level_v4u32_f32: case Intrinsic::nvvm_tex_unified_cube_array_v4u32_f32: case Intrinsic::nvvm_tex_unified_cube_array_level_v4u32_f32: + case Intrinsic::nvvm_tex_unified_cube_grad_v4s32_f32: + case Intrinsic::nvvm_tex_unified_cube_grad_v4u32_f32: + case Intrinsic::nvvm_tex_unified_cube_array_grad_v4s32_f32: + case Intrinsic::nvvm_tex_unified_cube_array_grad_v4u32_f32: case Intrinsic::nvvm_tld4_unified_r_2d_v4s32_f32: case Intrinsic::nvvm_tld4_unified_g_2d_v4s32_f32: case Intrinsic::nvvm_tld4_unified_b_2d_v4s32_f32: @@ -5262,9 +5294,7 @@ static SDValue PerformANDCombine(SDNode *N, return SDValue(); } - unsigned ExtType = - cast(Val->getOperand(Val->getNumOperands()-1))-> - getZExtValue(); + unsigned ExtType = Val->getConstantOperandVal(Val->getNumOperands() - 1); if (ExtType == ISD::SEXTLOAD) { // If for some reason the load is a sextload, the and is needed to zero // out the high 8 bits diff --git a/llvm/lib/Target/NVPTX/NVPTXISelLowering.h b/llvm/lib/Target/NVPTX/NVPTXISelLowering.h index 06adc0c47f0..5d3fd992812 100644 --- a/llvm/lib/Target/NVPTX/NVPTXISelLowering.h +++ b/llvm/lib/Target/NVPTX/NVPTXISelLowering.h @@ -240,6 +240,12 @@ enum NodeType : unsigned { TexUnifiedCubeArrayS32FloatLevel, TexUnifiedCubeArrayU32Float, TexUnifiedCubeArrayU32FloatLevel, + TexUnifiedCubeFloatFloatGrad, + TexUnifiedCubeS32FloatGrad, + TexUnifiedCubeU32FloatGrad, + TexUnifiedCubeArrayFloatFloatGrad, + TexUnifiedCubeArrayS32FloatGrad, + TexUnifiedCubeArrayU32FloatGrad, Tld4UnifiedR2DFloatFloat, Tld4UnifiedG2DFloatFloat, Tld4UnifiedB2DFloatFloat, @@ -631,8 +637,8 @@ private: SelectionDAG &DAG) const override; SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override; - Align getArgumentAlignment(SDValue Callee, const CallBase *CB, Type *Ty, - unsigned Idx, const DataLayout &DL) const; + Align getArgumentAlignment(const CallBase *CB, Type *Ty, unsigned Idx, + const DataLayout &DL) const; }; } // namespace llvm diff --git a/llvm/lib/Target/NVPTX/NVPTXIntrinsics.td b/llvm/lib/Target/NVPTX/NVPTXIntrinsics.td index 6b062a7f391..33f1e4a43e0 100644 --- a/llvm/lib/Target/NVPTX/NVPTXIntrinsics.td +++ b/llvm/lib/Target/NVPTX/NVPTXIntrinsics.td @@ -132,6 +132,7 @@ def INT_BARRIER_SYNC_CNT_II : NVPTXInst<(outs), (ins i32imm:$id, i32imm:$cnt), "barrier.sync \t$id, $cnt;", [(int_nvvm_barrier_sync_cnt imm:$id, imm:$cnt)]>, Requires<[hasPTX<60>, hasSM<30>]>; + class INT_BARRIER_CLUSTER Preds = [hasPTX<78>, hasSM<90>]>: NVPTXInst<(outs), (ins), "barrier.cluster."# variant #";", [(Intr)]>, @@ -145,6 +146,15 @@ def barrier_cluster_arrive_relaxed: def barrier_cluster_wait: INT_BARRIER_CLUSTER<"wait", int_nvvm_barrier_cluster_wait>; +// 'aligned' versions of the cluster barrier intrinsics +def barrier_cluster_arrive_aligned: + INT_BARRIER_CLUSTER<"arrive.aligned", int_nvvm_barrier_cluster_arrive_aligned>; +def barrier_cluster_arrive_relaxed_aligned: + INT_BARRIER_CLUSTER<"arrive.relaxed.aligned", + int_nvvm_barrier_cluster_arrive_relaxed_aligned, [hasPTX<80>, hasSM<90>]>; +def barrier_cluster_wait_aligned: + INT_BARRIER_CLUSTER<"wait.aligned", int_nvvm_barrier_cluster_wait_aligned>; + class SHFL_INSTR : NVPTXInst<(outs), (ins), "?", []> { @@ -401,6 +411,22 @@ def CP_ASYNC_WAIT_ALL : [(int_nvvm_cp_async_wait_all)]>, Requires<[hasPTX<70>, hasSM<80>]>; +// cp.async.bulk variants of the commit/wait group +def CP_ASYNC_BULK_COMMIT_GROUP : + NVPTXInst<(outs), (ins), "cp.async.bulk.commit_group;", + [(int_nvvm_cp_async_bulk_commit_group)]>, + Requires<[hasPTX<80>, hasSM<90>]>; + +def CP_ASYNC_BULK_WAIT_GROUP : + NVPTXInst<(outs), (ins i32imm:$n), "cp.async.bulk.wait_group $n;", + [(int_nvvm_cp_async_bulk_wait_group (i32 timm:$n))]>, + Requires<[hasPTX<80>, hasSM<90>]>; + +def CP_ASYNC_BULK_WAIT_GROUP_READ : + NVPTXInst<(outs), (ins i32imm:$n), "cp.async.bulk.wait_group.read $n;", + [(int_nvvm_cp_async_bulk_wait_group_read (i32 timm:$n))]>, + Requires<[hasPTX<80>, hasSM<90>]>; + //----------------------------------- // MBarrier Functions //----------------------------------- @@ -760,11 +786,14 @@ defm INT_NVVM_FMAN : MIN_MAX<"max">; // Multiplication // +def INT_NVVM_MULHI_S : F_MATH_2<"mul.hi.s16 \t$dst, $src0, $src1;", Int16Regs, + Int16Regs, Int16Regs, int_nvvm_mulhi_s>; +def INT_NVVM_MULHI_US : F_MATH_2<"mul.hi.u16 \t$dst, $src0, $src1;", Int16Regs, + Int16Regs, Int16Regs, int_nvvm_mulhi_us>; def INT_NVVM_MULHI_I : F_MATH_2<"mul.hi.s32 \t$dst, $src0, $src1;", Int32Regs, Int32Regs, Int32Regs, int_nvvm_mulhi_i>; def INT_NVVM_MULHI_UI : F_MATH_2<"mul.hi.u32 \t$dst, $src0, $src1;", Int32Regs, Int32Regs, Int32Regs, int_nvvm_mulhi_ui>; - def INT_NVVM_MULHI_LL : F_MATH_2<"mul.hi.s64 \t$dst, $src0, $src1;", Int64Regs, Int64Regs, Int64Regs, int_nvvm_mulhi_ll>; def INT_NVVM_MULHI_ULL : F_MATH_2<"mul.hi.u64 \t$dst, $src0, $src1;", Int64Regs, @@ -841,10 +870,18 @@ def INT_NVVM_DIV_RP_D : F_MATH_2<"div.rp.f64 \t$dst, $src0, $src1;", // Sad // +def INT_NVVM_SAD_S : F_MATH_3<"sad.s16 \t$dst, $src0, $src1, $src2;", + Int16Regs, Int16Regs, Int16Regs, Int16Regs, int_nvvm_sad_s>; +def INT_NVVM_SAD_US : F_MATH_3<"sad.u16 \t$dst, $src0, $src1, $src2;", + Int16Regs, Int16Regs, Int16Regs, Int16Regs, int_nvvm_sad_us>; def INT_NVVM_SAD_I : F_MATH_3<"sad.s32 \t$dst, $src0, $src1, $src2;", Int32Regs, Int32Regs, Int32Regs, Int32Regs, int_nvvm_sad_i>; def INT_NVVM_SAD_UI : F_MATH_3<"sad.u32 \t$dst, $src0, $src1, $src2;", Int32Regs, Int32Regs, Int32Regs, Int32Regs, int_nvvm_sad_ui>; +def INT_NVVM_SAD_LL : F_MATH_3<"sad.s64 \t$dst, $src0, $src1, $src2;", + Int64Regs, Int64Regs, Int64Regs, Int64Regs, int_nvvm_sad_ll>; +def INT_NVVM_SAD_ULL : F_MATH_3<"sad.u64 \t$dst, $src0, $src1, $src2;", + Int64Regs, Int64Regs, Int64Regs, Int64Regs, int_nvvm_sad_ull>; // // Floor Ceil @@ -3754,6 +3791,62 @@ defm TEX_UNIFIED_CUBE_ARRAY_U32_F32_LEVEL : TEX_UNIFIED_CUBE_ARRAY_LEVEL<"tex.level.acube.v4.u32.f32", Int32Regs, Float32Regs>; +class TEX_UNIFIED_CUBE_GRAD_base + : NVPTXInst<(outs outtype:$r, outtype:$g, + outtype:$b, outtype:$a), + !con(tex, (ins intype:$x, intype:$y, intype:$z, + intype:$gradx0, intype:$gradx1, + intype:$gradx2, intype:$grady0, + intype:$grady1, intype:$grady2)), + inst # " \t\\{$r, $g, $b, $a\\}, [$t, \\{$x, $y, $z, $z\\}]," + " \\{$gradx0, $gradx1, $gradx2, $gradx2\\}," + " \\{$grady0, $grady1, $grady2, $grady2\\};", + []>; + +multiclass TEX_UNIFIED_CUBE_GRAD { + def _R : TEX_UNIFIED_CUBE_GRAD_base; + def _I : TEX_UNIFIED_CUBE_GRAD_base; +} + +defm TEX_UNIFIED_CUBE_F32_F32_GRAD + : TEX_UNIFIED_CUBE_GRAD<"tex.grad.cube.v4.f32.f32", Float32Regs, Float32Regs>; +defm TEX_UNIFIED_CUBE_S32_F32_GRAD + : TEX_UNIFIED_CUBE_GRAD<"tex.grad.cube.v4.s32.f32", Int32Regs, Float32Regs>; +defm TEX_UNIFIED_CUBE_U32_F32_GRAD + : TEX_UNIFIED_CUBE_GRAD<"tex.grad.cube.v4.u32.f32", Int32Regs, Float32Regs>; + +class TEX_UNIFIED_CUBE_ARRAY_GRAD_base + : NVPTXInst<(outs outtype:$r, outtype:$g, + outtype:$b, outtype:$a), + !con(tex, (ins Int32Regs:$l, intype:$x, intype:$y, intype:$z, + intype:$gradx0, intype:$gradx1, + intype:$gradx2, intype:$grady0, + intype:$grady1, intype:$grady2)), + inst # " \t\\{$r, $g, $b, $a\\}, [$t, \\{$l, $x, $y, $z\\}]," + " \\{$gradx0, $gradx1, $gradx2, $gradx2\\}," + " \\{$grady0, $grady1, $grady2, $grady2\\};", + []>; +multiclass TEX_UNIFIED_CUBE_ARRAY_GRAD { + def _R : TEX_UNIFIED_CUBE_ARRAY_GRAD_base; + def _I : TEX_UNIFIED_CUBE_ARRAY_GRAD_base; +} + +defm TEX_UNIFIED_CUBE_ARRAY_F32_F32_GRAD + : TEX_UNIFIED_CUBE_ARRAY_GRAD<"tex.grad.acube.v4.f32.f32", + Float32Regs, Float32Regs>; +defm TEX_UNIFIED_CUBE_ARRAY_S32_F32_GRAD + : TEX_UNIFIED_CUBE_ARRAY_GRAD<"tex.grad.acube.v4.s32.f32", + Int32Regs, Float32Regs>; +defm TEX_UNIFIED_CUBE_ARRAY_U32_F32_GRAD + : TEX_UNIFIED_CUBE_ARRAY_GRAD<"tex.grad.acube.v4.u32.f32", + Int32Regs, Float32Regs>; + class TLD4_UNIFIED_2D_base : NVPTXInst<(outs outtype:$v0, outtype:$v1, diff --git a/llvm/lib/Target/NVPTX/NVPTXReplaceImageHandles.cpp b/llvm/lib/Target/NVPTX/NVPTXReplaceImageHandles.cpp index 85f75df39c0..f2515f97159 100644 --- a/llvm/lib/Target/NVPTX/NVPTXReplaceImageHandles.cpp +++ b/llvm/lib/Target/NVPTX/NVPTXReplaceImageHandles.cpp @@ -1319,6 +1319,18 @@ static unsigned texRegisterToIndexOpcode(unsigned RegOC) { return NVPTX::TEX_UNIFIED_CUBE_ARRAY_U32_F32_I; case NVPTX::TEX_UNIFIED_CUBE_ARRAY_U32_F32_LEVEL_R: return NVPTX::TEX_UNIFIED_CUBE_ARRAY_U32_F32_LEVEL_I; + case NVPTX::TEX_UNIFIED_CUBE_F32_F32_GRAD_R: + return NVPTX::TEX_UNIFIED_CUBE_F32_F32_GRAD_I; + case NVPTX::TEX_UNIFIED_CUBE_S32_F32_GRAD_R: + return NVPTX::TEX_UNIFIED_CUBE_S32_F32_GRAD_I; + case NVPTX::TEX_UNIFIED_CUBE_U32_F32_GRAD_R: + return NVPTX::TEX_UNIFIED_CUBE_U32_F32_GRAD_I; + case NVPTX::TEX_UNIFIED_CUBE_ARRAY_F32_F32_GRAD_R: + return NVPTX::TEX_UNIFIED_CUBE_ARRAY_F32_F32_GRAD_I; + case NVPTX::TEX_UNIFIED_CUBE_ARRAY_S32_F32_GRAD_R: + return NVPTX::TEX_UNIFIED_CUBE_ARRAY_S32_F32_GRAD_I; + case NVPTX::TEX_UNIFIED_CUBE_ARRAY_U32_F32_GRAD_R: + return NVPTX::TEX_UNIFIED_CUBE_ARRAY_U32_F32_GRAD_I; case NVPTX::TLD4_UNIFIED_R_2D_F32_F32_R: return NVPTX::TLD4_UNIFIED_R_2D_F32_F32_I; case NVPTX::TLD4_UNIFIED_G_2D_F32_F32_R: diff --git a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp index 4e164fda1d8..aec58d1c0dc 100644 --- a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp +++ b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp @@ -15430,7 +15430,8 @@ SDValue PPCTargetLowering::combineVectorShuffle(ShuffleVectorSDNode *SVN, for (int i = 1, e = Mask.size(); i < e; i += 2) { if (ShuffV[i] < 0) continue; - ShuffV[i] = (ShuffV[i - 1] + NumElts); + // If element from non-splat is undef, pick first element from splat. + ShuffV[i] = (ShuffV[i - 1] >= 0 ? ShuffV[i - 1] : 0) + NumElts; } // Example (odd elements from first vector): // vector_shuffle<16,0,17,1,18,2,19,3,20,4,21,5,22,6,23,7> t1, @@ -15438,7 +15439,8 @@ SDValue PPCTargetLowering::combineVectorShuffle(ShuffleVectorSDNode *SVN, for (int i = 0, e = Mask.size(); i < e; i += 2) { if (ShuffV[i] < 0) continue; - ShuffV[i] = (ShuffV[i + 1] + NumElts); + // If element from non-splat is undef, pick first element from splat. + ShuffV[i] = (ShuffV[i + 1] >= 0 ? ShuffV[i + 1] : 0) + NumElts; } } else { // Example (even elements from first vector): @@ -15447,7 +15449,8 @@ SDValue PPCTargetLowering::combineVectorShuffle(ShuffleVectorSDNode *SVN, for (int i = 0, e = Mask.size(); i < e; i += 2) { if (ShuffV[i] < 0) continue; - ShuffV[i] = ShuffV[i + 1] - NumElts; + // If element from non-splat is undef, pick first element from splat. + ShuffV[i] = ShuffV[i + 1] >= 0 ? ShuffV[i + 1] - NumElts : 0; } // Example (odd elements from first vector): // vector_shuffle<16,0,17,1,18,2,19,3,20,4,21,5,22,6,23,7> , t1 @@ -15455,7 +15458,8 @@ SDValue PPCTargetLowering::combineVectorShuffle(ShuffleVectorSDNode *SVN, for (int i = 1, e = Mask.size(); i < e; i += 2) { if (ShuffV[i] < 0) continue; - ShuffV[i] = ShuffV[i - 1] - NumElts; + // If element from non-splat is undef, pick first element from splat. + ShuffV[i] = ShuffV[i - 1] >= 0 ? ShuffV[i - 1] - NumElts : 0; } } diff --git a/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp b/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp index aaced58defe..15f6b65dea8 100644 --- a/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp +++ b/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp @@ -1973,14 +1973,6 @@ void PPCInstrInfo::LoadRegFromStackSlot(MachineFunction &MF, const DebugLoc &DL, unsigned Opcode = getLoadOpcodeForSpill(RC); NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(Opcode), DestReg), FrameIdx)); - PPCFunctionInfo *FuncInfo = MF.getInfo(); - - if (PPC::CRRCRegClass.hasSubClassEq(RC) || - PPC::CRBITRCRegClass.hasSubClassEq(RC)) - FuncInfo->setSpillsCR(); - - if (isXFormMemOp(Opcode)) - FuncInfo->setHasNonRISpills(); } void PPCInstrInfo::loadRegFromStackSlotNoUpd( @@ -1992,9 +1984,6 @@ void PPCInstrInfo::loadRegFromStackSlotNoUpd( DebugLoc DL; if (MI != MBB.end()) DL = MI->getDebugLoc(); - PPCFunctionInfo *FuncInfo = MF.getInfo(); - FuncInfo->setHasSpills(); - LoadRegFromStackSlot(MF, DL, DestReg, FrameIdx, RC, NewMIs); for (unsigned i = 0, e = NewMIs.size(); i != e; ++i) @@ -2155,11 +2144,17 @@ bool PPCInstrInfo::isPredicated(const MachineInstr &MI) const { bool PPCInstrInfo::isSchedulingBoundary(const MachineInstr &MI, const MachineBasicBlock *MBB, const MachineFunction &MF) const { + switch (MI.getOpcode()) { + default: + break; // Set MFFS and MTFSF as scheduling boundary to avoid unexpected code motion // across them, since some FP operations may change content of FPSCR. // TODO: Model FPSCR in PPC instruction definitions and remove the workaround - if (MI.getOpcode() == PPC::MFFS || MI.getOpcode() == PPC::MTFSF) + case PPC::MFFS: + case PPC::MTFSF: + case PPC::FENCE: return true; + } return TargetInstrInfo::isSchedulingBoundary(MI, MBB, MF); } diff --git a/llvm/lib/Target/PowerPC/PPCInstrInfo.td b/llvm/lib/Target/PowerPC/PPCInstrInfo.td index bf756e39bd5..5550ba42073 100644 --- a/llvm/lib/Target/PowerPC/PPCInstrInfo.td +++ b/llvm/lib/Target/PowerPC/PPCInstrInfo.td @@ -1328,6 +1328,9 @@ def SETFLM : PPCCustomInserterPseudo<(outs f8rc:$FRT), (ins f8rc:$FLM), "#SETFLM", [(set f64:$FRT, (int_ppc_setflm f8rc:$FLM))]>; } +let isBarrier = 1, hasSideEffects = 1, Defs = [RM] in +def FENCE : PPCEmitTimePseudo<(outs), (ins), "#FENCE", []>; + let Defs = [LR] in def MovePCtoLR : PPCEmitTimePseudo<(outs), (ins), "#MovePCtoLR", []>, PPC970_Unit_BRU; @@ -3187,6 +3190,7 @@ def : Pat<(PPCtc_return (i32 texternalsym:$dst), imm:$imm), def : Pat<(PPCtc_return CTRRC:$dst, imm:$imm), (TCRETURNri CTRRC:$dst, imm:$imm)>; +def : Pat<(int_ppc_fence), (FENCE)>; def : Pat<(int_ppc_readflm), (MFFS)>; def : Pat<(int_ppc_mffsl), (MFFSL)>; diff --git a/llvm/lib/Target/PowerPC/PPCTargetTransformInfo.cpp b/llvm/lib/Target/PowerPC/PPCTargetTransformInfo.cpp index 062b53e24a0..958353f2b4f 100644 --- a/llvm/lib/Target/PowerPC/PPCTargetTransformInfo.cpp +++ b/llvm/lib/Target/PowerPC/PPCTargetTransformInfo.cpp @@ -788,9 +788,10 @@ InstructionCost PPCTTIImpl::getMemoryOpCost(unsigned Opcode, Type *Src, // VSX has 32b/64b load instructions. Legalization can handle loading of // 32b/64b to VSR correctly and cheaply. But BaseT::getMemoryOpCost and // PPCTargetLowering can't compute the cost appropriately. So here we - // explicitly check this case. + // explicitly check this case. There are also corresponding store + // instructions. unsigned MemBytes = Src->getPrimitiveSizeInBits(); - if (Opcode == Instruction::Load && ST->hasVSX() && IsAltivecType && + if (ST->hasVSX() && IsAltivecType && (MemBytes == 64 || (ST->hasP8Vector() && MemBytes == 32))) return 1; diff --git a/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp b/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp index 7d42481db57..f6e8386aff4 100644 --- a/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp +++ b/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp @@ -169,6 +169,12 @@ class RISCVAsmParser : public MCTargetAsmParser { // 'add' is an overloaded mnemonic. bool checkPseudoAddTPRel(MCInst &Inst, OperandVector &Operands); + // Checks that a PseudoTLSDESCCall is using x5/t0 in its output operand. + // Enforcing this using a restricted register class for the output + // operand of PseudoTLSDESCCall results in a poor diagnostic due to the fact + // 'jalr' is an overloaded mnemonic. + bool checkPseudoTLSDESCCall(MCInst &Inst, OperandVector &Operands); + // Check instruction constraints. bool validateInstruction(MCInst &Inst, OperandVector &Operands); @@ -549,6 +555,16 @@ public: VK == RISCVMCExpr::VK_RISCV_TPREL_ADD; } + bool isTLSDESCCallSymbol() const { + int64_t Imm; + RISCVMCExpr::VariantKind VK = RISCVMCExpr::VK_RISCV_None; + // Must be of 'immediate' type but not a constant. + if (!isImm() || evaluateConstantImm(getImm(), Imm, VK)) + return false; + return RISCVAsmParser::classifySymbolRef(getImm(), VK) && + VK == RISCVMCExpr::VK_RISCV_TLSDESC_CALL; + } + bool isCSRSystemRegister() const { return isSystemRegister(); } bool isVTypeImm(unsigned N) const { @@ -601,7 +617,10 @@ public: if (!isImm()) return false; bool IsConstantImm = evaluateConstantImm(getImm(), Imm, VK); - if (VK == RISCVMCExpr::VK_RISCV_LO || VK == RISCVMCExpr::VK_RISCV_PCREL_LO) + if (VK == RISCVMCExpr::VK_RISCV_LO || + VK == RISCVMCExpr::VK_RISCV_PCREL_LO || + VK == RISCVMCExpr::VK_RISCV_TLSDESC_LOAD_LO || + VK == RISCVMCExpr::VK_RISCV_TLSDESC_ADD_LO) return true; // Given only Imm, ensuring that the actually specified constant is either // a signed or unsigned 64-bit number is unfortunately impossible. @@ -854,7 +873,9 @@ public: return IsValid && ((IsConstantImm && VK == RISCVMCExpr::VK_RISCV_None) || VK == RISCVMCExpr::VK_RISCV_LO || VK == RISCVMCExpr::VK_RISCV_PCREL_LO || - VK == RISCVMCExpr::VK_RISCV_TPREL_LO); + VK == RISCVMCExpr::VK_RISCV_TPREL_LO || + VK == RISCVMCExpr::VK_RISCV_TLSDESC_LOAD_LO || + VK == RISCVMCExpr::VK_RISCV_TLSDESC_ADD_LO); } bool isSImm12Lsb0() const { return isBareSimmNLsb0<12>(); } @@ -911,14 +932,16 @@ public: return IsValid && (VK == RISCVMCExpr::VK_RISCV_PCREL_HI || VK == RISCVMCExpr::VK_RISCV_GOT_HI || VK == RISCVMCExpr::VK_RISCV_TLS_GOT_HI || - VK == RISCVMCExpr::VK_RISCV_TLS_GD_HI); - } else { - return isUInt<20>(Imm) && (VK == RISCVMCExpr::VK_RISCV_None || - VK == RISCVMCExpr::VK_RISCV_PCREL_HI || - VK == RISCVMCExpr::VK_RISCV_GOT_HI || - VK == RISCVMCExpr::VK_RISCV_TLS_GOT_HI || - VK == RISCVMCExpr::VK_RISCV_TLS_GD_HI); + VK == RISCVMCExpr::VK_RISCV_TLS_GD_HI || + VK == RISCVMCExpr::VK_RISCV_TLSDESC_HI); } + + return isUInt<20>(Imm) && (VK == RISCVMCExpr::VK_RISCV_None || + VK == RISCVMCExpr::VK_RISCV_PCREL_HI || + VK == RISCVMCExpr::VK_RISCV_GOT_HI || + VK == RISCVMCExpr::VK_RISCV_TLS_GOT_HI || + VK == RISCVMCExpr::VK_RISCV_TLS_GD_HI || + VK == RISCVMCExpr::VK_RISCV_TLSDESC_HI); } bool isSImm21Lsb0JAL() const { return isBareSimmNLsb0<21>(); } @@ -1556,6 +1579,11 @@ bool RISCVAsmParser::MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode, SMLoc ErrorLoc = ((RISCVOperand &)*Operands[ErrorInfo]).getStartLoc(); return Error(ErrorLoc, "operand must be a symbol with %tprel_add modifier"); } + case Match_InvalidTLSDESCCallSymbol: { + SMLoc ErrorLoc = ((RISCVOperand &)*Operands[ErrorInfo]).getStartLoc(); + return Error(ErrorLoc, + "operand must be a symbol with %tlsdesc_call modifier"); + } case Match_InvalidRTZArg: { SMLoc ErrorLoc = ((RISCVOperand &)*Operands[ErrorInfo]).getStartLoc(); return Error(ErrorLoc, "operand must be 'rtz' floating-point rounding mode"); @@ -3324,6 +3352,19 @@ bool RISCVAsmParser::checkPseudoAddTPRel(MCInst &Inst, return false; } +bool RISCVAsmParser::checkPseudoTLSDESCCall(MCInst &Inst, + OperandVector &Operands) { + assert(Inst.getOpcode() == RISCV::PseudoTLSDESCCall && "Invalid instruction"); + assert(Inst.getOperand(0).isReg() && "Unexpected operand kind"); + if (Inst.getOperand(0).getReg() != RISCV::X5) { + SMLoc ErrorLoc = ((RISCVOperand &)*Operands[3]).getStartLoc(); + return Error(ErrorLoc, "the output operand must be t0/x5 when using " + "%tlsdesc_call modifier"); + } + + return false; +} + std::unique_ptr RISCVAsmParser::defaultMaskRegOp() const { return RISCVOperand::createReg(RISCV::NoRegister, llvm::SMLoc(), llvm::SMLoc()); @@ -3559,6 +3600,10 @@ bool RISCVAsmParser::processInstruction(MCInst &Inst, SMLoc IDLoc, if (checkPseudoAddTPRel(Inst, Operands)) return true; break; + case RISCV::PseudoTLSDESCCall: + if (checkPseudoTLSDESCCall(Inst, Operands)) + return true; + break; case RISCV::PseudoSEXT_B: emitPseudoExtend(Inst, /*SignExtend=*/true, /*Width=*/8, IDLoc, Out); return false; diff --git a/llvm/lib/Target/RISCV/GISel/RISCVCallLowering.cpp b/llvm/lib/Target/RISCV/GISel/RISCVCallLowering.cpp index 697ad476ff8..26eac17ed24 100644 --- a/llvm/lib/Target/RISCV/GISel/RISCVCallLowering.cpp +++ b/llvm/lib/Target/RISCV/GISel/RISCVCallLowering.cpp @@ -146,11 +146,11 @@ struct RISCVOutgoingValueHandler : public CallLowering::OutgoingValueHandler { if (Thunk) { *Thunk = assignFunc; - return 1; + return 2; } assignFunc(); - return 1; + return 2; } private: @@ -266,7 +266,7 @@ struct RISCVIncomingValueHandler : public CallLowering::IncomingValueHandler { MIRBuilder.buildMergeLikeInstr(Arg.Regs[0], NewRegs); - return 1; + return 2; } /// How the physical register gets marked varies between formal @@ -431,7 +431,7 @@ void RISCVCallLowering::saveVarArgRegisters( MachineFunction &MF = MIRBuilder.getMF(); const RISCVSubtarget &Subtarget = MF.getSubtarget(); unsigned XLenInBytes = Subtarget.getXLen() / 8; - ArrayRef ArgRegs = RISCV::getArgGPRs(); + ArrayRef ArgRegs = RISCV::getArgGPRs(Subtarget.getTargetABI()); MachineRegisterInfo &MRI = MF.getRegInfo(); unsigned Idx = CCInfo.getFirstUnallocated(ArgRegs); MachineFrameInfo &MFI = MF.getFrameInfo(); diff --git a/llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp b/llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp index 61bdbfc47d9..65a0a3e0929 100644 --- a/llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp +++ b/llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp @@ -16,6 +16,7 @@ #include "RISCVSubtarget.h" #include "RISCVTargetMachine.h" #include "llvm/CodeGen/GlobalISel/GIMatchTableExecutorImpl.h" +#include "llvm/CodeGen/GlobalISel/GISelKnownBits.h" #include "llvm/CodeGen/GlobalISel/GenericMachineInstrs.h" #include "llvm/CodeGen/GlobalISel/InstructionSelector.h" #include "llvm/CodeGen/GlobalISel/MIPatternMatch.h" @@ -159,9 +160,71 @@ RISCVInstructionSelector::RISCVInstructionSelector( InstructionSelector::ComplexRendererFns RISCVInstructionSelector::selectShiftMask(MachineOperand &Root) const { - // TODO: Also check if we are seeing the result of an AND operation which - // could be bypassed since we only check the lower log2(xlen) bits. - return {{[=](MachineInstrBuilder &MIB) { MIB.add(Root); }}}; + if (!Root.isReg()) + return std::nullopt; + + using namespace llvm::MIPatternMatch; + MachineRegisterInfo &MRI = MF->getRegInfo(); + + Register RootReg = Root.getReg(); + Register ShAmtReg = RootReg; + const LLT ShiftLLT = MRI.getType(RootReg); + unsigned ShiftWidth = ShiftLLT.getSizeInBits(); + assert(isPowerOf2_32(ShiftWidth) && "Unexpected max shift amount!"); + // Peek through zext. + Register ZExtSrcReg; + if (mi_match(ShAmtReg, MRI, m_GZExt(m_Reg(ZExtSrcReg)))) { + ShAmtReg = ZExtSrcReg; + } + + APInt AndMask; + Register AndSrcReg; + if (mi_match(ShAmtReg, MRI, m_GAnd(m_Reg(AndSrcReg), m_ICst(AndMask)))) { + APInt ShMask(AndMask.getBitWidth(), ShiftWidth - 1); + if (ShMask.isSubsetOf(AndMask)) { + ShAmtReg = AndSrcReg; + } else { + // SimplifyDemandedBits may have optimized the mask so try restoring any + // bits that are known zero. + KnownBits Known = KB->getKnownBits(ShAmtReg); + if (ShMask.isSubsetOf(AndMask | Known.Zero)) + ShAmtReg = AndSrcReg; + } + } + + APInt Imm; + Register Reg; + if (mi_match(ShAmtReg, MRI, m_GAdd(m_Reg(Reg), m_ICst(Imm)))) { + if (Imm != 0 && Imm.urem(ShiftWidth) == 0) + // If we are shifting by X+N where N == 0 mod Size, then just shift by X + // to avoid the ADD. + ShAmtReg = Reg; + } else if (mi_match(ShAmtReg, MRI, m_GSub(m_ICst(Imm), m_Reg(Reg)))) { + if (Imm != 0 && Imm.urem(ShiftWidth) == 0) { + // If we are shifting by N-X where N == 0 mod Size, then just shift by -X + // to generate a NEG instead of a SUB of a constant. + ShAmtReg = MRI.createVirtualRegister(&RISCV::GPRRegClass); + unsigned NegOpc = Subtarget->is64Bit() ? RISCV::SUBW : RISCV::SUB; + return {{[=](MachineInstrBuilder &MIB) { + MachineIRBuilder(*MIB.getInstr()) + .buildInstr(NegOpc, {ShAmtReg}, {Register(RISCV::X0), Reg}); + MIB.addReg(ShAmtReg); + }}}; + } + if (Imm.urem(ShiftWidth) == ShiftWidth - 1) { + // If we are shifting by N-X where N == -1 mod Size, then just shift by ~X + // to generate a NOT instead of a SUB of a constant. + ShAmtReg = MRI.createVirtualRegister(&RISCV::GPRRegClass); + return {{[=](MachineInstrBuilder &MIB) { + MachineIRBuilder(*MIB.getInstr()) + .buildInstr(RISCV::XORI, {ShAmtReg}, {Reg}) + .addImm(-1); + MIB.addReg(ShAmtReg); + }}}; + } + } + + return {{[=](MachineInstrBuilder &MIB) { MIB.addReg(ShAmtReg); }}}; } InstructionSelector::ComplexRendererFns @@ -200,8 +263,7 @@ RISCVInstructionSelector::selectSHXADDOp(MachineOperand &Root, // Given (and (shl y, c2), mask) in which mask has no leading zeros and // c3 trailing zeros. We can use an SRLI by c3 - c2 followed by a SHXADD. if (*LeftShift && Leading == 0 && C2.ult(Trailing) && Trailing == ShAmt) { - Register DstReg = - MRI.createGenericVirtualRegister(MRI.getType(RootReg)); + Register DstReg = MRI.createVirtualRegister(&RISCV::GPRRegClass); return {{[=](MachineInstrBuilder &MIB) { MachineIRBuilder(*MIB.getInstr()) .buildInstr(RISCV::SRLI, {DstReg}, {RegY}) @@ -213,8 +275,7 @@ RISCVInstructionSelector::selectSHXADDOp(MachineOperand &Root, // Given (and (lshr y, c2), mask) in which mask has c2 leading zeros and // c3 trailing zeros. We can use an SRLI by c2 + c3 followed by a SHXADD. if (!*LeftShift && Leading == C2 && Trailing == ShAmt) { - Register DstReg = - MRI.createGenericVirtualRegister(MRI.getType(RootReg)); + Register DstReg = MRI.createVirtualRegister(&RISCV::GPRRegClass); return {{[=](MachineInstrBuilder &MIB) { MachineIRBuilder(*MIB.getInstr()) .buildInstr(RISCV::SRLI, {DstReg}, {RegY}) @@ -253,7 +314,7 @@ RISCVInstructionSelector::selectSHXADDOp(MachineOperand &Root, (Trailing - C2.getLimitedValue()) == ShAmt; if (Cond) { - Register DstReg = MRI.createGenericVirtualRegister(MRI.getType(RootReg)); + Register DstReg = MRI.createVirtualRegister(&RISCV::GPRRegClass); return {{[=](MachineInstrBuilder &MIB) { MachineIRBuilder(*MIB.getInstr()) .buildInstr(RISCV::SRLIW, {DstReg}, {RegY}) @@ -292,8 +353,7 @@ RISCVInstructionSelector::selectSHXADD_UWOp(MachineOperand &Root, unsigned Leading = Mask.countl_zero(); unsigned Trailing = Mask.countr_zero(); if (Leading == 32 - ShAmt && C2 == Trailing && Trailing > ShAmt) { - Register DstReg = - MRI.createGenericVirtualRegister(MRI.getType(RootReg)); + Register DstReg = MRI.createVirtualRegister(&RISCV::GPRRegClass); return {{[=](MachineInstrBuilder &MIB) { MachineIRBuilder(*MIB.getInstr()) .buildInstr(RISCV::SLLI, {DstReg}, {RegX}) diff --git a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVAsmBackend.cpp b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVAsmBackend.cpp index 7ce08eabdeb..bd49875c959 100644 --- a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVAsmBackend.cpp +++ b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVAsmBackend.cpp @@ -86,6 +86,12 @@ RISCVAsmBackend::getFixupKindInfo(MCFixupKind Kind) const { {"fixup_riscv_call_plt", 0, 64, MCFixupKindInfo::FKF_IsPCRel}, {"fixup_riscv_relax", 0, 0, 0}, {"fixup_riscv_align", 0, 0, 0}, + + {"fixup_riscv_tlsdesc_hi20", 12, 20, + MCFixupKindInfo::FKF_IsPCRel | MCFixupKindInfo::FKF_IsTarget}, + {"fixup_riscv_tlsdesc_load_lo12", 20, 12, 0}, + {"fixup_riscv_tlsdesc_add_lo12", 20, 12, 0}, + {"fixup_riscv_tlsdesc_call", 0, 0, 0}, }; static_assert((std::size(Infos)) == RISCV::NumTargetFixupKinds, "Not all fixup kinds added to Infos array"); @@ -126,6 +132,7 @@ bool RISCVAsmBackend::shouldForceRelocation(const MCAssembler &Asm, case RISCV::fixup_riscv_got_hi20: case RISCV::fixup_riscv_tls_got_hi20: case RISCV::fixup_riscv_tls_gd_hi20: + case RISCV::fixup_riscv_tlsdesc_hi20: return true; } @@ -411,6 +418,7 @@ static uint64_t adjustFixupValue(const MCFixup &Fixup, uint64_t Value, case RISCV::fixup_riscv_got_hi20: case RISCV::fixup_riscv_tls_got_hi20: case RISCV::fixup_riscv_tls_gd_hi20: + case RISCV::fixup_riscv_tlsdesc_hi20: llvm_unreachable("Relocation should be unconditionally forced\n"); case FK_Data_1: case FK_Data_2: @@ -421,6 +429,7 @@ static uint64_t adjustFixupValue(const MCFixup &Fixup, uint64_t Value, case RISCV::fixup_riscv_lo12_i: case RISCV::fixup_riscv_pcrel_lo12_i: case RISCV::fixup_riscv_tprel_lo12_i: + case RISCV::fixup_riscv_tlsdesc_load_lo12: return Value & 0xfff; case RISCV::fixup_riscv_12_i: if (!isInt<12>(Value)) { @@ -524,6 +533,7 @@ bool RISCVAsmBackend::evaluateTargetFixup( switch (Fixup.getTargetKind()) { default: llvm_unreachable("Unexpected fixup kind!"); + case RISCV::fixup_riscv_tlsdesc_hi20: case RISCV::fixup_riscv_pcrel_hi20: AUIPCFixup = &Fixup; AUIPCDF = DF; diff --git a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.cpp b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.cpp index 74d0db545e5..be9c7d190b5 100644 --- a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.cpp +++ b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.cpp @@ -68,6 +68,11 @@ ABI computeTargetABI(const Triple &TT, const FeatureBitset &FeatureBits, TargetABI = ABI_Unknown; } + if ((TargetABI == RISCVABI::ABI::ABI_ILP32E || + (TargetABI == ABI_Unknown && IsRVE && !IsRV64)) && + FeatureBits[RISCV::FeatureStdExtD]) + report_fatal_error("ILP32E cannot be used with the D ISA extension"); + if (TargetABI != ABI_Unknown) return TargetABI; diff --git a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h index 433e2e6f80b..d7f7859ce43 100644 --- a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h +++ b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h @@ -264,11 +264,15 @@ enum { MO_TPREL_ADD = 10, MO_TLS_GOT_HI = 11, MO_TLS_GD_HI = 12, + MO_TLSDESC_HI = 13, + MO_TLSDESC_LOAD_LO = 14, + MO_TLSDESC_ADD_LO = 15, + MO_TLSDESC_CALL = 16, // Used to differentiate between target-specific "direct" flags and "bitmask" // flags. A machine operand can only have one "direct" flag, but can have // multiple "bitmask" flags. - MO_DIRECT_FLAG_MASK = 15 + MO_DIRECT_FLAG_MASK = 31 }; } // namespace RISCVII diff --git a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVELFObjectWriter.cpp b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVELFObjectWriter.cpp index 76e5b3ed402..2343c5fb253 100644 --- a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVELFObjectWriter.cpp +++ b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVELFObjectWriter.cpp @@ -77,6 +77,14 @@ unsigned RISCVELFObjectWriter::getRelocType(MCContext &Ctx, return ELF::R_RISCV_TLS_GOT_HI20; case RISCV::fixup_riscv_tls_gd_hi20: return ELF::R_RISCV_TLS_GD_HI20; + case RISCV::fixup_riscv_tlsdesc_hi20: + return ELF::R_RISCV_TLSDESC_HI20; + case RISCV::fixup_riscv_tlsdesc_load_lo12: + return ELF::R_RISCV_TLSDESC_LOAD_LO12; + case RISCV::fixup_riscv_tlsdesc_add_lo12: + return ELF::R_RISCV_TLSDESC_ADD_LO12; + case RISCV::fixup_riscv_tlsdesc_call: + return ELF::R_RISCV_TLSDESC_CALL; case RISCV::fixup_riscv_jal: return ELF::R_RISCV_JAL; case RISCV::fixup_riscv_branch: @@ -96,6 +104,13 @@ unsigned RISCVELFObjectWriter::getRelocType(MCContext &Ctx, default: Ctx.reportError(Fixup.getLoc(), "unsupported relocation type"); return ELF::R_RISCV_NONE; + case RISCV::fixup_riscv_tlsdesc_load_lo12: + return ELF::R_RISCV_TLSDESC_LOAD_LO12; + case RISCV::fixup_riscv_tlsdesc_add_lo12: + return ELF::R_RISCV_TLSDESC_ADD_LO12; + case RISCV::fixup_riscv_tlsdesc_call: + return ELF::R_RISCV_TLSDESC_CALL; + case FK_Data_1: Ctx.reportError(Fixup.getLoc(), "1-byte data relocations not supported"); return ELF::R_RISCV_NONE; diff --git a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVFixupKinds.h b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVFixupKinds.h index 74bd9398a9e..821372d3d39 100644 --- a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVFixupKinds.h +++ b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVFixupKinds.h @@ -71,6 +71,12 @@ enum Fixups { // Used to generate an R_RISCV_ALIGN relocation, which indicates the linker // should fixup the alignment after linker relaxation. fixup_riscv_align, + // Fixups indicating a TLS descriptor code sequence, corresponding to auipc, + // lw/ld, addi, and jalr, respectively. + fixup_riscv_tlsdesc_hi20, + fixup_riscv_tlsdesc_load_lo12, + fixup_riscv_tlsdesc_add_lo12, + fixup_riscv_tlsdesc_call, // Used as a sentinel, must be the last fixup_riscv_invalid, diff --git a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCCodeEmitter.cpp b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCCodeEmitter.cpp index 82fed50bce7..5ea386c3c32 100644 --- a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCCodeEmitter.cpp +++ b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCCodeEmitter.cpp @@ -57,6 +57,10 @@ public: SmallVectorImpl &Fixups, const MCSubtargetInfo &STI) const; + void expandTLSDESCCall(const MCInst &MI, SmallVectorImpl &CB, + SmallVectorImpl &Fixups, + const MCSubtargetInfo &STI) const; + void expandAddTPRel(const MCInst &MI, SmallVectorImpl &CB, SmallVectorImpl &Fixups, const MCSubtargetInfo &STI) const; @@ -154,6 +158,26 @@ void RISCVMCCodeEmitter::expandFunctionCall(const MCInst &MI, support::endian::write(CB, Binary, llvm::endianness::little); } +void RISCVMCCodeEmitter::expandTLSDESCCall(const MCInst &MI, + SmallVectorImpl &CB, + SmallVectorImpl &Fixups, + const MCSubtargetInfo &STI) const { + MCOperand SrcSymbol = MI.getOperand(3); + assert(SrcSymbol.isExpr() && + "Expected expression as first input to TLSDESCCALL"); + const RISCVMCExpr *Expr = dyn_cast(SrcSymbol.getExpr()); + MCRegister Link = MI.getOperand(0).getReg(); + MCRegister Dest = MI.getOperand(1).getReg(); + MCRegister Imm = MI.getOperand(2).getImm(); + Fixups.push_back(MCFixup::create( + 0, Expr, MCFixupKind(RISCV::fixup_riscv_tlsdesc_call), MI.getLoc())); + MCInst Call = + MCInstBuilder(RISCV::JALR).addReg(Link).addReg(Dest).addImm(Imm); + + uint32_t Binary = getBinaryCodeForInstr(Call, Fixups, STI); + support::endian::write(CB, Binary, llvm::endianness::little); +} + // Expand PseudoAddTPRel to a simple ADD with the correct relocation. void RISCVMCCodeEmitter::expandAddTPRel(const MCInst &MI, SmallVectorImpl &CB, @@ -303,6 +327,10 @@ void RISCVMCCodeEmitter::encodeInstruction(const MCInst &MI, expandLongCondBr(MI, CB, Fixups, STI); MCNumEmitted += 2; return; + case RISCV::PseudoTLSDESCCall: + expandTLSDESCCall(MI, CB, Fixups, STI); + MCNumEmitted += 1; + return; } switch (Size) { @@ -445,6 +473,18 @@ unsigned RISCVMCCodeEmitter::getImmOpValue(const MCInst &MI, unsigned OpNo, FixupKind = RISCV::fixup_riscv_call_plt; RelaxCandidate = true; break; + case RISCVMCExpr::VK_RISCV_TLSDESC_HI: + FixupKind = RISCV::fixup_riscv_tlsdesc_hi20; + break; + case RISCVMCExpr::VK_RISCV_TLSDESC_LOAD_LO: + FixupKind = RISCV::fixup_riscv_tlsdesc_load_lo12; + break; + case RISCVMCExpr::VK_RISCV_TLSDESC_ADD_LO: + FixupKind = RISCV::fixup_riscv_tlsdesc_add_lo12; + break; + case RISCVMCExpr::VK_RISCV_TLSDESC_CALL: + FixupKind = RISCV::fixup_riscv_tlsdesc_call; + break; } } else if ((Kind == MCExpr::SymbolRef && cast(Expr)->getKind() == diff --git a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCExpr.cpp b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCExpr.cpp index 64ddae61b1b..254a9a4bc0e 100644 --- a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCExpr.cpp +++ b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCExpr.cpp @@ -79,6 +79,7 @@ const MCFixup *RISCVMCExpr::getPCRelHiFixup(const MCFragment **DFOut) const { case RISCV::fixup_riscv_tls_got_hi20: case RISCV::fixup_riscv_tls_gd_hi20: case RISCV::fixup_riscv_pcrel_hi20: + case RISCV::fixup_riscv_tlsdesc_hi20: if (DFOut) *DFOut = DF; return &F; @@ -119,6 +120,10 @@ RISCVMCExpr::VariantKind RISCVMCExpr::getVariantKindForName(StringRef name) { .Case("tprel_add", VK_RISCV_TPREL_ADD) .Case("tls_ie_pcrel_hi", VK_RISCV_TLS_GOT_HI) .Case("tls_gd_pcrel_hi", VK_RISCV_TLS_GD_HI) + .Case("tlsdesc_hi", VK_RISCV_TLSDESC_HI) + .Case("tlsdesc_load_lo", VK_RISCV_TLSDESC_LOAD_LO) + .Case("tlsdesc_add_lo", VK_RISCV_TLSDESC_ADD_LO) + .Case("tlsdesc_call", VK_RISCV_TLSDESC_CALL) .Default(VK_RISCV_Invalid); } @@ -145,6 +150,14 @@ StringRef RISCVMCExpr::getVariantKindName(VariantKind Kind) { return "tprel_add"; case VK_RISCV_TLS_GOT_HI: return "tls_ie_pcrel_hi"; + case VK_RISCV_TLSDESC_HI: + return "tlsdesc_hi"; + case VK_RISCV_TLSDESC_LOAD_LO: + return "tlsdesc_load_lo"; + case VK_RISCV_TLSDESC_ADD_LO: + return "tlsdesc_add_lo"; + case VK_RISCV_TLSDESC_CALL: + return "tlsdesc_call"; case VK_RISCV_TLS_GD_HI: return "tls_gd_pcrel_hi"; case VK_RISCV_CALL: @@ -193,6 +206,9 @@ void RISCVMCExpr::fixELFSymbolsInTLSFixups(MCAssembler &Asm) const { case VK_RISCV_TPREL_HI: case VK_RISCV_TLS_GOT_HI: case VK_RISCV_TLS_GD_HI: + case VK_RISCV_TLSDESC_HI: + case VK_RISCV_TLSDESC_ADD_LO: + case VK_RISCV_TLSDESC_LOAD_LO: break; } @@ -206,6 +222,8 @@ bool RISCVMCExpr::evaluateAsConstant(int64_t &Res) const { Kind == VK_RISCV_GOT_HI || Kind == VK_RISCV_TPREL_HI || Kind == VK_RISCV_TPREL_LO || Kind == VK_RISCV_TPREL_ADD || Kind == VK_RISCV_TLS_GOT_HI || Kind == VK_RISCV_TLS_GD_HI || + Kind == VK_RISCV_TLSDESC_HI || Kind == VK_RISCV_TLSDESC_LOAD_LO || + Kind == VK_RISCV_TLSDESC_ADD_LO || Kind == VK_RISCV_TLSDESC_CALL || Kind == VK_RISCV_CALL || Kind == VK_RISCV_CALL_PLT) return false; diff --git a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCExpr.h b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCExpr.h index ee83bf0208e..fcc4c5c4396 100644 --- a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCExpr.h +++ b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCExpr.h @@ -37,6 +37,10 @@ public: VK_RISCV_CALL, VK_RISCV_CALL_PLT, VK_RISCV_32_PCREL, + VK_RISCV_TLSDESC_HI, + VK_RISCV_TLSDESC_LOAD_LO, + VK_RISCV_TLSDESC_ADD_LO, + VK_RISCV_TLSDESC_CALL, VK_RISCV_Invalid // Must be the last item }; diff --git a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVTargetStreamer.cpp b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVTargetStreamer.cpp index 29ffc3224b5..ac4861bf113 100644 --- a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVTargetStreamer.cpp +++ b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVTargetStreamer.cpp @@ -50,11 +50,14 @@ void RISCVTargetStreamer::setTargetABI(RISCVABI::ABI ABI) { void RISCVTargetStreamer::emitTargetAttributes(const MCSubtargetInfo &STI, bool EmitStackAlign) { - if (STI.hasFeature(RISCV::FeatureRVE)) - report_fatal_error("Codegen not yet implemented for RVE"); - - if (EmitStackAlign) - emitAttribute(RISCVAttrs::STACK_ALIGN, RISCVAttrs::ALIGN_16); + if (EmitStackAlign) { + if (TargetABI == RISCVABI::ABI_ILP32E) + emitAttribute(RISCVAttrs::STACK_ALIGN, RISCVAttrs::ALIGN_4); + else if (TargetABI == RISCVABI::ABI_LP64E) + emitAttribute(RISCVAttrs::STACK_ALIGN, RISCVAttrs::ALIGN_8); + else + emitAttribute(RISCVAttrs::STACK_ALIGN, RISCVAttrs::ALIGN_16); + } auto ParseResult = RISCVFeatures::parseFeatureBits( STI.hasFeature(RISCV::Feature64Bit), STI.getFeatureBits()); diff --git a/llvm/lib/Target/RISCV/RISCV.td b/llvm/lib/Target/RISCV/RISCV.td index be93d5933d3..e6e87928224 100644 --- a/llvm/lib/Target/RISCV/RISCV.td +++ b/llvm/lib/Target/RISCV/RISCV.td @@ -36,6 +36,7 @@ include "GISel/RISCVRegisterBanks.td" include "RISCVSchedRocket.td" include "RISCVSchedSiFive7.td" +include "RISCVSchedSiFiveP400.td" include "RISCVSchedSyntacoreSCR1.td" //===----------------------------------------------------------------------===// diff --git a/llvm/lib/Target/RISCV/RISCVAsmPrinter.cpp b/llvm/lib/Target/RISCV/RISCVAsmPrinter.cpp index f2bd5118fc0..b2e9cd87373 100644 --- a/llvm/lib/Target/RISCV/RISCVAsmPrinter.cpp +++ b/llvm/lib/Target/RISCV/RISCVAsmPrinter.cpp @@ -323,7 +323,8 @@ bool RISCVAsmPrinter::PrintAsmMemoryOperand(const MachineInstr *MI, // RISCVDAGToDAGISel::SelectInlineAsmMemoryOperand). if (!AddrReg.isReg()) return true; - if (!Offset.isImm() && !Offset.isGlobal() && !Offset.isBlockAddress()) + if (!Offset.isImm() && !Offset.isGlobal() && !Offset.isBlockAddress() && + !Offset.isMCSymbol()) return true; MCOperand MCO; @@ -332,7 +333,7 @@ bool RISCVAsmPrinter::PrintAsmMemoryOperand(const MachineInstr *MI, if (Offset.isImm()) OS << MCO.getImm(); - else if (Offset.isGlobal() || Offset.isBlockAddress()) + else if (Offset.isGlobal() || Offset.isBlockAddress() || Offset.isMCSymbol()) OS << *MCO.getExpr(); OS << "(" << RISCVInstPrinter::getRegisterName(AddrReg.getReg()) << ")"; return false; @@ -779,6 +780,18 @@ static MCOperand lowerSymbolOperand(const MachineOperand &MO, MCSymbol *Sym, case RISCVII::MO_TLS_GD_HI: Kind = RISCVMCExpr::VK_RISCV_TLS_GD_HI; break; + case RISCVII::MO_TLSDESC_HI: + Kind = RISCVMCExpr::VK_RISCV_TLSDESC_HI; + break; + case RISCVII::MO_TLSDESC_LOAD_LO: + Kind = RISCVMCExpr::VK_RISCV_TLSDESC_LOAD_LO; + break; + case RISCVII::MO_TLSDESC_ADD_LO: + Kind = RISCVMCExpr::VK_RISCV_TLSDESC_ADD_LO; + break; + case RISCVII::MO_TLSDESC_CALL: + Kind = RISCVMCExpr::VK_RISCV_TLSDESC_CALL; + break; } const MCExpr *ME = diff --git a/llvm/lib/Target/RISCV/RISCVCallingConv.td b/llvm/lib/Target/RISCV/RISCVCallingConv.td index 3dd0b372382..11b716f20f3 100644 --- a/llvm/lib/Target/RISCV/RISCVCallingConv.td +++ b/llvm/lib/Target/RISCV/RISCVCallingConv.td @@ -13,8 +13,10 @@ // The RISC-V calling convention is handled with custom code in // RISCVISelLowering.cpp (CC_RISCV). +def CSR_ILP32E_LP64E : CalleeSavedRegs<(add X1, X8, X9)>; + def CSR_ILP32_LP64 - : CalleeSavedRegs<(add X1, X8, X9, (sequence "X%u", 18, 27))>; + : CalleeSavedRegs<(add CSR_ILP32E_LP64E, (sequence "X%u", 18, 27))>; def CSR_ILP32F_LP64F : CalleeSavedRegs<(add CSR_ILP32_LP64, @@ -38,3 +40,15 @@ def CSR_XLEN_F32_Interrupt: CalleeSavedRegs<(add CSR_Interrupt, // Same as CSR_Interrupt, but including all 64-bit FP registers. def CSR_XLEN_F64_Interrupt: CalleeSavedRegs<(add CSR_Interrupt, (sequence "F%u_D", 0, 31))>; + +// Same as CSR_Interrupt, but excluding X16-X31. +def CSR_Interrupt_RVE : CalleeSavedRegs<(sub CSR_Interrupt, + (sequence "X%u", 16, 31))>; + +// Same as CSR_XLEN_F32_Interrupt, but excluding X16-X31. +def CSR_XLEN_F32_Interrupt_RVE: CalleeSavedRegs<(sub CSR_XLEN_F32_Interrupt, + (sequence "X%u", 16, 31))>; + +// Same as CSR_XLEN_F64_Interrupt, but excluding X16-X31. +def CSR_XLEN_F64_Interrupt_RVE: CalleeSavedRegs<(sub CSR_XLEN_F64_Interrupt, + (sequence "X%u", 16, 31))>; diff --git a/llvm/lib/Target/RISCV/RISCVCodeGenPrepare.cpp b/llvm/lib/Target/RISCV/RISCVCodeGenPrepare.cpp index f9d8401bab7..53fcc527e61 100644 --- a/llvm/lib/Target/RISCV/RISCVCodeGenPrepare.cpp +++ b/llvm/lib/Target/RISCV/RISCVCodeGenPrepare.cpp @@ -18,7 +18,9 @@ #include "llvm/ADT/Statistic.h" #include "llvm/Analysis/ValueTracking.h" #include "llvm/CodeGen/TargetPassConfig.h" +#include "llvm/IR/IRBuilder.h" #include "llvm/IR/InstVisitor.h" +#include "llvm/IR/Intrinsics.h" #include "llvm/IR/PatternMatch.h" #include "llvm/InitializePasses.h" #include "llvm/Pass.h" @@ -51,6 +53,7 @@ public: bool visitInstruction(Instruction &I) { return false; } bool visitAnd(BinaryOperator &BO); + bool visitIntrinsicInst(IntrinsicInst &I); }; } // end anonymous namespace @@ -65,20 +68,13 @@ bool RISCVCodeGenPrepare::visitAnd(BinaryOperator &BO) { if (!BO.getType()->isIntegerTy(64)) return false; - auto canBeSignExtend = [](Instruction *I) { - if (isa(I)) - return true; - if (isa(I)) - return I->hasNonNeg(); - return false; - }; + using namespace PatternMatch; - // Left hand side should be a sext or zext nneg. - Instruction *LHS = dyn_cast(BO.getOperand(0)); - if (!LHS || !canBeSignExtend(LHS)) + // Left hand side should be a zext nneg. + Value *LHSSrc; + if (!match(BO.getOperand(0), m_NNegZExt(m_Value(LHSSrc)))) return false; - Value *LHSSrc = LHS->getOperand(0); if (!LHSSrc->getType()->isIntegerTy(32)) return false; @@ -98,7 +94,63 @@ bool RISCVCodeGenPrepare::visitAnd(BinaryOperator &BO) { // Sign extend the constant and replace the And operand. C = SignExtend64<32>(C); - BO.setOperand(1, ConstantInt::get(LHS->getType(), C)); + BO.setOperand(1, ConstantInt::get(RHS->getType(), C)); + + return true; +} + +// LLVM vector reduction intrinsics return a scalar result, but on RISC-V vector +// reduction instructions write the result in the first element of a vector +// register. So when a reduction in a loop uses a scalar phi, we end up with +// unnecessary scalar moves: +// +// loop: +// vfmv.s.f v10, fa0 +// vfredosum.vs v8, v8, v10 +// vfmv.f.s fa0, v8 +// +// This mainly affects ordered fadd reductions, since other types of reduction +// typically use element-wise vectorisation in the loop body. This tries to +// vectorize any scalar phis that feed into a fadd reduction: +// +// loop: +// %phi = phi [ ..., %entry ], [ %acc, %loop ] +// %acc = call float @llvm.vector.reduce.fadd.nxv4f32(float %phi, %vec) +// +// -> +// +// loop: +// %phi = phi [ ..., %entry ], [ %acc.vec, %loop ] +// %phi.scalar = extractelement %phi, i64 0 +// %acc = call float @llvm.vector.reduce.fadd.nxv4f32(float %x, %vec) +// %acc.vec = insertelement poison, float %acc.next, i64 0 +// +// Which eliminates the scalar -> vector -> scalar crossing during instruction +// selection. +bool RISCVCodeGenPrepare::visitIntrinsicInst(IntrinsicInst &I) { + if (I.getIntrinsicID() != Intrinsic::vector_reduce_fadd) + return false; + + auto *PHI = dyn_cast(I.getOperand(0)); + if (!PHI || !PHI->hasOneUse() || + !llvm::is_contained(PHI->incoming_values(), &I)) + return false; + + Type *VecTy = I.getOperand(1)->getType(); + IRBuilder<> Builder(PHI); + auto *VecPHI = Builder.CreatePHI(VecTy, PHI->getNumIncomingValues()); + + for (auto *BB : PHI->blocks()) { + Builder.SetInsertPoint(BB->getTerminator()); + Value *InsertElt = Builder.CreateInsertElement( + VecTy, PHI->getIncomingValueForBlock(BB), (uint64_t)0); + VecPHI->addIncoming(InsertElt, BB); + } + + Builder.SetInsertPoint(&I); + I.setOperand(0, Builder.CreateExtractElement(VecPHI, (uint64_t)0)); + + PHI->eraseFromParent(); return true; } diff --git a/llvm/lib/Target/RISCV/RISCVExpandPseudoInsts.cpp b/llvm/lib/Target/RISCV/RISCVExpandPseudoInsts.cpp index ed2b1ceb7d6..0a314fdd41c 100644 --- a/llvm/lib/Target/RISCV/RISCVExpandPseudoInsts.cpp +++ b/llvm/lib/Target/RISCV/RISCVExpandPseudoInsts.cpp @@ -423,6 +423,10 @@ private: bool expandLoadTLSGDAddress(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, MachineBasicBlock::iterator &NextMBBI); + bool expandLoadTLSDescAddress(MachineBasicBlock &MBB, + MachineBasicBlock::iterator MBBI, + MachineBasicBlock::iterator &NextMBBI); + #ifndef NDEBUG unsigned getInstSizeInBytes(const MachineFunction &MF) const { unsigned Size = 0; @@ -481,6 +485,8 @@ bool RISCVPreRAExpandPseudo::expandMI(MachineBasicBlock &MBB, return expandLoadTLSIEAddress(MBB, MBBI, NextMBBI); case RISCV::PseudoLA_TLS_GD: return expandLoadTLSGDAddress(MBB, MBBI, NextMBBI); + case RISCV::PseudoLA_TLSDESC: + return expandLoadTLSDescAddress(MBB, MBBI, NextMBBI); } return false; } @@ -547,6 +553,51 @@ bool RISCVPreRAExpandPseudo::expandLoadTLSGDAddress( RISCV::ADDI); } +bool RISCVPreRAExpandPseudo::expandLoadTLSDescAddress( + MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, + MachineBasicBlock::iterator &NextMBBI) { + MachineFunction *MF = MBB.getParent(); + MachineInstr &MI = *MBBI; + DebugLoc DL = MI.getDebugLoc(); + + const auto &STI = MF->getSubtarget(); + unsigned SecondOpcode = STI.is64Bit() ? RISCV::LD : RISCV::LW; + + Register FinalReg = MI.getOperand(0).getReg(); + Register DestReg = + MF->getRegInfo().createVirtualRegister(&RISCV::GPRRegClass); + Register ScratchReg = + MF->getRegInfo().createVirtualRegister(&RISCV::GPRRegClass); + + MachineOperand &Symbol = MI.getOperand(1); + Symbol.setTargetFlags(RISCVII::MO_TLSDESC_HI); + MCSymbol *AUIPCSymbol = MF->getContext().createNamedTempSymbol("tlsdesc_hi"); + + MachineInstr *MIAUIPC = + BuildMI(MBB, MBBI, DL, TII->get(RISCV::AUIPC), ScratchReg).add(Symbol); + MIAUIPC->setPreInstrSymbol(*MF, AUIPCSymbol); + + BuildMI(MBB, MBBI, DL, TII->get(SecondOpcode), DestReg) + .addReg(ScratchReg) + .addSym(AUIPCSymbol, RISCVII::MO_TLSDESC_LOAD_LO); + + BuildMI(MBB, MBBI, DL, TII->get(RISCV::ADDI), RISCV::X10) + .addReg(ScratchReg) + .addSym(AUIPCSymbol, RISCVII::MO_TLSDESC_ADD_LO); + + BuildMI(MBB, MBBI, DL, TII->get(RISCV::PseudoTLSDESCCall), RISCV::X5) + .addReg(DestReg) + .addImm(0) + .addSym(AUIPCSymbol, RISCVII::MO_TLSDESC_CALL); + + BuildMI(MBB, MBBI, DL, TII->get(RISCV::ADD), FinalReg) + .addReg(RISCV::X10) + .addReg(RISCV::X4); + + MI.eraseFromParent(); + return true; +} + } // end of anonymous namespace INITIALIZE_PASS(RISCVExpandPseudo, "riscv-expand-pseudo", diff --git a/llvm/lib/Target/RISCV/RISCVFeatures.td b/llvm/lib/Target/RISCV/RISCVFeatures.td index 279509575bb..3878be680c0 100644 --- a/llvm/lib/Target/RISCV/RISCVFeatures.td +++ b/llvm/lib/Target/RISCV/RISCVFeatures.td @@ -10,19 +10,130 @@ // RISC-V subtarget features and instruction predicates. //===----------------------------------------------------------------------===// +// Integer Extensions + +def FeatureStdExtI + : SubtargetFeature<"i", "HasStdExtI", "true", + "'I' (Base Integer Instruction Set)">; +def HasStdExtI : Predicate<"Subtarget->hasStdExtI()">, + AssemblerPredicate<(all_of FeatureStdExtI), + "'I' (Base Integer Instruction Set)">; +def FeatureStdExtZic64b + : SubtargetFeature<"zic64b", "HasStdExtZic64b", "true", + "'Zic64b' (Cache Block Size Is 64 Bytes)">; + +def FeatureStdExtZicbom + : SubtargetFeature<"zicbom", "HasStdExtZicbom", "true", + "'Zicbom' (Cache-Block Management Instructions)">; +def HasStdExtZicbom : Predicate<"Subtarget->hasStdExtZicbom()">, + AssemblerPredicate<(all_of FeatureStdExtZicbom), + "'Zicbom' (Cache-Block Management Instructions)">; + +def FeatureStdExtZicbop + : SubtargetFeature<"zicbop", "HasStdExtZicbop", "true", + "'Zicbop' (Cache-Block Prefetch Instructions)">; +def HasStdExtZicbop : Predicate<"Subtarget->hasStdExtZicbop()">, + AssemblerPredicate<(all_of FeatureStdExtZicbop), + "'Zicbop' (Cache-Block Prefetch Instructions)">; + +def FeatureStdExtZicboz + : SubtargetFeature<"zicboz", "HasStdExtZicboz", "true", + "'Zicboz' (Cache-Block Zero Instructions)">; +def HasStdExtZicboz : Predicate<"Subtarget->hasStdExtZicboz()">, + AssemblerPredicate<(all_of FeatureStdExtZicboz), + "'Zicboz' (Cache-Block Zero Instructions)">; + +def FeatureStdExtZiccamoa + : SubtargetFeature<"ziccamoa", "HasStdExtZiccamoa", "true", + "'Ziccamoa' (Main Memory Supports All Atomics in A)">; + +def FeatureStdExtZiccif + : SubtargetFeature<"ziccif", "HasStdExtZiccif", "true", + "'Ziccif' (Main Memory Supports Instruction Fetch with Atomicity Requirement)">; + +def FeatureStdExtZicclsm + : SubtargetFeature<"zicclsm", "HasStdExtZicclsm", "true", + "'Zicclsm' (Main Memory Supports Misaligned Loads/Stores)">; + +def FeatureStdExtZiccrse + : SubtargetFeature<"ziccrse", "HasStdExtZiccrse", "true", + "'Ziccrse' (Main Memory Supports Forward Progress on LR/SC Sequences)">; + def FeatureStdExtZicsr : SubtargetFeature<"zicsr", "HasStdExtZicsr", "true", "'zicsr' (CSRs)">; def HasStdExtZicsr : Predicate<"Subtarget->hasStdExtZicsr()">, - AssemblerPredicate<(all_of FeatureStdExtZicsr), - "'Zicsr' (CSRs)">; + AssemblerPredicate<(all_of FeatureStdExtZicsr), + "'Zicsr' (CSRs)">; + +def FeatureStdExtZicntr + : SubtargetFeature<"zicntr", "HasStdExtZicntr", "true", + "'Zicntr' (Base Counters and Timers)", + [FeatureStdExtZicsr]>; + +def FeatureStdExtZicond + : SubtargetFeature<"experimental-zicond", "HasStdExtZicond", "true", + "'Zicond' (Integer Conditional Operations)">; +def HasStdExtZicond : Predicate<"Subtarget->hasStdExtZicond()">, + AssemblerPredicate<(all_of FeatureStdExtZicond), + "'Zicond' (Integer Conditional Operations)">; + +def FeatureStdExtZifencei + : SubtargetFeature<"zifencei", "HasStdExtZifencei", "true", + "'Zifencei' (fence.i)">; +def HasStdExtZifencei : Predicate<"Subtarget->hasStdExtZifencei()">, + AssemblerPredicate<(all_of FeatureStdExtZifencei), + "'Zifencei' (fence.i)">; + +def FeatureStdExtZihintpause + : SubtargetFeature<"zihintpause", "HasStdExtZihintpause", "true", + "'Zihintpause' (Pause Hint)">; +def HasStdExtZihintpause : Predicate<"Subtarget->hasStdExtZihintpause()">, + AssemblerPredicate<(all_of FeatureStdExtZihintpause), + "'Zihintpause' (Pause Hint)">; + +def FeatureStdExtZihintntl + : SubtargetFeature<"zihintntl", "HasStdExtZihintntl", "true", + "'Zihintntl' (Non-Temporal Locality Hints)">; +def HasStdExtZihintntl : Predicate<"Subtarget->hasStdExtZihintntl()">, + AssemblerPredicate<(all_of FeatureStdExtZihintntl), + "'Zihintntl' (Non-Temporal Locality Hints)">; + +def FeatureStdExtZihpm + : SubtargetFeature<"zihpm", "HasStdExtZihpm", "true", + "'Zihpm' (Hardware Performance Counters)", + [FeatureStdExtZicsr]>; + +def FeatureStdExtZimop : SubtargetFeature<"experimental-zimop", "HasStdExtZimop", "true", + "'Zimop' (May-Be-Operations)">; +def HasStdExtZimop : Predicate<"Subtarget->hasStdExtZimop()">, + AssemblerPredicate<(all_of FeatureStdExtZimop), + "'Zimop' (May-Be-Operations)">; + +def FeatureStdExtZicfilp + : SubtargetFeature<"experimental-zicfilp", "HasStdExtZicfilp", "true", + "'Zicfilp' (Landing pad)">; +def HasStdExtZicfilp : Predicate<"Subtarget->hasStdExtZicfilp()">, + AssemblerPredicate<(all_of FeatureStdExtZicfilp), + "'Zicfilp' (Landing pad)">; + +def FeatureStdExtZicfiss + : SubtargetFeature<"experimental-zicfiss", "HasStdExtZicfiss", "true", + "'Zicfiss' (Shadow stack)", + [FeatureStdExtZicsr, FeatureStdExtZimop]>; +def HasStdExtZicfiss : Predicate<"Subtarget->hasStdExtZicfiss()">, + AssemblerPredicate<(all_of FeatureStdExtZicfiss), + "'Zicfiss' (Shadow stack)">; +def NoHasStdExtZicfiss : Predicate<"!Subtarget->hasStdExtZicfiss()">; + +// Multiply Extensions def FeatureStdExtM : SubtargetFeature<"m", "HasStdExtM", "true", "'M' (Integer Multiplication and Division)">; def HasStdExtM : Predicate<"Subtarget->hasStdExtM()">, - AssemblerPredicate<(all_of FeatureStdExtM), - "'M' (Integer Multiplication and Division)">; + AssemblerPredicate<(all_of FeatureStdExtM), + "'M' (Integer Multiplication and Division)">; def FeatureStdExtZmmul : SubtargetFeature<"zmmul", "HasStdExtZmmul", "true", @@ -30,197 +141,282 @@ def FeatureStdExtZmmul def HasStdExtMOrZmmul : Predicate<"Subtarget->hasStdExtM() || Subtarget->hasStdExtZmmul()">, - AssemblerPredicate<(any_of FeatureStdExtM, FeatureStdExtZmmul), - "'M' (Integer Multiplication and Division) or " - "'Zmmul' (Integer Multiplication)">; + AssemblerPredicate<(any_of FeatureStdExtM, FeatureStdExtZmmul), + "'M' (Integer Multiplication and Division) or " + "'Zmmul' (Integer Multiplication)">; + +// Atomic Extensions def FeatureStdExtA : SubtargetFeature<"a", "HasStdExtA", "true", "'A' (Atomic Instructions)">; def HasStdExtA : Predicate<"Subtarget->hasStdExtA()">, - AssemblerPredicate<(all_of FeatureStdExtA), - "'A' (Atomic Instructions)">; + AssemblerPredicate<(all_of FeatureStdExtA), + "'A' (Atomic Instructions)">; + +def FeatureStdExtZtso + : SubtargetFeature<"experimental-ztso", "HasStdExtZtso", "true", + "'Ztso' (Memory Model - Total Store Order)">; +def HasStdExtZtso : Predicate<"Subtarget->hasStdExtZtso()">, + AssemblerPredicate<(all_of FeatureStdExtZtso), + "'Ztso' (Memory Model - Total Store Order)">; +def NotHasStdExtZtso : Predicate<"!Subtarget->hasStdExtZtso()">; + +def FeatureStdExtZa64rs : SubtargetFeature<"za64rs", "HasStdExtZa64rs", "true", + "'Za64rs' (Reservation Set Size of at Most 64 Bytes)">; + +def FeatureStdExtZa128rs : SubtargetFeature<"za128rs", "HasStdExtZa128rs", "true", + "'Za128rs' (Reservation Set Size of at Most 128 Bytes)">; + +def FeatureStdExtZacas + : SubtargetFeature<"experimental-zacas", "HasStdExtZacas", "true", + "'Zacas' (Atomic Compare-And-Swap Instructions)">; +def HasStdExtZacas : Predicate<"Subtarget->hasStdExtZacas()">, + AssemblerPredicate<(all_of FeatureStdExtZacas), + "'Zacas' (Atomic Compare-And-Swap Instructions)">; +def NoStdExtZacas : Predicate<"!Subtarget->hasStdExtZacas()">; + +def FeatureStdExtZawrs : SubtargetFeature<"zawrs", "HasStdExtZawrs", "true", + "'Zawrs' (Wait on Reservation Set)">; +def HasStdExtZawrs : Predicate<"Subtarget->hasStdExtZawrs()">, + AssemblerPredicate<(all_of FeatureStdExtZawrs), + "'Zawrs' (Wait on Reservation Set)">; + +// Floating Point Extensions def FeatureStdExtF : SubtargetFeature<"f", "HasStdExtF", "true", "'F' (Single-Precision Floating-Point)", [FeatureStdExtZicsr]>; def HasStdExtF : Predicate<"Subtarget->hasStdExtF()">, - AssemblerPredicate<(all_of FeatureStdExtF), - "'F' (Single-Precision Floating-Point)">; + AssemblerPredicate<(all_of FeatureStdExtF), + "'F' (Single-Precision Floating-Point)">; def FeatureStdExtD : SubtargetFeature<"d", "HasStdExtD", "true", "'D' (Double-Precision Floating-Point)", [FeatureStdExtF]>; def HasStdExtD : Predicate<"Subtarget->hasStdExtD()">, - AssemblerPredicate<(all_of FeatureStdExtD), - "'D' (Double-Precision Floating-Point)">; - -def FeatureStdExtH - : SubtargetFeature<"h", "HasStdExtH", "true", - "'H' (Hypervisor)">; - -def HasStdExtH : Predicate<"Subtarget->hasStdExtH()">, - AssemblerPredicate<(all_of FeatureStdExtH), - "'H' (Hypervisor)">; - -def FeatureStdExtZihintpause - : SubtargetFeature<"zihintpause", "HasStdExtZihintpause", "true", - "'Zihintpause' (Pause Hint)">; -def HasStdExtZihintpause : Predicate<"Subtarget->hasStdExtZihintpause()">, - AssemblerPredicate<(all_of FeatureStdExtZihintpause), - "'Zihintpause' (Pause Hint)">; - -def FeatureStdExtZihintntl - : SubtargetFeature<"zihintntl", "HasStdExtZihintntl", "true", - "'Zihintntl' (Non-Temporal Locality Hints)">; -def HasStdExtZihintntl : Predicate<"Subtarget->hasStdExtZihintntl()">, - AssemblerPredicate<(all_of FeatureStdExtZihintntl), - "'Zihintntl' (Non-Temporal Locality Hints)">; - -def FeatureStdExtZifencei - : SubtargetFeature<"zifencei", "HasStdExtZifencei", "true", - "'Zifencei' (fence.i)">; -def HasStdExtZifencei : Predicate<"Subtarget->hasStdExtZifencei()">, - AssemblerPredicate<(all_of FeatureStdExtZifencei), - "'Zifencei' (fence.i)">; - -def FeatureStdExtZicntr - : SubtargetFeature<"zicntr", "HasStdExtZicntr", "true", - "'Zicntr' (Base Counters and Timers)", - [FeatureStdExtZicsr]>; - -def FeatureStdExtZihpm - : SubtargetFeature<"zihpm", "HasStdExtZihpm", "true", - "'Zihpm' (Hardware Performance Counters)", - [FeatureStdExtZicsr]>; + AssemblerPredicate<(all_of FeatureStdExtD), + "'D' (Double-Precision Floating-Point)">; def FeatureStdExtZfhmin : SubtargetFeature<"zfhmin", "HasStdExtZfhmin", "true", "'Zfhmin' (Half-Precision Floating-Point Minimal)", [FeatureStdExtF]>; def HasStdExtZfhmin : Predicate<"Subtarget->hasStdExtZfhmin()">, - AssemblerPredicate<(all_of FeatureStdExtZfhmin), - "'Zfhmin' (Half-Precision Floating-Point Minimal)">; + AssemblerPredicate<(all_of FeatureStdExtZfhmin), + "'Zfh' (Half-Precision Floating-Point) or " + "'Zfhmin' (Half-Precision Floating-Point Minimal)">; def FeatureStdExtZfh : SubtargetFeature<"zfh", "HasStdExtZfh", "true", "'Zfh' (Half-Precision Floating-Point)", [FeatureStdExtZfhmin]>; def HasStdExtZfh : Predicate<"Subtarget->hasStdExtZfh()">, - AssemblerPredicate<(all_of FeatureStdExtZfh), - "'Zfh' (Half-Precision Floating-Point)">; + AssemblerPredicate<(all_of FeatureStdExtZfh), + "'Zfh' (Half-Precision Floating-Point)">; def NoStdExtZfh : Predicate<"!Subtarget->hasStdExtZfh()">; -def HasStdExtZfhOrZfhmin - : Predicate<"Subtarget->hasStdExtZfhmin()">, - AssemblerPredicate<(all_of FeatureStdExtZfhmin), - "'Zfh' (Half-Precision Floating-Point) or " - "'Zfhmin' (Half-Precision Floating-Point Minimal)">; +def FeatureStdExtZfbfmin + : SubtargetFeature<"experimental-zfbfmin", "HasStdExtZfbfmin", "true", + "'Zfbfmin' (Scalar BF16 Converts)", + [FeatureStdExtF]>; +def HasStdExtZfbfmin : Predicate<"Subtarget->hasStdExtZfbfmin()">, + AssemblerPredicate<(all_of FeatureStdExtZfbfmin), + "'Zfbfmin' (Scalar BF16 Converts)">; -def FeatureStdExtZfinx - : SubtargetFeature<"zfinx", "HasStdExtZfinx", "true", - "'Zfinx' (Float in Integer)", - [FeatureStdExtZicsr]>; -def HasStdExtZfinx : Predicate<"Subtarget->hasStdExtZfinx()">, - AssemblerPredicate<(all_of FeatureStdExtZfinx), - "'Zfinx' (Float in Integer)">; - -def FeatureStdExtZdinx - : SubtargetFeature<"zdinx", "HasStdExtZdinx", "true", - "'Zdinx' (Double in Integer)", - [FeatureStdExtZfinx]>; -def HasStdExtZdinx : Predicate<"Subtarget->hasStdExtZdinx()">, - AssemblerPredicate<(all_of FeatureStdExtZdinx), - "'Zdinx' (Double in Integer)">; - -def FeatureStdExtZhinxmin - : SubtargetFeature<"zhinxmin", "HasStdExtZhinxmin", "true", - "'Zhinxmin' (Half Float in Integer Minimal)", - [FeatureStdExtZfinx]>; -def HasStdExtZhinxmin : Predicate<"Subtarget->hasStdExtZhinxmin()">, - AssemblerPredicate<(all_of FeatureStdExtZhinxmin), - "'Zhinxmin' (Half Float in Integer Minimal)">; - -def FeatureStdExtZhinx - : SubtargetFeature<"zhinx", "HasStdExtZhinx", "true", - "'Zhinx' (Half Float in Integer)", - [FeatureStdExtZhinxmin]>; -def HasStdExtZhinx : Predicate<"Subtarget->hasStdExtZhinx()">, - AssemblerPredicate<(all_of FeatureStdExtZhinx), - "'Zhinx' (Half Float in Integer)">; -def NoStdExtZhinx : Predicate<"!Subtarget->hasStdExtZhinx()">; - -def HasStdExtZhinxOrZhinxmin - : Predicate<"Subtarget->hasStdExtZhinxmin()">, - AssemblerPredicate<(all_of FeatureStdExtZhinxmin), - "'Zhinx' (Half Float in Integer) or " - "'Zhinxmin' (Half Float in Integer Minimal)">; +def HasHalfFPLoadStoreMove + : Predicate<"Subtarget->hasHalfFPLoadStoreMove()">, + AssemblerPredicate<(any_of FeatureStdExtZfh, FeatureStdExtZfhmin, + FeatureStdExtZfbfmin), + "'Zfh' (Half-Precision Floating-Point) or " + "'Zfhmin' (Half-Precision Floating-Point Minimal) or " + "'Zfbfmin' (Scalar BF16 Converts)">; def FeatureStdExtZfa : SubtargetFeature<"zfa", "HasStdExtZfa", "true", "'Zfa' (Additional Floating-Point)", [FeatureStdExtF]>; def HasStdExtZfa : Predicate<"Subtarget->hasStdExtZfa()">, - AssemblerPredicate<(all_of FeatureStdExtZfa), - "'Zfa' (Additional Floating-Point)">; + AssemblerPredicate<(all_of FeatureStdExtZfa), + "'Zfa' (Additional Floating-Point)">; + +def FeatureStdExtZfinx + : SubtargetFeature<"zfinx", "HasStdExtZfinx", "true", + "'Zfinx' (Float in Integer)", + [FeatureStdExtZicsr]>; +def HasStdExtZfinx : Predicate<"Subtarget->hasStdExtZfinx()">, + AssemblerPredicate<(all_of FeatureStdExtZfinx), + "'Zfinx' (Float in Integer)">; + +def FeatureStdExtZdinx + : SubtargetFeature<"zdinx", "HasStdExtZdinx", "true", + "'Zdinx' (Double in Integer)", + [FeatureStdExtZfinx]>; +def HasStdExtZdinx : Predicate<"Subtarget->hasStdExtZdinx()">, + AssemblerPredicate<(all_of FeatureStdExtZdinx), + "'Zdinx' (Double in Integer)">; + +def FeatureStdExtZhinxmin + : SubtargetFeature<"zhinxmin", "HasStdExtZhinxmin", "true", + "'Zhinxmin' (Half Float in Integer Minimal)", + [FeatureStdExtZfinx]>; +def HasStdExtZhinxmin : Predicate<"Subtarget->hasStdExtZhinxmin()">, + AssemblerPredicate<(all_of FeatureStdExtZhinxmin), + "'Zhinx' (Half Float in Integer) or " + "'Zhinxmin' (Half Float in Integer Minimal)">; + +def FeatureStdExtZhinx + : SubtargetFeature<"zhinx", "HasStdExtZhinx", "true", + "'Zhinx' (Half Float in Integer)", + [FeatureStdExtZhinxmin]>; +def HasStdExtZhinx : Predicate<"Subtarget->hasStdExtZhinx()">, + AssemblerPredicate<(all_of FeatureStdExtZhinx), + "'Zhinx' (Half Float in Integer)">; +def NoStdExtZhinx : Predicate<"!Subtarget->hasStdExtZhinx()">; + +// Compressed Extensions def FeatureStdExtC : SubtargetFeature<"c", "HasStdExtC", "true", "'C' (Compressed Instructions)">; def HasStdExtC : Predicate<"Subtarget->hasStdExtC()">, - AssemblerPredicate<(all_of FeatureStdExtC), - "'C' (Compressed Instructions)">; + AssemblerPredicate<(all_of FeatureStdExtC), + "'C' (Compressed Instructions)">; + +def FeatureNoRVCHints + : SubtargetFeature<"no-rvc-hints", "EnableRVCHintInstrs", "false", + "Disable RVC Hint Instructions.">; +def HasRVCHints : Predicate<"Subtarget->enableRVCHintInstrs()">, + AssemblerPredicate<(all_of(not FeatureNoRVCHints)), + "RVC Hint Instructions">; + +def FeatureStdExtZca + : SubtargetFeature<"zca", "HasStdExtZca", "true", + "'Zca' (part of the C extension, excluding compressed " + "floating point loads/stores)">; + +def HasStdExtCOrZca + : Predicate<"Subtarget->hasStdExtCOrZca()">, + AssemblerPredicate<(any_of FeatureStdExtC, FeatureStdExtZca), + "'C' (Compressed Instructions) or " + "'Zca' (part of the C extension, excluding " + "compressed floating point loads/stores)">; + +def FeatureStdExtZcb + : SubtargetFeature<"zcb", "HasStdExtZcb", "true", + "'Zcb' (Compressed basic bit manipulation instructions)", + [FeatureStdExtZca]>; +def HasStdExtZcb : Predicate<"Subtarget->hasStdExtZcb()">, + AssemblerPredicate<(all_of FeatureStdExtZcb), + "'Zcb' (Compressed basic bit manipulation instructions)">; + +def FeatureStdExtZcd + : SubtargetFeature<"zcd", "HasStdExtZcd", "true", + "'Zcd' (Compressed Double-Precision Floating-Point Instructions)", + [FeatureStdExtZca]>; + +def HasStdExtCOrZcd + : Predicate<"Subtarget->hasStdExtC() || Subtarget->hasStdExtZcd()">, + AssemblerPredicate<(any_of FeatureStdExtC, FeatureStdExtZcd), + "'C' (Compressed Instructions) or " + "'Zcd' (Compressed Double-Precision Floating-Point Instructions)">; + +def FeatureStdExtZcf + : SubtargetFeature<"zcf", "HasStdExtZcf", "true", + "'Zcf' (Compressed Single-Precision Floating-Point Instructions)", + [FeatureStdExtZca]>; + +def FeatureStdExtZcmp + : SubtargetFeature<"zcmp", "HasStdExtZcmp", "true", + "'Zcmp' (sequenced instuctions for code-size reduction)", + [FeatureStdExtZca]>; +def HasStdExtZcmp : Predicate<"Subtarget->hasStdExtZcmp() && !Subtarget->hasStdExtC()">, + AssemblerPredicate<(all_of FeatureStdExtZcmp), + "'Zcmp' (sequenced instuctions for code-size reduction)">; + +def FeatureStdExtZcmt + : SubtargetFeature<"zcmt", "HasStdExtZcmt", "true", + "'Zcmt' (table jump instuctions for code-size reduction)", + [FeatureStdExtZca, FeatureStdExtZicsr]>; +def HasStdExtZcmt : Predicate<"Subtarget->hasStdExtZcmt()">, + AssemblerPredicate<(all_of FeatureStdExtZcmt), + "'Zcmt' (table jump instuctions for code-size reduction)">; + +def FeatureStdExtZce + : SubtargetFeature<"zce", "HasStdExtZce", "true", + "'Zce' (Compressed extensions for microcontrollers)", + [FeatureStdExtZca, FeatureStdExtZcb, FeatureStdExtZcmp, + FeatureStdExtZcmt]>; + +def HasStdExtCOrZcfOrZce + : Predicate<"Subtarget->hasStdExtC() || Subtarget->hasStdExtZcf() " + "Subtarget->hasStdExtZce()">, + AssemblerPredicate<(any_of FeatureStdExtC, FeatureStdExtZcf, + FeatureStdExtZce), + "'C' (Compressed Instructions) or " + "'Zcf' (Compressed Single-Precision Floating-Point Instructions)">; + +def FeatureStdExtZcmop : SubtargetFeature<"experimental-zcmop", "HasStdExtZcmop", "true", + "'Zcmop' (Compressed May-Be-Operations)", + [FeatureStdExtZca]>; +def HasStdExtZcmop : Predicate<"Subtarget->hasStdExtZcmop()">, + AssemblerPredicate<(all_of FeatureStdExtZcmop), + "'Zcmop' (Compressed May-Be-Operations)">; + +// Bitmanip Extensions def FeatureStdExtZba : SubtargetFeature<"zba", "HasStdExtZba", "true", "'Zba' (Address Generation Instructions)">; def HasStdExtZba : Predicate<"Subtarget->hasStdExtZba()">, - AssemblerPredicate<(all_of FeatureStdExtZba), - "'Zba' (Address Generation Instructions)">; + AssemblerPredicate<(all_of FeatureStdExtZba), + "'Zba' (Address Generation Instructions)">; def NotHasStdExtZba : Predicate<"!Subtarget->hasStdExtZba()">; def FeatureStdExtZbb : SubtargetFeature<"zbb", "HasStdExtZbb", "true", "'Zbb' (Basic Bit-Manipulation)">; def HasStdExtZbb : Predicate<"Subtarget->hasStdExtZbb()">, - AssemblerPredicate<(all_of FeatureStdExtZbb), - "'Zbb' (Basic Bit-Manipulation)">; + AssemblerPredicate<(all_of FeatureStdExtZbb), + "'Zbb' (Basic Bit-Manipulation)">; def FeatureStdExtZbc : SubtargetFeature<"zbc", "HasStdExtZbc", "true", "'Zbc' (Carry-Less Multiplication)">; def HasStdExtZbc : Predicate<"Subtarget->hasStdExtZbc()">, - AssemblerPredicate<(all_of FeatureStdExtZbc), - "'Zbc' (Carry-Less Multiplication)">; + AssemblerPredicate<(all_of FeatureStdExtZbc), + "'Zbc' (Carry-Less Multiplication)">; def FeatureStdExtZbs : SubtargetFeature<"zbs", "HasStdExtZbs", "true", "'Zbs' (Single-Bit Instructions)">; def HasStdExtZbs : Predicate<"Subtarget->hasStdExtZbs()">, - AssemblerPredicate<(all_of FeatureStdExtZbs), - "'Zbs' (Single-Bit Instructions)">; + AssemblerPredicate<(all_of FeatureStdExtZbs), + "'Zbs' (Single-Bit Instructions)">; + +// Bitmanip Extensions for Cryptography Extensions def FeatureStdExtZbkb : SubtargetFeature<"zbkb", "HasStdExtZbkb", "true", "'Zbkb' (Bitmanip instructions for Cryptography)">; def HasStdExtZbkb : Predicate<"Subtarget->hasStdExtZbkb()">, - AssemblerPredicate<(all_of FeatureStdExtZbkb), - "'Zbkb' (Bitmanip instructions for Cryptography)">; + AssemblerPredicate<(all_of FeatureStdExtZbkb), + "'Zbkb' (Bitmanip instructions for Cryptography)">; def FeatureStdExtZbkx : SubtargetFeature<"zbkx", "HasStdExtZbkx", "true", "'Zbkx' (Crossbar permutation instructions)">; def HasStdExtZbkx : Predicate<"Subtarget->hasStdExtZbkx()">, - AssemblerPredicate<(all_of FeatureStdExtZbkx), - "'Zbkx' (Crossbar permutation instructions)">; + AssemblerPredicate<(all_of FeatureStdExtZbkx), + "'Zbkx' (Crossbar permutation instructions)">; def HasStdExtZbbOrZbkb : Predicate<"Subtarget->hasStdExtZbb() || Subtarget->hasStdExtZbkb()">, - AssemblerPredicate<(any_of FeatureStdExtZbb, FeatureStdExtZbkb), - "'Zbb' (Basic Bit-Manipulation) or " - "'Zbkb' (Bitmanip instructions for Cryptography)">; + AssemblerPredicate<(any_of FeatureStdExtZbb, FeatureStdExtZbkb), + "'Zbb' (Basic Bit-Manipulation) or " + "'Zbkb' (Bitmanip instructions for Cryptography)">; // The Carry-less multiply subextension for cryptography is a subset of basic // carry-less multiply subextension. The former should be enabled if the latter @@ -231,66 +427,67 @@ def FeatureStdExtZbkc "Cryptography)">; def HasStdExtZbkc : Predicate<"Subtarget->hasStdExtZbkc()">, - AssemblerPredicate<(all_of FeatureStdExtZbkc), - "'Zbkc' (Carry-less multiply instructions for Cryptography)">; + AssemblerPredicate<(all_of FeatureStdExtZbkc), + "'Zbkc' (Carry-less multiply instructions for Cryptography)">; def HasStdExtZbcOrZbkc : Predicate<"Subtarget->hasStdExtZbc() || Subtarget->hasStdExtZbkc()">, - AssemblerPredicate<(any_of FeatureStdExtZbc, FeatureStdExtZbkc), - "'Zbc' (Carry-Less Multiplication) or " - "'Zbkc' (Carry-less multiply instructions " - "for Cryptography)">; + AssemblerPredicate<(any_of FeatureStdExtZbc, FeatureStdExtZbkc), + "'Zbc' (Carry-Less Multiplication) or " + "'Zbkc' (Carry-less multiply instructions " + "for Cryptography)">; + +// Cryptography Extensions def FeatureStdExtZknd : SubtargetFeature<"zknd", "HasStdExtZknd", "true", "'Zknd' (NIST Suite: AES Decryption)">; def HasStdExtZknd : Predicate<"Subtarget->hasStdExtZknd()">, - AssemblerPredicate<(all_of FeatureStdExtZknd), - "'Zknd' (NIST Suite: AES Decryption)">; + AssemblerPredicate<(all_of FeatureStdExtZknd), + "'Zknd' (NIST Suite: AES Decryption)">; def FeatureStdExtZkne : SubtargetFeature<"zkne", "HasStdExtZkne", "true", "'Zkne' (NIST Suite: AES Encryption)">; def HasStdExtZkne : Predicate<"Subtarget->hasStdExtZkne()">, - AssemblerPredicate<(all_of FeatureStdExtZkne), - "'Zkne' (NIST Suite: AES Encryption)">; + AssemblerPredicate<(all_of FeatureStdExtZkne), + "'Zkne' (NIST Suite: AES Encryption)">; // Some instructions belong to both Zknd and Zkne subextensions. // They should be enabled if either has been specified. def HasStdExtZkndOrZkne : Predicate<"Subtarget->hasStdExtZknd() || Subtarget->hasStdExtZkne()">, - AssemblerPredicate<(any_of FeatureStdExtZknd, FeatureStdExtZkne), - "'Zknd' (NIST Suite: AES Decryption) or " - "'Zkne' (NIST Suite: AES Encryption)">; + AssemblerPredicate<(any_of FeatureStdExtZknd, FeatureStdExtZkne), + "'Zknd' (NIST Suite: AES Decryption) or " + "'Zkne' (NIST Suite: AES Encryption)">; def FeatureStdExtZknh : SubtargetFeature<"zknh", "HasStdExtZknh", "true", "'Zknh' (NIST Suite: Hash Function Instructions)">; def HasStdExtZknh : Predicate<"Subtarget->hasStdExtZknh()">, - AssemblerPredicate<(all_of FeatureStdExtZknh), - "'Zknh' (NIST Suite: Hash Function Instructions)">; + AssemblerPredicate<(all_of FeatureStdExtZknh), + "'Zknh' (NIST Suite: Hash Function Instructions)">; def FeatureStdExtZksed : SubtargetFeature<"zksed", "HasStdExtZksed", "true", "'Zksed' (ShangMi Suite: SM4 Block Cipher Instructions)">; def HasStdExtZksed : Predicate<"Subtarget->hasStdExtZksed()">, - AssemblerPredicate<(all_of FeatureStdExtZksed), - "'Zksed' (ShangMi Suite: SM4 Block Cipher Instructions)">; + AssemblerPredicate<(all_of FeatureStdExtZksed), + "'Zksed' (ShangMi Suite: SM4 Block Cipher Instructions)">; def FeatureStdExtZksh : SubtargetFeature<"zksh", "HasStdExtZksh", "true", "'Zksh' (ShangMi Suite: SM3 Hash Function Instructions)">; def HasStdExtZksh : Predicate<"Subtarget->hasStdExtZksh()">, - AssemblerPredicate<(all_of FeatureStdExtZksh), - "'Zksh' (ShangMi Suite: SM3 Hash Function " - "Instructions)">; + AssemblerPredicate<(all_of FeatureStdExtZksh), + "'Zksh' (ShangMi Suite: SM3 Hash Function Instructions)">; def FeatureStdExtZkr : SubtargetFeature<"zkr", "HasStdExtZkr", "true", "'Zkr' (Entropy Source Extension)">; def HasStdExtZkr : Predicate<"Subtarget->hasStdExtZkr()">, - AssemblerPredicate<(all_of FeatureStdExtZkr), - "'Zkr' (Entropy Source Extension)">; + AssemblerPredicate<(all_of FeatureStdExtZkr), + "'Zkr' (Entropy Source Extension)">; def FeatureStdExtZkn : SubtargetFeature<"zkn", "HasStdExtZkn", "true", @@ -322,78 +519,7 @@ def FeatureStdExtZk FeatureStdExtZkr, FeatureStdExtZkt]>; -def FeatureStdExtZca - : SubtargetFeature<"zca", "HasStdExtZca", "true", - "'Zca' (part of the C extension, excluding compressed " - "floating point loads/stores)">; - -def HasStdExtCOrZca - : Predicate<"Subtarget->hasStdExtCOrZca()">, - AssemblerPredicate<(any_of FeatureStdExtC, FeatureStdExtZca), - "'C' (Compressed Instructions) or " - "'Zca' (part of the C extension, excluding " - "compressed floating point loads/stores)">; - -def FeatureStdExtZcb - : SubtargetFeature<"zcb", "HasStdExtZcb", "true", - "'Zcb' (Compressed basic bit manipulation instructions)", - [FeatureStdExtZca]>; -def HasStdExtZcb : Predicate<"Subtarget->hasStdExtZcb()">, - AssemblerPredicate<(all_of FeatureStdExtZcb), - "'Zcb' (Compressed basic bit manipulation instructions)">; - -def FeatureStdExtZcd - : SubtargetFeature<"zcd", "HasStdExtZcd", "true", - "'Zcd' (Compressed Double-Precision Floating-Point Instructions)", - [FeatureStdExtZca]>; - -def HasStdExtCOrZcd - : Predicate<"Subtarget->hasStdExtC() || Subtarget->hasStdExtZcd()">, - AssemblerPredicate<(any_of FeatureStdExtC, FeatureStdExtZcd), - "'C' (Compressed Instructions) or " - "'Zcd' (Compressed Double-Precision Floating-Point Instructions)">; - -def FeatureStdExtZcf - : SubtargetFeature<"zcf", "HasStdExtZcf", "true", - "'Zcf' (Compressed Single-Precision Floating-Point Instructions)", - [FeatureStdExtZca]>; - -def FeatureStdExtZcmp - : SubtargetFeature<"zcmp", "HasStdExtZcmp", "true", - "'Zcmp' (sequenced instuctions for code-size reduction)", - [FeatureStdExtZca]>; -def HasStdExtZcmp : Predicate<"Subtarget->hasStdExtZcmp() && !Subtarget->hasStdExtC()">, - AssemblerPredicate<(all_of FeatureStdExtZcmp), - "'Zcmp' (sequenced instuctions for code-size reduction)">; - -def FeatureStdExtZcmt - : SubtargetFeature<"zcmt", "HasStdExtZcmt", "true", - "'Zcmt' (table jump instuctions for code-size reduction)", - [FeatureStdExtZca, FeatureStdExtZicsr]>; -def HasStdExtZcmt : Predicate<"Subtarget->hasStdExtZcmt()">, - AssemblerPredicate<(all_of FeatureStdExtZcmt), - "'Zcmt' (table jump instuctions for code-size reduction)">; - -def FeatureStdExtZce - : SubtargetFeature<"zce", "HasStdExtZce", "true", - "'Zce' (Compressed extensions for microcontrollers)", - [FeatureStdExtZca, FeatureStdExtZcb, FeatureStdExtZcmp, - FeatureStdExtZcmt]>; - -def HasStdExtCOrZcfOrZce - : Predicate<"Subtarget->hasStdExtC() || Subtarget->hasStdExtZcf() " - "Subtarget->hasStdExtZce()">, - AssemblerPredicate<(any_of FeatureStdExtC, FeatureStdExtZcf, - FeatureStdExtZce), - "'C' (Compressed Instructions) or " - "'Zcf' (Compressed Single-Precision Floating-Point Instructions)">; - -def FeatureNoRVCHints - : SubtargetFeature<"no-rvc-hints", "EnableRVCHintInstrs", "false", - "Disable RVC Hint Instructions.">; -def HasRVCHints : Predicate<"Subtarget->enableRVCHintInstrs()">, - AssemblerPredicate<(all_of(not FeatureNoRVCHints)), - "RVC Hint Instructions">; +// Vector Extensions def FeatureStdExtZvl32b : SubtargetFeature<"zvl32b", "ZvlLen", "32", "'Zvl' (Minimum Vector Length) 32">; @@ -441,6 +567,151 @@ def FeatureStdExtV "'V' (Vector Extension for Application Processors)", [FeatureStdExtZvl128b, FeatureStdExtZve64d]>; +def FeatureStdExtZvfbfmin + : SubtargetFeature<"experimental-zvfbfmin", "HasStdExtZvfbfmin", "true", + "'Zvbfmin' (Vector BF16 Converts)", + [FeatureStdExtZve32f]>; +def HasStdExtZvfbfmin : Predicate<"Subtarget->hasStdExtZvfbfmin()">, + AssemblerPredicate<(all_of FeatureStdExtZvfbfmin), + "'Zvfbfmin' (Vector BF16 Converts)">; + +def FeatureStdExtZvfbfwma + : SubtargetFeature<"experimental-zvfbfwma", "HasStdExtZvfbfwma", "true", + "'Zvfbfwma' (Vector BF16 widening mul-add)", + [FeatureStdExtZvfbfmin, FeatureStdExtZfbfmin]>; +def HasStdExtZvfbfwma : Predicate<"Subtarget->hasStdExtZvfbfwma()">, + AssemblerPredicate<(all_of FeatureStdExtZvfbfwma), + "'Zvfbfwma' (Vector BF16 widening mul-add)">; + +def FeatureStdExtZvfhmin + : SubtargetFeature<"zvfhmin", "HasStdExtZvfhmin", "true", + "'Zvfhmin' (Vector Half-Precision Floating-Point Minimal)", + [FeatureStdExtZve32f]>; + +def FeatureStdExtZvfh + : SubtargetFeature<"zvfh", "HasStdExtZvfh", "true", + "'Zvfh' (Vector Half-Precision Floating-Point)", + [FeatureStdExtZvfhmin, FeatureStdExtZfhmin]>; + +def HasStdExtZfhOrZvfh + : Predicate<"Subtarget->hasStdExtZfh() || Subtarget->hasStdExtZvfh()">, + AssemblerPredicate<(any_of FeatureStdExtZfh, FeatureStdExtZvfh), + "'Zfh' (Half-Precision Floating-Point) or " + "'Zvfh' (Vector Half-Precision Floating-Point)">; + +// Vector Cryptography and Bitmanip Extensions + +def FeatureStdExtZvkb + : SubtargetFeature<"zvkb", "HasStdExtZvkb", "true", + "'Zvkb' (Vector Bit-manipulation used in Cryptography)">; +def HasStdExtZvkb : Predicate<"Subtarget->hasStdExtZvkb()">, + AssemblerPredicate<(all_of FeatureStdExtZvkb), + "'Zvkb' (Vector Bit-manipulation used in Cryptography)">; + +def FeatureStdExtZvbb + : SubtargetFeature<"zvbb", "HasStdExtZvbb", "true", + "'Zvbb' (Vector basic bit-manipulation instructions)", + [FeatureStdExtZvkb]>; +def HasStdExtZvbb : Predicate<"Subtarget->hasStdExtZvbb()">, + AssemblerPredicate<(all_of FeatureStdExtZvbb), + "'Zvbb' (Vector basic bit-manipulation instructions)">; + +def FeatureStdExtZvbc + : SubtargetFeature<"zvbc", "HasStdExtZvbc", "true", + "'Zvbc' (Vector Carryless Multiplication)">; +def HasStdExtZvbc : Predicate<"Subtarget->hasStdExtZvbc()">, + AssemblerPredicate<(all_of FeatureStdExtZvbc), + "'Zvbc' (Vector Carryless Multiplication)">; + +def FeatureStdExtZvkg + : SubtargetFeature<"zvkg", "HasStdExtZvkg", "true", + "'Zvkg' (Vector GCM instructions for Cryptography)">; +def HasStdExtZvkg : Predicate<"Subtarget->hasStdExtZvkg()">, + AssemblerPredicate<(all_of FeatureStdExtZvkg), + "'Zvkg' (Vector GCM instructions for Cryptography)">; + +def FeatureStdExtZvkned + : SubtargetFeature<"zvkned", "HasStdExtZvkned", "true", + "'Zvkned' (Vector AES Encryption & Decryption (Single Round))">; +def HasStdExtZvkned : Predicate<"Subtarget->hasStdExtZvkned()">, + AssemblerPredicate<(all_of FeatureStdExtZvkned), + "'Zvkned' (Vector AES Encryption & Decryption (Single Round))">; + +def FeatureStdExtZvknha + : SubtargetFeature<"zvknha", "HasStdExtZvknha", "true", + "'Zvknha' (Vector SHA-2 (SHA-256 only))">; +def HasStdExtZvknha : Predicate<"Subtarget->hasStdExtZvknha()">, + AssemblerPredicate<(all_of FeatureStdExtZvknha), + "'Zvknha' (Vector SHA-2 (SHA-256 only))">; + +def FeatureStdExtZvknhb + : SubtargetFeature<"zvknhb", "HasStdExtZvknhb", "true", + "'Zvknhb' (Vector SHA-2 (SHA-256 and SHA-512))", + [FeatureStdExtZve64x]>; +def HasStdExtZvknhb : Predicate<"Subtarget->hasStdExtZvknhb()">, + AssemblerPredicate<(all_of FeatureStdExtZvknhb), + "'Zvknhb' (Vector SHA-2 (SHA-256 and SHA-512))">; + +def HasStdExtZvknhaOrZvknhb : Predicate<"Subtarget->hasStdExtZvknha() || Subtarget->hasStdExtZvknhb()">, + AssemblerPredicate<(any_of FeatureStdExtZvknha, FeatureStdExtZvknhb), + "'Zvknha' or 'Zvknhb' (Vector SHA-2)">; + +def FeatureStdExtZvksed + : SubtargetFeature<"zvksed", "HasStdExtZvksed", "true", + "'Zvksed' (SM4 Block Cipher Instructions)">; +def HasStdExtZvksed : Predicate<"Subtarget->hasStdExtZvksed()">, + AssemblerPredicate<(all_of FeatureStdExtZvksed), + "'Zvksed' (SM4 Block Cipher Instructions)">; + +def FeatureStdExtZvksh + : SubtargetFeature<"zvksh", "HasStdExtZvksh", "true", + "'Zvksh' (SM3 Hash Function Instructions)">; +def HasStdExtZvksh : Predicate<"Subtarget->hasStdExtZvksh()">, + AssemblerPredicate<(all_of FeatureStdExtZvksh), + "'Zvksh' (SM3 Hash Function Instructions)">; + +def FeatureStdExtZvkt + : SubtargetFeature<"zvkt", "HasStdExtZvkt", "true", + "'Zvkt' (Vector Data-Independent Execution Latency)">; + +// Zvk short-hand extensions + +def FeatureStdExtZvkn + : SubtargetFeature<"zvkn", "HasStdExtZvkn", "true", + "'Zvkn' (shorthand for 'Zvkned', 'Zvknhb', 'Zvkb', and " + "'Zvkt')", + [FeatureStdExtZvkned, FeatureStdExtZvknhb, + FeatureStdExtZvkb, FeatureStdExtZvkt]>; + +def FeatureStdExtZvknc + : SubtargetFeature<"zvknc", "HasStdExtZvknc", "true", + "'Zvknc' (shorthand for 'Zvknc' and 'Zvbc')", + [FeatureStdExtZvkn, FeatureStdExtZvbc]>; + +def FeatureStdExtZvkng + : SubtargetFeature<"zvkng", "HasStdExtZvkng", "true", + "'zvkng' (shorthand for 'Zvkn' and 'Zvkg')", + [FeatureStdExtZvkn, FeatureStdExtZvkg]>; + +def FeatureStdExtZvks + : SubtargetFeature<"zvks", "HasStdExtZvks", "true", + "'Zvks' (shorthand for 'Zvksed', 'Zvksh', 'Zvkb', and " + "'Zvkt')", + [FeatureStdExtZvksed, FeatureStdExtZvksh, + FeatureStdExtZvkb, FeatureStdExtZvkt]>; + +def FeatureStdExtZvksc + : SubtargetFeature<"zvksc", "HasStdExtZvksc", "true", + "'Zvksc' (shorthand for 'Zvks' and 'Zvbc')", + [FeatureStdExtZvks, FeatureStdExtZvbc]>; + +def FeatureStdExtZvksg + : SubtargetFeature<"zvksg", "HasStdExtZvksg", "true", + "'Zvksg' (shorthand for 'Zvks' and 'Zvkg')", + [FeatureStdExtZvks, FeatureStdExtZvkg]>; + +// Vector instruction predicates + def HasVInstructions : Predicate<"Subtarget->hasVInstructions()">, AssemblerPredicate< (any_of FeatureStdExtZve32x), @@ -457,79 +728,48 @@ def HasVInstructionsAnyF : Predicate<"Subtarget->hasVInstructionsAnyF()">, "'V' (Vector Extension for Application Processors), 'Zve32f' " "(Vector Extensions for Embedded Processors)">; -def HasVInstructionsF64 : Predicate<"Subtarget->hasVInstructionsF64()">; - -def HasVInstructionsFullMultiply : Predicate<"Subtarget->hasVInstructionsFullMultiply()">; - -def FeatureStdExtZfbfmin - : SubtargetFeature<"experimental-zfbfmin", "HasStdExtZfbfmin", "true", - "'Zfbfmin' (Scalar BF16 Converts)", - [FeatureStdExtF]>; -def HasStdExtZfbfmin : Predicate<"Subtarget->hasStdExtZfbfmin()">, - AssemblerPredicate<(all_of FeatureStdExtZfbfmin), - "'Zfbfmin' (Scalar BF16 Converts)">; - -def FeatureStdExtZvfbfmin - : SubtargetFeature<"experimental-zvfbfmin", "HasStdExtZvfbfmin", "true", - "'Zvbfmin' (Vector BF16 Converts)", - [FeatureStdExtZve32f]>; -def HasStdExtZvfbfmin : Predicate<"Subtarget->hasStdExtZvfbfmin()">, - AssemblerPredicate<(all_of FeatureStdExtZvfbfmin), - "'Zvfbfmin' (Vector BF16 Converts)">; - -def FeatureStdExtZvfbfwma - : SubtargetFeature<"experimental-zvfbfwma", "HasStdExtZvfbfwma", "true", - "'Zvfbfwma' (Vector BF16 widening mul-add)", - [FeatureStdExtZvfbfmin, FeatureStdExtZfbfmin]>; -def HasStdExtZvfbfwma : Predicate<"Subtarget->hasStdExtZvfbfwma()">, - AssemblerPredicate<(all_of FeatureStdExtZvfbfwma), - "'Zvfbfwma' (Vector BF16 widening mul-add)">; - -def HasVInstructionsBF16 : Predicate<"Subtarget->hasVInstructionsBF16()">; - -def FeatureStdExtZvfhmin - : SubtargetFeature<"zvfhmin", "HasStdExtZvfhmin", "true", - "'Zvfhmin' (Vector Half-Precision Floating-Point Minimal)", - [FeatureStdExtZve32f]>; - -def FeatureStdExtZvfh - : SubtargetFeature<"zvfh", "HasStdExtZvfh", "true", - "'Zvfh' (Vector Half-Precision Floating-Point)", - [FeatureStdExtZvfhmin, FeatureStdExtZfhmin]>; - -def HasVInstructionsF16 : Predicate<"Subtarget->hasVInstructionsF16()">; - def HasVInstructionsF16Minimal : Predicate<"Subtarget->hasVInstructionsF16Minimal()">, AssemblerPredicate<(any_of FeatureStdExtZvfhmin, FeatureStdExtZvfh), "'Zvfhmin' (Vector Half-Precision Floating-Point Minimal) or " "'Zvfh' (Vector Half-Precision Floating-Point)">; -def HasStdExtZfhOrZvfh - : Predicate<"Subtarget->hasStdExtZfh() || Subtarget->hasStdExtZvfh()">, - AssemblerPredicate<(any_of FeatureStdExtZfh, FeatureStdExtZvfh), - "'Zfh' (Half-Precision Floating-Point) or " - "'Zvfh' (Vector Half-Precision Floating-Point)">; +def HasVInstructionsBF16 : Predicate<"Subtarget->hasVInstructionsBF16()">; +def HasVInstructionsF16 : Predicate<"Subtarget->hasVInstructionsF16()">; +def HasVInstructionsF64 : Predicate<"Subtarget->hasVInstructionsF64()">; -def FeatureStdExtZicbom - : SubtargetFeature<"zicbom", "HasStdExtZicbom", "true", - "'Zicbom' (Cache-Block Management Instructions)">; -def HasStdExtZicbom : Predicate<"Subtarget->hasStdExtZicbom()">, - AssemblerPredicate<(all_of FeatureStdExtZicbom), - "'Zicbom' (Cache-Block Management Instructions)">; +def HasVInstructionsFullMultiply : Predicate<"Subtarget->hasVInstructionsFullMultiply()">; -def FeatureStdExtZicboz - : SubtargetFeature<"zicboz", "HasStdExtZicboz", "true", - "'Zicboz' (Cache-Block Zero Instructions)">; -def HasStdExtZicboz : Predicate<"Subtarget->hasStdExtZicboz()">, - AssemblerPredicate<(all_of FeatureStdExtZicboz), - "'Zicboz' (Cache-Block Zero Instructions)">; +// Hypervisor Extensions -def FeatureStdExtZicbop - : SubtargetFeature<"zicbop", "HasStdExtZicbop", "true", - "'Zicbop' (Cache-Block Prefetch Instructions)">; -def HasStdExtZicbop : Predicate<"Subtarget->hasStdExtZicbop()">, - AssemblerPredicate<(all_of FeatureStdExtZicbop), - "'Zicbop' (Cache-Block Prefetch Instructions)">; +def FeatureStdExtH + : SubtargetFeature<"h", "HasStdExtH", "true", + "'H' (Hypervisor)">; + +def HasStdExtH : Predicate<"Subtarget->hasStdExtH()">, + AssemblerPredicate<(all_of FeatureStdExtH), + "'H' (Hypervisor)">; + +// Supervisor extensions + +def FeatureStdExtSmaia + : SubtargetFeature<"smaia", "HasStdExtSmaia", "true", + "'Smaia' (Advanced Interrupt Architecture Machine " + "Level)", []>; +def FeatureStdExtSsaia + : SubtargetFeature<"ssaia", "HasStdExtSsaia", "true", + "'Ssaia' (Advanced Interrupt Architecture Supervisor " + "Level)", []>; + +def FeatureStdExtSmepmp + : SubtargetFeature<"smepmp", "HasStdExtSmepmp", "true", + "'Smepmp' (Enhanced Physical Memory Protection)", []>; + +def FeatureStdExtSvinval + : SubtargetFeature<"svinval", "HasStdExtSvinval", "true", + "'Svinval' (Fine-Grained Address-Translation Cache Invalidation)">; +def HasStdExtSvinval : Predicate<"Subtarget->hasStdExtSvinval()">, + AssemblerPredicate<(all_of FeatureStdExtSvinval), + "'Svinval' (Fine-Grained Address-Translation Cache Invalidation)">; def FeatureStdExtSvnapot : SubtargetFeature<"svnapot", "HasStdExtSvnapot", "true", @@ -539,385 +779,203 @@ def FeatureStdExtSvpbmt : SubtargetFeature<"svpbmt", "HasStdExtSvpbmt", "true", "'Svpbmt' (Page-Based Memory Types)">; -def FeatureStdExtSvinval - : SubtargetFeature<"svinval", "HasStdExtSvinval", "true", - "'Svinval' (Fine-Grained Address-Translation Cache Invalidation)">; -def HasStdExtSvinval : Predicate<"Subtarget->hasStdExtSvinval()">, - AssemblerPredicate<(all_of FeatureStdExtSvinval), - "'Svinval' (Fine-Grained Address-Translation Cache Invalidation)">; - -def FeatureStdExtZtso - : SubtargetFeature<"experimental-ztso", "HasStdExtZtso", "true", - "'Ztso' (Memory Model - Total Store Order)">; -def HasStdExtZtso : Predicate<"Subtarget->hasStdExtZtso()">, - AssemblerPredicate<(all_of FeatureStdExtZtso), - "'Ztso' (Memory Model - Total Store Order)">; -def NotHasStdExtZtso : Predicate<"!Subtarget->hasStdExtZtso()">; - -def FeatureStdExtZawrs : SubtargetFeature<"zawrs", "HasStdExtZawrs", "true", - "'Zawrs' (Wait on Reservation Set)">; -def HasStdExtZawrs : Predicate<"Subtarget->hasStdExtZawrs()">, - AssemblerPredicate<(all_of FeatureStdExtZawrs), - "'Zawrs' (Wait on Reservation Set)">; - -def FeatureStdExtZvkb - : SubtargetFeature<"zvkb", "HasStdExtZvkb", "true", - "'Zvkb' (Vector Bit-manipulation used in Cryptography)">; -def HasStdExtZvkb : Predicate<"Subtarget->hasStdExtZvkb()">, - AssemblerPredicate<(all_of FeatureStdExtZvkb), - "'Zvkb' (Vector Bit-manipulation used in Cryptography)">; - -def FeatureStdExtZvbb - : SubtargetFeature<"zvbb", "HasStdExtZvbb", "true", - "'Zvbb' (Vector basic bit-manipulation instructions.)", - [FeatureStdExtZvkb]>; -def HasStdExtZvbb : Predicate<"Subtarget->hasStdExtZvbb()">, - AssemblerPredicate<(all_of FeatureStdExtZvbb), - "'Zvbb' (Vector basic bit-manipulation instructions.)">; - -def FeatureStdExtZvbc - : SubtargetFeature<"zvbc", "HasStdExtZvbc", "true", - "'Zvbc' (Vector Carryless Multiplication)">; -def HasStdExtZvbc : Predicate<"Subtarget->hasStdExtZvbc()">, - AssemblerPredicate<(all_of FeatureStdExtZvbc), - "'Zvbc' (Vector Carryless Multiplication)">; - -def FeatureStdExtZvkg - : SubtargetFeature<"zvkg", "HasStdExtZvkg", "true", - "'Zvkg' (Vector GCM instructions for Cryptography)">; -def HasStdExtZvkg : Predicate<"Subtarget->hasStdExtZvkg()">, - AssemblerPredicate<(all_of FeatureStdExtZvkg), - "'Zvkg' (Vector GCM instructions for Cryptography)">; - -def FeatureStdExtZvkned - : SubtargetFeature<"zvkned", "HasStdExtZvkned", "true", - "'Zvkned' (Vector AES Encryption & Decryption (Single Round))">; -def HasStdExtZvkned : Predicate<"Subtarget->hasStdExtZvkned()">, - AssemblerPredicate<(all_of FeatureStdExtZvkned), - "'Zvkned' (Vector AES Encryption & Decryption (Single Round))">; - -def FeatureStdExtZvknha - : SubtargetFeature<"zvknha", "HasStdExtZvknha", "true", - "'Zvknha' (Vector SHA-2 (SHA-256 only))">; -def HasStdExtZvknha : Predicate<"Subtarget->hasStdExtZvknha()">, - AssemblerPredicate<(all_of FeatureStdExtZvknha), - "'Zvknha' (Vector SHA-2 (SHA-256 only))">; - -def FeatureStdExtZvknhb - : SubtargetFeature<"zvknhb", "HasStdExtZvknhb", "true", - "'Zvknhb' (Vector SHA-2 (SHA-256 and SHA-512))", - [FeatureStdExtZve64x]>; -def HasStdExtZvknhb : Predicate<"Subtarget->hasStdExtZvknhb()">, - AssemblerPredicate<(all_of FeatureStdExtZvknhb), - "'Zvknhb' (Vector SHA-2 (SHA-256 and SHA-512))">; - -def HasStdExtZvknhaOrZvknhb : Predicate<"Subtarget->hasStdExtZvknha() || Subtarget->hasStdExtZvknhb()">, - AssemblerPredicate<(any_of FeatureStdExtZvknha, FeatureStdExtZvknhb), - "'Zvknha' or 'Zvknhb' (Vector SHA-2)">; - -def FeatureStdExtZvksed - : SubtargetFeature<"zvksed", "HasStdExtZvksed", "true", - "'Zvksed' (SM4 Block Cipher Instructions)">; -def HasStdExtZvksed : Predicate<"Subtarget->hasStdExtZvksed()">, - AssemblerPredicate<(all_of FeatureStdExtZvksed), - "'Zvksed' (SM4 Block Cipher Instructions)">; - -def FeatureStdExtZvksh - : SubtargetFeature<"zvksh", "HasStdExtZvksh", "true", - "'Zvksh' (SM3 Hash Function Instructions)">; -def HasStdExtZvksh : Predicate<"Subtarget->hasStdExtZvksh()">, - AssemblerPredicate<(all_of FeatureStdExtZvksh), - "'Zvksh' (SM3 Hash Function Instructions)">; - -def FeatureStdExtZvkt - : SubtargetFeature<"zvkt", "HasStdExtZvkt", "true", - "'Zvkt' (Vector Data-Independent Execution Latency)">; - -// Zvk short-hand extensions - -def FeatureStdExtZvkn - : SubtargetFeature<"zvkn", "HasStdExtZvkn", "true", - "This extension is shorthand for the following set of " - "other extensions: Zvkned, Zvknhb, Zvkb and Zvkt.", - [FeatureStdExtZvkned, FeatureStdExtZvknhb, - FeatureStdExtZvkb, FeatureStdExtZvkt]>; - -def FeatureStdExtZvknc - : SubtargetFeature<"zvknc", "HasStdExtZvknc", "true", - "This extension is shorthand for the following set of " - "other extensions: Zvkn and Zvbc.", - [FeatureStdExtZvkn, FeatureStdExtZvbc]>; - -def FeatureStdExtZvkng - : SubtargetFeature<"zvkng", "HasStdExtZvkng", "true", - "This extension is shorthand for the following set of " - "other extensions: Zvkn and Zvkg.", - [FeatureStdExtZvkn, FeatureStdExtZvkg]>; - -def FeatureStdExtZvks - : SubtargetFeature<"zvks", "HasStdExtZvks", "true", - "This extension is shorthand for the following set of " - "other extensions: Zvksed, Zvksh, Zvkb and Zvkt.", - [FeatureStdExtZvksed, FeatureStdExtZvksh, - FeatureStdExtZvkb, FeatureStdExtZvkt]>; - -def FeatureStdExtZvksc - : SubtargetFeature<"zvksc", "HasStdExtZvksc", "true", - "This extension is shorthand for the following set of " - "other extensions: Zvks and Zvbc.", - [FeatureStdExtZvks, FeatureStdExtZvbc]>; - -def FeatureStdExtZvksg - : SubtargetFeature<"zvksg", "HasStdExtZvksg", "true", - "This extension is shorthand for the following set of " - "other extensions: Zvks and Zvkg.", - [FeatureStdExtZvks, FeatureStdExtZvkg]>; - -def FeatureStdExtZicfilp - : SubtargetFeature<"experimental-zicfilp", "HasStdExtZicfilp", "true", - "'Zicfilp' (Landing pad)">; -def HasStdExtZicfilp : Predicate<"Subtarget->hasStdExtZicfilp()">, - AssemblerPredicate<(all_of FeatureStdExtZicfilp), - "'Zicfilp' (Landing pad)">; - -def FeatureStdExtZicond - : SubtargetFeature<"experimental-zicond", "HasStdExtZicond", "true", - "'Zicond' (Integer Conditional Operations)">; -def HasStdExtZicond : Predicate<"Subtarget->hasStdExtZicond()">, - AssemblerPredicate<(all_of FeatureStdExtZicond), - "'Zicond' (Integer Conditional Operations)">; - -def FeatureStdExtZimop : SubtargetFeature<"experimental-zimop", "HasStdExtZimop", "true", - "'Zimop' (May-Be-Operations)">; -def HasStdExtZimop : Predicate<"Subtarget->hasStdExtZimop()">, - AssemblerPredicate<(all_of FeatureStdExtZimop), - "'Zimop' (May-Be-Operations)">; - -def FeatureStdExtZcmop : SubtargetFeature<"experimental-zcmop", "HasStdExtZcmop", "true", - "'Zcmop' (Compressed May-Be-Operations)", - [FeatureStdExtZca]>; -def HasStdExtZcmop : Predicate<"Subtarget->hasStdExtZcmop()">, - AssemblerPredicate<(all_of FeatureStdExtZcmop), - "'Zcmop' (Compressed May-Be-Operations)">; - -def FeatureStdExtZicfiss - : SubtargetFeature<"experimental-zicfiss", "HasStdExtZicfiss", "true", - "'Zicfiss' (Shadow stack)", - [FeatureStdExtZicsr, FeatureStdExtZimop]>; -def HasStdExtZicfiss : Predicate<"Subtarget->hasStdExtZicfiss()">, - AssemblerPredicate<(all_of FeatureStdExtZicfiss), - "'Zicfiss' (Shadow stack)">; -def NoHasStdExtZicfiss : Predicate<"!Subtarget->hasStdExtZicfiss()">; - -def FeatureStdExtSmaia - : SubtargetFeature<"smaia", "HasStdExtSmaia", "true", - "'Smaia' (Smaia encompasses all added CSRs and all " - "modifications to interrupt response behavior that the " - "AIA specifies for a hart, over all privilege levels.)", - []>; - -def FeatureStdExtSsaia - : SubtargetFeature<"ssaia", "HasStdExtSsaia", "true", - "'Ssaia' (Ssaia is essentially the same as Smaia except " - "excluding the machine-level CSRs and behavior not " - "directly visible to supervisor level.)", []>; - -def HasHalfFPLoadStoreMove - : Predicate<"Subtarget->hasHalfFPLoadStoreMove()">, - AssemblerPredicate<(any_of FeatureStdExtZfh, FeatureStdExtZfhmin, - FeatureStdExtZfbfmin), - "'Zfh' (Half-Precision Floating-Point) or " - "'Zfhmin' (Half-Precision Floating-Point Minimal) or " - "'Zfbfmin' (Scalar BF16 Converts)">; - -def FeatureStdExtZacas - : SubtargetFeature<"experimental-zacas", "HasStdExtZacas", "true", - "'Zacas' (Atomic Compare-And-Swap Instructions)">; -def HasStdExtZacas : Predicate<"Subtarget->hasStdExtZacas()">, - AssemblerPredicate<(all_of FeatureStdExtZacas), - "'Zacas' (Atomic Compare-And-Swap Instructions)">; -def NoStdExtZacas : Predicate<"!Subtarget->hasStdExtZacas()">; - //===----------------------------------------------------------------------===// // Vendor extensions //===----------------------------------------------------------------------===// +// Ventana Extenions + def FeatureVendorXVentanaCondOps : SubtargetFeature<"xventanacondops", "HasVendorXVentanaCondOps", "true", "'XVentanaCondOps' (Ventana Conditional Ops)">; def HasVendorXVentanaCondOps : Predicate<"Subtarget->hasVendorXVentanaCondOps()">, - AssemblerPredicate<(all_of FeatureVendorXVentanaCondOps), - "'XVentanaCondOps' (Ventana Conditional Ops)">; + AssemblerPredicate<(all_of FeatureVendorXVentanaCondOps), + "'XVentanaCondOps' (Ventana Conditional Ops)">; + +// T-Head Extensions def FeatureVendorXTHeadBa : SubtargetFeature<"xtheadba", "HasVendorXTHeadBa", "true", "'xtheadba' (T-Head address calculation instructions)">; def HasVendorXTHeadBa : Predicate<"Subtarget->hasVendorXTHeadBa()">, - AssemblerPredicate<(all_of FeatureVendorXTHeadBa), - "'xtheadba' (T-Head address calculation instructions)">; + AssemblerPredicate<(all_of FeatureVendorXTHeadBa), + "'xtheadba' (T-Head address calculation instructions)">; def FeatureVendorXTHeadBb : SubtargetFeature<"xtheadbb", "HasVendorXTHeadBb", "true", "'xtheadbb' (T-Head basic bit-manipulation instructions)">; def HasVendorXTHeadBb : Predicate<"Subtarget->hasVendorXTHeadBb()">, - AssemblerPredicate<(all_of FeatureVendorXTHeadBb), - "'xtheadbb' (T-Head basic bit-manipulation instructions)">; + AssemblerPredicate<(all_of FeatureVendorXTHeadBb), + "'xtheadbb' (T-Head basic bit-manipulation instructions)">; def FeatureVendorXTHeadBs : SubtargetFeature<"xtheadbs", "HasVendorXTHeadBs", "true", "'xtheadbs' (T-Head single-bit instructions)">; def HasVendorXTHeadBs : Predicate<"Subtarget->hasVendorXTHeadBs()">, - AssemblerPredicate<(all_of FeatureVendorXTHeadBs), - "'xtheadbs' (T-Head single-bit instructions)">; + AssemblerPredicate<(all_of FeatureVendorXTHeadBs), + "'xtheadbs' (T-Head single-bit instructions)">; def FeatureVendorXTHeadCondMov : SubtargetFeature<"xtheadcondmov", "HasVendorXTHeadCondMov", "true", "'xtheadcondmov' (T-Head conditional move instructions)">; def HasVendorXTHeadCondMov : Predicate<"Subtarget->hasVendorXTHeadCondMov()">, - AssemblerPredicate<(all_of FeatureVendorXTHeadCondMov), - "'xtheadcondmov' (T-Head conditional move instructions)">; + AssemblerPredicate<(all_of FeatureVendorXTHeadCondMov), + "'xtheadcondmov' (T-Head conditional move instructions)">; def FeatureVendorXTHeadCmo : SubtargetFeature<"xtheadcmo", "HasVendorXTHeadCmo", "true", "'xtheadcmo' (T-Head cache management instructions)">; def HasVendorXTHeadCmo : Predicate<"Subtarget->hasVendorXTHeadCmo()">, - AssemblerPredicate<(all_of FeatureVendorXTHeadCmo), - "'xtheadcmo' (T-Head cache management instructions)">; + AssemblerPredicate<(all_of FeatureVendorXTHeadCmo), + "'xtheadcmo' (T-Head cache management instructions)">; def FeatureVendorXTHeadFMemIdx : SubtargetFeature<"xtheadfmemidx", "HasVendorXTHeadFMemIdx", "true", "'xtheadfmemidx' (T-Head FP Indexed Memory Operations)", [FeatureStdExtF]>; def HasVendorXTHeadFMemIdx : Predicate<"Subtarget->hasVendorXTHeadFMemIdx()">, - AssemblerPredicate<(all_of FeatureVendorXTHeadFMemIdx), - "'xtheadfmemidx' (T-Head FP Indexed Memory Operations)">; + AssemblerPredicate<(all_of FeatureVendorXTHeadFMemIdx), + "'xtheadfmemidx' (T-Head FP Indexed Memory Operations)">; def FeatureVendorXTHeadMac : SubtargetFeature<"xtheadmac", "HasVendorXTHeadMac", "true", "'xtheadmac' (T-Head Multiply-Accumulate Instructions)">; def HasVendorXTHeadMac : Predicate<"Subtarget->hasVendorXTHeadMac()">, - AssemblerPredicate<(all_of FeatureVendorXTHeadMac), - "'xtheadmac' (T-Head Multiply-Accumulate Instructions)">; + AssemblerPredicate<(all_of FeatureVendorXTHeadMac), + "'xtheadmac' (T-Head Multiply-Accumulate Instructions)">; def FeatureVendorXTHeadMemIdx : SubtargetFeature<"xtheadmemidx", "HasVendorXTHeadMemIdx", "true", "'xtheadmemidx' (T-Head Indexed Memory Operations)">; def HasVendorXTHeadMemIdx : Predicate<"Subtarget->hasVendorXTHeadMemIdx()">, - AssemblerPredicate<(all_of FeatureVendorXTHeadMemIdx), - "'xtheadmemidx' (T-Head Indexed Memory Operations)">; + AssemblerPredicate<(all_of FeatureVendorXTHeadMemIdx), + "'xtheadmemidx' (T-Head Indexed Memory Operations)">; def FeatureVendorXTHeadMemPair : SubtargetFeature<"xtheadmempair", "HasVendorXTHeadMemPair", "true", "'xtheadmempair' (T-Head two-GPR Memory Operations)">; def HasVendorXTHeadMemPair : Predicate<"Subtarget->hasVendorXTHeadMemPair()">, - AssemblerPredicate<(all_of FeatureVendorXTHeadMemPair), - "'xtheadmempair' (T-Head two-GPR Memory Operations)">; + AssemblerPredicate<(all_of FeatureVendorXTHeadMemPair), + "'xtheadmempair' (T-Head two-GPR Memory Operations)">; def FeatureVendorXTHeadSync : SubtargetFeature<"xtheadsync", "HasVendorXTHeadSync", "true", "'xtheadsync' (T-Head multicore synchronization instructions)">; def HasVendorXTHeadSync : Predicate<"Subtarget->hasVendorXTHeadSync()">, - AssemblerPredicate<(all_of FeatureVendorXTHeadSync), - "'xtheadsync' (T-Head multicore synchronization instructions)">; + AssemblerPredicate<(all_of FeatureVendorXTHeadSync), + "'xtheadsync' (T-Head multicore synchronization instructions)">; def FeatureVendorXTHeadVdot : SubtargetFeature<"xtheadvdot", "HasVendorXTHeadVdot", "true", "'xtheadvdot' (T-Head Vector Extensions for Dot)", [FeatureStdExtV]>; def HasVendorXTHeadVdot : Predicate<"Subtarget->hasVendorXTHeadVdot()">, - AssemblerPredicate<(all_of FeatureVendorXTHeadVdot), - "'xtheadvdot' (T-Head Vector Extensions for Dot)">; + AssemblerPredicate<(all_of FeatureVendorXTHeadVdot), + "'xtheadvdot' (T-Head Vector Extensions for Dot)">; + +// SiFive Extensions def FeatureVendorXSfvcp : SubtargetFeature<"xsfvcp", "HasVendorXSfvcp", "true", "'XSfvcp' (SiFive Custom Vector Coprocessor Interface Instructions)", [FeatureStdExtZve32x]>; def HasVendorXSfvcp : Predicate<"Subtarget->hasVendorXSfvcp()">, - AssemblerPredicate<(all_of FeatureVendorXSfvcp), - "'XSfvcp' (SiFive Custom Vector Coprocessor Interface Instructions)">; + AssemblerPredicate<(all_of FeatureVendorXSfvcp), + "'XSfvcp' (SiFive Custom Vector Coprocessor Interface Instructions)">; def FeatureVendorXSfvqmaccdod : SubtargetFeature<"xsfvqmaccdod", "HasVendorXSfvqmaccdod", "true", "'XSfvqmaccdod' (SiFive Int8 Matrix Multiplication Instructions (2-by-8 and 8-by-2))", [FeatureStdExtZve32x]>; -def HasVendorXSfvqmaccdod : Predicate<"Subtarget->hasVendorXSfvqmaccdod()">, - AssemblerPredicate<(all_of FeatureVendorXSfvqmaccdod), +def HasVendorXSfvqmaccdod + : Predicate<"Subtarget->hasVendorXSfvqmaccdod()">, + AssemblerPredicate<(all_of FeatureVendorXSfvqmaccdod), "'XSfvqmaccdod' (SiFive Int8 Matrix Multiplication Instructions (2-by-8 and 8-by-2))">; def FeatureVendorXSfvqmaccqoq : SubtargetFeature<"xsfvqmaccqoq", "HasVendorXSfvqmaccqoq", "true", "'XSfvqmaccqoq' (SiFive Int8 Matrix Multiplication Instructions (4-by-8 and 8-by-4))", [FeatureStdExtZve32x]>; -def HasVendorXSfvqmaccqoq : Predicate<"Subtarget->hasVendorXSfvqmaccqoq()">, - AssemblerPredicate<(all_of FeatureVendorXSfvqmaccqoq), +def HasVendorXSfvqmaccqoq + : Predicate<"Subtarget->hasVendorXSfvqmaccqoq()">, + AssemblerPredicate<(all_of FeatureVendorXSfvqmaccqoq), "'XSfvqmaccqoq' (SiFive Int8 Matrix Multiplication Instructions (4-by-8 and 8-by-4))">; def FeatureVendorXSfvfwmaccqqq : SubtargetFeature<"xsfvfwmaccqqq", "HasVendorXSfvfwmaccqqq", "true", "'XSfvfwmaccqqq' (SiFive Matrix Multiply Accumulate Instruction and 4-by-4))", [FeatureStdExtZve32f, FeatureStdExtZvfbfmin]>; -def HasVendorXSfvfwmaccqqq : Predicate<"Subtarget->hasVendorXSfvfwmaccqqq()">, - AssemblerPredicate<(all_of FeatureVendorXSfvfwmaccqqq), +def HasVendorXSfvfwmaccqqq + : Predicate<"Subtarget->hasVendorXSfvfwmaccqqq()">, + AssemblerPredicate<(all_of FeatureVendorXSfvfwmaccqqq), "'XSfvfwmaccqqq' (SiFive Matrix Multiply Accumulate Instruction and 4-by-4))">; def FeatureVendorXSfvfnrclipxfqf : SubtargetFeature<"xsfvfnrclipxfqf", "HasVendorXSfvfnrclipxfqf", "true", "'XSfvfnrclipxfqf' (SiFive FP32-to-int8 Ranged Clip Instructions)", [FeatureStdExtZve32f]>; -def HasVendorXSfvfnrclipxfqf : Predicate<"Subtarget->hasVendorXSfvfnrclipxfqf()">, - AssemblerPredicate<(all_of FeatureVendorXSfvfnrclipxfqf), - "'XSfvfnrclipxfqf' (SiFive FP32-to-int8 Ranged Clip Instructions)">; +def HasVendorXSfvfnrclipxfqf + : Predicate<"Subtarget->hasVendorXSfvfnrclipxfqf()">, + AssemblerPredicate<(all_of FeatureVendorXSfvfnrclipxfqf), + "'XSfvfnrclipxfqf' (SiFive FP32-to-int8 Ranged Clip Instructions)">; + +// Core-V Extensions + def FeatureVendorXCVelw : SubtargetFeature<"xcvelw", "HasVendorXCVelw", "true", "'XCVelw' (CORE-V Event Load Word)">; def HasVendorXCVelw : Predicate<"Subtarget->hasVendorXCVelw()">, - AssemblerPredicate<(any_of FeatureVendorXCVelw), - "'XCVelw' (CORE-V Event Load Word)">; + AssemblerPredicate<(any_of FeatureVendorXCVelw), + "'XCVelw' (CORE-V Event Load Word)">; def FeatureVendorXCVbitmanip : SubtargetFeature<"xcvbitmanip", "HasVendorXCVbitmanip", "true", "'XCVbitmanip' (CORE-V Bit Manipulation)">; -def HasVendorXCVbitmanip : Predicate<"Subtarget->hasVendorXCVbitmanip()">, - AssemblerPredicate<(all_of FeatureVendorXCVbitmanip), - "'XCVbitmanip' (CORE-V Bit Manipulation)">; +def HasVendorXCVbitmanip + : Predicate<"Subtarget->hasVendorXCVbitmanip()">, + AssemblerPredicate<(all_of FeatureVendorXCVbitmanip), + "'XCVbitmanip' (CORE-V Bit Manipulation)">; def FeatureVendorXCVmac : SubtargetFeature<"xcvmac", "HasVendorXCVmac", "true", "'XCVmac' (CORE-V Multiply-Accumulate)">; -def HasVendorXCVmac : Predicate<"Subtarget->hasVendorXCVmac()">, - AssemblerPredicate<(all_of FeatureVendorXCVmac), - "'XCVmac' (CORE-V Multiply-Accumulate)">; +def HasVendorXCVmac + : Predicate<"Subtarget->hasVendorXCVmac()">, + AssemblerPredicate<(all_of FeatureVendorXCVmac), + "'XCVmac' (CORE-V Multiply-Accumulate)">; def FeatureVendorXCVmem : SubtargetFeature<"xcvmem", "HasVendorXCVmem", "true", "'XCVmem' (CORE-V Post-incrementing Load & Store)">; def HasVendorXCVmem : Predicate<"Subtarget->hasVendorXCVmem()">, - AssemblerPredicate<(any_of FeatureVendorXCVmem), - "'XCVmem' (CORE-V Post-incrementing Load & Store)">; + AssemblerPredicate<(any_of FeatureVendorXCVmem), + "'XCVmem' (CORE-V Post-incrementing Load & Store)">; def FeatureVendorXCValu : SubtargetFeature<"xcvalu", "HasVendorXCValu", "true", "'XCValu' (CORE-V ALU Operations)">; -def HasVendorXCValu : Predicate<"Subtarget->hasVendorXCValu()">, - AssemblerPredicate<(all_of FeatureVendorXCValu), - "'XCValu' (CORE-V ALU Operations)">; +def HasVendorXCValu + : Predicate<"Subtarget->hasVendorXCValu()">, + AssemblerPredicate<(all_of FeatureVendorXCValu), + "'XCValu' (CORE-V ALU Operations)">; def FeatureVendorXCVsimd : SubtargetFeature<"xcvsimd", "HasVendorXCvsimd", "true", "'XCVsimd' (CORE-V SIMD ALU)">; def HasVendorXCVsimd : Predicate<"Subtarget->hasVendorXCVsimd()">, - AssemblerPredicate<(any_of FeatureVendorXCVsimd), - "'XCVsimd' (CORE-V SIMD ALU)">; + AssemblerPredicate<(any_of FeatureVendorXCVsimd), + "'XCVsimd' (CORE-V SIMD ALU)">; def FeatureVendorXCVbi : SubtargetFeature<"xcvbi", "HasVendorXCVbi", "true", "'XCVbi' (CORE-V Immediate Branching)">; -def HasVendorXCVbi : Predicate<"Subtarget->hasVendorXCVbi()">, - AssemblerPredicate<(all_of FeatureVendorXCVbi), - "'XCVbi' (CORE-V Immediate Branching)">; +def HasVendorXCVbi + : Predicate<"Subtarget->hasVendorXCVbi()">, + AssemblerPredicate<(all_of FeatureVendorXCVbi), + "'XCVbi' (CORE-V Immediate Branching)">; //===----------------------------------------------------------------------===// // LLVM specific features and extensions @@ -930,11 +988,11 @@ def Feature32Bit def Feature64Bit : SubtargetFeature<"64bit", "IsRV64", "true", "Implements RV64">; def IsRV64 : Predicate<"Subtarget->is64Bit()">, - AssemblerPredicate<(all_of Feature64Bit), - "RV64I Base Instruction Set">; + AssemblerPredicate<(all_of Feature64Bit), + "RV64I Base Instruction Set">; def IsRV32 : Predicate<"!Subtarget->is64Bit()">, - AssemblerPredicate<(all_of (not Feature64Bit)), - "RV32I Base Instruction Set">; + AssemblerPredicate<(all_of (not Feature64Bit)), + "RV32I Base Instruction Set">; defvar RV32 = DefaultMode; def RV64 : HwMode<"+64bit", [IsRV64]>; @@ -943,7 +1001,7 @@ def FeatureRVE : SubtargetFeature<"e", "IsRVE", "true", "Implements RV{32,64}E (provides 16 rather than 32 GPRs)">; def IsRVE : Predicate<"Subtarget->isRVE()">, - AssemblerPredicate<(all_of FeatureRVE)>; + AssemblerPredicate<(all_of FeatureRVE)>; def FeatureRelax : SubtargetFeature<"relax", "EnableLinkerRelax", "true", diff --git a/llvm/lib/Target/RISCV/RISCVFrameLowering.cpp b/llvm/lib/Target/RISCV/RISCVFrameLowering.cpp index 8dfea6d3862..d793c0b7377 100644 --- a/llvm/lib/Target/RISCV/RISCVFrameLowering.cpp +++ b/llvm/lib/Target/RISCV/RISCVFrameLowering.cpp @@ -27,6 +27,21 @@ using namespace llvm; +static Align getABIStackAlignment(RISCVABI::ABI ABI) { + if (ABI == RISCVABI::ABI_ILP32E) + return Align(4); + if (ABI == RISCVABI::ABI_LP64E) + return Align(8); + return Align(16); +} + +RISCVFrameLowering::RISCVFrameLowering(const RISCVSubtarget &STI) + : TargetFrameLowering(StackGrowsDown, + getABIStackAlignment(STI.getTargetABI()), + /*LocalAreaOffset=*/0, + /*TransientStackAlignment=*/Align(16)), + STI(STI) {} + static const Register AllPopRegs[] = { RISCV::X1, RISCV::X8, RISCV::X9, RISCV::X18, RISCV::X19, RISCV::X20, RISCV::X21, RISCV::X22, RISCV::X23, RISCV::X24, @@ -497,9 +512,11 @@ void RISCVFrameLowering::emitPrologue(MachineFunction &MF, // The following calculates the correct offset knowing the number of callee // saved registers spilt by the two methods. if (int LibCallRegs = getLibCallID(MF, MFI.getCalleeSavedInfo()) + 1) { - // Calculate the size of the frame managed by the libcall. The libcalls are - // implemented such that the stack will always be 16 byte aligned. - unsigned LibCallFrameSize = alignTo((STI.getXLen() / 8) * LibCallRegs, 16); + // Calculate the size of the frame managed by the libcall. The stack + // alignment of these libcalls should be the same as how we set it in + // getABIStackAlignment. + unsigned LibCallFrameSize = + alignTo((STI.getXLen() / 8) * LibCallRegs, getStackAlign()); RVFI->setLibCallStackSize(LibCallFrameSize); } @@ -974,6 +991,7 @@ void RISCVFrameLowering::determineCalleeSaves(MachineFunction &MF, // unconditionally save all Caller-saved registers and // all FP registers, regardless whether they are used. MachineFrameInfo &MFI = MF.getFrameInfo(); + auto &Subtarget = MF.getSubtarget(); if (MF.getFunction().hasFnAttribute("interrupt") && MFI.hasCalls()) { @@ -985,9 +1003,20 @@ void RISCVFrameLowering::determineCalleeSaves(MachineFunction &MF, }; for (auto Reg : CSRegs) - SavedRegs.set(Reg); + // Only save x0-x15 for RVE. + if (Reg < RISCV::X16 || !Subtarget.isRVE()) + SavedRegs.set(Reg); - if (MF.getSubtarget().hasStdExtF()) { + // According to psABI, if ilp32e/lp64e ABIs are used with an ISA that + // has any of the registers x16-x31 and f0-f31, then these registers are + // considered temporaries, so we should also save x16-x31 here. + if (STI.getTargetABI() == RISCVABI::ABI_ILP32E || + STI.getTargetABI() == RISCVABI::ABI_LP64E) { + for (MCPhysReg Reg = RISCV::X16; Reg <= RISCV::X31; Reg++) + SavedRegs.set(Reg); + } + + if (Subtarget.hasStdExtF()) { // If interrupt is enabled, this list contains all FP registers. const MCPhysReg * Regs = MF.getRegInfo().getCalleeSavedRegs(); diff --git a/llvm/lib/Target/RISCV/RISCVFrameLowering.h b/llvm/lib/Target/RISCV/RISCVFrameLowering.h index 9bc100981f2..5c1c7317d24 100644 --- a/llvm/lib/Target/RISCV/RISCVFrameLowering.h +++ b/llvm/lib/Target/RISCV/RISCVFrameLowering.h @@ -21,12 +21,7 @@ class RISCVSubtarget; class RISCVFrameLowering : public TargetFrameLowering { public: - explicit RISCVFrameLowering(const RISCVSubtarget &STI) - : TargetFrameLowering(StackGrowsDown, - /*StackAlignment=*/Align(16), - /*LocalAreaOffset=*/0, - /*TransientStackAlignment=*/Align(16)), - STI(STI) {} + explicit RISCVFrameLowering(const RISCVSubtarget &STI); void emitPrologue(MachineFunction &MF, MachineBasicBlock &MBB) const override; void emitEpilogue(MachineFunction &MF, MachineBasicBlock &MBB) const override; diff --git a/llvm/lib/Target/RISCV/RISCVGatherScatterLowering.cpp b/llvm/lib/Target/RISCV/RISCVGatherScatterLowering.cpp index 1129206800a..1dcb83a6078 100644 --- a/llvm/lib/Target/RISCV/RISCVGatherScatterLowering.cpp +++ b/llvm/lib/Target/RISCV/RISCVGatherScatterLowering.cpp @@ -136,10 +136,15 @@ static std::pair matchStridedStart(Value *Start, // multipled. auto *BO = dyn_cast(Start); if (!BO || (BO->getOpcode() != Instruction::Add && + BO->getOpcode() != Instruction::Or && BO->getOpcode() != Instruction::Shl && BO->getOpcode() != Instruction::Mul)) return std::make_pair(nullptr, nullptr); + if (BO->getOpcode() == Instruction::Or && + !cast(BO)->isDisjoint()) + return std::make_pair(nullptr, nullptr); + // Look for an operand that is splatted. unsigned OtherIndex = 0; Value *Splat = getSplatValue(BO->getOperand(1)); @@ -163,6 +168,10 @@ static std::pair matchStridedStart(Value *Start, switch (BO->getOpcode()) { default: llvm_unreachable("Unexpected opcode"); + case Instruction::Or: + // TODO: We'd be better off creating disjoint or here, but we don't yet + // have an IRBuilder API for that. + [[fallthrough]]; case Instruction::Add: Start = Builder.CreateAdd(Start, Splat); break; @@ -241,7 +250,7 @@ bool RISCVGatherScatterLowering::matchStridedRecurrence(Value *Index, Loop *L, return false; case Instruction::Or: // We need to be able to treat Or as Add. - if (!haveNoCommonBitsSet(BO->getOperand(0), BO->getOperand(1), *DL)) + if (!cast(BO)->isDisjoint()) return false; break; case Instruction::Add: diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp index cb9ffabc412..47c6cd6e548 100644 --- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp +++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp @@ -83,9 +83,6 @@ RISCVTargetLowering::RISCVTargetLowering(const TargetMachine &TM, const RISCVSubtarget &STI) : TargetLowering(TM), Subtarget(STI) { - if (Subtarget.isRVE()) - report_fatal_error("Codegen not yet implemented for RVE"); - RISCVABI::ABI ABI = Subtarget.getTargetABI(); assert(ABI != RISCVABI::ABI_Unknown && "Improperly initialised target ABI"); @@ -107,6 +104,8 @@ RISCVTargetLowering::RISCVTargetLowering(const TargetMachine &TM, default: report_fatal_error("Don't know how to lower this ABI"); case RISCVABI::ABI_ILP32: + case RISCVABI::ABI_ILP32E: + case RISCVABI::ABI_LP64E: case RISCVABI::ABI_ILP32F: case RISCVABI::ABI_ILP32D: case RISCVABI::ABI_LP64: @@ -688,7 +687,8 @@ RISCVTargetLowering::RISCVTargetLowering(const TargetMachine &TM, ISD::VP_FCEIL, ISD::VP_FFLOOR, ISD::VP_FROUND, ISD::VP_FROUNDEVEN, ISD::VP_FCOPYSIGN, ISD::VP_FROUNDTOZERO, ISD::VP_FRINT, ISD::VP_FNEARBYINT, ISD::VP_IS_FPCLASS, - ISD::EXPERIMENTAL_VP_REVERSE, ISD::EXPERIMENTAL_VP_SPLICE}; + ISD::VP_FMINIMUM, ISD::VP_FMAXIMUM, ISD::EXPERIMENTAL_VP_REVERSE, + ISD::EXPERIMENTAL_VP_SPLICE}; static const unsigned IntegerVecReduceOps[] = { ISD::VECREDUCE_ADD, ISD::VECREDUCE_AND, ISD::VECREDUCE_OR, @@ -928,7 +928,8 @@ RISCVTargetLowering::RISCVTargetLowering(const TargetMachine &TM, ISD::VP_FMINNUM, ISD::VP_FMAXNUM, ISD::VP_FCEIL, ISD::VP_FFLOOR, ISD::VP_FROUND, ISD::VP_FROUNDEVEN, ISD::VP_FCOPYSIGN, ISD::VP_FROUNDTOZERO, ISD::VP_FRINT, - ISD::VP_FNEARBYINT, ISD::VP_SETCC}; + ISD::VP_FNEARBYINT, ISD::VP_SETCC, ISD::VP_FMINIMUM, + ISD::VP_FMAXIMUM}; // Sets common operation actions on RVV floating-point vector types. const auto SetCommonVFPActions = [&](MVT VT) { @@ -1374,8 +1375,8 @@ RISCVTargetLowering::RISCVTargetLowering(const TargetMachine &TM, setPrefLoopAlignment(Subtarget.getPrefLoopAlignment()); setTargetDAGCombine({ISD::INTRINSIC_VOID, ISD::INTRINSIC_W_CHAIN, - ISD::INTRINSIC_WO_CHAIN, ISD::ADD, ISD::SUB, ISD::AND, - ISD::OR, ISD::XOR, ISD::SETCC, ISD::SELECT}); + ISD::INTRINSIC_WO_CHAIN, ISD::ADD, ISD::SUB, ISD::MUL, + ISD::AND, ISD::OR, ISD::XOR, ISD::SETCC, ISD::SELECT}); if (Subtarget.is64Bit()) setTargetDAGCombine(ISD::SRA); @@ -2593,11 +2594,12 @@ static SDValue getAllOnesMask(MVT VecVT, SDValue VL, const SDLoc &DL, static SDValue getVLOp(uint64_t NumElts, MVT ContainerVT, const SDLoc &DL, SelectionDAG &DAG, const RISCVSubtarget &Subtarget) { - // If we know the exact VLEN, our VL is exactly equal to VLMAX, and - // we can't encode the AVL as an immediate, use the VLMAX encoding. + // If we know the exact VLEN, and our VL is exactly equal to VLMAX, + // canonicalize the representation. InsertVSETVLI will pick the immediate + // encoding later if profitable. const auto [MinVLMAX, MaxVLMAX] = RISCVTargetLowering::computeVLMAXBounds(ContainerVT, Subtarget); - if (MinVLMAX == MaxVLMAX && NumElts == MinVLMAX && NumElts > 31) + if (MinVLMAX == MaxVLMAX && NumElts == MinVLMAX) return DAG.getRegister(RISCV::X0, Subtarget.getXLenVT()); return DAG.getConstant(NumElts, DL, Subtarget.getXLenVT()); @@ -4040,19 +4042,23 @@ static SDValue lowerScalarInsert(SDValue Scalar, SDValue VL, MVT VT, if (Scalar.getOpcode() == ISD::EXTRACT_VECTOR_ELT && isNullConstant(Scalar.getOperand(1))) { SDValue ExtractedVal = Scalar.getOperand(0); - MVT ExtractedVT = ExtractedVal.getSimpleValueType(); - MVT ExtractedContainerVT = ExtractedVT; - if (ExtractedContainerVT.isFixedLengthVector()) { - ExtractedContainerVT = getContainerForFixedLengthVector( - DAG, ExtractedContainerVT, Subtarget); - ExtractedVal = convertToScalableVector(ExtractedContainerVT, ExtractedVal, - DAG, Subtarget); - } - if (ExtractedContainerVT.bitsLE(VT)) - return DAG.getNode(ISD::INSERT_SUBVECTOR, DL, VT, Passthru, ExtractedVal, + // The element types must be the same. + if (ExtractedVal.getValueType().getVectorElementType() == + VT.getVectorElementType()) { + MVT ExtractedVT = ExtractedVal.getSimpleValueType(); + MVT ExtractedContainerVT = ExtractedVT; + if (ExtractedContainerVT.isFixedLengthVector()) { + ExtractedContainerVT = getContainerForFixedLengthVector( + DAG, ExtractedContainerVT, Subtarget); + ExtractedVal = convertToScalableVector(ExtractedContainerVT, + ExtractedVal, DAG, Subtarget); + } + if (ExtractedContainerVT.bitsLE(VT)) + return DAG.getNode(ISD::INSERT_SUBVECTOR, DL, VT, Passthru, + ExtractedVal, DAG.getConstant(0, DL, XLenVT)); + return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, ExtractedVal, DAG.getConstant(0, DL, XLenVT)); - return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, ExtractedVal, - DAG.getConstant(0, DL, XLenVT)); + } } @@ -4646,6 +4652,85 @@ static SDValue lowerVECTOR_SHUFFLEAsRotate(ShuffleVectorSDNode *SVN, return DAG.getBitcast(VT, Rotate); } +// If compiling with an exactly known VLEN, see if we can split a +// shuffle on m2 or larger into a small number of m1 sized shuffles +// which write each destination registers exactly once. +static SDValue lowerShuffleViaVRegSplitting(ShuffleVectorSDNode *SVN, + SelectionDAG &DAG, + const RISCVSubtarget &Subtarget) { + SDLoc DL(SVN); + MVT VT = SVN->getSimpleValueType(0); + SDValue V1 = SVN->getOperand(0); + SDValue V2 = SVN->getOperand(1); + ArrayRef Mask = SVN->getMask(); + unsigned NumElts = VT.getVectorNumElements(); + + // If we don't know exact data layout, not much we can do. If this + // is already m1 or smaller, no point in splitting further. + const unsigned MinVLen = Subtarget.getRealMinVLen(); + const unsigned MaxVLen = Subtarget.getRealMaxVLen(); + if (MinVLen != MaxVLen || VT.getSizeInBits().getFixedValue() <= MinVLen) + return SDValue(); + + MVT ElemVT = VT.getVectorElementType(); + unsigned ElemsPerVReg = MinVLen / ElemVT.getFixedSizeInBits(); + unsigned VRegsPerSrc = NumElts / ElemsPerVReg; + + SmallVector>> + OutMasks(VRegsPerSrc, {-1, {}}); + + // Check if our mask can be done as a 1-to-1 mapping from source + // to destination registers in the group without needing to + // write each destination more than once. + for (unsigned DstIdx = 0; DstIdx < Mask.size(); DstIdx++) { + int DstVecIdx = DstIdx / ElemsPerVReg; + int DstSubIdx = DstIdx % ElemsPerVReg; + int SrcIdx = Mask[DstIdx]; + if (SrcIdx < 0 || (unsigned)SrcIdx >= 2 * NumElts) + continue; + int SrcVecIdx = SrcIdx / ElemsPerVReg; + int SrcSubIdx = SrcIdx % ElemsPerVReg; + if (OutMasks[DstVecIdx].first == -1) + OutMasks[DstVecIdx].first = SrcVecIdx; + if (OutMasks[DstVecIdx].first != SrcVecIdx) + // Note: This case could easily be handled by keeping track of a chain + // of source values and generating two element shuffles below. This is + // less an implementation question, and more a profitability one. + return SDValue(); + + OutMasks[DstVecIdx].second.resize(ElemsPerVReg, -1); + OutMasks[DstVecIdx].second[DstSubIdx] = SrcSubIdx; + } + + EVT ContainerVT = getContainerForFixedLengthVector(DAG, VT, Subtarget); + MVT OneRegVT = MVT::getVectorVT(ElemVT, ElemsPerVReg); + MVT M1VT = getContainerForFixedLengthVector(DAG, OneRegVT, Subtarget); + assert(M1VT == getLMUL1VT(M1VT)); + unsigned NumOpElts = M1VT.getVectorMinNumElements(); + SDValue Vec = DAG.getUNDEF(ContainerVT); + // The following semantically builds up a fixed length concat_vector + // of the component shuffle_vectors. We eagerly lower to scalable here + // to avoid DAG combining it back to a large shuffle_vector again. + V1 = convertToScalableVector(ContainerVT, V1, DAG, Subtarget); + V2 = convertToScalableVector(ContainerVT, V2, DAG, Subtarget); + for (unsigned DstVecIdx = 0 ; DstVecIdx < OutMasks.size(); DstVecIdx++) { + auto &[SrcVecIdx, SrcSubMask] = OutMasks[DstVecIdx]; + if (SrcVecIdx == -1) + continue; + unsigned ExtractIdx = (SrcVecIdx % VRegsPerSrc) * NumOpElts; + SDValue SrcVec = (unsigned)SrcVecIdx > VRegsPerSrc ? V2 : V1; + SDValue SubVec = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, M1VT, SrcVec, + DAG.getVectorIdxConstant(ExtractIdx, DL)); + SubVec = convertFromScalableVector(OneRegVT, SubVec, DAG, Subtarget); + SubVec = DAG.getVectorShuffle(OneRegVT, DL, SubVec, SubVec, SrcSubMask); + SubVec = convertToScalableVector(M1VT, SubVec, DAG, Subtarget); + unsigned InsertIdx = DstVecIdx * NumOpElts; + Vec = DAG.getNode(ISD::INSERT_SUBVECTOR, DL, ContainerVT, Vec, SubVec, + DAG.getVectorIdxConstant(InsertIdx, DL)); + } + return convertFromScalableVector(VT, Vec, DAG, Subtarget); +} + static SDValue lowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG, const RISCVSubtarget &Subtarget) { SDValue V1 = Op.getOperand(0); @@ -4753,6 +4838,11 @@ static SDValue lowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG, } } + // For exact VLEN m2 or greater, try to split to m1 operations if we + // can split cleanly. + if (SDValue V = lowerShuffleViaVRegSplitting(SVN, DAG, Subtarget)) + return V; + ArrayRef Mask = SVN->getMask(); if (SDValue V = @@ -4846,54 +4936,28 @@ static SDValue lowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG, assert(!V1.isUndef() && "Unexpected shuffle canonicalization"); - SmallVector MaskVals; - // As a backup, shuffles can be lowered via a vrgather instruction, possibly - // merged with a second vrgather. - SmallVector GatherIndicesLHS, GatherIndicesRHS; - // By default we preserve the original operand order, and use a mask to // select LHS as true and RHS as false. However, since RVV vector selects may // feature splats but only on the LHS, we may choose to invert our mask and // instead select between RHS and LHS. bool SwapOps = DAG.isSplatValue(V2) && !DAG.isSplatValue(V1); - bool InvertMask = IsSelect == SwapOps; - // Keep a track of which non-undef indices are used by each LHS/RHS shuffle - // half. - DenseMap LHSIndexCounts, RHSIndexCounts; - - // Now construct the mask that will be used by the vselect or blended - // vrgather operation. For vrgathers, construct the appropriate indices into - // each vector. - for (int MaskIndex : Mask) { - bool SelectMaskVal = (MaskIndex < (int)NumElts) ^ InvertMask; - MaskVals.push_back(DAG.getConstant(SelectMaskVal, DL, XLenVT)); - if (!IsSelect) { - bool IsLHSOrUndefIndex = MaskIndex < (int)NumElts; - GatherIndicesLHS.push_back(IsLHSOrUndefIndex && MaskIndex >= 0 - ? DAG.getConstant(MaskIndex, DL, XLenVT) - : DAG.getUNDEF(XLenVT)); - GatherIndicesRHS.push_back( - IsLHSOrUndefIndex ? DAG.getUNDEF(XLenVT) - : DAG.getConstant(MaskIndex - NumElts, DL, XLenVT)); - if (IsLHSOrUndefIndex && MaskIndex >= 0) - ++LHSIndexCounts[MaskIndex]; - if (!IsLHSOrUndefIndex) - ++RHSIndexCounts[MaskIndex - NumElts]; + if (IsSelect) { + // Now construct the mask that will be used by the vselect operation. + SmallVector MaskVals; + for (int MaskIndex : Mask) { + bool SelectMaskVal = (MaskIndex < (int)NumElts) ^ SwapOps; + MaskVals.push_back(DAG.getConstant(SelectMaskVal, DL, XLenVT)); } - } - if (SwapOps) { - std::swap(V1, V2); - std::swap(GatherIndicesLHS, GatherIndicesRHS); - } + if (SwapOps) + std::swap(V1, V2); - assert(MaskVals.size() == NumElts && "Unexpected select-like shuffle"); - MVT MaskVT = MVT::getVectorVT(MVT::i1, NumElts); - SDValue SelectMask = DAG.getBuildVector(MaskVT, DL, MaskVals); - - if (IsSelect) + assert(MaskVals.size() == NumElts && "Unexpected select-like shuffle"); + MVT MaskVT = MVT::getVectorVT(MVT::i1, NumElts); + SDValue SelectMask = DAG.getBuildVector(MaskVT, DL, MaskVals); return DAG.getNode(ISD::VSELECT, DL, VT, SelectMask, V1, V2); + } // We might be able to express the shuffle as a bitrotate. But even if we // don't have Zvkb and have to expand, the expanded sequence of approx. 2 @@ -4909,6 +4973,43 @@ static SDValue lowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG, return SDValue(); } + // As a backup, shuffles can be lowered via a vrgather instruction, possibly + // merged with a second vrgather. + SmallVector GatherIndicesLHS, GatherIndicesRHS; + + // Keep a track of which non-undef indices are used by each LHS/RHS shuffle + // half. + DenseMap LHSIndexCounts, RHSIndexCounts; + + SmallVector MaskVals; + + // Now construct the mask that will be used by the blended vrgather operation. + // Cconstruct the appropriate indices into each vector. + for (int MaskIndex : Mask) { + bool SelectMaskVal = (MaskIndex < (int)NumElts) ^ !SwapOps; + MaskVals.push_back(DAG.getConstant(SelectMaskVal, DL, XLenVT)); + bool IsLHSOrUndefIndex = MaskIndex < (int)NumElts; + GatherIndicesLHS.push_back(IsLHSOrUndefIndex && MaskIndex >= 0 + ? DAG.getConstant(MaskIndex, DL, XLenVT) + : DAG.getUNDEF(XLenVT)); + GatherIndicesRHS.push_back( + IsLHSOrUndefIndex ? DAG.getUNDEF(XLenVT) + : DAG.getConstant(MaskIndex - NumElts, DL, XLenVT)); + if (IsLHSOrUndefIndex && MaskIndex >= 0) + ++LHSIndexCounts[MaskIndex]; + if (!IsLHSOrUndefIndex) + ++RHSIndexCounts[MaskIndex - NumElts]; + } + + if (SwapOps) { + std::swap(V1, V2); + std::swap(GatherIndicesLHS, GatherIndicesRHS); + } + + assert(MaskVals.size() == NumElts && "Unexpected select-like shuffle"); + MVT MaskVT = MVT::getVectorVT(MVT::i1, NumElts); + SDValue SelectMask = DAG.getBuildVector(MaskVT, DL, MaskVals); + unsigned GatherVXOpc = RISCVISD::VRGATHER_VX_VL; unsigned GatherVVOpc = RISCVISD::VRGATHER_VV_VL; MVT IndexVT = VT.changeTypeToInteger(); @@ -4932,56 +5033,60 @@ static SDValue lowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG, MVT IndexContainerVT = ContainerVT.changeVectorElementType(IndexVT.getScalarType()); - SDValue Gather; - // TODO: This doesn't trigger for i64 vectors on RV32, since there we - // encounter a bitcasted BUILD_VECTOR with low/high i32 values. - if (SDValue SplatValue = DAG.getSplatValue(V1, /*LegalTypes*/ true)) { - Gather = lowerScalarSplat(SDValue(), SplatValue, VL, ContainerVT, DL, DAG, - Subtarget); - } else { + // Base case for the recursion just below - handle the worst case + // single source permutation. Note that all the splat variants + // are handled above. + if (V2.isUndef()) { V1 = convertToScalableVector(ContainerVT, V1, DAG, Subtarget); - // If only one index is used, we can use a "splat" vrgather. - // TODO: We can splat the most-common index and fix-up any stragglers, if - // that's beneficial. - if (LHSIndexCounts.size() == 1) { - int SplatIndex = LHSIndexCounts.begin()->getFirst(); - Gather = DAG.getNode(GatherVXOpc, DL, ContainerVT, V1, - DAG.getConstant(SplatIndex, DL, XLenVT), - DAG.getUNDEF(ContainerVT), TrueMask, VL); - } else { - SDValue LHSIndices = DAG.getBuildVector(IndexVT, DL, GatherIndicesLHS); - LHSIndices = - convertToScalableVector(IndexContainerVT, LHSIndices, DAG, Subtarget); - - Gather = DAG.getNode(GatherVVOpc, DL, ContainerVT, V1, LHSIndices, - DAG.getUNDEF(ContainerVT), TrueMask, VL); - } + SDValue LHSIndices = DAG.getBuildVector(IndexVT, DL, GatherIndicesLHS); + LHSIndices = convertToScalableVector(IndexContainerVT, LHSIndices, DAG, + Subtarget); + SDValue Gather = DAG.getNode(GatherVVOpc, DL, ContainerVT, V1, LHSIndices, + DAG.getUNDEF(ContainerVT), TrueMask, VL); + return convertFromScalableVector(VT, Gather, DAG, Subtarget); } - // If a second vector operand is used by this shuffle, blend it in with an - // additional vrgather. - if (!V2.isUndef()) { - V2 = convertToScalableVector(ContainerVT, V2, DAG, Subtarget); - - MVT MaskContainerVT = ContainerVT.changeVectorElementType(MVT::i1); - SelectMask = - convertToScalableVector(MaskContainerVT, SelectMask, DAG, Subtarget); - - // If only one index is used, we can use a "splat" vrgather. - // TODO: We can splat the most-common index and fix-up any stragglers, if - // that's beneficial. - if (RHSIndexCounts.size() == 1) { - int SplatIndex = RHSIndexCounts.begin()->getFirst(); - Gather = DAG.getNode(GatherVXOpc, DL, ContainerVT, V2, - DAG.getConstant(SplatIndex, DL, XLenVT), Gather, - SelectMask, VL); - } else { - SDValue RHSIndices = DAG.getBuildVector(IndexVT, DL, GatherIndicesRHS); - RHSIndices = - convertToScalableVector(IndexContainerVT, RHSIndices, DAG, Subtarget); - Gather = DAG.getNode(GatherVVOpc, DL, ContainerVT, V2, RHSIndices, Gather, - SelectMask, VL); + // Translate the gather index we computed above (and possibly swapped) + // back to a shuffle mask. This step should disappear once we complete + // the migration to recursive design. + SmallVector ShuffleMaskLHS; + ShuffleMaskLHS.reserve(GatherIndicesLHS.size()); + for (SDValue GatherIndex : GatherIndicesLHS) { + if (GatherIndex.isUndef()) { + ShuffleMaskLHS.push_back(-1); + continue; } + auto *IdxC = cast(GatherIndex); + ShuffleMaskLHS.push_back(IdxC->getZExtValue()); + } + + // Recursively invoke lowering for the LHS as if there were no RHS. + // This allows us to leverage all of our single source permute tricks. + SDValue Gather = + DAG.getVectorShuffle(VT, DL, V1, DAG.getUNDEF(VT), ShuffleMaskLHS); + Gather = convertToScalableVector(ContainerVT, Gather, DAG, Subtarget); + + // Blend in second vector source with an additional vrgather. + V2 = convertToScalableVector(ContainerVT, V2, DAG, Subtarget); + + MVT MaskContainerVT = ContainerVT.changeVectorElementType(MVT::i1); + SelectMask = + convertToScalableVector(MaskContainerVT, SelectMask, DAG, Subtarget); + + // If only one index is used, we can use a "splat" vrgather. + // TODO: We can splat the most-common index and fix-up any stragglers, if + // that's beneficial. + if (RHSIndexCounts.size() == 1) { + int SplatIndex = RHSIndexCounts.begin()->getFirst(); + Gather = DAG.getNode(GatherVXOpc, DL, ContainerVT, V2, + DAG.getConstant(SplatIndex, DL, XLenVT), Gather, + SelectMask, VL); + } else { + SDValue RHSIndices = DAG.getBuildVector(IndexVT, DL, GatherIndicesRHS); + RHSIndices = + convertToScalableVector(IndexContainerVT, RHSIndices, DAG, Subtarget); + Gather = DAG.getNode(GatherVVOpc, DL, ContainerVT, V2, RHSIndices, Gather, + SelectMask, VL); } return convertFromScalableVector(VT, Gather, DAG, Subtarget); @@ -5401,7 +5506,16 @@ static SDValue lowerFMAXIMUM_FMINIMUM(SDValue Op, SelectionDAG &DAG, Y = convertToScalableVector(ContainerVT, Y, DAG, Subtarget); } - auto [Mask, VL] = getDefaultVLOps(VT, ContainerVT, DL, DAG, Subtarget); + SDValue Mask, VL; + if (Op->isVPOpcode()) { + Mask = Op.getOperand(2); + if (VT.isFixedLengthVector()) + Mask = convertToScalableVector(getMaskTypeFor(ContainerVT), Mask, DAG, + Subtarget); + VL = Op.getOperand(3); + } else { + std::tie(Mask, VL) = getDefaultVLOps(VT, ContainerVT, DL, DAG, Subtarget); + } SDValue NewY = Y; if (!XIsNeverNan) { @@ -5422,7 +5536,9 @@ static SDValue lowerFMAXIMUM_FMINIMUM(SDValue Op, SelectionDAG &DAG, } unsigned Opc = - Op.getOpcode() == ISD::FMAXIMUM ? RISCVISD::VFMAX_VL : RISCVISD::VFMIN_VL; + Op.getOpcode() == ISD::FMAXIMUM || Op->getOpcode() == ISD::VP_FMAXIMUM + ? RISCVISD::VFMAX_VL + : RISCVISD::VFMIN_VL; SDValue Res = DAG.getNode(Opc, DL, ContainerVT, NewX, NewY, DAG.getUNDEF(ContainerVT), Mask, VL); if (VT.isFixedLengthVector()) @@ -6651,6 +6767,13 @@ SDValue RISCVTargetLowering::LowerOperation(SDValue Op, !Subtarget.hasVInstructionsF16())) return SplitVPOp(Op, DAG); return lowerVectorFTRUNC_FCEIL_FFLOOR_FROUND(Op, DAG, Subtarget); + case ISD::VP_FMAXIMUM: + case ISD::VP_FMINIMUM: + if (Op.getValueType() == MVT::nxv32f16 && + (Subtarget.hasVInstructionsF16Minimal() && + !Subtarget.hasVInstructionsF16())) + return SplitVPOp(Op, DAG); + return lowerFMAXIMUM_FMINIMUM(Op, DAG, Subtarget); case ISD::EXPERIMENTAL_VP_SPLICE: return lowerVPSpliceExperimental(Op, DAG); case ISD::EXPERIMENTAL_VP_REVERSE: @@ -6859,6 +6982,23 @@ SDValue RISCVTargetLowering::getDynamicTLSAddr(GlobalAddressSDNode *N, return LowerCallTo(CLI).first; } +SDValue RISCVTargetLowering::getTLSDescAddr(GlobalAddressSDNode *N, + SelectionDAG &DAG) const { + SDLoc DL(N); + EVT Ty = getPointerTy(DAG.getDataLayout()); + const GlobalValue *GV = N->getGlobal(); + + // Use a PC-relative addressing mode to access the global dynamic GOT address. + // This generates the pattern (PseudoLA_TLSDESC sym), which expands to + // + // auipc tX, %tlsdesc_hi(symbol) // R_RISCV_TLSDESC_HI20(symbol) + // lw tY, tX, %tlsdesc_lo_load(label) // R_RISCV_TLSDESC_LOAD_LO12_I(label) + // addi a0, tX, %tlsdesc_lo_add(label) // R_RISCV_TLSDESC_ADD_LO12_I(label) + // jalr t0, tY // R_RISCV_TLSDESC_CALL(label) + SDValue Addr = DAG.getTargetGlobalAddress(GV, DL, Ty, 0, 0); + return SDValue(DAG.getMachineNode(RISCV::PseudoLA_TLSDESC, DL, Ty, Addr), 0); +} + SDValue RISCVTargetLowering::lowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const { GlobalAddressSDNode *N = cast(Op); @@ -6883,7 +7023,8 @@ SDValue RISCVTargetLowering::lowerGlobalTLSAddress(SDValue Op, break; case TLSModel::LocalDynamic: case TLSModel::GeneralDynamic: - Addr = getDynamicTLSAddr(N, DAG); + Addr = DAG.getTarget().useTLSDESC() ? getTLSDescAddr(N, DAG) + : getDynamicTLSAddr(N, DAG); break; } @@ -8500,6 +8641,9 @@ SDValue RISCVTargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op, return DAG.getNode(RISCVISD::VMERGE_VL, DL, VT, SelectCond, SplattedVal, Vec, DAG.getUNDEF(VT), VL); } + case Intrinsic::riscv_vfmv_s_f: + return DAG.getNode(RISCVISD::VFMV_S_F_VL, DL, Op.getSimpleValueType(), + Op.getOperand(1), Op.getOperand(2), Op.getOperand(3)); // EGS * EEW >= 128 bits case Intrinsic::riscv_vaesdf_vv: case Intrinsic::riscv_vaesdf_vs: @@ -12762,14 +12906,14 @@ static bool narrowIndex(SDValue &N, ISD::MemIndexType IndexType, SelectionDAG &D SDValue N0 = N.getOperand(0); if (N0.getOpcode() != ISD::ZERO_EXTEND && N0.getOpcode() != RISCVISD::VZEXT_VL) - return false;; + return false; if (!N0->hasOneUse()) - return false;; + return false; APInt ShAmt; SDValue N1 = N.getOperand(1); if (!ISD::isConstantSplatVector(N1.getNode(), ShAmt)) - return false;; + return false; SDValue Src = N0.getOperand(0); EVT SrcVT = Src.getValueType(); @@ -12863,9 +13007,9 @@ struct CombineResult; /// Helper class for folding sign/zero extensions. /// In particular, this class is used for the following combines: -/// add_vl -> vwadd(u) | vwadd(u)_w -/// sub_vl -> vwsub(u) | vwsub(u)_w -/// mul_vl -> vwmul(u) | vwmul_su +/// add | add_vl -> vwadd(u) | vwadd(u)_w +/// sub | sub_vl -> vwsub(u) | vwsub(u)_w +/// mul | mul_vl -> vwmul(u) | vwmul_su /// /// An object of this class represents an operand of the operation we want to /// combine. @@ -12910,6 +13054,8 @@ struct NodeExtensionHelper { /// E.g., for zext(a), this would return a. SDValue getSource() const { switch (OrigOperand.getOpcode()) { + case ISD::ZERO_EXTEND: + case ISD::SIGN_EXTEND: case RISCVISD::VSEXT_VL: case RISCVISD::VZEXT_VL: return OrigOperand.getOperand(0); @@ -12926,7 +13072,8 @@ struct NodeExtensionHelper { /// Get or create a value that can feed \p Root with the given extension \p /// SExt. If \p SExt is std::nullopt, this returns the source of this operand. /// \see ::getSource(). - SDValue getOrCreateExtendedOp(const SDNode *Root, SelectionDAG &DAG, + SDValue getOrCreateExtendedOp(SDNode *Root, SelectionDAG &DAG, + const RISCVSubtarget &Subtarget, std::optional SExt) const { if (!SExt.has_value()) return OrigOperand; @@ -12941,8 +13088,10 @@ struct NodeExtensionHelper { // If we need an extension, we should be changing the type. SDLoc DL(Root); - auto [Mask, VL] = getMaskAndVL(Root); + auto [Mask, VL] = getMaskAndVL(Root, DAG, Subtarget); switch (OrigOperand.getOpcode()) { + case ISD::ZERO_EXTEND: + case ISD::SIGN_EXTEND: case RISCVISD::VSEXT_VL: case RISCVISD::VZEXT_VL: return DAG.getNode(ExtOpc, DL, NarrowVT, Source, Mask, VL); @@ -12982,12 +13131,15 @@ struct NodeExtensionHelper { /// \pre \p Opcode represents a supported root (\see ::isSupportedRoot()). static unsigned getSameExtensionOpcode(unsigned Opcode, bool IsSExt) { switch (Opcode) { + case ISD::ADD: case RISCVISD::ADD_VL: case RISCVISD::VWADD_W_VL: case RISCVISD::VWADDU_W_VL: return IsSExt ? RISCVISD::VWADD_VL : RISCVISD::VWADDU_VL; + case ISD::MUL: case RISCVISD::MUL_VL: return IsSExt ? RISCVISD::VWMUL_VL : RISCVISD::VWMULU_VL; + case ISD::SUB: case RISCVISD::SUB_VL: case RISCVISD::VWSUB_W_VL: case RISCVISD::VWSUBU_W_VL: @@ -13000,7 +13152,8 @@ struct NodeExtensionHelper { /// Get the opcode to materialize \p Opcode(sext(a), zext(b)) -> /// newOpcode(a, b). static unsigned getSUOpcode(unsigned Opcode) { - assert(Opcode == RISCVISD::MUL_VL && "SU is only supported for MUL"); + assert((Opcode == RISCVISD::MUL_VL || Opcode == ISD::MUL) && + "SU is only supported for MUL"); return RISCVISD::VWMULSU_VL; } @@ -13008,8 +13161,10 @@ struct NodeExtensionHelper { /// newOpcode(a, b). static unsigned getWOpcode(unsigned Opcode, bool IsSExt) { switch (Opcode) { + case ISD::ADD: case RISCVISD::ADD_VL: return IsSExt ? RISCVISD::VWADD_W_VL : RISCVISD::VWADDU_W_VL; + case ISD::SUB: case RISCVISD::SUB_VL: return IsSExt ? RISCVISD::VWSUB_W_VL : RISCVISD::VWSUBU_W_VL; default: @@ -13019,19 +13174,49 @@ struct NodeExtensionHelper { using CombineToTry = std::function( SDNode * /*Root*/, const NodeExtensionHelper & /*LHS*/, - const NodeExtensionHelper & /*RHS*/)>; + const NodeExtensionHelper & /*RHS*/, SelectionDAG &, + const RISCVSubtarget &)>; /// Check if this node needs to be fully folded or extended for all users. bool needToPromoteOtherUsers() const { return EnforceOneUse; } /// Helper method to set the various fields of this struct based on the /// type of \p Root. - void fillUpExtensionSupport(SDNode *Root, SelectionDAG &DAG) { + void fillUpExtensionSupport(SDNode *Root, SelectionDAG &DAG, + const RISCVSubtarget &Subtarget) { SupportsZExt = false; SupportsSExt = false; EnforceOneUse = true; CheckMask = true; - switch (OrigOperand.getOpcode()) { + unsigned Opc = OrigOperand.getOpcode(); + switch (Opc) { + case ISD::ZERO_EXTEND: + case ISD::SIGN_EXTEND: { + MVT VT = OrigOperand.getSimpleValueType(); + if (!VT.isVector()) + break; + + SDValue NarrowElt = OrigOperand.getOperand(0); + MVT NarrowVT = NarrowElt.getSimpleValueType(); + + unsigned ScalarBits = VT.getScalarSizeInBits(); + unsigned NarrowScalarBits = NarrowVT.getScalarSizeInBits(); + + // Ensure the narrowing element type is legal + if (!Subtarget.getTargetLowering()->isTypeLegal(NarrowElt.getValueType())) + break; + + // Ensure the extension's semantic is equivalent to rvv vzext or vsext. + if (ScalarBits != NarrowScalarBits * 2) + break; + + SupportsZExt = Opc == ISD::ZERO_EXTEND; + SupportsSExt = Opc == ISD::SIGN_EXTEND; + + SDLoc DL(Root); + std::tie(Mask, VL) = getDefaultScalableVLOps(VT, DL, DAG, Subtarget); + break; + } case RISCVISD::VZEXT_VL: SupportsZExt = true; Mask = OrigOperand.getOperand(1); @@ -13087,8 +13272,16 @@ struct NodeExtensionHelper { } /// Check if \p Root supports any extension folding combines. - static bool isSupportedRoot(const SDNode *Root) { + static bool isSupportedRoot(const SDNode *Root, const SelectionDAG &DAG) { switch (Root->getOpcode()) { + case ISD::ADD: + case ISD::SUB: + case ISD::MUL: { + const TargetLowering &TLI = DAG.getTargetLoweringInfo(); + if (!TLI.isTypeLegal(Root->getValueType(0))) + return false; + return Root->getValueType(0).isScalableVector(); + } case RISCVISD::ADD_VL: case RISCVISD::MUL_VL: case RISCVISD::VWADD_W_VL: @@ -13103,9 +13296,10 @@ struct NodeExtensionHelper { } /// Build a NodeExtensionHelper for \p Root.getOperand(\p OperandIdx). - NodeExtensionHelper(SDNode *Root, unsigned OperandIdx, SelectionDAG &DAG) { - assert(isSupportedRoot(Root) && "Trying to build an helper with an " - "unsupported root"); + NodeExtensionHelper(SDNode *Root, unsigned OperandIdx, SelectionDAG &DAG, + const RISCVSubtarget &Subtarget) { + assert(isSupportedRoot(Root, DAG) && "Trying to build an helper with an " + "unsupported root"); assert(OperandIdx < 2 && "Requesting something else than LHS or RHS"); OrigOperand = Root->getOperand(OperandIdx); @@ -13121,7 +13315,7 @@ struct NodeExtensionHelper { SupportsZExt = Opc == RISCVISD::VWADDU_W_VL || Opc == RISCVISD::VWSUBU_W_VL; SupportsSExt = !SupportsZExt; - std::tie(Mask, VL) = getMaskAndVL(Root); + std::tie(Mask, VL) = getMaskAndVL(Root, DAG, Subtarget); CheckMask = true; // There's no existing extension here, so we don't have to worry about // making sure it gets removed. @@ -13130,7 +13324,7 @@ struct NodeExtensionHelper { } [[fallthrough]]; default: - fillUpExtensionSupport(Root, DAG); + fillUpExtensionSupport(Root, DAG, Subtarget); break; } } @@ -13146,14 +13340,27 @@ struct NodeExtensionHelper { } /// Helper function to get the Mask and VL from \p Root. - static std::pair getMaskAndVL(const SDNode *Root) { - assert(isSupportedRoot(Root) && "Unexpected root"); - return std::make_pair(Root->getOperand(3), Root->getOperand(4)); + static std::pair + getMaskAndVL(const SDNode *Root, SelectionDAG &DAG, + const RISCVSubtarget &Subtarget) { + assert(isSupportedRoot(Root, DAG) && "Unexpected root"); + switch (Root->getOpcode()) { + case ISD::ADD: + case ISD::SUB: + case ISD::MUL: { + SDLoc DL(Root); + MVT VT = Root->getSimpleValueType(0); + return getDefaultScalableVLOps(VT, DL, DAG, Subtarget); + } + default: + return std::make_pair(Root->getOperand(3), Root->getOperand(4)); + } } /// Check if the Mask and VL of this operand are compatible with \p Root. - bool areVLAndMaskCompatible(const SDNode *Root) const { - auto [Mask, VL] = getMaskAndVL(Root); + bool areVLAndMaskCompatible(SDNode *Root, SelectionDAG &DAG, + const RISCVSubtarget &Subtarget) const { + auto [Mask, VL] = getMaskAndVL(Root, DAG, Subtarget); return isMaskCompatible(Mask) && isVLCompatible(VL); } @@ -13161,11 +13368,14 @@ struct NodeExtensionHelper { /// foldings that are supported by this class. static bool isCommutative(const SDNode *N) { switch (N->getOpcode()) { + case ISD::ADD: + case ISD::MUL: case RISCVISD::ADD_VL: case RISCVISD::MUL_VL: case RISCVISD::VWADD_W_VL: case RISCVISD::VWADDU_W_VL: return true; + case ISD::SUB: case RISCVISD::SUB_VL: case RISCVISD::VWSUB_W_VL: case RISCVISD::VWSUBU_W_VL: @@ -13210,14 +13420,25 @@ struct CombineResult { /// Return a value that uses TargetOpcode and that can be used to replace /// Root. /// The actual replacement is *not* done in that method. - SDValue materialize(SelectionDAG &DAG) const { + SDValue materialize(SelectionDAG &DAG, + const RISCVSubtarget &Subtarget) const { SDValue Mask, VL, Merge; - std::tie(Mask, VL) = NodeExtensionHelper::getMaskAndVL(Root); - Merge = Root->getOperand(2); + std::tie(Mask, VL) = + NodeExtensionHelper::getMaskAndVL(Root, DAG, Subtarget); + switch (Root->getOpcode()) { + default: + Merge = Root->getOperand(2); + break; + case ISD::ADD: + case ISD::SUB: + case ISD::MUL: + Merge = DAG.getUNDEF(Root->getValueType(0)); + break; + } return DAG.getNode(TargetOpcode, SDLoc(Root), Root->getValueType(0), - LHS.getOrCreateExtendedOp(Root, DAG, SExtLHS), - RHS.getOrCreateExtendedOp(Root, DAG, SExtRHS), Merge, - Mask, VL); + LHS.getOrCreateExtendedOp(Root, DAG, Subtarget, SExtLHS), + RHS.getOrCreateExtendedOp(Root, DAG, Subtarget, SExtRHS), + Merge, Mask, VL); } }; @@ -13234,15 +13455,16 @@ struct CombineResult { static std::optional canFoldToVWWithSameExtensionImpl(SDNode *Root, const NodeExtensionHelper &LHS, const NodeExtensionHelper &RHS, bool AllowSExt, - bool AllowZExt) { + bool AllowZExt, SelectionDAG &DAG, + const RISCVSubtarget &Subtarget) { assert((AllowSExt || AllowZExt) && "Forgot to set what you want?"); - if (!LHS.areVLAndMaskCompatible(Root) || !RHS.areVLAndMaskCompatible(Root)) + if (!LHS.areVLAndMaskCompatible(Root, DAG, Subtarget) || + !RHS.areVLAndMaskCompatible(Root, DAG, Subtarget)) return std::nullopt; if (AllowZExt && LHS.SupportsZExt && RHS.SupportsZExt) return CombineResult(NodeExtensionHelper::getSameExtensionOpcode( Root->getOpcode(), /*IsSExt=*/false), - Root, LHS, /*SExtLHS=*/false, RHS, - /*SExtRHS=*/false); + Root, LHS, /*SExtLHS=*/false, RHS, /*SExtRHS=*/false); if (AllowSExt && LHS.SupportsSExt && RHS.SupportsSExt) return CombineResult(NodeExtensionHelper::getSameExtensionOpcode( Root->getOpcode(), /*IsSExt=*/true), @@ -13259,9 +13481,10 @@ canFoldToVWWithSameExtensionImpl(SDNode *Root, const NodeExtensionHelper &LHS, /// can be used to apply the pattern. static std::optional canFoldToVWWithSameExtension(SDNode *Root, const NodeExtensionHelper &LHS, - const NodeExtensionHelper &RHS) { + const NodeExtensionHelper &RHS, SelectionDAG &DAG, + const RISCVSubtarget &Subtarget) { return canFoldToVWWithSameExtensionImpl(Root, LHS, RHS, /*AllowSExt=*/true, - /*AllowZExt=*/true); + /*AllowZExt=*/true, DAG, Subtarget); } /// Check if \p Root follows a pattern Root(LHS, ext(RHS)) @@ -13270,8 +13493,9 @@ canFoldToVWWithSameExtension(SDNode *Root, const NodeExtensionHelper &LHS, /// can be used to apply the pattern. static std::optional canFoldToVW_W(SDNode *Root, const NodeExtensionHelper &LHS, - const NodeExtensionHelper &RHS) { - if (!RHS.areVLAndMaskCompatible(Root)) + const NodeExtensionHelper &RHS, SelectionDAG &DAG, + const RISCVSubtarget &Subtarget) { + if (!RHS.areVLAndMaskCompatible(Root, DAG, Subtarget)) return std::nullopt; // FIXME: Is it useful to form a vwadd.wx or vwsub.wx if it removes a scalar @@ -13295,9 +13519,10 @@ canFoldToVW_W(SDNode *Root, const NodeExtensionHelper &LHS, /// can be used to apply the pattern. static std::optional canFoldToVWWithSEXT(SDNode *Root, const NodeExtensionHelper &LHS, - const NodeExtensionHelper &RHS) { + const NodeExtensionHelper &RHS, SelectionDAG &DAG, + const RISCVSubtarget &Subtarget) { return canFoldToVWWithSameExtensionImpl(Root, LHS, RHS, /*AllowSExt=*/true, - /*AllowZExt=*/false); + /*AllowZExt=*/false, DAG, Subtarget); } /// Check if \p Root follows a pattern Root(zext(LHS), zext(RHS)) @@ -13306,9 +13531,10 @@ canFoldToVWWithSEXT(SDNode *Root, const NodeExtensionHelper &LHS, /// can be used to apply the pattern. static std::optional canFoldToVWWithZEXT(SDNode *Root, const NodeExtensionHelper &LHS, - const NodeExtensionHelper &RHS) { + const NodeExtensionHelper &RHS, SelectionDAG &DAG, + const RISCVSubtarget &Subtarget) { return canFoldToVWWithSameExtensionImpl(Root, LHS, RHS, /*AllowSExt=*/false, - /*AllowZExt=*/true); + /*AllowZExt=*/true, DAG, Subtarget); } /// Check if \p Root follows a pattern Root(sext(LHS), zext(RHS)) @@ -13317,10 +13543,13 @@ canFoldToVWWithZEXT(SDNode *Root, const NodeExtensionHelper &LHS, /// can be used to apply the pattern. static std::optional canFoldToVW_SU(SDNode *Root, const NodeExtensionHelper &LHS, - const NodeExtensionHelper &RHS) { + const NodeExtensionHelper &RHS, SelectionDAG &DAG, + const RISCVSubtarget &Subtarget) { + if (!LHS.SupportsSExt || !RHS.SupportsZExt) return std::nullopt; - if (!LHS.areVLAndMaskCompatible(Root) || !RHS.areVLAndMaskCompatible(Root)) + if (!LHS.areVLAndMaskCompatible(Root, DAG, Subtarget) || + !RHS.areVLAndMaskCompatible(Root, DAG, Subtarget)) return std::nullopt; return CombineResult(NodeExtensionHelper::getSUOpcode(Root->getOpcode()), Root, LHS, /*SExtLHS=*/true, RHS, /*SExtRHS=*/false); @@ -13330,6 +13559,8 @@ SmallVector NodeExtensionHelper::getSupportedFoldings(const SDNode *Root) { SmallVector Strategies; switch (Root->getOpcode()) { + case ISD::ADD: + case ISD::SUB: case RISCVISD::ADD_VL: case RISCVISD::SUB_VL: // add|sub -> vwadd(u)|vwsub(u) @@ -13337,6 +13568,7 @@ NodeExtensionHelper::getSupportedFoldings(const SDNode *Root) { // add|sub -> vwadd(u)_w|vwsub(u)_w Strategies.push_back(canFoldToVW_W); break; + case ISD::MUL: case RISCVISD::MUL_VL: // mul -> vwmul(u) Strategies.push_back(canFoldToVWWithSameExtension); @@ -13367,12 +13599,14 @@ NodeExtensionHelper::getSupportedFoldings(const SDNode *Root) { /// mul_vl -> vwmul(u) | vwmul_su /// vwadd_w(u) -> vwadd(u) /// vwub_w(u) -> vwadd(u) -static SDValue -combineBinOp_VLToVWBinOp_VL(SDNode *N, TargetLowering::DAGCombinerInfo &DCI) { +static SDValue combineBinOp_VLToVWBinOp_VL(SDNode *N, + TargetLowering::DAGCombinerInfo &DCI, + const RISCVSubtarget &Subtarget) { SelectionDAG &DAG = DCI.DAG; - assert(NodeExtensionHelper::isSupportedRoot(N) && - "Shouldn't have called this method"); + if (!NodeExtensionHelper::isSupportedRoot(N, DAG)) + return SDValue(); + SmallVector Worklist; SmallSet Inserted; Worklist.push_back(N); @@ -13381,11 +13615,11 @@ combineBinOp_VLToVWBinOp_VL(SDNode *N, TargetLowering::DAGCombinerInfo &DCI) { while (!Worklist.empty()) { SDNode *Root = Worklist.pop_back_val(); - if (!NodeExtensionHelper::isSupportedRoot(Root)) + if (!NodeExtensionHelper::isSupportedRoot(Root, DAG)) return SDValue(); - NodeExtensionHelper LHS(N, 0, DAG); - NodeExtensionHelper RHS(N, 1, DAG); + NodeExtensionHelper LHS(N, 0, DAG, Subtarget); + NodeExtensionHelper RHS(N, 1, DAG, Subtarget); auto AppendUsersIfNeeded = [&Worklist, &Inserted](const NodeExtensionHelper &Op) { if (Op.needToPromoteOtherUsers()) { @@ -13412,7 +13646,8 @@ combineBinOp_VLToVWBinOp_VL(SDNode *N, TargetLowering::DAGCombinerInfo &DCI) { for (NodeExtensionHelper::CombineToTry FoldingStrategy : FoldingStrategies) { - std::optional Res = FoldingStrategy(N, LHS, RHS); + std::optional Res = + FoldingStrategy(N, LHS, RHS, DAG, Subtarget); if (Res) { Matched = true; CombinesToApply.push_back(*Res); @@ -13441,7 +13676,7 @@ combineBinOp_VLToVWBinOp_VL(SDNode *N, TargetLowering::DAGCombinerInfo &DCI) { SmallVector> ValuesToReplace; ValuesToReplace.reserve(CombinesToApply.size()); for (CombineResult Res : CombinesToApply) { - SDValue NewValue = Res.materialize(DAG); + SDValue NewValue = Res.materialize(DAG, Subtarget); if (!InputRootReplacement) { assert(Res.Root == N && "First element is expected to be the current node"); @@ -14713,13 +14948,20 @@ static SDValue performCONCAT_VECTORSCombine(SDNode *N, SelectionDAG &DAG, static SDValue combineToVWMACC(SDNode *N, SelectionDAG &DAG, const RISCVSubtarget &Subtarget) { - assert(N->getOpcode() == RISCVISD::ADD_VL); + + assert(N->getOpcode() == RISCVISD::ADD_VL || N->getOpcode() == ISD::ADD); + + if (N->getValueType(0).isFixedLengthVector()) + return SDValue(); + SDValue Addend = N->getOperand(0); SDValue MulOp = N->getOperand(1); - SDValue AddMergeOp = N->getOperand(2); - if (!AddMergeOp.isUndef()) - return SDValue(); + if (N->getOpcode() == RISCVISD::ADD_VL) { + SDValue AddMergeOp = N->getOperand(2); + if (!AddMergeOp.isUndef()) + return SDValue(); + } auto IsVWMulOpc = [](unsigned Opc) { switch (Opc) { @@ -14743,8 +14985,16 @@ static SDValue combineToVWMACC(SDNode *N, SelectionDAG &DAG, if (!MulMergeOp.isUndef()) return SDValue(); - SDValue AddMask = N->getOperand(3); - SDValue AddVL = N->getOperand(4); + auto [AddMask, AddVL] = [](SDNode *N, SelectionDAG &DAG, + const RISCVSubtarget &Subtarget) { + if (N->getOpcode() == ISD::ADD) { + SDLoc DL(N); + return getDefaultScalableVLOps(N->getSimpleValueType(0), DL, DAG, + Subtarget); + } + return std::make_pair(N->getOperand(3), N->getOperand(4)); + }(N, DAG, Subtarget); + SDValue MulMask = MulOp.getOperand(3); SDValue MulVL = MulOp.getOperand(4); @@ -15010,10 +15260,18 @@ SDValue RISCVTargetLowering::PerformDAGCombine(SDNode *N, return DAG.getNode(ISD::AND, DL, VT, NewFMV, DAG.getConstant(~SignBit, DL, VT)); } - case ISD::ADD: + case ISD::ADD: { + if (SDValue V = combineBinOp_VLToVWBinOp_VL(N, DCI, Subtarget)) + return V; + if (SDValue V = combineToVWMACC(N, DAG, Subtarget)) + return V; return performADDCombine(N, DAG, Subtarget); - case ISD::SUB: + } + case ISD::SUB: { + if (SDValue V = combineBinOp_VLToVWBinOp_VL(N, DCI, Subtarget)) + return V; return performSUBCombine(N, DAG, Subtarget); + } case ISD::AND: return performANDCombine(N, DCI, Subtarget); case ISD::OR: @@ -15021,6 +15279,8 @@ SDValue RISCVTargetLowering::PerformDAGCombine(SDNode *N, case ISD::XOR: return performXORCombine(N, DAG, Subtarget); case ISD::MUL: + if (SDValue V = combineBinOp_VLToVWBinOp_VL(N, DCI, Subtarget)) + return V; return performMULCombine(N, DAG); case ISD::FADD: case ISD::UMAX: @@ -15497,7 +15757,7 @@ SDValue RISCVTargetLowering::PerformDAGCombine(SDNode *N, break; } case RISCVISD::ADD_VL: - if (SDValue V = combineBinOp_VLToVWBinOp_VL(N, DCI)) + if (SDValue V = combineBinOp_VLToVWBinOp_VL(N, DCI, Subtarget)) return V; return combineToVWMACC(N, DAG, Subtarget); case RISCVISD::SUB_VL: @@ -15506,7 +15766,7 @@ SDValue RISCVTargetLowering::PerformDAGCombine(SDNode *N, case RISCVISD::VWSUB_W_VL: case RISCVISD::VWSUBU_W_VL: case RISCVISD::MUL_VL: - return combineBinOp_VLToVWBinOp_VL(N, DCI); + return combineBinOp_VLToVWBinOp_VL(N, DCI, Subtarget); case RISCVISD::VFMADD_VL: case RISCVISD::VFNMADD_VL: case RISCVISD::VFMSUB_VL: @@ -15729,6 +15989,17 @@ SDValue RISCVTargetLowering::PerformDAGCombine(SDNode *N, break; } + case RISCVISD::VMV_X_S: { + SDValue Vec = N->getOperand(0); + MVT VecVT = N->getOperand(0).getSimpleValueType(); + const MVT M1VT = getLMUL1VT(VecVT); + if (M1VT.bitsLT(VecVT)) { + Vec = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, M1VT, Vec, + DAG.getVectorIdxConstant(0, DL)); + return DAG.getNode(RISCVISD::VMV_X_S, DL, N->getSimpleValueType(0), Vec); + } + break; + } case ISD::INTRINSIC_VOID: case ISD::INTRINSIC_W_CHAIN: case ISD::INTRINSIC_WO_CHAIN: { @@ -17047,12 +17318,39 @@ static const MCPhysReg ArgVRM4s[] = {RISCV::V8M4, RISCV::V12M4, RISCV::V16M4, RISCV::V20M4}; static const MCPhysReg ArgVRM8s[] = {RISCV::V8M8, RISCV::V16M8}; -ArrayRef RISCV::getArgGPRs() { - static const MCPhysReg ArgGPRs[] = {RISCV::X10, RISCV::X11, RISCV::X12, - RISCV::X13, RISCV::X14, RISCV::X15, - RISCV::X16, RISCV::X17}; +ArrayRef RISCV::getArgGPRs(const RISCVABI::ABI ABI) { + // The GPRs used for passing arguments in the ILP32* and LP64* ABIs, except + // the ILP32E ABI. + static const MCPhysReg ArgIGPRs[] = {RISCV::X10, RISCV::X11, RISCV::X12, + RISCV::X13, RISCV::X14, RISCV::X15, + RISCV::X16, RISCV::X17}; + // The GPRs used for passing arguments in the ILP32E/ILP64E ABI. + static const MCPhysReg ArgEGPRs[] = {RISCV::X10, RISCV::X11, RISCV::X12, + RISCV::X13, RISCV::X14, RISCV::X15}; - return ArrayRef(ArgGPRs); + if (ABI == RISCVABI::ABI_ILP32E || ABI == RISCVABI::ABI_LP64E) + return ArrayRef(ArgEGPRs); + + return ArrayRef(ArgIGPRs); +} + +static ArrayRef getFastCCArgGPRs(const RISCVABI::ABI ABI) { + // The GPRs used for passing arguments in the FastCC, X5 and X6 might be used + // for save-restore libcall, so we don't use them. + static const MCPhysReg FastCCIGPRs[] = { + RISCV::X10, RISCV::X11, RISCV::X12, RISCV::X13, RISCV::X14, + RISCV::X15, RISCV::X16, RISCV::X17, RISCV::X7, RISCV::X28, + RISCV::X29, RISCV::X30, RISCV::X31}; + + // The GPRs used for passing arguments in the FastCC when using ILP32E/ILP64E. + static const MCPhysReg FastCCEGPRs[] = {RISCV::X10, RISCV::X11, RISCV::X12, + RISCV::X13, RISCV::X14, RISCV::X15, + RISCV::X7}; + + if (ABI == RISCVABI::ABI_ILP32E || ABI == RISCVABI::ABI_LP64E) + return ArrayRef(FastCCEGPRs); + + return ArrayRef(FastCCIGPRs); } // Pass a 2*XLEN argument that has been split into two XLEN values through @@ -17060,17 +17358,23 @@ ArrayRef RISCV::getArgGPRs() { static bool CC_RISCVAssign2XLen(unsigned XLen, CCState &State, CCValAssign VA1, ISD::ArgFlagsTy ArgFlags1, unsigned ValNo2, MVT ValVT2, MVT LocVT2, - ISD::ArgFlagsTy ArgFlags2) { + ISD::ArgFlagsTy ArgFlags2, bool EABI) { unsigned XLenInBytes = XLen / 8; - ArrayRef ArgGPRs = RISCV::getArgGPRs(); + const RISCVSubtarget &STI = + State.getMachineFunction().getSubtarget(); + ArrayRef ArgGPRs = RISCV::getArgGPRs(STI.getTargetABI()); + if (Register Reg = State.AllocateReg(ArgGPRs)) { // At least one half can be passed via register. State.addLoc(CCValAssign::getReg(VA1.getValNo(), VA1.getValVT(), Reg, VA1.getLocVT(), CCValAssign::Full)); } else { // Both halves must be passed on the stack, with proper alignment. - Align StackAlign = - std::max(Align(XLenInBytes), ArgFlags1.getNonZeroOrigAlign()); + // TODO: To be compatible with GCC's behaviors, we force them to have 4-byte + // alignment. This behavior may be changed when RV32E/ILP32E is ratified. + Align StackAlign(XLenInBytes); + if (!EABI || XLen != 32) + StackAlign = std::max(StackAlign, ArgFlags1.getNonZeroOrigAlign()); State.addLoc( CCValAssign::getMem(VA1.getValNo(), VA1.getValVT(), State.AllocateStack(XLenInBytes, StackAlign), @@ -17151,7 +17455,9 @@ bool RISCV::CC_RISCV(const DataLayout &DL, RISCVABI::ABI ABI, unsigned ValNo, default: llvm_unreachable("Unexpected ABI"); case RISCVABI::ABI_ILP32: + case RISCVABI::ABI_ILP32E: case RISCVABI::ABI_LP64: + case RISCVABI::ABI_LP64E: break; case RISCVABI::ABI_ILP32F: case RISCVABI::ABI_LP64F: @@ -17183,7 +17489,7 @@ bool RISCV::CC_RISCV(const DataLayout &DL, RISCVABI::ABI ABI, unsigned ValNo, LocInfo = CCValAssign::BCvt; } - ArrayRef ArgGPRs = RISCV::getArgGPRs(); + ArrayRef ArgGPRs = RISCV::getArgGPRs(ABI); // If this is a variadic argument, the RISC-V calling convention requires // that it is assigned an 'even' or 'aligned' register if it has 8-byte @@ -17192,9 +17498,13 @@ bool RISCV::CC_RISCV(const DataLayout &DL, RISCVABI::ABI ABI, unsigned ValNo, // legalisation or not. The argument will not be passed by registers if the // original type is larger than 2*XLEN, so the register alignment rule does // not apply. + // TODO: To be compatible with GCC's behaviors, we don't align registers + // currently if we are using ILP32E calling convention. This behavior may be + // changed when RV32E/ILP32E is ratified. unsigned TwoXLenInBytes = (2 * XLen) / 8; if (!IsFixed && ArgFlags.getNonZeroOrigAlign() == TwoXLenInBytes && - DL.getTypeAllocSize(OrigTy) == TwoXLenInBytes) { + DL.getTypeAllocSize(OrigTy) == TwoXLenInBytes && + ABI != RISCVABI::ABI_ILP32E) { unsigned RegIdx = State.getFirstUnallocated(ArgGPRs); // Skip 'odd' register if necessary. if (RegIdx != std::size(ArgGPRs) && RegIdx % 2 == 1) @@ -17267,8 +17577,9 @@ bool RISCV::CC_RISCV(const DataLayout &DL, RISCVABI::ABI ABI, unsigned ValNo, ISD::ArgFlagsTy AF = PendingArgFlags[0]; PendingLocs.clear(); PendingArgFlags.clear(); - return CC_RISCVAssign2XLen(XLen, State, VA, AF, ValNo, ValVT, LocVT, - ArgFlags); + return CC_RISCVAssign2XLen( + XLen, State, VA, AF, ValNo, ValVT, LocVT, ArgFlags, + ABI == RISCVABI::ABI_ILP32E || ABI == RISCVABI::ABI_LP64E); } // Allocate to a register if possible, or else a stack slot. @@ -17594,15 +17905,8 @@ bool RISCV::CC_RISCV_FastCC(const DataLayout &DL, RISCVABI::ABI ABI, bool IsFixed, bool IsRet, Type *OrigTy, const RISCVTargetLowering &TLI, std::optional FirstMaskArgument) { - - // X5 and X6 might be used for save-restore libcall. - static const MCPhysReg GPRList[] = { - RISCV::X10, RISCV::X11, RISCV::X12, RISCV::X13, RISCV::X14, - RISCV::X15, RISCV::X16, RISCV::X17, RISCV::X7, RISCV::X28, - RISCV::X29, RISCV::X30, RISCV::X31}; - if (LocVT == MVT::i32 || LocVT == MVT::i64) { - if (unsigned Reg = State.AllocateReg(GPRList)) { + if (unsigned Reg = State.AllocateReg(getFastCCArgGPRs(ABI))) { State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); return false; } @@ -17653,7 +17957,7 @@ bool RISCV::CC_RISCV_FastCC(const DataLayout &DL, RISCVABI::ABI ABI, (LocVT == MVT::f32 && Subtarget.hasStdExtZfinx()) || (LocVT == MVT::f64 && Subtarget.is64Bit() && Subtarget.hasStdExtZdinx())) { - if (unsigned Reg = State.AllocateReg(GPRList)) { + if (unsigned Reg = State.AllocateReg(getFastCCArgGPRs(ABI))) { State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); return false; } @@ -17687,7 +17991,7 @@ bool RISCV::CC_RISCV_FastCC(const DataLayout &DL, RISCVABI::ABI ABI, State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); } else { // Try and pass the address via a "fast" GPR. - if (unsigned GPRReg = State.AllocateReg(GPRList)) { + if (unsigned GPRReg = State.AllocateReg(getFastCCArgGPRs(ABI))) { LocInfo = CCValAssign::Indirect; LocVT = TLI.getSubtarget().getXLenVT(); State.addLoc(CCValAssign::getReg(ValNo, ValVT, GPRReg, LocVT, LocInfo)); @@ -17788,6 +18092,8 @@ SDValue RISCVTargetLowering::LowerFormalArguments( case CallingConv::GRAAL: break; case CallingConv::GHC: + if (Subtarget.isRVE()) + report_fatal_error("GHC calling convention is not supported on RVE!"); if (!Subtarget.hasStdExtFOrZfinx() || !Subtarget.hasStdExtDOrZdinx()) report_fatal_error("GHC calling convention requires the (Zfinx/F) and " "(Zdinx/D) instruction set extensions"); @@ -17870,7 +18176,7 @@ SDValue RISCVTargetLowering::LowerFormalArguments( MF.getInfo()->setIsVectorCall(); if (IsVarArg) { - ArrayRef ArgRegs = RISCV::getArgGPRs(); + ArrayRef ArgRegs = RISCV::getArgGPRs(Subtarget.getTargetABI()); unsigned Idx = CCInfo.getFirstUnallocated(ArgRegs); const TargetRegisterClass *RC = &RISCV::GPRRegClass; MachineFrameInfo &MFI = MF.getFrameInfo(); @@ -18023,9 +18329,11 @@ SDValue RISCVTargetLowering::LowerCall(CallLoweringInfo &CLI, SmallVector ArgLocs; CCState ArgCCInfo(CallConv, IsVarArg, MF, ArgLocs, *DAG.getContext()); - if (CallConv == CallingConv::GHC) + if (CallConv == CallingConv::GHC) { + if (Subtarget.isRVE()) + report_fatal_error("GHC calling convention is not supported on RVE!"); ArgCCInfo.AnalyzeCallOperands(Outs, RISCV::CC_RISCV_GHC); - else + } else analyzeOutputArgs(MF, ArgCCInfo, Outs, /*IsRet=*/false, &CLI, CallConv == CallingConv::Fast ? RISCV::CC_RISCV_FastCC : RISCV::CC_RISCV); diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.h b/llvm/lib/Target/RISCV/RISCVISelLowering.h index c65953e37b1..30b9ad7e6f6 100644 --- a/llvm/lib/Target/RISCV/RISCVISelLowering.h +++ b/llvm/lib/Target/RISCV/RISCVISelLowering.h @@ -855,6 +855,7 @@ private: SDValue getStaticTLSAddr(GlobalAddressSDNode *N, SelectionDAG &DAG, bool UseGOT) const; SDValue getDynamicTLSAddr(GlobalAddressSDNode *N, SelectionDAG &DAG) const; + SDValue getTLSDescAddr(GlobalAddressSDNode *N, SelectionDAG &DAG) const; SDValue lowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const; SDValue lowerBlockAddress(SDValue Op, SelectionDAG &DAG) const; @@ -995,7 +996,7 @@ bool CC_RISCV_GHC(unsigned ValNo, MVT ValVT, MVT LocVT, CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags, CCState &State); -ArrayRef getArgGPRs(); +ArrayRef getArgGPRs(const RISCVABI::ABI ABI); } // end namespace RISCV diff --git a/llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp b/llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp index 6c9e529e4bf..a14f9a28354 100644 --- a/llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp +++ b/llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp @@ -26,6 +26,7 @@ #include "RISCV.h" #include "RISCVSubtarget.h" +#include "llvm/ADT/Statistic.h" #include "llvm/CodeGen/LiveIntervals.h" #include "llvm/CodeGen/MachineFunctionPass.h" #include @@ -34,6 +35,9 @@ using namespace llvm; #define DEBUG_TYPE "riscv-insert-vsetvli" #define RISCV_INSERT_VSETVLI_NAME "RISC-V Insert VSETVLI pass" +STATISTIC(NumInsertedVSETVL, "Number of VSETVL inst inserted"); +STATISTIC(NumRemovedVSETVL, "Number of VSETVL inst removed"); + static cl::opt DisableInsertVSETVLPHIOpt( "riscv-disable-insert-vsetvl-phi-opt", cl::init(false), cl::Hidden, cl::desc("Disable looking through phis when inserting vsetvlis.")); @@ -804,7 +808,18 @@ static VSETVLIInfo getInfoForVSETVLI(const MachineInstr &MI) { return NewInfo; } +static unsigned computeVLMAX(unsigned VLEN, unsigned SEW, + RISCVII::VLMUL VLMul) { + auto [LMul, Fractional] = RISCVVType::decodeVLMUL(VLMul); + if (Fractional) + VLEN = VLEN / LMul; + else + VLEN = VLEN * LMul; + return VLEN/SEW; +} + static VSETVLIInfo computeInfoForInstr(const MachineInstr &MI, uint64_t TSFlags, + const RISCVSubtarget &ST, const MachineRegisterInfo *MRI) { VSETVLIInfo InstrInfo; @@ -846,8 +861,15 @@ static VSETVLIInfo computeInfoForInstr(const MachineInstr &MI, uint64_t TSFlags, if (VLOp.isImm()) { int64_t Imm = VLOp.getImm(); // Conver the VLMax sentintel to X0 register. - if (Imm == RISCV::VLMaxSentinel) - InstrInfo.setAVLReg(RISCV::X0); + if (Imm == RISCV::VLMaxSentinel) { + // If we know the exact VLEN, see if we can use the constant encoding + // for the VLMAX instead. This reduces register pressure slightly. + const unsigned VLMAX = computeVLMAX(ST.getRealMaxVLen(), SEW, VLMul); + if (ST.getRealMinVLen() == ST.getRealMaxVLen() && VLMAX <= 31) + InstrInfo.setAVLImm(VLMAX); + else + InstrInfo.setAVLReg(RISCV::X0); + } else InstrInfo.setAVLImm(Imm); } else { @@ -893,6 +915,7 @@ void RISCVInsertVSETVLI::insertVSETVLI(MachineBasicBlock &MBB, MachineBasicBlock::iterator InsertPt, DebugLoc DL, const VSETVLIInfo &Info, const VSETVLIInfo &PrevInfo) { + ++NumInsertedVSETVL; if (PrevInfo.isValid() && !PrevInfo.isUnknown()) { // Use X0, X0 form if the AVL is the same and the SEW+LMUL gives the same // VLMAX. @@ -983,7 +1006,7 @@ static bool isLMUL1OrSmaller(RISCVII::VLMUL LMUL) { bool RISCVInsertVSETVLI::needVSETVLI(const MachineInstr &MI, const VSETVLIInfo &Require, const VSETVLIInfo &CurInfo) const { - assert(Require == computeInfoForInstr(MI, MI.getDesc().TSFlags, MRI)); + assert(Require == computeInfoForInstr(MI, MI.getDesc().TSFlags, *ST, MRI)); if (!CurInfo.isValid() || CurInfo.isUnknown() || CurInfo.hasSEWLMULRatioOnly()) return true; @@ -1071,7 +1094,7 @@ void RISCVInsertVSETVLI::transferBefore(VSETVLIInfo &Info, if (!RISCVII::hasSEWOp(TSFlags)) return; - const VSETVLIInfo NewInfo = computeInfoForInstr(MI, TSFlags, MRI); + const VSETVLIInfo NewInfo = computeInfoForInstr(MI, TSFlags, *ST, MRI); assert(NewInfo.isValid() && !NewInfo.isUnknown()); if (Info.isValid() && !needVSETVLI(MI, NewInfo, Info)) return; @@ -1560,6 +1583,7 @@ void RISCVInsertVSETVLI::doLocalPostpass(MachineBasicBlock &MBB) { Used = getDemanded(MI, MRI, ST); } + NumRemovedVSETVL += ToDelete.size(); for (auto *MI : ToDelete) MI->eraseFromParent(); } diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp b/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp index 9813c7a70df..592962cebe8 100644 --- a/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp +++ b/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp @@ -2379,7 +2379,11 @@ RISCVInstrInfo::getSerializableDirectMachineOperandTargetFlags() const { {MO_TPREL_HI, "riscv-tprel-hi"}, {MO_TPREL_ADD, "riscv-tprel-add"}, {MO_TLS_GOT_HI, "riscv-tls-got-hi"}, - {MO_TLS_GD_HI, "riscv-tls-gd-hi"}}; + {MO_TLS_GD_HI, "riscv-tls-gd-hi"}, + {MO_TLSDESC_HI, "riscv-tlsdesc-hi"}, + {MO_TLSDESC_LOAD_LO, "riscv-tlsdesc-load-lo"}, + {MO_TLSDESC_ADD_LO, "riscv-tlsdesc-add-lo"}, + {MO_TLSDESC_CALL, "riscv-tlsdesc-call"}}; return ArrayRef(TargetFlags); } bool RISCVInstrInfo::isFunctionSafeToOutlineFrom( @@ -2434,10 +2438,8 @@ RISCVInstrInfo::getOutliningCandidateInfo( unsigned SequenceSize = 0; - auto I = RepeatedSequenceLocs[0].front(); - auto E = std::next(RepeatedSequenceLocs[0].back()); - for (; I != E; ++I) - SequenceSize += getInstSizeInBytes(*I); + for (auto &MI : RepeatedSequenceLocs[0]) + SequenceSize += getInstSizeInBytes(MI); // call t0, function = 8 bytes. unsigned CallOverhead = 8; @@ -3126,18 +3128,39 @@ void RISCVInstrInfo::getVLENFactoredAmount(MachineFunction &MF, .addReg(ScaledRegister, RegState::Kill) .addReg(DestReg, RegState::Kill) .setMIFlag(Flag); - } else { + } else if (STI.hasStdExtM() || STI.hasStdExtZmmul()) { Register N = MRI.createVirtualRegister(&RISCV::GPRRegClass); movImm(MBB, II, DL, N, NumOfVReg, Flag); - if (!STI.hasStdExtM() && !STI.hasStdExtZmmul()) - MF.getFunction().getContext().diagnose(DiagnosticInfoUnsupported{ - MF.getFunction(), - "M- or Zmmul-extension must be enabled to calculate the vscaled size/" - "offset."}); BuildMI(MBB, II, DL, get(RISCV::MUL), DestReg) .addReg(DestReg, RegState::Kill) .addReg(N, RegState::Kill) .setMIFlag(Flag); + } else { + Register Acc = MRI.createVirtualRegister(&RISCV::GPRRegClass); + BuildMI(MBB, II, DL, get(RISCV::ADDI), Acc) + .addReg(RISCV::X0) + .addImm(0) + .setMIFlag(Flag); + uint32_t PrevShiftAmount = 0; + for (uint32_t ShiftAmount = 0; NumOfVReg >> ShiftAmount; ShiftAmount++) { + if (NumOfVReg & (1LL << ShiftAmount)) { + if (ShiftAmount) + BuildMI(MBB, II, DL, get(RISCV::SLLI), DestReg) + .addReg(DestReg, RegState::Kill) + .addImm(ShiftAmount - PrevShiftAmount) + .setMIFlag(Flag); + if (NumOfVReg >> (ShiftAmount + 1)) + BuildMI(MBB, II, DL, get(RISCV::ADD), Acc) + .addReg(Acc, RegState::Kill) + .addReg(DestReg) + .setMIFlag(Flag); + PrevShiftAmount = ShiftAmount; + } + } + BuildMI(MBB, II, DL, get(RISCV::ADD), DestReg) + .addReg(DestReg, RegState::Kill) + .addReg(Acc) + .setMIFlag(Flag); } } diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.td b/llvm/lib/Target/RISCV/RISCVInstrInfo.td index 792e0bbdf58..114329c2c7c 100644 --- a/llvm/lib/Target/RISCV/RISCVInstrInfo.td +++ b/llvm/lib/Target/RISCV/RISCVInstrInfo.td @@ -1742,6 +1742,35 @@ let hasSideEffects = 0, mayLoad = 0, mayStore = 0, Size = 8, isCodeGenOnly = 0, def PseudoLA_TLS_GD : Pseudo<(outs GPR:$dst), (ins bare_symbol:$src), [], "la.tls.gd", "$dst, $src">; +let hasSideEffects = 0, mayLoad = 1, mayStore = 0, Size = 32, isCodeGenOnly = 0 in +def PseudoLA_TLSDESC : Pseudo<(outs GPR:$dst), (ins bare_symbol:$src), [], + "la.tlsdesc", "$dst, $src">; + +def TLSDESCCallSymbol : AsmOperandClass { + let Name = "TLSDESCCallSymbol"; + let RenderMethod = "addImmOperands"; + let DiagnosticType = "InvalidTLSDESCCallSymbol"; + let ParserMethod = "parseOperandWithModifier"; +} + +// A bare symbol with the %tlsdesc_call variant. +def tlsdesc_call_symbol : Operand { + let ParserMatchClass = TLSDESCCallSymbol; +} +// This is a special case of the JALR instruction used to facilitate the use of a +// fourth operand to emit a relocation on a symbol relating to this instruction. +// The relocation does not affect any bits of the instruction itself but is used +// as a hint to the linker. +let isCall = 1, isBarrier = 1, isCodeGenOnly = 0, Size = 8, hasSideEffects = 0, + mayStore = 0, mayLoad = 0 in +def PseudoTLSDESCCall : Pseudo<(outs GPR:$rd), + (ins GPR:$rs1, simm12:$imm12, tlsdesc_call_symbol:$src), [], + "jalr", "$rd, ${imm12}(${rs1}), $src">, + Sched<[WriteJalr, ReadJalr]> { + let Defs = [X10]; + let Uses = [X10]; +} + /// Sign/Zero Extends diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td b/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td index fcb18b67623..d3973f9b2ed 100644 --- a/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td +++ b/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td @@ -6764,24 +6764,18 @@ defm PseudoVID : VPseudoVID_V; let Predicates = [HasVInstructions] in { let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in { - foreach m = MxList in { - defvar mx = m.MX; - let VLMul = m.value in { - let HasSEWOp = 1, BaseInstr = VMV_X_S in - def PseudoVMV_X_S # "_" # mx: - Pseudo<(outs GPR:$rd), (ins m.vrclass:$rs2, ixlenimm:$sew), []>, - Sched<[WriteVIMovVX, ReadVIMovVX]>, - RISCVVPseudo; - let HasVLOp = 1, HasSEWOp = 1, BaseInstr = VMV_S_X, - Constraints = "$rd = $rs1" in - def PseudoVMV_S_X # "_" # mx: Pseudo<(outs m.vrclass:$rd), - (ins m.vrclass:$rs1, GPR:$rs2, - AVL:$vl, ixlenimm:$sew), - []>, - Sched<[WriteVIMovXV, ReadVIMovXV, ReadVIMovXX]>, - RISCVVPseudo; - } - } + let HasSEWOp = 1, BaseInstr = VMV_X_S in + def PseudoVMV_X_S: + Pseudo<(outs GPR:$rd), (ins VR:$rs2, ixlenimm:$sew), []>, + Sched<[WriteVIMovVX, ReadVIMovVX]>, + RISCVVPseudo; + let HasVLOp = 1, HasSEWOp = 1, BaseInstr = VMV_S_X, + Constraints = "$rd = $rs1" in + def PseudoVMV_S_X: Pseudo<(outs VR:$rd), + (ins VR:$rs1, GPR:$rs2, AVL:$vl, ixlenimm:$sew), + []>, + Sched<[WriteVIMovXV, ReadVIMovXV, ReadVIMovXX]>, + RISCVVPseudo; } } // Predicates = [HasVInstructions] @@ -7408,39 +7402,13 @@ defm : VPatNullaryV<"int_riscv_vid", "PseudoVID">; // 16.1. Integer Scalar Move Instructions //===----------------------------------------------------------------------===// -foreach vti = AllIntegerVectors in { +foreach vti = NoGroupIntegerVectors in { let Predicates = GetVTypePredicates.Predicates in def : Pat<(XLenVT (riscv_vmv_x_s (vti.Vector vti.RegClass:$rs2))), - (!cast("PseudoVMV_X_S_" # vti.LMul.MX) $rs2, vti.Log2SEW)>; + (PseudoVMV_X_S $rs2, vti.Log2SEW)>; // vmv.s.x is handled with a custom node in RISCVInstrInfoVVLPatterns.td } -//===----------------------------------------------------------------------===// -// 16.2. Floating-Point Scalar Move Instructions -//===----------------------------------------------------------------------===// - -foreach fvti = AllFloatVectors in { - let Predicates = GetVTypePredicates.Predicates in { - def : Pat<(fvti.Vector (int_riscv_vfmv_s_f (fvti.Vector fvti.RegClass:$rs1), - (fvti.Scalar fvti.ScalarRegClass:$rs2), VLOpFrag)), - (!cast("PseudoVFMV_S_"#fvti.ScalarSuffix#"_" # - fvti.LMul.MX) - (fvti.Vector $rs1), - (fvti.Scalar fvti.ScalarRegClass:$rs2), - GPR:$vl, fvti.Log2SEW)>; - - def : Pat<(fvti.Vector (int_riscv_vfmv_s_f (fvti.Vector fvti.RegClass:$rs1), - (fvti.Scalar (fpimm0)), VLOpFrag)), - (!cast("PseudoVMV_S_X_" # fvti.LMul.MX) - (fvti.Vector $rs1), (XLenVT X0), GPR:$vl, fvti.Log2SEW)>; - - def : Pat<(fvti.Vector (int_riscv_vfmv_s_f (fvti.Vector fvti.RegClass:$rs1), - (fvti.Scalar (SelectFPImm (XLenVT GPR:$imm))), VLOpFrag)), - (!cast("PseudoVMV_S_X_" # fvti.LMul.MX) - (fvti.Vector $rs1), GPR:$imm, GPR:$vl, fvti.Log2SEW)>; - } -} - //===----------------------------------------------------------------------===// // 16.3. Vector Slide Instructions //===----------------------------------------------------------------------===// diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td b/llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td index 1deb9a70946..6e7be2647e8 100644 --- a/llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td +++ b/llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td @@ -2794,16 +2794,19 @@ foreach mti = AllMasks in { // 16. Vector Permutation Instructions // 16.1. Integer Scalar Move Instructions -// 16.4. Vector Register Gather Instruction -foreach vti = AllIntegerVectors in { +foreach vti = NoGroupIntegerVectors in { let Predicates = GetVTypePredicates.Predicates in { def : Pat<(vti.Vector (riscv_vmv_s_x_vl (vti.Vector vti.RegClass:$merge), vti.ScalarRegClass:$rs1, VLOpFrag)), - (!cast("PseudoVMV_S_X_"#vti.LMul.MX) - vti.RegClass:$merge, - (vti.Scalar vti.ScalarRegClass:$rs1), GPR:$vl, vti.Log2SEW)>; + (PseudoVMV_S_X $merge, vti.ScalarRegClass:$rs1, GPR:$vl, + vti.Log2SEW)>; + } +} +// 16.4. Vector Register Gather Instruction +foreach vti = AllIntegerVectors in { + let Predicates = GetVTypePredicates.Predicates in { def : Pat<(vti.Vector (riscv_vrgather_vv_vl vti.RegClass:$rs2, vti.RegClass:$rs1, vti.RegClass:$merge, @@ -2851,18 +2854,21 @@ foreach vti = AllIntegerVectors in { } // 16.2. Floating-Point Scalar Move Instructions -foreach vti = AllFloatVectors in { +foreach vti = NoGroupFloatVectors in { let Predicates = GetVTypePredicates.Predicates in { def : Pat<(vti.Vector (riscv_vfmv_s_f_vl (vti.Vector vti.RegClass:$merge), (vti.Scalar (fpimm0)), VLOpFrag)), - (!cast("PseudoVMV_S_X_"#vti.LMul.MX) - vti.RegClass:$merge, (XLenVT X0), GPR:$vl, vti.Log2SEW)>; + (PseudoVMV_S_X $merge, (XLenVT X0), GPR:$vl, vti.Log2SEW)>; def : Pat<(vti.Vector (riscv_vfmv_s_f_vl (vti.Vector vti.RegClass:$merge), (vti.Scalar (SelectFPImm (XLenVT GPR:$imm))), VLOpFrag)), - (!cast("PseudoVMV_S_X_"#vti.LMul.MX) - vti.RegClass:$merge, GPR:$imm, GPR:$vl, vti.Log2SEW)>; + (PseudoVMV_S_X $merge, GPR:$imm, GPR:$vl, vti.Log2SEW)>; + } +} + +foreach vti = AllFloatVectors in { + let Predicates = GetVTypePredicates.Predicates in { def : Pat<(vti.Vector (riscv_vfmv_s_f_vl (vti.Vector vti.RegClass:$merge), vti.ScalarRegClass:$rs1, VLOpFrag)), diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoZfh.td b/llvm/lib/Target/RISCV/RISCVInstrInfoZfh.td index 055f1303278..2e0f754cdf7 100644 --- a/llvm/lib/Target/RISCV/RISCVInstrInfoZfh.td +++ b/llvm/lib/Target/RISCV/RISCVInstrInfoZfh.td @@ -40,30 +40,30 @@ def FPR16INX : RegisterOperand { def ZfhExt : ExtInfo<"", "", [HasStdExtZfh], f16, FPR16, FPR32, ?, FPR16>; -def ZfhminExt : ExtInfo<"", "", [HasStdExtZfhOrZfhmin], +def ZfhminExt : ExtInfo<"", "", [HasStdExtZfhmin], f16, FPR16, FPR32, ?, FPR16>; def ZfhDExt : ExtInfo<"", "", [HasStdExtZfh, HasStdExtD], ?, ?, FPR32, FPR64, FPR16>; -def ZfhminDExt : ExtInfo<"", "", [HasStdExtZfhOrZfhmin, HasStdExtD], +def ZfhminDExt : ExtInfo<"", "", [HasStdExtZfhmin, HasStdExtD], ?, ?, FPR32, FPR64, FPR16>; def ZhinxExt : ExtInfo<"_INX", "RVZfinx", [HasStdExtZhinx], f16, FPR16INX, FPR32INX, ?, FPR16INX>; def ZhinxminExt : ExtInfo<"_INX", "RVZfinx", - [HasStdExtZhinxOrZhinxmin], + [HasStdExtZhinxmin], f16, FPR16INX, FPR32INX, ?, FPR16INX>; def ZhinxZdinxExt : ExtInfo<"_INX", "RVZfinx", [HasStdExtZhinx, HasStdExtZdinx, IsRV64], ?, ?, FPR32INX, FPR64INX, FPR16INX>; def ZhinxminZdinxExt : ExtInfo<"_INX", "RVZfinx", - [HasStdExtZhinxOrZhinxmin, HasStdExtZdinx, IsRV64], + [HasStdExtZhinxmin, HasStdExtZdinx, IsRV64], ?, ?, FPR32INX, FPR64INX, FPR16INX>; def ZhinxZdinx32Ext : ExtInfo<"_IN32X", "RV32Zdinx", [HasStdExtZhinx, HasStdExtZdinx, IsRV32], ?, ?, FPR32INX, FPR64IN32X, FPR16INX >; def ZhinxminZdinx32Ext : ExtInfo<"_IN32X", "RV32Zdinx", - [HasStdExtZhinxOrZhinxmin, HasStdExtZdinx, IsRV32], + [HasStdExtZhinxmin, HasStdExtZdinx, IsRV32], ?, ?, FPR32INX, FPR64IN32X, FPR16INX>; defvar ZfhExts = [ZfhExt, ZhinxExt]; @@ -200,10 +200,10 @@ foreach Ext = ZfhminDExts in { // Assembler Pseudo Instructions (User-Level ISA, Version 2.2, Chapter 20) //===----------------------------------------------------------------------===// -let Predicates = [HasStdExtZfhOrZfhmin] in { +let Predicates = [HasStdExtZfhmin] in { def : InstAlias<"flh $rd, (${rs1})", (FLH FPR16:$rd, GPR:$rs1, 0), 0>; def : InstAlias<"fsh $rs2, (${rs1})", (FSH FPR16:$rs2, GPR:$rs1, 0), 0>; -} // Predicates = [HasStdExtZfhOrZfhmin] +} // Predicates = [HasStdExtZfhmin] let Predicates = [HasStdExtZfh] in { def : InstAlias<"fmv.h $rd, $rs", (FSGNJ_H FPR16:$rd, FPR16:$rs, FPR16:$rs)>; @@ -223,10 +223,10 @@ def PseudoQuietFLT_H : PseudoQuietFCMP; } } // Predicates = [HasStdExtZfh] -let Predicates = [HasStdExtZfhOrZfhmin] in { +let Predicates = [HasStdExtZfhmin] in { def PseudoFLH : PseudoFloatLoad<"flh", FPR16>; def PseudoFSH : PseudoStore<"fsh", FPR16>; -} // Predicates = [HasStdExtZfhOrZfhmin] +} // Predicates = [HasStdExtZfhmin] let Predicates = [HasStdExtZhinx] in { def : InstAlias<"fmv.h $rd, $rs", (FSGNJ_H_INX FPR16INX:$rd, FPR16INX:$rs, FPR16INX:$rs)>; @@ -242,7 +242,7 @@ let usesCustomInserter = 1 in { def PseudoQuietFLE_H_INX : PseudoQuietFCMP; def PseudoQuietFLT_H_INX : PseudoQuietFCMP; } -} // Predicates = [HasStdExtZhinxOrZhinxmin] +} // Predicates = [HasStdExtZhinxmin] //===----------------------------------------------------------------------===// // Pseudo-instructions and codegen patterns @@ -412,15 +412,15 @@ defm Select_FPR16INX : SelectCC_GPR_rrirr; def PseudoFROUND_H_INX : PseudoFROUND; } // Predicates = [HasStdExtZhinx] -let Predicates = [HasStdExtZfhOrZfhmin] in { +let Predicates = [HasStdExtZfhmin] in { /// Loads def : LdPat; /// Stores def : StPat; -} // Predicates = [HasStdExtZfhOrZfhmin] +} // Predicates = [HasStdExtZfhmin] -let Predicates = [HasStdExtZhinxOrZhinxmin] in { +let Predicates = [HasStdExtZhinxmin] in { /// Loads def : Pat<(f16 (load (AddrRegImm (XLenVT GPR:$rs1), simm12:$imm12))), (COPY_TO_REGCLASS (LH GPR:$rs1, simm12:$imm12), GPRF16)>; @@ -429,9 +429,9 @@ def : Pat<(f16 (load (AddrRegImm (XLenVT GPR:$rs1), simm12:$imm12))), def : Pat<(store (f16 FPR16INX:$rs2), (AddrRegImm (XLenVT GPR:$rs1), simm12:$imm12)), (SH (COPY_TO_REGCLASS FPR16INX:$rs2, GPR), GPR:$rs1, simm12:$imm12)>; -} // Predicates = [HasStdExtZhinxOrZhinxmin] +} // Predicates = [HasStdExtZhinxmin] -let Predicates = [HasStdExtZfhOrZfhmin] in { +let Predicates = [HasStdExtZfhmin] in { /// Float conversion operations // f32 -> f16, f16 -> f32 @@ -444,9 +444,9 @@ def : Pat<(riscv_fmv_x_anyexth (f16 FPR16:$src)), (FMV_X_H FPR16:$src)>; def : Pat<(riscv_fmv_x_signexth (f16 FPR16:$src)), (FMV_X_H FPR16:$src)>; def : Pat<(fcopysign FPR32:$rs1, (f16 FPR16:$rs2)), (FSGNJ_S $rs1, (FCVT_S_H $rs2, FRM_RNE))>; -} // Predicates = [HasStdExtZfhOrZfhmin] +} // Predicates = [HasStdExtZfhmin] -let Predicates = [HasStdExtZhinxOrZhinxmin] in { +let Predicates = [HasStdExtZhinxmin] in { /// Float conversion operations // f32 -> f16, f16 -> f32 @@ -459,7 +459,7 @@ def : Pat<(riscv_fmv_x_anyexth FPR16INX:$src), (COPY_TO_REGCLASS FPR16INX:$src, def : Pat<(riscv_fmv_x_signexth FPR16INX:$src), (COPY_TO_REGCLASS FPR16INX:$src, GPR)>; def : Pat<(fcopysign FPR32INX:$rs1, FPR16INX:$rs2), (FSGNJ_S_INX $rs1, (FCVT_S_H_INX $rs2, FRM_RNE))>; -} // Predicates = [HasStdExtZhinxOrZhinxmin] +} // Predicates = [HasStdExtZhinxmin] let Predicates = [HasStdExtZfh] in { // half->[u]int. Round-to-zero must be used. @@ -561,7 +561,7 @@ def : Pat<(any_sint_to_fp (i64 GPR:$rs1)), (FCVT_H_L_INX $rs1, FRM_DYN)>; def : Pat<(any_uint_to_fp (i64 GPR:$rs1)), (FCVT_H_LU_INX $rs1, FRM_DYN)>; } // Predicates = [HasStdExtZhinx, IsRV64] -let Predicates = [HasStdExtZfhOrZfhmin, HasStdExtD] in { +let Predicates = [HasStdExtZfhmin, HasStdExtD] in { /// Float conversion operations // f64 -> f16, f16 -> f64 def : Pat<(f16 (any_fpround FPR64:$rs1)), (FCVT_H_D FPR64:$rs1, FRM_DYN)>; @@ -571,9 +571,9 @@ def : Pat<(any_fpextend (f16 FPR16:$rs1)), (FCVT_D_H FPR16:$rs1, FRM_RNE)>; def : Pat<(f16 (fcopysign FPR16:$rs1, FPR64:$rs2)), (FSGNJ_H $rs1, (FCVT_H_D $rs2, FRM_DYN))>; def : Pat<(fcopysign FPR64:$rs1, (f16 FPR16:$rs2)), (FSGNJ_D $rs1, (FCVT_D_H $rs2, FRM_RNE))>; -} // Predicates = [HasStdExtZfhOrZfhmin, HasStdExtD] +} // Predicates = [HasStdExtZfhmin, HasStdExtD] -let Predicates = [HasStdExtZhinxOrZhinxmin, HasStdExtZdinx, IsRV32] in { +let Predicates = [HasStdExtZhinxmin, HasStdExtZdinx, IsRV32] in { /// Float conversion operations // f64 -> f16, f16 -> f64 def : Pat<(any_fpround FPR64IN32X:$rs1), (FCVT_H_D_IN32X FPR64IN32X:$rs1, FRM_DYN)>; @@ -583,9 +583,9 @@ def : Pat<(any_fpextend FPR16INX:$rs1), (FCVT_D_H_IN32X FPR16INX:$rs1, FRM_RNE)> def : Pat<(fcopysign FPR16INX:$rs1, FPR64IN32X:$rs2), (FSGNJ_H_INX $rs1, (FCVT_H_D_IN32X $rs2, 0b111))>; def : Pat<(fcopysign FPR64IN32X:$rs1, FPR16INX:$rs2), (FSGNJ_D_IN32X $rs1, (FCVT_D_H_IN32X $rs2, FRM_RNE))>; -} // Predicates = [HasStdExtZhinxOrZhinxmin, HasStdExtZdinx, IsRV32] +} // Predicates = [HasStdExtZhinxmin, HasStdExtZdinx, IsRV32] -let Predicates = [HasStdExtZhinxOrZhinxmin, HasStdExtZdinx, IsRV64] in { +let Predicates = [HasStdExtZhinxmin, HasStdExtZdinx, IsRV64] in { /// Float conversion operations // f64 -> f16, f16 -> f64 def : Pat<(any_fpround FPR64INX:$rs1), (FCVT_H_D_INX FPR64INX:$rs1, FRM_DYN)>; @@ -595,7 +595,7 @@ def : Pat<(any_fpextend FPR16INX:$rs1), (FCVT_D_H_INX FPR16INX:$rs1, FRM_RNE)>; def : Pat<(fcopysign FPR16INX:$rs1, FPR64INX:$rs2), (FSGNJ_H_INX $rs1, (FCVT_H_D_INX $rs2, 0b111))>; def : Pat<(fcopysign FPR64INX:$rs1, FPR16INX:$rs2), (FSGNJ_D_INX $rs1, (FCVT_D_H_INX $rs2, FRM_RNE))>; -} // Predicates = [HasStdExtZhinxOrZhinxmin, HasStdExtZdinx, IsRV64] +} // Predicates = [HasStdExtZhinxmin, HasStdExtZdinx, IsRV64] let Predicates = [HasStdExtZfhmin, NoStdExtZfh] in { // half->[u]int. Round-to-zero must be used. diff --git a/llvm/lib/Target/RISCV/RISCVMergeBaseOffset.cpp b/llvm/lib/Target/RISCV/RISCVMergeBaseOffset.cpp index ae46d5554d3..410989177a8 100644 --- a/llvm/lib/Target/RISCV/RISCVMergeBaseOffset.cpp +++ b/llvm/lib/Target/RISCV/RISCVMergeBaseOffset.cpp @@ -181,7 +181,7 @@ bool RISCVMergeBaseOffsetOpt::foldLargeOffset(MachineInstr &Hi, Register Reg = Rs == GAReg ? Rt : Rs; // Can't fold if the register has more than one use. - if (!MRI->hasOneUse(Reg)) + if (!Reg.isVirtual() || !MRI->hasOneUse(Reg)) return false; // This can point to an ADDI(W) or a LUI: MachineInstr &OffsetTail = *MRI->getVRegDef(Reg); @@ -192,9 +192,18 @@ bool RISCVMergeBaseOffsetOpt::foldLargeOffset(MachineInstr &Hi, MachineOperand &AddiImmOp = OffsetTail.getOperand(2); if (AddiImmOp.getTargetFlags() != RISCVII::MO_None) return false; + Register AddiReg = OffsetTail.getOperand(1).getReg(); int64_t OffLo = AddiImmOp.getImm(); - MachineInstr &OffsetLui = - *MRI->getVRegDef(OffsetTail.getOperand(1).getReg()); + + // Handle rs1 of ADDI is X0. + if (AddiReg == RISCV::X0) { + LLVM_DEBUG(dbgs() << " Offset Instrs: " << OffsetTail); + foldOffset(Hi, Lo, TailAdd, OffLo); + OffsetTail.eraseFromParent(); + return true; + } + + MachineInstr &OffsetLui = *MRI->getVRegDef(AddiReg); MachineOperand &LuiImmOp = OffsetLui.getOperand(1); if (OffsetLui.getOpcode() != RISCV::LUI || LuiImmOp.getTargetFlags() != RISCVII::MO_None || @@ -204,7 +213,7 @@ bool RISCVMergeBaseOffsetOpt::foldLargeOffset(MachineInstr &Hi, Offset += OffLo; // RV32 ignores the upper 32 bits. ADDIW sign extends the result. if (!ST->is64Bit() || OffsetTail.getOpcode() == RISCV::ADDIW) - Offset = SignExtend64<32>(Offset); + Offset = SignExtend64<32>(Offset); // We can only fold simm32 offsets. if (!isInt<32>(Offset)) return false; @@ -246,14 +255,14 @@ bool RISCVMergeBaseOffsetOpt::foldShiftedOffset(MachineInstr &Hi, TailShXAdd.getOpcode() == RISCV::SH3ADD) && "Expected SHXADD instruction!"); - // The first source is the shifted operand. - Register Rs1 = TailShXAdd.getOperand(1).getReg(); - if (GAReg != TailShXAdd.getOperand(2).getReg()) return false; + // The first source is the shifted operand. + Register Rs1 = TailShXAdd.getOperand(1).getReg(); + // Can't fold if the register has more than one use. - if (!MRI->hasOneUse(Rs1)) + if (!Rs1.isVirtual() || !MRI->hasOneUse(Rs1)) return false; // This can point to an ADDI X0, C. MachineInstr &OffsetTail = *MRI->getVRegDef(Rs1); @@ -360,6 +369,8 @@ bool RISCVMergeBaseOffsetOpt::foldIntoMemoryOps(MachineInstr &Hi, // Tail: lw vreg3, 8(vreg2) std::optional CommonOffset; + DenseMap> + InlineAsmMemoryOpIndexesMap; for (const MachineInstr &UseMI : MRI->use_instructions(DestReg)) { switch (UseMI.getOpcode()) { default: @@ -394,6 +405,49 @@ bool RISCVMergeBaseOffsetOpt::foldIntoMemoryOps(MachineInstr &Hi, if (CommonOffset && Offset != CommonOffset) return false; CommonOffset = Offset; + break; + } + case RISCV::INLINEASM: + case RISCV::INLINEASM_BR: { + SmallVector InlineAsmMemoryOpIndexes; + unsigned NumOps = 0; + for (unsigned I = InlineAsm::MIOp_FirstOperand; + I < UseMI.getNumOperands(); I += 1 + NumOps) { + const MachineOperand &FlagsMO = UseMI.getOperand(I); + // Should be an imm. + if (!FlagsMO.isImm()) + continue; + + const InlineAsm::Flag Flags(FlagsMO.getImm()); + NumOps = Flags.getNumOperandRegisters(); + + // Memory constraints have two operands. + if (NumOps != 2 || !Flags.isMemKind()) + continue; + + // We can't do this for constraint A because AMO instructions don't have + // an immediate offset field. + if (Flags.getMemoryConstraintID() == InlineAsm::ConstraintCode::A) + return false; + + const MachineOperand &AddrMO = UseMI.getOperand(I + 1); + if (!AddrMO.isReg() || AddrMO.getReg() != DestReg) + continue; + + const MachineOperand &OffsetMO = UseMI.getOperand(I + 2); + if (!OffsetMO.isImm()) + continue; + + // All inline asm memory operands must use the same offset. + int64_t Offset = OffsetMO.getImm(); + if (CommonOffset && Offset != CommonOffset) + return false; + CommonOffset = Offset; + InlineAsmMemoryOpIndexes.push_back(I + 1); + } + InlineAsmMemoryOpIndexesMap.insert( + std::make_pair(&UseMI, InlineAsmMemoryOpIndexes)); + break; } } } @@ -418,13 +472,36 @@ bool RISCVMergeBaseOffsetOpt::foldIntoMemoryOps(MachineInstr &Hi, // Update the immediate in the load/store instructions to add the offset. for (MachineInstr &UseMI : llvm::make_early_inc_range(MRI->use_instructions(DestReg))) { - UseMI.removeOperand(2); - UseMI.addOperand(ImmOp); - // Update the base reg in the Tail instruction to feed from LUI. - // Output of Hi is only used in Lo, no need to use MRI->replaceRegWith(). - UseMI.getOperand(1).setReg(Hi.getOperand(0).getReg()); + if (UseMI.getOpcode() == RISCV::INLINEASM || + UseMI.getOpcode() == RISCV::INLINEASM_BR) { + auto &InlineAsmMemoryOpIndexes = InlineAsmMemoryOpIndexesMap[&UseMI]; + for (unsigned I : InlineAsmMemoryOpIndexes) { + MachineOperand &MO = UseMI.getOperand(I + 1); + switch (ImmOp.getType()) { + case MachineOperand::MO_GlobalAddress: + MO.ChangeToGA(ImmOp.getGlobal(), ImmOp.getOffset(), + ImmOp.getTargetFlags()); + break; + case MachineOperand::MO_MCSymbol: + MO.ChangeToMCSymbol(ImmOp.getMCSymbol(), ImmOp.getTargetFlags()); + MO.setOffset(ImmOp.getOffset()); + break; + case MachineOperand::MO_BlockAddress: + MO.ChangeToBA(ImmOp.getBlockAddress(), ImmOp.getOffset(), + ImmOp.getTargetFlags()); + break; + default: + report_fatal_error("unsupported machine operand type"); + break; + } + } + } else { + UseMI.removeOperand(2); + UseMI.addOperand(ImmOp); + } } + MRI->replaceRegWith(Lo.getOperand(0).getReg(), Hi.getOperand(0).getReg()); Lo.eraseFromParent(); return true; } diff --git a/llvm/lib/Target/RISCV/RISCVOptWInstrs.cpp b/llvm/lib/Target/RISCV/RISCVOptWInstrs.cpp index c16eee67f3c..b7d185ab9d9 100644 --- a/llvm/lib/Target/RISCV/RISCVOptWInstrs.cpp +++ b/llvm/lib/Target/RISCV/RISCVOptWInstrs.cpp @@ -370,13 +370,7 @@ static bool isSignExtendingOpW(const MachineInstr &MI, return MI.getOperand(1).getReg() == RISCV::X0; case RISCV::PseudoAtomicLoadNand32: return true; - case RISCV::PseudoVMV_X_S_MF8: - case RISCV::PseudoVMV_X_S_MF4: - case RISCV::PseudoVMV_X_S_MF2: - case RISCV::PseudoVMV_X_S_M1: - case RISCV::PseudoVMV_X_S_M2: - case RISCV::PseudoVMV_X_S_M4: - case RISCV::PseudoVMV_X_S_M8: { + case RISCV::PseudoVMV_X_S: { // vmv.x.s has at least 33 sign bits if log2(sew) <= 5. int64_t Log2SEW = MI.getOperand(2).getImm(); assert(Log2SEW >= 3 && Log2SEW <= 6 && "Unexpected Log2SEW"); diff --git a/llvm/lib/Target/RISCV/RISCVProcessors.td b/llvm/lib/Target/RISCV/RISCVProcessors.td index 52800f08612..03ca505d100 100644 --- a/llvm/lib/Target/RISCV/RISCVProcessors.td +++ b/llvm/lib/Target/RISCV/RISCVProcessors.td @@ -215,7 +215,7 @@ def SIFIVE_X280 : RISCVProcessorModel<"sifive-x280", SiFive7Model, [TuneSiFive7, TuneDLenFactor2]>; -def SIFIVE_P450 : RISCVProcessorModel<"sifive-p450", NoSchedModel, +def SIFIVE_P450 : RISCVProcessorModel<"sifive-p450", SiFiveP400Model, [Feature64Bit, FeatureStdExtZifencei, FeatureStdExtM, @@ -223,17 +223,64 @@ def SIFIVE_P450 : RISCVProcessorModel<"sifive-p450", NoSchedModel, FeatureStdExtF, FeatureStdExtD, FeatureStdExtC, + FeatureStdExtZa64rs, + FeatureStdExtZic64b, FeatureStdExtZicbop, FeatureStdExtZicbom, FeatureStdExtZicboz, + FeatureStdExtZiccamoa, + FeatureStdExtZiccif, + FeatureStdExtZicclsm, + FeatureStdExtZiccrse, FeatureStdExtZihintntl, FeatureStdExtZihintpause, FeatureStdExtZihpm, FeatureStdExtZba, FeatureStdExtZbb, FeatureStdExtZbs, - FeatureStdExtZfhmin], - [TuneConditionalCompressedMoveFusion]>; + FeatureStdExtZfhmin, + FeatureFastUnalignedAccess], + [TuneNoDefaultUnroll, + TuneConditionalCompressedMoveFusion, + TuneLUIADDIFusion, + TuneAUIPCADDIFusion]>; + +def SIFIVE_P670 : RISCVProcessorModel<"sifive-p670", NoSchedModel, + [Feature64Bit, + FeatureStdExtZifencei, + FeatureStdExtM, + FeatureStdExtA, + FeatureStdExtF, + FeatureStdExtD, + FeatureStdExtC, + FeatureStdExtZa64rs, + FeatureStdExtZic64b, + FeatureStdExtZicbop, + FeatureStdExtZicbom, + FeatureStdExtZicboz, + FeatureStdExtZiccamoa, + FeatureStdExtZiccif, + FeatureStdExtZicclsm, + FeatureStdExtZiccrse, + FeatureStdExtZihintntl, + FeatureStdExtZihintpause, + FeatureStdExtZihpm, + FeatureStdExtZba, + FeatureStdExtZbb, + FeatureStdExtZbs, + FeatureStdExtZfhmin, + FeatureStdExtV, + FeatureStdExtZvl128b, + FeatureStdExtZvbb, + FeatureStdExtZvknc, + FeatureStdExtZvkng, + FeatureStdExtZvksc, + FeatureStdExtZvksg, + FeatureFastUnalignedAccess], + [TuneNoDefaultUnroll, + TuneConditionalCompressedMoveFusion, + TuneLUIADDIFusion, + TuneAUIPCADDIFusion]>; def SYNTACORE_SCR1_BASE : RISCVProcessorModel<"syntacore-scr1-base", SyntacoreSCR1Model, diff --git a/llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp b/llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp index 24f8d600f1e..d7bb46a221d 100644 --- a/llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp +++ b/llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp @@ -63,13 +63,18 @@ RISCVRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const { if (Subtarget.hasStdExtD()) return CSR_XLEN_F64_Interrupt_SaveList; if (Subtarget.hasStdExtF()) - return CSR_XLEN_F32_Interrupt_SaveList; - return CSR_Interrupt_SaveList; + return Subtarget.isRVE() ? CSR_XLEN_F32_Interrupt_RVE_SaveList + : CSR_XLEN_F32_Interrupt_SaveList; + return Subtarget.isRVE() ? CSR_Interrupt_RVE_SaveList + : CSR_Interrupt_SaveList; } switch (Subtarget.getTargetABI()) { default: llvm_unreachable("Unrecognized ABI"); + case RISCVABI::ABI_ILP32E: + case RISCVABI::ABI_LP64E: + return CSR_ILP32E_LP64E_SaveList; case RISCVABI::ABI_ILP32: case RISCVABI::ABI_LP64: return CSR_ILP32_LP64_SaveList; @@ -109,6 +114,11 @@ BitVector RISCVRegisterInfo::getReservedRegs(const MachineFunction &MF) const { // beginning with 'x0' for instructions that take register pairs. markSuperRegs(Reserved, RISCV::DUMMY_REG_PAIR_WITH_X0); + // There are only 16 GPRs for RVE. + if (Subtarget.isRVE()) + for (MCPhysReg Reg = RISCV::X16; Reg <= RISCV::X31; Reg++) + markSuperRegs(Reserved, Reg); + // V registers for code generation. We handle them manually. markSuperRegs(Reserved, RISCV::VL); markSuperRegs(Reserved, RISCV::VTYPE); @@ -270,8 +280,9 @@ void RISCVRegisterInfo::lowerVSPILL(MachineBasicBlock::iterator II) const { MachineBasicBlock &MBB = *II->getParent(); MachineFunction &MF = *MBB.getParent(); MachineRegisterInfo &MRI = MF.getRegInfo(); - const TargetInstrInfo *TII = MF.getSubtarget().getInstrInfo(); - const TargetRegisterInfo *TRI = MF.getSubtarget().getRegisterInfo(); + const RISCVSubtarget &STI = MF.getSubtarget(); + const TargetInstrInfo *TII = STI.getInstrInfo(); + const TargetRegisterInfo *TRI = STI.getRegisterInfo(); auto ZvlssegInfo = RISCV::isRVVSpillForZvlsseg(II->getOpcode()); unsigned NF = ZvlssegInfo->first; @@ -303,7 +314,6 @@ void RISCVRegisterInfo::lowerVSPILL(MachineBasicBlock::iterator II) const { Register VL = MRI.createVirtualRegister(&RISCV::GPRRegClass); // Optimize for constant VLEN. - const RISCVSubtarget &STI = MF.getSubtarget(); if (STI.getRealMinVLen() == STI.getRealMaxVLen()) { const int64_t VLENB = STI.getRealMinVLen() / 8; int64_t Offset = VLENB * LMUL; @@ -347,8 +357,9 @@ void RISCVRegisterInfo::lowerVRELOAD(MachineBasicBlock::iterator II) const { MachineBasicBlock &MBB = *II->getParent(); MachineFunction &MF = *MBB.getParent(); MachineRegisterInfo &MRI = MF.getRegInfo(); - const TargetInstrInfo *TII = MF.getSubtarget().getInstrInfo(); - const TargetRegisterInfo *TRI = MF.getSubtarget().getRegisterInfo(); + const RISCVSubtarget &STI = MF.getSubtarget(); + const TargetInstrInfo *TII = STI.getInstrInfo(); + const TargetRegisterInfo *TRI = STI.getRegisterInfo(); auto ZvlssegInfo = RISCV::isRVVSpillForZvlsseg(II->getOpcode()); unsigned NF = ZvlssegInfo->first; @@ -380,7 +391,6 @@ void RISCVRegisterInfo::lowerVRELOAD(MachineBasicBlock::iterator II) const { Register VL = MRI.createVirtualRegister(&RISCV::GPRRegClass); // Optimize for constant VLEN. - const RISCVSubtarget &STI = MF.getSubtarget(); if (STI.getRealMinVLen() == STI.getRealMaxVLen()) { const int64_t VLENB = STI.getRealMinVLen() / 8; int64_t Offset = VLENB * LMUL; @@ -673,6 +683,9 @@ RISCVRegisterInfo::getCallPreservedMask(const MachineFunction & MF, switch (Subtarget.getTargetABI()) { default: llvm_unreachable("Unrecognized ABI"); + case RISCVABI::ABI_ILP32E: + case RISCVABI::ABI_LP64E: + return CSR_ILP32E_LP64E_RegMask; case RISCVABI::ABI_ILP32: case RISCVABI::ABI_LP64: return CSR_ILP32_LP64_RegMask; @@ -740,6 +753,7 @@ bool RISCVRegisterInfo::getRegAllocationHints( SmallVectorImpl &Hints, const MachineFunction &MF, const VirtRegMap *VRM, const LiveRegMatrix *Matrix) const { const MachineRegisterInfo *MRI = &MF.getRegInfo(); + auto &Subtarget = MF.getSubtarget(); bool BaseImplRetVal = TargetRegisterInfo::getRegAllocationHints( VirtReg, Order, Hints, MF, VRM, Matrix); @@ -763,7 +777,7 @@ bool RISCVRegisterInfo::getRegAllocationHints( // This is all of the compressible binary instructions. If an instruction // needs GPRC register class operands \p NeedGPRC will be set to true. - auto isCompressible = [](const MachineInstr &MI, bool &NeedGPRC) { + auto isCompressible = [&Subtarget](const MachineInstr &MI, bool &NeedGPRC) { NeedGPRC = false; switch (MI.getOpcode()) { default: @@ -776,9 +790,16 @@ bool RISCVRegisterInfo::getRegAllocationHints( case RISCV::SUBW: NeedGPRC = true; return true; - case RISCV::ANDI: + case RISCV::ANDI: { NeedGPRC = true; - return MI.getOperand(2).isImm() && isInt<6>(MI.getOperand(2).getImm()); + if (!MI.getOperand(2).isImm()) + return false; + int64_t Imm = MI.getOperand(2).getImm(); + if (isInt<6>(Imm)) + return true; + // c.zext.b + return Subtarget.hasStdExtZcb() && Imm == 255; + } case RISCV::SRAI: case RISCV::SRLI: NeedGPRC = true; @@ -789,6 +810,24 @@ bool RISCVRegisterInfo::getRegAllocationHints( case RISCV::ADDI: case RISCV::ADDIW: return MI.getOperand(2).isImm() && isInt<6>(MI.getOperand(2).getImm()); + case RISCV::MUL: + case RISCV::SEXT_B: + case RISCV::SEXT_H: + case RISCV::ZEXT_H_RV32: + case RISCV::ZEXT_H_RV64: + // c.mul, c.sext.b, c.sext.h, c.zext.h + NeedGPRC = true; + return Subtarget.hasStdExtZcb(); + case RISCV::ADD_UW: + // c.zext.w + NeedGPRC = true; + return Subtarget.hasStdExtZcb() && MI.getOperand(2).isReg() && + MI.getOperand(2).getReg() == RISCV::X0; + case RISCV::XORI: + // c.not + NeedGPRC = true; + return Subtarget.hasStdExtZcb() && MI.getOperand(2).isImm() && + MI.getOperand(2).getImm() == -1; } }; @@ -810,13 +849,15 @@ bool RISCVRegisterInfo::getRegAllocationHints( bool NeedGPRC; if (isCompressible(MI, NeedGPRC)) { if (OpIdx == 0 && MI.getOperand(1).isReg()) { - if (!NeedGPRC || isCompressibleOpnd(MI.getOperand(2))) + if (!NeedGPRC || MI.getNumExplicitOperands() < 3 || + MI.getOpcode() == RISCV::ADD_UW || + isCompressibleOpnd(MI.getOperand(2))) tryAddHint(MO, MI.getOperand(1), NeedGPRC); if (MI.isCommutable() && MI.getOperand(2).isReg() && (!NeedGPRC || isCompressibleOpnd(MI.getOperand(1)))) tryAddHint(MO, MI.getOperand(2), NeedGPRC); - } else if (OpIdx == 1 && - (!NeedGPRC || isCompressibleOpnd(MI.getOperand(2)))) { + } else if (OpIdx == 1 && (!NeedGPRC || MI.getNumExplicitOperands() < 3 || + isCompressibleOpnd(MI.getOperand(2)))) { tryAddHint(MO, MI.getOperand(0), NeedGPRC); } else if (MI.isCommutable() && OpIdx == 2 && (!NeedGPRC || isCompressibleOpnd(MI.getOperand(1)))) { diff --git a/llvm/lib/Target/RISCV/RISCVSchedSiFiveP400.td b/llvm/lib/Target/RISCV/RISCVSchedSiFiveP400.td new file mode 100644 index 00000000000..02fff5b52bb --- /dev/null +++ b/llvm/lib/Target/RISCV/RISCVSchedSiFiveP400.td @@ -0,0 +1,354 @@ +//==- RISCVSchedSiFiveP400.td - SiFiveP400 Scheduling Defs ---*- tablegen -*-=// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +//===----------------------------------------------------------------------===// + +def SiFiveP400Model : SchedMachineModel { + let IssueWidth = 3; // 3 micro-ops are dispatched per cycle. + let MicroOpBufferSize = 56; // Max micro-ops that can be buffered. + let LoadLatency = 4; // Cycles for loads to access the cache. + let MispredictPenalty = 9; // Extra cycles for a mispredicted branch. + let PostRAScheduler = true; + let UnsupportedFeatures = [HasStdExtZbkb, HasStdExtZbkc, HasStdExtZbkx, + HasStdExtZcmt, HasStdExtZknd, HasStdExtZkne, + HasStdExtZknh, HasStdExtZksed, HasStdExtZksh, + HasStdExtZkr]; + let CompleteModel = false; +} + +// The SiFiveP400 microarchitecure has 6 pipelines: +// Three pipelines for integer operations. +// One pipeline for FPU operations. +// One pipeline for Load operations. +// One pipeline for Store operations. +let SchedModel = SiFiveP400Model in { + +def SiFiveP400IEXQ0 : ProcResource<1>; +def SiFiveP400IEXQ1 : ProcResource<1>; +def SiFiveP400IEXQ2 : ProcResource<1>; +def SiFiveP400FEXQ0 : ProcResource<1>; +def SiFiveP400Load : ProcResource<1>; +def SiFiveP400Store : ProcResource<1>; + +def SiFiveP400IntArith : ProcResGroup<[SiFiveP400IEXQ0, SiFiveP400IEXQ1, SiFiveP400IEXQ2]>; +defvar SiFiveP400Branch = SiFiveP400IEXQ0; +defvar SiFiveP400SYS = SiFiveP400IEXQ1; +defvar SiFiveP400MulDiv = SiFiveP400IEXQ2; +defvar SiFiveP400I2F = SiFiveP400IEXQ2; +def SiFiveP400Div : ProcResource<1>; + +defvar SiFiveP400FloatArith = SiFiveP400FEXQ0; +defvar SiFiveP400F2I = SiFiveP400FEXQ0; +def SiFiveP400FloatDiv : ProcResource<1>; + +let Latency = 1 in { +// Integer arithmetic and logic +def : WriteRes; +def : WriteRes; +def : WriteRes; +def : WriteRes; +def : WriteRes; +def : WriteRes; +// Branching +def : WriteRes; +def : WriteRes; +def : WriteRes; +} + +// CMOV +def P400WriteCMOV : SchedWriteRes<[SiFiveP400Branch, SiFiveP400IEXQ1]> { + let Latency = 2; + let NumMicroOps = 2; +} +def : InstRW<[P400WriteCMOV], (instrs PseudoCCMOVGPRNoX0)>; + +let Latency = 3 in { +// Integer multiplication +def : WriteRes; +def : WriteRes; +// cpop[w] look exactly like multiply. +def : WriteRes; +def : WriteRes; +} + +// Integer division +def : WriteRes { + let Latency = 35; + let ReleaseAtCycles = [1, 34]; +} +def : WriteRes { + let Latency = 20; + let ReleaseAtCycles = [1, 19]; +} + +let Latency = 1 in { +// Bitmanip +def : WriteRes; +def : WriteRes; +def : WriteRes; +def : WriteRes; + +def : WriteRes; +def : WriteRes; +def : WriteRes; +def : WriteRes; + +def : WriteRes; + +def : WriteRes; + +def : WriteRes; +def : WriteRes; + +def : WriteRes; +def : WriteRes; +def : WriteRes; +def : WriteRes; +} + +// Memory +let Latency = 1 in { +def : WriteRes; +def : WriteRes; +def : WriteRes; +def : WriteRes; +def : WriteRes; +def : WriteRes; +def : WriteRes; +} +let Latency = 4 in { +def : WriteRes; +def : WriteRes; +} +let Latency = 4 in { +def : WriteRes; +def : WriteRes; +} + +let Latency = 6 in { +def : WriteRes; +def : WriteRes; +def : WriteRes; +} + +// Atomic memory +let Latency = 3 in { +def : WriteRes; +def : WriteRes; +def : WriteRes; +def : WriteRes; +def : WriteRes; +def : WriteRes; +} + +// Floating point +let Latency = 4 in { +def : WriteRes; +def : WriteRes; +def : WriteRes; + +def : WriteRes; +def : WriteRes; +def : WriteRes; + +def : WriteRes; +def : WriteRes; +def : WriteRes; +} + +let Latency = 2 in { +def : WriteRes; +def : WriteRes; +def : WriteRes; + +def : WriteRes; +def : WriteRes; +def : WriteRes; +} + +// Half precision. +def : WriteRes { + let Latency = 19; + let ReleaseAtCycles = [1, 18]; +} +def : WriteRes { + let Latency = 18; + let ReleaseAtCycles = [1, 17]; +} + +// Single precision. +def : WriteRes { + let Latency = 19; + let ReleaseAtCycles = [1, 18]; +} +def : WriteRes { + let Latency = 18; + let ReleaseAtCycles = [1, 17]; +} + +// Double precision +def : WriteRes { + let Latency = 33; + let ReleaseAtCycles = [1, 32]; +} +def : WriteRes { + let Latency = 33; + let ReleaseAtCycles = [1, 32]; +} + +// Conversions +let Latency = 2 in { +def : WriteRes; +def : WriteRes; +def : WriteRes; +def : WriteRes; +def : WriteRes; +def : WriteRes; +def : WriteRes; +def : WriteRes; +def : WriteRes; +def : WriteRes; +def : WriteRes; +def : WriteRes; +def : WriteRes; +def : WriteRes; +def : WriteRes; +def : WriteRes; +def : WriteRes; +def : WriteRes; + +def : WriteRes; +def : WriteRes; +def : WriteRes; +def : WriteRes; +def : WriteRes; +def : WriteRes; +def : WriteRes; +def : WriteRes; +def : WriteRes; +def : WriteRes; +def : WriteRes; +def : WriteRes; +} + +// Others +def : WriteRes; +def : WriteRes; + +// FIXME: This could be better modeled by looking at the regclasses of the operands. +def : InstRW<[WriteIALU, ReadIALU], (instrs COPY)>; + +//===----------------------------------------------------------------------===// +// Bypass and advance +def : ReadAdvance; +def : ReadAdvance; +def : ReadAdvance; +def : ReadAdvance; +def : ReadAdvance; +def : ReadAdvance; +def : ReadAdvance; +def : ReadAdvance; +def : ReadAdvance; +def : ReadAdvance; +def : ReadAdvance; +def : ReadAdvance; +def : ReadAdvance; +def : ReadAdvance; +def : ReadAdvance; +def : ReadAdvance; +def : ReadAdvance; +def : ReadAdvance; +def : ReadAdvance; +def : ReadAdvance; +def : ReadAdvance; +def : ReadAdvance; +def : ReadAdvance; +def : ReadAdvance; +def : ReadAdvance; +def : ReadAdvance; +def : ReadAdvance; +def : ReadAdvance; +def : ReadAdvance; +def : ReadAdvance; +def : ReadAdvance; +def : ReadAdvance; +def : ReadAdvance; +def : ReadAdvance; +def : ReadAdvance; +def : ReadAdvance; +def : ReadAdvance; +def : ReadAdvance; +def : ReadAdvance; +def : ReadAdvance; +def : ReadAdvance; +def : ReadAdvance; +def : ReadAdvance; +def : ReadAdvance; +def : ReadAdvance; +def : ReadAdvance; +def : ReadAdvance; +def : ReadAdvance; +def : ReadAdvance; +def : ReadAdvance; +def : ReadAdvance; +def : ReadAdvance; +def : ReadAdvance; +def : ReadAdvance; +def : ReadAdvance; +def : ReadAdvance; +def : ReadAdvance; +def : ReadAdvance; +def : ReadAdvance; +def : ReadAdvance; +def : ReadAdvance; +def : ReadAdvance; +def : ReadAdvance; +def : ReadAdvance; +def : ReadAdvance; +def : ReadAdvance; +def : ReadAdvance; +def : ReadAdvance; +def : ReadAdvance; +def : ReadAdvance; +def : ReadAdvance; +def : ReadAdvance; +def : ReadAdvance; +def : ReadAdvance; +def : ReadAdvance; +def : ReadAdvance; +def : ReadAdvance; +def : ReadAdvance; +def : ReadAdvance; + +// Bitmanip +def : ReadAdvance; +def : ReadAdvance; +def : ReadAdvance; +def : ReadAdvance; +def : ReadAdvance; +def : ReadAdvance; +def : ReadAdvance; +def : ReadAdvance; +def : ReadAdvance; +def : ReadAdvance; +def : ReadAdvance; +def : ReadAdvance; +def : ReadAdvance; +def : ReadAdvance; +def : ReadAdvance; +def : ReadAdvance; + +//===----------------------------------------------------------------------===// +// Unsupported extensions +defm : UnsupportedSchedZbc; +defm : UnsupportedSchedZbkb; +defm : UnsupportedSchedZbkx; +defm : UnsupportedSchedSFB; +defm : UnsupportedSchedZfa; +defm : UnsupportedSchedV; +} diff --git a/llvm/lib/Target/RISCV/RISCVTargetMachine.cpp b/llvm/lib/Target/RISCV/RISCVTargetMachine.cpp index 3abdb600365..b4b81b545a5 100644 --- a/llvm/lib/Target/RISCV/RISCVTargetMachine.cpp +++ b/llvm/lib/Target/RISCV/RISCVTargetMachine.cpp @@ -128,10 +128,20 @@ extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeRISCVTarget() { initializeRISCVPushPopOptPass(*PR); } -static StringRef computeDataLayout(const Triple &TT) { - if (TT.isArch64Bit()) +static StringRef computeDataLayout(const Triple &TT, + const TargetOptions &Options) { + StringRef ABIName = Options.MCOptions.getABIName(); + if (TT.isArch64Bit()) { + if (ABIName == "lp64e") + return "e-m:e-p:64:64-i64:64-i128:128-n32:64-S64"; + return "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"; + } assert(TT.isArch32Bit() && "only RV32 and RV64 are currently supported"); + + if (ABIName == "ilp32e") + return "e-m:e-p:32:32-i64:64-n32-S32"; + return "e-m:e-p:32:32-i64:64-n32-S128"; } @@ -146,7 +156,7 @@ RISCVTargetMachine::RISCVTargetMachine(const Target &T, const Triple &TT, std::optional RM, std::optional CM, CodeGenOptLevel OL, bool JIT) - : LLVMTargetMachine(T, computeDataLayout(TT), TT, CPU, FS, Options, + : LLVMTargetMachine(T, computeDataLayout(TT, Options), TT, CPU, FS, Options, getEffectiveRelocModel(TT, RM), getEffectiveCodeModel(CM, CodeModel::Small), OL), TLOF(std::make_unique()) { @@ -348,7 +358,8 @@ public: ScheduleDAGMILive *DAG = nullptr; if (EnableMISchedLoadClustering) { DAG = createGenericSchedLive(C); - DAG->addMutation(createLoadClusterDAGMutation(DAG->TII, DAG->TRI)); + DAG->addMutation(createLoadClusterDAGMutation( + DAG->TII, DAG->TRI, /*ReorderWhileClustering=*/true)); } if (ST.hasMacroFusion()) { DAG = DAG ? DAG : createGenericSchedLive(C); diff --git a/llvm/lib/Target/RISCV/RISCVTargetObjectFile.cpp b/llvm/lib/Target/RISCV/RISCVTargetObjectFile.cpp index 7c9e57e6eef..1535149b919 100644 --- a/llvm/lib/Target/RISCV/RISCVTargetObjectFile.cpp +++ b/llvm/lib/Target/RISCV/RISCVTargetObjectFile.cpp @@ -12,6 +12,7 @@ #include "llvm/BinaryFormat/ELF.h" #include "llvm/MC/MCContext.h" #include "llvm/MC/MCSectionELF.h" +#include "llvm/MC/MCValue.h" using namespace llvm; @@ -25,6 +26,7 @@ void RISCVELFTargetObjectFile::Initialize(MCContext &Ctx, TargetLoweringObjectFileELF::Initialize(Ctx, TM); PLTRelativeVariantKind = MCSymbolRefExpr::VK_PLT; + SupportIndirectSymViaGOTPCRel = true; SmallDataSection = getContext().getELFSection( ".sdata", ELF::SHT_PROGBITS, ELF::SHF_WRITE | ELF::SHF_ALLOC); @@ -32,6 +34,16 @@ void RISCVELFTargetObjectFile::Initialize(MCContext &Ctx, ELF::SHF_WRITE | ELF::SHF_ALLOC); } +const MCExpr *RISCVELFTargetObjectFile::getIndirectSymViaGOTPCRel( + const GlobalValue *GV, const MCSymbol *Sym, const MCValue &MV, + int64_t Offset, MachineModuleInfo *MMI, MCStreamer &Streamer) const { + int64_t FinalOffset = Offset + MV.getConstant(); + const MCExpr *Res = + MCSymbolRefExpr::create(Sym, MCSymbolRefExpr::VK_GOTPCREL, getContext()); + const MCExpr *Off = MCConstantExpr::create(FinalOffset, getContext()); + return MCBinaryExpr::createAdd(Res, Off, getContext()); +} + // A address must be loaded from a small section if its size is less than the // small section size threshold. Data in this section could be addressed by // using gp_rel operator. diff --git a/llvm/lib/Target/RISCV/RISCVTargetObjectFile.h b/llvm/lib/Target/RISCV/RISCVTargetObjectFile.h index 890effd0732..0910fbd3d95 100644 --- a/llvm/lib/Target/RISCV/RISCVTargetObjectFile.h +++ b/llvm/lib/Target/RISCV/RISCVTargetObjectFile.h @@ -42,6 +42,12 @@ public: void getModuleMetadata(Module &M) override; bool isInSmallSection(uint64_t Size) const; + + const MCExpr *getIndirectSymViaGOTPCRel(const GlobalValue *GV, + const MCSymbol *Sym, + const MCValue &MV, int64_t Offset, + MachineModuleInfo *MMI, + MCStreamer &Streamer) const override; }; } // end namespace llvm diff --git a/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp b/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp index b3916c98700..866d5cf340e 100644 --- a/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp +++ b/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp @@ -84,8 +84,10 @@ RISCVTTIImpl::getRISCVInstructionCost(ArrayRef OpCodes, MVT VT, Cost += VL; break; } + case RISCV::VMV_X_S: case RISCV::VMV_S_X: - // FIXME: VMV_S_X doesn't use LMUL, the cost should be 1 + Cost += 1; + break; default: Cost += LMULCost; } @@ -443,10 +445,13 @@ InstructionCost RISCVTTIImpl::getShuffleCost(TTI::ShuffleKind Kind, // vsetivli zero, 8, e8, mf2, ta, ma (ignored) // vmv.s.x v0, a0 // vmerge.vvm v8, v9, v8, v0 + // We use 2 for the cost of the mask materialization as this is the true + // cost for small masks and most shuffles are small. At worst, this cost + // should be a very small constant for the constant pool load. As such, + // we may bias towards large selects slightly more than truely warranted. return LT.first * - (TLI->getLMULCost(LT.second) + // FIXME: should be 1 for li - getRISCVInstructionCost({RISCV::VMV_S_X, RISCV::VMERGE_VVM}, - LT.second, CostKind)); + (1 + getRISCVInstructionCost({RISCV::VMV_S_X, RISCV::VMERGE_VVM}, + LT.second, CostKind)); } case TTI::SK_Broadcast: { bool HasScalar = (Args.size() > 0) && (Operator::getOpcode(Args[0]) == @@ -474,10 +479,9 @@ InstructionCost RISCVTTIImpl::getShuffleCost(TTI::ShuffleKind Kind, return LT.first * (TLI->getLMULCost(LT.second) + // FIXME: this should be 1 for andi - TLI->getLMULCost( - LT.second) + // FIXME: vmv.x.s is the same as extractelement getRISCVInstructionCost({RISCV::VMV_V_I, RISCV::VMERGE_VIM, - RISCV::VMV_V_X, RISCV::VMSNE_VI}, + RISCV::VMV_X_S, RISCV::VMV_V_X, + RISCV::VMSNE_VI}, LT.second, CostKind)); } @@ -655,494 +659,61 @@ InstructionCost RISCVTTIImpl::getGatherScatterOpCost( // instruction counts with the following adjustments made: // * One vsetvli is considered free. static const CostTblEntry VectorIntrinsicCostTable[]{ - {Intrinsic::floor, MVT::v2f32, 9}, - {Intrinsic::floor, MVT::v4f32, 9}, - {Intrinsic::floor, MVT::v8f32, 9}, - {Intrinsic::floor, MVT::v16f32, 9}, - {Intrinsic::floor, MVT::nxv1f32, 9}, - {Intrinsic::floor, MVT::nxv2f32, 9}, - {Intrinsic::floor, MVT::nxv4f32, 9}, - {Intrinsic::floor, MVT::nxv8f32, 9}, - {Intrinsic::floor, MVT::nxv16f32, 9}, - {Intrinsic::floor, MVT::v2f64, 9}, - {Intrinsic::floor, MVT::v4f64, 9}, - {Intrinsic::floor, MVT::v8f64, 9}, - {Intrinsic::floor, MVT::v16f64, 9}, - {Intrinsic::floor, MVT::nxv1f64, 9}, - {Intrinsic::floor, MVT::nxv2f64, 9}, - {Intrinsic::floor, MVT::nxv4f64, 9}, - {Intrinsic::floor, MVT::nxv8f64, 9}, - {Intrinsic::ceil, MVT::v2f32, 9}, - {Intrinsic::ceil, MVT::v4f32, 9}, - {Intrinsic::ceil, MVT::v8f32, 9}, - {Intrinsic::ceil, MVT::v16f32, 9}, - {Intrinsic::ceil, MVT::nxv1f32, 9}, - {Intrinsic::ceil, MVT::nxv2f32, 9}, - {Intrinsic::ceil, MVT::nxv4f32, 9}, - {Intrinsic::ceil, MVT::nxv8f32, 9}, - {Intrinsic::ceil, MVT::nxv16f32, 9}, - {Intrinsic::ceil, MVT::v2f64, 9}, - {Intrinsic::ceil, MVT::v4f64, 9}, - {Intrinsic::ceil, MVT::v8f64, 9}, - {Intrinsic::ceil, MVT::v16f64, 9}, - {Intrinsic::ceil, MVT::nxv1f64, 9}, - {Intrinsic::ceil, MVT::nxv2f64, 9}, - {Intrinsic::ceil, MVT::nxv4f64, 9}, - {Intrinsic::ceil, MVT::nxv8f64, 9}, - {Intrinsic::trunc, MVT::v2f32, 7}, - {Intrinsic::trunc, MVT::v4f32, 7}, - {Intrinsic::trunc, MVT::v8f32, 7}, - {Intrinsic::trunc, MVT::v16f32, 7}, - {Intrinsic::trunc, MVT::nxv1f32, 7}, - {Intrinsic::trunc, MVT::nxv2f32, 7}, - {Intrinsic::trunc, MVT::nxv4f32, 7}, - {Intrinsic::trunc, MVT::nxv8f32, 7}, - {Intrinsic::trunc, MVT::nxv16f32, 7}, - {Intrinsic::trunc, MVT::v2f64, 7}, - {Intrinsic::trunc, MVT::v4f64, 7}, - {Intrinsic::trunc, MVT::v8f64, 7}, - {Intrinsic::trunc, MVT::v16f64, 7}, - {Intrinsic::trunc, MVT::nxv1f64, 7}, - {Intrinsic::trunc, MVT::nxv2f64, 7}, - {Intrinsic::trunc, MVT::nxv4f64, 7}, - {Intrinsic::trunc, MVT::nxv8f64, 7}, - {Intrinsic::round, MVT::v2f32, 9}, - {Intrinsic::round, MVT::v4f32, 9}, - {Intrinsic::round, MVT::v8f32, 9}, - {Intrinsic::round, MVT::v16f32, 9}, - {Intrinsic::round, MVT::nxv1f32, 9}, - {Intrinsic::round, MVT::nxv2f32, 9}, - {Intrinsic::round, MVT::nxv4f32, 9}, - {Intrinsic::round, MVT::nxv8f32, 9}, - {Intrinsic::round, MVT::nxv16f32, 9}, - {Intrinsic::round, MVT::v2f64, 9}, - {Intrinsic::round, MVT::v4f64, 9}, - {Intrinsic::round, MVT::v8f64, 9}, - {Intrinsic::round, MVT::v16f64, 9}, - {Intrinsic::round, MVT::nxv1f64, 9}, - {Intrinsic::round, MVT::nxv2f64, 9}, - {Intrinsic::round, MVT::nxv4f64, 9}, - {Intrinsic::round, MVT::nxv8f64, 9}, - {Intrinsic::roundeven, MVT::v2f32, 9}, - {Intrinsic::roundeven, MVT::v4f32, 9}, - {Intrinsic::roundeven, MVT::v8f32, 9}, - {Intrinsic::roundeven, MVT::v16f32, 9}, - {Intrinsic::roundeven, MVT::nxv1f32, 9}, - {Intrinsic::roundeven, MVT::nxv2f32, 9}, - {Intrinsic::roundeven, MVT::nxv4f32, 9}, - {Intrinsic::roundeven, MVT::nxv8f32, 9}, - {Intrinsic::roundeven, MVT::nxv16f32, 9}, - {Intrinsic::roundeven, MVT::v2f64, 9}, - {Intrinsic::roundeven, MVT::v4f64, 9}, - {Intrinsic::roundeven, MVT::v8f64, 9}, - {Intrinsic::roundeven, MVT::v16f64, 9}, - {Intrinsic::roundeven, MVT::nxv1f64, 9}, - {Intrinsic::roundeven, MVT::nxv2f64, 9}, - {Intrinsic::roundeven, MVT::nxv4f64, 9}, - {Intrinsic::roundeven, MVT::nxv8f64, 9}, - {Intrinsic::rint, MVT::v2f32, 7}, - {Intrinsic::rint, MVT::v4f32, 7}, - {Intrinsic::rint, MVT::v8f32, 7}, - {Intrinsic::rint, MVT::v16f32, 7}, - {Intrinsic::rint, MVT::nxv1f32, 7}, - {Intrinsic::rint, MVT::nxv2f32, 7}, - {Intrinsic::rint, MVT::nxv4f32, 7}, - {Intrinsic::rint, MVT::nxv8f32, 7}, - {Intrinsic::rint, MVT::nxv16f32, 7}, - {Intrinsic::rint, MVT::v2f64, 7}, - {Intrinsic::rint, MVT::v4f64, 7}, - {Intrinsic::rint, MVT::v8f64, 7}, - {Intrinsic::rint, MVT::v16f64, 7}, - {Intrinsic::rint, MVT::nxv1f64, 7}, - {Intrinsic::rint, MVT::nxv2f64, 7}, - {Intrinsic::rint, MVT::nxv4f64, 7}, - {Intrinsic::rint, MVT::nxv8f64, 7}, - {Intrinsic::lrint, MVT::v2i32, 1}, - {Intrinsic::lrint, MVT::v4i32, 1}, - {Intrinsic::lrint, MVT::v8i32, 1}, - {Intrinsic::lrint, MVT::v16i32, 1}, - {Intrinsic::lrint, MVT::nxv1i32, 1}, - {Intrinsic::lrint, MVT::nxv2i32, 1}, - {Intrinsic::lrint, MVT::nxv4i32, 1}, - {Intrinsic::lrint, MVT::nxv8i32, 1}, - {Intrinsic::lrint, MVT::nxv16i32, 1}, - {Intrinsic::lrint, MVT::v2i64, 1}, - {Intrinsic::lrint, MVT::v4i64, 1}, - {Intrinsic::lrint, MVT::v8i64, 1}, - {Intrinsic::lrint, MVT::v16i64, 1}, - {Intrinsic::lrint, MVT::nxv1i64, 1}, - {Intrinsic::lrint, MVT::nxv2i64, 1}, - {Intrinsic::lrint, MVT::nxv4i64, 1}, - {Intrinsic::lrint, MVT::nxv8i64, 1}, - {Intrinsic::llrint, MVT::v2i64, 1}, - {Intrinsic::llrint, MVT::v4i64, 1}, - {Intrinsic::llrint, MVT::v8i64, 1}, - {Intrinsic::llrint, MVT::v16i64, 1}, - {Intrinsic::llrint, MVT::nxv1i64, 1}, - {Intrinsic::llrint, MVT::nxv2i64, 1}, - {Intrinsic::llrint, MVT::nxv4i64, 1}, - {Intrinsic::llrint, MVT::nxv8i64, 1}, - {Intrinsic::nearbyint, MVT::v2f32, 9}, - {Intrinsic::nearbyint, MVT::v4f32, 9}, - {Intrinsic::nearbyint, MVT::v8f32, 9}, - {Intrinsic::nearbyint, MVT::v16f32, 9}, - {Intrinsic::nearbyint, MVT::nxv1f32, 9}, - {Intrinsic::nearbyint, MVT::nxv2f32, 9}, - {Intrinsic::nearbyint, MVT::nxv4f32, 9}, - {Intrinsic::nearbyint, MVT::nxv8f32, 9}, - {Intrinsic::nearbyint, MVT::nxv16f32, 9}, - {Intrinsic::nearbyint, MVT::v2f64, 9}, - {Intrinsic::nearbyint, MVT::v4f64, 9}, - {Intrinsic::nearbyint, MVT::v8f64, 9}, - {Intrinsic::nearbyint, MVT::v16f64, 9}, - {Intrinsic::nearbyint, MVT::nxv1f64, 9}, - {Intrinsic::nearbyint, MVT::nxv2f64, 9}, - {Intrinsic::nearbyint, MVT::nxv4f64, 9}, - {Intrinsic::nearbyint, MVT::nxv8f64, 9}, - {Intrinsic::bswap, MVT::v2i16, 3}, - {Intrinsic::bswap, MVT::v4i16, 3}, - {Intrinsic::bswap, MVT::v8i16, 3}, - {Intrinsic::bswap, MVT::v16i16, 3}, - {Intrinsic::bswap, MVT::nxv1i16, 3}, - {Intrinsic::bswap, MVT::nxv2i16, 3}, - {Intrinsic::bswap, MVT::nxv4i16, 3}, - {Intrinsic::bswap, MVT::nxv8i16, 3}, - {Intrinsic::bswap, MVT::nxv16i16, 3}, - {Intrinsic::bswap, MVT::v2i32, 12}, - {Intrinsic::bswap, MVT::v4i32, 12}, - {Intrinsic::bswap, MVT::v8i32, 12}, - {Intrinsic::bswap, MVT::v16i32, 12}, - {Intrinsic::bswap, MVT::nxv1i32, 12}, - {Intrinsic::bswap, MVT::nxv2i32, 12}, - {Intrinsic::bswap, MVT::nxv4i32, 12}, - {Intrinsic::bswap, MVT::nxv8i32, 12}, - {Intrinsic::bswap, MVT::nxv16i32, 12}, - {Intrinsic::bswap, MVT::v2i64, 31}, - {Intrinsic::bswap, MVT::v4i64, 31}, - {Intrinsic::bswap, MVT::v8i64, 31}, - {Intrinsic::bswap, MVT::v16i64, 31}, - {Intrinsic::bswap, MVT::nxv1i64, 31}, - {Intrinsic::bswap, MVT::nxv2i64, 31}, - {Intrinsic::bswap, MVT::nxv4i64, 31}, - {Intrinsic::bswap, MVT::nxv8i64, 31}, - {Intrinsic::vp_bswap, MVT::v2i16, 3}, - {Intrinsic::vp_bswap, MVT::v4i16, 3}, - {Intrinsic::vp_bswap, MVT::v8i16, 3}, - {Intrinsic::vp_bswap, MVT::v16i16, 3}, - {Intrinsic::vp_bswap, MVT::nxv1i16, 3}, - {Intrinsic::vp_bswap, MVT::nxv2i16, 3}, - {Intrinsic::vp_bswap, MVT::nxv4i16, 3}, - {Intrinsic::vp_bswap, MVT::nxv8i16, 3}, - {Intrinsic::vp_bswap, MVT::nxv16i16, 3}, - {Intrinsic::vp_bswap, MVT::v2i32, 12}, - {Intrinsic::vp_bswap, MVT::v4i32, 12}, - {Intrinsic::vp_bswap, MVT::v8i32, 12}, - {Intrinsic::vp_bswap, MVT::v16i32, 12}, - {Intrinsic::vp_bswap, MVT::nxv1i32, 12}, - {Intrinsic::vp_bswap, MVT::nxv2i32, 12}, - {Intrinsic::vp_bswap, MVT::nxv4i32, 12}, - {Intrinsic::vp_bswap, MVT::nxv8i32, 12}, - {Intrinsic::vp_bswap, MVT::nxv16i32, 12}, - {Intrinsic::vp_bswap, MVT::v2i64, 31}, - {Intrinsic::vp_bswap, MVT::v4i64, 31}, - {Intrinsic::vp_bswap, MVT::v8i64, 31}, - {Intrinsic::vp_bswap, MVT::v16i64, 31}, - {Intrinsic::vp_bswap, MVT::nxv1i64, 31}, - {Intrinsic::vp_bswap, MVT::nxv2i64, 31}, - {Intrinsic::vp_bswap, MVT::nxv4i64, 31}, - {Intrinsic::vp_bswap, MVT::nxv8i64, 31}, - {Intrinsic::vp_fshl, MVT::v2i8, 7}, - {Intrinsic::vp_fshl, MVT::v4i8, 7}, - {Intrinsic::vp_fshl, MVT::v8i8, 7}, - {Intrinsic::vp_fshl, MVT::v16i8, 7}, - {Intrinsic::vp_fshl, MVT::nxv1i8, 7}, - {Intrinsic::vp_fshl, MVT::nxv2i8, 7}, - {Intrinsic::vp_fshl, MVT::nxv4i8, 7}, - {Intrinsic::vp_fshl, MVT::nxv8i8, 7}, - {Intrinsic::vp_fshl, MVT::nxv16i8, 7}, - {Intrinsic::vp_fshl, MVT::nxv32i8, 7}, - {Intrinsic::vp_fshl, MVT::nxv64i8, 7}, - {Intrinsic::vp_fshl, MVT::v2i16, 7}, - {Intrinsic::vp_fshl, MVT::v4i16, 7}, - {Intrinsic::vp_fshl, MVT::v8i16, 7}, - {Intrinsic::vp_fshl, MVT::v16i16, 7}, - {Intrinsic::vp_fshl, MVT::nxv1i16, 7}, - {Intrinsic::vp_fshl, MVT::nxv2i16, 7}, - {Intrinsic::vp_fshl, MVT::nxv4i16, 7}, - {Intrinsic::vp_fshl, MVT::nxv8i16, 7}, - {Intrinsic::vp_fshl, MVT::nxv16i16, 7}, - {Intrinsic::vp_fshl, MVT::nxv32i16, 7}, - {Intrinsic::vp_fshl, MVT::v2i32, 7}, - {Intrinsic::vp_fshl, MVT::v4i32, 7}, - {Intrinsic::vp_fshl, MVT::v8i32, 7}, - {Intrinsic::vp_fshl, MVT::v16i32, 7}, - {Intrinsic::vp_fshl, MVT::nxv1i32, 7}, - {Intrinsic::vp_fshl, MVT::nxv2i32, 7}, - {Intrinsic::vp_fshl, MVT::nxv4i32, 7}, - {Intrinsic::vp_fshl, MVT::nxv8i32, 7}, - {Intrinsic::vp_fshl, MVT::nxv16i32, 7}, - {Intrinsic::vp_fshl, MVT::v2i64, 7}, - {Intrinsic::vp_fshl, MVT::v4i64, 7}, - {Intrinsic::vp_fshl, MVT::v8i64, 7}, - {Intrinsic::vp_fshl, MVT::v16i64, 7}, - {Intrinsic::vp_fshl, MVT::nxv1i64, 7}, - {Intrinsic::vp_fshl, MVT::nxv2i64, 7}, - {Intrinsic::vp_fshl, MVT::nxv4i64, 7}, - {Intrinsic::vp_fshl, MVT::nxv8i64, 7}, - {Intrinsic::vp_fshr, MVT::v2i8, 7}, - {Intrinsic::vp_fshr, MVT::v4i8, 7}, - {Intrinsic::vp_fshr, MVT::v8i8, 7}, - {Intrinsic::vp_fshr, MVT::v16i8, 7}, - {Intrinsic::vp_fshr, MVT::nxv1i8, 7}, - {Intrinsic::vp_fshr, MVT::nxv2i8, 7}, - {Intrinsic::vp_fshr, MVT::nxv4i8, 7}, - {Intrinsic::vp_fshr, MVT::nxv8i8, 7}, - {Intrinsic::vp_fshr, MVT::nxv16i8, 7}, - {Intrinsic::vp_fshr, MVT::nxv32i8, 7}, - {Intrinsic::vp_fshr, MVT::nxv64i8, 7}, - {Intrinsic::vp_fshr, MVT::v2i16, 7}, - {Intrinsic::vp_fshr, MVT::v4i16, 7}, - {Intrinsic::vp_fshr, MVT::v8i16, 7}, - {Intrinsic::vp_fshr, MVT::v16i16, 7}, - {Intrinsic::vp_fshr, MVT::nxv1i16, 7}, - {Intrinsic::vp_fshr, MVT::nxv2i16, 7}, - {Intrinsic::vp_fshr, MVT::nxv4i16, 7}, - {Intrinsic::vp_fshr, MVT::nxv8i16, 7}, - {Intrinsic::vp_fshr, MVT::nxv16i16, 7}, - {Intrinsic::vp_fshr, MVT::nxv32i16, 7}, - {Intrinsic::vp_fshr, MVT::v2i32, 7}, - {Intrinsic::vp_fshr, MVT::v4i32, 7}, - {Intrinsic::vp_fshr, MVT::v8i32, 7}, - {Intrinsic::vp_fshr, MVT::v16i32, 7}, - {Intrinsic::vp_fshr, MVT::nxv1i32, 7}, - {Intrinsic::vp_fshr, MVT::nxv2i32, 7}, - {Intrinsic::vp_fshr, MVT::nxv4i32, 7}, - {Intrinsic::vp_fshr, MVT::nxv8i32, 7}, - {Intrinsic::vp_fshr, MVT::nxv16i32, 7}, - {Intrinsic::vp_fshr, MVT::v2i64, 7}, - {Intrinsic::vp_fshr, MVT::v4i64, 7}, - {Intrinsic::vp_fshr, MVT::v8i64, 7}, - {Intrinsic::vp_fshr, MVT::v16i64, 7}, - {Intrinsic::vp_fshr, MVT::nxv1i64, 7}, - {Intrinsic::vp_fshr, MVT::nxv2i64, 7}, - {Intrinsic::vp_fshr, MVT::nxv4i64, 7}, - {Intrinsic::vp_fshr, MVT::nxv8i64, 7}, - {Intrinsic::bitreverse, MVT::v2i8, 17}, - {Intrinsic::bitreverse, MVT::v4i8, 17}, - {Intrinsic::bitreverse, MVT::v8i8, 17}, - {Intrinsic::bitreverse, MVT::v16i8, 17}, - {Intrinsic::bitreverse, MVT::nxv1i8, 17}, - {Intrinsic::bitreverse, MVT::nxv2i8, 17}, - {Intrinsic::bitreverse, MVT::nxv4i8, 17}, - {Intrinsic::bitreverse, MVT::nxv8i8, 17}, - {Intrinsic::bitreverse, MVT::nxv16i8, 17}, - {Intrinsic::bitreverse, MVT::v2i16, 24}, - {Intrinsic::bitreverse, MVT::v4i16, 24}, - {Intrinsic::bitreverse, MVT::v8i16, 24}, - {Intrinsic::bitreverse, MVT::v16i16, 24}, - {Intrinsic::bitreverse, MVT::nxv1i16, 24}, - {Intrinsic::bitreverse, MVT::nxv2i16, 24}, - {Intrinsic::bitreverse, MVT::nxv4i16, 24}, - {Intrinsic::bitreverse, MVT::nxv8i16, 24}, - {Intrinsic::bitreverse, MVT::nxv16i16, 24}, - {Intrinsic::bitreverse, MVT::v2i32, 33}, - {Intrinsic::bitreverse, MVT::v4i32, 33}, - {Intrinsic::bitreverse, MVT::v8i32, 33}, - {Intrinsic::bitreverse, MVT::v16i32, 33}, - {Intrinsic::bitreverse, MVT::nxv1i32, 33}, - {Intrinsic::bitreverse, MVT::nxv2i32, 33}, - {Intrinsic::bitreverse, MVT::nxv4i32, 33}, - {Intrinsic::bitreverse, MVT::nxv8i32, 33}, - {Intrinsic::bitreverse, MVT::nxv16i32, 33}, - {Intrinsic::bitreverse, MVT::v2i64, 52}, - {Intrinsic::bitreverse, MVT::v4i64, 52}, - {Intrinsic::bitreverse, MVT::v8i64, 52}, - {Intrinsic::bitreverse, MVT::v16i64, 52}, - {Intrinsic::bitreverse, MVT::nxv1i64, 52}, - {Intrinsic::bitreverse, MVT::nxv2i64, 52}, - {Intrinsic::bitreverse, MVT::nxv4i64, 52}, - {Intrinsic::bitreverse, MVT::nxv8i64, 52}, - {Intrinsic::vp_bitreverse, MVT::v2i8, 17}, - {Intrinsic::vp_bitreverse, MVT::v4i8, 17}, - {Intrinsic::vp_bitreverse, MVT::v8i8, 17}, - {Intrinsic::vp_bitreverse, MVT::v16i8, 17}, - {Intrinsic::vp_bitreverse, MVT::nxv1i8, 17}, - {Intrinsic::vp_bitreverse, MVT::nxv2i8, 17}, - {Intrinsic::vp_bitreverse, MVT::nxv4i8, 17}, - {Intrinsic::vp_bitreverse, MVT::nxv8i8, 17}, - {Intrinsic::vp_bitreverse, MVT::nxv16i8, 17}, - {Intrinsic::vp_bitreverse, MVT::v2i16, 24}, - {Intrinsic::vp_bitreverse, MVT::v4i16, 24}, - {Intrinsic::vp_bitreverse, MVT::v8i16, 24}, - {Intrinsic::vp_bitreverse, MVT::v16i16, 24}, - {Intrinsic::vp_bitreverse, MVT::nxv1i16, 24}, - {Intrinsic::vp_bitreverse, MVT::nxv2i16, 24}, - {Intrinsic::vp_bitreverse, MVT::nxv4i16, 24}, - {Intrinsic::vp_bitreverse, MVT::nxv8i16, 24}, - {Intrinsic::vp_bitreverse, MVT::nxv16i16, 24}, - {Intrinsic::vp_bitreverse, MVT::v2i32, 33}, - {Intrinsic::vp_bitreverse, MVT::v4i32, 33}, - {Intrinsic::vp_bitreverse, MVT::v8i32, 33}, - {Intrinsic::vp_bitreverse, MVT::v16i32, 33}, - {Intrinsic::vp_bitreverse, MVT::nxv1i32, 33}, - {Intrinsic::vp_bitreverse, MVT::nxv2i32, 33}, - {Intrinsic::vp_bitreverse, MVT::nxv4i32, 33}, - {Intrinsic::vp_bitreverse, MVT::nxv8i32, 33}, - {Intrinsic::vp_bitreverse, MVT::nxv16i32, 33}, - {Intrinsic::vp_bitreverse, MVT::v2i64, 52}, - {Intrinsic::vp_bitreverse, MVT::v4i64, 52}, - {Intrinsic::vp_bitreverse, MVT::v8i64, 52}, - {Intrinsic::vp_bitreverse, MVT::v16i64, 52}, - {Intrinsic::vp_bitreverse, MVT::nxv1i64, 52}, - {Intrinsic::vp_bitreverse, MVT::nxv2i64, 52}, - {Intrinsic::vp_bitreverse, MVT::nxv4i64, 52}, - {Intrinsic::vp_bitreverse, MVT::nxv8i64, 52}, - {Intrinsic::ctpop, MVT::v2i8, 12}, - {Intrinsic::ctpop, MVT::v4i8, 12}, - {Intrinsic::ctpop, MVT::v8i8, 12}, - {Intrinsic::ctpop, MVT::v16i8, 12}, - {Intrinsic::ctpop, MVT::nxv1i8, 12}, - {Intrinsic::ctpop, MVT::nxv2i8, 12}, - {Intrinsic::ctpop, MVT::nxv4i8, 12}, - {Intrinsic::ctpop, MVT::nxv8i8, 12}, - {Intrinsic::ctpop, MVT::nxv16i8, 12}, - {Intrinsic::ctpop, MVT::v2i16, 19}, - {Intrinsic::ctpop, MVT::v4i16, 19}, - {Intrinsic::ctpop, MVT::v8i16, 19}, - {Intrinsic::ctpop, MVT::v16i16, 19}, - {Intrinsic::ctpop, MVT::nxv1i16, 19}, - {Intrinsic::ctpop, MVT::nxv2i16, 19}, - {Intrinsic::ctpop, MVT::nxv4i16, 19}, - {Intrinsic::ctpop, MVT::nxv8i16, 19}, - {Intrinsic::ctpop, MVT::nxv16i16, 19}, - {Intrinsic::ctpop, MVT::v2i32, 20}, - {Intrinsic::ctpop, MVT::v4i32, 20}, - {Intrinsic::ctpop, MVT::v8i32, 20}, - {Intrinsic::ctpop, MVT::v16i32, 20}, - {Intrinsic::ctpop, MVT::nxv1i32, 20}, - {Intrinsic::ctpop, MVT::nxv2i32, 20}, - {Intrinsic::ctpop, MVT::nxv4i32, 20}, - {Intrinsic::ctpop, MVT::nxv8i32, 20}, - {Intrinsic::ctpop, MVT::nxv16i32, 20}, - {Intrinsic::ctpop, MVT::v2i64, 21}, - {Intrinsic::ctpop, MVT::v4i64, 21}, - {Intrinsic::ctpop, MVT::v8i64, 21}, - {Intrinsic::ctpop, MVT::v16i64, 21}, - {Intrinsic::ctpop, MVT::nxv1i64, 21}, - {Intrinsic::ctpop, MVT::nxv2i64, 21}, - {Intrinsic::ctpop, MVT::nxv4i64, 21}, - {Intrinsic::ctpop, MVT::nxv8i64, 21}, - {Intrinsic::vp_ctpop, MVT::v2i8, 12}, - {Intrinsic::vp_ctpop, MVT::v4i8, 12}, - {Intrinsic::vp_ctpop, MVT::v8i8, 12}, - {Intrinsic::vp_ctpop, MVT::v16i8, 12}, - {Intrinsic::vp_ctpop, MVT::nxv1i8, 12}, - {Intrinsic::vp_ctpop, MVT::nxv2i8, 12}, - {Intrinsic::vp_ctpop, MVT::nxv4i8, 12}, - {Intrinsic::vp_ctpop, MVT::nxv8i8, 12}, - {Intrinsic::vp_ctpop, MVT::nxv16i8, 12}, - {Intrinsic::vp_ctpop, MVT::v2i16, 19}, - {Intrinsic::vp_ctpop, MVT::v4i16, 19}, - {Intrinsic::vp_ctpop, MVT::v8i16, 19}, - {Intrinsic::vp_ctpop, MVT::v16i16, 19}, - {Intrinsic::vp_ctpop, MVT::nxv1i16, 19}, - {Intrinsic::vp_ctpop, MVT::nxv2i16, 19}, - {Intrinsic::vp_ctpop, MVT::nxv4i16, 19}, - {Intrinsic::vp_ctpop, MVT::nxv8i16, 19}, - {Intrinsic::vp_ctpop, MVT::nxv16i16, 19}, - {Intrinsic::vp_ctpop, MVT::v2i32, 20}, - {Intrinsic::vp_ctpop, MVT::v4i32, 20}, - {Intrinsic::vp_ctpop, MVT::v8i32, 20}, - {Intrinsic::vp_ctpop, MVT::v16i32, 20}, - {Intrinsic::vp_ctpop, MVT::nxv1i32, 20}, - {Intrinsic::vp_ctpop, MVT::nxv2i32, 20}, - {Intrinsic::vp_ctpop, MVT::nxv4i32, 20}, - {Intrinsic::vp_ctpop, MVT::nxv8i32, 20}, - {Intrinsic::vp_ctpop, MVT::nxv16i32, 20}, - {Intrinsic::vp_ctpop, MVT::v2i64, 21}, - {Intrinsic::vp_ctpop, MVT::v4i64, 21}, - {Intrinsic::vp_ctpop, MVT::v8i64, 21}, - {Intrinsic::vp_ctpop, MVT::v16i64, 21}, - {Intrinsic::vp_ctpop, MVT::nxv1i64, 21}, - {Intrinsic::vp_ctpop, MVT::nxv2i64, 21}, - {Intrinsic::vp_ctpop, MVT::nxv4i64, 21}, - {Intrinsic::vp_ctpop, MVT::nxv8i64, 21}, - {Intrinsic::vp_ctlz, MVT::v2i8, 19}, - {Intrinsic::vp_ctlz, MVT::v4i8, 19}, - {Intrinsic::vp_ctlz, MVT::v8i8, 19}, - {Intrinsic::vp_ctlz, MVT::v16i8, 19}, - {Intrinsic::vp_ctlz, MVT::nxv1i8, 19}, - {Intrinsic::vp_ctlz, MVT::nxv2i8, 19}, - {Intrinsic::vp_ctlz, MVT::nxv4i8, 19}, - {Intrinsic::vp_ctlz, MVT::nxv8i8, 19}, - {Intrinsic::vp_ctlz, MVT::nxv16i8, 19}, - {Intrinsic::vp_ctlz, MVT::nxv32i8, 19}, - {Intrinsic::vp_ctlz, MVT::nxv64i8, 19}, - {Intrinsic::vp_ctlz, MVT::v2i16, 28}, - {Intrinsic::vp_ctlz, MVT::v4i16, 28}, - {Intrinsic::vp_ctlz, MVT::v8i16, 28}, - {Intrinsic::vp_ctlz, MVT::v16i16, 28}, - {Intrinsic::vp_ctlz, MVT::nxv1i16, 28}, - {Intrinsic::vp_ctlz, MVT::nxv2i16, 28}, - {Intrinsic::vp_ctlz, MVT::nxv4i16, 28}, - {Intrinsic::vp_ctlz, MVT::nxv8i16, 28}, - {Intrinsic::vp_ctlz, MVT::nxv16i16, 28}, - {Intrinsic::vp_ctlz, MVT::nxv32i16, 28}, - {Intrinsic::vp_ctlz, MVT::v2i32, 31}, - {Intrinsic::vp_ctlz, MVT::v4i32, 31}, - {Intrinsic::vp_ctlz, MVT::v8i32, 31}, - {Intrinsic::vp_ctlz, MVT::v16i32, 31}, - {Intrinsic::vp_ctlz, MVT::nxv1i32, 31}, - {Intrinsic::vp_ctlz, MVT::nxv2i32, 31}, - {Intrinsic::vp_ctlz, MVT::nxv4i32, 31}, - {Intrinsic::vp_ctlz, MVT::nxv8i32, 31}, - {Intrinsic::vp_ctlz, MVT::nxv16i32, 31}, - {Intrinsic::vp_ctlz, MVT::v2i64, 35}, - {Intrinsic::vp_ctlz, MVT::v4i64, 35}, - {Intrinsic::vp_ctlz, MVT::v8i64, 35}, - {Intrinsic::vp_ctlz, MVT::v16i64, 35}, - {Intrinsic::vp_ctlz, MVT::nxv1i64, 35}, - {Intrinsic::vp_ctlz, MVT::nxv2i64, 35}, - {Intrinsic::vp_ctlz, MVT::nxv4i64, 35}, - {Intrinsic::vp_ctlz, MVT::nxv8i64, 35}, - {Intrinsic::vp_cttz, MVT::v2i8, 16}, - {Intrinsic::vp_cttz, MVT::v4i8, 16}, - {Intrinsic::vp_cttz, MVT::v8i8, 16}, - {Intrinsic::vp_cttz, MVT::v16i8, 16}, - {Intrinsic::vp_cttz, MVT::nxv1i8, 16}, - {Intrinsic::vp_cttz, MVT::nxv2i8, 16}, - {Intrinsic::vp_cttz, MVT::nxv4i8, 16}, - {Intrinsic::vp_cttz, MVT::nxv8i8, 16}, - {Intrinsic::vp_cttz, MVT::nxv16i8, 16}, - {Intrinsic::vp_cttz, MVT::nxv32i8, 16}, - {Intrinsic::vp_cttz, MVT::nxv64i8, 16}, - {Intrinsic::vp_cttz, MVT::v2i16, 23}, - {Intrinsic::vp_cttz, MVT::v4i16, 23}, - {Intrinsic::vp_cttz, MVT::v8i16, 23}, - {Intrinsic::vp_cttz, MVT::v16i16, 23}, - {Intrinsic::vp_cttz, MVT::nxv1i16, 23}, - {Intrinsic::vp_cttz, MVT::nxv2i16, 23}, - {Intrinsic::vp_cttz, MVT::nxv4i16, 23}, - {Intrinsic::vp_cttz, MVT::nxv8i16, 23}, - {Intrinsic::vp_cttz, MVT::nxv16i16, 23}, - {Intrinsic::vp_cttz, MVT::nxv32i16, 23}, - {Intrinsic::vp_cttz, MVT::v2i32, 24}, - {Intrinsic::vp_cttz, MVT::v4i32, 24}, - {Intrinsic::vp_cttz, MVT::v8i32, 24}, - {Intrinsic::vp_cttz, MVT::v16i32, 24}, - {Intrinsic::vp_cttz, MVT::nxv1i32, 24}, - {Intrinsic::vp_cttz, MVT::nxv2i32, 24}, - {Intrinsic::vp_cttz, MVT::nxv4i32, 24}, - {Intrinsic::vp_cttz, MVT::nxv8i32, 24}, - {Intrinsic::vp_cttz, MVT::nxv16i32, 24}, - {Intrinsic::vp_cttz, MVT::v2i64, 25}, - {Intrinsic::vp_cttz, MVT::v4i64, 25}, - {Intrinsic::vp_cttz, MVT::v8i64, 25}, - {Intrinsic::vp_cttz, MVT::v16i64, 25}, - {Intrinsic::vp_cttz, MVT::nxv1i64, 25}, - {Intrinsic::vp_cttz, MVT::nxv2i64, 25}, - {Intrinsic::vp_cttz, MVT::nxv4i64, 25}, - {Intrinsic::vp_cttz, MVT::nxv8i64, 25}, + {Intrinsic::floor, MVT::f32, 9}, + {Intrinsic::floor, MVT::f64, 9}, + {Intrinsic::ceil, MVT::f32, 9}, + {Intrinsic::ceil, MVT::f64, 9}, + {Intrinsic::trunc, MVT::f32, 7}, + {Intrinsic::trunc, MVT::f64, 7}, + {Intrinsic::round, MVT::f32, 9}, + {Intrinsic::round, MVT::f64, 9}, + {Intrinsic::roundeven, MVT::f32, 9}, + {Intrinsic::roundeven, MVT::f64, 9}, + {Intrinsic::rint, MVT::f32, 7}, + {Intrinsic::rint, MVT::f64, 7}, + {Intrinsic::lrint, MVT::i32, 1}, + {Intrinsic::lrint, MVT::i64, 1}, + {Intrinsic::llrint, MVT::i64, 1}, + {Intrinsic::nearbyint, MVT::f32, 9}, + {Intrinsic::nearbyint, MVT::f64, 9}, + {Intrinsic::bswap, MVT::i16, 3}, + {Intrinsic::bswap, MVT::i32, 12}, + {Intrinsic::bswap, MVT::i64, 31}, + {Intrinsic::vp_bswap, MVT::i16, 3}, + {Intrinsic::vp_bswap, MVT::i32, 12}, + {Intrinsic::vp_bswap, MVT::i64, 31}, + {Intrinsic::vp_fshl, MVT::i8, 7}, + {Intrinsic::vp_fshl, MVT::i16, 7}, + {Intrinsic::vp_fshl, MVT::i32, 7}, + {Intrinsic::vp_fshl, MVT::i64, 7}, + {Intrinsic::vp_fshr, MVT::i8, 7}, + {Intrinsic::vp_fshr, MVT::i16, 7}, + {Intrinsic::vp_fshr, MVT::i32, 7}, + {Intrinsic::vp_fshr, MVT::i64, 7}, + {Intrinsic::bitreverse, MVT::i8, 17}, + {Intrinsic::bitreverse, MVT::i16, 24}, + {Intrinsic::bitreverse, MVT::i32, 33}, + {Intrinsic::bitreverse, MVT::i64, 52}, + {Intrinsic::vp_bitreverse, MVT::i8, 17}, + {Intrinsic::vp_bitreverse, MVT::i16, 24}, + {Intrinsic::vp_bitreverse, MVT::i32, 33}, + {Intrinsic::vp_bitreverse, MVT::i64, 52}, + {Intrinsic::ctpop, MVT::i8, 12}, + {Intrinsic::ctpop, MVT::i16, 19}, + {Intrinsic::ctpop, MVT::i32, 20}, + {Intrinsic::ctpop, MVT::i64, 21}, + {Intrinsic::vp_ctpop, MVT::i8, 12}, + {Intrinsic::vp_ctpop, MVT::i16, 19}, + {Intrinsic::vp_ctpop, MVT::i32, 20}, + {Intrinsic::vp_ctpop, MVT::i64, 21}, + {Intrinsic::vp_ctlz, MVT::i8, 19}, + {Intrinsic::vp_ctlz, MVT::i16, 28}, + {Intrinsic::vp_ctlz, MVT::i32, 31}, + {Intrinsic::vp_ctlz, MVT::i64, 35}, + {Intrinsic::vp_cttz, MVT::i8, 16}, + {Intrinsic::vp_cttz, MVT::i16, 23}, + {Intrinsic::vp_cttz, MVT::i32, 24}, + {Intrinsic::vp_cttz, MVT::i64, 25}, }; static unsigned getISDForVPIntrinsicID(Intrinsic::ID ID) { @@ -1250,10 +821,13 @@ RISCVTTIImpl::getIntrinsicInstrCost(const IntrinsicCostAttributes &ICA, } if (ST->hasVInstructions() && RetTy->isVectorTy()) { - auto LT = getTypeLegalizationCost(RetTy); - if (const auto *Entry = CostTableLookup(VectorIntrinsicCostTable, - ICA.getID(), LT.second)) - return LT.first * Entry->Cost; + if (auto LT = getTypeLegalizationCost(RetTy); + LT.second.isVector()) { + MVT EltTy = LT.second.getVectorElementType(); + if (const auto *Entry = CostTableLookup(VectorIntrinsicCostTable, + ICA.getID(), EltTy)) + return LT.first * Entry->Cost; + } } return BaseT::getIntrinsicInstrCost(ICA, CostKind); @@ -1476,7 +1050,7 @@ InstructionCost RISCVTTIImpl::getMemoryOpCost(unsigned Opcode, Type *Src, // possible accessed by the instruction. Note that BasicTTI already // handles the LT.first term for us. if (std::pair LT = getTypeLegalizationCost(Src); - LT.second.isVector()) + LT.second.isVector() && CostKind != TTI::TCK_CodeSize) BaseCost *= TLI->getLMULCost(LT.second); return Cost + BaseCost; diff --git a/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.h b/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.h index 7e5dbddb5b5..0747a778fe9 100644 --- a/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.h +++ b/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.h @@ -362,8 +362,7 @@ public: const TargetTransformInfo::LSRCost &C2); bool shouldFoldTerminatingConditionAfterLSR() const { - // FIXME: Enabling this causes miscompiles. - return false; + return true; } }; diff --git a/llvm/lib/Target/SPIRV/SPIRV.h b/llvm/lib/Target/SPIRV/SPIRV.h index 3151d69ab74..b947062d79e 100644 --- a/llvm/lib/Target/SPIRV/SPIRV.h +++ b/llvm/lib/Target/SPIRV/SPIRV.h @@ -20,6 +20,7 @@ class InstructionSelector; class RegisterBankInfo; ModulePass *createSPIRVPrepareFunctionsPass(const SPIRVTargetMachine &TM); +FunctionPass *createSPIRVStripConvergenceIntrinsicsPass(); FunctionPass *createSPIRVRegularizerPass(); FunctionPass *createSPIRVPreLegalizerPass(); FunctionPass *createSPIRVEmitIntrinsicsPass(SPIRVTargetMachine *TM); diff --git a/llvm/lib/Target/SPIRV/SPIRVEmitIntrinsics.cpp b/llvm/lib/Target/SPIRV/SPIRVEmitIntrinsics.cpp index fb4e9932dd2..90ec98bb361 100644 --- a/llvm/lib/Target/SPIRV/SPIRVEmitIntrinsics.cpp +++ b/llvm/lib/Target/SPIRV/SPIRVEmitIntrinsics.cpp @@ -314,7 +314,9 @@ void SPIRVEmitIntrinsics::insertPtrCastInstr(Instruction *I) { if (A && A->getAllocatedType() == ExpectedElementType) return; - if (dyn_cast(Pointer)) + // Do not emit spv_ptrcast if Pointer is a result of GEP of expected type. + GetElementPtrInst *GEPI = dyn_cast(Pointer); + if (GEPI && GEPI->getResultElementType() == ExpectedElementType) return; setInsertPointSkippingPhis(*IRB, I); diff --git a/llvm/lib/Target/SPIRV/SPIRVModuleAnalysis.cpp b/llvm/lib/Target/SPIRV/SPIRVModuleAnalysis.cpp index 2a830535a2a..370da046984 100644 --- a/llvm/lib/Target/SPIRV/SPIRVModuleAnalysis.cpp +++ b/llvm/lib/Target/SPIRV/SPIRVModuleAnalysis.cpp @@ -263,34 +263,6 @@ void SPIRVModuleAnalysis::processDefInstrs(const Module &M) { [](const SPIRV::DTSortableEntry *E) { return E->getIsFunc(); }, true); } -// True if there is an instruction in the MS list with all the same operands as -// the given instruction has (after the given starting index). -// TODO: maybe it needs to check Opcodes too. -static bool findSameInstrInMS(const MachineInstr &A, - SPIRV::ModuleSectionType MSType, - SPIRV::ModuleAnalysisInfo &MAI, - unsigned StartOpIndex = 0) { - for (const auto *B : MAI.MS[MSType]) { - const unsigned NumAOps = A.getNumOperands(); - if (NumAOps != B->getNumOperands() || A.getNumDefs() != B->getNumDefs()) - continue; - bool AllOpsMatch = true; - for (unsigned i = StartOpIndex; i < NumAOps && AllOpsMatch; ++i) { - if (A.getOperand(i).isReg() && B->getOperand(i).isReg()) { - Register RegA = A.getOperand(i).getReg(); - Register RegB = B->getOperand(i).getReg(); - AllOpsMatch = MAI.getRegisterAlias(A.getMF(), RegA) == - MAI.getRegisterAlias(B->getMF(), RegB); - } else { - AllOpsMatch = A.getOperand(i).isIdenticalTo(B->getOperand(i)); - } - } - if (AllOpsMatch) - return true; - } - return false; -} - // Look for IDs declared with Import linkage, and map the corresponding function // to the register defining that variable (which will usually be the result of // an OpFunction). This lets us call externally imported functions using @@ -319,15 +291,43 @@ void SPIRVModuleAnalysis::collectFuncNames(MachineInstr &MI, } } +using InstrSignature = SmallVector; +using InstrTraces = std::set; + +// Returns a representation of an instruction as a vector of MachineOperand +// hash values, see llvm::hash_value(const MachineOperand &MO) for details. +// This creates a signature of the instruction with the same content +// that MachineOperand::isIdenticalTo uses for comparison. +static InstrSignature instrToSignature(MachineInstr &MI, + SPIRV::ModuleAnalysisInfo &MAI) { + InstrSignature Signature; + for (unsigned i = 0; i < MI.getNumOperands(); ++i) { + const MachineOperand &MO = MI.getOperand(i); + size_t h; + if (MO.isReg()) { + Register RegAlias = MAI.getRegisterAlias(MI.getMF(), MO.getReg()); + // mimic llvm::hash_value(const MachineOperand &MO) + h = hash_combine(MO.getType(), (unsigned)RegAlias, MO.getSubReg(), + MO.isDef()); + } else { + h = hash_value(MO); + } + Signature.push_back(h); + } + return Signature; +} + // Collect the given instruction in the specified MS. We assume global register // numbering has already occurred by this point. We can directly compare reg // arguments when detecting duplicates. static void collectOtherInstr(MachineInstr &MI, SPIRV::ModuleAnalysisInfo &MAI, - SPIRV::ModuleSectionType MSType, + SPIRV::ModuleSectionType MSType, InstrTraces &IS, bool Append = true) { MAI.setSkipEmission(&MI); - if (findSameInstrInMS(MI, MSType, MAI)) - return; // Found a duplicate, so don't add it. + InstrSignature MISign = instrToSignature(MI, MAI); + auto FoundMI = IS.insert(MISign); + if (!FoundMI.second) + return; // insert failed, so we found a duplicate; don't add it to MAI.MS // No duplicates, so add it. if (Append) MAI.MS[MSType].push_back(&MI); @@ -338,6 +338,7 @@ static void collectOtherInstr(MachineInstr &MI, SPIRV::ModuleAnalysisInfo &MAI, // Some global instructions make reference to function-local ID regs, so cannot // be correctly collected until these registers are globally numbered. void SPIRVModuleAnalysis::processOtherInstrs(const Module &M) { + InstrTraces IS; for (auto F = M.begin(), E = M.end(); F != E; ++F) { if ((*F).isDeclaration()) continue; @@ -349,20 +350,20 @@ void SPIRVModuleAnalysis::processOtherInstrs(const Module &M) { continue; const unsigned OpCode = MI.getOpcode(); if (OpCode == SPIRV::OpName || OpCode == SPIRV::OpMemberName) { - collectOtherInstr(MI, MAI, SPIRV::MB_DebugNames); + collectOtherInstr(MI, MAI, SPIRV::MB_DebugNames, IS); } else if (OpCode == SPIRV::OpEntryPoint) { - collectOtherInstr(MI, MAI, SPIRV::MB_EntryPoints); + collectOtherInstr(MI, MAI, SPIRV::MB_EntryPoints, IS); } else if (TII->isDecorationInstr(MI)) { - collectOtherInstr(MI, MAI, SPIRV::MB_Annotations); + collectOtherInstr(MI, MAI, SPIRV::MB_Annotations, IS); collectFuncNames(MI, &*F); } else if (TII->isConstantInstr(MI)) { // Now OpSpecConstant*s are not in DT, // but they need to be collected anyway. - collectOtherInstr(MI, MAI, SPIRV::MB_TypeConstVars); + collectOtherInstr(MI, MAI, SPIRV::MB_TypeConstVars, IS); } else if (OpCode == SPIRV::OpFunction) { collectFuncNames(MI, &*F); } else if (OpCode == SPIRV::OpTypeForwardPointer) { - collectOtherInstr(MI, MAI, SPIRV::MB_TypeConstVars, false); + collectOtherInstr(MI, MAI, SPIRV::MB_TypeConstVars, IS, false); } } } @@ -409,7 +410,7 @@ void SPIRV::RequirementHandler::pruneCapabilities( const CapabilityList &ToPrune) { for (const auto &Cap : ToPrune) { AllCaps.insert(Cap); - auto FoundIndex = std::find(MinimalCaps.begin(), MinimalCaps.end(), Cap); + auto FoundIndex = llvm::find(MinimalCaps, Cap); if (FoundIndex != MinimalCaps.end()) MinimalCaps.erase(FoundIndex); CapabilityList ImplicitDecls = @@ -597,8 +598,9 @@ void RequirementHandler::initAvailableCapabilitiesForVulkan( const SPIRVSubtarget &ST) { addAvailableCaps({Capability::Shader, Capability::Linkage}); - // Provided by Vulkan version 1.0. - addAvailableCaps({Capability::Int16, Capability::Int64, Capability::Float64}); + // Provided by all supported Vulkan versions. + addAvailableCaps({Capability::Int16, Capability::Int64, Capability::Float16, + Capability::Float64}); } } // namespace SPIRV @@ -733,7 +735,10 @@ void addInstrRequirements(const MachineInstr &MI, auto SC = MI.getOperand(1).getImm(); Reqs.getAndAddRequirements(SPIRV::OperandCategory::StorageClassOperand, SC, ST); - // If it's a type of pointer to float16, add Float16Buffer capability. + // If it's a type of pointer to float16 targeting OpenCL, add Float16Buffer + // capability. + if (!ST.isOpenCLEnv()) + break; assert(MI.getOperand(2).isReg()); const MachineRegisterInfo &MRI = MI.getMF()->getRegInfo(); SPIRVType *TypeDef = MRI.getVRegDef(MI.getOperand(2).getReg()); diff --git a/llvm/lib/Target/SPIRV/SPIRVStripConvergentIntrinsics.cpp b/llvm/lib/Target/SPIRV/SPIRVStripConvergentIntrinsics.cpp new file mode 100644 index 00000000000..dca30535acf --- /dev/null +++ b/llvm/lib/Target/SPIRV/SPIRVStripConvergentIntrinsics.cpp @@ -0,0 +1,86 @@ +//===-- SPIRVStripConvergentIntrinsics.cpp ----------------------*- C++ -*-===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// +// +// This pass trims convergence intrinsics as those were only useful when +// modifying the CFG during IR passes. +// +//===----------------------------------------------------------------------===// + +#include "SPIRV.h" +#include "SPIRVSubtarget.h" +#include "SPIRVTargetMachine.h" +#include "SPIRVUtils.h" +#include "llvm/CodeGen/IntrinsicLowering.h" +#include "llvm/IR/IRBuilder.h" +#include "llvm/IR/IntrinsicInst.h" +#include "llvm/IR/Intrinsics.h" +#include "llvm/IR/IntrinsicsSPIRV.h" +#include "llvm/Transforms/Utils/Cloning.h" +#include "llvm/Transforms/Utils/LowerMemIntrinsics.h" + +using namespace llvm; + +namespace llvm { +void initializeSPIRVStripConvergentIntrinsicsPass(PassRegistry &); +} + +class SPIRVStripConvergentIntrinsics : public FunctionPass { +public: + static char ID; + + SPIRVStripConvergentIntrinsics() : FunctionPass(ID) { + initializeSPIRVStripConvergentIntrinsicsPass( + *PassRegistry::getPassRegistry()); + }; + + virtual bool runOnFunction(Function &F) override { + DenseSet ToRemove; + + for (BasicBlock &BB : F) { + for (Instruction &I : BB) { + if (auto *II = dyn_cast(&I)) { + if (II->getIntrinsicID() != + Intrinsic::experimental_convergence_entry && + II->getIntrinsicID() != + Intrinsic::experimental_convergence_loop && + II->getIntrinsicID() != + Intrinsic::experimental_convergence_anchor) { + continue; + } + + II->replaceAllUsesWith(UndefValue::get(II->getType())); + ToRemove.insert(II); + } else if (auto *CI = dyn_cast(&I)) { + auto OB = CI->getOperandBundle(LLVMContext::OB_convergencectrl); + if (!OB.has_value()) + continue; + + auto *NewCall = CallBase::removeOperandBundle( + CI, LLVMContext::OB_convergencectrl, CI); + NewCall->copyMetadata(*CI); + CI->replaceAllUsesWith(NewCall); + ToRemove.insert(CI); + } + } + } + + // All usages must be removed before their definition is removed. + for (Instruction *I : ToRemove) + I->eraseFromParent(); + + return ToRemove.size() != 0; + } +}; + +char SPIRVStripConvergentIntrinsics::ID = 0; +INITIALIZE_PASS(SPIRVStripConvergentIntrinsics, "strip-convergent-intrinsics", + "SPIRV strip convergent intrinsics", false, false) + +FunctionPass *llvm::createSPIRVStripConvergenceIntrinsicsPass() { + return new SPIRVStripConvergentIntrinsics(); +} diff --git a/llvm/lib/Target/SPIRV/SPIRVTargetMachine.cpp b/llvm/lib/Target/SPIRV/SPIRVTargetMachine.cpp index 62d9090d289..3485e367dfc 100644 --- a/llvm/lib/Target/SPIRV/SPIRVTargetMachine.cpp +++ b/llvm/lib/Target/SPIRV/SPIRVTargetMachine.cpp @@ -168,6 +168,7 @@ void SPIRVPassConfig::addIRPasses() { TargetPassConfig::addIRPasses(); addPass(createSPIRVRegularizerPass()); addPass(createSPIRVPrepareFunctionsPass(TM)); + addPass(createSPIRVStripConvergenceIntrinsicsPass()); } void SPIRVPassConfig::addISelPrepare() { diff --git a/llvm/lib/Target/Sparc/AsmParser/SparcAsmParser.cpp b/llvm/lib/Target/Sparc/AsmParser/SparcAsmParser.cpp index 54a7d921445..7a956636831 100644 --- a/llvm/lib/Target/Sparc/AsmParser/SparcAsmParser.cpp +++ b/llvm/lib/Target/Sparc/AsmParser/SparcAsmParser.cpp @@ -1352,7 +1352,7 @@ bool SparcAsmParser::matchRegisterName(const AsmToken &Tok, MCRegister &RegNo, return true; } - if (name.substr(0, 3).equals_insensitive("asr") && + if (name.starts_with_insensitive("asr") && !name.substr(3).getAsInteger(10, intVal) && intVal > 0 && intVal < 32) { RegNo = ASRRegs[intVal]; RegKind = SparcOperand::rk_Special; @@ -1421,7 +1421,7 @@ bool SparcAsmParser::matchRegisterName(const AsmToken &Tok, MCRegister &RegNo, } // %fcc0 - %fcc3 - if (name.substr(0, 3).equals_insensitive("fcc") && + if (name.starts_with_insensitive("fcc") && !name.substr(3).getAsInteger(10, intVal) && intVal < 4) { // FIXME: check 64bit and handle %fcc1 - %fcc3 RegNo = Sparc::FCC0 + intVal; @@ -1430,40 +1430,40 @@ bool SparcAsmParser::matchRegisterName(const AsmToken &Tok, MCRegister &RegNo, } // %g0 - %g7 - if (name.substr(0, 1).equals_insensitive("g") && + if (name.starts_with_insensitive("g") && !name.substr(1).getAsInteger(10, intVal) && intVal < 8) { RegNo = IntRegs[intVal]; RegKind = SparcOperand::rk_IntReg; return true; } // %o0 - %o7 - if (name.substr(0, 1).equals_insensitive("o") && + if (name.starts_with_insensitive("o") && !name.substr(1).getAsInteger(10, intVal) && intVal < 8) { RegNo = IntRegs[8 + intVal]; RegKind = SparcOperand::rk_IntReg; return true; } - if (name.substr(0, 1).equals_insensitive("l") && + if (name.starts_with_insensitive("l") && !name.substr(1).getAsInteger(10, intVal) && intVal < 8) { RegNo = IntRegs[16 + intVal]; RegKind = SparcOperand::rk_IntReg; return true; } - if (name.substr(0, 1).equals_insensitive("i") && + if (name.starts_with_insensitive("i") && !name.substr(1).getAsInteger(10, intVal) && intVal < 8) { RegNo = IntRegs[24 + intVal]; RegKind = SparcOperand::rk_IntReg; return true; } // %f0 - %f31 - if (name.substr(0, 1).equals_insensitive("f") && + if (name.starts_with_insensitive("f") && !name.substr(1, 2).getAsInteger(10, intVal) && intVal < 32) { RegNo = FloatRegs[intVal]; RegKind = SparcOperand::rk_FloatReg; return true; } // %f32 - %f62 - if (name.substr(0, 1).equals_insensitive("f") && + if (name.starts_with_insensitive("f") && !name.substr(1, 2).getAsInteger(10, intVal) && intVal >= 32 && intVal <= 62 && (intVal % 2 == 0)) { // FIXME: Check V9 @@ -1473,7 +1473,7 @@ bool SparcAsmParser::matchRegisterName(const AsmToken &Tok, MCRegister &RegNo, } // %r0 - %r31 - if (name.substr(0, 1).equals_insensitive("r") && + if (name.starts_with_insensitive("r") && !name.substr(1, 2).getAsInteger(10, intVal) && intVal < 31) { RegNo = IntRegs[intVal]; RegKind = SparcOperand::rk_IntReg; @@ -1481,7 +1481,7 @@ bool SparcAsmParser::matchRegisterName(const AsmToken &Tok, MCRegister &RegNo, } // %c0 - %c31 - if (name.substr(0, 1).equals_insensitive("c") && + if (name.starts_with_insensitive("c") && !name.substr(1).getAsInteger(10, intVal) && intVal < 32) { RegNo = CoprocRegs[intVal]; RegKind = SparcOperand::rk_CoprocReg; diff --git a/llvm/lib/Target/Sparc/Sparc.td b/llvm/lib/Target/Sparc/Sparc.td index 1a71cfed312..7b103395652 100644 --- a/llvm/lib/Target/Sparc/Sparc.td +++ b/llvm/lib/Target/Sparc/Sparc.td @@ -62,6 +62,13 @@ def UsePopc : SubtargetFeature<"popc", "UsePopc", "true", def FeatureSoftFloat : SubtargetFeature<"soft-float", "UseSoftFloat", "true", "Use software emulation for floating point">; +//===----------------------------------------------------------------------===// +// SPARC Subtarget tuning features. +// + +def TuneSlowRDPC : SubtargetFeature<"slow-rdpc", "HasSlowRDPC", "true", + "rd %pc, %XX is slow", [FeatureV9]>; + //==== Features added predmoninantly for LEON subtarget support include "LeonFeatures.td" @@ -89,8 +96,9 @@ def SparcAsmParserVariant : AsmParserVariant { // SPARC processors supported. //===----------------------------------------------------------------------===// -class Proc Features> - : Processor; +class Proc Features, + list TuneFeatures = []> + : Processor; def : Proc<"generic", []>; def : Proc<"v7", [FeatureSoftMulDiv, FeatureNoFSMULD]>; @@ -118,9 +126,11 @@ def : Proc<"ma2480", [FeatureLeon, LeonCASA]>; def : Proc<"ma2485", [FeatureLeon, LeonCASA]>; def : Proc<"ma2x8x", [FeatureLeon, LeonCASA]>; def : Proc<"v9", [FeatureV9]>; -def : Proc<"ultrasparc", [FeatureV9, FeatureV8Deprecated, FeatureVIS]>; +def : Proc<"ultrasparc", [FeatureV9, FeatureV8Deprecated, FeatureVIS], + [TuneSlowRDPC]>; def : Proc<"ultrasparc3", [FeatureV9, FeatureV8Deprecated, FeatureVIS, - FeatureVIS2]>; + FeatureVIS2], + [TuneSlowRDPC]>; def : Proc<"niagara", [FeatureV9, FeatureV8Deprecated, FeatureVIS, FeatureVIS2]>; def : Proc<"niagara2", [FeatureV9, FeatureV8Deprecated, UsePopc, diff --git a/llvm/lib/Target/Sparc/SparcAsmPrinter.cpp b/llvm/lib/Target/Sparc/SparcAsmPrinter.cpp index cca624e0926..215a8ea8319 100644 --- a/llvm/lib/Target/Sparc/SparcAsmPrinter.cpp +++ b/llvm/lib/Target/Sparc/SparcAsmPrinter.cpp @@ -13,6 +13,7 @@ #include "MCTargetDesc/SparcInstPrinter.h" #include "MCTargetDesc/SparcMCExpr.h" +#include "MCTargetDesc/SparcMCTargetDesc.h" #include "MCTargetDesc/SparcTargetStreamer.h" #include "Sparc.h" #include "SparcInstrInfo.h" @@ -111,6 +112,15 @@ static void EmitCall(MCStreamer &OutStreamer, OutStreamer.emitInstruction(CallInst, STI); } +static void EmitRDPC(MCStreamer &OutStreamer, MCOperand &RD, + const MCSubtargetInfo &STI) { + MCInst RDPCInst; + RDPCInst.setOpcode(SP::RDASR); + RDPCInst.addOperand(RD); + RDPCInst.addOperand(MCOperand::createReg(SP::ASR5)); + OutStreamer.emitInstruction(RDPCInst, STI); +} + static void EmitSETHI(MCStreamer &OutStreamer, MCOperand &Imm, MCOperand &RD, const MCSubtargetInfo &STI) @@ -226,7 +236,7 @@ void SparcAsmPrinter::LowerGETPCXAndEmitMCInsts(const MachineInstr *MI, MCOperand RegO7 = MCOperand::createReg(SP::O7); // : - // call + // // This will be either `call ` or `rd %pc, %o7`. // : // sethi %hi(_GLOBAL_OFFSET_TABLE_+(-)), // : @@ -234,8 +244,17 @@ void SparcAsmPrinter::LowerGETPCXAndEmitMCInsts(const MachineInstr *MI, // add , %o7, OutStreamer->emitLabel(StartLabel); - MCOperand Callee = createPCXCallOP(EndLabel, OutContext); - EmitCall(*OutStreamer, Callee, STI); + if (!STI.getTargetTriple().isSPARC64() || + STI.hasFeature(Sparc::TuneSlowRDPC)) { + MCOperand Callee = createPCXCallOP(EndLabel, OutContext); + EmitCall(*OutStreamer, Callee, STI); + } else { + // TODO find out whether it is possible to store PC + // in other registers, to enable leaf function optimization. + // (On the other hand, approx. over 97.8% of GETPCXes happen + // in non-leaf functions, so would this be worth the effort?) + EmitRDPC(*OutStreamer, RegO7, STI); + } OutStreamer->emitLabel(SethiLabel); MCOperand hiImm = createPCXRelExprOp(SparcMCExpr::VK_Sparc_PC22, GOTLabel, StartLabel, SethiLabel, diff --git a/llvm/lib/Target/Sparc/SparcSubtarget.cpp b/llvm/lib/Target/Sparc/SparcSubtarget.cpp index 81c2137ea73..6b09904ca5e 100644 --- a/llvm/lib/Target/Sparc/SparcSubtarget.cpp +++ b/llvm/lib/Target/Sparc/SparcSubtarget.cpp @@ -12,6 +12,7 @@ #include "SparcSubtarget.h" #include "Sparc.h" +#include "llvm/ADT/StringRef.h" #include "llvm/MC/TargetRegistry.h" #include "llvm/Support/MathExtras.h" @@ -25,15 +26,18 @@ using namespace llvm; void SparcSubtarget::anchor() { } -SparcSubtarget &SparcSubtarget::initializeSubtargetDependencies(StringRef CPU, - StringRef FS) { +SparcSubtarget &SparcSubtarget::initializeSubtargetDependencies( + StringRef CPU, StringRef TuneCPU, StringRef FS) { // Determine default and user specified characteristics std::string CPUName = std::string(CPU); if (CPUName.empty()) CPUName = (Is64Bit) ? "v9" : "v8"; + if (TuneCPU.empty()) + TuneCPU = CPUName; + // Parse features string. - ParseSubtargetFeatures(CPUName, /*TuneCPU*/ CPUName, FS); + ParseSubtargetFeatures(CPUName, TuneCPU, FS); // Popc is a v9-only instruction. if (!IsV9) @@ -42,11 +46,12 @@ SparcSubtarget &SparcSubtarget::initializeSubtargetDependencies(StringRef CPU, return *this; } -SparcSubtarget::SparcSubtarget(const Triple &TT, const std::string &CPU, - const std::string &FS, const TargetMachine &TM, +SparcSubtarget::SparcSubtarget(const StringRef &CPU, const StringRef &TuneCPU, + const StringRef &FS, const TargetMachine &TM, bool is64Bit) - : SparcGenSubtargetInfo(TT, CPU, /*TuneCPU*/ CPU, FS), TargetTriple(TT), - Is64Bit(is64Bit), InstrInfo(initializeSubtargetDependencies(CPU, FS)), + : SparcGenSubtargetInfo(TM.getTargetTriple(), CPU, TuneCPU, FS), + TargetTriple(TM.getTargetTriple()), Is64Bit(is64Bit), + InstrInfo(initializeSubtargetDependencies(CPU, TuneCPU, FS)), TLInfo(TM, *this), FrameLowering(*this) {} int SparcSubtarget::getAdjustedFrameSize(int frameSize) const { diff --git a/llvm/lib/Target/Sparc/SparcSubtarget.h b/llvm/lib/Target/Sparc/SparcSubtarget.h index 8e3d05d5d7e..cdb210f6748 100644 --- a/llvm/lib/Target/Sparc/SparcSubtarget.h +++ b/llvm/lib/Target/Sparc/SparcSubtarget.h @@ -44,8 +44,8 @@ class SparcSubtarget : public SparcGenSubtargetInfo { SparcFrameLowering FrameLowering; public: - SparcSubtarget(const Triple &TT, const std::string &CPU, - const std::string &FS, const TargetMachine &TM, bool is64bit); + SparcSubtarget(const StringRef &CPU, const StringRef &TuneCPU, + const StringRef &FS, const TargetMachine &TM, bool is64bit); const SparcInstrInfo *getInstrInfo() const override { return &InstrInfo; } const TargetFrameLowering *getFrameLowering() const override { @@ -70,7 +70,9 @@ public: /// ParseSubtargetFeatures - Parses features string setting specified /// subtarget options. Definition of function is auto generated by tblgen. void ParseSubtargetFeatures(StringRef CPU, StringRef TuneCPU, StringRef FS); - SparcSubtarget &initializeSubtargetDependencies(StringRef CPU, StringRef FS); + SparcSubtarget &initializeSubtargetDependencies(StringRef CPU, + StringRef TuneCPU, + StringRef FS); bool is64Bit() const { return Is64Bit; } diff --git a/llvm/lib/Target/Sparc/SparcTargetMachine.cpp b/llvm/lib/Target/Sparc/SparcTargetMachine.cpp index dbc26636e39..b408af2ea59 100644 --- a/llvm/lib/Target/Sparc/SparcTargetMachine.cpp +++ b/llvm/lib/Target/Sparc/SparcTargetMachine.cpp @@ -116,10 +116,13 @@ SparcTargetMachine::~SparcTargetMachine() = default; const SparcSubtarget * SparcTargetMachine::getSubtargetImpl(const Function &F) const { Attribute CPUAttr = F.getFnAttribute("target-cpu"); + Attribute TuneAttr = F.getFnAttribute("tune-cpu"); Attribute FSAttr = F.getFnAttribute("target-features"); std::string CPU = CPUAttr.isValid() ? CPUAttr.getValueAsString().str() : TargetCPU; + std::string TuneCPU = + TuneAttr.isValid() ? TuneAttr.getValueAsString().str() : CPU; std::string FS = FSAttr.isValid() ? FSAttr.getValueAsString().str() : TargetFS; @@ -137,8 +140,8 @@ SparcTargetMachine::getSubtargetImpl(const Function &F) const { // creation will depend on the TM and the code generation flags on the // function that reside in TargetOptions. resetTargetOptions(F); - I = std::make_unique(TargetTriple, CPU, FS, *this, - this->is64Bit); + I = std::make_unique(CPU, TuneCPU, FS, *this, + this->is64Bit); } return I.get(); } diff --git a/llvm/lib/Target/SystemZ/SystemZElimCompare.cpp b/llvm/lib/Target/SystemZ/SystemZElimCompare.cpp index 340dba1362a..7423ed429ff 100644 --- a/llvm/lib/Target/SystemZ/SystemZElimCompare.cpp +++ b/llvm/lib/Target/SystemZ/SystemZElimCompare.cpp @@ -115,12 +115,6 @@ static bool preservesValueOf(MachineInstr &MI, unsigned Reg) { case SystemZ::LTR: case SystemZ::LTGR: case SystemZ::LTGFR: - case SystemZ::LER: - case SystemZ::LDR: - case SystemZ::LXR: - case SystemZ::LTEBR: - case SystemZ::LTDBR: - case SystemZ::LTXBR: if (MI.getOperand(1).getReg() == Reg) return true; } @@ -498,18 +492,10 @@ bool SystemZElimCompare::adjustCCMasksForInstr( // Return true if Compare is a comparison against zero. static bool isCompareZero(MachineInstr &Compare) { - switch (Compare.getOpcode()) { - case SystemZ::LTEBRCompare: - case SystemZ::LTDBRCompare: - case SystemZ::LTXBRCompare: + if (isLoadAndTestAsCmp(Compare)) return true; - - default: - if (isLoadAndTestAsCmp(Compare)) - return true; - return Compare.getNumExplicitOperands() == 2 && - Compare.getOperand(1).isImm() && Compare.getOperand(1).getImm() == 0; - } + return Compare.getNumExplicitOperands() == 2 && + Compare.getOperand(1).isImm() && Compare.getOperand(1).getImm() == 0; } // Try to optimize cases where comparison instruction Compare is testing @@ -569,7 +555,7 @@ bool SystemZElimCompare::optimizeCompareZero( // Also do a forward search to handle cases where an instruction after the // compare can be converted, like - // LTEBRCompare %f0s, %f0s; %f2s = LER %f0s => LTEBRCompare %f2s, %f0s + // CGHI %r0d, 0; %r1d = LGR %r0d => LTGR %r1d, %r0d auto MIRange = llvm::make_range( std::next(MachineBasicBlock::iterator(&Compare)), MBB.end()); for (MachineInstr &MI : llvm::make_early_inc_range(MIRange)) { diff --git a/llvm/lib/Target/SystemZ/SystemZISelLowering.cpp b/llvm/lib/Target/SystemZ/SystemZISelLowering.cpp index 7d387c7b9f2..924df12578f 100644 --- a/llvm/lib/Target/SystemZ/SystemZISelLowering.cpp +++ b/llvm/lib/Target/SystemZ/SystemZISelLowering.cpp @@ -6046,8 +6046,7 @@ SDValue SystemZTargetLowering::lowerIS_FPCLASS(SDValue Op, SDLoc DL(Op); MVT ResultVT = Op.getSimpleValueType(); SDValue Arg = Op.getOperand(0); - auto CNode = cast(Op.getOperand(1)); - unsigned Check = CNode->getZExtValue(); + unsigned Check = Op.getConstantOperandVal(1); unsigned TDCMask = 0; if (Check & fcSNan) @@ -9438,11 +9437,11 @@ MachineBasicBlock *SystemZTargetLowering::EmitInstrWithCustomInserter( return emitTransactionBegin(MI, MBB, SystemZ::TBEGIN, true); case SystemZ::TBEGINC: return emitTransactionBegin(MI, MBB, SystemZ::TBEGINC, true); - case SystemZ::LTEBRCompare_VecPseudo: + case SystemZ::LTEBRCompare_Pseudo: return emitLoadAndTestCmp0(MI, MBB, SystemZ::LTEBR); - case SystemZ::LTDBRCompare_VecPseudo: + case SystemZ::LTDBRCompare_Pseudo: return emitLoadAndTestCmp0(MI, MBB, SystemZ::LTDBR); - case SystemZ::LTXBRCompare_VecPseudo: + case SystemZ::LTXBRCompare_Pseudo: return emitLoadAndTestCmp0(MI, MBB, SystemZ::LTXBR); case SystemZ::PROBED_ALLOCA: diff --git a/llvm/lib/Target/SystemZ/SystemZInstrFP.td b/llvm/lib/Target/SystemZ/SystemZInstrFP.td index ea62e99a583..6e67425c1e7 100644 --- a/llvm/lib/Target/SystemZ/SystemZInstrFP.td +++ b/llvm/lib/Target/SystemZ/SystemZInstrFP.td @@ -51,36 +51,27 @@ let isCodeGenOnly = 1 in def LDR32 : UnaryRR<"ldr", 0x28, null_frag, FP32, FP32>; // Moves between two floating-point registers that also set the condition -// codes. +// codes. Note that these instructions will turn SNaNs into QNaNs and should +// not be used for comparison if the result will be used afterwards. let Uses = [FPC], mayRaiseFPException = 1, Defs = [CC], CCValues = 0xF, CompareZeroCCMask = 0xF in { - defm LTEBR : LoadAndTestRRE<"ltebr", 0xB302, FP32>; - defm LTDBR : LoadAndTestRRE<"ltdbr", 0xB312, FP64>; - defm LTXBR : LoadAndTestRRE<"ltxbr", 0xB342, FP128>; -} -// Note that LTxBRCompare is not available if we have vector support, -// since load-and-test instructions will partially clobber the target -// (vector) register. -let Predicates = [FeatureNoVector] in { - defm : CompareZeroFP; - defm : CompareZeroFP; - defm : CompareZeroFP; + def LTEBR : UnaryRRE<"ltebr", 0xB302, null_frag, FP32, FP32>; + def LTDBR : UnaryRRE<"ltdbr", 0xB312, null_frag, FP64, FP64>; + def LTXBR : UnaryRRE<"ltxbr", 0xB342, null_frag, FP128, FP128>; } -// Use a normal load-and-test for compare against zero in case of -// vector support (via a pseudo to simplify instruction selection). +// Use a load-and-test for compare against zero (via a pseudo to simplify +// instruction selection). let Uses = [FPC], mayRaiseFPException = 1, Defs = [CC], usesCustomInserter = 1, hasNoSchedulingInfo = 1 in { - def LTEBRCompare_VecPseudo : Pseudo<(outs), (ins FP32:$R1, FP32:$R2), []>; - def LTDBRCompare_VecPseudo : Pseudo<(outs), (ins FP64:$R1, FP64:$R2), []>; - def LTXBRCompare_VecPseudo : Pseudo<(outs), (ins FP128:$R1, FP128:$R2), []>; + def LTEBRCompare_Pseudo : Pseudo<(outs), (ins FP32:$R1), []>; + def LTDBRCompare_Pseudo : Pseudo<(outs), (ins FP64:$R1), []>; + def LTXBRCompare_Pseudo : Pseudo<(outs), (ins FP128:$R1), []>; } -let Predicates = [FeatureVector] in { - defm : CompareZeroFP; - defm : CompareZeroFP; -} -let Predicates = [FeatureVector, FeatureNoVectorEnhancements1] in - defm : CompareZeroFP; +defm : CompareZeroFP; +defm : CompareZeroFP; +let Predicates = [FeatureNoVectorEnhancements1] in + defm : CompareZeroFP; // Moves between 64-bit integer and floating-point registers. def LGDR : UnaryRRE<"lgdr", 0xB3CD, bitconvert, GR64, FP64>; diff --git a/llvm/lib/Target/SystemZ/SystemZInstrFormats.td b/llvm/lib/Target/SystemZ/SystemZInstrFormats.td index 2e5ff4a1df6..bb9fa0fc33f 100644 --- a/llvm/lib/Target/SystemZ/SystemZInstrFormats.td +++ b/llvm/lib/Target/SystemZ/SystemZInstrFormats.td @@ -5036,18 +5036,6 @@ class BranchPreloadMII opcode> (ins imm32zx4:$M1, brtarget12bpp:$RI2, brtarget24bpp:$RI3), mnemonic#"\t$M1, $RI2, $RI3", []>; -// A floating-point load-and test operation. Create both a normal unary -// operation and one that acts as a comparison against zero. -// Note that the comparison against zero operation is not available if we -// have vector support, since load-and-test instructions will partially -// clobber the target (vector) register. -multiclass LoadAndTestRRE opcode, - RegisterOperand cls> { - def "" : UnaryRRE; - let isCodeGenOnly = 1, Predicates = [FeatureNoVector] in - def Compare : CompareRRE; -} - //===----------------------------------------------------------------------===// // Pseudo instructions //===----------------------------------------------------------------------===// diff --git a/llvm/lib/Target/SystemZ/SystemZInstrInfo.cpp b/llvm/lib/Target/SystemZ/SystemZInstrInfo.cpp index ac8c395f906..bf6547cc87e 100644 --- a/llvm/lib/Target/SystemZ/SystemZInstrInfo.cpp +++ b/llvm/lib/Target/SystemZ/SystemZInstrInfo.cpp @@ -1692,9 +1692,6 @@ unsigned SystemZInstrInfo::getLoadAndTest(unsigned Opcode) const { case SystemZ::LR: return SystemZ::LTR; case SystemZ::LGFR: return SystemZ::LTGFR; case SystemZ::LGR: return SystemZ::LTGR; - case SystemZ::LER: return SystemZ::LTEBR; - case SystemZ::LDR: return SystemZ::LTDBR; - case SystemZ::LXR: return SystemZ::LTXBR; case SystemZ::LCDFR: return SystemZ::LCDBR; case SystemZ::LPDFR: return SystemZ::LPDBR; case SystemZ::LNDFR: return SystemZ::LNDBR; diff --git a/llvm/lib/Target/SystemZ/SystemZPatterns.td b/llvm/lib/Target/SystemZ/SystemZPatterns.td index e3190eddb9f..5e5dca77e95 100644 --- a/llvm/lib/Target/SystemZ/SystemZPatterns.td +++ b/llvm/lib/Target/SystemZ/SystemZPatterns.td @@ -145,12 +145,11 @@ multiclass BlockLoadStore { - def : Pat<(z_any_fcmp cls:$reg, (fpimm0)), (insn cls:$reg, cls:$reg)>; + def : Pat<(z_any_fcmp cls:$reg, (fpimm0)), (insn cls:$reg)>; // The sign of the zero makes no difference. - def : Pat<(z_any_fcmp cls:$reg, (fpimmneg0)), (insn cls:$reg, cls:$reg)>; + def : Pat<(z_any_fcmp cls:$reg, (fpimmneg0)), (insn cls:$reg)>; } // Use INSN for performing binary operation OPERATION of type VT diff --git a/llvm/lib/Target/SystemZ/SystemZRegisterInfo.cpp b/llvm/lib/Target/SystemZ/SystemZRegisterInfo.cpp index d5313acd878..d246d3f3c5b 100644 --- a/llvm/lib/Target/SystemZ/SystemZRegisterInfo.cpp +++ b/llvm/lib/Target/SystemZ/SystemZRegisterInfo.cpp @@ -387,7 +387,8 @@ bool SystemZRegisterInfo::shouldCoalesce(MachineInstr *MI, // Coalesce anything which is not a COPY involving a subreg to/from GR128. if (!(NewRC->hasSuperClassEq(&SystemZ::GR128BitRegClass) && - (getRegSizeInBits(*SrcRC) <= 64 || getRegSizeInBits(*DstRC) <= 64))) + (getRegSizeInBits(*SrcRC) <= 64 || getRegSizeInBits(*DstRC) <= 64) && + !MI->getOperand(1).isUndef())) return true; // Allow coalescing of a GR128 subreg COPY only if the subreg liverange is diff --git a/llvm/lib/Target/SystemZ/SystemZScheduleZ13.td b/llvm/lib/Target/SystemZ/SystemZScheduleZ13.td index fe84ca45374..9ce1a0d06b5 100644 --- a/llvm/lib/Target/SystemZ/SystemZScheduleZ13.td +++ b/llvm/lib/Target/SystemZ/SystemZScheduleZ13.td @@ -784,9 +784,7 @@ def : InstRW<[WLat2, FXb2, GroupAlone], (instregex "LXR$")>; // Load and Test def : InstRW<[WLat3, WLat3, VecXsPm, NormalGr], (instregex "LT(E|D)BR$")>; -def : InstRW<[WLat3, VecXsPm, NormalGr], (instregex "LT(E|D)BRCompare$")>; -def : InstRW<[WLat10, WLat10, VecDF4, GroupAlone], - (instregex "LTXBR(Compare)?$")>; +def : InstRW<[WLat10, WLat10, VecDF4, GroupAlone], (instregex "LTXBR$")>; // Copy sign def : InstRW<[WLat2, VecXsPm, NormalGr], (instregex "CPSDR(d|s)(d|s)$")>; diff --git a/llvm/lib/Target/SystemZ/SystemZScheduleZ14.td b/llvm/lib/Target/SystemZ/SystemZScheduleZ14.td index d5eab33dbb4..7e6302ae656 100644 --- a/llvm/lib/Target/SystemZ/SystemZScheduleZ14.td +++ b/llvm/lib/Target/SystemZ/SystemZScheduleZ14.td @@ -804,9 +804,7 @@ def : InstRW<[WLat2, FXb2, GroupAlone], (instregex "LXR$")>; // Load and Test def : InstRW<[WLat3, WLat3, VecXsPm, NormalGr], (instregex "LT(E|D)BR$")>; -def : InstRW<[WLat3, VecXsPm, NormalGr], (instregex "LT(E|D)BRCompare$")>; -def : InstRW<[WLat10, WLat10, VecDF4, GroupAlone], - (instregex "LTXBR(Compare)?$")>; +def : InstRW<[WLat10, WLat10, VecDF4, GroupAlone], (instregex "LTXBR$")>; // Copy sign def : InstRW<[WLat2, VecXsPm, NormalGr], (instregex "CPSDR(d|s)(d|s)$")>; diff --git a/llvm/lib/Target/SystemZ/SystemZScheduleZ15.td b/llvm/lib/Target/SystemZ/SystemZScheduleZ15.td index 09b505fc149..89edcf426bd 100644 --- a/llvm/lib/Target/SystemZ/SystemZScheduleZ15.td +++ b/llvm/lib/Target/SystemZ/SystemZScheduleZ15.td @@ -821,9 +821,7 @@ def : InstRW<[WLat2, FXb2, GroupAlone], (instregex "LXR$")>; // Load and Test def : InstRW<[WLat3, WLat3, VecXsPm, NormalGr], (instregex "LT(E|D)BR$")>; -def : InstRW<[WLat3, VecXsPm, NormalGr], (instregex "LT(E|D)BRCompare$")>; -def : InstRW<[WLat10, WLat10, VecDF4, GroupAlone], - (instregex "LTXBR(Compare)?$")>; +def : InstRW<[WLat10, WLat10, VecDF4, GroupAlone], (instregex "LTXBR$")>; // Copy sign def : InstRW<[WLat2, VecXsPm, NormalGr], (instregex "CPSDR(d|s)(d|s)$")>; diff --git a/llvm/lib/Target/SystemZ/SystemZScheduleZ16.td b/llvm/lib/Target/SystemZ/SystemZScheduleZ16.td index 695604af1b8..8f6dc3befc1 100644 --- a/llvm/lib/Target/SystemZ/SystemZScheduleZ16.td +++ b/llvm/lib/Target/SystemZ/SystemZScheduleZ16.td @@ -822,9 +822,7 @@ def : InstRW<[WLat2, FXb2, GroupAlone], (instregex "LXR$")>; // Load and Test def : InstRW<[WLat3, WLat3, VecXsPm, NormalGr], (instregex "LT(E|D)BR$")>; -def : InstRW<[WLat3, VecXsPm, NormalGr], (instregex "LT(E|D)BRCompare$")>; -def : InstRW<[WLat10, WLat10, VecDF4, GroupAlone], - (instregex "LTXBR(Compare)?$")>; +def : InstRW<[WLat10, WLat10, VecDF4, GroupAlone], (instregex "LTXBR$")>; // Copy sign def : InstRW<[WLat2, VecXsPm, NormalGr], (instregex "CPSDR(d|s)(d|s)$")>; diff --git a/llvm/lib/Target/SystemZ/SystemZScheduleZ196.td b/llvm/lib/Target/SystemZ/SystemZScheduleZ196.td index 98ea7d09490..226db9d4272 100644 --- a/llvm/lib/Target/SystemZ/SystemZScheduleZ196.td +++ b/llvm/lib/Target/SystemZ/SystemZScheduleZ196.td @@ -716,8 +716,7 @@ def : InstRW<[WLat2, FXU2, GroupAlone2], (instregex "LXR$")>; // Load and Test def : InstRW<[WLat9, WLat9, FPU, NormalGr], (instregex "LT(E|D)BR$")>; -def : InstRW<[WLat9, FPU, NormalGr], (instregex "LT(E|D)BRCompare$")>; -def : InstRW<[WLat10, WLat10, FPU4, GroupAlone], (instregex "LTXBR(Compare)?$")>; +def : InstRW<[WLat10, WLat10, FPU4, GroupAlone], (instregex "LTXBR$")>; // Copy sign def : InstRW<[WLat5, FXU2, GroupAlone], (instregex "CPSDR(d|s)(d|s)$")>; diff --git a/llvm/lib/Target/SystemZ/SystemZScheduleZEC12.td b/llvm/lib/Target/SystemZ/SystemZScheduleZEC12.td index bd0bc480a00..f5ecdb1f438 100644 --- a/llvm/lib/Target/SystemZ/SystemZScheduleZEC12.td +++ b/llvm/lib/Target/SystemZ/SystemZScheduleZEC12.td @@ -754,8 +754,7 @@ def : InstRW<[WLat2, FXU2, GroupAlone], (instregex "LXR$")>; // Load and Test def : InstRW<[WLat9, WLat9, FPU, NormalGr], (instregex "LT(E|D)BR$")>; -def : InstRW<[WLat9, FPU, NormalGr], (instregex "LT(E|D)BRCompare$")>; -def : InstRW<[WLat10, WLat10, FPU4, GroupAlone], (instregex "LTXBR(Compare)?$")>; +def : InstRW<[WLat10, WLat10, FPU4, GroupAlone], (instregex "LTXBR$")>; // Copy sign def : InstRW<[WLat5, FXU2, GroupAlone], (instregex "CPSDR(d|s)(d|s)$")>; diff --git a/llvm/lib/Target/SystemZ/SystemZTargetTransformInfo.cpp b/llvm/lib/Target/SystemZ/SystemZTargetTransformInfo.cpp index 1f97e0f761c..9370fb51a96 100644 --- a/llvm/lib/Target/SystemZ/SystemZTargetTransformInfo.cpp +++ b/llvm/lib/Target/SystemZ/SystemZTargetTransformInfo.cpp @@ -75,8 +75,8 @@ InstructionCost SystemZTTIImpl::getIntImmCost(const APInt &Imm, Type *Ty, // here, so that constant hoisting will ignore this constant. if (BitSize == 0) return TTI::TCC_Free; - // No cost model for operations on integers larger than 64 bit implemented yet. - if (BitSize > 64) + // No cost model for operations on integers larger than 128 bit implemented yet. + if ((!ST->hasVector() && BitSize > 64) || BitSize > 128) return TTI::TCC_Free; if (Imm == 0) @@ -96,7 +96,8 @@ InstructionCost SystemZTTIImpl::getIntImmCost(const APInt &Imm, Type *Ty, return 2 * TTI::TCC_Basic; } - return 4 * TTI::TCC_Basic; + // i128 immediates loads from Constant Pool + return 2 * TTI::TCC_Basic; } InstructionCost SystemZTTIImpl::getIntImmCostInst(unsigned Opcode, unsigned Idx, @@ -479,21 +480,27 @@ InstructionCost SystemZTTIImpl::getArithmeticInstrCost( return LIBCALL_COST; // Give discount for some combined logical operations if supported. - if (Args.size() == 2 && ST->hasMiscellaneousExtensions3()) { + if (Args.size() == 2) { if (Opcode == Instruction::Xor) { for (const Value *A : Args) { if (const Instruction *I = dyn_cast(A)) if (I->hasOneUse() && - (I->getOpcode() == Instruction::And || - I->getOpcode() == Instruction::Or || + (I->getOpcode() == Instruction::Or || + I->getOpcode() == Instruction::And || I->getOpcode() == Instruction::Xor)) - return 0; + if ((ScalarBits <= 64 && ST->hasMiscellaneousExtensions3()) || + (isInt128InVR(Ty) && + (I->getOpcode() == Instruction::Or || ST->hasVectorEnhancements1()))) + return 0; } } - else if (Opcode == Instruction::Or || Opcode == Instruction::And) { + else if (Opcode == Instruction::And || Opcode == Instruction::Or) { for (const Value *A : Args) { if (const Instruction *I = dyn_cast(A)) - if (I->hasOneUse() && I->getOpcode() == Instruction::Xor) + if ((I->hasOneUse() && I->getOpcode() == Instruction::Xor) && + ((ScalarBits <= 64 && ST->hasMiscellaneousExtensions3()) || + (isInt128InVR(Ty) && + (Opcode == Instruction::And || ST->hasVectorEnhancements1())))) return 0; } } @@ -774,29 +781,63 @@ InstructionCost SystemZTTIImpl::getCastInstrCost(unsigned Opcode, Type *Dst, assert (!Dst->isVectorTy()); if (Opcode == Instruction::SIToFP || Opcode == Instruction::UIToFP) { + if (Src->isIntegerTy(128)) + return LIBCALL_COST; if (SrcScalarBits >= 32 || (I != nullptr && isa(I->getOperand(0)))) return 1; return SrcScalarBits > 1 ? 2 /*i8/i16 extend*/ : 5 /*branch seq.*/; } - if ((Opcode == Instruction::ZExt || Opcode == Instruction::SExt) && - Src->isIntegerTy(1)) { - if (ST->hasLoadStoreOnCond2()) - return 2; // li 0; loc 1 + if ((Opcode == Instruction::FPToSI || Opcode == Instruction::FPToUI) && + Dst->isIntegerTy(128)) + return LIBCALL_COST; - // This should be extension of a compare i1 result, which is done with - // ipm and a varying sequence of instructions. - unsigned Cost = 0; - if (Opcode == Instruction::SExt) - Cost = (DstScalarBits < 64 ? 3 : 4); - if (Opcode == Instruction::ZExt) - Cost = 3; - Type *CmpOpTy = ((I != nullptr) ? getCmpOpsType(I) : nullptr); - if (CmpOpTy != nullptr && CmpOpTy->isFloatingPointTy()) - // If operands of an fp-type was compared, this costs +1. - Cost++; - return Cost; + if ((Opcode == Instruction::ZExt || Opcode == Instruction::SExt)) { + if (Src->isIntegerTy(1)) { + if (DstScalarBits == 128) + return 5 /*branch seq.*/; + + if (ST->hasLoadStoreOnCond2()) + return 2; // li 0; loc 1 + + // This should be extension of a compare i1 result, which is done with + // ipm and a varying sequence of instructions. + unsigned Cost = 0; + if (Opcode == Instruction::SExt) + Cost = (DstScalarBits < 64 ? 3 : 4); + if (Opcode == Instruction::ZExt) + Cost = 3; + Type *CmpOpTy = ((I != nullptr) ? getCmpOpsType(I) : nullptr); + if (CmpOpTy != nullptr && CmpOpTy->isFloatingPointTy()) + // If operands of an fp-type was compared, this costs +1. + Cost++; + return Cost; + } + else if (isInt128InVR(Dst)) { + // Extensions from GPR to i128 (in VR) typically costs two instructions, + // but a zero-extending load would be just one extra instruction. + if (Opcode == Instruction::ZExt && I != nullptr) + if (LoadInst *Ld = dyn_cast(I->getOperand(0))) + if (Ld->hasOneUse()) + return 1; + return 2; + } + } + + if (Opcode == Instruction::Trunc && isInt128InVR(Src) && I != nullptr) { + if (LoadInst *Ld = dyn_cast(I->getOperand(0))) + if (Ld->hasOneUse()) + return 0; // Will be converted to GPR load. + bool OnlyTruncatingStores = true; + for (const User *U : I->users()) + if (!isa(U)) { + OnlyTruncatingStores = false; + break; + } + if (OnlyTruncatingStores) + return 0; + return 2; // Vector element extraction. } } else if (ST->hasVector()) { @@ -930,7 +971,7 @@ InstructionCost SystemZTTIImpl::getCmpSelInstrCost(unsigned Opcode, Type *ValTy, // A loaded value compared with 0 with multiple users becomes Load and // Test. The load is then not foldable, so return 0 cost for the ICmp. unsigned ScalarBits = ValTy->getScalarSizeInBits(); - if (I != nullptr && ScalarBits >= 32) + if (I != nullptr && (ScalarBits == 32 || ScalarBits == 64)) if (LoadInst *Ld = dyn_cast(I->getOperand(0))) if (const ConstantInt *C = dyn_cast(I->getOperand(1))) if (!Ld->hasOneUse() && Ld->getParent() == I->getParent() && @@ -943,8 +984,8 @@ InstructionCost SystemZTTIImpl::getCmpSelInstrCost(unsigned Opcode, Type *ValTy, return Cost; } case Instruction::Select: - if (ValTy->isFloatingPointTy()) - return 4; // No load on condition for FP - costs a conditional jump. + if (ValTy->isFloatingPointTy() || isInt128InVR(ValTy)) + return 4; // No LOC for FP / i128 - costs a conditional jump. return 1; // Load On Condition / Select Register. } } @@ -1157,6 +1198,10 @@ InstructionCost SystemZTTIImpl::getMemoryOpCost(unsigned Opcode, Type *Src, return BaseT::getMemoryOpCost(Opcode, Src, Alignment, AddressSpace, CostKind); + // FP128 is a legal type but kept in a register pair on older CPUs. + if (Src->isFP128Ty() && !ST->hasVectorEnhancements1()) + return 2; + unsigned NumOps = (Src->isVectorTy() ? getNumVectorRegs(Src) : getNumberOfParts(Src)); @@ -1177,10 +1222,6 @@ InstructionCost SystemZTTIImpl::getMemoryOpCost(unsigned Opcode, Type *Src, } } - if (Src->getScalarSizeInBits() == 128) - // 128 bit scalars are held in a pair of two 64 bit registers. - NumOps *= 2; - return NumOps; } @@ -1236,7 +1277,6 @@ InstructionCost SystemZTTIImpl::getInterleavedMemoryOpCost( // dst vector for vperm (S.A.). unsigned NumSrcVecs = std::min(NumEltsPerVecReg, Factor); unsigned NumDstVecs = NumVectorMemOps; - assert (NumSrcVecs > 1 && "Expected at least two source vectors."); NumPermutes += (NumDstVecs * NumSrcVecs) - NumDstVecs; } diff --git a/llvm/lib/Target/SystemZ/SystemZTargetTransformInfo.h b/llvm/lib/Target/SystemZ/SystemZTargetTransformInfo.h index 62c59ddc3f0..2cccdf6d17d 100644 --- a/llvm/lib/Target/SystemZ/SystemZTargetTransformInfo.h +++ b/llvm/lib/Target/SystemZ/SystemZTargetTransformInfo.h @@ -28,6 +28,8 @@ class SystemZTTIImpl : public BasicTTIImplBase { unsigned const LIBCALL_COST = 30; + bool isInt128InVR(Type *Ty) { return Ty->isIntegerTy(128) && ST->hasVector(); } + public: explicit SystemZTTIImpl(const SystemZTargetMachine *TM, const Function &F) : BaseT(TM, F.getParent()->getDataLayout()), ST(TM->getSubtargetImpl(F)), diff --git a/llvm/lib/Target/TargetMachine.cpp b/llvm/lib/Target/TargetMachine.cpp index 2a4383314e4..0839fb22d35 100644 --- a/llvm/lib/Target/TargetMachine.cpp +++ b/llvm/lib/Target/TargetMachine.cpp @@ -58,24 +58,8 @@ bool TargetMachine::isLargeGlobalValue(const GlobalValue *GVal) const { if (GV->isThreadLocal()) return false; - // We should properly mark well-known section name prefixes as small/large, - // because otherwise the output section may have the wrong section flags and - // the linker will lay it out in an unexpected way. - StringRef Name = GV->getSection(); - if (!Name.empty()) { - auto IsPrefix = [&](StringRef Prefix) { - StringRef S = Name; - return S.consume_front(Prefix) && (S.empty() || S[0] == '.'); - }; - if (IsPrefix(".bss") || IsPrefix(".data") || IsPrefix(".rodata")) - return false; - if (IsPrefix(".lbss") || IsPrefix(".ldata") || IsPrefix(".lrodata")) - return true; - } - // For x86-64, we treat an explicit GlobalVariable small code model to mean // that the global should be placed in a small section, and ditto for large. - // Well-known section names above take precedence for correctness. if (auto CM = GV->getCodeModel()) { if (*CM == CodeModel::Small) return false; @@ -83,6 +67,20 @@ bool TargetMachine::isLargeGlobalValue(const GlobalValue *GVal) const { return true; } + // Treat all globals in explicit sections as small, except for the standard + // large sections of .lbss, .ldata, .lrodata. This reduces the risk of linking + // together small and large sections, resulting in small references to large + // data sections. The code model attribute overrides this above. + if (GV->hasSection()) { + StringRef Name = GV->getSection(); + auto IsPrefix = [&](StringRef Prefix) { + StringRef S = Name; + return S.consume_front(Prefix) && (S.empty() || S[0] == '.'); + }; + return IsPrefix(".lbss") || IsPrefix(".ldata") || IsPrefix(".lrodata"); + } + + // Respect large data threshold for medium and large code models. if (getCodeModel() == CodeModel::Medium || getCodeModel() == CodeModel::Large) { if (!GV->getValueType()->isSized()) @@ -215,6 +213,7 @@ bool TargetMachine::shouldAssumeDSOLocal(const Module &M, } bool TargetMachine::useEmulatedTLS() const { return Options.EmulatedTLS; } +bool TargetMachine::useTLSDESC() const { return Options.EnableTLSDESC; } TLSModel::Model TargetMachine::getTLSModel(const GlobalValue *GV) const { bool IsPIE = GV->getParent()->getPIELevel() != PIELevel::Default; diff --git a/llvm/lib/Target/WebAssembly/AsmParser/WebAssemblyAsmParser.cpp b/llvm/lib/Target/WebAssembly/AsmParser/WebAssemblyAsmParser.cpp index 1b92997f03f..3cc4d50271e 100644 --- a/llvm/lib/Target/WebAssembly/AsmParser/WebAssemblyAsmParser.cpp +++ b/llvm/lib/Target/WebAssembly/AsmParser/WebAssemblyAsmParser.cpp @@ -851,7 +851,7 @@ public: // symbol auto WasmSym = cast(Ctx.getOrCreateSymbol(SymName)); WasmSym->setType(wasm::WASM_SYMBOL_TYPE_TABLE); - wasm::WasmTableType Type = {uint8_t(*ElemType), Limits}; + wasm::WasmTableType Type = {*ElemType, Limits}; WasmSym->setTableType(Type); TOut.emitTableType(WasmSym); return expect(AsmToken::EndOfStatement, "EOL"); diff --git a/llvm/lib/Target/WebAssembly/WebAssemblyDebugValueManager.cpp b/llvm/lib/Target/WebAssembly/WebAssemblyDebugValueManager.cpp index fd510f85a8a..a2a054127d5 100644 --- a/llvm/lib/Target/WebAssembly/WebAssemblyDebugValueManager.cpp +++ b/llvm/lib/Target/WebAssembly/WebAssemblyDebugValueManager.cpp @@ -17,11 +17,15 @@ #include "WebAssemblyMachineFunctionInfo.h" #include "llvm/CodeGen/MachineInstr.h" #include "llvm/IR/DebugInfoMetadata.h" +#include "llvm/IR/Function.h" using namespace llvm; WebAssemblyDebugValueManager::WebAssemblyDebugValueManager(MachineInstr *Def) : Def(Def) { + if (!Def->getMF()->getFunction().getSubprogram()) + return; + // This code differs from MachineInstr::collectDebugValues in that it scans // the whole BB, not just contiguous DBG_VALUEs, until another definition to // the same register is encountered. diff --git a/llvm/lib/Target/WebAssembly/WebAssemblyUtilities.cpp b/llvm/lib/Target/WebAssembly/WebAssemblyUtilities.cpp index 189111cef7d..ac7cf5b37fc 100644 --- a/llvm/lib/Target/WebAssembly/WebAssemblyUtilities.cpp +++ b/llvm/lib/Target/WebAssembly/WebAssemblyUtilities.cpp @@ -134,7 +134,7 @@ MCSymbolWasm *WebAssembly::getOrCreateFuncrefCallTableSymbol( Sym->setWeak(true); wasm::WasmLimits Limits = {0, 1, 1}; - wasm::WasmTableType TableType = {wasm::WASM_TYPE_FUNCREF, Limits}; + wasm::WasmTableType TableType = {wasm::ValType::FUNCREF, Limits}; Sym->setType(wasm::WASM_SYMBOL_TYPE_TABLE); Sym->setTableType(TableType); } diff --git a/llvm/lib/Target/X86/MCTargetDesc/X86BaseInfo.h b/llvm/lib/Target/X86/MCTargetDesc/X86BaseInfo.h index e006dd87736..4442b80861b 100644 --- a/llvm/lib/Target/X86/MCTargetDesc/X86BaseInfo.h +++ b/llvm/lib/Target/X86/MCTargetDesc/X86BaseInfo.h @@ -818,6 +818,8 @@ enum : uint64_t { /// Encoding EncodingShift = SSEDomainShift + 2, EncodingMask = 0x3 << EncodingShift, + /// LEGACY - encoding using REX/REX2 or w/o opcode prefix. + LEGACY = 0 << EncodingShift, /// VEX - encoding using 0xC4/0xC5 VEX = 1 << EncodingShift, /// XOP - Opcode prefix used by XOP instructions. @@ -1258,6 +1260,10 @@ inline bool canUseApxExtendedReg(const MCInstrDesc &Desc) { if (Encoding == X86II::EVEX) return true; + unsigned Opcode = Desc.Opcode; + // MOV32r0 is always expanded to XOR32rr + if (Opcode == X86::MOV32r0) + return true; // To be conservative, egpr is not used for all pseudo instructions // because we are not sure what instruction it will become. // FIXME: Could we improve it in X86ExpandPseudo? @@ -1266,7 +1272,6 @@ inline bool canUseApxExtendedReg(const MCInstrDesc &Desc) { // MAP OB/TB in legacy encoding space can always use egpr except // XSAVE*/XRSTOR*. - unsigned Opcode = Desc.Opcode; switch (Opcode) { default: break; diff --git a/llvm/lib/Target/X86/MCTargetDesc/X86InstComments.cpp b/llvm/lib/Target/X86/MCTargetDesc/X86InstComments.cpp index 20b37d5a999..619328af127 100644 --- a/llvm/lib/Target/X86/MCTargetDesc/X86InstComments.cpp +++ b/llvm/lib/Target/X86/MCTargetDesc/X86InstComments.cpp @@ -1212,15 +1212,7 @@ bool llvm::EmitAnyX86InstComments(const MCInst *MI, raw_ostream &OS, case X86::VMOVSDZrr: Src2Name = getRegName(MI->getOperand(2).getReg()); Src1Name = getRegName(MI->getOperand(1).getReg()); - [[fallthrough]]; - - case X86::MOVSDrm_alt: - case X86::MOVSDrm: - case X86::VMOVSDrm_alt: - case X86::VMOVSDrm: - case X86::VMOVSDZrm: - case X86::VMOVSDZrm_alt: - DecodeScalarMoveMask(2, nullptr == Src2Name, ShuffleMask); + DecodeScalarMoveMask(2, false, ShuffleMask); DestName = getRegName(MI->getOperand(0).getReg()); break; @@ -1229,15 +1221,7 @@ bool llvm::EmitAnyX86InstComments(const MCInst *MI, raw_ostream &OS, case X86::VMOVSSZrr: Src2Name = getRegName(MI->getOperand(2).getReg()); Src1Name = getRegName(MI->getOperand(1).getReg()); - [[fallthrough]]; - - case X86::MOVSSrm: - case X86::MOVSSrm_alt: - case X86::VMOVSSrm: - case X86::VMOVSSrm_alt: - case X86::VMOVSSZrm: - case X86::VMOVSSZrm_alt: - DecodeScalarMoveMask(4, nullptr == Src2Name, ShuffleMask); + DecodeScalarMoveMask(4, false, ShuffleMask); DestName = getRegName(MI->getOperand(0).getReg()); break; @@ -1248,22 +1232,10 @@ bool llvm::EmitAnyX86InstComments(const MCInst *MI, raw_ostream &OS, case X86::VMOVZPQILo2PQIrr: case X86::VMOVZPQILo2PQIZrr: Src1Name = getRegName(MI->getOperand(1).getReg()); - [[fallthrough]]; - - case X86::MOVQI2PQIrm: - case X86::VMOVQI2PQIrm: - case X86::VMOVQI2PQIZrm: DecodeZeroMoveLowMask(2, ShuffleMask); DestName = getRegName(MI->getOperand(0).getReg()); break; - case X86::MOVDI2PDIrm: - case X86::VMOVDI2PDIrm: - case X86::VMOVDI2PDIZrm: - DecodeZeroMoveLowMask(4, ShuffleMask); - DestName = getRegName(MI->getOperand(0).getReg()); - break; - case X86::EXTRQI: if (MI->getOperand(2).isImm() && MI->getOperand(3).isImm()) diff --git a/llvm/lib/Target/X86/MCTargetDesc/X86InstPrinterCommon.cpp b/llvm/lib/Target/X86/MCTargetDesc/X86InstPrinterCommon.cpp index 1947313a9df..e519c00a211 100644 --- a/llvm/lib/Target/X86/MCTargetDesc/X86InstPrinterCommon.cpp +++ b/llvm/lib/Target/X86/MCTargetDesc/X86InstPrinterCommon.cpp @@ -30,7 +30,9 @@ void X86InstPrinterCommon::printCondCode(const MCInst *MI, unsigned Op, raw_ostream &O) { int64_t Imm = MI->getOperand(Op).getImm(); bool Flavor = MI->getOpcode() == X86::CMPCCXADDmr32 || - MI->getOpcode() == X86::CMPCCXADDmr64; + MI->getOpcode() == X86::CMPCCXADDmr64 || + MI->getOpcode() == X86::CMPCCXADDmr32_EVEX || + MI->getOpcode() == X86::CMPCCXADDmr64_EVEX; switch (Imm) { default: llvm_unreachable("Invalid condcode argument!"); case 0: O << "o"; break; diff --git a/llvm/lib/Target/X86/X86AsmPrinter.cpp b/llvm/lib/Target/X86/X86AsmPrinter.cpp index 15cfd247f12..9f0fd4d0938 100644 --- a/llvm/lib/Target/X86/X86AsmPrinter.cpp +++ b/llvm/lib/Target/X86/X86AsmPrinter.cpp @@ -774,6 +774,14 @@ bool X86AsmPrinter::PrintAsmOperand(const MachineInstr *MI, unsigned OpNo, PrintOperand(MI, OpNo, O); return false; + case 'p': { + const MachineOperand &MO = MI->getOperand(OpNo); + if (MO.getType() != MachineOperand::MO_GlobalAddress) + return true; + PrintSymbolOperand(MO, O); + return false; + } + case 'P': // This is the operand of a call, treat specially. PrintPCRelImm(MI, OpNo, O); return false; diff --git a/llvm/lib/Target/X86/X86CodeGenPassBuilder.cpp b/llvm/lib/Target/X86/X86CodeGenPassBuilder.cpp new file mode 100644 index 00000000000..616f777833e --- /dev/null +++ b/llvm/lib/Target/X86/X86CodeGenPassBuilder.cpp @@ -0,0 +1,56 @@ +//===-- X86CodeGenPassBuilder.cpp ---------------------------------*- C++ -*-=// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// +/// \file +/// This file contains X86 CodeGen pipeline builder. +/// TODO: Port CodeGen passes to new pass manager. +//===----------------------------------------------------------------------===// + +#include "X86TargetMachine.h" + +#include "llvm/CodeGen/CodeGenPassBuilder.h" +#include "llvm/MC/MCStreamer.h" + +using namespace llvm; + +namespace { + +class X86CodeGenPassBuilder : public CodeGenPassBuilder { +public: + explicit X86CodeGenPassBuilder(LLVMTargetMachine &TM, + CGPassBuilderOption Opts, + PassInstrumentationCallbacks *PIC) + : CodeGenPassBuilder(TM, Opts, PIC) {} + void addPreISel(AddIRPass &addPass) const; + void addAsmPrinter(AddMachinePass &, CreateMCStreamer) const; + Error addInstSelector(AddMachinePass &) const; +}; + +void X86CodeGenPassBuilder::addPreISel(AddIRPass &addPass) const { + // TODO: Add passes pre instruction selection. +} + +void X86CodeGenPassBuilder::addAsmPrinter(AddMachinePass &addPass, + CreateMCStreamer) const { + // TODO: Add AsmPrinter. +} + +Error X86CodeGenPassBuilder::addInstSelector(AddMachinePass &) const { + // TODO: Add instruction selector. + return Error::success(); +} + +} // namespace + +Error X86TargetMachine::buildCodeGenPipeline( + ModulePassManager &MPM, MachineFunctionPassManager &MFPM, + MachineFunctionAnalysisManager &, raw_pwrite_stream &Out, + raw_pwrite_stream *DwoOut, CodeGenFileType FileType, + CGPassBuilderOption Opt, PassInstrumentationCallbacks *PIC) { + auto CGPB = X86CodeGenPassBuilder(*this, Opt, PIC); + return CGPB.buildPipeline(MPM, MFPM, Out, DwoOut, FileType); +} diff --git a/llvm/lib/Target/X86/X86CompressEVEX.cpp b/llvm/lib/Target/X86/X86CompressEVEX.cpp index b95baddd9de..a9704e30478 100644 --- a/llvm/lib/Target/X86/X86CompressEVEX.cpp +++ b/llvm/lib/Target/X86/X86CompressEVEX.cpp @@ -121,44 +121,6 @@ static bool usesExtendedRegister(const MachineInstr &MI) { return false; } -static bool checkVEXInstPredicate(unsigned OldOpc, const X86Subtarget &ST) { - switch (OldOpc) { - default: - return true; - case X86::VCVTNEPS2BF16Z128rm: - case X86::VCVTNEPS2BF16Z128rr: - case X86::VCVTNEPS2BF16Z256rm: - case X86::VCVTNEPS2BF16Z256rr: - return ST.hasAVXNECONVERT(); - case X86::VPDPBUSDSZ128m: - case X86::VPDPBUSDSZ128r: - case X86::VPDPBUSDSZ256m: - case X86::VPDPBUSDSZ256r: - case X86::VPDPBUSDZ128m: - case X86::VPDPBUSDZ128r: - case X86::VPDPBUSDZ256m: - case X86::VPDPBUSDZ256r: - case X86::VPDPWSSDSZ128m: - case X86::VPDPWSSDSZ128r: - case X86::VPDPWSSDSZ256m: - case X86::VPDPWSSDSZ256r: - case X86::VPDPWSSDZ128m: - case X86::VPDPWSSDZ128r: - case X86::VPDPWSSDZ256m: - case X86::VPDPWSSDZ256r: - return ST.hasAVXVNNI(); - case X86::VPMADD52HUQZ128m: - case X86::VPMADD52HUQZ128r: - case X86::VPMADD52HUQZ256m: - case X86::VPMADD52HUQZ256r: - case X86::VPMADD52LUQZ128m: - case X86::VPMADD52LUQZ128r: - case X86::VPMADD52LUQZ256m: - case X86::VPMADD52LUQZ256r: - return ST.hasAVXIFMA(); - } -} - // Do any custom cleanup needed to finalize the conversion. static bool performCustomAdjustments(MachineInstr &MI, unsigned NewOpc) { (void)NewOpc; @@ -220,6 +182,28 @@ static bool performCustomAdjustments(MachineInstr &MI, unsigned NewOpc) { return true; } +static bool isRedundantNewDataDest(MachineInstr &MI, const X86Subtarget &ST) { + // $rbx = ADD64rr_ND $rbx, $rax / $rbx = ADD64rr_ND $rax, $rbx + // -> + // $rbx = ADD64rr $rbx, $rax + const MCInstrDesc &Desc = MI.getDesc(); + Register Reg0 = MI.getOperand(0).getReg(); + const MachineOperand &Op1 = MI.getOperand(1); + if (!Op1.isReg()) + return false; + Register Reg1 = Op1.getReg(); + if (Reg1 == Reg0) + return true; + + // Op1 and Op2 may be commutable for ND instructions. + if (!Desc.isCommutable() || Desc.getNumOperands() < 3 || + !MI.getOperand(2).isReg() || MI.getOperand(2).getReg() != Reg0) + return false; + // Opcode may change after commute, e.g. SHRD -> SHLD + ST.getInstrInfo()->commuteInstruction(MI, false, 1, 2); + return true; +} + static bool CompressEVEXImpl(MachineInstr &MI, const X86Subtarget &ST) { uint64_t TSFlags = MI.getDesc().TSFlags; @@ -241,26 +225,48 @@ static bool CompressEVEXImpl(MachineInstr &MI, const X86Subtarget &ST) { // // For AVX512 cases, EVEX prefix is needed in order to carry this information // thus preventing the transformation to VEX encoding. + bool IsND = X86II::hasNewDataDest(TSFlags); if (TSFlags & X86II::EVEX_B) - return false; + if (!IsND || !isRedundantNewDataDest(MI, ST)) + return false; ArrayRef Table = ArrayRef(X86CompressEVEXTable); unsigned Opc = MI.getOpcode(); const auto *I = llvm::lower_bound(Table, Opc); - if (I == Table.end() || I->OldOpc != Opc) + if (I == Table.end() || I->OldOpc != Opc) { + assert(!IsND && "Missing entry for ND instruction"); return false; + } - if (usesExtendedRegister(MI) || !checkVEXInstPredicate(Opc, ST) || - !performCustomAdjustments(MI, I->NewOpc)) - return false; + if (!IsND) { + if (usesExtendedRegister(MI) || !checkPredicate(I->NewOpc, &ST) || + !performCustomAdjustments(MI, I->NewOpc)) + return false; + } const MCInstrDesc &NewDesc = ST.getInstrInfo()->get(I->NewOpc); MI.setDesc(NewDesc); - uint64_t Encoding = NewDesc.TSFlags & X86II::EncodingMask; - auto AsmComment = - (Encoding == X86II::VEX) ? X86::AC_EVEX_2_VEX : X86::AC_EVEX_2_LEGACY; + unsigned AsmComment; + switch (NewDesc.TSFlags & X86II::EncodingMask) { + case X86II::LEGACY: + AsmComment = X86::AC_EVEX_2_LEGACY; + break; + case X86II::VEX: + AsmComment = X86::AC_EVEX_2_VEX; + break; + case X86II::EVEX: + AsmComment = X86::AC_EVEX_2_EVEX; + assert(IsND && (NewDesc.TSFlags & X86II::EVEX_NF) && + "Unknown EVEX2EVEX compression"); + break; + default: + llvm_unreachable("Unknown EVEX compression"); + } MI.setAsmPrinterFlag(AsmComment); + if (IsND) + MI.tieOperands(0, 1); + return true; } diff --git a/llvm/lib/Target/X86/X86ExpandPseudo.cpp b/llvm/lib/Target/X86/X86ExpandPseudo.cpp index ecc7208e760..95c4b02842a 100644 --- a/llvm/lib/Target/X86/X86ExpandPseudo.cpp +++ b/llvm/lib/Target/X86/X86ExpandPseudo.cpp @@ -556,16 +556,18 @@ bool X86ExpandPseudo::ExpandMI(MachineBasicBlock &MBB, case TargetOpcode::ICALL_BRANCH_FUNNEL: ExpandICallBranchFunnel(&MBB, MBBI); return true; +#define GET_EGPR_IF_ENABLED(OPC) (STI->hasEGPR() ? OPC##_EVEX : OPC) case X86::PLDTILECFGV: { - MI.setDesc(TII->get(X86::LDTILECFG)); + MI.setDesc(TII->get(GET_EGPR_IF_ENABLED(X86::LDTILECFG))); return true; } case X86::PTILELOADDV: case X86::PTILELOADDT1V: { for (unsigned i = 2; i > 0; --i) MI.removeOperand(i); - unsigned Opc = - Opcode == X86::PTILELOADDV ? X86::TILELOADD : X86::TILELOADDT1; + unsigned Opc = Opcode == X86::PTILELOADDV + ? GET_EGPR_IF_ENABLED(X86::TILELOADD) + : GET_EGPR_IF_ENABLED(X86::TILELOADDT1); MI.setDesc(TII->get(Opc)); return true; } @@ -599,9 +601,10 @@ bool X86ExpandPseudo::ExpandMI(MachineBasicBlock &MBB, case X86::PTILESTOREDV: { for (int i = 1; i >= 0; --i) MI.removeOperand(i); - MI.setDesc(TII->get(X86::TILESTORED)); + MI.setDesc(TII->get(GET_EGPR_IF_ENABLED(X86::TILESTORED))); return true; } +#undef GET_EGPR_IF_ENABLED case X86::PTILEZEROV: { for (int i = 2; i > 0; --i) // Remove row, col MI.removeOperand(i); diff --git a/llvm/lib/Target/X86/X86FixupVectorConstants.cpp b/llvm/lib/Target/X86/X86FixupVectorConstants.cpp index 483becebbe1..9da8d7338ea 100644 --- a/llvm/lib/Target/X86/X86FixupVectorConstants.cpp +++ b/llvm/lib/Target/X86/X86FixupVectorConstants.cpp @@ -63,23 +63,6 @@ FunctionPass *llvm::createX86FixupVectorConstants() { return new X86FixupVectorConstantsPass(); } -static const Constant *getConstantFromPool(const MachineInstr &MI, - const MachineOperand &Op) { - if (!Op.isCPI() || Op.getOffset() != 0) - return nullptr; - - ArrayRef Constants = - MI.getParent()->getParent()->getConstantPool()->getConstants(); - const MachineConstantPoolEntry &ConstantEntry = Constants[Op.getIndex()]; - - // Bail if this is a machine constant pool entry, we won't be able to dig out - // anything useful. - if (ConstantEntry.isMachineConstantPoolEntry()) - return nullptr; - - return ConstantEntry.Val.ConstVal; -} - // Attempt to extract the full width of bits data from the constant. static std::optional extractConstantBits(const Constant *C) { unsigned NumBits = C->getType()->getPrimitiveSizeInBits(); @@ -175,9 +158,49 @@ static std::optional getSplatableConstant(const Constant *C, return std::nullopt; } +// Split raw bits into a constant vector of elements of a specific bit width. +// NOTE: We don't always bother converting to scalars if the vector length is 1. +static Constant *rebuildConstant(LLVMContext &Ctx, Type *SclTy, + const APInt &Bits, unsigned NumSclBits) { + unsigned BitWidth = Bits.getBitWidth(); + + if (NumSclBits == 8) { + SmallVector RawBits; + for (unsigned I = 0; I != BitWidth; I += 8) + RawBits.push_back(Bits.extractBits(8, I).getZExtValue()); + return ConstantDataVector::get(Ctx, RawBits); + } + + if (NumSclBits == 16) { + SmallVector RawBits; + for (unsigned I = 0; I != BitWidth; I += 16) + RawBits.push_back(Bits.extractBits(16, I).getZExtValue()); + if (SclTy->is16bitFPTy()) + return ConstantDataVector::getFP(SclTy, RawBits); + return ConstantDataVector::get(Ctx, RawBits); + } + + if (NumSclBits == 32) { + SmallVector RawBits; + for (unsigned I = 0; I != BitWidth; I += 32) + RawBits.push_back(Bits.extractBits(32, I).getZExtValue()); + if (SclTy->isFloatTy()) + return ConstantDataVector::getFP(SclTy, RawBits); + return ConstantDataVector::get(Ctx, RawBits); + } + + assert(NumSclBits == 64 && "Unhandled vector element width"); + + SmallVector RawBits; + for (unsigned I = 0; I != BitWidth; I += 64) + RawBits.push_back(Bits.extractBits(64, I).getZExtValue()); + if (SclTy->isDoubleTy()) + return ConstantDataVector::getFP(SclTy, RawBits); + return ConstantDataVector::get(Ctx, RawBits); +} + // Attempt to rebuild a normalized splat vector constant of the requested splat // width, built up of potentially smaller scalar values. -// NOTE: We don't always bother converting to scalars if the vector length is 1. static Constant *rebuildSplatableConstant(const Constant *C, unsigned SplatBitWidth) { std::optional Splat = getSplatableConstant(C, SplatBitWidth); @@ -190,40 +213,14 @@ static Constant *rebuildSplatableConstant(const Constant *C, Type *SclTy = OriginalType->getScalarType(); unsigned NumSclBits = SclTy->getPrimitiveSizeInBits(); NumSclBits = std::min(NumSclBits, SplatBitWidth); - LLVMContext &Ctx = OriginalType->getContext(); - - if (NumSclBits == 8) { - SmallVector RawBits; - for (unsigned I = 0; I != SplatBitWidth; I += 8) - RawBits.push_back(Splat->extractBits(8, I).getZExtValue()); - return ConstantDataVector::get(Ctx, RawBits); - } - - if (NumSclBits == 16) { - SmallVector RawBits; - for (unsigned I = 0; I != SplatBitWidth; I += 16) - RawBits.push_back(Splat->extractBits(16, I).getZExtValue()); - if (SclTy->is16bitFPTy()) - return ConstantDataVector::getFP(SclTy, RawBits); - return ConstantDataVector::get(Ctx, RawBits); - } - - if (NumSclBits == 32) { - SmallVector RawBits; - for (unsigned I = 0; I != SplatBitWidth; I += 32) - RawBits.push_back(Splat->extractBits(32, I).getZExtValue()); - if (SclTy->isFloatTy()) - return ConstantDataVector::getFP(SclTy, RawBits); - return ConstantDataVector::get(Ctx, RawBits); - } // Fallback to i64 / double. - SmallVector RawBits; - for (unsigned I = 0; I != SplatBitWidth; I += 64) - RawBits.push_back(Splat->extractBits(64, I).getZExtValue()); - if (SclTy->isDoubleTy()) - return ConstantDataVector::getFP(SclTy, RawBits); - return ConstantDataVector::get(Ctx, RawBits); + NumSclBits = (NumSclBits == 8 || NumSclBits == 16 || NumSclBits == 32) + ? NumSclBits + : 64; + + // Extract per-element bits. + return rebuildConstant(OriginalType->getContext(), SclTy, *Splat, NumSclBits); } bool X86FixupVectorConstantsPass::processInstruction(MachineFunction &MF, @@ -243,8 +240,7 @@ bool X86FixupVectorConstantsPass::processInstruction(MachineFunction &MF, assert(MI.getNumOperands() >= (OperandNo + X86::AddrNumOperands) && "Unexpected number of operands!"); - MachineOperand &CstOp = MI.getOperand(OperandNo + X86::AddrDisp); - if (auto *C = getConstantFromPool(MI, CstOp)) { + if (auto *C = X86::getConstantFromPool(MI, OperandNo)) { // Attempt to detect a suitable splat from increasing splat widths. std::pair Broadcasts[] = { {8, OpBcst8}, {16, OpBcst16}, {32, OpBcst32}, @@ -258,7 +254,7 @@ bool X86FixupVectorConstantsPass::processInstruction(MachineFunction &MF, unsigned NewCPI = CP->getConstantPoolIndex(NewCst, Align(BitWidth / 8)); MI.setDesc(TII->get(OpBcst)); - CstOp.setIndex(NewCPI); + MI.getOperand(OperandNo + X86::AddrDisp).setIndex(NewCPI); return true; } } diff --git a/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp b/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp index 53ce720be2d..833f058253d 100644 --- a/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp +++ b/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp @@ -2355,8 +2355,7 @@ SDValue X86DAGToDAGISel::matchIndexRecursively(SDValue N, Src.hasOneUse()) { if (CurDAG->isBaseWithConstantOffset(Src)) { SDValue AddSrc = Src.getOperand(0); - auto *AddVal = cast(Src.getOperand(1)); - uint64_t Offset = (uint64_t)AddVal->getZExtValue(); + uint64_t Offset = Src.getConstantOperandVal(1); if (!foldOffsetIntoAddress(Offset * AM.Scale, AM)) { SDLoc DL(N); SDValue Res; @@ -3189,12 +3188,16 @@ bool X86DAGToDAGISel::isSExtAbsoluteSymbolRef(unsigned Width, SDNode *N) const { if (!GA) return false; - std::optional CR = GA->getGlobal()->getAbsoluteSymbolRange(); - if (!CR) - return Width == 32 && TM.getCodeModel() == CodeModel::Small; - - return CR->getSignedMin().sge(-1ull << Width) && - CR->getSignedMax().slt(1ull << Width); + auto *GV = GA->getGlobal(); + std::optional CR = GV->getAbsoluteSymbolRange(); + if (CR) + return CR->getSignedMin().sge(-1ull << Width) && + CR->getSignedMax().slt(1ull << Width); + // In the kernel code model, globals are in the negative 2GB of the address + // space, so globals can be a sign extended 32-bit immediate. + // In other code models, small globals are in the low 2GB of the address + // space, so sign extending them is equivalent to zero extending them. + return Width == 32 && !TM.isLargeGlobalValue(GV); } X86::CondCode X86DAGToDAGISel::getCondFromNode(SDNode *N) const { @@ -4087,14 +4090,17 @@ MachineSDNode *X86DAGToDAGISel::matchBEXTRFromAndImm(SDNode *Node) { SDValue Control; unsigned ROpc, MOpc; +#define GET_EGPR_IF_ENABLED(OPC) (Subtarget->hasEGPR() ? OPC##_EVEX : OPC) if (!PreferBEXTR) { assert(Subtarget->hasBMI2() && "We must have BMI2's BZHI then."); // If we can't make use of BEXTR then we can't fuse shift+mask stages. // Let's perform the mask first, and apply shift later. Note that we need to // widen the mask to account for the fact that we'll apply shift afterwards! Control = CurDAG->getTargetConstant(Shift + MaskSize, dl, NVT); - ROpc = NVT == MVT::i64 ? X86::BZHI64rr : X86::BZHI32rr; - MOpc = NVT == MVT::i64 ? X86::BZHI64rm : X86::BZHI32rm; + ROpc = NVT == MVT::i64 ? GET_EGPR_IF_ENABLED(X86::BZHI64rr) + : GET_EGPR_IF_ENABLED(X86::BZHI32rr); + MOpc = NVT == MVT::i64 ? GET_EGPR_IF_ENABLED(X86::BZHI64rm) + : GET_EGPR_IF_ENABLED(X86::BZHI32rm); unsigned NewOpc = NVT == MVT::i64 ? X86::MOV32ri64 : X86::MOV32ri; Control = SDValue(CurDAG->getMachineNode(NewOpc, dl, NVT, Control), 0); } else { @@ -4109,8 +4115,10 @@ MachineSDNode *X86DAGToDAGISel::matchBEXTRFromAndImm(SDNode *Node) { } else { assert(Subtarget->hasBMI() && "We must have BMI1's BEXTR then."); // BMI requires the immediate to placed in a register. - ROpc = NVT == MVT::i64 ? X86::BEXTR64rr : X86::BEXTR32rr; - MOpc = NVT == MVT::i64 ? X86::BEXTR64rm : X86::BEXTR32rm; + ROpc = NVT == MVT::i64 ? GET_EGPR_IF_ENABLED(X86::BEXTR64rr) + : GET_EGPR_IF_ENABLED(X86::BEXTR32rr); + MOpc = NVT == MVT::i64 ? GET_EGPR_IF_ENABLED(X86::BEXTR64rm) + : GET_EGPR_IF_ENABLED(X86::BEXTR32rm); unsigned NewOpc = NVT == MVT::i64 ? X86::MOV32ri64 : X86::MOV32ri; Control = SDValue(CurDAG->getMachineNode(NewOpc, dl, NVT, Control), 0); } @@ -5483,25 +5491,30 @@ void X86DAGToDAGISel::Select(SDNode *Node) { switch (NVT.SimpleTy) { default: llvm_unreachable("Unsupported VT!"); case MVT::i32: - Opc = UseMULXHi ? X86::MULX32Hrr : - UseMULX ? X86::MULX32rr : - IsSigned ? X86::IMUL32r : X86::MUL32r; - MOpc = UseMULXHi ? X86::MULX32Hrm : - UseMULX ? X86::MULX32rm : - IsSigned ? X86::IMUL32m : X86::MUL32m; + Opc = UseMULXHi ? X86::MULX32Hrr + : UseMULX ? GET_EGPR_IF_ENABLED(X86::MULX32rr) + : IsSigned ? X86::IMUL32r + : X86::MUL32r; + MOpc = UseMULXHi ? X86::MULX32Hrm + : UseMULX ? GET_EGPR_IF_ENABLED(X86::MULX32rm) + : IsSigned ? X86::IMUL32m + : X86::MUL32m; LoReg = UseMULX ? X86::EDX : X86::EAX; HiReg = X86::EDX; break; case MVT::i64: - Opc = UseMULXHi ? X86::MULX64Hrr : - UseMULX ? X86::MULX64rr : - IsSigned ? X86::IMUL64r : X86::MUL64r; - MOpc = UseMULXHi ? X86::MULX64Hrm : - UseMULX ? X86::MULX64rm : - IsSigned ? X86::IMUL64m : X86::MUL64m; + Opc = UseMULXHi ? X86::MULX64Hrr + : UseMULX ? GET_EGPR_IF_ENABLED(X86::MULX64rr) + : IsSigned ? X86::IMUL64r + : X86::MUL64r; + MOpc = UseMULXHi ? X86::MULX64Hrm + : UseMULX ? GET_EGPR_IF_ENABLED(X86::MULX64rm) + : IsSigned ? X86::IMUL64m + : X86::MUL64m; LoReg = UseMULX ? X86::RDX : X86::RAX; HiReg = X86::RDX; break; +#undef GET_EGPR_IF_ENABLED } SDValue Tmp0, Tmp1, Tmp2, Tmp3, Tmp4; diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp index 700ab797b2f..e158312caff 100644 --- a/llvm/lib/Target/X86/X86ISelLowering.cpp +++ b/llvm/lib/Target/X86/X86ISelLowering.cpp @@ -21523,9 +21523,19 @@ static SDValue LowerFP_TO_FP16(SDValue Op, SelectionDAG &DAG) { SDValue X86TargetLowering::LowerFP_TO_BF16(SDValue Op, SelectionDAG &DAG) const { SDLoc DL(Op); + + MVT SVT = Op.getOperand(0).getSimpleValueType(); + if (SVT == MVT::f32 && (Subtarget.hasBF16() || Subtarget.hasAVXNECONVERT())) { + SDValue Res; + Res = DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, MVT::v4f32, Op.getOperand(0)); + Res = DAG.getNode(X86ISD::CVTNEPS2BF16, DL, MVT::v8bf16, Res); + Res = DAG.getBitcast(MVT::v8i16, Res); + return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::i16, Res, + DAG.getIntPtrConstant(0, DL)); + } + MakeLibCallOptions CallOptions; - RTLIB::Libcall LC = - RTLIB::getFPROUND(Op.getOperand(0).getValueType(), MVT::bf16); + RTLIB::Libcall LC = RTLIB::getFPROUND(SVT, MVT::bf16); SDValue Res = makeLibCall(DAG, LC, MVT::f16, Op.getOperand(0), CallOptions, DL).first; return DAG.getBitcast(MVT::i16, Res); @@ -36364,14 +36374,22 @@ X86TargetLowering::EmitInstrWithCustomInserter(MachineInstr &MI, unsigned Opc; switch (MI.getOpcode()) { default: llvm_unreachable("illegal opcode!"); - case X86::PTILELOADD: Opc = X86::TILELOADD; break; - case X86::PTILELOADDT1: Opc = X86::TILELOADDT1; break; - case X86::PTILESTORED: Opc = X86::TILESTORED; break; +#define GET_EGPR_IF_ENABLED(OPC) (Subtarget.hasEGPR() ? OPC##_EVEX : OPC) + case X86::PTILELOADD: + Opc = GET_EGPR_IF_ENABLED(X86::TILELOADD); + break; + case X86::PTILELOADDT1: + Opc = GET_EGPR_IF_ENABLED(X86::TILELOADDT1); + break; + case X86::PTILESTORED: + Opc = GET_EGPR_IF_ENABLED(X86::TILESTORED); + break; +#undef GET_EGPR_IF_ENABLED } MachineInstrBuilder MIB = BuildMI(*BB, MI, MIMD, TII->get(Opc)); unsigned CurOp = 0; - if (Opc != X86::TILESTORED) + if (Opc != X86::TILESTORED && Opc != X86::TILESTORED_EVEX) MIB.addReg(TMMImmToTMMReg(MI.getOperand(CurOp++).getImm()), RegState::Define); @@ -36381,7 +36399,7 @@ X86TargetLowering::EmitInstrWithCustomInserter(MachineInstr &MI, MIB.add(MI.getOperand(CurOp++)); // displacement MIB.add(MI.getOperand(CurOp++)); // segment - if (Opc == X86::TILESTORED) + if (Opc == X86::TILESTORED || Opc == X86::TILESTORED_EVEX) MIB.addReg(TMMImmToTMMReg(MI.getOperand(CurOp++).getImm()), RegState::Undef); @@ -39620,6 +39638,7 @@ static SDValue canonicalizeShuffleWithOp(SDValue N, SelectionDAG &DAG, ISD::isBuildVectorAllZeros(Op.getNode()) || ISD::isBuildVectorOfConstantSDNodes(Op.getNode()) || ISD::isBuildVectorOfConstantFPSDNodes(Op.getNode()) || + getTargetConstantFromNode(dyn_cast(Op)) || (Op.getOpcode() == ISD::INSERT_SUBVECTOR && Op->hasOneUse()) || (isTargetShuffle(Op.getOpcode()) && Op->hasOneUse()) || (FoldLoad && isShuffleFoldableLoad(Op)) || @@ -56676,6 +56695,10 @@ X86TargetLowering::getConstraintType(StringRef Constraint) const { switch (Constraint[0]) { default: break; + case 'W': + if (Constraint[1] != 's') + break; + return C_Other; case 'Y': switch (Constraint[1]) { default: @@ -56880,11 +56903,6 @@ void X86TargetLowering::LowerAsmOperandForConstraint(SDValue Op, std::vector &Ops, SelectionDAG &DAG) const { SDValue Result; - - // Only support length 1 constraints for now. - if (Constraint.size() > 1) - return; - char ConstraintLetter = Constraint[0]; switch (ConstraintLetter) { default: break; @@ -56966,6 +56984,26 @@ void X86TargetLowering::LowerAsmOperandForConstraint(SDValue Op, } return; } + case 'W': { + assert(Constraint[1] == 's'); + // Op is a BlockAddressSDNode or a GlobalAddressSDNode with an optional + // offset. + if (const auto *BA = dyn_cast(Op)) { + Ops.push_back(DAG.getTargetBlockAddress(BA->getBlockAddress(), + BA->getValueType(0))); + } else { + int64_t Offset = 0; + if (Op->getOpcode() == ISD::ADD && + isa(Op->getOperand(1))) { + Offset = cast(Op->getOperand(1))->getSExtValue(); + Op = Op->getOperand(0); + } + if (const auto *GA = dyn_cast(Op)) + Ops.push_back(DAG.getTargetGlobalAddress(GA->getGlobal(), SDLoc(Op), + GA->getValueType(0), Offset)); + } + return; + } case 'Z': { // 32-bit unsigned value if (auto *C = dyn_cast(Op)) { @@ -57075,17 +57113,17 @@ X86TargetLowering::getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI, // in the normal allocation? case 'k': if (Subtarget.hasAVX512()) { - if (VT == MVT::i1) + if (VT == MVT::v1i1 || VT == MVT::i1) return std::make_pair(0U, &X86::VK1RegClass); - if (VT == MVT::i8) + if (VT == MVT::v8i1 || VT == MVT::i8) return std::make_pair(0U, &X86::VK8RegClass); - if (VT == MVT::i16) + if (VT == MVT::v16i1 || VT == MVT::i16) return std::make_pair(0U, &X86::VK16RegClass); } if (Subtarget.hasBWI()) { - if (VT == MVT::i32) + if (VT == MVT::v32i1 || VT == MVT::i32) return std::make_pair(0U, &X86::VK32RegClass); - if (VT == MVT::i64) + if (VT == MVT::v64i1 || VT == MVT::i64) return std::make_pair(0U, &X86::VK64RegClass); } break; @@ -57333,17 +57371,17 @@ X86TargetLowering::getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI, case 'k': // This register class doesn't allocate k0 for masked vector operation. if (Subtarget.hasAVX512()) { - if (VT == MVT::i1) + if (VT == MVT::v1i1 || VT == MVT::i1) return std::make_pair(0U, &X86::VK1WMRegClass); - if (VT == MVT::i8) + if (VT == MVT::v8i1 || VT == MVT::i8) return std::make_pair(0U, &X86::VK8WMRegClass); - if (VT == MVT::i16) + if (VT == MVT::v16i1 || VT == MVT::i16) return std::make_pair(0U, &X86::VK16WMRegClass); } if (Subtarget.hasBWI()) { - if (VT == MVT::i32) + if (VT == MVT::v32i1 || VT == MVT::i32) return std::make_pair(0U, &X86::VK32WMRegClass); - if (VT == MVT::i64) + if (VT == MVT::v64i1 || VT == MVT::i64) return std::make_pair(0U, &X86::VK64WMRegClass); } break; @@ -57496,15 +57534,15 @@ X86TargetLowering::getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI, Res.second = nullptr; } } else if (isVKClass(*Class)) { - if (VT == MVT::i1) + if (VT == MVT::v1i1 || VT == MVT::i1) Res.second = &X86::VK1RegClass; - else if (VT == MVT::i8) + else if (VT == MVT::v8i1 || VT == MVT::i8) Res.second = &X86::VK8RegClass; - else if (VT == MVT::i16) + else if (VT == MVT::v16i1 || VT == MVT::i16) Res.second = &X86::VK16RegClass; - else if (VT == MVT::i32) + else if (VT == MVT::v32i1 || VT == MVT::i32) Res.second = &X86::VK32RegClass; - else if (VT == MVT::i64) + else if (VT == MVT::v64i1 || VT == MVT::i64) Res.second = &X86::VK64RegClass; else { // Type mismatch and not a clobber: Return an error; diff --git a/llvm/lib/Target/X86/X86InstrArithmetic.td b/llvm/lib/Target/X86/X86InstrArithmetic.td index 76b0fe5f5ca..560a4097a9c 100644 --- a/llvm/lib/Target/X86/X86InstrArithmetic.td +++ b/llvm/lib/Target/X86/X86InstrArithmetic.td @@ -1338,17 +1338,23 @@ defm ANDN32 : AndN, EVEX, Requires<[HasBMI, HasEGPR, In64BitMode] defm ANDN64 : AndN, EVEX, REX_W, Requires<[HasBMI, HasEGPR, In64BitMode]>; } -let Predicates = [HasBMI], AddedComplexity = -6 in { +multiclass Andn_Pats { def : Pat<(and (not GR32:$src1), GR32:$src2), - (ANDN32rr GR32:$src1, GR32:$src2)>; + (!cast(ANDN32rr#suffix) GR32:$src1, GR32:$src2)>; def : Pat<(and (not GR64:$src1), GR64:$src2), - (ANDN64rr GR64:$src1, GR64:$src2)>; + (!cast(ANDN64rr#suffix) GR64:$src1, GR64:$src2)>; def : Pat<(and (not GR32:$src1), (loadi32 addr:$src2)), - (ANDN32rm GR32:$src1, addr:$src2)>; + (!cast(ANDN32rm#suffix) GR32:$src1, addr:$src2)>; def : Pat<(and (not GR64:$src1), (loadi64 addr:$src2)), - (ANDN64rm GR64:$src1, addr:$src2)>; + (!cast(ANDN64rm#suffix) GR64:$src1, addr:$src2)>; } +let Predicates = [HasBMI, NoEGPR], AddedComplexity = -6 in + defm : Andn_Pats<"">; + +let Predicates = [HasBMI, HasEGPR], AddedComplexity = -6 in + defm : Andn_Pats<"_EVEX">; + //===----------------------------------------------------------------------===// // MULX Instruction // diff --git a/llvm/lib/Target/X86/X86InstrCompiler.td b/llvm/lib/Target/X86/X86InstrCompiler.td index 422391a6e02..9f1712274bc 100644 --- a/llvm/lib/Target/X86/X86InstrCompiler.td +++ b/llvm/lib/Target/X86/X86InstrCompiler.td @@ -1787,31 +1787,54 @@ let Predicates = [HasNDD] in { } // Shift amount is implicitly masked. -multiclass MaskedShiftAmountPats { +multiclass MaskedShiftAmountPats { // (shift x (and y, 31)) ==> (shift x, y) - def : Pat<(frag GR8:$src1, (shiftMask32 CL)), - (!cast(name # "8rCL") GR8:$src1)>; - def : Pat<(frag GR16:$src1, (shiftMask32 CL)), - (!cast(name # "16rCL") GR16:$src1)>; - def : Pat<(frag GR32:$src1, (shiftMask32 CL)), - (!cast(name # "32rCL") GR32:$src1)>; - def : Pat<(store (frag (loadi8 addr:$dst), (shiftMask32 CL)), addr:$dst), - (!cast(name # "8mCL") addr:$dst)>; - def : Pat<(store (frag (loadi16 addr:$dst), (shiftMask32 CL)), addr:$dst), - (!cast(name # "16mCL") addr:$dst)>; - def : Pat<(store (frag (loadi32 addr:$dst), (shiftMask32 CL)), addr:$dst), - (!cast(name # "32mCL") addr:$dst)>; - // (shift x (and y, 63)) ==> (shift x, y) - def : Pat<(frag GR64:$src1, (shiftMask64 CL)), - (!cast(name # "64rCL") GR64:$src1)>; + let Predicates = [NoNDD] in { + def : Pat<(frag GR8:$src1, (shiftMask32 CL)), + (!cast(NAME # "8rCL") GR8:$src1)>; + def : Pat<(frag GR16:$src1, (shiftMask32 CL)), + (!cast(NAME # "16rCL") GR16:$src1)>; + def : Pat<(frag GR32:$src1, (shiftMask32 CL)), + (!cast(NAME # "32rCL") GR32:$src1)>; + def : Pat<(frag GR64:$src1, (shiftMask64 CL)), + (!cast(NAME # "64rCL") GR64:$src1)>; + } + let Predicates = [HasNDD] in { + def : Pat<(frag GR8:$src1, (shiftMask32 CL)), + (!cast(NAME # "8rCL_ND") GR8:$src1)>; + def : Pat<(frag GR16:$src1, (shiftMask32 CL)), + (!cast(NAME # "16rCL_ND") GR16:$src1)>; + def : Pat<(frag GR32:$src1, (shiftMask32 CL)), + (!cast(NAME # "32rCL_ND") GR32:$src1)>; + def : Pat<(frag GR64:$src1, (shiftMask64 CL)), + (!cast(NAME # "64rCL_ND") GR64:$src1)>; + } + + def : Pat<(store (frag (loadi8 addr:$dst), (shiftMask32 CL)), addr:$dst), + (!cast(NAME # "8mCL") addr:$dst)>; + def : Pat<(store (frag (loadi16 addr:$dst), (shiftMask32 CL)), addr:$dst), + (!cast(NAME # "16mCL") addr:$dst)>; + def : Pat<(store (frag (loadi32 addr:$dst), (shiftMask32 CL)), addr:$dst), + (!cast(NAME # "32mCL") addr:$dst)>; def : Pat<(store (frag (loadi64 addr:$dst), (shiftMask64 CL)), addr:$dst), - (!cast(name # "64mCL") addr:$dst)>; + (!cast(NAME # "64mCL") addr:$dst)>; + + let Predicates = [HasNDD] in { + def : Pat<(frag (loadi8 addr:$src), (shiftMask32 CL)), + (!cast(NAME # "8mCL_ND") addr:$src)>; + def : Pat<(frag (loadi16 addr:$src), (shiftMask32 CL)), + (!cast(NAME # "16mCL_ND") addr:$src)>; + def : Pat<(frag (loadi32 addr:$src), (shiftMask32 CL)), + (!cast(NAME # "32mCL_ND") addr:$src)>; + def : Pat<(frag (loadi64 addr:$src), (shiftMask64 CL)), + (!cast(NAME # "64mCL_ND") addr:$src)>; + } } -defm : MaskedShiftAmountPats; -defm : MaskedShiftAmountPats; -defm : MaskedShiftAmountPats; +defm SHL : MaskedShiftAmountPats; +defm SHR : MaskedShiftAmountPats; +defm SAR : MaskedShiftAmountPats; // ROL/ROR instructions allow a stronger mask optimization than shift for 8- and // 16-bit. We can remove a mask of any (bitwidth - 1) on the rotation amount @@ -1819,138 +1842,107 @@ defm : MaskedShiftAmountPats; // docs with: "tempCOUNT <- (COUNT & COUNTMASK) MOD SIZE". Masking the rotation // amount could affect EFLAGS results, but that does not matter because we are // not tracking flags for these nodes. -multiclass MaskedRotateAmountPats { +multiclass MaskedRotateAmountPats { // (rot x (and y, BitWidth - 1)) ==> (rot x, y) - def : Pat<(frag GR8:$src1, (shiftMask8 CL)), - (!cast(name # "8rCL") GR8:$src1)>; - def : Pat<(frag GR16:$src1, (shiftMask16 CL)), - (!cast(name # "16rCL") GR16:$src1)>; - def : Pat<(frag GR32:$src1, (shiftMask32 CL)), - (!cast(name # "32rCL") GR32:$src1)>; - def : Pat<(store (frag (loadi8 addr:$dst), (shiftMask8 CL)), addr:$dst), - (!cast(name # "8mCL") addr:$dst)>; - def : Pat<(store (frag (loadi16 addr:$dst), (shiftMask16 CL)), addr:$dst), - (!cast(name # "16mCL") addr:$dst)>; - def : Pat<(store (frag (loadi32 addr:$dst), (shiftMask32 CL)), addr:$dst), - (!cast(name # "32mCL") addr:$dst)>; - - // (rot x (and y, 63)) ==> (rot x, y) - def : Pat<(frag GR64:$src1, (shiftMask64 CL)), - (!cast(name # "64rCL") GR64:$src1)>; - def : Pat<(store (frag (loadi64 addr:$dst), (shiftMask64 CL)), addr:$dst), - (!cast(name # "64mCL") addr:$dst)>; -} - - -defm : MaskedRotateAmountPats; -defm : MaskedRotateAmountPats; - -// Double "funnel" shift amount is implicitly masked. -// (fshl/fshr x (and y, 31)) ==> (fshl/fshr x, y) (NOTE: modulo32) -def : Pat<(X86fshl GR16:$src1, GR16:$src2, (shiftMask32 CL)), - (SHLD16rrCL GR16:$src1, GR16:$src2)>; -def : Pat<(X86fshr GR16:$src2, GR16:$src1, (shiftMask32 CL)), - (SHRD16rrCL GR16:$src1, GR16:$src2)>; - -// (fshl/fshr x (and y, 31)) ==> (fshl/fshr x, y) -def : Pat<(fshl GR32:$src1, GR32:$src2, (shiftMask32 CL)), - (SHLD32rrCL GR32:$src1, GR32:$src2)>; -def : Pat<(fshr GR32:$src2, GR32:$src1, (shiftMask32 CL)), - (SHRD32rrCL GR32:$src1, GR32:$src2)>; - -// (fshl/fshr x (and y, 63)) ==> (fshl/fshr x, y) -def : Pat<(fshl GR64:$src1, GR64:$src2, (shiftMask64 CL)), - (SHLD64rrCL GR64:$src1, GR64:$src2)>; -def : Pat<(fshr GR64:$src2, GR64:$src1, (shiftMask64 CL)), - (SHRD64rrCL GR64:$src1, GR64:$src2)>; - -let Predicates = [HasBMI2] in { - let AddedComplexity = 1 in { - def : Pat<(sra GR32:$src1, (shiftMask32 GR8:$src2)), - (SARX32rr GR32:$src1, - (INSERT_SUBREG - (i32 (IMPLICIT_DEF)), GR8:$src2, sub_8bit))>; - def : Pat<(sra GR64:$src1, (shiftMask64 GR8:$src2)), - (SARX64rr GR64:$src1, - (INSERT_SUBREG - (i64 (IMPLICIT_DEF)), GR8:$src2, sub_8bit))>; - - def : Pat<(srl GR32:$src1, (shiftMask32 GR8:$src2)), - (SHRX32rr GR32:$src1, - (INSERT_SUBREG - (i32 (IMPLICIT_DEF)), GR8:$src2, sub_8bit))>; - def : Pat<(srl GR64:$src1, (shiftMask64 GR8:$src2)), - (SHRX64rr GR64:$src1, - (INSERT_SUBREG - (i64 (IMPLICIT_DEF)), GR8:$src2, sub_8bit))>; - - def : Pat<(shl GR32:$src1, (shiftMask32 GR8:$src2)), - (SHLX32rr GR32:$src1, - (INSERT_SUBREG - (i32 (IMPLICIT_DEF)), GR8:$src2, sub_8bit))>; - def : Pat<(shl GR64:$src1, (shiftMask64 GR8:$src2)), - (SHLX64rr GR64:$src1, - (INSERT_SUBREG - (i64 (IMPLICIT_DEF)), GR8:$src2, sub_8bit))>; + let Predicates = [NoNDD] in { + def : Pat<(frag GR8:$src1, (shiftMask8 CL)), + (!cast(NAME # "8rCL") GR8:$src1)>; + def : Pat<(frag GR16:$src1, (shiftMask16 CL)), + (!cast(NAME # "16rCL") GR16:$src1)>; + def : Pat<(frag GR32:$src1, (shiftMask32 CL)), + (!cast(NAME # "32rCL") GR32:$src1)>; + def : Pat<(frag GR64:$src1, (shiftMask64 CL)), + (!cast(NAME # "64rCL") GR64:$src1)>; + } + let Predicates = [HasNDD] in { + def : Pat<(frag GR8:$src1, (shiftMask8 CL)), + (!cast(NAME # "8rCL_ND") GR8:$src1)>; + def : Pat<(frag GR16:$src1, (shiftMask16 CL)), + (!cast(NAME # "16rCL_ND") GR16:$src1)>; + def : Pat<(frag GR32:$src1, (shiftMask32 CL)), + (!cast(NAME # "32rCL_ND") GR32:$src1)>; + def : Pat<(frag GR64:$src1, (shiftMask64 CL)), + (!cast(NAME # "64rCL_ND") GR64:$src1)>; } - def : Pat<(sra (loadi32 addr:$src1), (shiftMask32 GR8:$src2)), - (SARX32rm addr:$src1, - (INSERT_SUBREG - (i32 (IMPLICIT_DEF)), GR8:$src2, sub_8bit))>; - def : Pat<(sra (loadi64 addr:$src1), (shiftMask64 GR8:$src2)), - (SARX64rm addr:$src1, - (INSERT_SUBREG - (i64 (IMPLICIT_DEF)), GR8:$src2, sub_8bit))>; + def : Pat<(store (frag (loadi8 addr:$dst), (shiftMask8 CL)), addr:$dst), + (!cast(NAME # "8mCL") addr:$dst)>; + def : Pat<(store (frag (loadi16 addr:$dst), (shiftMask16 CL)), addr:$dst), + (!cast(NAME # "16mCL") addr:$dst)>; + def : Pat<(store (frag (loadi32 addr:$dst), (shiftMask32 CL)), addr:$dst), + (!cast(NAME # "32mCL") addr:$dst)>; + def : Pat<(store (frag (loadi64 addr:$dst), (shiftMask64 CL)), addr:$dst), + (!cast(NAME # "64mCL") addr:$dst)>; - def : Pat<(srl (loadi32 addr:$src1), (shiftMask32 GR8:$src2)), - (SHRX32rm addr:$src1, - (INSERT_SUBREG - (i32 (IMPLICIT_DEF)), GR8:$src2, sub_8bit))>; - def : Pat<(srl (loadi64 addr:$src1), (shiftMask64 GR8:$src2)), - (SHRX64rm addr:$src1, - (INSERT_SUBREG - (i64 (IMPLICIT_DEF)), GR8:$src2, sub_8bit))>; - - def : Pat<(shl (loadi32 addr:$src1), (shiftMask32 GR8:$src2)), - (SHLX32rm addr:$src1, - (INSERT_SUBREG - (i32 (IMPLICIT_DEF)), GR8:$src2, sub_8bit))>; - def : Pat<(shl (loadi64 addr:$src1), (shiftMask64 GR8:$src2)), - (SHLX64rm addr:$src1, - (INSERT_SUBREG - (i64 (IMPLICIT_DEF)), GR8:$src2, sub_8bit))>; + let Predicates = [HasNDD] in { + def : Pat<(frag (loadi8 addr:$src), (shiftMask8 CL)), + (!cast(NAME # "8mCL_ND") addr:$src)>; + def : Pat<(frag (loadi16 addr:$src), (shiftMask16 CL)), + (!cast(NAME # "16mCL_ND") addr:$src)>; + def : Pat<(frag (loadi32 addr:$src), (shiftMask32 CL)), + (!cast(NAME # "32mCL_ND") addr:$src)>; + def : Pat<(frag (loadi64 addr:$src), (shiftMask64 CL)), + (!cast(NAME # "64mCL_ND") addr:$src)>; + } } +defm ROL : MaskedRotateAmountPats; +defm ROR : MaskedRotateAmountPats; + +multiclass MaskedShlrdAmountPats { + let Predicates = [p] in { + // Double "funnel" shift amount is implicitly masked. + // (fshl/fshr x (and y, 31)) ==> (fshl/fshr x, y) (NOTE: modulo32) + def : Pat<(X86fshl GR16:$src1, GR16:$src2, (shiftMask32 CL)), + (!cast(SHLD16rrCL#suffix) GR16:$src1, GR16:$src2)>; + def : Pat<(X86fshr GR16:$src2, GR16:$src1, (shiftMask32 CL)), + (!cast(SHRD16rrCL#suffix) GR16:$src1, GR16:$src2)>; + + // (fshl/fshr x (and y, 31)) ==> (fshl/fshr x, y) + def : Pat<(fshl GR32:$src1, GR32:$src2, (shiftMask32 CL)), + (!cast(SHLD32rrCL#suffix) GR32:$src1, GR32:$src2)>; + def : Pat<(fshr GR32:$src2, GR32:$src1, (shiftMask32 CL)), + (!cast(SHRD32rrCL#suffix) GR32:$src1, GR32:$src2)>; + + // (fshl/fshr x (and y, 63)) ==> (fshl/fshr x, y) + def : Pat<(fshl GR64:$src1, GR64:$src2, (shiftMask64 CL)), + (!cast(SHLD64rrCL#suffix) GR64:$src1, GR64:$src2)>; + def : Pat<(fshr GR64:$src2, GR64:$src1, (shiftMask64 CL)), + (!cast(SHRD64rrCL#suffix) GR64:$src1, GR64:$src2)>; + } +} + +defm : MaskedShlrdAmountPats<"", NoNDD>; +defm : MaskedShlrdAmountPats<"_ND", HasNDD>; + // Use BTR/BTS/BTC for clearing/setting/toggling a bit in a variable location. -multiclass one_bit_patterns { - def : Pat<(and RC:$src1, (rotl -2, GR8:$src2)), - (BTR RC:$src1, - (INSERT_SUBREG (VT (IMPLICIT_DEF)), GR8:$src2, sub_8bit))>; - def : Pat<(or RC:$src1, (shl 1, GR8:$src2)), - (BTS RC:$src1, - (INSERT_SUBREG (VT (IMPLICIT_DEF)), GR8:$src2, sub_8bit))>; - def : Pat<(xor RC:$src1, (shl 1, GR8:$src2)), - (BTC RC:$src1, - (INSERT_SUBREG (VT (IMPLICIT_DEF)), GR8:$src2, sub_8bit))>; +multiclass OneBitPats { + def : Pat<(and rc:$src1, (rotl -2, GR8:$src2)), + (btr rc:$src1, + (INSERT_SUBREG (vt (IMPLICIT_DEF)), GR8:$src2, sub_8bit))>; + def : Pat<(or rc:$src1, (shl 1, GR8:$src2)), + (bts rc:$src1, + (INSERT_SUBREG (vt (IMPLICIT_DEF)), GR8:$src2, sub_8bit))>; + def : Pat<(xor rc:$src1, (shl 1, GR8:$src2)), + (btc rc:$src1, + (INSERT_SUBREG (vt (IMPLICIT_DEF)), GR8:$src2, sub_8bit))>; // Similar to above, but removing unneeded masking of the shift amount. - def : Pat<(and RC:$src1, (rotl -2, (ShiftMask GR8:$src2))), - (BTR RC:$src1, - (INSERT_SUBREG (VT (IMPLICIT_DEF)), GR8:$src2, sub_8bit))>; - def : Pat<(or RC:$src1, (shl 1, (ShiftMask GR8:$src2))), - (BTS RC:$src1, - (INSERT_SUBREG (VT (IMPLICIT_DEF)), GR8:$src2, sub_8bit))>; - def : Pat<(xor RC:$src1, (shl 1, (ShiftMask GR8:$src2))), - (BTC RC:$src1, - (INSERT_SUBREG (VT (IMPLICIT_DEF)), GR8:$src2, sub_8bit))>; + def : Pat<(and rc:$src1, (rotl -2, (mask GR8:$src2))), + (btr rc:$src1, + (INSERT_SUBREG (vt (IMPLICIT_DEF)), GR8:$src2, sub_8bit))>; + def : Pat<(or rc:$src1, (shl 1, (mask GR8:$src2))), + (bts rc:$src1, + (INSERT_SUBREG (vt (IMPLICIT_DEF)), GR8:$src2, sub_8bit))>; + def : Pat<(xor rc:$src1, (shl 1, (mask GR8:$src2))), + (btc rc:$src1, + (INSERT_SUBREG (vt (IMPLICIT_DEF)), GR8:$src2, sub_8bit))>; } -defm : one_bit_patterns; -defm : one_bit_patterns; -defm : one_bit_patterns; +defm : OneBitPats; +defm : OneBitPats; +defm : OneBitPats; //===----------------------------------------------------------------------===// // EFLAGS-defining Patterns diff --git a/llvm/lib/Target/X86/X86InstrInfo.cpp b/llvm/lib/Target/X86/X86InstrInfo.cpp index bddda689135..d6f9aa6d6ac 100644 --- a/llvm/lib/Target/X86/X86InstrInfo.cpp +++ b/llvm/lib/Target/X86/X86InstrInfo.cpp @@ -2260,23 +2260,30 @@ static unsigned getCommutedVPERMV3Opcode(unsigned Opcode) { MachineInstr *X86InstrInfo::commuteInstructionImpl(MachineInstr &MI, bool NewMI, unsigned OpIdx1, unsigned OpIdx2) const { - auto cloneIfNew = [NewMI](MachineInstr &MI) -> MachineInstr & { - if (NewMI) - return *MI.getParent()->getParent()->CloneMachineInstr(&MI); - return MI; + auto CloneIfNew = [&](MachineInstr &MI) { + return std::exchange(NewMI, false) + ? MI.getParent()->getParent()->CloneMachineInstr(&MI) + : &MI; }; + MachineInstr *WorkingMI = nullptr; + unsigned Opc = MI.getOpcode(); - switch (MI.getOpcode()) { - case X86::SHRD16rri8: // A = SHRD16rri8 B, C, I -> A = SHLD16rri8 C, B, (16-I) - case X86::SHLD16rri8: // A = SHLD16rri8 B, C, I -> A = SHRD16rri8 C, B, (16-I) - case X86::SHRD32rri8: // A = SHRD32rri8 B, C, I -> A = SHLD32rri8 C, B, (32-I) - case X86::SHLD32rri8: // A = SHLD32rri8 B, C, I -> A = SHRD32rri8 C, B, (32-I) - case X86::SHRD64rri8: // A = SHRD64rri8 B, C, I -> A = SHLD64rri8 C, B, (64-I) - case X86::SHLD64rri8: { // A = SHLD64rri8 B, C, I -> A = SHRD64rri8 C, B, - // (64-I) - unsigned Opc; + switch (Opc) { + // SHLD B, C, I <-> SHRD C, B, (BitWidth - I) + case X86::SHRD16rri8: + case X86::SHLD16rri8: + case X86::SHRD32rri8: + case X86::SHLD32rri8: + case X86::SHRD64rri8: + case X86::SHLD64rri8: + case X86::SHRD16rri8_ND: + case X86::SHLD16rri8_ND: + case X86::SHRD32rri8_ND: + case X86::SHLD32rri8_ND: + case X86::SHRD64rri8_ND: + case X86::SHLD64rri8_ND: { unsigned Size; - switch (MI.getOpcode()) { + switch (Opc) { default: llvm_unreachable("Unreachable!"); case X86::SHRD16rri8: @@ -2303,33 +2310,52 @@ MachineInstr *X86InstrInfo::commuteInstructionImpl(MachineInstr &MI, bool NewMI, Size = 64; Opc = X86::SHRD64rri8; break; + case X86::SHRD16rri8_ND: + Size = 16; + Opc = X86::SHLD16rri8_ND; + break; + case X86::SHLD16rri8_ND: + Size = 16; + Opc = X86::SHRD16rri8_ND; + break; + case X86::SHRD32rri8_ND: + Size = 32; + Opc = X86::SHLD32rri8_ND; + break; + case X86::SHLD32rri8_ND: + Size = 32; + Opc = X86::SHRD32rri8_ND; + break; + case X86::SHRD64rri8_ND: + Size = 64; + Opc = X86::SHLD64rri8_ND; + break; + case X86::SHLD64rri8_ND: + Size = 64; + Opc = X86::SHRD64rri8_ND; + break; } - unsigned Amt = MI.getOperand(3).getImm(); - auto &WorkingMI = cloneIfNew(MI); - WorkingMI.setDesc(get(Opc)); - WorkingMI.getOperand(3).setImm(Size - Amt); - return TargetInstrInfo::commuteInstructionImpl(WorkingMI, /*NewMI=*/false, - OpIdx1, OpIdx2); + WorkingMI = CloneIfNew(MI); + WorkingMI->setDesc(get(Opc)); + WorkingMI->getOperand(3).setImm(Size - MI.getOperand(3).getImm()); + break; } case X86::PFSUBrr: - case X86::PFSUBRrr: { + case X86::PFSUBRrr: // PFSUB x, y: x = x - y // PFSUBR x, y: x = y - x - unsigned Opc = - (X86::PFSUBRrr == MI.getOpcode() ? X86::PFSUBrr : X86::PFSUBRrr); - auto &WorkingMI = cloneIfNew(MI); - WorkingMI.setDesc(get(Opc)); - return TargetInstrInfo::commuteInstructionImpl(WorkingMI, /*NewMI=*/false, - OpIdx1, OpIdx2); - } + WorkingMI = CloneIfNew(MI); + WorkingMI->setDesc( + get(X86::PFSUBRrr == Opc ? X86::PFSUBrr : X86::PFSUBRrr)); + break; case X86::BLENDPDrri: case X86::BLENDPSrri: case X86::VBLENDPDrri: case X86::VBLENDPSrri: // If we're optimizing for size, try to use MOVSD/MOVSS. if (MI.getParent()->getParent()->getFunction().hasOptSize()) { - unsigned Mask, Opc; - switch (MI.getOpcode()) { + unsigned Mask; + switch (Opc) { default: llvm_unreachable("Unreachable!"); case X86::BLENDPDrri: @@ -2350,12 +2376,10 @@ MachineInstr *X86InstrInfo::commuteInstructionImpl(MachineInstr &MI, bool NewMI, break; } if ((MI.getOperand(3).getImm() ^ Mask) == 1) { - auto &WorkingMI = cloneIfNew(MI); - WorkingMI.setDesc(get(Opc)); - WorkingMI.removeOperand(3); - return TargetInstrInfo::commuteInstructionImpl(WorkingMI, - /*NewMI=*/false, OpIdx1, - OpIdx2); + WorkingMI = CloneIfNew(MI); + WorkingMI->setDesc(get(Opc)); + WorkingMI->removeOperand(3); + break; } } [[fallthrough]]; @@ -2367,7 +2391,7 @@ MachineInstr *X86InstrInfo::commuteInstructionImpl(MachineInstr &MI, bool NewMI, case X86::VPBLENDDYrri: case X86::VPBLENDWYrri: { int8_t Mask; - switch (MI.getOpcode()) { + switch (Opc) { default: llvm_unreachable("Unreachable!"); case X86::BLENDPDrri: @@ -2408,10 +2432,9 @@ MachineInstr *X86InstrInfo::commuteInstructionImpl(MachineInstr &MI, bool NewMI, // Using int8_t to ensure it will be sign extended to the int64_t that // setImm takes in order to match isel behavior. int8_t Imm = MI.getOperand(3).getImm() & Mask; - auto &WorkingMI = cloneIfNew(MI); - WorkingMI.getOperand(3).setImm(Mask ^ Imm); - return TargetInstrInfo::commuteInstructionImpl(WorkingMI, /*NewMI=*/false, - OpIdx1, OpIdx2); + WorkingMI = CloneIfNew(MI); + WorkingMI->getOperand(3).setImm(Mask ^ Imm); + break; } case X86::INSERTPSrr: case X86::VINSERTPSrr: @@ -2428,10 +2451,9 @@ MachineInstr *X86InstrInfo::commuteInstructionImpl(MachineInstr &MI, bool NewMI, unsigned AltIdx = llvm::countr_zero((ZMask | (1 << DstIdx)) ^ 15); assert(AltIdx < 4 && "Illegal insertion index"); unsigned AltImm = (AltIdx << 6) | (AltIdx << 4) | ZMask; - auto &WorkingMI = cloneIfNew(MI); - WorkingMI.getOperand(MI.getNumOperands() - 1).setImm(AltImm); - return TargetInstrInfo::commuteInstructionImpl(WorkingMI, /*NewMI=*/false, - OpIdx1, OpIdx2); + WorkingMI = CloneIfNew(MI); + WorkingMI->getOperand(MI.getNumOperands() - 1).setImm(AltImm); + break; } return nullptr; } @@ -2441,8 +2463,8 @@ MachineInstr *X86InstrInfo::commuteInstructionImpl(MachineInstr &MI, bool NewMI, case X86::VMOVSSrr: { // On SSE41 or later we can commute a MOVSS/MOVSD to a BLENDPS/BLENDPD. if (Subtarget.hasSSE41()) { - unsigned Mask, Opc; - switch (MI.getOpcode()) { + unsigned Mask; + switch (Opc) { default: llvm_unreachable("Unreachable!"); case X86::MOVSDrr: @@ -2463,31 +2485,24 @@ MachineInstr *X86InstrInfo::commuteInstructionImpl(MachineInstr &MI, bool NewMI, break; } - auto &WorkingMI = cloneIfNew(MI); - WorkingMI.setDesc(get(Opc)); - WorkingMI.addOperand(MachineOperand::CreateImm(Mask)); - return TargetInstrInfo::commuteInstructionImpl(WorkingMI, /*NewMI=*/false, - OpIdx1, OpIdx2); + WorkingMI = CloneIfNew(MI); + WorkingMI->setDesc(get(Opc)); + WorkingMI->addOperand(MachineOperand::CreateImm(Mask)); + break; } - // Convert to SHUFPD. - assert(MI.getOpcode() == X86::MOVSDrr && - "Can only commute MOVSDrr without SSE4.1"); - - auto &WorkingMI = cloneIfNew(MI); - WorkingMI.setDesc(get(X86::SHUFPDrri)); - WorkingMI.addOperand(MachineOperand::CreateImm(0x02)); - return TargetInstrInfo::commuteInstructionImpl(WorkingMI, /*NewMI=*/false, - OpIdx1, OpIdx2); + WorkingMI = CloneIfNew(MI); + WorkingMI->setDesc(get(X86::SHUFPDrri)); + WorkingMI->addOperand(MachineOperand::CreateImm(0x02)); + break; } case X86::SHUFPDrri: { // Commute to MOVSD. assert(MI.getOperand(3).getImm() == 0x02 && "Unexpected immediate!"); - auto &WorkingMI = cloneIfNew(MI); - WorkingMI.setDesc(get(X86::MOVSDrr)); - WorkingMI.removeOperand(3); - return TargetInstrInfo::commuteInstructionImpl(WorkingMI, /*NewMI=*/false, - OpIdx1, OpIdx2); + WorkingMI = CloneIfNew(MI); + WorkingMI->setDesc(get(X86::MOVSDrr)); + WorkingMI->removeOperand(3); + break; } case X86::PCLMULQDQrr: case X86::VPCLMULQDQrr: @@ -2500,10 +2515,9 @@ MachineInstr *X86InstrInfo::commuteInstructionImpl(MachineInstr &MI, bool NewMI, unsigned Imm = MI.getOperand(3).getImm(); unsigned Src1Hi = Imm & 0x01; unsigned Src2Hi = Imm & 0x10; - auto &WorkingMI = cloneIfNew(MI); - WorkingMI.getOperand(3).setImm((Src1Hi << 4) | (Src2Hi >> 4)); - return TargetInstrInfo::commuteInstructionImpl(WorkingMI, /*NewMI=*/false, - OpIdx1, OpIdx2); + WorkingMI = CloneIfNew(MI); + WorkingMI->getOperand(3).setImm((Src1Hi << 4) | (Src2Hi >> 4)); + break; } case X86::VPCMPBZ128rri: case X86::VPCMPUBZ128rri: @@ -2552,15 +2566,13 @@ MachineInstr *X86InstrInfo::commuteInstructionImpl(MachineInstr &MI, bool NewMI, case X86::VPCMPWZ256rrik: case X86::VPCMPUWZ256rrik: case X86::VPCMPWZrrik: - case X86::VPCMPUWZrrik: { + case X86::VPCMPUWZrrik: + WorkingMI = CloneIfNew(MI); // Flip comparison mode immediate (if necessary). - unsigned Imm = MI.getOperand(MI.getNumOperands() - 1).getImm() & 0x7; - Imm = X86::getSwappedVPCMPImm(Imm); - auto &WorkingMI = cloneIfNew(MI); - WorkingMI.getOperand(MI.getNumOperands() - 1).setImm(Imm); - return TargetInstrInfo::commuteInstructionImpl(WorkingMI, /*NewMI=*/false, - OpIdx1, OpIdx2); - } + WorkingMI->getOperand(MI.getNumOperands() - 1) + .setImm(X86::getSwappedVPCMPImm( + MI.getOperand(MI.getNumOperands() - 1).getImm() & 0x7)); + break; case X86::VPCOMBri: case X86::VPCOMUBri: case X86::VPCOMDri: @@ -2568,15 +2580,12 @@ MachineInstr *X86InstrInfo::commuteInstructionImpl(MachineInstr &MI, bool NewMI, case X86::VPCOMQri: case X86::VPCOMUQri: case X86::VPCOMWri: - case X86::VPCOMUWri: { + case X86::VPCOMUWri: + WorkingMI = CloneIfNew(MI); // Flip comparison mode immediate (if necessary). - unsigned Imm = MI.getOperand(3).getImm() & 0x7; - Imm = X86::getSwappedVPCOMImm(Imm); - auto &WorkingMI = cloneIfNew(MI); - WorkingMI.getOperand(3).setImm(Imm); - return TargetInstrInfo::commuteInstructionImpl(WorkingMI, /*NewMI=*/false, - OpIdx1, OpIdx2); - } + WorkingMI->getOperand(3).setImm( + X86::getSwappedVPCOMImm(MI.getOperand(3).getImm() & 0x7)); + break; case X86::VCMPSDZrr: case X86::VCMPSSZrr: case X86::VCMPPDZrri: @@ -2594,35 +2603,28 @@ MachineInstr *X86InstrInfo::commuteInstructionImpl(MachineInstr &MI, bool NewMI, case X86::VCMPPDZ128rrik: case X86::VCMPPSZ128rrik: case X86::VCMPPDZ256rrik: - case X86::VCMPPSZ256rrik: { - unsigned Imm = - MI.getOperand(MI.getNumExplicitOperands() - 1).getImm() & 0x1f; - Imm = X86::getSwappedVCMPImm(Imm); - auto &WorkingMI = cloneIfNew(MI); - WorkingMI.getOperand(MI.getNumExplicitOperands() - 1).setImm(Imm); - return TargetInstrInfo::commuteInstructionImpl(WorkingMI, /*NewMI=*/false, - OpIdx1, OpIdx2); - } + case X86::VCMPPSZ256rrik: + WorkingMI = CloneIfNew(MI); + WorkingMI->getOperand(MI.getNumExplicitOperands() - 1) + .setImm(X86::getSwappedVCMPImm( + MI.getOperand(MI.getNumExplicitOperands() - 1).getImm() & 0x1f)); + break; case X86::VPERM2F128rr: - case X86::VPERM2I128rr: { + case X86::VPERM2I128rr: // Flip permute source immediate. // Imm & 0x02: lo = if set, select Op1.lo/hi else Op0.lo/hi. // Imm & 0x20: hi = if set, select Op1.lo/hi else Op0.lo/hi. - int8_t Imm = MI.getOperand(3).getImm() & 0xFF; - auto &WorkingMI = cloneIfNew(MI); - WorkingMI.getOperand(3).setImm(Imm ^ 0x22); - return TargetInstrInfo::commuteInstructionImpl(WorkingMI, /*NewMI=*/false, - OpIdx1, OpIdx2); - } + WorkingMI = CloneIfNew(MI); + WorkingMI->getOperand(3).setImm((MI.getOperand(3).getImm() & 0xFF) ^ 0x22); + break; case X86::MOVHLPSrr: case X86::UNPCKHPDrr: case X86::VMOVHLPSrr: case X86::VUNPCKHPDrr: case X86::VMOVHLPSZrr: - case X86::VUNPCKHPDZ128rr: { + case X86::VUNPCKHPDZ128rr: assert(Subtarget.hasSSE2() && "Commuting MOVHLP/UNPCKHPD requires SSE2!"); - unsigned Opc = MI.getOpcode(); switch (Opc) { default: llvm_unreachable("Unreachable!"); @@ -2645,20 +2647,17 @@ MachineInstr *X86InstrInfo::commuteInstructionImpl(MachineInstr &MI, bool NewMI, Opc = X86::VMOVHLPSZrr; break; } - auto &WorkingMI = cloneIfNew(MI); - WorkingMI.setDesc(get(Opc)); - return TargetInstrInfo::commuteInstructionImpl(WorkingMI, /*NewMI=*/false, - OpIdx1, OpIdx2); - } + WorkingMI = CloneIfNew(MI); + WorkingMI->setDesc(get(Opc)); + break; case X86::CMOV16rr: case X86::CMOV32rr: case X86::CMOV64rr: { - auto &WorkingMI = cloneIfNew(MI); + WorkingMI = CloneIfNew(MI); unsigned OpNo = MI.getDesc().getNumOperands() - 1; X86::CondCode CC = static_cast(MI.getOperand(OpNo).getImm()); - WorkingMI.getOperand(OpNo).setImm(X86::GetOppositeBranchCondition(CC)); - return TargetInstrInfo::commuteInstructionImpl(WorkingMI, /*NewMI=*/false, - OpIdx1, OpIdx2); + WorkingMI->getOperand(OpNo).setImm(X86::GetOppositeBranchCondition(CC)); + break; } case X86::VPTERNLOGDZrri: case X86::VPTERNLOGDZrmi: @@ -2702,34 +2701,25 @@ MachineInstr *X86InstrInfo::commuteInstructionImpl(MachineInstr &MI, bool NewMI, case X86::VPTERNLOGQZ128rmbikz: case X86::VPTERNLOGQZ256rmbikz: case X86::VPTERNLOGQZrmbikz: { - auto &WorkingMI = cloneIfNew(MI); - commuteVPTERNLOG(WorkingMI, OpIdx1, OpIdx2); - return TargetInstrInfo::commuteInstructionImpl(WorkingMI, /*NewMI=*/false, - OpIdx1, OpIdx2); + WorkingMI = CloneIfNew(MI); + commuteVPTERNLOG(*WorkingMI, OpIdx1, OpIdx2); + break; } - default: { - if (isCommutableVPERMV3Instruction(MI.getOpcode())) { - unsigned Opc = getCommutedVPERMV3Opcode(MI.getOpcode()); - auto &WorkingMI = cloneIfNew(MI); - WorkingMI.setDesc(get(Opc)); - return TargetInstrInfo::commuteInstructionImpl(WorkingMI, /*NewMI=*/false, - OpIdx1, OpIdx2); + default: + if (isCommutableVPERMV3Instruction(Opc)) { + WorkingMI = CloneIfNew(MI); + WorkingMI->setDesc(get(getCommutedVPERMV3Opcode(Opc))); + break; } - const X86InstrFMA3Group *FMA3Group = - getFMA3Group(MI.getOpcode(), MI.getDesc().TSFlags); - if (FMA3Group) { - unsigned Opc = - getFMA3OpcodeToCommuteOperands(MI, OpIdx1, OpIdx2, *FMA3Group); - auto &WorkingMI = cloneIfNew(MI); - WorkingMI.setDesc(get(Opc)); - return TargetInstrInfo::commuteInstructionImpl(WorkingMI, /*NewMI=*/false, - OpIdx1, OpIdx2); + if (auto *FMA3Group = getFMA3Group(Opc, MI.getDesc().TSFlags)) { + WorkingMI = CloneIfNew(MI); + WorkingMI->setDesc( + get(getFMA3OpcodeToCommuteOperands(MI, OpIdx1, OpIdx2, *FMA3Group))); + break; } - - return TargetInstrInfo::commuteInstructionImpl(MI, NewMI, OpIdx1, OpIdx2); - } } + return TargetInstrInfo::commuteInstructionImpl(MI, NewMI, OpIdx1, OpIdx2); } bool X86InstrInfo::findThreeSrcCommutedOpIndices(const MachineInstr &MI, @@ -3463,6 +3453,82 @@ bool X86::isX87Instruction(MachineInstr &MI) { return false; } +int X86::getFirstAddrOperandIdx(const MachineInstr &MI) { + auto IsMemOp = [](const MCOperandInfo &OpInfo) { + return OpInfo.OperandType == MCOI::OPERAND_MEMORY; + }; + + const MCInstrDesc &Desc = MI.getDesc(); + + // Directly invoke the MC-layer routine for real (i.e., non-pseudo) + // instructions (fast case). + if (!X86II::isPseudo(Desc.TSFlags)) { + int MemRefIdx = X86II::getMemoryOperandNo(Desc.TSFlags); + if (MemRefIdx >= 0) + return MemRefIdx + X86II::getOperandBias(Desc); +#ifdef EXPENSIVE_CHECKS + assert(none_of(Desc.operands(), IsMemOp) && + "Got false negative from X86II::getMemoryOperandNo()!"); +#endif + return -1; + } + + // Otherwise, handle pseudo instructions by examining the type of their + // operands (slow case). An instruction cannot have a memory reference if it + // has fewer than AddrNumOperands (= 5) explicit operands. + unsigned NumOps = Desc.getNumOperands(); + if (NumOps < X86::AddrNumOperands) { +#ifdef EXPENSIVE_CHECKS + assert(none_of(Desc.operands(), IsMemOp) && + "Expected no operands to have OPERAND_MEMORY type!"); +#endif + return -1; + } + + // The first operand with type OPERAND_MEMORY indicates the start of a memory + // reference. We expect the following AddrNumOperand-1 operands to also have + // OPERAND_MEMORY type. + for (unsigned I = 0, E = NumOps - X86::AddrNumOperands; I != E; ++I) { + if (IsMemOp(Desc.operands()[I])) { +#ifdef EXPENSIVE_CHECKS + assert(std::all_of(Desc.operands().begin() + I, + Desc.operands().begin() + I + X86::AddrNumOperands, + IsMemOp) && + "Expected all five operands in the memory reference to have " + "OPERAND_MEMORY type!"); +#endif + return I; + } + } + + return -1; +} + +const Constant *X86::getConstantFromPool(const MachineInstr &MI, + unsigned OpNo) { + assert(MI.getNumOperands() >= (OpNo + X86::AddrNumOperands) && + "Unexpected number of operands!"); + + const MachineOperand &Index = MI.getOperand(OpNo + X86::AddrIndexReg); + if (!Index.isReg() || Index.getReg() != X86::NoRegister) + return nullptr; + + const MachineOperand &Disp = MI.getOperand(OpNo + X86::AddrDisp); + if (!Disp.isCPI() || Disp.getOffset() != 0) + return nullptr; + + ArrayRef Constants = + MI.getParent()->getParent()->getConstantPool()->getConstants(); + const MachineConstantPoolEntry &ConstantEntry = Constants[Disp.getIndex()]; + + // Bail if this is a machine constant pool entry, we won't be able to dig out + // anything useful. + if (ConstantEntry.isMachineConstantPoolEntry()) + return nullptr; + + return ConstantEntry.Val.ConstVal; +} + bool X86InstrInfo::isUnconditionalTailCall(const MachineInstr &MI) const { switch (MI.getOpcode()) { case X86::TCRETURNdi: @@ -4314,7 +4380,10 @@ static unsigned getLoadStoreRegOpcode(Register Reg, case 1024: assert(X86::TILERegClass.hasSubClassEq(RC) && "Unknown 1024-byte regclass"); assert(STI.hasAMXTILE() && "Using 8*1024-bit register requires AMX-TILE"); - return Load ? X86::TILELOADD : X86::TILESTORED; +#define GET_EGPR_IF_ENABLED(OPC) (STI.hasEGPR() ? OPC##_EVEX : OPC) + return Load ? GET_EGPR_IF_ENABLED(X86::TILELOADD) + : GET_EGPR_IF_ENABLED(X86::TILESTORED); +#undef GET_EGPR_IF_ENABLED } } @@ -4507,6 +4576,8 @@ static bool isAMXOpcode(unsigned Opc) { return false; case X86::TILELOADD: case X86::TILESTORED: + case X86::TILELOADD_EVEX: + case X86::TILESTORED_EVEX: return true; } } @@ -4518,7 +4589,8 @@ void X86InstrInfo::loadStoreTileReg(MachineBasicBlock &MBB, switch (Opc) { default: llvm_unreachable("Unexpected special opcode!"); - case X86::TILESTORED: { + case X86::TILESTORED: + case X86::TILESTORED_EVEX: { // tilestored %tmm, (%sp, %idx) MachineRegisterInfo &RegInfo = MBB.getParent()->getRegInfo(); Register VirtReg = RegInfo.createVirtualRegister(&X86::GR64_NOSPRegClass); @@ -4531,7 +4603,8 @@ void X86InstrInfo::loadStoreTileReg(MachineBasicBlock &MBB, MO.setIsKill(true); break; } - case X86::TILELOADD: { + case X86::TILELOADD: + case X86::TILELOADD_EVEX: { // tileloadd (%sp, %idx), %tmm MachineRegisterInfo &RegInfo = MBB.getParent()->getRegInfo(); Register VirtReg = RegInfo.createVirtualRegister(&X86::GR64_NOSPRegClass); @@ -10314,23 +10387,20 @@ enum MachineOutlinerClass { MachineOutlinerDefault, MachineOutlinerTailCall }; std::optional X86InstrInfo::getOutliningCandidateInfo( std::vector &RepeatedSequenceLocs) const { - unsigned SequenceSize = - std::accumulate(RepeatedSequenceLocs[0].front(), - std::next(RepeatedSequenceLocs[0].back()), 0, - [](unsigned Sum, const MachineInstr &MI) { - // FIXME: x86 doesn't implement getInstSizeInBytes, so - // we can't tell the cost. Just assume each instruction - // is one byte. - if (MI.isDebugInstr() || MI.isKill()) - return Sum; - return Sum + 1; - }); + unsigned SequenceSize = 0; + for (auto &MI : RepeatedSequenceLocs[0]) { + // FIXME: x86 doesn't implement getInstSizeInBytes, so + // we can't tell the cost. Just assume each instruction + // is one byte. + if (MI.isDebugInstr() || MI.isKill()) + continue; + SequenceSize += 1; + } // We check to see if CFI Instructions are present, and if they are // we find the number of CFI Instructions in the candidates. unsigned CFICount = 0; - for (auto &I : make_range(RepeatedSequenceLocs[0].front(), - std::next(RepeatedSequenceLocs[0].back()))) { + for (auto &I : RepeatedSequenceLocs[0]) { if (I.isCFIInstruction()) CFICount++; } @@ -10349,7 +10419,7 @@ X86InstrInfo::getOutliningCandidateInfo( } // FIXME: Use real size in bytes for call and ret instructions. - if (RepeatedSequenceLocs[0].back()->isTerminator()) { + if (RepeatedSequenceLocs[0].back().isTerminator()) { for (outliner::Candidate &C : RepeatedSequenceLocs) C.setCallInfo(MachineOutlinerTailCall, 1); diff --git a/llvm/lib/Target/X86/X86InstrInfo.h b/llvm/lib/Target/X86/X86InstrInfo.h index eb0734f9a61..939bc7daf1c 100644 --- a/llvm/lib/Target/X86/X86InstrInfo.h +++ b/llvm/lib/Target/X86/X86InstrInfo.h @@ -32,7 +32,9 @@ enum AsmComments { // For instr that was compressed from EVEX to LEGACY. AC_EVEX_2_LEGACY = MachineInstr::TAsmComments, // For instr that was compressed from EVEX to VEX. - AC_EVEX_2_VEX = AC_EVEX_2_LEGACY << 1 + AC_EVEX_2_VEX = AC_EVEX_2_LEGACY << 1, + // For instr that was compressed from EVEX to EVEX. + AC_EVEX_2_EVEX = AC_EVEX_2_VEX << 1 }; /// Return a pair of condition code for the given predicate and whether @@ -77,6 +79,16 @@ unsigned getSwappedVCMPImm(unsigned Imm); /// Check if the instruction is X87 instruction. bool isX87Instruction(MachineInstr &MI); + +/// Return the index of the instruction's first address operand, if it has a +/// memory reference, or -1 if it has none. Unlike X86II::getMemoryOperandNo(), +/// this also works for both pseudo instructions (e.g., TCRETURNmi) as well as +/// real instructions (e.g., JMP64m). +int getFirstAddrOperandIdx(const MachineInstr &MI); + +/// Find any constant pool entry associated with a specific instruction operand. +const Constant *getConstantFromPool(const MachineInstr &MI, unsigned OpNo); + } // namespace X86 /// isGlobalStubReference - Return true if the specified TargetFlag operand is diff --git a/llvm/lib/Target/X86/X86InstrMisc.td b/llvm/lib/Target/X86/X86InstrMisc.td index 753cf62392a..229aa3c6f1f 100644 --- a/llvm/lib/Target/X86/X86InstrMisc.td +++ b/llvm/lib/Target/X86/X86InstrMisc.td @@ -1241,43 +1241,49 @@ let Predicates = [HasBMI, In64BitMode], Defs = [EFLAGS] in { defm BLSI64 : Bls<"blsi", MRM3r, MRM3m, Xi64, "_EVEX">, EVEX; } -let Predicates = [HasBMI] in { +multiclass Bls_Pats { // FIXME(1): patterns for the load versions are not implemented // FIXME(2): By only matching `add_su` and `ineg_su` we may emit // extra `mov` instructions if `src` has future uses. It may be better // to always match if `src` has more users. def : Pat<(and GR32:$src, (add_su GR32:$src, -1)), - (BLSR32rr GR32:$src)>; + (!cast(BLSR32rr#suffix) GR32:$src)>; def : Pat<(and GR64:$src, (add_su GR64:$src, -1)), - (BLSR64rr GR64:$src)>; + (!cast(BLSR64rr#suffix) GR64:$src)>; def : Pat<(xor GR32:$src, (add_su GR32:$src, -1)), - (BLSMSK32rr GR32:$src)>; + (!cast(BLSMSK32rr#suffix) GR32:$src)>; def : Pat<(xor GR64:$src, (add_su GR64:$src, -1)), - (BLSMSK64rr GR64:$src)>; + (!cast(BLSMSK64rr#suffix) GR64:$src)>; def : Pat<(and GR32:$src, (ineg_su GR32:$src)), - (BLSI32rr GR32:$src)>; + (!cast(BLSI32rr#suffix) GR32:$src)>; def : Pat<(and GR64:$src, (ineg_su GR64:$src)), - (BLSI64rr GR64:$src)>; + (!cast(BLSI64rr#suffix) GR64:$src)>; // Versions to match flag producing ops. def : Pat<(and_flag_nocf GR32:$src, (add_su GR32:$src, -1)), - (BLSR32rr GR32:$src)>; + (!cast(BLSR32rr#suffix) GR32:$src)>; def : Pat<(and_flag_nocf GR64:$src, (add_su GR64:$src, -1)), - (BLSR64rr GR64:$src)>; + (!cast(BLSR64rr#suffix) GR64:$src)>; def : Pat<(xor_flag_nocf GR32:$src, (add_su GR32:$src, -1)), - (BLSMSK32rr GR32:$src)>; + (!cast(BLSMSK32rr#suffix) GR32:$src)>; def : Pat<(xor_flag_nocf GR64:$src, (add_su GR64:$src, -1)), - (BLSMSK64rr GR64:$src)>; + (!cast(BLSMSK64rr#suffix) GR64:$src)>; def : Pat<(and_flag_nocf GR32:$src, (ineg_su GR32:$src)), - (BLSI32rr GR32:$src)>; + (!cast(BLSI32rr#suffix) GR32:$src)>; def : Pat<(and_flag_nocf GR64:$src, (ineg_su GR64:$src)), - (BLSI64rr GR64:$src)>; + (!cast(BLSI64rr#suffix) GR64:$src)>; } +let Predicates = [HasBMI, NoEGPR] in + defm : Bls_Pats<"">; + +let Predicates = [HasBMI, HasEGPR] in + defm : Bls_Pats<"_EVEX">; + multiclass Bmi4VOp3 o, string m, X86TypeInfo t, SDPatternOperator node, X86FoldableSchedWrite sched, string Suffix = ""> { let SchedRW = [sched], Form = MRMSrcReg4VOp3 in @@ -1324,7 +1330,7 @@ def AndMask64 : ImmLeaf; // Use BEXTR for 64-bit 'and' with large immediate 'mask'. -let Predicates = [HasBMI, NoBMI2, NoTBM] in { +let Predicates = [HasBMI, NoBMI2, NoTBM, NoEGPR] in { def : Pat<(and GR64:$src, AndMask64:$mask), (BEXTR64rr GR64:$src, (SUBREG_TO_REG (i64 0), @@ -1335,8 +1341,19 @@ let Predicates = [HasBMI, NoBMI2, NoTBM] in { (MOV32ri (BEXTRMaskXForm imm:$mask)), sub_32bit))>; } +let Predicates = [HasBMI, NoBMI2, NoTBM, HasEGPR] in { + def : Pat<(and GR64:$src, AndMask64:$mask), + (BEXTR64rr_EVEX GR64:$src, + (SUBREG_TO_REG (i64 0), + (MOV32ri (BEXTRMaskXForm imm:$mask)), sub_32bit))>; + def : Pat<(and (loadi64 addr:$src), AndMask64:$mask), + (BEXTR64rm_EVEX addr:$src, + (SUBREG_TO_REG (i64 0), + (MOV32ri (BEXTRMaskXForm imm:$mask)), sub_32bit))>; +} + // Use BZHI for 64-bit 'and' with large immediate 'mask'. -let Predicates = [HasBMI2, NoTBM] in { +let Predicates = [HasBMI2, NoTBM, NoEGPR] in { def : Pat<(and GR64:$src, AndMask64:$mask), (BZHI64rr GR64:$src, (INSERT_SUBREG (i64 (IMPLICIT_DEF)), @@ -1347,39 +1364,41 @@ let Predicates = [HasBMI2, NoTBM] in { (MOV8ri (CountTrailingOnes imm:$mask)), sub_8bit))>; } -multiclass bmi_pdep_pext { - def rr#Suffix : I<0xF5, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2), - !strconcat(mnemonic, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"), - [(set RC:$dst, (OpNode RC:$src1, RC:$src2))]>, - NoCD8, VVVV, Sched<[WriteALU]>; - def rm#Suffix : I<0xF5, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2), - !strconcat(mnemonic, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"), - [(set RC:$dst, (OpNode RC:$src1, (ld_frag addr:$src2)))]>, - NoCD8, VVVV, Sched<[WriteALU.Folded, WriteALU.ReadAfterFold]>; +let Predicates = [HasBMI2, NoTBM, HasEGPR] in { + def : Pat<(and GR64:$src, AndMask64:$mask), + (BZHI64rr_EVEX GR64:$src, + (INSERT_SUBREG (i64 (IMPLICIT_DEF)), + (MOV8ri (CountTrailingOnes imm:$mask)), sub_8bit))>; + def : Pat<(and (loadi64 addr:$src), AndMask64:$mask), + (BZHI64rm_EVEX addr:$src, + (INSERT_SUBREG (i64 (IMPLICIT_DEF)), + (MOV8ri (CountTrailingOnes imm:$mask)), sub_8bit))>; +} + +multiclass PdepPext { + def rr#suffix : ITy<0xF5, MRMSrcReg, t, (outs t.RegClass:$dst), + (ins t.RegClass:$src1, t.RegClass:$src2), m, binop_ndd_args, + [(set t.RegClass:$dst, (node t.RegClass:$src1, t.RegClass:$src2))]>, + T8, VVVV, Sched<[WriteALU]>; + def rm#suffix : ITy<0xF5, MRMSrcMem, t, (outs t.RegClass:$dst), + (ins t.RegClass:$src1, t.MemOperand:$src2), m, binop_ndd_args, + [(set t.RegClass:$dst, (node t.RegClass:$src1, (t.LoadNode addr:$src2)))]>, + T8, VVVV, Sched<[WriteALU.Folded, WriteALU.ReadAfterFold]>; } let Predicates = [HasBMI2, NoEGPR] in { - defm PDEP32 : bmi_pdep_pext<"pdep{l}", GR32, i32mem, - X86pdep, loadi32>, T8, XD, VEX; - defm PDEP64 : bmi_pdep_pext<"pdep{q}", GR64, i64mem, - X86pdep, loadi64>, T8, XD, REX_W, VEX; - defm PEXT32 : bmi_pdep_pext<"pext{l}", GR32, i32mem, - X86pext, loadi32>, T8, XS, VEX; - defm PEXT64 : bmi_pdep_pext<"pext{q}", GR64, i64mem, - X86pext, loadi64>, T8, XS, REX_W, VEX; + defm PDEP32 : PdepPext<"pdep", Xi32, X86pdep>, XD, VEX; + defm PDEP64 : PdepPext<"pdep", Xi64, X86pdep>, XD, REX_W, VEX; + defm PEXT32 : PdepPext<"pext", Xi32, X86pext>, XS, VEX; + defm PEXT64 : PdepPext<"pext", Xi64, X86pext>, XS, REX_W, VEX; } let Predicates = [HasBMI2, HasEGPR] in { - defm PDEP32 : bmi_pdep_pext<"pdep{l}", GR32, i32mem, - X86pdep, loadi32, "_EVEX">, T8, XD, EVEX; - defm PDEP64 : bmi_pdep_pext<"pdep{q}", GR64, i64mem, - X86pdep, loadi64, "_EVEX">, T8, XD, REX_W, EVEX; - defm PEXT32 : bmi_pdep_pext<"pext{l}", GR32, i32mem, - X86pext, loadi32, "_EVEX">, T8, XS, EVEX; - defm PEXT64 : bmi_pdep_pext<"pext{q}", GR64, i64mem, - X86pext, loadi64, "_EVEX">, T8, XS, REX_W, EVEX; + defm PDEP32 : PdepPext<"pdep", Xi32, X86pdep, "_EVEX">, XD, EVEX; + defm PDEP64 : PdepPext<"pdep", Xi64, X86pdep, "_EVEX">, XD, REX_W, EVEX; + defm PEXT32 : PdepPext<"pext", Xi32, X86pext, "_EVEX">, XS, EVEX; + defm PEXT64 : PdepPext<"pext", Xi64, X86pext, "_EVEX">, XS, REX_W, EVEX; } //===----------------------------------------------------------------------===// diff --git a/llvm/lib/Target/X86/X86InstrSSE.td b/llvm/lib/Target/X86/X86InstrSSE.td index e8a1a2b8388..7d94fec9a35 100644 --- a/llvm/lib/Target/X86/X86InstrSSE.td +++ b/llvm/lib/Target/X86/X86InstrSSE.td @@ -6663,14 +6663,14 @@ let Defs = [ECX, EFLAGS], Uses = [EAX, EDX], hasSideEffects = 0 in { class Crc32r : ITy<0xF1, MRMSrcReg, t, (outs rc:$dst), (ins rc:$src1, t.RegClass:$src2), "crc32", binop_args, [(set rc:$dst, (node rc:$src1, t.RegClass:$src2))]>, - Sched<[WriteCRC32]>, NoCD8 { + Sched<[WriteCRC32]> { let Constraints = "$src1 = $dst"; } class Crc32m : ITy<0xF1, MRMSrcMem, t, (outs rc:$dst), (ins rc:$src1, t.MemOperand:$src2), "crc32", binop_args, [(set rc:$dst, (node rc:$src1, (load addr:$src2)))]>, - Sched<[WriteCRC32.Folded, WriteCRC32.ReadAfterFold]>, NoCD8 { + Sched<[WriteCRC32.Folded, WriteCRC32.ReadAfterFold]> { let Constraints = "$src1 = $dst"; } @@ -8331,6 +8331,10 @@ let Predicates = [HasAVXNECONVERT] in { f256mem>, T8; defm VCVTNEPS2BF16 : VCVTNEPS2BF16_BASE, VEX, T8, XS, ExplicitVEXPrefix; + def : Pat<(v8bf16 (X86cvtneps2bf16 (v4f32 VR128X:$src))), + (VCVTNEPS2BF16rr VR128:$src)>; + def : Pat<(v8bf16 (X86cvtneps2bf16 (loadv4f32 addr:$src))), + (VCVTNEPS2BF16rm addr:$src)>; def : Pat<(v8bf16 (X86vfpround (v8f32 VR256:$src))), (VCVTNEPS2BF16Yrr VR256:$src)>; def : Pat<(v8bf16 (X86vfpround (loadv8f32 addr:$src))), diff --git a/llvm/lib/Target/X86/X86InstrShiftRotate.td b/llvm/lib/Target/X86/X86InstrShiftRotate.td index f951894db18..2a5488847e6 100644 --- a/llvm/lib/Target/X86/X86InstrShiftRotate.td +++ b/llvm/lib/Target/X86/X86InstrShiftRotate.td @@ -10,767 +10,256 @@ // //===----------------------------------------------------------------------===// -// FIXME: Someone needs to smear multipattern goodness all over this file. - -let Defs = [EFLAGS], hasSideEffects = 0 in { - -let Constraints = "$src1 = $dst" in { -let Uses = [CL], SchedRW = [WriteShiftCL] in { -def SHL8rCL : I<0xD2, MRM4r, (outs GR8 :$dst), (ins GR8 :$src1), - "shl{b}\t{%cl, $dst|$dst, cl}", - [(set GR8:$dst, (shl GR8:$src1, CL))]>; -def SHL16rCL : I<0xD3, MRM4r, (outs GR16:$dst), (ins GR16:$src1), - "shl{w}\t{%cl, $dst|$dst, cl}", - [(set GR16:$dst, (shl GR16:$src1, CL))]>, OpSize16; -def SHL32rCL : I<0xD3, MRM4r, (outs GR32:$dst), (ins GR32:$src1), - "shl{l}\t{%cl, $dst|$dst, cl}", - [(set GR32:$dst, (shl GR32:$src1, CL))]>, OpSize32; -def SHL64rCL : RI<0xD3, MRM4r, (outs GR64:$dst), (ins GR64:$src1), - "shl{q}\t{%cl, $dst|$dst, cl}", - [(set GR64:$dst, (shl GR64:$src1, CL))]>; -} // Uses = [CL], SchedRW - -let SchedRW = [WriteShift] in { -let isConvertibleToThreeAddress = 1 in { // Can transform into LEA. -def SHL8ri : Ii8<0xC0, MRM4r, (outs GR8 :$dst), (ins GR8 :$src1, u8imm:$src2), - "shl{b}\t{$src2, $dst|$dst, $src2}", - [(set GR8:$dst, (shl GR8:$src1, (i8 imm:$src2)))]>; - -def SHL16ri : Ii8<0xC1, MRM4r, (outs GR16:$dst), (ins GR16:$src1, u8imm:$src2), - "shl{w}\t{$src2, $dst|$dst, $src2}", - [(set GR16:$dst, (shl GR16:$src1, (i8 imm:$src2)))]>, - OpSize16; -def SHL32ri : Ii8<0xC1, MRM4r, (outs GR32:$dst), (ins GR32:$src1, u8imm:$src2), - "shl{l}\t{$src2, $dst|$dst, $src2}", - [(set GR32:$dst, (shl GR32:$src1, (i8 imm:$src2)))]>, - OpSize32; -def SHL64ri : RIi8<0xC1, MRM4r, (outs GR64:$dst), - (ins GR64:$src1, u8imm:$src2), - "shl{q}\t{$src2, $dst|$dst, $src2}", - [(set GR64:$dst, (shl GR64:$src1, (i8 imm:$src2)))]>; -} // isConvertibleToThreeAddress = 1 - -def SHL8r1 : I<0xD0, MRM4r, (outs GR8:$dst), (ins GR8:$src1), - "shl{b}\t$dst", []>; -def SHL16r1 : I<0xD1, MRM4r, (outs GR16:$dst), (ins GR16:$src1), - "shl{w}\t$dst", []>, OpSize16; -def SHL32r1 : I<0xD1, MRM4r, (outs GR32:$dst), (ins GR32:$src1), - "shl{l}\t$dst", []>, OpSize32; -def SHL64r1 : RI<0xD1, MRM4r, (outs GR64:$dst), (ins GR64:$src1), - "shl{q}\t$dst", []>; -} // SchedRW -} // Constraints = "$src = $dst" - -// FIXME: Why do we need an explicit "Uses = [CL]" when the instr has a pattern -// using CL? -let Uses = [CL], SchedRW = [WriteShiftCLLd, WriteRMW] in { -def SHL8mCL : I<0xD2, MRM4m, (outs), (ins i8mem :$dst), - "shl{b}\t{%cl, $dst|$dst, cl}", - [(store (shl (loadi8 addr:$dst), CL), addr:$dst)]>; -def SHL16mCL : I<0xD3, MRM4m, (outs), (ins i16mem:$dst), - "shl{w}\t{%cl, $dst|$dst, cl}", - [(store (shl (loadi16 addr:$dst), CL), addr:$dst)]>, - OpSize16; -def SHL32mCL : I<0xD3, MRM4m, (outs), (ins i32mem:$dst), - "shl{l}\t{%cl, $dst|$dst, cl}", - [(store (shl (loadi32 addr:$dst), CL), addr:$dst)]>, - OpSize32; -def SHL64mCL : RI<0xD3, MRM4m, (outs), (ins i64mem:$dst), - "shl{q}\t{%cl, $dst|$dst, cl}", - [(store (shl (loadi64 addr:$dst), CL), addr:$dst)]>, - Requires<[In64BitMode]>; -} // Uses, SchedRW - -let SchedRW = [WriteShiftLd, WriteRMW], mayLoad = 1, mayStore = 1 in { -def SHL8mi : Ii8<0xC0, MRM4m, (outs), (ins i8mem :$dst, u8imm:$src), - "shl{b}\t{$src, $dst|$dst, $src}", - [(store (shl (loadi8 addr:$dst), (i8 imm:$src)), addr:$dst)]>; -def SHL16mi : Ii8<0xC1, MRM4m, (outs), (ins i16mem:$dst, u8imm:$src), - "shl{w}\t{$src, $dst|$dst, $src}", - [(store (shl (loadi16 addr:$dst), (i8 imm:$src)), addr:$dst)]>, - OpSize16; -def SHL32mi : Ii8<0xC1, MRM4m, (outs), (ins i32mem:$dst, u8imm:$src), - "shl{l}\t{$src, $dst|$dst, $src}", - [(store (shl (loadi32 addr:$dst), (i8 imm:$src)), addr:$dst)]>, - OpSize32; -def SHL64mi : RIi8<0xC1, MRM4m, (outs), (ins i64mem:$dst, u8imm:$src), - "shl{q}\t{$src, $dst|$dst, $src}", - [(store (shl (loadi64 addr:$dst), (i8 imm:$src)), addr:$dst)]>, - Requires<[In64BitMode]>; - -// Shift by 1 -def SHL8m1 : I<0xD0, MRM4m, (outs), (ins i8mem :$dst), - "shl{b}\t$dst", []>; -def SHL16m1 : I<0xD1, MRM4m, (outs), (ins i16mem:$dst), - "shl{w}\t$dst", []>, OpSize16; -def SHL32m1 : I<0xD1, MRM4m, (outs), (ins i32mem:$dst), - "shl{l}\t$dst", []>, OpSize32; -def SHL64m1 : RI<0xD1, MRM4m, (outs), (ins i64mem:$dst), - "shl{q}\t$dst", []>, Requires<[In64BitMode]>; -} // SchedRW, mayLoad, mayStore - -let Constraints = "$src1 = $dst" in { -let Uses = [CL], SchedRW = [WriteShiftCL] in { -def SHR8rCL : I<0xD2, MRM5r, (outs GR8 :$dst), (ins GR8 :$src1), - "shr{b}\t{%cl, $dst|$dst, cl}", - [(set GR8:$dst, (srl GR8:$src1, CL))]>; -def SHR16rCL : I<0xD3, MRM5r, (outs GR16:$dst), (ins GR16:$src1), - "shr{w}\t{%cl, $dst|$dst, cl}", - [(set GR16:$dst, (srl GR16:$src1, CL))]>, OpSize16; -def SHR32rCL : I<0xD3, MRM5r, (outs GR32:$dst), (ins GR32:$src1), - "shr{l}\t{%cl, $dst|$dst, cl}", - [(set GR32:$dst, (srl GR32:$src1, CL))]>, OpSize32; -def SHR64rCL : RI<0xD3, MRM5r, (outs GR64:$dst), (ins GR64:$src1), - "shr{q}\t{%cl, $dst|$dst, cl}", - [(set GR64:$dst, (srl GR64:$src1, CL))]>; -} // Uses, SchedRW - -let SchedRW = [WriteShift] in { -def SHR8ri : Ii8<0xC0, MRM5r, (outs GR8:$dst), (ins GR8:$src1, u8imm:$src2), - "shr{b}\t{$src2, $dst|$dst, $src2}", - [(set GR8:$dst, (srl GR8:$src1, (i8 imm:$src2)))]>; -def SHR16ri : Ii8<0xC1, MRM5r, (outs GR16:$dst), (ins GR16:$src1, u8imm:$src2), - "shr{w}\t{$src2, $dst|$dst, $src2}", - [(set GR16:$dst, (srl GR16:$src1, (i8 imm:$src2)))]>, - OpSize16; -def SHR32ri : Ii8<0xC1, MRM5r, (outs GR32:$dst), (ins GR32:$src1, u8imm:$src2), - "shr{l}\t{$src2, $dst|$dst, $src2}", - [(set GR32:$dst, (srl GR32:$src1, (i8 imm:$src2)))]>, - OpSize32; -def SHR64ri : RIi8<0xC1, MRM5r, (outs GR64:$dst), (ins GR64:$src1, u8imm:$src2), - "shr{q}\t{$src2, $dst|$dst, $src2}", - [(set GR64:$dst, (srl GR64:$src1, (i8 imm:$src2)))]>; - -// Shift right by 1 -def SHR8r1 : I<0xD0, MRM5r, (outs GR8:$dst), (ins GR8:$src1), - "shr{b}\t$dst", []>; -def SHR16r1 : I<0xD1, MRM5r, (outs GR16:$dst), (ins GR16:$src1), - "shr{w}\t$dst", []>, OpSize16; -def SHR32r1 : I<0xD1, MRM5r, (outs GR32:$dst), (ins GR32:$src1), - "shr{l}\t$dst", []>, OpSize32; -def SHR64r1 : RI<0xD1, MRM5r, (outs GR64:$dst), (ins GR64:$src1), - "shr{q}\t$dst", []>; -} // SchedRW -} // Constraints = "$src = $dst" - - -let Uses = [CL], SchedRW = [WriteShiftCLLd, WriteRMW] in { -def SHR8mCL : I<0xD2, MRM5m, (outs), (ins i8mem :$dst), - "shr{b}\t{%cl, $dst|$dst, cl}", - [(store (srl (loadi8 addr:$dst), CL), addr:$dst)]>; -def SHR16mCL : I<0xD3, MRM5m, (outs), (ins i16mem:$dst), - "shr{w}\t{%cl, $dst|$dst, cl}", - [(store (srl (loadi16 addr:$dst), CL), addr:$dst)]>, - OpSize16; -def SHR32mCL : I<0xD3, MRM5m, (outs), (ins i32mem:$dst), - "shr{l}\t{%cl, $dst|$dst, cl}", - [(store (srl (loadi32 addr:$dst), CL), addr:$dst)]>, - OpSize32; -def SHR64mCL : RI<0xD3, MRM5m, (outs), (ins i64mem:$dst), - "shr{q}\t{%cl, $dst|$dst, cl}", - [(store (srl (loadi64 addr:$dst), CL), addr:$dst)]>, - Requires<[In64BitMode]>; -} // Uses, SchedRW - -let SchedRW = [WriteShiftLd, WriteRMW], mayLoad = 1, mayStore = 1 in { -def SHR8mi : Ii8<0xC0, MRM5m, (outs), (ins i8mem :$dst, u8imm:$src), - "shr{b}\t{$src, $dst|$dst, $src}", - [(store (srl (loadi8 addr:$dst), (i8 imm:$src)), addr:$dst)]>; -def SHR16mi : Ii8<0xC1, MRM5m, (outs), (ins i16mem:$dst, u8imm:$src), - "shr{w}\t{$src, $dst|$dst, $src}", - [(store (srl (loadi16 addr:$dst), (i8 imm:$src)), addr:$dst)]>, - OpSize16; -def SHR32mi : Ii8<0xC1, MRM5m, (outs), (ins i32mem:$dst, u8imm:$src), - "shr{l}\t{$src, $dst|$dst, $src}", - [(store (srl (loadi32 addr:$dst), (i8 imm:$src)), addr:$dst)]>, - OpSize32; -def SHR64mi : RIi8<0xC1, MRM5m, (outs), (ins i64mem:$dst, u8imm:$src), - "shr{q}\t{$src, $dst|$dst, $src}", - [(store (srl (loadi64 addr:$dst), (i8 imm:$src)), addr:$dst)]>, - Requires<[In64BitMode]>; - -// Shift by 1 -def SHR8m1 : I<0xD0, MRM5m, (outs), (ins i8mem :$dst), - "shr{b}\t$dst", []>; -def SHR16m1 : I<0xD1, MRM5m, (outs), (ins i16mem:$dst), - "shr{w}\t$dst", []>, OpSize16; -def SHR32m1 : I<0xD1, MRM5m, (outs), (ins i32mem:$dst), - "shr{l}\t$dst", []>, OpSize32; -def SHR64m1 : RI<0xD1, MRM5m, (outs), (ins i64mem:$dst), - "shr{q}\t$dst", []>, Requires<[In64BitMode]>; -} // SchedRW, mayLoad, mayStore - - -let Constraints = "$src1 = $dst" in { -let Uses = [CL], SchedRW = [WriteShiftCL] in { -def SAR8rCL : I<0xD2, MRM7r, (outs GR8 :$dst), (ins GR8 :$src1), - "sar{b}\t{%cl, $dst|$dst, cl}", - [(set GR8:$dst, (sra GR8:$src1, CL))]>; -def SAR16rCL : I<0xD3, MRM7r, (outs GR16:$dst), (ins GR16:$src1), - "sar{w}\t{%cl, $dst|$dst, cl}", - [(set GR16:$dst, (sra GR16:$src1, CL))]>, - OpSize16; -def SAR32rCL : I<0xD3, MRM7r, (outs GR32:$dst), (ins GR32:$src1), - "sar{l}\t{%cl, $dst|$dst, cl}", - [(set GR32:$dst, (sra GR32:$src1, CL))]>, - OpSize32; -def SAR64rCL : RI<0xD3, MRM7r, (outs GR64:$dst), (ins GR64:$src1), - "sar{q}\t{%cl, $dst|$dst, cl}", - [(set GR64:$dst, (sra GR64:$src1, CL))]>; -} // Uses, SchedRW - -let SchedRW = [WriteShift] in { -def SAR8ri : Ii8<0xC0, MRM7r, (outs GR8 :$dst), (ins GR8 :$src1, u8imm:$src2), - "sar{b}\t{$src2, $dst|$dst, $src2}", - [(set GR8:$dst, (sra GR8:$src1, (i8 imm:$src2)))]>; -def SAR16ri : Ii8<0xC1, MRM7r, (outs GR16:$dst), (ins GR16:$src1, u8imm:$src2), - "sar{w}\t{$src2, $dst|$dst, $src2}", - [(set GR16:$dst, (sra GR16:$src1, (i8 imm:$src2)))]>, - OpSize16; -def SAR32ri : Ii8<0xC1, MRM7r, (outs GR32:$dst), (ins GR32:$src1, u8imm:$src2), - "sar{l}\t{$src2, $dst|$dst, $src2}", - [(set GR32:$dst, (sra GR32:$src1, (i8 imm:$src2)))]>, - OpSize32; -def SAR64ri : RIi8<0xC1, MRM7r, (outs GR64:$dst), - (ins GR64:$src1, u8imm:$src2), - "sar{q}\t{$src2, $dst|$dst, $src2}", - [(set GR64:$dst, (sra GR64:$src1, (i8 imm:$src2)))]>; - -// Shift by 1 -def SAR8r1 : I<0xD0, MRM7r, (outs GR8 :$dst), (ins GR8 :$src1), - "sar{b}\t$dst", []>; -def SAR16r1 : I<0xD1, MRM7r, (outs GR16:$dst), (ins GR16:$src1), - "sar{w}\t$dst", []>, OpSize16; -def SAR32r1 : I<0xD1, MRM7r, (outs GR32:$dst), (ins GR32:$src1), - "sar{l}\t$dst", []>, OpSize32; -def SAR64r1 : RI<0xD1, MRM7r, (outs GR64:$dst), (ins GR64:$src1), - "sar{q}\t$dst", []>; -} // SchedRW -} // Constraints = "$src = $dst" - - -let Uses = [CL], SchedRW = [WriteShiftCLLd, WriteRMW] in { -def SAR8mCL : I<0xD2, MRM7m, (outs), (ins i8mem :$dst), - "sar{b}\t{%cl, $dst|$dst, cl}", - [(store (sra (loadi8 addr:$dst), CL), addr:$dst)]>; -def SAR16mCL : I<0xD3, MRM7m, (outs), (ins i16mem:$dst), - "sar{w}\t{%cl, $dst|$dst, cl}", - [(store (sra (loadi16 addr:$dst), CL), addr:$dst)]>, - OpSize16; -def SAR32mCL : I<0xD3, MRM7m, (outs), (ins i32mem:$dst), - "sar{l}\t{%cl, $dst|$dst, cl}", - [(store (sra (loadi32 addr:$dst), CL), addr:$dst)]>, - OpSize32; -def SAR64mCL : RI<0xD3, MRM7m, (outs), (ins i64mem:$dst), - "sar{q}\t{%cl, $dst|$dst, cl}", - [(store (sra (loadi64 addr:$dst), CL), addr:$dst)]>, - Requires<[In64BitMode]>; -} // Uses, SchedRW - -let SchedRW = [WriteShiftLd, WriteRMW], mayLoad = 1, mayStore = 1 in { -def SAR8mi : Ii8<0xC0, MRM7m, (outs), (ins i8mem :$dst, u8imm:$src), - "sar{b}\t{$src, $dst|$dst, $src}", - [(store (sra (loadi8 addr:$dst), (i8 imm:$src)), addr:$dst)]>; -def SAR16mi : Ii8<0xC1, MRM7m, (outs), (ins i16mem:$dst, u8imm:$src), - "sar{w}\t{$src, $dst|$dst, $src}", - [(store (sra (loadi16 addr:$dst), (i8 imm:$src)), addr:$dst)]>, - OpSize16; -def SAR32mi : Ii8<0xC1, MRM7m, (outs), (ins i32mem:$dst, u8imm:$src), - "sar{l}\t{$src, $dst|$dst, $src}", - [(store (sra (loadi32 addr:$dst), (i8 imm:$src)), addr:$dst)]>, - OpSize32; -def SAR64mi : RIi8<0xC1, MRM7m, (outs), (ins i64mem:$dst, u8imm:$src), - "sar{q}\t{$src, $dst|$dst, $src}", - [(store (sra (loadi64 addr:$dst), (i8 imm:$src)), addr:$dst)]>, - Requires<[In64BitMode]>; - -// Shift by 1 -def SAR8m1 : I<0xD0, MRM7m, (outs), (ins i8mem :$dst), - "sar{b}\t$dst", []>; -def SAR16m1 : I<0xD1, MRM7m, (outs), (ins i16mem:$dst), - "sar{w}\t$dst", []>, OpSize16; -def SAR32m1 : I<0xD1, MRM7m, (outs), (ins i32mem:$dst), - "sar{l}\t$dst", []>, OpSize32; -def SAR64m1 : RI<0xD1, MRM7m, (outs), (ins i64mem:$dst), - "sar{q}\t$dst", []>, Requires<[In64BitMode]>; -} // SchedRW - //===----------------------------------------------------------------------===// -// Rotate instructions +// Shift/Rotate instructions //===----------------------------------------------------------------------===// -let Constraints = "$src1 = $dst" in { +multiclass ShiftRotate uses = []> { -let Uses = [CL, EFLAGS], SchedRW = [WriteRotateCL] in { -def RCL8rCL : I<0xD2, MRM2r, (outs GR8:$dst), (ins GR8:$src1), - "rcl{b}\t{%cl, $dst|$dst, cl}", []>; -def RCL16rCL : I<0xD3, MRM2r, (outs GR16:$dst), (ins GR16:$src1), - "rcl{w}\t{%cl, $dst|$dst, cl}", []>, OpSize16; -def RCL32rCL : I<0xD3, MRM2r, (outs GR32:$dst), (ins GR32:$src1), - "rcl{l}\t{%cl, $dst|$dst, cl}", []>, OpSize32; -def RCL64rCL : RI<0xD3, MRM2r, (outs GR64:$dst), (ins GR64:$src1), - "rcl{q}\t{%cl, $dst|$dst, cl}", []>; -} // Uses = [CL, EFLAGS], SchedRW + let Uses = uses in { + let isConvertibleToThreeAddress = !if(!eq(m, "shl"), 1, 0) in { + let Predicates = [NoNDD] in { + def 8ri : BinOpRI8U_R, Sched<[ri]>, DefEFLAGS; + def 16ri : BinOpRI8U_R, Sched<[ri]>, DefEFLAGS, OpSize16; + def 32ri : BinOpRI8U_R, Sched<[ri]>, DefEFLAGS, OpSize32; + def 64ri : BinOpRI8U_R, Sched<[ri]>, DefEFLAGS; + } + let Predicates = [HasNDD, In64BitMode] in { + def 8ri_ND : BinOpRI8U_R, Sched<[ri]>, DefEFLAGS; + def 16ri_ND : BinOpRI8U_R, Sched<[ri]>, DefEFLAGS, PD; + def 32ri_ND : BinOpRI8U_R, Sched<[ri]>, DefEFLAGS; + def 64ri_ND : BinOpRI8U_R, Sched<[ri]>, DefEFLAGS; + } + let Predicates = [In64BitMode] in { + def 8ri_EVEX : BinOpRI8U_R, Sched<[ri]>, DefEFLAGS, PL; + def 16ri_EVEX : BinOpRI8U_R, Sched<[ri]>, DefEFLAGS, PL, PD; + def 32ri_EVEX : BinOpRI8U_R, Sched<[ri]>, DefEFLAGS, PL; + def 64ri_EVEX : BinOpRI8U_R, Sched<[ri]>, DefEFLAGS, PL; + } + } -let Uses = [EFLAGS], SchedRW = [WriteRotate] in { -def RCL8r1 : I<0xD0, MRM2r, (outs GR8:$dst), (ins GR8:$src1), - "rcl{b}\t$dst", []>; -def RCL8ri : Ii8<0xC0, MRM2r, (outs GR8:$dst), (ins GR8:$src1, u8imm:$cnt), - "rcl{b}\t{$cnt, $dst|$dst, $cnt}", []>; -def RCL16r1 : I<0xD1, MRM2r, (outs GR16:$dst), (ins GR16:$src1), - "rcl{w}\t$dst", []>, OpSize16; -def RCL16ri : Ii8<0xC1, MRM2r, (outs GR16:$dst), (ins GR16:$src1, u8imm:$cnt), - "rcl{w}\t{$cnt, $dst|$dst, $cnt}", []>, OpSize16; -def RCL32r1 : I<0xD1, MRM2r, (outs GR32:$dst), (ins GR32:$src1), - "rcl{l}\t$dst", []>, OpSize32; -def RCL32ri : Ii8<0xC1, MRM2r, (outs GR32:$dst), (ins GR32:$src1, u8imm:$cnt), - "rcl{l}\t{$cnt, $dst|$dst, $cnt}", []>, OpSize32; -def RCL64r1 : RI<0xD1, MRM2r, (outs GR64:$dst), (ins GR64:$src1), - "rcl{q}\t$dst", []>; -def RCL64ri : RIi8<0xC1, MRM2r, (outs GR64:$dst), (ins GR64:$src1, u8imm:$cnt), - "rcl{q}\t{$cnt, $dst|$dst, $cnt}", []>; -} // Uses = [EFLAGS], SchedRW + def 8mi : BinOpMI8U_M, Sched<[mi, WriteRMW]>, DefEFLAGS; + def 16mi : BinOpMI8U_M, Sched<[mi, WriteRMW]>, DefEFLAGS, OpSize16; + def 32mi : BinOpMI8U_M, Sched<[mi, WriteRMW]>, DefEFLAGS, OpSize32; + def 64mi : BinOpMI8U_M, Sched<[mi, WriteRMW]>, DefEFLAGS, Requires<[In64BitMode]>; + let Predicates = [HasNDD, In64BitMode] in { + def 8mi_ND : BinOpMI8U_R, Sched<[mi, ri]>, DefEFLAGS; + def 16mi_ND : BinOpMI8U_R, Sched<[mi, ri]>, DefEFLAGS, PD; + def 32mi_ND : BinOpMI8U_R, Sched<[mi, ri]>, DefEFLAGS; + def 64mi_ND : BinOpMI8U_R, Sched<[mi, ri]>, DefEFLAGS; + } + let Predicates = [In64BitMode] in { + def 8mi_EVEX : BinOpMI8U_M, Sched<[mi, WriteRMW]>, DefEFLAGS, PL; + def 16mi_EVEX : BinOpMI8U_M, Sched<[mi, WriteRMW]>, DefEFLAGS, PL, PD; + def 32mi_EVEX : BinOpMI8U_M, Sched<[mi, WriteRMW]>, DefEFLAGS, PL; + def 64mi_EVEX : BinOpMI8U_M, Sched<[mi, WriteRMW]>, DefEFLAGS, PL; + } -let Uses = [CL, EFLAGS], SchedRW = [WriteRotateCL] in { -def RCR8rCL : I<0xD2, MRM3r, (outs GR8:$dst), (ins GR8:$src1), - "rcr{b}\t{%cl, $dst|$dst, cl}", []>; -def RCR16rCL : I<0xD3, MRM3r, (outs GR16:$dst), (ins GR16:$src1), - "rcr{w}\t{%cl, $dst|$dst, cl}", []>, OpSize16; -def RCR32rCL : I<0xD3, MRM3r, (outs GR32:$dst), (ins GR32:$src1), - "rcr{l}\t{%cl, $dst|$dst, cl}", []>, OpSize32; -def RCR64rCL : RI<0xD3, MRM3r, (outs GR64:$dst), (ins GR64:$src1), - "rcr{q}\t{%cl, $dst|$dst, cl}", []>; -} // Uses = [CL, EFLAGS], SchedRW + let SchedRW = [ri] in { + def 8r1 : UnaryOpR_RF<0xD1, RegMRM, m, Xi8>; + def 16r1 : UnaryOpR_RF<0xD1, RegMRM, m, Xi16>, OpSize16; + def 32r1 : UnaryOpR_RF<0xD1, RegMRM, m, Xi32>, OpSize32; + def 64r1 : UnaryOpR_RF<0xD1, RegMRM, m, Xi64>; -let Uses = [EFLAGS], SchedRW = [WriteRotate] in { -def RCR8r1 : I<0xD0, MRM3r, (outs GR8:$dst), (ins GR8:$src1), - "rcr{b}\t$dst", []>; -def RCR8ri : Ii8<0xC0, MRM3r, (outs GR8:$dst), (ins GR8:$src1, u8imm:$cnt), - "rcr{b}\t{$cnt, $dst|$dst, $cnt}", []>; -def RCR16r1 : I<0xD1, MRM3r, (outs GR16:$dst), (ins GR16:$src1), - "rcr{w}\t$dst", []>, OpSize16; -def RCR16ri : Ii8<0xC1, MRM3r, (outs GR16:$dst), (ins GR16:$src1, u8imm:$cnt), - "rcr{w}\t{$cnt, $dst|$dst, $cnt}", []>, OpSize16; -def RCR32r1 : I<0xD1, MRM3r, (outs GR32:$dst), (ins GR32:$src1), - "rcr{l}\t$dst", []>, OpSize32; -def RCR32ri : Ii8<0xC1, MRM3r, (outs GR32:$dst), (ins GR32:$src1, u8imm:$cnt), - "rcr{l}\t{$cnt, $dst|$dst, $cnt}", []>, OpSize32; -def RCR64r1 : RI<0xD1, MRM3r, (outs GR64:$dst), (ins GR64:$src1), - "rcr{q}\t$dst", []>; -def RCR64ri : RIi8<0xC1, MRM3r, (outs GR64:$dst), (ins GR64:$src1, u8imm:$cnt), - "rcr{q}\t{$cnt, $dst|$dst, $cnt}", []>; -} // Uses = [EFLAGS], SchedRW -} // Constraints = "$src = $dst" + // FIXME: Assembler can't tell whether it's 8r1_ND or 8rCL when the source register is cl, e.g. + // + // shlb %cl, %al + // + // GNU binutils distinguish them by adding an explicit $1 to asm string of 8r1_ND. But we haven't support + // constant immediate in asm string for X86 in TD. So we add DisassembleOnly for 8r1_ND for the time being. + let Predicates = [In64BitMode] in { + def 8r1_ND : UnaryOpR_RF<0xD1, RegMRM, m, Xi8, null_frag, 1>, DisassembleOnly; + def 16r1_ND : UnaryOpR_RF<0xD1, RegMRM, m, Xi16, null_frag, 1>, PD; + def 32r1_ND : UnaryOpR_RF<0xD1, RegMRM, m, Xi32, null_frag, 1>; + def 64r1_ND : UnaryOpR_RF<0xD1, RegMRM, m, Xi64, null_frag, 1>; -let mayLoad = 1, mayStore = 1 in { -let Uses = [EFLAGS], SchedRW = [WriteRotateLd, WriteRMW] in { -def RCL8m1 : I<0xD0, MRM2m, (outs), (ins i8mem:$dst), - "rcl{b}\t$dst", []>; -def RCL8mi : Ii8<0xC0, MRM2m, (outs), (ins i8mem:$dst, u8imm:$cnt), - "rcl{b}\t{$cnt, $dst|$dst, $cnt}", []>; -def RCL16m1 : I<0xD1, MRM2m, (outs), (ins i16mem:$dst), - "rcl{w}\t$dst", []>, OpSize16; -def RCL16mi : Ii8<0xC1, MRM2m, (outs), (ins i16mem:$dst, u8imm:$cnt), - "rcl{w}\t{$cnt, $dst|$dst, $cnt}", []>, OpSize16; -def RCL32m1 : I<0xD1, MRM2m, (outs), (ins i32mem:$dst), - "rcl{l}\t$dst", []>, OpSize32; -def RCL32mi : Ii8<0xC1, MRM2m, (outs), (ins i32mem:$dst, u8imm:$cnt), - "rcl{l}\t{$cnt, $dst|$dst, $cnt}", []>, OpSize32; -def RCL64m1 : RI<0xD1, MRM2m, (outs), (ins i64mem:$dst), - "rcl{q}\t$dst", []>, Requires<[In64BitMode]>; -def RCL64mi : RIi8<0xC1, MRM2m, (outs), (ins i64mem:$dst, u8imm:$cnt), - "rcl{q}\t{$cnt, $dst|$dst, $cnt}", []>, - Requires<[In64BitMode]>; + def 8r1_EVEX : UnaryOpR_RF<0xD1, RegMRM, m, Xi8>, PL; + def 16r1_EVEX : UnaryOpR_RF<0xD1, RegMRM, m, Xi16>, PL, PD; + def 32r1_EVEX : UnaryOpR_RF<0xD1, RegMRM, m, Xi32>, PL; + def 64r1_EVEX : UnaryOpR_RF<0xD1, RegMRM, m, Xi64>, PL; + } + } -def RCR8m1 : I<0xD0, MRM3m, (outs), (ins i8mem:$dst), - "rcr{b}\t$dst", []>; -def RCR8mi : Ii8<0xC0, MRM3m, (outs), (ins i8mem:$dst, u8imm:$cnt), - "rcr{b}\t{$cnt, $dst|$dst, $cnt}", []>; -def RCR16m1 : I<0xD1, MRM3m, (outs), (ins i16mem:$dst), - "rcr{w}\t$dst", []>, OpSize16; -def RCR16mi : Ii8<0xC1, MRM3m, (outs), (ins i16mem:$dst, u8imm:$cnt), - "rcr{w}\t{$cnt, $dst|$dst, $cnt}", []>, OpSize16; -def RCR32m1 : I<0xD1, MRM3m, (outs), (ins i32mem:$dst), - "rcr{l}\t$dst", []>, OpSize32; -def RCR32mi : Ii8<0xC1, MRM3m, (outs), (ins i32mem:$dst, u8imm:$cnt), - "rcr{l}\t{$cnt, $dst|$dst, $cnt}", []>, OpSize32; -def RCR64m1 : RI<0xD1, MRM3m, (outs), (ins i64mem:$dst), - "rcr{q}\t$dst", []>, Requires<[In64BitMode]>; -def RCR64mi : RIi8<0xC1, MRM3m, (outs), (ins i64mem:$dst, u8imm:$cnt), - "rcr{q}\t{$cnt, $dst|$dst, $cnt}", []>, - Requires<[In64BitMode]>; -} // Uses = [EFLAGS], SchedRW + let SchedRW = [mi, WriteRMW] in { + def 8m1 : UnaryOpM_MF<0xD1, MemMRM, m, Xi8>; + def 16m1 : UnaryOpM_MF<0xD1, MemMRM, m, Xi16>, OpSize16; + def 32m1 : UnaryOpM_MF<0xD1, MemMRM, m, Xi32>, OpSize32; + def 64m1 : UnaryOpM_MF<0xD1, MemMRM, m, Xi64>, Requires<[In64BitMode]>; -let Uses = [CL, EFLAGS], SchedRW = [WriteRotateCLLd, WriteRMW] in { -def RCL8mCL : I<0xD2, MRM2m, (outs), (ins i8mem:$dst), - "rcl{b}\t{%cl, $dst|$dst, cl}", []>; -def RCL16mCL : I<0xD3, MRM2m, (outs), (ins i16mem:$dst), - "rcl{w}\t{%cl, $dst|$dst, cl}", []>, OpSize16; -def RCL32mCL : I<0xD3, MRM2m, (outs), (ins i32mem:$dst), - "rcl{l}\t{%cl, $dst|$dst, cl}", []>, OpSize32; -def RCL64mCL : RI<0xD3, MRM2m, (outs), (ins i64mem:$dst), - "rcl{q}\t{%cl, $dst|$dst, cl}", []>, - Requires<[In64BitMode]>; + let Predicates = [In64BitMode] in { + def 8m1_EVEX : UnaryOpM_MF<0xD1, MemMRM, m, Xi8>, PL; + def 16m1_EVEX : UnaryOpM_MF<0xD1, MemMRM, m, Xi16>, PL, PD; + def 32m1_EVEX : UnaryOpM_MF<0xD1, MemMRM, m, Xi32>, PL; + def 64m1_EVEX : UnaryOpM_MF<0xD1, MemMRM, m, Xi64>, PL; + } + } + let SchedRW = [mi, ri], Predicates = [In64BitMode] in { + def 8m1_ND : UnaryOpM_RF<0xD1, MemMRM, m, Xi8>; + def 16m1_ND : UnaryOpM_RF<0xD1, MemMRM, m, Xi16>, PD; + def 32m1_ND : UnaryOpM_RF<0xD1, MemMRM, m, Xi32>; + def 64m1_ND : UnaryOpM_RF<0xD1, MemMRM, m, Xi64>; + } + } -def RCR8mCL : I<0xD2, MRM3m, (outs), (ins i8mem:$dst), - "rcr{b}\t{%cl, $dst|$dst, cl}", []>; -def RCR16mCL : I<0xD3, MRM3m, (outs), (ins i16mem:$dst), - "rcr{w}\t{%cl, $dst|$dst, cl}", []>, OpSize16; -def RCR32mCL : I<0xD3, MRM3m, (outs), (ins i32mem:$dst), - "rcr{l}\t{%cl, $dst|$dst, cl}", []>, OpSize32; -def RCR64mCL : RI<0xD3, MRM3m, (outs), (ins i64mem:$dst), - "rcr{q}\t{%cl, $dst|$dst, cl}", []>, - Requires<[In64BitMode]>; -} // Uses = [CL, EFLAGS], SchedRW -} // mayLoad, mayStore + let Uses = !listconcat([CL], uses), Defs = [EFLAGS] in { + let Predicates = [NoNDD] in { + def 8rCL : BinOpRC_R, Sched<[rCL]>; + def 16rCL : BinOpRC_R, Sched<[rCL]>, OpSize16; + def 32rCL : BinOpRC_R, Sched<[rCL]>, OpSize32; + def 64rCL : BinOpRC_R, Sched<[rCL]>; + } + let Predicates = [HasNDD, In64BitMode] in { + def 8rCL_ND : BinOpRC_R, Sched<[rCL]>; + def 16rCL_ND : BinOpRC_R, Sched<[rCL]>, PD; + def 32rCL_ND : BinOpRC_R, Sched<[rCL]>; + def 64rCL_ND : BinOpRC_R, Sched<[rCL]>; + } + let Predicates = [In64BitMode] in { + def 8rCL_EVEX : BinOpRC_R, Sched<[rCL]>, PL; + def 16rCL_EVEX : BinOpRC_R, Sched<[rCL]>, PL, PD; + def 32rCL_EVEX : BinOpRC_R, Sched<[rCL]>, PL; + def 64rCL_EVEX : BinOpRC_R, Sched<[rCL]>, PL; + } -let Constraints = "$src1 = $dst" in { -// FIXME: provide shorter instructions when imm8 == 1 -let Uses = [CL], SchedRW = [WriteRotateCL] in { -def ROL8rCL : I<0xD2, MRM0r, (outs GR8 :$dst), (ins GR8 :$src1), - "rol{b}\t{%cl, $dst|$dst, cl}", - [(set GR8:$dst, (rotl GR8:$src1, CL))]>; -def ROL16rCL : I<0xD3, MRM0r, (outs GR16:$dst), (ins GR16:$src1), - "rol{w}\t{%cl, $dst|$dst, cl}", - [(set GR16:$dst, (rotl GR16:$src1, CL))]>, OpSize16; -def ROL32rCL : I<0xD3, MRM0r, (outs GR32:$dst), (ins GR32:$src1), - "rol{l}\t{%cl, $dst|$dst, cl}", - [(set GR32:$dst, (rotl GR32:$src1, CL))]>, OpSize32; -def ROL64rCL : RI<0xD3, MRM0r, (outs GR64:$dst), (ins GR64:$src1), - "rol{q}\t{%cl, $dst|$dst, cl}", - [(set GR64:$dst, (rotl GR64:$src1, CL))]>; -} // Uses, SchedRW + def 8mCL : BinOpMC_M, Sched<[mCL, WriteRMW]>; + def 16mCL : BinOpMC_M, Sched<[mCL, WriteRMW]>, OpSize16; + def 32mCL : BinOpMC_M, Sched<[mCL, WriteRMW]>, OpSize32; + def 64mCL : BinOpMC_M, Sched<[mCL, WriteRMW]>, Requires<[In64BitMode]>; -let SchedRW = [WriteRotate] in { -def ROL8ri : Ii8<0xC0, MRM0r, (outs GR8 :$dst), (ins GR8 :$src1, u8imm:$src2), - "rol{b}\t{$src2, $dst|$dst, $src2}", - [(set GR8:$dst, (rotl GR8:$src1, (i8 imm:$src2)))]>; -def ROL16ri : Ii8<0xC1, MRM0r, (outs GR16:$dst), (ins GR16:$src1, u8imm:$src2), - "rol{w}\t{$src2, $dst|$dst, $src2}", - [(set GR16:$dst, (rotl GR16:$src1, (i8 imm:$src2)))]>, - OpSize16; -def ROL32ri : Ii8<0xC1, MRM0r, (outs GR32:$dst), (ins GR32:$src1, u8imm:$src2), - "rol{l}\t{$src2, $dst|$dst, $src2}", - [(set GR32:$dst, (rotl GR32:$src1, (i8 imm:$src2)))]>, - OpSize32; -def ROL64ri : RIi8<0xC1, MRM0r, (outs GR64:$dst), - (ins GR64:$src1, u8imm:$src2), - "rol{q}\t{$src2, $dst|$dst, $src2}", - [(set GR64:$dst, (rotl GR64:$src1, (i8 imm:$src2)))]>; + let Predicates = [HasNDD, In64BitMode] in { + def 8mCL_ND : BinOpMC_R, Sched<[mCL, rCL]>; + def 16mCL_ND : BinOpMC_R, Sched<[mCL, rCL]>, PD; + def 32mCL_ND : BinOpMC_R, Sched<[mCL, rCL]>; + def 64mCL_ND : BinOpMC_R, Sched<[mCL, rCL]>; + } -// Rotate by 1 -def ROL8r1 : I<0xD0, MRM0r, (outs GR8 :$dst), (ins GR8 :$src1), - "rol{b}\t$dst", []>; -def ROL16r1 : I<0xD1, MRM0r, (outs GR16:$dst), (ins GR16:$src1), - "rol{w}\t$dst", []>, OpSize16; -def ROL32r1 : I<0xD1, MRM0r, (outs GR32:$dst), (ins GR32:$src1), - "rol{l}\t$dst", []>, OpSize32; -def ROL64r1 : RI<0xD1, MRM0r, (outs GR64:$dst), (ins GR64:$src1), - "rol{q}\t$dst", []>; -} // SchedRW -} // Constraints = "$src = $dst" - -let Uses = [CL], SchedRW = [WriteRotateCLLd, WriteRMW] in { -def ROL8mCL : I<0xD2, MRM0m, (outs), (ins i8mem :$dst), - "rol{b}\t{%cl, $dst|$dst, cl}", - [(store (rotl (loadi8 addr:$dst), CL), addr:$dst)]>; -def ROL16mCL : I<0xD3, MRM0m, (outs), (ins i16mem:$dst), - "rol{w}\t{%cl, $dst|$dst, cl}", - [(store (rotl (loadi16 addr:$dst), CL), addr:$dst)]>, OpSize16; -def ROL32mCL : I<0xD3, MRM0m, (outs), (ins i32mem:$dst), - "rol{l}\t{%cl, $dst|$dst, cl}", - [(store (rotl (loadi32 addr:$dst), CL), addr:$dst)]>, OpSize32; -def ROL64mCL : RI<0xD3, MRM0m, (outs), (ins i64mem:$dst), - "rol{q}\t{%cl, $dst|$dst, cl}", - [(store (rotl (loadi64 addr:$dst), CL), addr:$dst)]>, - Requires<[In64BitMode]>; -} // Uses, SchedRW - -let SchedRW = [WriteRotateLd, WriteRMW], mayLoad = 1, mayStore = 1 in { -def ROL8mi : Ii8<0xC0, MRM0m, (outs), (ins i8mem :$dst, u8imm:$src1), - "rol{b}\t{$src1, $dst|$dst, $src1}", - [(store (rotl (loadi8 addr:$dst), (i8 imm:$src1)), addr:$dst)]>; -def ROL16mi : Ii8<0xC1, MRM0m, (outs), (ins i16mem:$dst, u8imm:$src1), - "rol{w}\t{$src1, $dst|$dst, $src1}", - [(store (rotl (loadi16 addr:$dst), (i8 imm:$src1)), addr:$dst)]>, - OpSize16; -def ROL32mi : Ii8<0xC1, MRM0m, (outs), (ins i32mem:$dst, u8imm:$src1), - "rol{l}\t{$src1, $dst|$dst, $src1}", - [(store (rotl (loadi32 addr:$dst), (i8 imm:$src1)), addr:$dst)]>, - OpSize32; -def ROL64mi : RIi8<0xC1, MRM0m, (outs), (ins i64mem:$dst, u8imm:$src1), - "rol{q}\t{$src1, $dst|$dst, $src1}", - [(store (rotl (loadi64 addr:$dst), (i8 imm:$src1)), addr:$dst)]>, - Requires<[In64BitMode]>; - -// Rotate by 1 -def ROL8m1 : I<0xD0, MRM0m, (outs), (ins i8mem :$dst), - "rol{b}\t$dst", []>; -def ROL16m1 : I<0xD1, MRM0m, (outs), (ins i16mem:$dst), - "rol{w}\t$dst", []>, OpSize16; -def ROL32m1 : I<0xD1, MRM0m, (outs), (ins i32mem:$dst), - "rol{l}\t$dst", []>, OpSize32; -def ROL64m1 : RI<0xD1, MRM0m, (outs), (ins i64mem:$dst), - "rol{q}\t$dst", []>, Requires<[In64BitMode]>; -} // SchedRW, mayLoad, mayStore - -let Constraints = "$src1 = $dst" in { -let Uses = [CL], SchedRW = [WriteRotateCL] in { -def ROR8rCL : I<0xD2, MRM1r, (outs GR8 :$dst), (ins GR8 :$src1), - "ror{b}\t{%cl, $dst|$dst, cl}", - [(set GR8:$dst, (rotr GR8:$src1, CL))]>; -def ROR16rCL : I<0xD3, MRM1r, (outs GR16:$dst), (ins GR16:$src1), - "ror{w}\t{%cl, $dst|$dst, cl}", - [(set GR16:$dst, (rotr GR16:$src1, CL))]>, OpSize16; -def ROR32rCL : I<0xD3, MRM1r, (outs GR32:$dst), (ins GR32:$src1), - "ror{l}\t{%cl, $dst|$dst, cl}", - [(set GR32:$dst, (rotr GR32:$src1, CL))]>, OpSize32; -def ROR64rCL : RI<0xD3, MRM1r, (outs GR64:$dst), (ins GR64:$src1), - "ror{q}\t{%cl, $dst|$dst, cl}", - [(set GR64:$dst, (rotr GR64:$src1, CL))]>; + let Predicates = [In64BitMode] in { + def 8mCL_EVEX : BinOpMC_M, Sched<[mCL, WriteRMW]>, PL; + def 16mCL_EVEX : BinOpMC_M, Sched<[mCL, WriteRMW]>, PL, PD; + def 32mCL_EVEX : BinOpMC_M, Sched<[mCL, WriteRMW]>, PL; + def 64mCL_EVEX : BinOpMC_M, Sched<[mCL, WriteRMW]>, PL; + } + } } -let SchedRW = [WriteRotate] in { -def ROR8ri : Ii8<0xC0, MRM1r, (outs GR8 :$dst), (ins GR8 :$src1, u8imm:$src2), - "ror{b}\t{$src2, $dst|$dst, $src2}", - [(set GR8:$dst, (rotr GR8:$src1, (i8 imm:$src2)))]>; -def ROR16ri : Ii8<0xC1, MRM1r, (outs GR16:$dst), (ins GR16:$src1, u8imm:$src2), - "ror{w}\t{$src2, $dst|$dst, $src2}", - [(set GR16:$dst, (rotr GR16:$src1, (i8 imm:$src2)))]>, - OpSize16; -def ROR32ri : Ii8<0xC1, MRM1r, (outs GR32:$dst), (ins GR32:$src1, u8imm:$src2), - "ror{l}\t{$src2, $dst|$dst, $src2}", - [(set GR32:$dst, (rotr GR32:$src1, (i8 imm:$src2)))]>, - OpSize32; -def ROR64ri : RIi8<0xC1, MRM1r, (outs GR64:$dst), - (ins GR64:$src1, u8imm:$src2), - "ror{q}\t{$src2, $dst|$dst, $src2}", - [(set GR64:$dst, (rotr GR64:$src1, (i8 imm:$src2)))]>; +multiclass ShiftRotate_NF { + let Predicates = [In64BitMode] in { + let isConvertibleToThreeAddress = !if(!eq(m, "shl"), 1, 0) in { + def 8ri_NF : BinOpRI8U_R, Sched<[ri]>, NF; + def 16ri_NF : BinOpRI8U_R, Sched<[ri]>, NF, PD; + def 32ri_NF : BinOpRI8U_R, Sched<[ri]>, NF; + def 64ri_NF : BinOpRI8U_R, Sched<[ri]>, NF; -// Rotate by 1 -def ROR8r1 : I<0xD0, MRM1r, (outs GR8 :$dst), (ins GR8 :$src1), - "ror{b}\t$dst", []>; -def ROR16r1 : I<0xD1, MRM1r, (outs GR16:$dst), (ins GR16:$src1), - "ror{w}\t$dst", []>, OpSize16; -def ROR32r1 : I<0xD1, MRM1r, (outs GR32:$dst), (ins GR32:$src1), - "ror{l}\t$dst", []>, OpSize32; -def ROR64r1 : RI<0xD1, MRM1r, (outs GR64:$dst), (ins GR64:$src1), - "ror{q}\t$dst", []>; -} // SchedRW -} // Constraints = "$src = $dst", SchedRW + def 8ri_NF_ND : BinOpRI8U_R, Sched<[ri]>, EVEX_NF; + def 16ri_NF_ND : BinOpRI8U_R, Sched<[ri]>, EVEX_NF, PD; + def 32ri_NF_ND : BinOpRI8U_R, Sched<[ri]>, EVEX_NF; + def 64ri_NF_ND : BinOpRI8U_R, Sched<[ri]>, EVEX_NF; + } -let Uses = [CL], SchedRW = [WriteRotateCLLd, WriteRMW] in { -def ROR8mCL : I<0xD2, MRM1m, (outs), (ins i8mem :$dst), - "ror{b}\t{%cl, $dst|$dst, cl}", - [(store (rotr (loadi8 addr:$dst), CL), addr:$dst)]>; -def ROR16mCL : I<0xD3, MRM1m, (outs), (ins i16mem:$dst), - "ror{w}\t{%cl, $dst|$dst, cl}", - [(store (rotr (loadi16 addr:$dst), CL), addr:$dst)]>, OpSize16; -def ROR32mCL : I<0xD3, MRM1m, (outs), (ins i32mem:$dst), - "ror{l}\t{%cl, $dst|$dst, cl}", - [(store (rotr (loadi32 addr:$dst), CL), addr:$dst)]>, OpSize32; -def ROR64mCL : RI<0xD3, MRM1m, (outs), (ins i64mem:$dst), - "ror{q}\t{%cl, $dst|$dst, cl}", - [(store (rotr (loadi64 addr:$dst), CL), addr:$dst)]>, - Requires<[In64BitMode]>; -} // Uses, SchedRW + def 8mi_NF : BinOpMI8U_M, Sched<[mi, WriteRMW]>, NF; + def 16mi_NF : BinOpMI8U_M, Sched<[mi, WriteRMW]>, NF, PD; + def 32mi_NF : BinOpMI8U_M, Sched<[mi, WriteRMW]>, NF; + def 64mi_NF : BinOpMI8U_M, Sched<[mi, WriteRMW]>, NF; -let SchedRW = [WriteRotateLd, WriteRMW], mayLoad = 1, mayStore =1 in { -def ROR8mi : Ii8<0xC0, MRM1m, (outs), (ins i8mem :$dst, u8imm:$src), - "ror{b}\t{$src, $dst|$dst, $src}", - [(store (rotr (loadi8 addr:$dst), (i8 imm:$src)), addr:$dst)]>; -def ROR16mi : Ii8<0xC1, MRM1m, (outs), (ins i16mem:$dst, u8imm:$src), - "ror{w}\t{$src, $dst|$dst, $src}", - [(store (rotr (loadi16 addr:$dst), (i8 imm:$src)), addr:$dst)]>, - OpSize16; -def ROR32mi : Ii8<0xC1, MRM1m, (outs), (ins i32mem:$dst, u8imm:$src), - "ror{l}\t{$src, $dst|$dst, $src}", - [(store (rotr (loadi32 addr:$dst), (i8 imm:$src)), addr:$dst)]>, - OpSize32; -def ROR64mi : RIi8<0xC1, MRM1m, (outs), (ins i64mem:$dst, u8imm:$src), - "ror{q}\t{$src, $dst|$dst, $src}", - [(store (rotr (loadi64 addr:$dst), (i8 imm:$src)), addr:$dst)]>, - Requires<[In64BitMode]>; + def 8mi_NF_ND : BinOpMI8U_R, Sched<[mi, ri]>, EVEX_NF; + def 16mi_NF_ND : BinOpMI8U_R, Sched<[mi, ri]>, EVEX_NF, PD; + def 32mi_NF_ND : BinOpMI8U_R, Sched<[mi, ri]>, EVEX_NF; + def 64mi_NF_ND : BinOpMI8U_R, Sched<[mi, ri]>, EVEX_NF; -// Rotate by 1 -def ROR8m1 : I<0xD0, MRM1m, (outs), (ins i8mem :$dst), - "ror{b}\t$dst", []>; -def ROR16m1 : I<0xD1, MRM1m, (outs), (ins i16mem:$dst), - "ror{w}\t$dst", []>, OpSize16; -def ROR32m1 : I<0xD1, MRM1m, (outs), (ins i32mem:$dst), - "ror{l}\t$dst", []>, - OpSize32; -def ROR64m1 : RI<0xD1, MRM1m, (outs), (ins i64mem:$dst), - "ror{q}\t$dst", []>, Requires<[In64BitMode]>; -} // SchedRW, mayLoad, mayStore + let SchedRW = [ri] in { + // FIXME: Assembler can't tell whether it's 8r1_NF_ND or 8rCL_NF when the source register is cl, e.g. + // + // {nf} shlb %cl, %al + // + // GNU binutils distinguish them by adding an explicit $1 to asm string of 8r1_NF_ND. But we haven't support + // constant immediate in asm string for X86 in TD. So we add DisassembleOnly for 8r1_NF_ND for the time being. + def 8r1_NF : UnaryOpR_R<0xD1, RegMRM, m, Xi8>, NF; + def 16r1_NF : UnaryOpR_R<0xD1, RegMRM, m, Xi16>, NF, PD; + def 32r1_NF : UnaryOpR_R<0xD1, RegMRM, m, Xi32>, NF; + def 64r1_NF : UnaryOpR_R<0xD1, RegMRM, m, Xi64>, NF; + def 8r1_NF_ND : UnaryOpR_R<0xD1, RegMRM, m, Xi8, null_frag, 1>, EVEX_NF, DisassembleOnly; + def 16r1_NF_ND : UnaryOpR_R<0xD1, RegMRM, m, Xi16, null_frag, 1>, EVEX_NF, PD; + def 32r1_NF_ND : UnaryOpR_R<0xD1, RegMRM, m, Xi32, null_frag, 1>, EVEX_NF; + def 64r1_NF_ND : UnaryOpR_R<0xD1, RegMRM, m, Xi64, null_frag, 1>, EVEX_NF; + } -//===----------------------------------------------------------------------===// -// Double shift instructions (generalizations of rotate) -//===----------------------------------------------------------------------===// + let SchedRW = [mi, WriteRMW] in { + def 8m1_NF : UnaryOpM_M<0xD1, MemMRM, m, Xi8>, NF; + def 16m1_NF : UnaryOpM_M<0xD1, MemMRM, m, Xi16>, NF, PD; + def 32m1_NF : UnaryOpM_M<0xD1, MemMRM, m, Xi32>, NF; + def 64m1_NF : UnaryOpM_M<0xD1, MemMRM, m, Xi64>, NF; + } + let SchedRW = [mi, ri] in { + def 8m1_NF_ND : UnaryOpM_R<0xD1, MemMRM, m, Xi8>, EVEX_NF; + def 16m1_NF_ND : UnaryOpM_R<0xD1, MemMRM, m, Xi16>, EVEX_NF, PD; + def 32m1_NF_ND : UnaryOpM_R<0xD1, MemMRM, m, Xi32>, EVEX_NF; + def 64m1_NF_ND : UnaryOpM_R<0xD1, MemMRM, m, Xi64>, EVEX_NF; + } -let Constraints = "$src1 = $dst" in { + let Uses = [CL] in { + def 8rCL_NF : BinOpRC_R, Sched<[rCL]>, NF; + def 16rCL_NF : BinOpRC_R, Sched<[rCL]>, NF, PD; + def 32rCL_NF : BinOpRC_R, Sched<[rCL]>, NF; + def 64rCL_NF : BinOpRC_R, Sched<[rCL]>, NF; -let Uses = [CL], SchedRW = [WriteSHDrrcl] in { -def SHLD16rrCL : I<0xA5, MRMDestReg, (outs GR16:$dst), - (ins GR16:$src1, GR16:$src2), - "shld{w}\t{%cl, $src2, $dst|$dst, $src2, cl}", - [(set GR16:$dst, (X86fshl GR16:$src1, GR16:$src2, CL))]>, - TB, OpSize16; -def SHRD16rrCL : I<0xAD, MRMDestReg, (outs GR16:$dst), - (ins GR16:$src1, GR16:$src2), - "shrd{w}\t{%cl, $src2, $dst|$dst, $src2, cl}", - [(set GR16:$dst, (X86fshr GR16:$src2, GR16:$src1, CL))]>, - TB, OpSize16; -def SHLD32rrCL : I<0xA5, MRMDestReg, (outs GR32:$dst), - (ins GR32:$src1, GR32:$src2), - "shld{l}\t{%cl, $src2, $dst|$dst, $src2, cl}", - [(set GR32:$dst, (fshl GR32:$src1, GR32:$src2, CL))]>, - TB, OpSize32; -def SHRD32rrCL : I<0xAD, MRMDestReg, (outs GR32:$dst), - (ins GR32:$src1, GR32:$src2), - "shrd{l}\t{%cl, $src2, $dst|$dst, $src2, cl}", - [(set GR32:$dst, (fshr GR32:$src2, GR32:$src1, CL))]>, - TB, OpSize32; -def SHLD64rrCL : RI<0xA5, MRMDestReg, (outs GR64:$dst), - (ins GR64:$src1, GR64:$src2), - "shld{q}\t{%cl, $src2, $dst|$dst, $src2, cl}", - [(set GR64:$dst, (fshl GR64:$src1, GR64:$src2, CL))]>, - TB; -def SHRD64rrCL : RI<0xAD, MRMDestReg, (outs GR64:$dst), - (ins GR64:$src1, GR64:$src2), - "shrd{q}\t{%cl, $src2, $dst|$dst, $src2, cl}", - [(set GR64:$dst, (fshr GR64:$src2, GR64:$src1, CL))]>, - TB; -} // Uses, SchedRW + def 8rCL_NF_ND : BinOpRC_R, Sched<[rCL]>, EVEX_NF; + def 16rCL_NF_ND : BinOpRC_R, Sched<[rCL]>, EVEX_NF, PD; + def 32rCL_NF_ND : BinOpRC_R, Sched<[rCL]>, EVEX_NF; + def 64rCL_NF_ND : BinOpRC_R, Sched<[rCL]>, EVEX_NF; -let isCommutable = 1, SchedRW = [WriteSHDrri] in { // These instructions commute to each other. -def SHLD16rri8 : Ii8<0xA4, MRMDestReg, - (outs GR16:$dst), - (ins GR16:$src1, GR16:$src2, u8imm:$src3), - "shld{w}\t{$src3, $src2, $dst|$dst, $src2, $src3}", - [(set GR16:$dst, (X86fshl GR16:$src1, GR16:$src2, - (i8 imm:$src3)))]>, - TB, OpSize16; -def SHRD16rri8 : Ii8<0xAC, MRMDestReg, - (outs GR16:$dst), - (ins GR16:$src1, GR16:$src2, u8imm:$src3), - "shrd{w}\t{$src3, $src2, $dst|$dst, $src2, $src3}", - [(set GR16:$dst, (X86fshr GR16:$src2, GR16:$src1, - (i8 imm:$src3)))]>, - TB, OpSize16; -def SHLD32rri8 : Ii8<0xA4, MRMDestReg, - (outs GR32:$dst), - (ins GR32:$src1, GR32:$src2, u8imm:$src3), - "shld{l}\t{$src3, $src2, $dst|$dst, $src2, $src3}", - [(set GR32:$dst, (fshl GR32:$src1, GR32:$src2, - (i8 imm:$src3)))]>, - TB, OpSize32; -def SHRD32rri8 : Ii8<0xAC, MRMDestReg, - (outs GR32:$dst), - (ins GR32:$src1, GR32:$src2, u8imm:$src3), - "shrd{l}\t{$src3, $src2, $dst|$dst, $src2, $src3}", - [(set GR32:$dst, (fshr GR32:$src2, GR32:$src1, - (i8 imm:$src3)))]>, - TB, OpSize32; -def SHLD64rri8 : RIi8<0xA4, MRMDestReg, - (outs GR64:$dst), - (ins GR64:$src1, GR64:$src2, u8imm:$src3), - "shld{q}\t{$src3, $src2, $dst|$dst, $src2, $src3}", - [(set GR64:$dst, (fshl GR64:$src1, GR64:$src2, - (i8 imm:$src3)))]>, - TB; -def SHRD64rri8 : RIi8<0xAC, MRMDestReg, - (outs GR64:$dst), - (ins GR64:$src1, GR64:$src2, u8imm:$src3), - "shrd{q}\t{$src3, $src2, $dst|$dst, $src2, $src3}", - [(set GR64:$dst, (fshr GR64:$src2, GR64:$src1, - (i8 imm:$src3)))]>, - TB; -} // SchedRW -} // Constraints = "$src = $dst" + def 8mCL_NF : BinOpMC_M, Sched<[mCL, WriteRMW]>, NF; + def 16mCL_NF : BinOpMC_M, Sched<[mCL, WriteRMW]>, NF, PD; + def 32mCL_NF : BinOpMC_M, Sched<[mCL, WriteRMW]>, NF; + def 64mCL_NF : BinOpMC_M, Sched<[mCL, WriteRMW]>, NF; -let Uses = [CL], SchedRW = [WriteSHDmrcl] in { -def SHLD16mrCL : I<0xA5, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2), - "shld{w}\t{%cl, $src2, $dst|$dst, $src2, cl}", - [(store (X86fshl (loadi16 addr:$dst), GR16:$src2, CL), - addr:$dst)]>, TB, OpSize16; -def SHRD16mrCL : I<0xAD, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2), - "shrd{w}\t{%cl, $src2, $dst|$dst, $src2, cl}", - [(store (X86fshr GR16:$src2, (loadi16 addr:$dst), CL), - addr:$dst)]>, TB, OpSize16; + def 8mCL_NF_ND : BinOpMC_R, Sched<[mCL, rCL]>, EVEX_NF; + def 16mCL_NF_ND : BinOpMC_R, Sched<[mCL, rCL]>, EVEX_NF, PD; + def 32mCL_NF_ND : BinOpMC_R, Sched<[mCL, rCL]>, EVEX_NF; + def 64mCL_NF_ND : BinOpMC_R, Sched<[mCL, rCL]>, EVEX_NF; + } + } +} +defm SHL: ShiftRotate<"shl", MRM4r, MRM4m, shl, WriteShiftCL, WriteShift, WriteShiftCLLd, WriteShiftLd>; +defm SHR: ShiftRotate<"shr", MRM5r, MRM5m, srl, WriteShiftCL, WriteShift, WriteShiftCLLd, WriteShiftLd>; +defm SAR: ShiftRotate<"sar", MRM7r, MRM7m, sra, WriteShiftCL, WriteShift, WriteShiftCLLd, WriteShiftLd>; -def SHLD32mrCL : I<0xA5, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2), - "shld{l}\t{%cl, $src2, $dst|$dst, $src2, cl}", - [(store (fshl (loadi32 addr:$dst), GR32:$src2, CL), - addr:$dst)]>, TB, OpSize32; -def SHRD32mrCL : I<0xAD, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2), - "shrd{l}\t{%cl, $src2, $dst|$dst, $src2, cl}", - [(store (fshr GR32:$src2, (loadi32 addr:$dst), CL), - addr:$dst)]>, TB, OpSize32; +defm ROL: ShiftRotate<"rol", MRM0r, MRM0m, rotl, WriteRotateCL, WriteRotate, WriteRotateCLLd, WriteRotateLd>; +defm ROR: ShiftRotate<"ror", MRM1r, MRM1m, rotr, WriteRotateCL, WriteRotate, WriteRotateCLLd, WriteRotateLd>; +defm RCL: ShiftRotate<"rcl", MRM2r, MRM2m, null_frag, WriteRotateCL, WriteRotate, WriteRotateCLLd, WriteRotateLd, [EFLAGS]>; +defm RCR: ShiftRotate<"rcr", MRM3r, MRM3m, null_frag, WriteRotateCL, WriteRotate, WriteRotateCLLd, WriteRotateLd, [EFLAGS]>; -def SHLD64mrCL : RI<0xA5, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src2), - "shld{q}\t{%cl, $src2, $dst|$dst, $src2, cl}", - [(store (fshl (loadi64 addr:$dst), GR64:$src2, CL), - addr:$dst)]>, TB; -def SHRD64mrCL : RI<0xAD, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src2), - "shrd{q}\t{%cl, $src2, $dst|$dst, $src2, cl}", - [(store (fshr GR64:$src2, (loadi64 addr:$dst), CL), - addr:$dst)]>, TB; -} // Uses, SchedRW +defm SHL: ShiftRotate_NF<"shl", MRM4r, MRM4m, WriteShiftCL, WriteShift, WriteShiftCLLd, WriteShiftLd>; +defm SHR: ShiftRotate_NF<"shr", MRM5r, MRM5m, WriteShiftCL, WriteShift, WriteShiftCLLd, WriteShiftLd>; +defm SAR: ShiftRotate_NF<"sar", MRM7r, MRM7m, WriteShiftCL, WriteShift, WriteShiftCLLd, WriteShiftLd>; -let SchedRW = [WriteSHDmri] in { -def SHLD16mri8 : Ii8<0xA4, MRMDestMem, - (outs), (ins i16mem:$dst, GR16:$src2, u8imm:$src3), - "shld{w}\t{$src3, $src2, $dst|$dst, $src2, $src3}", - [(store (X86fshl (loadi16 addr:$dst), GR16:$src2, - (i8 imm:$src3)), addr:$dst)]>, - TB, OpSize16; -def SHRD16mri8 : Ii8<0xAC, MRMDestMem, - (outs), (ins i16mem:$dst, GR16:$src2, u8imm:$src3), - "shrd{w}\t{$src3, $src2, $dst|$dst, $src2, $src3}", - [(store (X86fshr GR16:$src2, (loadi16 addr:$dst), - (i8 imm:$src3)), addr:$dst)]>, - TB, OpSize16; - -def SHLD32mri8 : Ii8<0xA4, MRMDestMem, - (outs), (ins i32mem:$dst, GR32:$src2, u8imm:$src3), - "shld{l}\t{$src3, $src2, $dst|$dst, $src2, $src3}", - [(store (fshl (loadi32 addr:$dst), GR32:$src2, - (i8 imm:$src3)), addr:$dst)]>, - TB, OpSize32; -def SHRD32mri8 : Ii8<0xAC, MRMDestMem, - (outs), (ins i32mem:$dst, GR32:$src2, u8imm:$src3), - "shrd{l}\t{$src3, $src2, $dst|$dst, $src2, $src3}", - [(store (fshr GR32:$src2, (loadi32 addr:$dst), - (i8 imm:$src3)), addr:$dst)]>, - TB, OpSize32; - -def SHLD64mri8 : RIi8<0xA4, MRMDestMem, - (outs), (ins i64mem:$dst, GR64:$src2, u8imm:$src3), - "shld{q}\t{$src3, $src2, $dst|$dst, $src2, $src3}", - [(store (fshl (loadi64 addr:$dst), GR64:$src2, - (i8 imm:$src3)), addr:$dst)]>, - TB; -def SHRD64mri8 : RIi8<0xAC, MRMDestMem, - (outs), (ins i64mem:$dst, GR64:$src2, u8imm:$src3), - "shrd{q}\t{$src3, $src2, $dst|$dst, $src2, $src3}", - [(store (fshr GR64:$src2, (loadi64 addr:$dst), - (i8 imm:$src3)), addr:$dst)]>, - TB; -} // SchedRW - -} // Defs = [EFLAGS], hasSideEffects +defm ROL: ShiftRotate_NF<"rol", MRM0r, MRM0m, WriteRotateCL, WriteRotate, WriteRotateCLLd, WriteRotateLd>; +defm ROR: ShiftRotate_NF<"ror", MRM1r, MRM1m, WriteRotateCL, WriteRotate, WriteRotateCLLd, WriteRotateLd>; // Use the opposite rotate if allows us to use the rotate by 1 instruction. -def : Pat<(rotl GR8:$src1, (i8 7)), (ROR8r1 GR8:$src1)>; -def : Pat<(rotl GR16:$src1, (i8 15)), (ROR16r1 GR16:$src1)>; -def : Pat<(rotl GR32:$src1, (i8 31)), (ROR32r1 GR32:$src1)>; -def : Pat<(rotl GR64:$src1, (i8 63)), (ROR64r1 GR64:$src1)>; -def : Pat<(rotr GR8:$src1, (i8 7)), (ROL8r1 GR8:$src1)>; -def : Pat<(rotr GR16:$src1, (i8 15)), (ROL16r1 GR16:$src1)>; -def : Pat<(rotr GR32:$src1, (i8 31)), (ROL32r1 GR32:$src1)>; -def : Pat<(rotr GR64:$src1, (i8 63)), (ROL64r1 GR64:$src1)>; +let Predicates = [NoNDD] in { + def : Pat<(rotl GR8:$src1, (i8 7)), (ROR8r1 GR8:$src1)>; + def : Pat<(rotl GR16:$src1, (i8 15)), (ROR16r1 GR16:$src1)>; + def : Pat<(rotl GR32:$src1, (i8 31)), (ROR32r1 GR32:$src1)>; + def : Pat<(rotl GR64:$src1, (i8 63)), (ROR64r1 GR64:$src1)>; + def : Pat<(rotr GR8:$src1, (i8 7)), (ROL8r1 GR8:$src1)>; + def : Pat<(rotr GR16:$src1, (i8 15)), (ROL16r1 GR16:$src1)>; + def : Pat<(rotr GR32:$src1, (i8 31)), (ROL32r1 GR32:$src1)>; + def : Pat<(rotr GR64:$src1, (i8 63)), (ROL64r1 GR64:$src1)>; +} +let Predicates = [HasNDD] in { + def : Pat<(rotl GR8:$src1, (i8 7)), (ROR8r1_ND GR8:$src1)>; + def : Pat<(rotl GR16:$src1, (i8 15)), (ROR16r1_ND GR16:$src1)>; + def : Pat<(rotl GR32:$src1, (i8 31)), (ROR32r1_ND GR32:$src1)>; + def : Pat<(rotl GR64:$src1, (i8 63)), (ROR64r1_ND GR64:$src1)>; + def : Pat<(rotr GR8:$src1, (i8 7)), (ROL8r1_ND GR8:$src1)>; + def : Pat<(rotr GR16:$src1, (i8 15)), (ROL16r1_ND GR16:$src1)>; + def : Pat<(rotr GR32:$src1, (i8 31)), (ROL32r1_ND GR32:$src1)>; + def : Pat<(rotr GR64:$src1, (i8 63)), (ROL64r1_ND GR64:$src1)>; +} def : Pat<(store (rotl (loadi8 addr:$dst), (i8 7)), addr:$dst), (ROR8m1 addr:$dst)>; @@ -790,6 +279,227 @@ def : Pat<(store (rotr (loadi32 addr:$dst), (i8 31)), addr:$dst), def : Pat<(store (rotr (loadi64 addr:$dst), (i8 63)), addr:$dst), (ROL64m1 addr:$dst)>, Requires<[In64BitMode]>; +let Predicates = [HasNDD] in { +def : Pat<(rotl (loadi8 addr:$src), (i8 7)), + (ROR8m1_ND addr:$src)>; +def : Pat<(rotl (loadi16 addr:$src), (i8 15)), + (ROR16m1_ND addr:$src)>; +def : Pat<(rotl (loadi32 addr:$src), (i8 31)), + (ROR32m1_ND addr:$src)>; +def : Pat<(rotl (loadi64 addr:$src), (i8 63)), + (ROR64m1_ND addr:$src)>; + +def : Pat<(rotr (loadi8 addr:$src), (i8 7)), + (ROL8m1_ND addr:$src)>; +def : Pat<(rotr (loadi16 addr:$src), (i8 15)), + (ROL16m1_ND addr:$src)>; +def : Pat<(rotr (loadi32 addr:$src), (i8 31)), + (ROL32m1_ND addr:$src)>; +def : Pat<(rotr (loadi64 addr:$src), (i8 63)), + (ROL64m1_ND addr:$src)>; +} + +// Patterns for rotate with relocImm for the immediate field. +let Predicates = [NoNDD] in { + def : Pat<(rotl GR8:$src1, (i8 relocImm:$src2)), + (ROL8ri GR8:$src1, relocImm:$src2)>; + def : Pat<(rotl GR16:$src1, (i8 relocImm:$src2)), + (ROL16ri GR16:$src1, relocImm:$src2)>; + def : Pat<(rotl GR32:$src1, (i8 relocImm:$src2)), + (ROL32ri GR32:$src1, relocImm:$src2)>; + def : Pat<(rotl GR64:$src1, (i8 relocImm:$src2)), + (ROL64ri GR64:$src1, relocImm:$src2)>; + + def : Pat<(rotr GR8:$src1, (i8 relocImm:$src2)), + (ROR8ri GR8:$src1, relocImm:$src2)>; + def : Pat<(rotr GR16:$src1, (i8 relocImm:$src2)), + (ROR16ri GR16:$src1, relocImm:$src2)>; + def : Pat<(rotr GR32:$src1, (i8 relocImm:$src2)), + (ROR32ri GR32:$src1, relocImm:$src2)>; + def : Pat<(rotr GR64:$src1, (i8 relocImm:$src2)), + (ROR64ri GR64:$src1, relocImm:$src2)>; +} +let Predicates = [HasNDD] in { + def : Pat<(rotl GR8:$src1, (i8 relocImm:$src2)), + (ROL8ri_ND GR8:$src1, relocImm:$src2)>; + def : Pat<(rotl GR16:$src1, (i8 relocImm:$src2)), + (ROL16ri_ND GR16:$src1, relocImm:$src2)>; + def : Pat<(rotl GR32:$src1, (i8 relocImm:$src2)), + (ROL32ri_ND GR32:$src1, relocImm:$src2)>; + def : Pat<(rotl GR64:$src1, (i8 relocImm:$src2)), + (ROL64ri_ND GR64:$src1, relocImm:$src2)>; + + def : Pat<(rotr GR8:$src1, (i8 relocImm:$src2)), + (ROR8ri_ND GR8:$src1, relocImm:$src2)>; + def : Pat<(rotr GR16:$src1, (i8 relocImm:$src2)), + (ROR16ri_ND GR16:$src1, relocImm:$src2)>; + def : Pat<(rotr GR32:$src1, (i8 relocImm:$src2)), + (ROR32ri_ND GR32:$src1, relocImm:$src2)>; + def : Pat<(rotr GR64:$src1, (i8 relocImm:$src2)), + (ROR64ri_ND GR64:$src1, relocImm:$src2)>; +} + +//===----------------------------------------------------------------------===// +// Double precision shift instructions (generalizations of rotate) +//===----------------------------------------------------------------------===// + +class ShlrdOpRRI8U_R o, string m, X86TypeInfo t, SDPatternOperator node = null_frag, bit ndd = 0> + : ITy, NDD { + let isCommutable = 1; + let ImmT = Imm8; + let SchedRW = [WriteSHDrri]; + let Pattern = !if(!eq(m, "shld"), + [(set t.RegClass:$dst, (node t.RegClass:$src1, t.RegClass:$src2, (i8 imm:$src3)))], + [(set t.RegClass:$dst, (node t.RegClass:$src2, t.RegClass:$src1, (i8 imm:$src3)))]); +} + +class ShlrdOpRRC_R o, string m, X86TypeInfo t, SDPatternOperator node = null_frag, bit ndd = 0> + : BinOpRR, NDD { + let Uses = [CL]; + let SchedRW = [WriteSHDrrcl]; + let Pattern = !if(!eq(m, "shld"), + [(set t.RegClass:$dst, (node t.RegClass:$src1, t.RegClass:$src2, CL))], + [(set t.RegClass:$dst, (node t.RegClass:$src2, t.RegClass:$src1, CL))]); +} + +class ShlrdOpMRI8U_M o, string m, X86TypeInfo t, SDPatternOperator node = null_frag> + : ITy, TB { + let ImmT = Imm8; + let SchedRW = [WriteSHDmri]; + let mayLoad = 1; + let mayStore = 1; + let Pattern = !if(!eq(m, "shld"), + [(store (node (t.LoadNode addr:$src1), t.RegClass:$src2, (i8 imm:$src3)), addr:$src1)], + [(store (node t.RegClass:$src2, (t.LoadNode addr:$src1), (i8 imm:$src3)), addr:$src1)]); +} + +class ShlrdOpMRC_M o, string m, X86TypeInfo t, SDPatternOperator node = null_frag> + : BinOpMR, TB { + let Uses = [CL]; + let SchedRW = [WriteSHDmrcl]; + let mayStore = 1; + let Pattern = !if(!eq(m, "shld"), + [(store (node (t.LoadNode addr:$src1), t.RegClass:$src2, CL), addr:$src1)], + [(store (node t.RegClass:$src2, (t.LoadNode addr:$src1), CL), addr:$src1)]); +} + +class ShlrdOpMRI8U_R o, string m, X86TypeInfo t, SDPatternOperator node = null_frag> + : ITy, NDD<1> { + let ImmT = Imm8; + let SchedRW = [WriteSHDmri]; + let mayLoad = 1; + let Pattern = !if(!eq(m, "shld"), + [(set t.RegClass:$dst, (node (t.LoadNode addr:$src1), t.RegClass:$src2, (i8 imm:$src3)))], + [(set t.RegClass:$dst, (node t.RegClass:$src2, (t.LoadNode addr:$src1), (i8 imm:$src3)))]); +} + +class ShlrdOpMRC_R o, string m, X86TypeInfo t, SDPatternOperator node = null_frag> + : BinOpMR, NDD<1> { + let Uses = [CL]; + let SchedRW = [WriteSHDmrcl]; + let Pattern = !if(!eq(m, "shld"), + [(set t.RegClass:$dst, (node (t.LoadNode addr:$src1), t.RegClass:$src2, CL))], + [(set t.RegClass:$dst, (node t.RegClass:$src2, (t.LoadNode addr:$src1), CL))]); +} + +multiclass Shlrd o1, bits<8> o2, bits<8> o3, string m, SDPatternOperator node, SDPatternOperator t_node> { + let Predicates = [NoNDD] in { + def 16rri8 : ShlrdOpRRI8U_R, TB, DefEFLAGS, OpSize16; + def 32rri8 : ShlrdOpRRI8U_R, TB, DefEFLAGS, OpSize32; + def 64rri8 : ShlrdOpRRI8U_R, TB, DefEFLAGS; + + def 16rrCL : ShlrdOpRRC_R, TB, DefEFLAGS, OpSize16; + def 32rrCL : ShlrdOpRRC_R, TB, DefEFLAGS, OpSize32; + def 64rrCL : ShlrdOpRRC_R, TB, DefEFLAGS; + } + let Predicates = [HasNDD, In64BitMode] in { + def 16rri8_ND : ShlrdOpRRI8U_R, DefEFLAGS, PD; + def 32rri8_ND : ShlrdOpRRI8U_R, DefEFLAGS; + def 64rri8_ND : ShlrdOpRRI8U_R, DefEFLAGS; + + def 16rrCL_ND : ShlrdOpRRC_R, DefEFLAGS, PD; + def 32rrCL_ND : ShlrdOpRRC_R, DefEFLAGS; + def 64rrCL_ND : ShlrdOpRRC_R, DefEFLAGS; + } + + let Predicates = [In64BitMode] in { + def 16rri8_NF : ShlrdOpRRI8U_R, NF, PD; + def 32rri8_NF : ShlrdOpRRI8U_R, NF; + def 64rri8_NF : ShlrdOpRRI8U_R, NF; + + def 16rrCL_NF : ShlrdOpRRC_R, NF, PD; + def 32rrCL_NF : ShlrdOpRRC_R, NF; + def 64rrCL_NF : ShlrdOpRRC_R, NF; + + def 16rri8_NF_ND : ShlrdOpRRI8U_R, EVEX_NF, PD; + def 32rri8_NF_ND : ShlrdOpRRI8U_R, EVEX_NF; + def 64rri8_NF_ND : ShlrdOpRRI8U_R, EVEX_NF; + + def 16rrCL_NF_ND : ShlrdOpRRC_R, EVEX_NF, PD; + def 32rrCL_NF_ND : ShlrdOpRRC_R, EVEX_NF; + def 64rrCL_NF_ND : ShlrdOpRRC_R, EVEX_NF; + + def 16rri8_EVEX : ShlrdOpRRI8U_R, DefEFLAGS, PL, PD; + def 32rri8_EVEX : ShlrdOpRRI8U_R, DefEFLAGS, PL; + def 64rri8_EVEX : ShlrdOpRRI8U_R, DefEFLAGS, PL; + + def 16rrCL_EVEX : ShlrdOpRRC_R, DefEFLAGS, PL, PD; + def 32rrCL_EVEX : ShlrdOpRRC_R, DefEFLAGS, PL; + def 64rrCL_EVEX : ShlrdOpRRC_R, DefEFLAGS, PL; + } + + def 16mri8 : ShlrdOpMRI8U_M, DefEFLAGS, OpSize16; + def 32mri8 : ShlrdOpMRI8U_M, DefEFLAGS, OpSize32; + def 64mri8 : ShlrdOpMRI8U_M, DefEFLAGS; + + def 16mrCL : ShlrdOpMRC_M, DefEFLAGS, OpSize16; + def 32mrCL : ShlrdOpMRC_M, DefEFLAGS, OpSize32; + def 64mrCL : ShlrdOpMRC_M, DefEFLAGS; + + let Predicates = [HasNDD, In64BitMode] in { + def 16mri8_ND : ShlrdOpMRI8U_R, DefEFLAGS, PD; + def 32mri8_ND : ShlrdOpMRI8U_R, DefEFLAGS; + def 64mri8_ND : ShlrdOpMRI8U_R, DefEFLAGS; + + def 16mrCL_ND : ShlrdOpMRC_R, DefEFLAGS, PD; + def 32mrCL_ND : ShlrdOpMRC_R, DefEFLAGS; + def 64mrCL_ND : ShlrdOpMRC_R, DefEFLAGS; + } + + let Predicates = [In64BitMode] in { + def 16mri8_NF : ShlrdOpMRI8U_M, NF, PD; + def 32mri8_NF : ShlrdOpMRI8U_M, NF; + def 64mri8_NF : ShlrdOpMRI8U_M, NF; + + def 16mrCL_NF : ShlrdOpMRC_M, NF, PD; + def 32mrCL_NF : ShlrdOpMRC_M, NF; + def 64mrCL_NF : ShlrdOpMRC_M, NF; + + def 16mri8_NF_ND : ShlrdOpMRI8U_R, EVEX_NF, PD; + def 32mri8_NF_ND : ShlrdOpMRI8U_R, EVEX_NF; + def 64mri8_NF_ND : ShlrdOpMRI8U_R, EVEX_NF; + + def 16mrCL_NF_ND : ShlrdOpMRC_R, EVEX_NF, PD; + def 32mrCL_NF_ND : ShlrdOpMRC_R, EVEX_NF; + def 64mrCL_NF_ND : ShlrdOpMRC_R, EVEX_NF; + + def 16mri8_EVEX : ShlrdOpMRI8U_M, DefEFLAGS, PL, PD; + def 32mri8_EVEX : ShlrdOpMRI8U_M, DefEFLAGS, PL; + def 64mri8_EVEX : ShlrdOpMRI8U_M, DefEFLAGS, PL; + + def 16mrCL_EVEX : ShlrdOpMRC_M, DefEFLAGS, PL, PD; + def 32mrCL_EVEX : ShlrdOpMRC_M, DefEFLAGS, PL; + def 64mrCL_EVEX : ShlrdOpMRC_M, DefEFLAGS, PL; + } +} + +defm SHLD : Shlrd<0xA4, 0xA5, 0x24, "shld", fshl, X86fshl>; +defm SHRD : Shlrd<0xAC, 0xAD, 0x2C, "shrd", fshr, X86fshr>; + // Sandy Bridge and newer Intel processors support faster rotates using // SHLD to avoid a partial flag update on the normal rotate instructions. // Use a pseudo so that TwoInstructionPass and register allocation will see @@ -812,6 +522,10 @@ let Predicates = [HasFastSHLDRotate], AddedComplexity = 5, [(set GR64:$dst, (rotr GR64:$src1, (i8 imm:$shamt)))]>; } +//===----------------------------------------------------------------------===// +// BMI Shift/Rotate instructions +//===----------------------------------------------------------------------===// + def ROT32L2R_imm8 : SDNodeXFormgetZExtValue(), SDLoc(N)); @@ -824,85 +538,93 @@ def ROT64L2R_imm8 : SDNodeXForm { -let hasSideEffects = 0 in { - def ri#Suffix : Ii8<0xF0, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, u8imm:$src2), - !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>, - TA, XD, VEX, Sched<[WriteShift]>; - let mayLoad = 1 in - def mi#Suffix : Ii8<0xF0, MRMSrcMem, (outs RC:$dst), - (ins x86memop:$src1, u8imm:$src2), - !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>, - TA, XD, VEX, Sched<[WriteShiftLd]>; +class RorXri + : ITy<0xF0, MRMSrcReg, t, (outs t.RegClass:$dst), (ins t.RegClass:$src1, u8imm:$src2), + "rorx", binop_ndd_args, []>, TA, XD, Sched<[WriteShift]> { + let ImmT = Imm8; } +class RorXmi + : ITy<0xF0, MRMSrcMem, t, (outs t.RegClass:$dst), (ins t.MemOperand:$src1, u8imm:$src2), + "rorx", binop_ndd_args, []>, TA, XD, Sched<[WriteShiftLd]> { + let ImmT = Imm8; + let mayLoad = 1; } -multiclass bmi_shift { -let hasSideEffects = 0 in { - def rr#Suffix : I<0xF7, MRMSrcReg4VOp3, (outs RC:$dst), (ins RC:$src1, RC:$src2), - !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>, - VEX, Sched<[WriteShift]>; - let mayLoad = 1 in - def rm#Suffix : I<0xF7, MRMSrcMem4VOp3, - (outs RC:$dst), (ins x86memop:$src1, RC:$src2), - !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>, - VEX, Sched<[WriteShift.Folded, - // x86memop:$src1 - ReadDefault, ReadDefault, ReadDefault, ReadDefault, - ReadDefault, - // RC:$src2 - WriteShift.ReadAfterFold]>; -} +multiclass RorX { + let Predicates = [HasBMI2, NoEGPR] in { + def ri : RorXri, VEX; + def mi : RorXmi, VEX; + } + let Predicates = [HasBMI2, HasEGPR, In64BitMode] in { + def ri_EVEX : RorXri, EVEX; + def mi_EVEX : RorXmi, EVEX; + } } -let Predicates = [HasBMI2, NoEGPR] in { - defm RORX32 : bmi_rotate<"rorx{l}", GR32, i32mem>; - defm RORX64 : bmi_rotate<"rorx{q}", GR64, i64mem>, REX_W; - defm SARX32 : bmi_shift<"sarx{l}", GR32, i32mem>, T8, XS; - defm SARX64 : bmi_shift<"sarx{q}", GR64, i64mem>, T8, XS, REX_W; - defm SHRX32 : bmi_shift<"shrx{l}", GR32, i32mem>, T8, XD; - defm SHRX64 : bmi_shift<"shrx{q}", GR64, i64mem>, T8, XD, REX_W; - defm SHLX32 : bmi_shift<"shlx{l}", GR32, i32mem>, T8, PD; - defm SHLX64 : bmi_shift<"shlx{q}", GR64, i64mem>, T8, PD, REX_W; +defm RORX32: RorX; +defm RORX64: RorX; + +class ShiftXrr + : ITy<0xF7, MRMSrcReg4VOp3, t, (outs t.RegClass:$dst), (ins t.RegClass:$src1, t.RegClass:$src2), + m, binop_ndd_args, []>, T8, Sched<[WriteShift]>; + +class ShiftXrm + : ITy<0xF7, MRMSrcMem4VOp3, t, (outs t.RegClass:$dst), (ins t.MemOperand:$src1, t.RegClass:$src2), + m, binop_ndd_args, []>, T8, + Sched<[WriteShift.Folded, + // x86memop:$src1 + ReadDefault, ReadDefault, ReadDefault, ReadDefault, + ReadDefault, + // RC:$src2 + WriteShift.ReadAfterFold]> { + let mayLoad = 1; } -let Predicates = [HasBMI2, HasEGPR, In64BitMode] in { - defm RORX32 : bmi_rotate<"rorx{l}", GR32, i32mem, "_EVEX">, EVEX; - defm RORX64 : bmi_rotate<"rorx{q}", GR64, i64mem, "_EVEX">, REX_W, EVEX; - defm SARX32 : bmi_shift<"sarx{l}", GR32, i32mem, "_EVEX">, T8, XS, EVEX; - defm SARX64 : bmi_shift<"sarx{q}", GR64, i64mem, "_EVEX">, T8, XS, REX_W, EVEX; - defm SHRX32 : bmi_shift<"shrx{l}", GR32, i32mem, "_EVEX">, T8, XD, EVEX; - defm SHRX64 : bmi_shift<"shrx{q}", GR64, i64mem, "_EVEX">, T8, XD, REX_W, EVEX; - defm SHLX32 : bmi_shift<"shlx{l}", GR32, i32mem, "_EVEX">, T8, PD, EVEX; - defm SHLX64 : bmi_shift<"shlx{q}", GR64, i64mem, "_EVEX">, T8, PD, REX_W, EVEX; + +multiclass ShiftX { + let Predicates = [HasBMI2, NoEGPR] in { + def rr : ShiftXrr, VEX; + def rm : ShiftXrm, VEX; + } + let Predicates = [HasBMI2, HasEGPR, In64BitMode] in { + def rr_EVEX : ShiftXrr, EVEX; + def rm_EVEX : ShiftXrm, EVEX; + } } -let Predicates = [HasBMI2] in { +defm SARX32: ShiftX<"sarx", Xi32>, XS; +defm SARX64: ShiftX<"sarx", Xi64>, XS; +defm SHRX32: ShiftX<"shrx", Xi32>, XD; +defm SHRX64: ShiftX<"shrx", Xi64>, XD; +defm SHLX32: ShiftX<"shlx", Xi32>, PD; +defm SHLX64: ShiftX<"shlx", Xi64>, PD; + +multiclass RORX_Pats { // Prefer RORX which is non-destructive and doesn't update EFLAGS. let AddedComplexity = 10 in { def : Pat<(rotr GR32:$src, (i8 imm:$shamt)), - (RORX32ri GR32:$src, imm:$shamt)>; + (!cast(RORX32ri#suffix) GR32:$src, imm:$shamt)>; def : Pat<(rotr GR64:$src, (i8 imm:$shamt)), - (RORX64ri GR64:$src, imm:$shamt)>; + (!cast(RORX64ri#suffix) GR64:$src, imm:$shamt)>; def : Pat<(rotl GR32:$src, (i8 imm:$shamt)), - (RORX32ri GR32:$src, (ROT32L2R_imm8 imm:$shamt))>; + (!cast(RORX32ri#suffix) GR32:$src, (ROT32L2R_imm8 imm:$shamt))>; def : Pat<(rotl GR64:$src, (i8 imm:$shamt)), - (RORX64ri GR64:$src, (ROT64L2R_imm8 imm:$shamt))>; + (!cast(RORX64ri#suffix) GR64:$src, (ROT64L2R_imm8 imm:$shamt))>; } def : Pat<(rotr (loadi32 addr:$src), (i8 imm:$shamt)), - (RORX32mi addr:$src, imm:$shamt)>; + (!cast(RORX32mi#suffix) addr:$src, imm:$shamt)>; def : Pat<(rotr (loadi64 addr:$src), (i8 imm:$shamt)), - (RORX64mi addr:$src, imm:$shamt)>; + (!cast(RORX64mi#suffix) addr:$src, imm:$shamt)>; def : Pat<(rotl (loadi32 addr:$src), (i8 imm:$shamt)), - (RORX32mi addr:$src, (ROT32L2R_imm8 imm:$shamt))>; + (!cast(RORX32mi#suffix) addr:$src, (ROT32L2R_imm8 imm:$shamt))>; def : Pat<(rotl (loadi64 addr:$src), (i8 imm:$shamt)), - (RORX64mi addr:$src, (ROT64L2R_imm8 imm:$shamt))>; + (!cast(RORX64mi#suffix) addr:$src, (ROT64L2R_imm8 imm:$shamt))>; +} +multiclass ShiftX_Pats { // Prefer SARX/SHRX/SHLX over SAR/SHR/SHL with variable shift BUT not // immediate shift, i.e. the following code is considered better // @@ -917,34 +639,19 @@ let Predicates = [HasBMI2] in { // ... %edi, ... // let AddedComplexity = 1 in { - def : Pat<(sra GR32:$src1, GR8:$src2), - (SARX32rr GR32:$src1, - (INSERT_SUBREG - (i32 (IMPLICIT_DEF)), GR8:$src2, sub_8bit))>; - def : Pat<(sra GR64:$src1, GR8:$src2), - (SARX64rr GR64:$src1, - (INSERT_SUBREG - (i64 (IMPLICIT_DEF)), GR8:$src2, sub_8bit))>; - - def : Pat<(srl GR32:$src1, GR8:$src2), - (SHRX32rr GR32:$src1, - (INSERT_SUBREG - (i32 (IMPLICIT_DEF)), GR8:$src2, sub_8bit))>; - def : Pat<(srl GR64:$src1, GR8:$src2), - (SHRX64rr GR64:$src1, - (INSERT_SUBREG - (i64 (IMPLICIT_DEF)), GR8:$src2, sub_8bit))>; - - def : Pat<(shl GR32:$src1, GR8:$src2), - (SHLX32rr GR32:$src1, - (INSERT_SUBREG - (i32 (IMPLICIT_DEF)), GR8:$src2, sub_8bit))>; - def : Pat<(shl GR64:$src1, GR8:$src2), - (SHLX64rr GR64:$src1, - (INSERT_SUBREG - (i64 (IMPLICIT_DEF)), GR8:$src2, sub_8bit))>; + def : Pat<(op GR32:$src1, GR8:$src2), + (!cast(NAME#"32rr"#suffix) GR32:$src1, + (INSERT_SUBREG (i32 (IMPLICIT_DEF)), GR8:$src2, sub_8bit))>; + def : Pat<(op GR64:$src1, GR8:$src2), + (!cast(NAME#"64rr"#suffix) GR64:$src1, + (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GR8:$src2, sub_8bit))>; + def : Pat<(op GR32:$src1, (shiftMask32 GR8:$src2)), + (!cast(NAME#"32rr"#suffix) GR32:$src1, + (INSERT_SUBREG (i32 (IMPLICIT_DEF)), GR8:$src2, sub_8bit))>; + def : Pat<(op GR64:$src1, (shiftMask64 GR8:$src2)), + (!cast(NAME#"64rr"#suffix) GR64:$src1, + (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GR8:$src2, sub_8bit))>; } - // We prefer to use // mov (%ecx), %esi // shl $imm, $esi @@ -955,48 +662,30 @@ let Predicates = [HasBMI2] in { // shlx %al, (%ecx), %esi // // This priority is enforced by IsProfitableToFoldLoad. - def : Pat<(sra (loadi32 addr:$src1), GR8:$src2), - (SARX32rm addr:$src1, - (INSERT_SUBREG - (i32 (IMPLICIT_DEF)), GR8:$src2, sub_8bit))>; - def : Pat<(sra (loadi64 addr:$src1), GR8:$src2), - (SARX64rm addr:$src1, - (INSERT_SUBREG - (i64 (IMPLICIT_DEF)), GR8:$src2, sub_8bit))>; - - def : Pat<(srl (loadi32 addr:$src1), GR8:$src2), - (SHRX32rm addr:$src1, - (INSERT_SUBREG - (i32 (IMPLICIT_DEF)), GR8:$src2, sub_8bit))>; - def : Pat<(srl (loadi64 addr:$src1), GR8:$src2), - (SHRX64rm addr:$src1, - (INSERT_SUBREG - (i64 (IMPLICIT_DEF)), GR8:$src2, sub_8bit))>; - - def : Pat<(shl (loadi32 addr:$src1), GR8:$src2), - (SHLX32rm addr:$src1, - (INSERT_SUBREG - (i32 (IMPLICIT_DEF)), GR8:$src2, sub_8bit))>; - def : Pat<(shl (loadi64 addr:$src1), GR8:$src2), - (SHLX64rm addr:$src1, - (INSERT_SUBREG - (i64 (IMPLICIT_DEF)), GR8:$src2, sub_8bit))>; + def : Pat<(op (loadi32 addr:$src1), GR8:$src2), + (!cast(NAME#"32rm"#suffix) addr:$src1, + (INSERT_SUBREG (i32 (IMPLICIT_DEF)), GR8:$src2, sub_8bit))>; + def : Pat<(op (loadi64 addr:$src1), GR8:$src2), + (!cast(NAME#"64rm"#suffix) addr:$src1, + (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GR8:$src2, sub_8bit))>; + def : Pat<(op (loadi32 addr:$src1), (shiftMask32 GR8:$src2)), + (!cast(NAME#"32rm"#suffix) addr:$src1, + (INSERT_SUBREG (i32 (IMPLICIT_DEF)), GR8:$src2, sub_8bit))>; + def : Pat<(op (loadi64 addr:$src1), (shiftMask64 GR8:$src2)), + (!cast(NAME#"64rm"#suffix) addr:$src1, + (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GR8:$src2, sub_8bit))>; } -def : Pat<(rotl GR8:$src1, (i8 relocImm:$src2)), - (ROL8ri GR8:$src1, relocImm:$src2)>; -def : Pat<(rotl GR16:$src1, (i8 relocImm:$src2)), - (ROL16ri GR16:$src1, relocImm:$src2)>; -def : Pat<(rotl GR32:$src1, (i8 relocImm:$src2)), - (ROL32ri GR32:$src1, relocImm:$src2)>; -def : Pat<(rotl GR64:$src1, (i8 relocImm:$src2)), - (ROL64ri GR64:$src1, relocImm:$src2)>; +let Predicates = [HasBMI2, NoEGPR] in { + defm : RORX_Pats<"">; + defm SARX : ShiftX_Pats; + defm SHRX : ShiftX_Pats; + defm SHLX : ShiftX_Pats; +} -def : Pat<(rotr GR8:$src1, (i8 relocImm:$src2)), - (ROR8ri GR8:$src1, relocImm:$src2)>; -def : Pat<(rotr GR16:$src1, (i8 relocImm:$src2)), - (ROR16ri GR16:$src1, relocImm:$src2)>; -def : Pat<(rotr GR32:$src1, (i8 relocImm:$src2)), - (ROR32ri GR32:$src1, relocImm:$src2)>; -def : Pat<(rotr GR64:$src1, (i8 relocImm:$src2)), - (ROR64ri GR64:$src1, relocImm:$src2)>; +let Predicates = [HasBMI2, HasEGPR] in { + defm : RORX_Pats<"_EVEX">; + defm SARX : ShiftX_Pats; + defm SHRX : ShiftX_Pats; + defm SHLX : ShiftX_Pats; +} diff --git a/llvm/lib/Target/X86/X86InstrUtils.td b/llvm/lib/Target/X86/X86InstrUtils.td index f4ae15837fb..05ddcfbf272 100644 --- a/llvm/lib/Target/X86/X86InstrUtils.td +++ b/llvm/lib/Target/X86/X86InstrUtils.td @@ -99,6 +99,12 @@ defvar unaryop_args = "$src1"; defvar unaryop_ndd_args = "{$src1, $dst|$dst, $src1}"; defvar binop_args = "{$src2, $src1|$src1, $src2}"; defvar binop_ndd_args = "{$src2, $src1, $dst|$dst, $src1, $src2}"; +defvar binop_cl_args = "{%cl, $src1|$src1, cl}"; +defvar binop_cl_ndd_args = "{%cl, $src1, $dst|$dst, $src1, cl}"; +defvar triop_args = "{$src3, $src2, $src1|$src1, $src2, $src3}"; +defvar triop_ndd_args = "{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"; +defvar triop_cl_args = "{%cl, $src2, $src1|$src1, $src2, cl}"; +defvar triop_cl_ndd_args = "{%cl, $src2, $src1, $dst|$dst, $src1, $src2, cl}"; defvar tie_dst_src1 = "$src1 = $dst"; // NDD - Helper for new data destination instructions @@ -110,9 +116,9 @@ class NDD { Map OpMap = !if(!eq(ndd, 0), OB, T_MAP4); } // NF - Helper for NF (no flags update) instructions -class NF: T_MAP4, EVEX, EVEX_NF, NoCD8; +class NF: T_MAP4, EVEX, EVEX_NF; // PL - Helper for promoted legacy instructions -class PL: T_MAP4, EVEX, NoCD8, ExplicitEVEXPrefix; +class PL: T_MAP4, EVEX, ExplicitEVEXPrefix; //===----------------------------------------------------------------------===// // X86 Type infomation definitions @@ -958,7 +964,7 @@ class ITy o, Format f, X86TypeInfo t, dag outs, dag ins, string m, string args, list p> : I<{o{7}, o{6}, o{5}, o{4}, o{3}, o{2}, o{1}, !if(!eq(t.HasEvenOpcode, 1), 0, o{0})}, f, outs, ins, - !strconcat(m, "{", t.InstrSuffix, "}\t", args), p> { + !strconcat(m, "{", t.InstrSuffix, "}\t", args), p>, NoCD8 { let hasSideEffects = 0; let hasREX_W = t.HasREX_W; } @@ -1063,6 +1069,13 @@ class BinOpRI_F o, string m, X86TypeInfo t, SDPatternOperator node, class BinOpRI_R o, string m, X86TypeInfo t, Format f, bit ndd = 0> : BinOpRI, NDD; +// BinOpRI8U_R - Instructions that read "reg, u8imm" and write "reg". +class BinOpRI8U_R + : ITy<0xC1, f, t, (outs t.RegClass:$dst), (ins t.RegClass:$src1, u8imm:$src2), m, + !if(!eq(ndd, 0), binop_args, binop_ndd_args), + [(set t.RegClass:$dst, (node t.RegClass:$src1, (i8 imm:$src2)))]>, NDD { + let ImmT = Imm8; +} // BinOpRI_RF - Instructions that read "reg, imm" and write "reg", EFLAGS. class BinOpRI_RF o, string m, X86TypeInfo t, SDPatternOperator node, Format f, bit ndd = 0> : BinOpRI let ImmT = Imm8; let mayLoad = 1; } +// BinOpMI8U - Instructions that read "[mem], u8imm". +class BinOpMI8U p> + : ITy<0xC1, f, t, out, (ins t.MemOperand:$src1, u8imm:$src2), m, args, p> { + let ImmT = Imm8; + let mayLoad = 1; +} // BinOpMI8_F - Instructions that read "[mem], imm8" and write EFLAGS only. class BinOpMI8_F : BinOpMI8, Sched<[WriteALU.Folded]>, DefEFLAGS; // BinOpMI8_R - Instructions that read "[mem], imm8" and write "reg". class BinOpMI8_R : BinOpMI8, Sched<[WriteALU.Folded, WriteALU.ReadAfterFold]>, NDD<1>; +// BinOpMI8U_R - Instructions that read "[mem], u8imm" and write "reg". +class BinOpMI8U_R + : BinOpMI8U, NDD<1>; // BinOpMI8_RF - Instructions that read "[mem], imm8" and write "reg"/EFLAGS. class BinOpMI8_RF : BinOpMI8, Sched<[WriteALU.Folded, WriteALU.ReadAfterFold]>, DefEFLAGS, NDD<1>; @@ -1237,6 +1260,12 @@ class BinOpMI8_M : BinOpMI8, Sched<[WriteALURMW]> { let mayStore = 1; } +// BinOpMI8U_M - Instructions that read "[mem], u8imm" and write "[mem]". +class BinOpMI8U_M + : BinOpMI8U { + let mayStore = 1; +} // BinOpMI8_MF - Instructions that read "[mem], imm8" and write "[mem]", EFLAGS. class BinOpMI8_MF : BinOpMI8, Sched<[WriteALURMW]>, DefEFLAGS { @@ -1278,6 +1307,28 @@ class BinOpAIF_AF o, string m, X86TypeInfo t, Register areg, let Defs = [areg, EFLAGS]; let SchedRW = [WriteADC]; } +// BinOpRC_R - Instructions that read "reg, cl" and write reg. +class BinOpRC_R + : ITy<0xD3, f, t, (outs t.RegClass:$dst), (ins t.RegClass:$src1), m, + !if(!eq(ndd, 0), binop_cl_args, binop_cl_ndd_args), + [(set t.RegClass:$dst, (node t.RegClass:$src1, CL))]>, NDD { + let Uses = [CL]; +} +// BinOpMC_M - Instructions that read "[mem], cl" and write [mem]. +class BinOpMC_M + : ITy<0xD3, f, t, (outs), (ins t.MemOperand:$src1), m, binop_cl_args, + [(store (node (t.LoadNode addr:$src1), CL), addr:$src1)]> { + let Uses = [CL]; + let mayLoad = 1; + let mayStore = 1; +} +// BinOpMC_R - Instructions that read "[mem], cl" and write reg. +class BinOpMC_R + : ITy<0xD3, f, t, (outs t.RegClass:$dst), (ins t.MemOperand:$src1), m, binop_cl_ndd_args, + [(set t.RegClass:$dst, (node (t.LoadNode addr:$src1), CL))]>, NDD<1> { + let Uses = [CL]; + let mayLoad = 1; +} // UnaryOpR - Instructions that read "reg". class UnaryOpR o, Format f, string m, string args, X86TypeInfo t, @@ -1285,13 +1336,13 @@ class UnaryOpR o, Format f, string m, string args, X86TypeInfo t, : ITy, Sched<[WriteALU]>; // UnaryOpR_R - Instructions that read "reg" and write "reg". class UnaryOpR_R o, Format f, string m, X86TypeInfo t, - SDPatternOperator node, bit ndd = 0> + SDPatternOperator node = null_frag, bit ndd = 0> : UnaryOpR, NDD; // UnaryOpR_RF - Instructions that read "reg" and write "reg"/EFLAGS. class UnaryOpR_RF o, Format f, string m, X86TypeInfo t, - SDPatternOperator node, bit ndd = 0> + SDPatternOperator node = null_frag, bit ndd = 0> : UnaryOpR o, Format f, string m, string args, X86TypeInfo t, } // UnaryOpM_R - Instructions that read "[mem]" and writes "reg". class UnaryOpM_R o, Format f, string m, X86TypeInfo t, - SDPatternOperator node> + SDPatternOperator node = null_frag> : UnaryOpM, Sched<[WriteALU.Folded, WriteALU.ReadAfterFold]>, NDD<1>; // UnaryOpM_RF - Instructions that read "[mem]" and writes "reg"/EFLAGS. class UnaryOpM_RF o, Format f, string m, X86TypeInfo t, - SDPatternOperator node> + SDPatternOperator node = null_frag> : UnaryOpM, Sched<[WriteALU.Folded, WriteALU.ReadAfterFold]>, DefEFLAGS, NDD<1>; // UnaryOpM_M - Instructions that read "[mem]" and writes "[mem]". class UnaryOpM_M o, Format f, string m, X86TypeInfo t, - SDPatternOperator node> + SDPatternOperator node = null_frag> : UnaryOpM, Sched<[WriteALURMW]>{ @@ -1325,7 +1376,7 @@ class UnaryOpM_M o, Format f, string m, X86TypeInfo t, } // UnaryOpM_MF - Instructions that read "[mem]" and writes "[mem]"/EFLAGS. class UnaryOpM_MF o, Format f, string m, X86TypeInfo t, - SDPatternOperator node> + SDPatternOperator node = null_frag> : UnaryOpM, Sched<[WriteALURMW]>, DefEFLAGS { diff --git a/llvm/lib/Target/X86/X86LoadValueInjectionLoadHardening.cpp b/llvm/lib/Target/X86/X86LoadValueInjectionLoadHardening.cpp index 2e492fa9c5e..4dfe7556df0 100644 --- a/llvm/lib/Target/X86/X86LoadValueInjectionLoadHardening.cpp +++ b/llvm/lib/Target/X86/X86LoadValueInjectionLoadHardening.cpp @@ -770,16 +770,13 @@ bool X86LoadValueInjectionLoadHardeningPass::instrUsesRegToAccessMemory( MI.getOpcode() == X86::SFENCE || MI.getOpcode() == X86::LFENCE) return false; - // FIXME: This does not handle pseudo loading instruction like TCRETURN* - const MCInstrDesc &Desc = MI.getDesc(); - int MemRefBeginIdx = X86II::getMemoryOperandNo(Desc.TSFlags); + const int MemRefBeginIdx = X86::getFirstAddrOperandIdx(MI); if (MemRefBeginIdx < 0) { LLVM_DEBUG(dbgs() << "Warning: unable to obtain memory operand for loading " "instruction:\n"; MI.print(dbgs()); dbgs() << '\n';); return false; } - MemRefBeginIdx += X86II::getOperandBias(Desc); const MachineOperand &BaseMO = MI.getOperand(MemRefBeginIdx + X86::AddrBaseReg); diff --git a/llvm/lib/Target/X86/X86LowerTileCopy.cpp b/llvm/lib/Target/X86/X86LowerTileCopy.cpp index d6b42145859..e7afc49240e 100644 --- a/llvm/lib/Target/X86/X86LowerTileCopy.cpp +++ b/llvm/lib/Target/X86/X86LowerTileCopy.cpp @@ -107,7 +107,8 @@ bool X86LowerTileCopy::runOnMachineFunction(MachineFunction &MF) { // mov 64 %rax BuildMI(MBB, MI, DL, TII->get(X86::MOV64ri), GR64Cand).addImm(64); // tilestored %tmm, (%sp, %idx) - unsigned Opc = X86::TILESTORED; +#define GET_EGPR_IF_ENABLED(OPC) (ST.hasEGPR() ? OPC##_EVEX : OPC) + unsigned Opc = GET_EGPR_IF_ENABLED(X86::TILESTORED); MachineInstr *NewMI = addFrameReference(BuildMI(MBB, MI, DL, TII->get(Opc)), TileSS) .addReg(SrcReg, getKillRegState(SrcMO.isKill())); @@ -115,7 +116,8 @@ bool X86LowerTileCopy::runOnMachineFunction(MachineFunction &MF) { MO.setReg(GR64Cand); MO.setIsKill(true); // tileloadd (%sp, %idx), %tmm - Opc = X86::TILELOADD; + Opc = GET_EGPR_IF_ENABLED(X86::TILELOADD); +#undef GET_EGPR_IF_ENABLED NewMI = addFrameReference(BuildMI(MBB, MI, DL, TII->get(Opc), DstReg), TileSS); // restore %rax diff --git a/llvm/lib/Target/X86/X86MCInstLower.cpp b/llvm/lib/Target/X86/X86MCInstLower.cpp index 133ee204156..58ebe023cd6 100644 --- a/llvm/lib/Target/X86/X86MCInstLower.cpp +++ b/llvm/lib/Target/X86/X86MCInstLower.cpp @@ -948,24 +948,22 @@ void X86AsmPrinter::LowerASAN_CHECK_MEMACCESS(const MachineInstr &MI) { void X86AsmPrinter::LowerPATCHABLE_OP(const MachineInstr &MI, X86MCInstLower &MCIL) { - // PATCHABLE_OP minsize, opcode, operands + // PATCHABLE_OP minsize NoAutoPaddingScope NoPadScope(*OutStreamer); - unsigned MinSize = MI.getOperand(0).getImm(); - unsigned Opcode = MI.getOperand(1).getImm(); - // Opcode PATCHABLE_OP is a special case: there is no instruction to wrap, - // simply emit a nop of size MinSize. - bool EmptyInst = (Opcode == TargetOpcode::PATCHABLE_OP); - - MCInst MCI; - MCI.setOpcode(Opcode); - for (auto &MO : drop_begin(MI.operands(), 2)) - if (auto MaybeOperand = MCIL.LowerMachineOperand(&MI, MO)) - MCI.addOperand(*MaybeOperand); + auto NextMI = std::find_if(std::next(MI.getIterator()), + MI.getParent()->end().getInstrIterator(), + [](auto &II) { return !II.isMetaInstruction(); }); SmallString<256> Code; - if (!EmptyInst) { + unsigned MinSize = MI.getOperand(0).getImm(); + + if (NextMI != MI.getParent()->end()) { + // Lower the next MachineInstr to find its byte size. + MCInst MCI; + MCIL.Lower(&*NextMI, MCI); + SmallVector Fixups; CodeEmitter->encodeInstruction(MCI, Code, Fixups, getSubtargetInfo()); } @@ -981,21 +979,12 @@ void X86AsmPrinter::LowerPATCHABLE_OP(const MachineInstr &MI, OutStreamer->emitInstruction( MCInstBuilder(X86::MOV32rr_REV).addReg(X86::EDI).addReg(X86::EDI), *Subtarget); - } else if (MinSize == 2 && Opcode == X86::PUSH64r) { - // This is an optimization that lets us get away without emitting a nop in - // many cases. - // - // NB! In some cases the encoding for PUSH64r (e.g. PUSH64r %r9) takes two - // bytes too, so the check on MinSize is important. - MCI.setOpcode(X86::PUSH64rmr); } else { unsigned NopSize = emitNop(*OutStreamer, MinSize, Subtarget); assert(NopSize == MinSize && "Could not implement MinSize!"); (void)NopSize; } } - if (!EmptyInst) - OutStreamer->emitInstruction(MCI, getSubtargetInfo()); } // Lower a stackmap of the form: @@ -1399,23 +1388,6 @@ PrevCrossBBInst(MachineBasicBlock::const_iterator MBBI) { return MBBI; } -static const Constant *getConstantFromPool(const MachineInstr &MI, - const MachineOperand &Op) { - if (!Op.isCPI() || Op.getOffset() != 0) - return nullptr; - - ArrayRef Constants = - MI.getParent()->getParent()->getConstantPool()->getConstants(); - const MachineConstantPoolEntry &ConstantEntry = Constants[Op.getIndex()]; - - // Bail if this is a machine constant pool entry, we won't be able to dig out - // anything useful. - if (ConstantEntry.isMachineConstantPoolEntry()) - return nullptr; - - return ConstantEntry.Val.ConstVal; -} - static std::string getShuffleComment(const MachineInstr *MI, unsigned SrcOp1Idx, unsigned SrcOp2Idx, ArrayRef Mask) { std::string Comment; @@ -1501,58 +1473,115 @@ static std::string getShuffleComment(const MachineInstr *MI, unsigned SrcOp1Idx, return Comment; } -static void printConstant(const APInt &Val, raw_ostream &CS) { +static void printConstant(const APInt &Val, raw_ostream &CS, + bool PrintZero = false) { if (Val.getBitWidth() <= 64) { - CS << Val.getZExtValue(); + CS << (PrintZero ? 0ULL : Val.getZExtValue()); } else { // print multi-word constant as (w0,w1) CS << "("; for (int i = 0, N = Val.getNumWords(); i < N; ++i) { if (i > 0) CS << ","; - CS << Val.getRawData()[i]; + CS << (PrintZero ? 0ULL : Val.getRawData()[i]); } CS << ")"; } } -static void printConstant(const APFloat &Flt, raw_ostream &CS) { +static void printConstant(const APFloat &Flt, raw_ostream &CS, + bool PrintZero = false) { SmallString<32> Str; - // Force scientific notation to distinquish from integers. - Flt.toString(Str, 0, 0); + // Force scientific notation to distinguish from integers. + if (PrintZero) + APFloat::getZero(Flt.getSemantics()).toString(Str, 0, 0); + else + Flt.toString(Str, 0, 0); CS << Str; } static void printConstant(const Constant *COp, unsigned BitWidth, - raw_ostream &CS) { + raw_ostream &CS, bool PrintZero = false) { if (isa(COp)) { CS << "u"; } else if (auto *CI = dyn_cast(COp)) { - printConstant(CI->getValue(), CS); + printConstant(CI->getValue(), CS, PrintZero); } else if (auto *CF = dyn_cast(COp)) { - printConstant(CF->getValueAPF(), CS); + printConstant(CF->getValueAPF(), CS, PrintZero); } else if (auto *CDS = dyn_cast(COp)) { Type *EltTy = CDS->getElementType(); bool IsInteger = EltTy->isIntegerTy(); bool IsFP = EltTy->isHalfTy() || EltTy->isFloatTy() || EltTy->isDoubleTy(); unsigned EltBits = EltTy->getPrimitiveSizeInBits(); unsigned E = std::min(BitWidth / EltBits, CDS->getNumElements()); - assert((BitWidth % EltBits) == 0 && "Broadcast element size mismatch"); + assert((BitWidth % EltBits) == 0 && "Element size mismatch"); for (unsigned I = 0; I != E; ++I) { if (I != 0) CS << ","; if (IsInteger) - printConstant(CDS->getElementAsAPInt(I), CS); + printConstant(CDS->getElementAsAPInt(I), CS, PrintZero); else if (IsFP) - printConstant(CDS->getElementAsAPFloat(I), CS); + printConstant(CDS->getElementAsAPFloat(I), CS, PrintZero); else CS << "?"; } + } else if (auto *CV = dyn_cast(COp)) { + unsigned EltBits = CV->getType()->getScalarSizeInBits(); + unsigned E = std::min(BitWidth / EltBits, CV->getNumOperands()); + assert((BitWidth % EltBits) == 0 && "Element size mismatch"); + for (unsigned I = 0; I != E; ++I) { + if (I != 0) + CS << ","; + printConstant(CV->getOperand(I), EltBits, CS, PrintZero); + } } else { CS << "?"; } } +static void printZeroUpperMove(const MachineInstr *MI, MCStreamer &OutStreamer, + int SclWidth, int VecWidth, + const char *ShuffleComment) { + std::string Comment; + raw_string_ostream CS(Comment); + const MachineOperand &DstOp = MI->getOperand(0); + CS << X86ATTInstPrinter::getRegisterName(DstOp.getReg()) << " = "; + + if (auto *C = X86::getConstantFromPool(*MI, 1)) { + CS << "["; + printConstant(C, SclWidth, CS); + for (int I = 1, E = VecWidth / SclWidth; I < E; ++I) { + CS << ","; + printConstant(C, SclWidth, CS, true); + } + CS << "]"; + OutStreamer.AddComment(CS.str()); + return; // early-out + } + + // We didn't find a constant load, fallback to a shuffle mask decode. + CS << ShuffleComment; + OutStreamer.AddComment(CS.str()); +} + +static void printBroadcast(const MachineInstr *MI, MCStreamer &OutStreamer, + int Repeats, int BitWidth) { + if (auto *C = X86::getConstantFromPool(*MI, 1)) { + std::string Comment; + raw_string_ostream CS(Comment); + const MachineOperand &DstOp = MI->getOperand(0); + CS << X86ATTInstPrinter::getRegisterName(DstOp.getReg()) << " = "; + CS << "["; + for (int l = 0; l != Repeats; ++l) { + if (l != 0) + CS << ","; + printConstant(C, BitWidth, CS); + } + CS << "]"; + OutStreamer.AddComment(CS.str()); + } +} + void X86AsmPrinter::EmitSEHInstruction(const MachineInstr *MI) { assert(MF->hasWinCFI() && "SEH_ instruction in function without WinCFI?"); assert((getSubtarget().isOSWindows() || TM.getTargetTriple().isUEFI()) && @@ -1668,13 +1697,8 @@ static void addConstantComments(const MachineInstr *MI, ++SrcIdx; } } - unsigned MaskIdx = SrcIdx + 1 + X86::AddrDisp; - assert(MI->getNumOperands() >= (SrcIdx + 1 + X86::AddrNumOperands) && - "Unexpected number of operands!"); - - const MachineOperand &MaskOp = MI->getOperand(MaskIdx); - if (auto *C = getConstantFromPool(*MI, MaskOp)) { + if (auto *C = X86::getConstantFromPool(*MI, SrcIdx + 1)) { unsigned Width = getRegisterWidth(MI->getDesc().operands()[0]); SmallVector Mask; DecodePSHUFBMask(C, Width, Mask); @@ -1746,13 +1770,8 @@ static void addConstantComments(const MachineInstr *MI, ++SrcIdx; } } - unsigned MaskIdx = SrcIdx + 1 + X86::AddrDisp; - assert(MI->getNumOperands() >= (SrcIdx + 1 + X86::AddrNumOperands) && - "Unexpected number of operands!"); - - const MachineOperand &MaskOp = MI->getOperand(MaskIdx); - if (auto *C = getConstantFromPool(*MI, MaskOp)) { + if (auto *C = X86::getConstantFromPool(*MI, SrcIdx + 1)) { unsigned Width = getRegisterWidth(MI->getDesc().operands()[0]); SmallVector Mask; DecodeVPERMILPMask(C, ElSize, Width, Mask); @@ -1780,8 +1799,7 @@ static void addConstantComments(const MachineInstr *MI, case X86::VPERMIL2PDrm: case X86::VPERMIL2PDYrm: ElSize = 64; break; } - const MachineOperand &MaskOp = MI->getOperand(3 + X86::AddrDisp); - if (auto *C = getConstantFromPool(*MI, MaskOp)) { + if (auto *C = X86::getConstantFromPool(*MI, 3)) { unsigned Width = getRegisterWidth(MI->getDesc().operands()[0]); SmallVector Mask; DecodeVPERMIL2PMask(C, (unsigned)CtrlOp.getImm(), ElSize, Width, Mask); @@ -1792,11 +1810,7 @@ static void addConstantComments(const MachineInstr *MI, } case X86::VPPERMrrm: { - assert(MI->getNumOperands() >= (3 + X86::AddrNumOperands) && - "Unexpected number of operands!"); - - const MachineOperand &MaskOp = MI->getOperand(3 + X86::AddrDisp); - if (auto *C = getConstantFromPool(*MI, MaskOp)) { + if (auto *C = X86::getConstantFromPool(*MI, 3)) { unsigned Width = getRegisterWidth(MI->getDesc().operands()[0]); SmallVector Mask; DecodeVPPERMMask(C, Width, Mask); @@ -1807,9 +1821,7 @@ static void addConstantComments(const MachineInstr *MI, } case X86::MMX_MOVQ64rm: { - assert(MI->getNumOperands() == (1 + X86::AddrNumOperands) && - "Unexpected number of operands!"); - if (auto *C = getConstantFromPool(*MI, MI->getOperand(1 + X86::AddrDisp))) { + if (auto *C = X86::getConstantFromPool(*MI, 1)) { std::string Comment; raw_string_ostream CS(Comment); const MachineOperand &DstOp = MI->getOperand(0); @@ -1822,6 +1834,30 @@ static void addConstantComments(const MachineInstr *MI, break; } + case X86::MOVSDrm: + case X86::VMOVSDrm: + case X86::VMOVSDZrm: + case X86::MOVSDrm_alt: + case X86::VMOVSDrm_alt: + case X86::VMOVSDZrm_alt: + case X86::MOVQI2PQIrm: + case X86::VMOVQI2PQIrm: + case X86::VMOVQI2PQIZrm: + printZeroUpperMove(MI, OutStreamer, 64, 128, "mem[0],zero"); + break; + + case X86::MOVSSrm: + case X86::VMOVSSrm: + case X86::VMOVSSZrm: + case X86::MOVSSrm_alt: + case X86::VMOVSSrm_alt: + case X86::VMOVSSZrm_alt: + case X86::MOVDI2PDIrm: + case X86::VMOVDI2PDIrm: + case X86::VMOVDI2PDIZrm: + printZeroUpperMove(MI, OutStreamer, 32, 128, "mem[0],zero,zero,zero"); + break; + #define MOV_CASE(Prefix, Suffix) \ case X86::Prefix##MOVAPD##Suffix##rm: \ case X86::Prefix##MOVAPS##Suffix##rm: \ @@ -1854,186 +1890,95 @@ static void addConstantComments(const MachineInstr *MI, #define CASE_512_MOV_RM() \ MOV_AVX512_CASE(Z) -#define CASE_ALL_MOV_RM() \ - MOV_CASE(, ) /* SSE */ \ - MOV_CASE(V, ) /* AVX-128 */ \ - MOV_CASE(V, Y) /* AVX-256 */ \ - MOV_AVX512_CASE(Z) \ - MOV_AVX512_CASE(Z256) \ - MOV_AVX512_CASE(Z128) - // For loads from a constant pool to a vector register, print the constant // loaded. - CASE_ALL_MOV_RM() + CASE_128_MOV_RM() + printBroadcast(MI, OutStreamer, 1, 128); + break; + CASE_256_MOV_RM() + printBroadcast(MI, OutStreamer, 1, 256); + break; + CASE_512_MOV_RM() + printBroadcast(MI, OutStreamer, 1, 512); + break; case X86::VBROADCASTF128rm: case X86::VBROADCASTI128rm: case X86::VBROADCASTF32X4Z256rm: - case X86::VBROADCASTF32X4rm: - case X86::VBROADCASTF32X8rm: case X86::VBROADCASTF64X2Z128rm: - case X86::VBROADCASTF64X2rm: - case X86::VBROADCASTF64X4rm: case X86::VBROADCASTI32X4Z256rm: - case X86::VBROADCASTI32X4rm: - case X86::VBROADCASTI32X8rm: case X86::VBROADCASTI64X2Z128rm: + printBroadcast(MI, OutStreamer, 2, 128); + break; + case X86::VBROADCASTF32X4rm: + case X86::VBROADCASTF64X2rm: + case X86::VBROADCASTI32X4rm: case X86::VBROADCASTI64X2rm: + printBroadcast(MI, OutStreamer, 4, 128); + break; + case X86::VBROADCASTF32X8rm: + case X86::VBROADCASTF64X4rm: + case X86::VBROADCASTI32X8rm: case X86::VBROADCASTI64X4rm: - assert(MI->getNumOperands() >= (1 + X86::AddrNumOperands) && - "Unexpected number of operands!"); - if (auto *C = getConstantFromPool(*MI, MI->getOperand(1 + X86::AddrDisp))) { - int NumLanes = 1; - int BitWidth = 128; - int CstEltSize = C->getType()->getScalarSizeInBits(); - - // Get destination BitWidth + override NumLanes for the broadcasts. - switch (MI->getOpcode()) { - CASE_128_MOV_RM() NumLanes = 1; BitWidth = 128; break; - CASE_256_MOV_RM() NumLanes = 1; BitWidth = 256; break; - CASE_512_MOV_RM() NumLanes = 1; BitWidth = 512; break; - case X86::VBROADCASTF128rm: NumLanes = 2; BitWidth = 128; break; - case X86::VBROADCASTI128rm: NumLanes = 2; BitWidth = 128; break; - case X86::VBROADCASTF32X4Z256rm: NumLanes = 2; BitWidth = 128; break; - case X86::VBROADCASTF32X4rm: NumLanes = 4; BitWidth = 128; break; - case X86::VBROADCASTF32X8rm: NumLanes = 2; BitWidth = 256; break; - case X86::VBROADCASTF64X2Z128rm: NumLanes = 2; BitWidth = 128; break; - case X86::VBROADCASTF64X2rm: NumLanes = 4; BitWidth = 128; break; - case X86::VBROADCASTF64X4rm: NumLanes = 2; BitWidth = 256; break; - case X86::VBROADCASTI32X4Z256rm: NumLanes = 2; BitWidth = 128; break; - case X86::VBROADCASTI32X4rm: NumLanes = 4; BitWidth = 128; break; - case X86::VBROADCASTI32X8rm: NumLanes = 2; BitWidth = 256; break; - case X86::VBROADCASTI64X2Z128rm: NumLanes = 2; BitWidth = 128; break; - case X86::VBROADCASTI64X2rm: NumLanes = 4; BitWidth = 128; break; - case X86::VBROADCASTI64X4rm: NumLanes = 2; BitWidth = 256; break; - } - - std::string Comment; - raw_string_ostream CS(Comment); - const MachineOperand &DstOp = MI->getOperand(0); - CS << X86ATTInstPrinter::getRegisterName(DstOp.getReg()) << " = "; - if (auto *CDS = dyn_cast(C)) { - int NumElements = CDS->getNumElements(); - if ((BitWidth % CstEltSize) == 0) - NumElements = std::min(NumElements, BitWidth / CstEltSize); - CS << "["; - for (int l = 0; l != NumLanes; ++l) { - for (int i = 0; i < NumElements; ++i) { - if (i != 0 || l != 0) - CS << ","; - if (CDS->getElementType()->isIntegerTy()) - printConstant(CDS->getElementAsAPInt(i), CS); - else if (CDS->getElementType()->isHalfTy() || - CDS->getElementType()->isFloatTy() || - CDS->getElementType()->isDoubleTy()) - printConstant(CDS->getElementAsAPFloat(i), CS); - else - CS << "?"; - } - } - CS << "]"; - OutStreamer.AddComment(CS.str()); - } else if (auto *CV = dyn_cast(C)) { - int NumOperands = CV->getNumOperands(); - if ((BitWidth % CstEltSize) == 0) - NumOperands = std::min(NumOperands, BitWidth / CstEltSize); - CS << "<"; - for (int l = 0; l != NumLanes; ++l) { - for (int i = 0; i < NumOperands; ++i) { - if (i != 0 || l != 0) - CS << ","; - printConstant(CV->getOperand(i), - CV->getType()->getPrimitiveSizeInBits(), CS); - } - } - CS << ">"; - OutStreamer.AddComment(CS.str()); - } - } + printBroadcast(MI, OutStreamer, 2, 256); break; + // For broadcast loads from a constant pool to a vector register, repeatedly + // print the constant loaded. case X86::MOVDDUPrm: case X86::VMOVDDUPrm: case X86::VMOVDDUPZ128rm: - case X86::VBROADCASTSSrm: - case X86::VBROADCASTSSYrm: - case X86::VBROADCASTSSZ128rm: - case X86::VBROADCASTSSZ256rm: - case X86::VBROADCASTSSZrm: + case X86::VPBROADCASTQrm: + case X86::VPBROADCASTQZ128rm: + printBroadcast(MI, OutStreamer, 2, 64); + break; case X86::VBROADCASTSDYrm: case X86::VBROADCASTSDZ256rm: - case X86::VBROADCASTSDZrm: - case X86::VPBROADCASTBrm: - case X86::VPBROADCASTBYrm: - case X86::VPBROADCASTBZ128rm: - case X86::VPBROADCASTBZ256rm: - case X86::VPBROADCASTBZrm: - case X86::VPBROADCASTDrm: - case X86::VPBROADCASTDYrm: - case X86::VPBROADCASTDZ128rm: - case X86::VPBROADCASTDZ256rm: - case X86::VPBROADCASTDZrm: - case X86::VPBROADCASTQrm: case X86::VPBROADCASTQYrm: - case X86::VPBROADCASTQZ128rm: case X86::VPBROADCASTQZ256rm: + printBroadcast(MI, OutStreamer, 4, 64); + break; + case X86::VBROADCASTSDZrm: case X86::VPBROADCASTQZrm: + printBroadcast(MI, OutStreamer, 8, 64); + break; + case X86::VBROADCASTSSrm: + case X86::VBROADCASTSSZ128rm: + case X86::VPBROADCASTDrm: + case X86::VPBROADCASTDZ128rm: + printBroadcast(MI, OutStreamer, 4, 32); + break; + case X86::VBROADCASTSSYrm: + case X86::VBROADCASTSSZ256rm: + case X86::VPBROADCASTDYrm: + case X86::VPBROADCASTDZ256rm: + printBroadcast(MI, OutStreamer, 8, 32); + break; + case X86::VBROADCASTSSZrm: + case X86::VPBROADCASTDZrm: + printBroadcast(MI, OutStreamer, 16, 32); + break; case X86::VPBROADCASTWrm: - case X86::VPBROADCASTWYrm: case X86::VPBROADCASTWZ128rm: + printBroadcast(MI, OutStreamer, 8, 16); + break; + case X86::VPBROADCASTWYrm: case X86::VPBROADCASTWZ256rm: + printBroadcast(MI, OutStreamer, 16, 16); + break; case X86::VPBROADCASTWZrm: - assert(MI->getNumOperands() >= (1 + X86::AddrNumOperands) && - "Unexpected number of operands!"); - if (auto *C = getConstantFromPool(*MI, MI->getOperand(1 + X86::AddrDisp))) { - int NumElts, EltBits; - switch (MI->getOpcode()) { - default: llvm_unreachable("Invalid opcode"); - case X86::MOVDDUPrm: NumElts = 2; EltBits = 64; break; - case X86::VMOVDDUPrm: NumElts = 2; EltBits = 64; break; - case X86::VMOVDDUPZ128rm: NumElts = 2; EltBits = 64; break; - case X86::VBROADCASTSSrm: NumElts = 4; EltBits = 32; break; - case X86::VBROADCASTSSYrm: NumElts = 8; EltBits = 32; break; - case X86::VBROADCASTSSZ128rm: NumElts = 4; EltBits = 32; break; - case X86::VBROADCASTSSZ256rm: NumElts = 8; EltBits = 32; break; - case X86::VBROADCASTSSZrm: NumElts = 16; EltBits = 32; break; - case X86::VBROADCASTSDYrm: NumElts = 4; EltBits = 64; break; - case X86::VBROADCASTSDZ256rm: NumElts = 4; EltBits = 64; break; - case X86::VBROADCASTSDZrm: NumElts = 8; EltBits = 64; break; - case X86::VPBROADCASTBrm: NumElts = 16; EltBits = 8; break; - case X86::VPBROADCASTBYrm: NumElts = 32; EltBits = 8; break; - case X86::VPBROADCASTBZ128rm: NumElts = 16; EltBits = 8; break; - case X86::VPBROADCASTBZ256rm: NumElts = 32; EltBits = 8; break; - case X86::VPBROADCASTBZrm: NumElts = 64; EltBits = 8; break; - case X86::VPBROADCASTDrm: NumElts = 4; EltBits = 32; break; - case X86::VPBROADCASTDYrm: NumElts = 8; EltBits = 32; break; - case X86::VPBROADCASTDZ128rm: NumElts = 4; EltBits = 32; break; - case X86::VPBROADCASTDZ256rm: NumElts = 8; EltBits = 32; break; - case X86::VPBROADCASTDZrm: NumElts = 16; EltBits = 32; break; - case X86::VPBROADCASTQrm: NumElts = 2; EltBits = 64; break; - case X86::VPBROADCASTQYrm: NumElts = 4; EltBits = 64; break; - case X86::VPBROADCASTQZ128rm: NumElts = 2; EltBits = 64; break; - case X86::VPBROADCASTQZ256rm: NumElts = 4; EltBits = 64; break; - case X86::VPBROADCASTQZrm: NumElts = 8; EltBits = 64; break; - case X86::VPBROADCASTWrm: NumElts = 8; EltBits = 16; break; - case X86::VPBROADCASTWYrm: NumElts = 16; EltBits = 16; break; - case X86::VPBROADCASTWZ128rm: NumElts = 8; EltBits = 16; break; - case X86::VPBROADCASTWZ256rm: NumElts = 16; EltBits = 16; break; - case X86::VPBROADCASTWZrm: NumElts = 32; EltBits = 16; break; - } - - std::string Comment; - raw_string_ostream CS(Comment); - const MachineOperand &DstOp = MI->getOperand(0); - CS << X86ATTInstPrinter::getRegisterName(DstOp.getReg()) << " = "; - CS << "["; - for (int i = 0; i != NumElts; ++i) { - if (i != 0) - CS << ","; - printConstant(C, EltBits, CS); - } - CS << "]"; - OutStreamer.AddComment(CS.str()); - } + printBroadcast(MI, OutStreamer, 32, 16); + break; + case X86::VPBROADCASTBrm: + case X86::VPBROADCASTBZ128rm: + printBroadcast(MI, OutStreamer, 16, 8); + break; + case X86::VPBROADCASTBYrm: + case X86::VPBROADCASTBZ256rm: + printBroadcast(MI, OutStreamer, 32, 8); + break; + case X86::VPBROADCASTBZrm: + printBroadcast(MI, OutStreamer, 64, 8); + break; } } @@ -2055,18 +2000,20 @@ void X86AsmPrinter::emitInstruction(const MachineInstr *MI) { } } + // Add comments for values loaded from constant pool. + if (OutStreamer->isVerboseAsm()) + addConstantComments(MI, *OutStreamer); + // Add a comment about EVEX compression if (TM.Options.MCOptions.ShowMCEncoding) { if (MI->getAsmPrinterFlags() & X86::AC_EVEX_2_LEGACY) OutStreamer->AddComment("EVEX TO LEGACY Compression ", false); else if (MI->getAsmPrinterFlags() & X86::AC_EVEX_2_VEX) OutStreamer->AddComment("EVEX TO VEX Compression ", false); + else if (MI->getAsmPrinterFlags() & X86::AC_EVEX_2_EVEX) + OutStreamer->AddComment("EVEX TO EVEX Compression ", false); } - // Add comments for values loaded from constant pool. - if (OutStreamer->isVerboseAsm()) - addConstantComments(MI, *OutStreamer); - switch (MI->getOpcode()) { case TargetOpcode::DBG_VALUE: llvm_unreachable("Should be handled target independently"); diff --git a/llvm/lib/Target/X86/X86PfmCounters.td b/llvm/lib/Target/X86/X86PfmCounters.td index 48d68954970..da3acc5bbf5 100644 --- a/llvm/lib/Target/X86/X86PfmCounters.td +++ b/llvm/lib/Target/X86/X86PfmCounters.td @@ -19,7 +19,12 @@ def : PfmCountersDefaultBinding; // Intel X86 Counters. defvar DefaultIntelPfmValidationCounters = [ - PfmValidationCounter + PfmValidationCounter, + PfmValidationCounter, + PfmValidationCounter, + PfmValidationCounter, + PfmValidationCounter, + PfmValidationCounter ]; def PentiumPfmCounters : ProcPfmCounters { @@ -200,7 +205,12 @@ def : PfmCountersBinding<"tigerlake", IceLakePfmCounters>; // AMD X86 Counters. defvar DefaultAMDPfmValidationCounters = [ - PfmValidationCounter + PfmValidationCounter, + PfmValidationCounter, + PfmValidationCounter, + PfmValidationCounter, + PfmValidationCounter, + PfmValidationCounter ]; // Set basic counters for AMD cpus that we know libpfm4 supports. diff --git a/llvm/lib/Target/X86/X86SpeculativeLoadHardening.cpp b/llvm/lib/Target/X86/X86SpeculativeLoadHardening.cpp index 6301285fe95..69a54e7667b 100644 --- a/llvm/lib/Target/X86/X86SpeculativeLoadHardening.cpp +++ b/llvm/lib/Target/X86/X86SpeculativeLoadHardening.cpp @@ -1317,12 +1317,7 @@ void X86SpeculativeLoadHardeningPass::tracePredStateThroughBlocksAndHarden( continue; // Extract the memory operand information about this instruction. - // FIXME: This doesn't handle loading pseudo instructions which we often - // could handle with similarly generic logic. We probably need to add an - // MI-layer routine similar to the MC-layer one we use here which maps - // pseudos much like this maps real instructions. - const MCInstrDesc &Desc = MI.getDesc(); - int MemRefBeginIdx = X86II::getMemoryOperandNo(Desc.TSFlags); + const int MemRefBeginIdx = X86::getFirstAddrOperandIdx(MI); if (MemRefBeginIdx < 0) { LLVM_DEBUG(dbgs() << "WARNING: unable to harden loading instruction: "; @@ -1330,8 +1325,6 @@ void X86SpeculativeLoadHardeningPass::tracePredStateThroughBlocksAndHarden( continue; } - MemRefBeginIdx += X86II::getOperandBias(Desc); - MachineOperand &BaseMO = MI.getOperand(MemRefBeginIdx + X86::AddrBaseReg); MachineOperand &IndexMO = @@ -1400,12 +1393,9 @@ void X86SpeculativeLoadHardeningPass::tracePredStateThroughBlocksAndHarden( // Check if this is a load whose address needs to be hardened. if (HardenLoadAddr.erase(&MI)) { - const MCInstrDesc &Desc = MI.getDesc(); - int MemRefBeginIdx = X86II::getMemoryOperandNo(Desc.TSFlags); + const int MemRefBeginIdx = X86::getFirstAddrOperandIdx(MI); assert(MemRefBeginIdx >= 0 && "Cannot have an invalid index here!"); - MemRefBeginIdx += X86II::getOperandBias(Desc); - MachineOperand &BaseMO = MI.getOperand(MemRefBeginIdx + X86::AddrBaseReg); MachineOperand &IndexMO = @@ -1802,11 +1792,9 @@ MachineInstr *X86SpeculativeLoadHardeningPass::sinkPostLoadHardenedInst( // Otherwise, this is a load and the load component can't be data // invariant so check how this register is being used. - const MCInstrDesc &Desc = UseMI.getDesc(); - int MemRefBeginIdx = X86II::getMemoryOperandNo(Desc.TSFlags); + const int MemRefBeginIdx = X86::getFirstAddrOperandIdx(UseMI); assert(MemRefBeginIdx >= 0 && "Should always have mem references here!"); - MemRefBeginIdx += X86II::getOperandBias(Desc); MachineOperand &BaseMO = UseMI.getOperand(MemRefBeginIdx + X86::AddrBaseReg); @@ -1840,7 +1828,7 @@ MachineInstr *X86SpeculativeLoadHardeningPass::sinkPostLoadHardenedInst( // just bail. Also check that its register class is one of the ones we // can harden. Register UseDefReg = UseMI.getOperand(0).getReg(); - if (!UseDefReg.isVirtual() || !canHardenRegister(UseDefReg)) + if (!canHardenRegister(UseDefReg)) return {}; SingleUseMI = &UseMI; @@ -1863,6 +1851,10 @@ MachineInstr *X86SpeculativeLoadHardeningPass::sinkPostLoadHardenedInst( } bool X86SpeculativeLoadHardeningPass::canHardenRegister(Register Reg) { + // We only support hardening virtual registers. + if (!Reg.isVirtual()) + return false; + auto *RC = MRI->getRegClass(Reg); int RegBytes = TRI->getRegSizeInBits(*RC) / 8; if (RegBytes > 8) @@ -1909,7 +1901,6 @@ unsigned X86SpeculativeLoadHardeningPass::hardenValueInRegister( Register Reg, MachineBasicBlock &MBB, MachineBasicBlock::iterator InsertPt, const DebugLoc &Loc) { assert(canHardenRegister(Reg) && "Cannot harden this register!"); - assert(Reg.isVirtual() && "Cannot harden a physical register!"); auto *RC = MRI->getRegClass(Reg); int Bytes = TRI->getRegSizeInBits(*RC) / 8; diff --git a/llvm/lib/Target/X86/X86TargetMachine.cpp b/llvm/lib/Target/X86/X86TargetMachine.cpp index b92bffbe623..9e4cf1ea996 100644 --- a/llvm/lib/Target/X86/X86TargetMachine.cpp +++ b/llvm/lib/Target/X86/X86TargetMachine.cpp @@ -113,6 +113,9 @@ static std::unique_ptr createTLOF(const Triple &TT) { if (TT.isOSBinFormatCOFF()) return std::make_unique(); + + if (TT.getArch() == Triple::x86_64) + return std::make_unique(); return std::make_unique(); } diff --git a/llvm/lib/Target/X86/X86TargetMachine.h b/llvm/lib/Target/X86/X86TargetMachine.h index 4836be4db0e..f31c971df95 100644 --- a/llvm/lib/Target/X86/X86TargetMachine.h +++ b/llvm/lib/Target/X86/X86TargetMachine.h @@ -58,6 +58,12 @@ public: createMachineFunctionInfo(BumpPtrAllocator &Allocator, const Function &F, const TargetSubtargetInfo *STI) const override; + Error buildCodeGenPipeline(ModulePassManager &, MachineFunctionPassManager &, + MachineFunctionAnalysisManager &, + raw_pwrite_stream &, raw_pwrite_stream *, + CodeGenFileType, CGPassBuilderOption, + PassInstrumentationCallbacks *) override; + bool isJIT() const { return IsJIT; } bool isNoopAddrSpaceCast(unsigned SrcAS, unsigned DestAS) const override; diff --git a/llvm/lib/Target/X86/X86TargetObjectFile.cpp b/llvm/lib/Target/X86/X86TargetObjectFile.cpp index 53c692060f0..e2ddf43e398 100644 --- a/llvm/lib/Target/X86/X86TargetObjectFile.cpp +++ b/llvm/lib/Target/X86/X86TargetObjectFile.cpp @@ -57,7 +57,7 @@ const MCExpr *X86ELFTargetObjectFile::getDebugThreadLocalSymbol( return MCSymbolRefExpr::create(Sym, MCSymbolRefExpr::VK_DTPOFF, getContext()); } -const MCExpr *X86ELFTargetObjectFile::getIndirectSymViaGOTPCRel( +const MCExpr *X86_64ELFTargetObjectFile::getIndirectSymViaGOTPCRel( const GlobalValue *GV, const MCSymbol *Sym, const MCValue &MV, int64_t Offset, MachineModuleInfo *MMI, MCStreamer &Streamer) const { int64_t FinalOffset = Offset + MV.getConstant(); diff --git a/llvm/lib/Target/X86/X86TargetObjectFile.h b/llvm/lib/Target/X86/X86TargetObjectFile.h index ed9390d1fad..a0e1762a2cb 100644 --- a/llvm/lib/Target/X86/X86TargetObjectFile.h +++ b/llvm/lib/Target/X86/X86TargetObjectFile.h @@ -36,16 +36,22 @@ namespace llvm { MCStreamer &Streamer) const override; }; - /// This implementation is used for X86 ELF targets that don't - /// have a further specialization. + /// This implementation is used for X86 ELF targets that don't have a further + /// specialization (and as a base class for X86_64, which does). class X86ELFTargetObjectFile : public TargetLoweringObjectFileELF { public: X86ELFTargetObjectFile() { PLTRelativeVariantKind = MCSymbolRefExpr::VK_PLT; - SupportIndirectSymViaGOTPCRel = true; } /// Describe a TLS variable address within debug info. const MCExpr *getDebugThreadLocalSymbol(const MCSymbol *Sym) const override; + }; + + /// This implementation is used for X86_64 ELF targets, and defers to + /// X86ELFTargetObjectFile for commonalities with 32-bit targets. + class X86_64ELFTargetObjectFile : public X86ELFTargetObjectFile { + public: + X86_64ELFTargetObjectFile() { SupportIndirectSymViaGOTPCRel = true; } const MCExpr * getIndirectSymViaGOTPCRel(const GlobalValue *GV, const MCSymbol *Sym, diff --git a/llvm/lib/TargetParser/AArch64TargetParser.cpp b/llvm/lib/TargetParser/AArch64TargetParser.cpp index d3c72497c41..fd47f786a46 100644 --- a/llvm/lib/TargetParser/AArch64TargetParser.cpp +++ b/llvm/lib/TargetParser/AArch64TargetParser.cpp @@ -12,12 +12,15 @@ //===----------------------------------------------------------------------===// #include "llvm/TargetParser/AArch64TargetParser.h" +#include "llvm/Support/Debug.h" #include "llvm/Support/Format.h" #include "llvm/Support/raw_ostream.h" #include "llvm/TargetParser/ARMTargetParserCommon.h" #include "llvm/TargetParser/Triple.h" #include +#define DEBUG_TYPE "target-parser" + using namespace llvm; static unsigned checkArchVersion(llvm::StringRef Arch) { @@ -26,15 +29,15 @@ static unsigned checkArchVersion(llvm::StringRef Arch) { return 0; } -std::optional AArch64::getArchForCpu(StringRef CPU) { +const AArch64::ArchInfo *AArch64::getArchForCpu(StringRef CPU) { if (CPU == "generic") - return ARMV8A; + return &ARMV8A; // Note: this now takes cpu aliases into account std::optional Cpu = parseCpu(CPU); if (!Cpu) - return {}; - return Cpu->Arch; + return nullptr; + return &Cpu->Arch; } std::optional AArch64::ArchInfo::findBySubArch(StringRef SubArch) { @@ -47,11 +50,8 @@ std::optional AArch64::ArchInfo::findBySubArch(StringRef SubA uint64_t AArch64::getCpuSupportsMask(ArrayRef FeatureStrs) { uint64_t FeaturesMask = 0; for (const StringRef &FeatureStr : FeatureStrs) { - for (const auto &E : llvm::AArch64::Extensions) - if (FeatureStr == E.Name) { - FeaturesMask |= (1ULL << E.CPUFeature); - break; - } + if (auto Ext = parseArchExtension(FeatureStr)) + FeaturesMask |= (1ULL << Ext->CPUFeature); } return FeaturesMask; } @@ -75,17 +75,14 @@ StringRef AArch64::resolveCPUAlias(StringRef Name) { } StringRef AArch64::getArchExtFeature(StringRef ArchExt) { - if (ArchExt.starts_with("no")) { - StringRef ArchExtBase(ArchExt.substr(2)); - for (const auto &AE : Extensions) { - if (!AE.NegFeature.empty() && ArchExtBase == AE.Name) - return AE.NegFeature; - } + bool IsNegated = ArchExt.starts_with("no"); + StringRef ArchExtBase = IsNegated ? ArchExt.drop_front(2) : ArchExt; + + if (auto AE = parseArchExtension(ArchExtBase)) { + // Note: the returned string can be empty. + return IsNegated ? AE->NegFeature : AE->Feature; } - for (const auto &AE : Extensions) - if (!AE.Feature.empty() && ArchExt == AE.Name) - return AE.Feature; return StringRef(); } @@ -103,7 +100,7 @@ bool AArch64::isX18ReservedByDefault(const Triple &TT) { } // Allows partial match, ex. "v8a" matches "armv8a". -std::optional AArch64::parseArch(StringRef Arch) { +const AArch64::ArchInfo *AArch64::parseArch(StringRef Arch) { Arch = llvm::ARM::getCanonicalArchName(Arch); if (checkArchVersion(Arch) < 8) return {}; @@ -111,7 +108,7 @@ std::optional AArch64::parseArch(StringRef Arch) { StringRef Syn = llvm::ARM::getArchSynonym(Arch); for (const auto *A : ArchInfos) { if (A->Name.ends_with(Syn)) - return *A; + return A; } return {}; } @@ -150,3 +147,137 @@ void AArch64::PrintSupportedExtensions(StringMap DescMap) { } } } + +const llvm::AArch64::ExtensionInfo & +lookupExtensionByID(llvm::AArch64::ArchExtKind ExtID) { + for (const auto &E : llvm::AArch64::Extensions) + if (E.ID == ExtID) + return E; + llvm_unreachable("Invalid extension ID"); +} + +void AArch64::ExtensionSet::enable(ArchExtKind E) { + if (Enabled.test(E)) + return; + + LLVM_DEBUG(llvm::dbgs() << "Enable " << lookupExtensionByID(E).Name << "\n"); + + Touched.set(E); + Enabled.set(E); + + // Recursively enable all features that this one depends on. This handles all + // of the simple cases, where the behaviour doesn't depend on the base + // architecture version. + for (auto Dep : ExtensionDependencies) + if (E == Dep.Later) + enable(Dep.Earlier); + + // Special cases for dependencies which vary depending on the base + // architecture version. + if (BaseArch) { + // +sve implies +f32mm if the base architecture is v8.6A+ or v9.1A+ + // It isn't the case in general that sve implies both f64mm and f32mm + if (E == AEK_SVE && BaseArch->is_superset(ARMV8_6A)) + enable(AEK_F32MM); + + // +fp16 implies +fp16fml for v8.4A+, but not v9.0-A+ + if (E == AEK_FP16 && BaseArch->is_superset(ARMV8_4A) && + !BaseArch->is_superset(ARMV9A)) + enable(AEK_FP16FML); + + // For all architectures, +crypto enables +aes and +sha2. + if (E == AEK_CRYPTO) { + enable(AEK_AES); + enable(AEK_SHA2); + } + + // For v8.4A+ and v9.0A+, +crypto also enables +sha3 and +sm4. + if (E == AEK_CRYPTO && BaseArch->is_superset(ARMV8_4A)) { + enable(AEK_SHA3); + enable(AEK_SM4); + } + } +} + +void AArch64::ExtensionSet::disable(ArchExtKind E) { + // -crypto always disables aes, sha2, sha3 and sm4, even for architectures + // where the latter two would not be enabled by +crypto. + if (E == AEK_CRYPTO) { + disable(AEK_AES); + disable(AEK_SHA2); + disable(AEK_SHA3); + disable(AEK_SM4); + } + + if (!Enabled.test(E)) + return; + + LLVM_DEBUG(llvm::dbgs() << "Disable " << lookupExtensionByID(E).Name << "\n"); + + Touched.set(E); + Enabled.reset(E); + + // Recursively disable all features that depends on this one. + for (auto Dep : ExtensionDependencies) + if (E == Dep.Earlier) + disable(Dep.Later); +} + +void AArch64::ExtensionSet::toLLVMFeatureList( + std::vector &Features) const { + if (BaseArch && !BaseArch->ArchFeature.empty()) + Features.push_back(BaseArch->ArchFeature); + + for (const auto &E : Extensions) { + if (E.Feature.empty() || !Touched.test(E.ID)) + continue; + if (Enabled.test(E.ID)) + Features.push_back(E.Feature); + else + Features.push_back(E.NegFeature); + } +} + +void AArch64::ExtensionSet::addCPUDefaults(const CpuInfo &CPU) { + LLVM_DEBUG(llvm::dbgs() << "addCPUDefaults(" << CPU.Name << ")\n"); + BaseArch = &CPU.Arch; + + AArch64::ExtensionBitset CPUExtensions = CPU.getImpliedExtensions(); + for (const auto &E : Extensions) + if (CPUExtensions.test(E.ID)) + enable(E.ID); +} + +void AArch64::ExtensionSet::addArchDefaults(const ArchInfo &Arch) { + LLVM_DEBUG(llvm::dbgs() << "addArchDefaults(" << Arch.Name << ")\n"); + BaseArch = &Arch; + + for (const auto &E : Extensions) + if (Arch.DefaultExts.test(E.ID)) + enable(E.ID); +} + +bool AArch64::ExtensionSet::parseModifier(StringRef Modifier) { + LLVM_DEBUG(llvm::dbgs() << "parseModifier(" << Modifier << ")\n"); + + // Negative modifiers, with the syntax "no" + if (Modifier.starts_with("no")) { + StringRef ModifierBase(Modifier.substr(2)); + for (const auto &AE : Extensions) { + if (!AE.NegFeature.empty() && ModifierBase == AE.Name) { + disable(AE.ID); + return true; + } + } + } + + // Positive modifiers + for (const auto &AE : Extensions) { + if (!AE.Feature.empty() && Modifier == AE.Name) { + enable(AE.ID); + return true; + } + } + + return false; +} diff --git a/llvm/lib/TargetParser/ARMTargetParser.cpp b/llvm/lib/TargetParser/ARMTargetParser.cpp index ce640f5b8d4..67f937ebc33 100644 --- a/llvm/lib/TargetParser/ARMTargetParser.cpp +++ b/llvm/lib/TargetParser/ARMTargetParser.cpp @@ -86,6 +86,7 @@ unsigned ARM::parseArchVersion(StringRef Arch) { case ArchKind::ARMV9_2A: case ArchKind::ARMV9_3A: case ArchKind::ARMV9_4A: + case ArchKind::ARMV9_5A: return 9; case ArchKind::INVALID: return 0; @@ -123,6 +124,7 @@ static ARM::ProfileKind getProfileKind(ARM::ArchKind AK) { case ARM::ArchKind::ARMV9_2A: case ARM::ArchKind::ARMV9_3A: case ARM::ArchKind::ARMV9_4A: + case ARM::ArchKind::ARMV9_5A: return ARM::ProfileKind::A; case ARM::ArchKind::ARMV4: case ARM::ArchKind::ARMV4T: @@ -596,6 +598,7 @@ StringRef ARM::getARMCPUForArch(const llvm::Triple &Triple, StringRef MArch) { case llvm::Triple::TvOS: case llvm::Triple::WatchOS: case llvm::Triple::DriverKit: + case llvm::Triple::XROS: if (MArch == "v7k") return "cortex-a7"; break; diff --git a/llvm/lib/TargetParser/Host.cpp b/llvm/lib/TargetParser/Host.cpp index 32941c013c6..f1197c29655 100644 --- a/llvm/lib/TargetParser/Host.cpp +++ b/llvm/lib/TargetParser/Host.cpp @@ -310,6 +310,13 @@ StringRef sys::detail::getHostCPUNameForARM(StringRef ProcCpuinfoContent) { } } + if (Implementer == "0x6d") { // Microsoft Corporation. + // The Microsoft Azure Cobalt 100 CPU is handled as a Neoverse N2. + return StringSwitch(Part) + .Case("0xd49", "neoverse-n2") + .Default("generic"); + } + if (Implementer == "0xc0") { // Ampere Computing return StringSwitch(Part) .Case("0xac3", "ampere1") diff --git a/llvm/lib/TargetParser/TargetParser.cpp b/llvm/lib/TargetParser/TargetParser.cpp index d741d2ce794..3cbe974ff31 100644 --- a/llvm/lib/TargetParser/TargetParser.cpp +++ b/llvm/lib/TargetParser/TargetParser.cpp @@ -275,12 +275,15 @@ void AMDGPU::fillAMDGPUFeatureMap(StringRef GPU, const Triple &T, case GK_GFX1201: case GK_GFX1200: Features["ci-insts"] = true; - Features["dot5-insts"] = true; Features["dot7-insts"] = true; Features["dot8-insts"] = true; Features["dot9-insts"] = true; Features["dot10-insts"] = true; Features["dl-insts"] = true; + Features["atomic-ds-pk-add-16-insts"] = true; + Features["atomic-flat-pk-add-16-insts"] = true; + Features["atomic-buffer-global-pk-add-f16-insts"] = true; + Features["atomic-global-pk-add-bf16-inst"] = true; Features["16-bit-insts"] = true; Features["dpp"] = true; Features["gfx8-insts"] = true; @@ -291,7 +294,6 @@ void AMDGPU::fillAMDGPUFeatureMap(StringRef GPU, const Triple &T, Features["gfx12-insts"] = true; Features["atomic-fadd-rtn-insts"] = true; Features["image-insts"] = true; - Features["gws"] = true; break; case GK_GFX1151: case GK_GFX1150: @@ -371,6 +373,7 @@ void AMDGPU::fillAMDGPUFeatureMap(StringRef GPU, const Triple &T, case GK_GFX940: Features["gfx940-insts"] = true; Features["fp8-insts"] = true; + Features["fp8-conversion-insts"] = true; Features["atomic-ds-pk-add-16-insts"] = true; Features["atomic-flat-pk-add-16-insts"] = true; Features["atomic-global-pk-add-bf16-inst"] = true; diff --git a/llvm/lib/TargetParser/Triple.cpp b/llvm/lib/TargetParser/Triple.cpp index b9971c25af7..0bbe8a3cedf 100644 --- a/llvm/lib/TargetParser/Triple.cpp +++ b/llvm/lib/TargetParser/Triple.cpp @@ -7,6 +7,7 @@ //===----------------------------------------------------------------------===// #include "llvm/TargetParser/Triple.h" +#include "llvm/ADT/DenseMap.h" #include "llvm/ADT/SmallString.h" #include "llvm/ADT/StringExtras.h" #include "llvm/ADT/StringSwitch.h" @@ -273,6 +274,8 @@ StringRef Triple::getOSTypeName(OSType Kind) { case ZOS: return "zos"; case ShaderModel: return "shadermodel"; case LiteOS: return "liteos"; + case XROS: return "xros"; + case Vulkan: return "vulkan"; } llvm_unreachable("Invalid OSType"); @@ -550,8 +553,7 @@ static Triple::ArchType parseArch(StringRef ArchName) { .Case("hsail64", Triple::hsail64) .Case("spir", Triple::spir) .Case("spir64", Triple::spir64) - .Cases("spirv", "spirv1.0", "spirv1.1", "spirv1.2", - "spirv1.3", "spirv1.4", "spirv1.5", Triple::spirv) + .Cases("spirv", "spirv1.5", "spirv1.6", Triple::spirv) .Cases("spirv32", "spirv32v1.0", "spirv32v1.1", "spirv32v1.2", "spirv32v1.3", "spirv32v1.4", "spirv32v1.5", Triple::spirv32) .Cases("spirv64", "spirv64v1.0", "spirv64v1.1", "spirv64v1.2", @@ -634,6 +636,8 @@ static Triple::OSType parseOS(StringRef OSName) { .StartsWith("tvos", Triple::TvOS) .StartsWith("watchos", Triple::WatchOS) .StartsWith("driverkit", Triple::DriverKit) + .StartsWith("xros", Triple::XROS) + .StartsWith("visionos", Triple::XROS) .StartsWith("mesa3d", Triple::Mesa3D) .StartsWith("amdpal", Triple::AMDPAL) .StartsWith("hermit", Triple::HermitCore) @@ -643,6 +647,7 @@ static Triple::OSType parseOS(StringRef OSName) { .StartsWith("shadermodel", Triple::ShaderModel) .StartsWith("liteos", Triple::LiteOS) .StartsWith("serenity", Triple::Serenity) + .StartsWith("vulkan", Triple::Vulkan) .Default(Triple::UnknownOS); } @@ -727,6 +732,7 @@ static Triple::SubArchType parseSubArch(StringRef SubArchName) { .EndsWith("v1.3", Triple::SPIRVSubArch_v13) .EndsWith("v1.4", Triple::SPIRVSubArch_v14) .EndsWith("v1.5", Triple::SPIRVSubArch_v15) + .EndsWith("v1.6", Triple::SPIRVSubArch_v16) .Default(Triple::NoSubArch); StringRef ARMSubArch = ARM::getCanonicalArchName(SubArchName); @@ -805,6 +811,8 @@ static Triple::SubArchType parseSubArch(StringRef SubArchName) { return Triple::ARMSubArch_v9_3a; case ARM::ArchKind::ARMV9_4A: return Triple::ARMSubArch_v9_4a; + case ARM::ArchKind::ARMV9_5A: + return Triple::ARMSubArch_v9_5a; case ARM::ArchKind::ARMV8R: return Triple::ARMSubArch_v8r; case ARM::ArchKind::ARMV8MBaseline: @@ -1224,6 +1232,8 @@ VersionTuple Triple::getOSVersion() const { OSName = OSName.substr(OSTypeName.size()); else if (getOS() == MacOSX) OSName.consume_front("macos"); + else if (OSName.starts_with("visionos")) + OSName.consume_front("visionos"); return parseVersionFromName(OSName); } @@ -1265,6 +1275,8 @@ bool Triple::getMacOSXVersion(VersionTuple &Version) const { // IOS. Version = VersionTuple(10, 4); break; + case XROS: + llvm_unreachable("OSX version isn't relevant for xrOS"); case DriverKit: llvm_unreachable("OSX version isn't relevant for DriverKit"); } @@ -1289,6 +1301,11 @@ VersionTuple Triple::getiOSVersion() const { return (getArch() == aarch64) ? VersionTuple(7) : VersionTuple(5); return Version; } + case XROS: { + // xrOS 1 is aligned with iOS 17. + VersionTuple Version = getOSVersion(); + return Version.withMajorReplaced(Version.getMajor() + 16); + } case WatchOS: llvm_unreachable("conflicting triple info"); case DriverKit: @@ -1314,6 +1331,8 @@ VersionTuple Triple::getWatchOSVersion() const { } case IOS: llvm_unreachable("conflicting triple info"); + case XROS: + llvm_unreachable("watchOS version isn't relevant for xrOS"); case DriverKit: llvm_unreachable("DriverKit doesn't have a WatchOS version"); } @@ -1331,6 +1350,31 @@ VersionTuple Triple::getDriverKitVersion() const { } } +VersionTuple Triple::getVulkanVersion() const { + if (getArch() != spirv || getOS() != Vulkan) + llvm_unreachable("invalid Vulkan SPIR-V triple"); + + VersionTuple VulkanVersion = getOSVersion(); + SubArchType SpirvVersion = getSubArch(); + + llvm::DenseMap ValidVersionMap = { + // Vulkan 1.2 -> SPIR-V 1.5. + {VersionTuple(1, 2), SPIRVSubArch_v15}, + // Vulkan 1.3 -> SPIR-V 1.6. + {VersionTuple(1, 3), SPIRVSubArch_v16}}; + + // If Vulkan version is unset, default to 1.2. + if (VulkanVersion == VersionTuple(0)) + VulkanVersion = VersionTuple(1, 2); + + if (ValidVersionMap.contains(VulkanVersion) && + (ValidVersionMap.lookup(VulkanVersion) == SpirvVersion || + SpirvVersion == NoSubArch)) + return VulkanVersion; + + return VersionTuple(0); +} + void Triple::setTriple(const Twine &Str) { *this = Triple(Str); } diff --git a/llvm/lib/TargetParser/X86TargetParser.cpp b/llvm/lib/TargetParser/X86TargetParser.cpp index d46ff07ec73..518fb9d8921 100644 --- a/llvm/lib/TargetParser/X86TargetParser.cpp +++ b/llvm/lib/TargetParser/X86TargetParser.cpp @@ -347,7 +347,7 @@ constexpr ProcInfo Processors[] = { // Tigerlake microarchitecture based processors. { {"tigerlake"}, CK_Tigerlake, FEATURE_AVX512VP2INTERSECT, FeaturesTigerlake, 'l', false }, // Sapphire Rapids microarchitecture based processors. - { {"sapphirerapids"}, CK_SapphireRapids, FEATURE_AVX512BF16, FeaturesSapphireRapids, 'n', false }, + { {"sapphirerapids"}, CK_SapphireRapids, FEATURE_AVX512FP16, FeaturesSapphireRapids, 'n', false }, // Alderlake microarchitecture based processors. { {"alderlake"}, CK_Alderlake, FEATURE_AVX2, FeaturesAlderlake, 'p', false }, // Raptorlake microarchitecture based processors. @@ -369,12 +369,12 @@ constexpr ProcInfo Processors[] = { // Grandridge microarchitecture based processors. { {"grandridge"}, CK_Grandridge, FEATURE_AVX2, FeaturesSierraforest, 'p', false }, // Granite Rapids microarchitecture based processors. - { {"graniterapids"}, CK_Graniterapids, FEATURE_AVX512BF16, FeaturesGraniteRapids, 'n', false }, + { {"graniterapids"}, CK_Graniterapids, FEATURE_AVX512FP16, FeaturesGraniteRapids, 'n', false }, // Granite Rapids D microarchitecture based processors. - { {"graniterapids-d"}, CK_GraniterapidsD, FEATURE_AVX512BF16, FeaturesGraniteRapids | FeatureAMX_COMPLEX, '\0', false }, - { {"graniterapids_d"}, CK_GraniterapidsD, FEATURE_AVX512BF16, FeaturesGraniteRapids | FeatureAMX_COMPLEX, 'n', true }, + { {"graniterapids-d"}, CK_GraniterapidsD, FEATURE_AVX512FP16, FeaturesGraniteRapids | FeatureAMX_COMPLEX, '\0', false }, + { {"graniterapids_d"}, CK_GraniterapidsD, FEATURE_AVX512FP16, FeaturesGraniteRapids | FeatureAMX_COMPLEX, 'n', true }, // Emerald Rapids microarchitecture based processors. - { {"emeraldrapids"}, CK_Emeraldrapids, FEATURE_AVX512BF16, FeaturesSapphireRapids, 'n', false }, + { {"emeraldrapids"}, CK_Emeraldrapids, FEATURE_AVX512FP16, FeaturesSapphireRapids, 'n', false }, // Clearwaterforest microarchitecture based processors. { {"clearwaterforest"}, CK_Lunarlake, FEATURE_AVX2, FeaturesClearwaterforest, 'p', false }, // Knights Landing processor. diff --git a/llvm/lib/TextAPI/Platform.cpp b/llvm/lib/TextAPI/Platform.cpp index ed041af40aa..e891594300c 100644 --- a/llvm/lib/TextAPI/Platform.cpp +++ b/llvm/lib/TextAPI/Platform.cpp @@ -106,6 +106,10 @@ std::string getOSAndEnvironmentName(PlatformType Platform, return "watchos" + Version + "-simulator"; case PLATFORM_DRIVERKIT: return "driverkit" + Version; + case PLATFORM_XROS: + return "xros" + Version; + case PLATFORM_XROS_SIMULATOR: + return "xros" + Version + "-simulator"; } llvm_unreachable("Unknown llvm::MachO::PlatformType enum"); } diff --git a/llvm/lib/TextAPI/RecordsSlice.cpp b/llvm/lib/TextAPI/RecordsSlice.cpp index 7ceffc7c928..840fe1855da 100644 --- a/llvm/lib/TextAPI/RecordsSlice.cpp +++ b/llvm/lib/TextAPI/RecordsSlice.cpp @@ -332,9 +332,8 @@ llvm::MachO::convertToInterfaceFile(const Records &Slices) { } File = createInterfaceFile(Slices, *InstallNames.begin()); - for (auto it = std::next(InstallNames.begin()); it != InstallNames.end(); - ++it) - File->addDocument(createInterfaceFile(Slices, *it)); + for (StringRef IN : llvm::drop_begin(InstallNames)) + File->addDocument(createInterfaceFile(Slices, IN)); return File; } diff --git a/llvm/lib/ToolDrivers/llvm-lib/LibDriver.cpp b/llvm/lib/ToolDrivers/llvm-lib/LibDriver.cpp index 1c140edb07a..5d7ec0fb030 100644 --- a/llvm/lib/ToolDrivers/llvm-lib/LibDriver.cpp +++ b/llvm/lib/ToolDrivers/llvm-lib/LibDriver.cpp @@ -67,7 +67,7 @@ public: static std::string getDefaultOutputPath(const NewArchiveMember &FirstMember) { SmallString<128> Val = StringRef(FirstMember.Buf->getBufferIdentifier()); sys::path::replace_extension(Val, ".lib"); - return std::string(Val.str()); + return std::string(Val); } static std::vector getSearchPaths(opt::InputArgList *Args, diff --git a/llvm/lib/Transforms/AggressiveInstCombine/AggressiveInstCombine.cpp b/llvm/lib/Transforms/AggressiveInstCombine/AggressiveInstCombine.cpp index d09ac1c099c..49fa0f59d48 100644 --- a/llvm/lib/Transforms/AggressiveInstCombine/AggressiveInstCombine.cpp +++ b/llvm/lib/Transforms/AggressiveInstCombine/AggressiveInstCombine.cpp @@ -808,8 +808,8 @@ static bool foldConsecutiveLoads(Instruction &I, const DataLayout &DL, APInt Offset1(DL.getIndexTypeSizeInBits(Load1Ptr->getType()), 0); Load1Ptr = Load1Ptr->stripAndAccumulateConstantOffsets( DL, Offset1, /* AllowNonInbounds */ true); - Load1Ptr = Builder.CreateGEP(Builder.getInt8Ty(), Load1Ptr, - Builder.getInt32(Offset1.getZExtValue())); + Load1Ptr = Builder.CreatePtrAdd(Load1Ptr, + Builder.getInt32(Offset1.getZExtValue())); } // Generate wider load. NewLoad = Builder.CreateAlignedLoad(WiderType, Load1Ptr, LI1->getAlign(), diff --git a/llvm/lib/Transforms/Coroutines/CoroEarly.cpp b/llvm/lib/Transforms/Coroutines/CoroEarly.cpp index d510b90d9de..489106422e1 100644 --- a/llvm/lib/Transforms/Coroutines/CoroEarly.cpp +++ b/llvm/lib/Transforms/Coroutines/CoroEarly.cpp @@ -203,7 +203,7 @@ void Lowerer::lowerEarlyIntrinsics(Function &F) { if (CII->getInfo().isPreSplit()) { assert(F.isPresplitCoroutine() && "The frontend uses Swtich-Resumed ABI should emit " - "\"coroutine.presplit\" attribute for the coroutine."); + "\"presplitcoroutine\" attribute for the coroutine."); setCannotDuplicate(CII); CII->setCoroutineSelf(); CoroId = cast(&I); diff --git a/llvm/lib/Transforms/Coroutines/CoroFrame.cpp b/llvm/lib/Transforms/Coroutines/CoroFrame.cpp index 89a1ad2243c..e69c718f0ae 100644 --- a/llvm/lib/Transforms/Coroutines/CoroFrame.cpp +++ b/llvm/lib/Transforms/Coroutines/CoroFrame.cpp @@ -963,18 +963,15 @@ static void cacheDIVar(FrameDataInfo &FrameData, if (DIVarCache.contains(V)) continue; - SmallVector DDIs; - SmallVector DPVs; - findDbgDeclares(DDIs, V, &DPVs); - auto CacheIt = [&DIVarCache, V](auto &Container) { + auto CacheIt = [&DIVarCache, V](const auto &Container) { auto *I = llvm::find_if(Container, [](auto *DDI) { return DDI->getExpression()->getNumElements() == 0; }); if (I != Container.end()) DIVarCache.insert({V, (*I)->getVariable()}); }; - CacheIt(DDIs); - CacheIt(DPVs); + CacheIt(findDbgDeclares(V)); + CacheIt(findDPVDeclares(V)); } } @@ -1125,9 +1122,8 @@ static void buildFrameDebugInfo(Function &F, coro::Shape &Shape, assert(PromiseAlloca && "Coroutine with switch ABI should own Promise alloca"); - SmallVector DIs; - SmallVector DPVs; - findDbgDeclares(DIs, PromiseAlloca, &DPVs); + TinyPtrVector DIs = findDbgDeclares(PromiseAlloca); + TinyPtrVector DPVs = findDPVDeclares(PromiseAlloca); DILocalVariable *PromiseDIVariable = nullptr; DILocation *DILoc = nullptr; @@ -1293,8 +1289,8 @@ static void buildFrameDebugInfo(Function &F, coro::Shape &Shape, // struct f.frame { // ResumeFnTy ResumeFnAddr; // ResumeFnTy DestroyFnAddr; -// int ResumeIndex; // ... promise (if present) ... +// int ResumeIndex; // ... spills ... // }; static StructType *buildFrameType(Function &F, coro::Shape &Shape, @@ -1865,15 +1861,14 @@ static void insertSpills(const FrameDataInfo &FrameData, coro::Shape &Shape) { FrameTy->getElementType(FrameData.getFieldIndex(E.first)), GEP, SpillAlignment, E.first->getName() + Twine(".reload")); - SmallVector DIs; - SmallVector DPVs; - findDbgDeclares(DIs, Def, &DPVs); + TinyPtrVector DIs = findDbgDeclares(Def); + TinyPtrVector DPVs = findDPVDeclares(Def); // Try best to find dbg.declare. If the spill is a temp, there may not // be a direct dbg.declare. Walk up the load chain to find one from an // alias. if (F->getSubprogram()) { auto *CurDef = Def; - while (DIs.empty() && isa(CurDef)) { + while (DIs.empty() && DPVs.empty() && isa(CurDef)) { auto *LdInst = cast(CurDef); // Only consider ptr to ptr same type load. if (LdInst->getPointerOperandType() != LdInst->getType()) @@ -1881,9 +1876,8 @@ static void insertSpills(const FrameDataInfo &FrameData, coro::Shape &Shape) { CurDef = LdInst->getPointerOperand(); if (!isa(CurDef)) break; - DIs.clear(); - DPVs.clear(); - findDbgDeclares(DIs, CurDef, &DPVs); + DIs = findDbgDeclares(CurDef); + DPVs = findDPVDeclares(CurDef); } } @@ -2022,8 +2016,8 @@ static void insertSpills(const FrameDataInfo &FrameData, coro::Shape &Shape) { auto *FramePtr = GetFramePointer(Alloca); auto &Value = *Alias.second; auto ITy = IntegerType::get(C, Value.getBitWidth()); - auto *AliasPtr = Builder.CreateGEP(Type::getInt8Ty(C), FramePtr, - ConstantInt::get(ITy, Value)); + auto *AliasPtr = + Builder.CreatePtrAdd(FramePtr, ConstantInt::get(ITy, Value)); Alias.first->replaceUsesWithIf( AliasPtr, [&](Use &U) { return DT.dominates(CB, U); }); } @@ -2972,7 +2966,7 @@ void coro::salvageDebugInfo( Function *F = DPV.getFunction(); // Follow the pointer arithmetic all the way to the incoming // function argument and convert into a DIExpression. - bool SkipOutermostLoad = DPV.getType() == DPValue::LocationType::Declare; + bool SkipOutermostLoad = DPV.isDbgDeclare(); Value *OriginalStorage = DPV.getVariableLocationOp(0); auto SalvagedInfo = ::salvageDebugInfoImpl( diff --git a/llvm/lib/Transforms/IPO/ArgumentPromotion.cpp b/llvm/lib/Transforms/IPO/ArgumentPromotion.cpp index fb3fa8d23da..8058282c422 100644 --- a/llvm/lib/Transforms/IPO/ArgumentPromotion.cpp +++ b/llvm/lib/Transforms/IPO/ArgumentPromotion.cpp @@ -100,7 +100,7 @@ static Value *createByteGEP(IRBuilderBase &IRB, const DataLayout &DL, Value *Ptr, Type *ResElemTy, int64_t Offset) { if (Offset != 0) { APInt APOffset(DL.getIndexTypeSizeInBits(Ptr->getType()), Offset); - Ptr = IRB.CreateGEP(IRB.getInt8Ty(), Ptr, IRB.getInt(APOffset)); + Ptr = IRB.CreatePtrAdd(Ptr, IRB.getInt(APOffset)); } return Ptr; } diff --git a/llvm/lib/Transforms/IPO/AttributorAttributes.cpp b/llvm/lib/Transforms/IPO/AttributorAttributes.cpp index cc5a4ee8c2b..585364dd7aa 100644 --- a/llvm/lib/Transforms/IPO/AttributorAttributes.cpp +++ b/llvm/lib/Transforms/IPO/AttributorAttributes.cpp @@ -298,8 +298,8 @@ static Value *constructPointer(Value *Ptr, int64_t Offset, << "-bytes\n"); if (Offset) - Ptr = IRB.CreateGEP(IRB.getInt8Ty(), Ptr, IRB.getInt64(Offset), - Ptr->getName() + ".b" + Twine(Offset)); + Ptr = IRB.CreatePtrAdd(Ptr, IRB.getInt64(Offset), + Ptr->getName() + ".b" + Twine(Offset)); return Ptr; } diff --git a/llvm/lib/Transforms/IPO/EmbedBitcodePass.cpp b/llvm/lib/Transforms/IPO/EmbedBitcodePass.cpp index 48ef0772e80..6af3a45701b 100644 --- a/llvm/lib/Transforms/IPO/EmbedBitcodePass.cpp +++ b/llvm/lib/Transforms/IPO/EmbedBitcodePass.cpp @@ -7,6 +7,8 @@ //===----------------------------------------------------------------------===// #include "llvm/Transforms/IPO/EmbedBitcodePass.h" +#include "llvm/Bitcode/BitcodeWriter.h" +#include "llvm/Bitcode/BitcodeWriterPass.h" #include "llvm/IR/PassManager.h" #include "llvm/Pass.h" #include "llvm/Support/ErrorHandling.h" @@ -16,6 +18,7 @@ #include "llvm/Transforms/IPO/ThinLTOBitcodeWriter.h" #include "llvm/Transforms/Utils/ModuleUtils.h" +#include #include using namespace llvm; @@ -30,9 +33,16 @@ PreservedAnalyses EmbedBitcodePass::run(Module &M, ModuleAnalysisManager &AM) { report_fatal_error( "EmbedBitcode pass currently only supports ELF object format", /*gen_crash_diag=*/false); + std::string Data; raw_string_ostream OS(Data); - ThinLTOBitcodeWriterPass(OS, /*ThinLinkOS=*/nullptr).run(M, AM); + if (IsThinLTO) + ThinLTOBitcodeWriterPass(OS, /*ThinLinkOS=*/nullptr).run(M, AM); + else + BitcodeWriterPass(OS, /*ShouldPreserveUseListOrder=*/false, EmitLTOSummary) + .run(M, AM); + embedBufferInModule(M, MemoryBufferRef(Data, "ModuleData"), ".llvm.lto"); + return PreservedAnalyses::all(); } diff --git a/llvm/lib/Transforms/IPO/IROutliner.cpp b/llvm/lib/Transforms/IPO/IROutliner.cpp index a6e19df7c5f..8e6d0e81437 100644 --- a/llvm/lib/Transforms/IPO/IROutliner.cpp +++ b/llvm/lib/Transforms/IPO/IROutliner.cpp @@ -154,8 +154,7 @@ struct OutlinableGroup { /// \param SourceBB - the BasicBlock to pull Instructions from. /// \param TargetBB - the BasicBlock to put Instruction into. static void moveBBContents(BasicBlock &SourceBB, BasicBlock &TargetBB) { - for (Instruction &I : llvm::make_early_inc_range(SourceBB)) - I.moveBeforePreserving(TargetBB, TargetBB.end()); + TargetBB.splice(TargetBB.end(), &SourceBB); } /// A function to sort the keys of \p Map, which must be a mapping of constant diff --git a/llvm/lib/Transforms/IPO/MemProfContextDisambiguation.cpp b/llvm/lib/Transforms/IPO/MemProfContextDisambiguation.cpp index 0a6f69bc73d..e10b3c56ae1 100644 --- a/llvm/lib/Transforms/IPO/MemProfContextDisambiguation.cpp +++ b/llvm/lib/Transforms/IPO/MemProfContextDisambiguation.cpp @@ -45,6 +45,7 @@ #include "llvm/Transforms/IPO.h" #include "llvm/Transforms/Utils/Cloning.h" #include +#include #include using namespace llvm; using namespace llvm::memprof; @@ -577,7 +578,7 @@ class ModuleCallsiteContextGraph public: ModuleCallsiteContextGraph( Module &M, - function_ref OREGetter); + llvm::function_ref OREGetter); private: friend CallsiteContextGraph OREGetter; + llvm::function_ref OREGetter; }; /// Represents a call in the summary index graph, which can either be an @@ -640,7 +641,7 @@ class IndexCallsiteContextGraph public: IndexCallsiteContextGraph( ModuleSummaryIndex &Index, - function_ref + llvm::function_ref isPrevailing); ~IndexCallsiteContextGraph() { @@ -686,7 +687,7 @@ private: std::map FSToVIMap; const ModuleSummaryIndex &Index; - function_ref + llvm::function_ref isPrevailing; // Saves/owns the callsite info structures synthesized for missing tail call @@ -1523,7 +1524,8 @@ CallsiteContextGraph::getStackIdsWithContextNodes( } ModuleCallsiteContextGraph::ModuleCallsiteContextGraph( - Module &M, function_ref OREGetter) + Module &M, + llvm::function_ref OREGetter) : Mod(M), OREGetter(OREGetter) { for (auto &F : M) { std::vector CallsWithMetadata; @@ -1582,7 +1584,7 @@ ModuleCallsiteContextGraph::ModuleCallsiteContextGraph( IndexCallsiteContextGraph::IndexCallsiteContextGraph( ModuleSummaryIndex &Index, - function_ref + llvm::function_ref isPrevailing) : Index(Index), isPrevailing(isPrevailing) { for (auto &I : Index) { @@ -3622,7 +3624,7 @@ bool CallsiteContextGraph::process() { bool MemProfContextDisambiguation::processModule( Module &M, - function_ref OREGetter) { + llvm::function_ref OREGetter) { // If we have an import summary, then the cloning decisions were made during // the thin link on the index. Apply them and return. @@ -3689,7 +3691,7 @@ PreservedAnalyses MemProfContextDisambiguation::run(Module &M, void MemProfContextDisambiguation::run( ModuleSummaryIndex &Index, - function_ref + llvm::function_ref isPrevailing) { // TODO: If/when other types of memprof cloning are enabled beyond just for // hot and cold, we will need to change this to individually control the diff --git a/llvm/lib/Transforms/IPO/SampleProfileProbe.cpp b/llvm/lib/Transforms/IPO/SampleProfileProbe.cpp index 8f0b12d0cfe..090e5560483 100644 --- a/llvm/lib/Transforms/IPO/SampleProfileProbe.cpp +++ b/llvm/lib/Transforms/IPO/SampleProfileProbe.cpp @@ -186,9 +186,7 @@ void SampleProfileProber::computeCFGHash() { std::vector Indexes; JamCRC JC; for (auto &BB : *F) { - auto *TI = BB.getTerminator(); - for (unsigned I = 0, E = TI->getNumSuccessors(); I != E; ++I) { - auto *Succ = TI->getSuccessor(I); + for (BasicBlock *Succ : successors(&BB)) { auto Index = getBlockId(Succ); for (int J = 0; J < 4; J++) Indexes.push_back((uint8_t)(Index >> (J * 8))); diff --git a/llvm/lib/Transforms/IPO/WholeProgramDevirt.cpp b/llvm/lib/Transforms/IPO/WholeProgramDevirt.cpp index 85afc020dbf..01aba47cdbf 100644 --- a/llvm/lib/Transforms/IPO/WholeProgramDevirt.cpp +++ b/llvm/lib/Transforms/IPO/WholeProgramDevirt.cpp @@ -1769,7 +1769,7 @@ void DevirtModule::applyVirtualConstProp(CallSiteInfo &CSInfo, StringRef FnName, continue; auto *RetType = cast(Call.CB.getType()); IRBuilder<> B(&Call.CB); - Value *Addr = B.CreateGEP(Int8Ty, Call.VTable, Byte); + Value *Addr = B.CreatePtrAdd(Call.VTable, Byte); if (RetType->getBitWidth() == 1) { Value *Bits = B.CreateLoad(Int8Ty, Addr); Value *BitsAndBit = B.CreateAnd(Bits, Bit); @@ -2066,14 +2066,14 @@ void DevirtModule::scanTypeCheckedLoadUsers(Function *TypeCheckedLoadFunc) { Value *LoadedValue = nullptr; if (TypeCheckedLoadFunc->getIntrinsicID() == Intrinsic::type_checked_load_relative) { - Value *GEP = LoadB.CreateGEP(Int8Ty, Ptr, Offset); + Value *GEP = LoadB.CreatePtrAdd(Ptr, Offset); LoadedValue = LoadB.CreateLoad(Int32Ty, GEP); LoadedValue = LoadB.CreateSExt(LoadedValue, IntPtrTy); GEP = LoadB.CreatePtrToInt(GEP, IntPtrTy); LoadedValue = LoadB.CreateAdd(GEP, LoadedValue); LoadedValue = LoadB.CreateIntToPtr(LoadedValue, Int8PtrTy); } else { - Value *GEP = LoadB.CreateGEP(Int8Ty, Ptr, Offset); + Value *GEP = LoadB.CreatePtrAdd(Ptr, Offset); LoadedValue = LoadB.CreateLoad(Int8PtrTy, GEP); } diff --git a/llvm/lib/Transforms/InstCombine/InstCombineAddSub.cpp b/llvm/lib/Transforms/InstCombine/InstCombineAddSub.cpp index c7e6f32c540..8a00b75a1f7 100644 --- a/llvm/lib/Transforms/InstCombine/InstCombineAddSub.cpp +++ b/llvm/lib/Transforms/InstCombine/InstCombineAddSub.cpp @@ -1683,6 +1683,9 @@ Instruction *InstCombinerImpl::visitAdd(BinaryOperator &I) { } } + if (Instruction *R = tryFoldInstWithCtpopWithNot(&I)) + return R; + // TODO(jingyue): Consider willNotOverflowSignedAdd and // willNotOverflowUnsignedAdd to reduce the number of invocations of // computeKnownBits. @@ -2445,6 +2448,9 @@ Instruction *InstCombinerImpl::visitSub(BinaryOperator &I) { } } + if (Instruction *R = tryFoldInstWithCtpopWithNot(&I)) + return R; + if (Instruction *R = foldSubOfMinMax(I, Builder)) return R; diff --git a/llvm/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp b/llvm/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp index 0620752e321..5fd944a859e 100644 --- a/llvm/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp +++ b/llvm/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp @@ -2809,6 +2809,10 @@ static Instruction *matchFunnelShift(Instruction &Or, InstCombinerImpl &IC, match(R, m_And(m_Neg(m_Specific(X)), m_SpecificInt(Mask)))) return X; + // (shl ShVal, X) | (lshr ShVal, ((-X) & (Width - 1))) + if (match(R, m_And(m_Neg(m_Specific(L)), m_SpecificInt(Mask)))) + return L; + // Similar to above, but the shift amount may be extended after masking, // so return the extended value as the parameter for the intrinsic. if (match(L, m_ZExt(m_And(m_Value(X), m_SpecificInt(Mask)))) && @@ -3398,6 +3402,9 @@ Instruction *InstCombinerImpl::visitOr(BinaryOperator &I) { if (Instruction *R = foldBinOpShiftWithShift(I)) return R; + if (Instruction *R = tryFoldInstWithCtpopWithNot(&I)) + return R; + Value *X, *Y; const APInt *CV; if (match(&I, m_c_Or(m_OneUse(m_Xor(m_Value(X), m_APInt(CV))), m_Value(Y))) && diff --git a/llvm/lib/Transforms/InstCombine/InstCombineCalls.cpp b/llvm/lib/Transforms/InstCombine/InstCombineCalls.cpp index 64fbd5543a9..a647be2d26c 100644 --- a/llvm/lib/Transforms/InstCombine/InstCombineCalls.cpp +++ b/llvm/lib/Transforms/InstCombine/InstCombineCalls.cpp @@ -282,10 +282,12 @@ Instruction *InstCombinerImpl::SimplifyAnyMemSet(AnyMemSetInst *MI) { Constant *FillVal = ConstantInt::get(ITy, Fill); StoreInst *S = Builder.CreateStore(FillVal, Dest, MI->isVolatile()); S->copyMetadata(*MI, LLVMContext::MD_DIAssignID); - for (auto *DAI : at::getAssignmentMarkers(S)) { - if (llvm::is_contained(DAI->location_ops(), FillC)) - DAI->replaceVariableLocationOp(FillC, FillVal); - } + auto replaceOpForAssignmentMarkers = [FillC, FillVal](auto *DbgAssign) { + if (llvm::is_contained(DbgAssign->location_ops(), FillC)) + DbgAssign->replaceVariableLocationOp(FillC, FillVal); + }; + for_each(at::getAssignmentMarkers(S), replaceOpForAssignmentMarkers); + for_each(at::getDPVAssignmentMarkers(S), replaceOpForAssignmentMarkers); S->setAlignment(Alignment); if (isa(MI)) diff --git a/llvm/lib/Transforms/InstCombine/InstCombineCasts.cpp b/llvm/lib/Transforms/InstCombine/InstCombineCasts.cpp index 6629ca840a6..58f0763bb0c 100644 --- a/llvm/lib/Transforms/InstCombine/InstCombineCasts.cpp +++ b/llvm/lib/Transforms/InstCombine/InstCombineCasts.cpp @@ -103,6 +103,16 @@ Value *InstCombinerImpl::EvaluateInDifferentType(Value *V, Type *Ty, } } break; + case Instruction::ShuffleVector: { + auto *ScalarTy = cast(Ty)->getElementType(); + auto *VTy = cast(I->getOperand(0)->getType()); + auto *FixedTy = VectorType::get(ScalarTy, VTy->getElementCount()); + Value *Op0 = EvaluateInDifferentType(I->getOperand(0), FixedTy, isSigned); + Value *Op1 = EvaluateInDifferentType(I->getOperand(1), FixedTy, isSigned); + Res = new ShuffleVectorInst(Op0, Op1, + cast(I)->getShuffleMask()); + break; + } default: // TODO: Can handle more cases here. llvm_unreachable("Unreachable!"); @@ -363,6 +373,9 @@ static bool canEvaluateTruncated(Value *V, Type *Ty, InstCombinerImpl &IC, I->getOpcode() == Instruction::FPToSI); return Ty->getScalarSizeInBits() >= MinBitWidth; } + case Instruction::ShuffleVector: + return canEvaluateTruncated(I->getOperand(0), Ty, IC, CxtI) && + canEvaluateTruncated(I->getOperand(1), Ty, IC, CxtI); default: // TODO: Can handle more cases here. break; diff --git a/llvm/lib/Transforms/InstCombine/InstCombineCompares.cpp b/llvm/lib/Transforms/InstCombine/InstCombineCompares.cpp index 7c1aff44552..8c0fd662255 100644 --- a/llvm/lib/Transforms/InstCombine/InstCombineCompares.cpp +++ b/llvm/lib/Transforms/InstCombine/InstCombineCompares.cpp @@ -1323,6 +1323,9 @@ Instruction *InstCombinerImpl::foldICmpWithConstant(ICmpInst &Cmp) { return replaceInstUsesWith(Cmp, NewPhi); } + if (Instruction *R = tryFoldInstWithCtpopWithNot(&Cmp)) + return R; + return nullptr; } diff --git a/llvm/lib/Transforms/InstCombine/InstCombineInternal.h b/llvm/lib/Transforms/InstCombine/InstCombineInternal.h index 21c61bd9901..c24b6e3a5b3 100644 --- a/llvm/lib/Transforms/InstCombine/InstCombineInternal.h +++ b/llvm/lib/Transforms/InstCombine/InstCombineInternal.h @@ -505,6 +505,10 @@ public: Value *SimplifySelectsFeedingBinaryOp(BinaryOperator &I, Value *LHS, Value *RHS); + // If `I` has operand `(ctpop (not x))`, fold `I` with `(sub nuw nsw + // BitWidth(x), (ctpop x))`. + Instruction *tryFoldInstWithCtpopWithNot(Instruction *I); + // (Binop1 (Binop2 (logic_shift X, C), C1), (logic_shift Y, C)) // -> (logic_shift (Binop1 (Binop2 X, inv_logic_shift(C1, C)), Y), C) // (Binop1 (Binop2 (logic_shift X, Amt), Mask), (logic_shift Y, Amt)) diff --git a/llvm/lib/Transforms/InstCombine/InstCombineMulDivRem.cpp b/llvm/lib/Transforms/InstCombine/InstCombineMulDivRem.cpp index e7f983a00e3..6c3adf00c18 100644 --- a/llvm/lib/Transforms/InstCombine/InstCombineMulDivRem.cpp +++ b/llvm/lib/Transforms/InstCombine/InstCombineMulDivRem.cpp @@ -330,6 +330,19 @@ Instruction *InstCombinerImpl::visitMul(BinaryOperator &I) { return BinaryOperator::CreateMul(X, X); } + { + Value *X, *Y; + // abs(X) * abs(Y) -> abs(X * Y) + if (I.hasNoSignedWrap() && + match(Op0, + m_OneUse(m_Intrinsic(m_Value(X), m_One()))) && + match(Op1, m_OneUse(m_Intrinsic(m_Value(Y), m_One())))) + return replaceInstUsesWith( + I, Builder.CreateBinaryIntrinsic(Intrinsic::abs, + Builder.CreateNSWMul(X, Y), + Builder.getTrue())); + } + // -X * C --> X * -C Value *X, *Y; Constant *Op1C; diff --git a/llvm/lib/Transforms/InstCombine/InstCombineShifts.cpp b/llvm/lib/Transforms/InstCombine/InstCombineShifts.cpp index b7958978c45..54490c46dfa 100644 --- a/llvm/lib/Transforms/InstCombine/InstCombineShifts.cpp +++ b/llvm/lib/Transforms/InstCombine/InstCombineShifts.cpp @@ -366,14 +366,14 @@ static Instruction *foldShiftOfShiftedBinOp(BinaryOperator &I, Type *Ty = I.getType(); - // Find a matching one-use shift by constant. The fold is not valid if the sum + // Find a matching shift by constant. The fold is not valid if the sum // of the shift values equals or exceeds bitwidth. - // TODO: Remove the one-use check if the other logic operand (Y) is constant. Value *X, *Y; - auto matchFirstShift = [&](Value *V) { - APInt Threshold(Ty->getScalarSizeInBits(), Ty->getScalarSizeInBits()); - return match(V, - m_OneUse(m_BinOp(ShiftOpcode, m_Value(X), m_Constant(C0)))) && + auto matchFirstShift = [&](Value *V, Value *W) { + unsigned Size = Ty->getScalarSizeInBits(); + APInt Threshold(Size, Size); + return match(V, m_BinOp(ShiftOpcode, m_Value(X), m_Constant(C0))) && + (V->hasOneUse() || match(W, m_ImmConstant())) && match(ConstantExpr::getAdd(C0, C1), m_SpecificInt_ICMP(ICmpInst::ICMP_ULT, Threshold)); }; @@ -382,9 +382,9 @@ static Instruction *foldShiftOfShiftedBinOp(BinaryOperator &I, // is not so we cannot reoder if we match operand(1) and need to keep the // operands in their original positions. bool FirstShiftIsOp1 = false; - if (matchFirstShift(BinInst->getOperand(0))) + if (matchFirstShift(BinInst->getOperand(0), BinInst->getOperand(1))) Y = BinInst->getOperand(1); - else if (matchFirstShift(BinInst->getOperand(1))) { + else if (matchFirstShift(BinInst->getOperand(1), BinInst->getOperand(0))) { Y = BinInst->getOperand(0); FirstShiftIsOp1 = BinInst->getOpcode() == Instruction::Sub; } else diff --git a/llvm/lib/Transforms/InstCombine/InstructionCombining.cpp b/llvm/lib/Transforms/InstCombine/InstructionCombining.cpp index 7f2018b3a19..249f4a7710e 100644 --- a/llvm/lib/Transforms/InstCombine/InstructionCombining.cpp +++ b/llvm/lib/Transforms/InstCombine/InstructionCombining.cpp @@ -740,6 +740,93 @@ static Value *tryFactorization(BinaryOperator &I, const SimplifyQuery &SQ, return RetVal; } +// If `I` has one Const operand and the other matches `(ctpop (not x))`, +// replace `(ctpop (not x))` with `(sub nuw nsw BitWidth(x), (ctpop x))`. +// This is only useful is the new subtract can fold so we only handle the +// following cases: +// 1) (add/sub/disjoint_or C, (ctpop (not x)) +// -> (add/sub/disjoint_or C', (ctpop x)) +// 1) (cmp pred C, (ctpop (not x)) +// -> (cmp pred C', (ctpop x)) +Instruction *InstCombinerImpl::tryFoldInstWithCtpopWithNot(Instruction *I) { + unsigned Opc = I->getOpcode(); + unsigned ConstIdx = 1; + switch (Opc) { + default: + return nullptr; + // (ctpop (not x)) <-> (sub nuw nsw BitWidth(x) - (ctpop x)) + // We can fold the BitWidth(x) with add/sub/icmp as long the other operand + // is constant. + case Instruction::Sub: + ConstIdx = 0; + break; + case Instruction::ICmp: + // Signed predicates aren't correct in some edge cases like for i2 types, as + // well since (ctpop x) is known [0, log2(BitWidth(x))] almost all signed + // comparisons against it are simplfied to unsigned. + if (cast(I)->isSigned()) + return nullptr; + break; + case Instruction::Or: + if (!match(I, m_DisjointOr(m_Value(), m_Value()))) + return nullptr; + [[fallthrough]]; + case Instruction::Add: + break; + } + + Value *Op; + // Find ctpop. + if (!match(I->getOperand(1 - ConstIdx), + m_OneUse(m_Intrinsic(m_Value(Op))))) + return nullptr; + + Constant *C; + // Check other operand is ImmConstant. + if (!match(I->getOperand(ConstIdx), m_ImmConstant(C))) + return nullptr; + + Type *Ty = Op->getType(); + Constant *BitWidthC = ConstantInt::get(Ty, Ty->getScalarSizeInBits()); + // Need extra check for icmp. Note if this check is true, it generally means + // the icmp will simplify to true/false. + if (Opc == Instruction::ICmp && !cast(I)->isEquality() && + !ConstantExpr::getICmp(ICmpInst::ICMP_UGT, C, BitWidthC)->isZeroValue()) + return nullptr; + + // Check we can invert `(not x)` for free. + bool Consumes = false; + if (!isFreeToInvert(Op, Op->hasOneUse(), Consumes) || !Consumes) + return nullptr; + Value *NotOp = getFreelyInverted(Op, Op->hasOneUse(), &Builder); + assert(NotOp != nullptr && + "Desync between isFreeToInvert and getFreelyInverted"); + + Value *CtpopOfNotOp = Builder.CreateIntrinsic(Ty, Intrinsic::ctpop, NotOp); + + Value *R = nullptr; + + // Do the transformation here to avoid potentially introducing an infinite + // loop. + switch (Opc) { + case Instruction::Sub: + R = Builder.CreateAdd(CtpopOfNotOp, ConstantExpr::getSub(C, BitWidthC)); + break; + case Instruction::Or: + case Instruction::Add: + R = Builder.CreateSub(ConstantExpr::getAdd(C, BitWidthC), CtpopOfNotOp); + break; + case Instruction::ICmp: + R = Builder.CreateICmp(cast(I)->getSwappedPredicate(), + CtpopOfNotOp, ConstantExpr::getSub(BitWidthC, C)); + break; + default: + llvm_unreachable("Unhandled Opcode"); + } + assert(R != nullptr); + return replaceInstUsesWith(*I, R); +} + // (Binop1 (Binop2 (logic_shift X, C), C1), (logic_shift Y, C)) // IFF // 1) the logic_shifts match @@ -4435,7 +4522,7 @@ bool InstCombinerImpl::run() { if (isa(I)) // PHI -> Non-PHI InsertPos = InstParent->getFirstInsertionPt(); else // Non-PHI -> PHI - InsertPos = InstParent->getFirstNonPHI()->getIterator(); + InsertPos = InstParent->getFirstNonPHIIt(); } Result->insertInto(InstParent, InsertPos); diff --git a/llvm/lib/Transforms/Instrumentation/AddressSanitizer.cpp b/llvm/lib/Transforms/Instrumentation/AddressSanitizer.cpp index 5e7e08eaa99..caab98c732e 100644 --- a/llvm/lib/Transforms/Instrumentation/AddressSanitizer.cpp +++ b/llvm/lib/Transforms/Instrumentation/AddressSanitizer.cpp @@ -1590,8 +1590,7 @@ void AddressSanitizer::instrumentMaskedLoadOrStore( InstrumentedAddress = IRB.CreateExtractElement(Addr, Index); } else if (Stride) { Index = IRB.CreateMul(Index, Stride); - Addr = IRB.CreateBitCast(Addr, PointerType::getUnqual(*C)); - InstrumentedAddress = IRB.CreateGEP(Type::getInt8Ty(*C), Addr, {Index}); + InstrumentedAddress = IRB.CreatePtrAdd(Addr, Index); } else { InstrumentedAddress = IRB.CreateGEP(VTy, Addr, {Zero, Index}); } @@ -2079,6 +2078,8 @@ bool ModuleAddressSanitizer::ShouldUseMachOGlobalsSection() const { return true; if (TargetTriple.isDriverKit()) return true; + if (TargetTriple.isXROS()) + return true; return false; } diff --git a/llvm/lib/Transforms/Instrumentation/CGProfile.cpp b/llvm/lib/Transforms/Instrumentation/CGProfile.cpp index e2e5f21b376..c322d0abd6b 100644 --- a/llvm/lib/Transforms/Instrumentation/CGProfile.cpp +++ b/llvm/lib/Transforms/Instrumentation/CGProfile.cpp @@ -44,8 +44,8 @@ addModuleFlags(Module &M, return true; } -static bool runCGProfilePass( - Module &M, FunctionAnalysisManager &FAM) { +static bool runCGProfilePass(Module &M, FunctionAnalysisManager &FAM, + bool InLTO) { MapVector, uint64_t> Counts; InstrProfSymtab Symtab; auto UpdateCounts = [&](TargetTransformInfo &TTI, Function *F, @@ -59,7 +59,7 @@ static bool runCGProfilePass( Count = SaturatingAdd(Count, NewCount); }; // Ignore error here. Indirect calls are ignored if this fails. - (void)(bool) Symtab.create(M); + (void)(bool)Symtab.create(M, InLTO); for (auto &F : M) { // Avoid extra cost of running passes for BFI when the function doesn't have // entry count. @@ -101,7 +101,7 @@ static bool runCGProfilePass( PreservedAnalyses CGProfilePass::run(Module &M, ModuleAnalysisManager &MAM) { FunctionAnalysisManager &FAM = MAM.getResult(M).getManager(); - runCGProfilePass(M, FAM); + runCGProfilePass(M, FAM, InLTO); return PreservedAnalyses::all(); } diff --git a/llvm/lib/Transforms/Instrumentation/GCOVProfiling.cpp b/llvm/lib/Transforms/Instrumentation/GCOVProfiling.cpp index 1ff0a34bae2..c7f6f2a43c1 100644 --- a/llvm/lib/Transforms/Instrumentation/GCOVProfiling.cpp +++ b/llvm/lib/Transforms/Instrumentation/GCOVProfiling.cpp @@ -535,7 +535,7 @@ std::string GCOVProfiler::mangleName(const DICompileUnit *CU, SmallString<128> Filename = GCovFile->getString(); sys::path::replace_extension(Filename, Notes ? "gcno" : "gcda"); - return std::string(Filename.str()); + return std::string(Filename); } } @@ -546,7 +546,7 @@ std::string GCOVProfiler::mangleName(const DICompileUnit *CU, if (sys::fs::current_path(CurPath)) return std::string(FName); sys::path::append(CurPath, FName); - return std::string(CurPath.str()); + return std::string(CurPath); } bool GCOVProfiler::runOnModule( diff --git a/llvm/lib/Transforms/Instrumentation/HWAddressSanitizer.cpp b/llvm/lib/Transforms/Instrumentation/HWAddressSanitizer.cpp index f7f8fed643e..efb621cde90 100644 --- a/llvm/lib/Transforms/Instrumentation/HWAddressSanitizer.cpp +++ b/llvm/lib/Transforms/Instrumentation/HWAddressSanitizer.cpp @@ -862,7 +862,7 @@ Value *HWAddressSanitizer::memToShadow(Value *Mem, IRBuilder<> &IRB) { if (Mapping.Offset == 0) return IRB.CreateIntToPtr(Shadow, PtrTy); // (Mem >> Scale) + Offset - return IRB.CreateGEP(Int8Ty, ShadowBase, Shadow); + return IRB.CreatePtrAdd(ShadowBase, Shadow); } int64_t HWAddressSanitizer::getAccessInfo(bool IsWrite, diff --git a/llvm/lib/Transforms/Instrumentation/MemorySanitizer.cpp b/llvm/lib/Transforms/Instrumentation/MemorySanitizer.cpp index 94af63da38c..15bca538860 100644 --- a/llvm/lib/Transforms/Instrumentation/MemorySanitizer.cpp +++ b/llvm/lib/Transforms/Instrumentation/MemorySanitizer.cpp @@ -4103,7 +4103,11 @@ struct MemorySanitizerVisitor : public InstVisitor { // do the usual thing: check argument shadow and mark all outputs as // clean. Note that any side effects of the inline asm that are not // immediately visible in its constraints are not handled. - if (ClHandleAsmConservative && MS.CompileKernel) + // For now, handle inline asm by default for KMSAN. + bool HandleAsm = ClHandleAsmConservative.getNumOccurrences() + ? ClHandleAsmConservative + : MS.CompileKernel; + if (HandleAsm) visitAsmInstruction(CB); else visitInstruction(CB); @@ -4557,7 +4561,15 @@ struct MemorySanitizerVisitor : public InstVisitor { return; Value *SizeVal = IRB.CreateTypeSize(MS.IntptrTy, DL.getTypeStoreSize(ElemTy)); - IRB.CreateCall(MS.MsanInstrumentAsmStoreFn, {Operand, SizeVal}); + if (MS.CompileKernel) { + IRB.CreateCall(MS.MsanInstrumentAsmStoreFn, {Operand, SizeVal}); + } else { + // ElemTy, derived from elementtype(), does not encode the alignment of + // the pointer. Conservatively assume that the shadow memory is unaligned. + auto [ShadowPtr, _] = + getShadowOriginPtrUserspace(Operand, IRB, IRB.getInt8Ty(), Align(1)); + IRB.CreateAlignedStore(getCleanShadow(ElemTy), ShadowPtr, Align(1)); + } } /// Get the number of output arguments returned by pointers. @@ -5253,8 +5265,8 @@ struct VarArgAArch64Helper : public VarArgHelperBase { Align(8), /*isStore*/ true) .first; - Value *GrSrcPtr = IRB.CreateInBoundsGEP(IRB.getInt8Ty(), VAArgTLSCopy, - GrRegSaveAreaShadowPtrOff); + Value *GrSrcPtr = + IRB.CreateInBoundsPtrAdd(VAArgTLSCopy, GrRegSaveAreaShadowPtrOff); Value *GrCopySize = IRB.CreateSub(GrArgSize, GrRegSaveAreaShadowPtrOff); IRB.CreateMemCpy(GrRegSaveAreaShadowPtr, Align(8), GrSrcPtr, Align(8), @@ -5269,10 +5281,9 @@ struct VarArgAArch64Helper : public VarArgHelperBase { Align(8), /*isStore*/ true) .first; - Value *VrSrcPtr = IRB.CreateInBoundsGEP( - IRB.getInt8Ty(), - IRB.CreateInBoundsGEP(IRB.getInt8Ty(), VAArgTLSCopy, - IRB.getInt32(AArch64VrBegOffset)), + Value *VrSrcPtr = IRB.CreateInBoundsPtrAdd( + IRB.CreateInBoundsPtrAdd(VAArgTLSCopy, + IRB.getInt32(AArch64VrBegOffset)), VrRegSaveAreaShadowPtrOff); Value *VrCopySize = IRB.CreateSub(VrArgSize, VrRegSaveAreaShadowPtrOff); @@ -5285,8 +5296,8 @@ struct VarArgAArch64Helper : public VarArgHelperBase { Align(16), /*isStore*/ true) .first; - Value *StackSrcPtr = IRB.CreateInBoundsGEP( - IRB.getInt8Ty(), VAArgTLSCopy, IRB.getInt32(AArch64VAEndOffset)); + Value *StackSrcPtr = IRB.CreateInBoundsPtrAdd( + VAArgTLSCopy, IRB.getInt32(AArch64VAEndOffset)); IRB.CreateMemCpy(StackSaveAreaShadowPtr, Align(16), StackSrcPtr, Align(16), VAArgOverflowSize); diff --git a/llvm/lib/Transforms/Instrumentation/SanitizerCoverage.cpp b/llvm/lib/Transforms/Instrumentation/SanitizerCoverage.cpp index ce570bdfd8b..17c1c442384 100644 --- a/llvm/lib/Transforms/Instrumentation/SanitizerCoverage.cpp +++ b/llvm/lib/Transforms/Instrumentation/SanitizerCoverage.cpp @@ -329,8 +329,8 @@ ModuleSanitizerCoverage::CreateSecStartEnd(Module &M, const char *Section, // Account for the fact that on windows-msvc __start_* symbols actually // point to a uint64_t before the start of the array. - auto GEP = IRB.CreateGEP(Int8Ty, SecStart, - ConstantInt::get(IntptrTy, sizeof(uint64_t))); + auto GEP = + IRB.CreatePtrAdd(SecStart, ConstantInt::get(IntptrTy, sizeof(uint64_t))); return std::make_pair(GEP, SecEnd); } diff --git a/llvm/lib/Transforms/ObjCARC/DependencyAnalysis.cpp b/llvm/lib/Transforms/ObjCARC/DependencyAnalysis.cpp index 0fea6bcc488..7af9c39f823 100644 --- a/llvm/lib/Transforms/ObjCARC/DependencyAnalysis.cpp +++ b/llvm/lib/Transforms/ObjCARC/DependencyAnalysis.cpp @@ -242,7 +242,7 @@ static bool findDependencies(DependenceKind Flavor, const Value *Arg, } while (!Worklist.empty()); // Determine whether the original StartBB post-dominates all of the blocks we - // visited. If not, insert a sentinal indicating that most optimizations are + // visited. If not, insert a sentinel indicating that most optimizations are // not safe. for (const BasicBlock *BB : Visited) { if (BB == StartBB) diff --git a/llvm/lib/Transforms/Scalar/ADCE.cpp b/llvm/lib/Transforms/Scalar/ADCE.cpp index 9af275a9f4e..90b544c8922 100644 --- a/llvm/lib/Transforms/Scalar/ADCE.cpp +++ b/llvm/lib/Transforms/Scalar/ADCE.cpp @@ -549,6 +549,11 @@ ADCEChanged AggressiveDeadCodeElimination::removeDeadInstructions() { // like the rest of this loop does. Extending support to assignment tracking // is future work. for (DPValue &DPV : make_early_inc_range(I.getDbgValueRange())) { + // Avoid removing a DPV that is linked to instructions because it holds + // information about an existing store. + if (DPV.isDbgAssign()) + if (!at::getAssignmentInsts(&DPV).empty()) + continue; if (AliveScopes.count(DPV.getDebugLoc()->getScope())) continue; I.dropOneDbgValue(&DPV); diff --git a/llvm/lib/Transforms/Scalar/ConstantHoisting.cpp b/llvm/lib/Transforms/Scalar/ConstantHoisting.cpp index 9e40d94dd73..49f8761a139 100644 --- a/llvm/lib/Transforms/Scalar/ConstantHoisting.cpp +++ b/llvm/lib/Transforms/Scalar/ConstantHoisting.cpp @@ -576,9 +576,6 @@ ConstantHoistingPass::maximizeConstantsInRange(ConstCandVecType::iterator S, ConstCandVecType::iterator &MaxCostItr) { unsigned NumUses = 0; - bool OptForSize = Entry->getParent()->hasOptSize() || - llvm::shouldOptimizeForSize(Entry->getParent(), PSI, BFI, - PGSOQueryType::IRPass); if (!OptForSize || std::distance(S,E) > 100) { for (auto ConstCand = S; ConstCand != E; ++ConstCand) { NumUses += ConstCand->Uses.size(); @@ -948,6 +945,10 @@ bool ConstantHoistingPass::runImpl(Function &Fn, TargetTransformInfo &TTI, this->Ctx = &Fn.getContext(); this->Entry = &Entry; this->PSI = PSI; + this->OptForSize = Entry.getParent()->hasOptSize() || + llvm::shouldOptimizeForSize(Entry.getParent(), PSI, BFI, + PGSOQueryType::IRPass); + // Collect all constant candidates. collectConstantCandidates(Fn); diff --git a/llvm/lib/Transforms/Scalar/ConstraintElimination.cpp b/llvm/lib/Transforms/Scalar/ConstraintElimination.cpp index 6fec54ac792..8f09569d0d9 100644 --- a/llvm/lib/Transforms/Scalar/ConstraintElimination.cpp +++ b/llvm/lib/Transforms/Scalar/ConstraintElimination.cpp @@ -1314,9 +1314,7 @@ static void generateReproducer(CmpInst *Cond, Module *M, static std::optional checkCondition(CmpInst::Predicate Pred, Value *A, Value *B, Instruction *CheckInst, - ConstraintInfo &Info, unsigned NumIn, - unsigned NumOut, - Instruction *ContextInst) { + ConstraintInfo &Info) { LLVM_DEBUG(dbgs() << "Checking " << *CheckInst << "\n"); auto R = Info.getConstraintForSolving(Pred, A, B); @@ -1385,9 +1383,9 @@ static bool checkAndReplaceCondition( return true; }; - if (auto ImpliedCondition = checkCondition( - Cmp->getPredicate(), Cmp->getOperand(0), Cmp->getOperand(1), Cmp, - Info, NumIn, NumOut, ContextInst)) + if (auto ImpliedCondition = + checkCondition(Cmp->getPredicate(), Cmp->getOperand(0), + Cmp->getOperand(1), Cmp, Info)) return ReplaceCmpWithConstant(Cmp, *ImpliedCondition); return false; } @@ -1446,8 +1444,7 @@ static bool checkOrAndOpImpliedByOther( // Check if the second condition can be simplified now. if (auto ImpliedCondition = checkCondition(CmpToCheck->getPredicate(), CmpToCheck->getOperand(0), - CmpToCheck->getOperand(1), CmpToCheck, Info, CB.NumIn, - CB.NumOut, CB.getContextInst())) { + CmpToCheck->getOperand(1), CmpToCheck, Info)) { if (IsOr && isa(JoinOp)) { JoinOp->setOperand( OtherOpIdx == 0 ? 2 : 0, diff --git a/llvm/lib/Transforms/Scalar/DFAJumpThreading.cpp b/llvm/lib/Transforms/Scalar/DFAJumpThreading.cpp index c5bf913cda3..85d4065286e 100644 --- a/llvm/lib/Transforms/Scalar/DFAJumpThreading.cpp +++ b/llvm/lib/Transforms/Scalar/DFAJumpThreading.cpp @@ -307,7 +307,7 @@ void unfold(DomTreeUpdater *DTU, SelectInstToUnfold SIToUnfold, struct ClonedBlock { BasicBlock *BB; - uint64_t State; ///< \p State corresponds to the next value of a switch stmnt. + APInt State; ///< \p State corresponds to the next value of a switch stmnt. }; typedef std::deque PathType; @@ -344,9 +344,9 @@ inline raw_ostream &operator<<(raw_ostream &OS, const PathType &Path) { /// exit state, and the block that determines the next state. struct ThreadingPath { /// Exit value is DFA's exit state for the given path. - uint64_t getExitValue() const { return ExitVal; } + APInt getExitValue() const { return ExitVal; } void setExitValue(const ConstantInt *V) { - ExitVal = V->getZExtValue(); + ExitVal = V->getValue(); IsExitValSet = true; } bool isExitValueSet() const { return IsExitValSet; } @@ -365,7 +365,7 @@ struct ThreadingPath { private: PathType Path; - uint64_t ExitVal; + APInt ExitVal; const BasicBlock *DBB = nullptr; bool IsExitValSet = false; }; @@ -744,7 +744,7 @@ private: for (ThreadingPath &TPath : SwitchPaths->getThreadingPaths()) { PathType PathBBs = TPath.getPath(); - uint64_t NextState = TPath.getExitValue(); + APInt NextState = TPath.getExitValue(); const BasicBlock *Determinator = TPath.getDeterminatorBB(); // Update Metrics for the Switch block, this is always cloned @@ -901,7 +901,7 @@ private: DuplicateBlockMap &DuplicateMap, SmallSet &BlocksToClean, DomTreeUpdater *DTU) { - uint64_t NextState = Path.getExitValue(); + APInt NextState = Path.getExitValue(); const BasicBlock *Determinator = Path.getDeterminatorBB(); PathType PathBBs = Path.getPath(); @@ -910,8 +910,9 @@ private: PathBBs.pop_front(); auto DetIt = llvm::find(PathBBs, Determinator); - auto Prev = std::prev(DetIt); - BasicBlock *PrevBB = *Prev; + // When there is only one BB in PathBBs, the determinator takes itself as a + // direct predecessor. + BasicBlock *PrevBB = PathBBs.size() == 1 ? *DetIt : *std::prev(DetIt); for (auto BBIt = DetIt; BBIt != PathBBs.end(); BBIt++) { BasicBlock *BB = *BBIt; BlocksToClean.insert(BB); @@ -993,13 +994,14 @@ private: /// This function also includes updating phi nodes in the successors of the /// BB, and remapping uses that were defined locally in the cloned BB. BasicBlock *cloneBlockAndUpdatePredecessor(BasicBlock *BB, BasicBlock *PrevBB, - uint64_t NextState, + const APInt &NextState, DuplicateBlockMap &DuplicateMap, DefMap &NewDefs, DomTreeUpdater *DTU) { ValueToValueMapTy VMap; BasicBlock *NewBB = CloneBasicBlock( - BB, VMap, ".jt" + std::to_string(NextState), BB->getParent()); + BB, VMap, ".jt" + std::to_string(NextState.getLimitedValue()), + BB->getParent()); NewBB->moveAfter(BB); NumCloned++; @@ -1034,7 +1036,7 @@ private: /// This means creating a new incoming value from NewBB with the new /// instruction wherever there is an incoming value from BB. void updateSuccessorPhis(BasicBlock *BB, BasicBlock *ClonedBB, - uint64_t NextState, ValueToValueMapTy &VMap, + const APInt &NextState, ValueToValueMapTy &VMap, DuplicateBlockMap &DuplicateMap) { std::vector BlocksToUpdate; @@ -1144,7 +1146,7 @@ private: void updateLastSuccessor(ThreadingPath &TPath, DuplicateBlockMap &DuplicateMap, DomTreeUpdater *DTU) { - uint64_t NextState = TPath.getExitValue(); + APInt NextState = TPath.getExitValue(); BasicBlock *BB = TPath.getPath().back(); BasicBlock *LastBlock = getClonedBB(BB, NextState, DuplicateMap); @@ -1198,7 +1200,7 @@ private: /// Checks if BB was already cloned for a particular next state value. If it /// was then it returns this cloned block, and otherwise null. - BasicBlock *getClonedBB(BasicBlock *BB, uint64_t NextState, + BasicBlock *getClonedBB(BasicBlock *BB, const APInt &NextState, DuplicateBlockMap &DuplicateMap) { CloneList ClonedBBs = DuplicateMap[BB]; @@ -1212,10 +1214,10 @@ private: /// Helper to get the successor corresponding to a particular case value for /// a switch statement. - BasicBlock *getNextCaseSuccessor(SwitchInst *Switch, uint64_t NextState) { + BasicBlock *getNextCaseSuccessor(SwitchInst *Switch, const APInt &NextState) { BasicBlock *NextCase = nullptr; for (auto Case : Switch->cases()) { - if (Case.getCaseValue()->getZExtValue() == NextState) { + if (Case.getCaseValue()->getValue() == NextState) { NextCase = Case.getCaseSuccessor(); break; } diff --git a/llvm/lib/Transforms/Scalar/DeadStoreElimination.cpp b/llvm/lib/Transforms/Scalar/DeadStoreElimination.cpp index 008dcc53fd4..11a91bfbe5b 100644 --- a/llvm/lib/Transforms/Scalar/DeadStoreElimination.cpp +++ b/llvm/lib/Transforms/Scalar/DeadStoreElimination.cpp @@ -488,27 +488,27 @@ static void shortenAssignment(Instruction *Inst, Value *OriginalDest, uint64_t DeadSliceSizeInBits = OldSizeInBits - NewSizeInBits; uint64_t DeadSliceOffsetInBits = OldOffsetInBits + (IsOverwriteEnd ? NewSizeInBits : 0); - auto SetDeadFragExpr = [](DbgAssignIntrinsic *DAI, + auto SetDeadFragExpr = [](auto *Assign, DIExpression::FragmentInfo DeadFragment) { // createFragmentExpression expects an offset relative to the existing // fragment offset if there is one. uint64_t RelativeOffset = DeadFragment.OffsetInBits - - DAI->getExpression() + Assign->getExpression() ->getFragmentInfo() .value_or(DIExpression::FragmentInfo(0, 0)) .OffsetInBits; if (auto NewExpr = DIExpression::createFragmentExpression( - DAI->getExpression(), RelativeOffset, DeadFragment.SizeInBits)) { - DAI->setExpression(*NewExpr); + Assign->getExpression(), RelativeOffset, DeadFragment.SizeInBits)) { + Assign->setExpression(*NewExpr); return; } // Failed to create a fragment expression for this so discard the value, // making this a kill location. auto *Expr = *DIExpression::createFragmentExpression( - DIExpression::get(DAI->getContext(), std::nullopt), + DIExpression::get(Assign->getContext(), std::nullopt), DeadFragment.OffsetInBits, DeadFragment.SizeInBits); - DAI->setExpression(Expr); - DAI->setKillLocation(); + Assign->setExpression(Expr); + Assign->setKillLocation(); }; // A DIAssignID to use so that the inserted dbg.assign intrinsics do not @@ -526,32 +526,35 @@ static void shortenAssignment(Instruction *Inst, Value *OriginalDest, // returned by getAssignmentMarkers so save a copy of the markers to iterate // over. auto LinkedRange = at::getAssignmentMarkers(Inst); + SmallVector LinkedDPVAssigns = at::getDPVAssignmentMarkers(Inst); SmallVector Linked(LinkedRange.begin(), LinkedRange.end()); - for (auto *DAI : Linked) { + auto InsertAssignForOverlap = [&](auto *Assign) { std::optional NewFragment; if (!at::calculateFragmentIntersect(DL, OriginalDest, DeadSliceOffsetInBits, - DeadSliceSizeInBits, DAI, + DeadSliceSizeInBits, Assign, NewFragment) || !NewFragment) { // We couldn't calculate the intersecting fragment for some reason. Be // cautious and unlink the whole assignment from the store. - DAI->setKillAddress(); - DAI->setAssignId(GetDeadLink()); - continue; + Assign->setKillAddress(); + Assign->setAssignId(GetDeadLink()); + return; } // No intersect. if (NewFragment->SizeInBits == 0) - continue; + return; // Fragments overlap: insert a new dbg.assign for this dead part. - auto *NewAssign = cast(DAI->clone()); - NewAssign->insertAfter(DAI); + auto *NewAssign = static_cast(Assign->clone()); + NewAssign->insertAfter(Assign); NewAssign->setAssignId(GetDeadLink()); if (NewFragment) SetDeadFragExpr(NewAssign, *NewFragment); NewAssign->setKillAddress(); - } + }; + for_each(Linked, InsertAssignForOverlap); + for_each(LinkedDPVAssigns, InsertAssignForOverlap); } static bool tryToShorten(Instruction *DeadI, int64_t &DeadStart, diff --git a/llvm/lib/Transforms/Scalar/LICM.cpp b/llvm/lib/Transforms/Scalar/LICM.cpp index 9117378568b..f3e40a5cb80 100644 --- a/llvm/lib/Transforms/Scalar/LICM.cpp +++ b/llvm/lib/Transforms/Scalar/LICM.cpp @@ -2323,8 +2323,8 @@ collectPromotionCandidates(MemorySSA *MSSA, AliasAnalysis *AA, Loop *L) { SmallVector, bool>, 0> Result; for (auto [Set, HasReadsOutsideSet] : Sets) { SmallSetVector PointerMustAliases; - for (const auto &ASI : *Set) - PointerMustAliases.insert(ASI.getValue()); + for (const auto &MemLoc : *Set) + PointerMustAliases.insert(const_cast(MemLoc.Ptr)); Result.emplace_back(std::move(PointerMustAliases), HasReadsOutsideSet); } diff --git a/llvm/lib/Transforms/Scalar/LoopDeletion.cpp b/llvm/lib/Transforms/Scalar/LoopDeletion.cpp index c041e3621a1..bfe9374cf2f 100644 --- a/llvm/lib/Transforms/Scalar/LoopDeletion.cpp +++ b/llvm/lib/Transforms/Scalar/LoopDeletion.cpp @@ -452,6 +452,13 @@ static LoopDeletionResult deleteLoopIfDead(Loop *L, DominatorTree &DT, BasicBlock *ExitBlock = L->getUniqueExitBlock(); + // We can't directly branch to an EH pad. Don't bother handling this edge + // case. + if (ExitBlock && ExitBlock->isEHPad()) { + LLVM_DEBUG(dbgs() << "Cannot delete loop exiting to EH pad.\n"); + return LoopDeletionResult::Unmodified; + } + if (ExitBlock && isLoopNeverExecuted(L)) { LLVM_DEBUG(dbgs() << "Loop is proven to never execute, delete it!\n"); // We need to forget the loop before setting the incoming values of the exit @@ -487,13 +494,6 @@ static LoopDeletionResult deleteLoopIfDead(Loop *L, DominatorTree &DT, return LoopDeletionResult::Unmodified; } - // We can't directly branch to an EH pad. Don't bother handling this edge - // case. - if (ExitBlock && ExitBlock->isEHPad()) { - LLVM_DEBUG(dbgs() << "Cannot delete loop exiting to EH pad.\n"); - return LoopDeletionResult::Unmodified; - } - // Finally, we have to check that the loop really is dead. bool Changed = false; if (!isLoopDead(L, SE, ExitingBlocks, ExitBlock, Changed, Preheader, LI)) { diff --git a/llvm/lib/Transforms/Scalar/LoopStrengthReduce.cpp b/llvm/lib/Transforms/Scalar/LoopStrengthReduce.cpp index a58bbe31856..7ebc5da8b25 100644 --- a/llvm/lib/Transforms/Scalar/LoopStrengthReduce.cpp +++ b/llvm/lib/Transforms/Scalar/LoopStrengthReduce.cpp @@ -6366,10 +6366,12 @@ struct SCEVDbgValueBuilder { /// and DIExpression. struct DVIRecoveryRec { DVIRecoveryRec(DbgValueInst *DbgValue) - : DVI(DbgValue), Expr(DbgValue->getExpression()), + : DbgRef(DbgValue), Expr(DbgValue->getExpression()), HadLocationArgList(false) {} + DVIRecoveryRec(DPValue *DPV) + : DbgRef(DPV), Expr(DPV->getExpression()), HadLocationArgList(false) {} - DbgValueInst *DVI; + PointerUnion DbgRef; DIExpression *Expr; bool HadLocationArgList; SmallVector LocationOps; @@ -6401,17 +6403,19 @@ static unsigned numLLVMArgOps(SmallVectorImpl &Expr) { /// Overwrites DVI with the location and Ops as the DIExpression. This will /// create an invalid expression if Ops has any dwarf::DW_OP_llvm_arg operands, /// because a DIArglist is not created for the first argument of the dbg.value. -static void updateDVIWithLocation(DbgValueInst &DVI, Value *Location, +template +static void updateDVIWithLocation(T &DbgVal, Value *Location, SmallVectorImpl &Ops) { - assert( - numLLVMArgOps(Ops) == 0 && - "Expected expression that does not contain any DW_OP_llvm_arg operands."); - DVI.setRawLocation(ValueAsMetadata::get(Location)); - DVI.setExpression(DIExpression::get(DVI.getContext(), Ops)); + assert(numLLVMArgOps(Ops) == 0 && "Expected expression that does not " + "contain any DW_OP_llvm_arg operands."); + DbgVal.setRawLocation(ValueAsMetadata::get(Location)); + DbgVal.setExpression(DIExpression::get(DbgVal.getContext(), Ops)); + DbgVal.setExpression(DIExpression::get(DbgVal.getContext(), Ops)); } /// Overwrite DVI with locations placed into a DIArglist. -static void updateDVIWithLocations(DbgValueInst &DVI, +template +static void updateDVIWithLocations(T &DbgVal, SmallVectorImpl &Locations, SmallVectorImpl &Ops) { assert(numLLVMArgOps(Ops) != 0 && @@ -6421,8 +6425,8 @@ static void updateDVIWithLocations(DbgValueInst &DVI, for (Value *V : Locations) MetadataLocs.push_back(ValueAsMetadata::get(V)); auto ValArrayRef = llvm::ArrayRef(MetadataLocs); - DVI.setRawLocation(llvm::DIArgList::get(DVI.getContext(), ValArrayRef)); - DVI.setExpression(DIExpression::get(DVI.getContext(), Ops)); + DbgVal.setRawLocation(llvm::DIArgList::get(DbgVal.getContext(), ValArrayRef)); + DbgVal.setExpression(DIExpression::get(DbgVal.getContext(), Ops)); } /// Write the new expression and new location ops for the dbg.value. If possible @@ -6433,30 +6437,37 @@ static void updateDVIWithLocations(DbgValueInst &DVI, static void UpdateDbgValueInst(DVIRecoveryRec &DVIRec, SmallVectorImpl &NewLocationOps, SmallVectorImpl &NewExpr) { - unsigned NumLLVMArgs = numLLVMArgOps(NewExpr); - if (NumLLVMArgs == 0) { - // Location assumed to be on the stack. - updateDVIWithLocation(*DVIRec.DVI, NewLocationOps[0], NewExpr); - } else if (NumLLVMArgs == 1 && NewExpr[0] == dwarf::DW_OP_LLVM_arg) { - // There is only a single DW_OP_llvm_arg at the start of the expression, - // so it can be omitted along with DIArglist. - assert(NewExpr[1] == 0 && - "Lone LLVM_arg in a DIExpression should refer to location-op 0."); - llvm::SmallVector ShortenedOps(llvm::drop_begin(NewExpr, 2)); - updateDVIWithLocation(*DVIRec.DVI, NewLocationOps[0], ShortenedOps); - } else { - // Multiple DW_OP_llvm_arg, so DIArgList is strictly necessary. - updateDVIWithLocations(*DVIRec.DVI, NewLocationOps, NewExpr); - } + auto UpdateDbgValueInstImpl = [&](auto *DbgVal) { + unsigned NumLLVMArgs = numLLVMArgOps(NewExpr); + if (NumLLVMArgs == 0) { + // Location assumed to be on the stack. + updateDVIWithLocation(*DbgVal, NewLocationOps[0], NewExpr); + } else if (NumLLVMArgs == 1 && NewExpr[0] == dwarf::DW_OP_LLVM_arg) { + // There is only a single DW_OP_llvm_arg at the start of the expression, + // so it can be omitted along with DIArglist. + assert(NewExpr[1] == 0 && + "Lone LLVM_arg in a DIExpression should refer to location-op 0."); + llvm::SmallVector ShortenedOps(llvm::drop_begin(NewExpr, 2)); + updateDVIWithLocation(*DbgVal, NewLocationOps[0], ShortenedOps); + } else { + // Multiple DW_OP_llvm_arg, so DIArgList is strictly necessary. + updateDVIWithLocations(*DbgVal, NewLocationOps, NewExpr); + } - // If the DIExpression was previously empty then add the stack terminator. - // Non-empty expressions have only had elements inserted into them and so the - // terminator should already be present e.g. stack_value or fragment. - DIExpression *SalvageExpr = DVIRec.DVI->getExpression(); - if (!DVIRec.Expr->isComplex() && SalvageExpr->isComplex()) { - SalvageExpr = DIExpression::append(SalvageExpr, {dwarf::DW_OP_stack_value}); - DVIRec.DVI->setExpression(SalvageExpr); - } + // If the DIExpression was previously empty then add the stack terminator. + // Non-empty expressions have only had elements inserted into them and so + // the terminator should already be present e.g. stack_value or fragment. + DIExpression *SalvageExpr = DbgVal->getExpression(); + if (!DVIRec.Expr->isComplex() && SalvageExpr->isComplex()) { + SalvageExpr = + DIExpression::append(SalvageExpr, {dwarf::DW_OP_stack_value}); + DbgVal->setExpression(SalvageExpr); + } + }; + if (isa(DVIRec.DbgRef)) + UpdateDbgValueInstImpl(cast(DVIRec.DbgRef)); + else + UpdateDbgValueInstImpl(cast(DVIRec.DbgRef)); } /// Cached location ops may be erased during LSR, in which case a poison is @@ -6470,40 +6481,49 @@ static Value *getValueOrPoison(WeakVH &VH, LLVMContext &C) { /// Restore the DVI's pre-LSR arguments. Substitute undef for any erased values. static void restorePreTransformState(DVIRecoveryRec &DVIRec) { - LLVM_DEBUG(dbgs() << "scev-salvage: restore dbg.value to pre-LSR state\n" - << "scev-salvage: post-LSR: " << *DVIRec.DVI << '\n'); - assert(DVIRec.Expr && "Expected an expression"); - DVIRec.DVI->setExpression(DVIRec.Expr); + auto RestorePreTransformStateImpl = [&](auto *DbgVal) { + LLVM_DEBUG(dbgs() << "scev-salvage: restore dbg.value to pre-LSR state\n" + << "scev-salvage: post-LSR: " << *DbgVal << '\n'); + assert(DVIRec.Expr && "Expected an expression"); + DbgVal->setExpression(DVIRec.Expr); - // Even a single location-op may be inside a DIArgList and referenced with - // DW_OP_LLVM_arg, which is valid only with a DIArgList. - if (!DVIRec.HadLocationArgList) { - assert(DVIRec.LocationOps.size() == 1 && - "Unexpected number of location ops."); - // LSR's unsuccessful salvage attempt may have added DIArgList, which in - // this case was not present before, so force the location back to a single - // uncontained Value. - Value *CachedValue = - getValueOrPoison(DVIRec.LocationOps[0], DVIRec.DVI->getContext()); - DVIRec.DVI->setRawLocation(ValueAsMetadata::get(CachedValue)); - } else { - SmallVector MetadataLocs; - for (WeakVH VH : DVIRec.LocationOps) { - Value *CachedValue = getValueOrPoison(VH, DVIRec.DVI->getContext()); - MetadataLocs.push_back(ValueAsMetadata::get(CachedValue)); + // Even a single location-op may be inside a DIArgList and referenced with + // DW_OP_LLVM_arg, which is valid only with a DIArgList. + if (!DVIRec.HadLocationArgList) { + assert(DVIRec.LocationOps.size() == 1 && + "Unexpected number of location ops."); + // LSR's unsuccessful salvage attempt may have added DIArgList, which in + // this case was not present before, so force the location back to a + // single uncontained Value. + Value *CachedValue = + getValueOrPoison(DVIRec.LocationOps[0], DbgVal->getContext()); + DbgVal->setRawLocation(ValueAsMetadata::get(CachedValue)); + } else { + SmallVector MetadataLocs; + for (WeakVH VH : DVIRec.LocationOps) { + Value *CachedValue = getValueOrPoison(VH, DbgVal->getContext()); + MetadataLocs.push_back(ValueAsMetadata::get(CachedValue)); + } + auto ValArrayRef = llvm::ArrayRef(MetadataLocs); + DbgVal->setRawLocation( + llvm::DIArgList::get(DbgVal->getContext(), ValArrayRef)); } - auto ValArrayRef = llvm::ArrayRef(MetadataLocs); - DVIRec.DVI->setRawLocation( - llvm::DIArgList::get(DVIRec.DVI->getContext(), ValArrayRef)); - } - LLVM_DEBUG(dbgs() << "scev-salvage: pre-LSR: " << *DVIRec.DVI << '\n'); + LLVM_DEBUG(dbgs() << "scev-salvage: pre-LSR: " << *DbgVal << '\n'); + }; + if (isa(DVIRec.DbgRef)) + RestorePreTransformStateImpl(cast(DVIRec.DbgRef)); + else + RestorePreTransformStateImpl(cast(DVIRec.DbgRef)); } static bool SalvageDVI(llvm::Loop *L, ScalarEvolution &SE, llvm::PHINode *LSRInductionVar, DVIRecoveryRec &DVIRec, const SCEV *SCEVInductionVar, SCEVDbgValueBuilder IterCountExpr) { - if (!DVIRec.DVI->isKillLocation()) + + if (isa(DVIRec.DbgRef) + ? !cast(DVIRec.DbgRef)->isKillLocation() + : !cast(DVIRec.DbgRef)->isKillLocation()) return false; // LSR may have caused several changes to the dbg.value in the failed salvage @@ -6596,16 +6616,20 @@ static bool SalvageDVI(llvm::Loop *L, ScalarEvolution &SE, } UpdateDbgValueInst(DVIRec, NewLocationOps, NewExpr); - LLVM_DEBUG(dbgs() << "scev-salvage: Updated DVI: " << *DVIRec.DVI << "\n"); + if (isa(DVIRec.DbgRef)) + LLVM_DEBUG(dbgs() << "scev-salvage: Updated DVI: " + << *cast(DVIRec.DbgRef) << "\n"); + else + LLVM_DEBUG(dbgs() << "scev-salvage: Updated DVI: " + << *cast(DVIRec.DbgRef) << "\n"); return true; } /// Obtain an expression for the iteration count, then attempt to salvage the /// dbg.value intrinsics. -static void -DbgRewriteSalvageableDVIs(llvm::Loop *L, ScalarEvolution &SE, - llvm::PHINode *LSRInductionVar, - SmallVector, 2> &DVIToUpdate) { +static void DbgRewriteSalvageableDVIs( + llvm::Loop *L, ScalarEvolution &SE, llvm::PHINode *LSRInductionVar, + SmallVector, 2> &DVIToUpdate) { if (DVIToUpdate.empty()) return; @@ -6647,48 +6671,56 @@ static void DbgGatherSalvagableDVI( SmallSet, 2> &DVIHandles) { for (const auto &B : L->getBlocks()) { for (auto &I : *B) { + auto ProcessDbgValue = [&](auto *DbgVal) -> bool { + // Ensure that if any location op is undef that the dbg.vlue is not + // cached. + if (DbgVal->isKillLocation()) + return false; + + // Check that the location op SCEVs are suitable for translation to + // DIExpression. + const auto &HasTranslatableLocationOps = + [&](const auto *DbgValToTranslate) -> bool { + for (const auto LocOp : DbgValToTranslate->location_ops()) { + if (!LocOp) + return false; + + if (!SE.isSCEVable(LocOp->getType())) + return false; + + const SCEV *S = SE.getSCEV(LocOp); + if (SE.containsUndefs(S)) + return false; + } + return true; + }; + + if (!HasTranslatableLocationOps(DbgVal)) + return false; + + std::unique_ptr NewRec = + std::make_unique(DbgVal); + // Each location Op may need a SCEVDbgValueBuilder in order to recover + // it. Pre-allocating a vector will enable quick lookups of the builder + // later during the salvage. + NewRec->RecoveryExprs.resize(DbgVal->getNumVariableLocationOps()); + for (const auto LocOp : DbgVal->location_ops()) { + NewRec->SCEVs.push_back(SE.getSCEV(LocOp)); + NewRec->LocationOps.push_back(LocOp); + NewRec->HadLocationArgList = DbgVal->hasArgList(); + } + SalvageableDVISCEVs.push_back(std::move(NewRec)); + return true; + }; + for (auto &DPV : I.getDbgValueRange()) { + if (DPV.isDbgValue() || DPV.isDbgAssign()) + ProcessDbgValue(&DPV); + } auto DVI = dyn_cast(&I); if (!DVI) continue; - // Ensure that if any location op is undef that the dbg.vlue is not - // cached. - if (DVI->isKillLocation()) - continue; - - // Check that the location op SCEVs are suitable for translation to - // DIExpression. - const auto &HasTranslatableLocationOps = - [&](const DbgValueInst *DVI) -> bool { - for (const auto LocOp : DVI->location_ops()) { - if (!LocOp) - return false; - - if (!SE.isSCEVable(LocOp->getType())) - return false; - - const SCEV *S = SE.getSCEV(LocOp); - if (SE.containsUndefs(S)) - return false; - } - return true; - }; - - if (!HasTranslatableLocationOps(DVI)) - continue; - - std::unique_ptr NewRec = - std::make_unique(DVI); - // Each location Op may need a SCEVDbgValueBuilder in order to recover it. - // Pre-allocating a vector will enable quick lookups of the builder later - // during the salvage. - NewRec->RecoveryExprs.resize(DVI->getNumVariableLocationOps()); - for (const auto LocOp : DVI->location_ops()) { - NewRec->SCEVs.push_back(SE.getSCEV(LocOp)); - NewRec->LocationOps.push_back(LocOp); - NewRec->HadLocationArgList = DVI->hasArgList(); - } - SalvageableDVISCEVs.push_back(std::move(NewRec)); - DVIHandles.insert(DVI); + if (ProcessDbgValue(DVI)) + DVIHandles.insert(DVI); } } } @@ -6816,7 +6848,8 @@ canFoldTermCondOfLoop(Loop *L, ScalarEvolution &SE, DominatorTree &DT, // iteration. The simplest case to consider is a candidate IV which is // narrower than the trip count (and thus original IV), but this can // also happen due to non-unit strides on the candidate IVs. - if (!AddRec->hasNoSelfWrap()) + if (!AddRec->hasNoSelfWrap() || + !SE.isKnownNonZero(AddRec->getStepRecurrence(SE))) continue; const SCEVAddRecExpr *PostInc = AddRec->getPostIncExpr(SE); @@ -6984,7 +7017,7 @@ static bool ReduceLoopStrength(Loop *L, IVUsers &IU, ScalarEvolution &SE, assert(Expander.isSafeToExpand(TermValueS) && "Terminating value was checked safe in canFoldTerminatingCondition"); - // Create new terminating value at loop header + // Create new terminating value at loop preheader Value *TermValue = Expander.expandCodeFor(TermValueS, ToHelpFold->getType(), LoopPreheader->getTerminator()); diff --git a/llvm/lib/Transforms/Scalar/LoopVersioningLICM.cpp b/llvm/lib/Transforms/Scalar/LoopVersioningLICM.cpp index 9d5e6693c0e..f39c2448484 100644 --- a/llvm/lib/Transforms/Scalar/LoopVersioningLICM.cpp +++ b/llvm/lib/Transforms/Scalar/LoopVersioningLICM.cpp @@ -258,13 +258,13 @@ bool LoopVersioningLICM::legalLoopMemoryAccesses() { // With MustAlias its not worth adding runtime bound check. if (AS.isMustAlias()) return false; - Value *SomePtr = AS.begin()->getValue(); + const Value *SomePtr = AS.begin()->Ptr; bool TypeCheck = true; // Check for Mod & MayAlias HasMayAlias |= AS.isMayAlias(); HasMod |= AS.isMod(); - for (const auto &A : AS) { - Value *Ptr = A.getValue(); + for (const auto &MemLoc : AS) { + const Value *Ptr = MemLoc.Ptr; // Alias tracker should have pointers of same data type. // // FIXME: check no longer effective since opaque pointers? diff --git a/llvm/lib/Transforms/Scalar/MemCpyOptimizer.cpp b/llvm/lib/Transforms/Scalar/MemCpyOptimizer.cpp index 9d058e0d248..805bbe40bd7 100644 --- a/llvm/lib/Transforms/Scalar/MemCpyOptimizer.cpp +++ b/llvm/lib/Transforms/Scalar/MemCpyOptimizer.cpp @@ -1297,9 +1297,9 @@ bool MemCpyOptPass::processMemSetMemCpyDependence(MemCpyInst *MemCpy, Value *SizeDiff = Builder.CreateSub(DestSize, SrcSize); Value *MemsetLen = Builder.CreateSelect( Ule, ConstantInt::getNullValue(DestSize->getType()), SizeDiff); - Instruction *NewMemSet = Builder.CreateMemSet( - Builder.CreateGEP(Builder.getInt8Ty(), Dest, SrcSize), - MemSet->getOperand(1), MemsetLen, Alignment); + Instruction *NewMemSet = + Builder.CreateMemSet(Builder.CreatePtrAdd(Dest, SrcSize), + MemSet->getOperand(1), MemsetLen, Alignment); assert(isa(MSSAU->getMemorySSA()->getMemoryAccess(MemCpy)) && "MemCpy must be a MemoryDef"); diff --git a/llvm/lib/Transforms/Scalar/RewriteStatepointsForGC.cpp b/llvm/lib/Transforms/Scalar/RewriteStatepointsForGC.cpp index b98f823ab00..45ce3bf3cea 100644 --- a/llvm/lib/Transforms/Scalar/RewriteStatepointsForGC.cpp +++ b/llvm/lib/Transforms/Scalar/RewriteStatepointsForGC.cpp @@ -967,51 +967,6 @@ static Value *findBasePointer(Value *I, DefiningValueMapTy &Cache, return BDVState(BaseValue, BDVState::Base, BaseValue); }; - bool Progress = true; - while (Progress) { -#ifndef NDEBUG - const size_t OldSize = States.size(); -#endif - Progress = false; - // We're only changing values in this loop, thus safe to keep iterators. - // Since this is computing a fixed point, the order of visit does not - // effect the result. TODO: We could use a worklist here and make this run - // much faster. - for (auto Pair : States) { - Value *BDV = Pair.first; - // Only values that do not have known bases or those that have differing - // type (scalar versus vector) from a possible known base should be in the - // lattice. - assert((!isKnownBase(BDV, KnownBases) || - !areBothVectorOrScalar(BDV, Pair.second.getBaseValue())) && - "why did it get added?"); - - BDVState NewState(BDV); - visitBDVOperands(BDV, [&](Value *Op) { - Value *BDV = findBaseOrBDV(Op, Cache, KnownBases); - auto OpState = GetStateForBDV(BDV, Op); - NewState.meet(OpState); - }); - - BDVState OldState = Pair.second; - if (OldState != NewState) { - Progress = true; - States[BDV] = NewState; - } - } - - assert(OldSize == States.size() && - "fixed point shouldn't be adding any new nodes to state"); - } - -#ifndef NDEBUG - VerifyStates(); - LLVM_DEBUG(dbgs() << "States after meet iteration:\n"); - for (const auto &Pair : States) { - LLVM_DEBUG(dbgs() << " " << Pair.second << " for " << *Pair.first << "\n"); - } -#endif - // Even though we have identified a concrete base (or a conflict) for all live // pointers at this point, there are cases where the base is of an // incompatible type compared to the original instruction. We conservatively @@ -1023,7 +978,7 @@ static Value *findBasePointer(Value *I, DefiningValueMapTy &Cache, // the BDVs. // TODO: in many cases the instructions emited for the conflicting states // will be identical to the I itself (if the I's operate on their BDVs - // themselves). We should expoit this, but can't do it here since it would + // themselves). We should exploit this, but can't do it here since it would // break the invariant about the BDVs not being known to be a base. // TODO: the code also does not handle constants at all - the algorithm relies // on all constants having the same BDV and therefore constant-only insns @@ -1050,6 +1005,60 @@ static Value *findBasePointer(Value *I, DefiningValueMapTy &Cache, return false; }; + bool Progress = true; + while (Progress) { +#ifndef NDEBUG + const size_t OldSize = States.size(); +#endif + Progress = false; + // We're only changing values in this loop, thus safe to keep iterators. + // Since this is computing a fixed point, the order of visit does not + // effect the result. TODO: We could use a worklist here and make this run + // much faster. + for (auto Pair : States) { + Value *BDV = Pair.first; + // Only values that do not have known bases or those that have differing + // type (scalar versus vector) from a possible known base should be in the + // lattice. + assert((!isKnownBase(BDV, KnownBases) || + !areBothVectorOrScalar(BDV, Pair.second.getBaseValue())) && + "why did it get added?"); + + BDVState NewState(BDV); + visitBDVOperands(BDV, [&](Value *Op) { + Value *BDV = findBaseOrBDV(Op, Cache, KnownBases); + auto OpState = GetStateForBDV(BDV, Op); + NewState.meet(OpState); + }); + + // if the instruction has known base, but should in fact be marked as + // conflict because of incompatible in/out types, we mark it as such + // ensuring that it will propagate through the fixpoint iteration + auto I = cast(BDV); + auto BV = NewState.getBaseValue(); + if (BV && MarkConflict(I, BV)) + NewState = BDVState(I, BDVState::Conflict); + + BDVState OldState = Pair.second; + if (OldState != NewState) { + Progress = true; + States[BDV] = NewState; + } + } + + assert(OldSize == States.size() && + "fixed point shouldn't be adding any new nodes to state"); + } + +#ifndef NDEBUG + VerifyStates(); + LLVM_DEBUG(dbgs() << "States after meet iteration:\n"); + for (const auto &Pair : States) { + LLVM_DEBUG(dbgs() << " " << Pair.second << " for " << *Pair.first << "\n"); + } + + // since we do the conflict marking as part of the fixpoint iteration this + // loop only asserts that invariants are met for (auto Pair : States) { Instruction *I = cast(Pair.first); BDVState State = Pair.second; @@ -1061,18 +1070,7 @@ static Value *findBasePointer(Value *I, DefiningValueMapTy &Cache, (!isKnownBase(I, KnownBases) || !areBothVectorOrScalar(I, BaseValue)) && "why did it get added?"); assert(!State.isUnknown() && "Optimistic algorithm didn't complete!"); - - // since we only mark vec-scalar insns as conflicts in the pass, our work is - // done if the instruction already conflicts - if (State.isConflict()) - continue; - - if (MarkConflict(I, BaseValue)) - States[I] = BDVState(I, BDVState::Conflict); } - -#ifndef NDEBUG - VerifyStates(); #endif // Insert Phis for all conflicts diff --git a/llvm/lib/Transforms/Scalar/SROA.cpp b/llvm/lib/Transforms/Scalar/SROA.cpp index 75cddfa16d6..bdbaf4f55c9 100644 --- a/llvm/lib/Transforms/Scalar/SROA.cpp +++ b/llvm/lib/Transforms/Scalar/SROA.cpp @@ -319,6 +319,29 @@ static DebugVariable getAggregateVariable(DbgVariableIntrinsic *DVI) { return DebugVariable(DVI->getVariable(), std::nullopt, DVI->getDebugLoc().getInlinedAt()); } +static DebugVariable getAggregateVariable(DPValue *DPV) { + return DebugVariable(DPV->getVariable(), std::nullopt, + DPV->getDebugLoc().getInlinedAt()); +} + +static DPValue *createLinkedAssign(DPValue *, DIBuilder &DIB, + Instruction *LinkedInstr, Value *NewValue, + DILocalVariable *Variable, + DIExpression *Expression, Value *Address, + DIExpression *AddressExpression, + const DILocation *DI) { + (void)DIB; + return DPValue::createLinkedDPVAssign(LinkedInstr, NewValue, Variable, + Expression, Address, AddressExpression, + DI); +} +static DbgAssignIntrinsic *createLinkedAssign( + DbgAssignIntrinsic *, DIBuilder &DIB, Instruction *LinkedInstr, + Value *NewValue, DILocalVariable *Variable, DIExpression *Expression, + Value *Address, DIExpression *AddressExpression, const DILocation *DI) { + return DIB.insertDbgAssign(LinkedInstr, NewValue, Variable, Expression, + Address, AddressExpression, DI); +} /// Find linked dbg.assign and generate a new one with the correct /// FragmentInfo. Link Inst to the new dbg.assign. If Value is nullptr the @@ -340,8 +363,9 @@ static void migrateDebugInfo(AllocaInst *OldAlloca, bool IsSplit, Instruction *Inst, Value *Dest, Value *Value, const DataLayout &DL) { auto MarkerRange = at::getAssignmentMarkers(OldInst); + auto DPVAssignMarkerRange = at::getDPVAssignmentMarkers(OldInst); // Nothing to do if OldInst has no linked dbg.assign intrinsics. - if (MarkerRange.empty()) + if (MarkerRange.empty() && DPVAssignMarkerRange.empty()) return; LLVM_DEBUG(dbgs() << " migrateDebugInfo\n"); @@ -362,6 +386,9 @@ static void migrateDebugInfo(AllocaInst *OldAlloca, bool IsSplit, for (auto *DAI : at::getAssignmentMarkers(OldAlloca)) BaseFragments[getAggregateVariable(DAI)] = DAI->getExpression()->getFragmentInfo(); + for (auto *DPV : at::getDPVAssignmentMarkers(OldAlloca)) + BaseFragments[getAggregateVariable(DPV)] = + DPV->getExpression()->getFragmentInfo(); // The new inst needs a DIAssignID unique metadata tag (if OldInst has // one). It shouldn't already have one: assert this assumption. @@ -371,7 +398,7 @@ static void migrateDebugInfo(AllocaInst *OldAlloca, bool IsSplit, DIBuilder DIB(*OldInst->getModule(), /*AllowUnresolved*/ false); assert(OldAlloca->isStaticAlloca()); - for (DbgAssignIntrinsic *DbgAssign : MarkerRange) { + auto MigrateDbgAssign = [&](auto DbgAssign) { LLVM_DEBUG(dbgs() << " existing dbg.assign is: " << *DbgAssign << "\n"); auto *Expr = DbgAssign->getExpression(); @@ -382,7 +409,7 @@ static void migrateDebugInfo(AllocaInst *OldAlloca, bool IsSplit, { auto R = BaseFragments.find(getAggregateVariable(DbgAssign)); if (R == BaseFragments.end()) - continue; + return; BaseFragment = R->second; } std::optional CurrentFragment = @@ -393,7 +420,7 @@ static void migrateDebugInfo(AllocaInst *OldAlloca, bool IsSplit, BaseFragment, CurrentFragment, NewFragment); if (Result == Skip) - continue; + return; if (Result == UseFrag && !(NewFragment == CurrentFragment)) { if (CurrentFragment) { // Rewrite NewFragment to be relative to the existing one (this is @@ -425,9 +452,10 @@ static void migrateDebugInfo(AllocaInst *OldAlloca, bool IsSplit, } ::Value *NewValue = Value ? Value : DbgAssign->getValue(); - auto *NewAssign = DIB.insertDbgAssign( - Inst, NewValue, DbgAssign->getVariable(), Expr, Dest, - DIExpression::get(Ctx, std::nullopt), DbgAssign->getDebugLoc()); + auto *NewAssign = createLinkedAssign( + DbgAssign, DIB, Inst, NewValue, DbgAssign->getVariable(), Expr, Dest, + DIExpression::get(Expr->getContext(), std::nullopt), + DbgAssign->getDebugLoc()); // If we've updated the value but the original dbg.assign has an arglist // then kill it now - we can't use the requested new value. @@ -461,9 +489,11 @@ static void migrateDebugInfo(AllocaInst *OldAlloca, bool IsSplit, NewAssign->moveBefore(DbgAssign); NewAssign->setDebugLoc(DbgAssign->getDebugLoc()); - LLVM_DEBUG(dbgs() << "Created new assign intrinsic: " << *NewAssign - << "\n"); - } + LLVM_DEBUG(dbgs() << "Created new assign: " << *NewAssign << "\n"); + }; + + for_each(MarkerRange, MigrateDbgAssign); + for_each(DPVAssignMarkerRange, MigrateDbgAssign); } namespace { @@ -1903,8 +1933,8 @@ static Value *getAdjustedPtr(IRBuilderTy &IRB, const DataLayout &DL, Value *Ptr, APInt Offset, Type *PointerTy, const Twine &NamePrefix) { if (Offset != 0) - Ptr = IRB.CreateInBoundsGEP(IRB.getInt8Ty(), Ptr, IRB.getInt(Offset), - NamePrefix + "sroa_idx"); + Ptr = IRB.CreateInBoundsPtrAdd(Ptr, IRB.getInt(Offset), + NamePrefix + "sroa_idx"); return IRB.CreatePointerBitCastOrAddrSpaceCast(Ptr, PointerTy, NamePrefix + "sroa_cast"); } @@ -2108,8 +2138,9 @@ static bool isVectorPromotionViableForSlice(Partition &P, const Slice &S, /// Test whether a vector type is viable for promotion. /// -/// This implements the necessary checking for \c isVectorPromotionViable over -/// all slices of the alloca for the given VectorType. +/// This implements the necessary checking for \c checkVectorTypesForPromotion +/// (and thus isVectorPromotionViable) over all slices of the alloca for the +/// given VectorType. static bool checkVectorTypeForPromotion(Partition &P, VectorType *VTy, const DataLayout &DL) { uint64_t ElementSize = @@ -2134,88 +2165,16 @@ static bool checkVectorTypeForPromotion(Partition &P, VectorType *VTy, return true; } -/// Test whether the given alloca partitioning and range of slices can be -/// promoted to a vector. +/// Test whether any vector type in \p CandidateTys is viable for promotion. /// -/// This is a quick test to check whether we can rewrite a particular alloca -/// partition (and its newly formed alloca) into a vector alloca with only -/// whole-vector loads and stores such that it could be promoted to a vector -/// SSA value. We only can ensure this for a limited set of operations, and we -/// don't want to do the rewrites unless we are confident that the result will -/// be promotable, so we have an early test here. -static VectorType *isVectorPromotionViable(Partition &P, const DataLayout &DL) { - // Collect the candidate types for vector-based promotion. Also track whether - // we have different element types. - SmallVector CandidateTys; - SetVector LoadStoreTys; - Type *CommonEltTy = nullptr; - VectorType *CommonVecPtrTy = nullptr; - bool HaveVecPtrTy = false; - bool HaveCommonEltTy = true; - bool HaveCommonVecPtrTy = true; - auto CheckCandidateType = [&](Type *Ty) { - if (auto *VTy = dyn_cast(Ty)) { - // Return if bitcast to vectors is different for total size in bits. - if (!CandidateTys.empty()) { - VectorType *V = CandidateTys[0]; - if (DL.getTypeSizeInBits(VTy).getFixedValue() != - DL.getTypeSizeInBits(V).getFixedValue()) { - CandidateTys.clear(); - return; - } - } - CandidateTys.push_back(VTy); - Type *EltTy = VTy->getElementType(); - - if (!CommonEltTy) - CommonEltTy = EltTy; - else if (CommonEltTy != EltTy) - HaveCommonEltTy = false; - - if (EltTy->isPointerTy()) { - HaveVecPtrTy = true; - if (!CommonVecPtrTy) - CommonVecPtrTy = VTy; - else if (CommonVecPtrTy != VTy) - HaveCommonVecPtrTy = false; - } - } - }; - // Put load and store types into a set for de-duplication. - for (const Slice &S : P) { - Type *Ty; - if (auto *LI = dyn_cast(S.getUse()->getUser())) - Ty = LI->getType(); - else if (auto *SI = dyn_cast(S.getUse()->getUser())) - Ty = SI->getValueOperand()->getType(); - else - continue; - LoadStoreTys.insert(Ty); - // Consider any loads or stores that are the exact size of the slice. - if (S.beginOffset() == P.beginOffset() && S.endOffset() == P.endOffset()) - CheckCandidateType(Ty); - } - // Consider additional vector types where the element type size is a - // multiple of load/store element size. - for (Type *Ty : LoadStoreTys) { - if (!VectorType::isValidElementType(Ty)) - continue; - unsigned TypeSize = DL.getTypeSizeInBits(Ty).getFixedValue(); - // Make a copy of CandidateTys and iterate through it, because we might - // append to CandidateTys in the loop. - SmallVector CandidateTysCopy = CandidateTys; - for (VectorType *&VTy : CandidateTysCopy) { - unsigned VectorSize = DL.getTypeSizeInBits(VTy).getFixedValue(); - unsigned ElementSize = - DL.getTypeSizeInBits(VTy->getElementType()).getFixedValue(); - if (TypeSize != VectorSize && TypeSize != ElementSize && - VectorSize % TypeSize == 0) { - VectorType *NewVTy = VectorType::get(Ty, VectorSize / TypeSize, false); - CheckCandidateType(NewVTy); - } - } - } - +/// This implements the necessary checking for \c isVectorPromotionViable over +/// all slices of the alloca for the given VectorType. +static VectorType * +checkVectorTypesForPromotion(Partition &P, const DataLayout &DL, + SmallVectorImpl &CandidateTys, + bool HaveCommonEltTy, Type *CommonEltTy, + bool HaveVecPtrTy, bool HaveCommonVecPtrTy, + VectorType *CommonVecPtrTy) { // If we didn't find a vector type, nothing to do here. if (CandidateTys.empty()) return nullptr; @@ -2298,6 +2257,101 @@ static VectorType *isVectorPromotionViable(Partition &P, const DataLayout &DL) { return nullptr; } +/// Test whether the given alloca partitioning and range of slices can be +/// promoted to a vector. +/// +/// This is a quick test to check whether we can rewrite a particular alloca +/// partition (and its newly formed alloca) into a vector alloca with only +/// whole-vector loads and stores such that it could be promoted to a vector +/// SSA value. We only can ensure this for a limited set of operations, and we +/// don't want to do the rewrites unless we are confident that the result will +/// be promotable, so we have an early test here. +static VectorType *isVectorPromotionViable(Partition &P, const DataLayout &DL) { + // Collect the candidate types for vector-based promotion. Also track whether + // we have different element types. + SmallVector CandidateTys; + SetVector LoadStoreTys; + Type *CommonEltTy = nullptr; + VectorType *CommonVecPtrTy = nullptr; + bool HaveVecPtrTy = false; + bool HaveCommonEltTy = true; + bool HaveCommonVecPtrTy = true; + auto CheckCandidateType = [&](Type *Ty) { + if (auto *VTy = dyn_cast(Ty)) { + // Return if bitcast to vectors is different for total size in bits. + if (!CandidateTys.empty()) { + VectorType *V = CandidateTys[0]; + if (DL.getTypeSizeInBits(VTy).getFixedValue() != + DL.getTypeSizeInBits(V).getFixedValue()) { + CandidateTys.clear(); + return; + } + } + CandidateTys.push_back(VTy); + Type *EltTy = VTy->getElementType(); + + if (!CommonEltTy) + CommonEltTy = EltTy; + else if (CommonEltTy != EltTy) + HaveCommonEltTy = false; + + if (EltTy->isPointerTy()) { + HaveVecPtrTy = true; + if (!CommonVecPtrTy) + CommonVecPtrTy = VTy; + else if (CommonVecPtrTy != VTy) + HaveCommonVecPtrTy = false; + } + } + }; + + // Put load and store types into a set for de-duplication. + for (const Slice &S : P) { + Type *Ty; + if (auto *LI = dyn_cast(S.getUse()->getUser())) + Ty = LI->getType(); + else if (auto *SI = dyn_cast(S.getUse()->getUser())) + Ty = SI->getValueOperand()->getType(); + else + continue; + LoadStoreTys.insert(Ty); + // Consider any loads or stores that are the exact size of the slice. + if (S.beginOffset() == P.beginOffset() && S.endOffset() == P.endOffset()) + CheckCandidateType(Ty); + } + + if (auto *VTy = checkVectorTypesForPromotion( + P, DL, CandidateTys, HaveCommonEltTy, CommonEltTy, HaveVecPtrTy, + HaveCommonVecPtrTy, CommonVecPtrTy)) + return VTy; + + // Consider additional vector types where the element type size is a + // multiple of load/store element size. + for (Type *Ty : LoadStoreTys) { + if (!VectorType::isValidElementType(Ty)) + continue; + unsigned TypeSize = DL.getTypeSizeInBits(Ty).getFixedValue(); + // Make a copy of CandidateTys and iterate through it, because we might + // append to CandidateTys in the loop. + SmallVector CandidateTysCopy = CandidateTys; + CandidateTys.clear(); + for (VectorType *&VTy : CandidateTysCopy) { + unsigned VectorSize = DL.getTypeSizeInBits(VTy).getFixedValue(); + unsigned ElementSize = + DL.getTypeSizeInBits(VTy->getElementType()).getFixedValue(); + if (TypeSize != VectorSize && TypeSize != ElementSize && + VectorSize % TypeSize == 0) { + VectorType *NewVTy = VectorType::get(Ty, VectorSize / TypeSize, false); + CheckCandidateType(NewVTy); + } + } + } + + return checkVectorTypesForPromotion(P, DL, CandidateTys, HaveCommonEltTy, + CommonEltTy, HaveVecPtrTy, + HaveCommonVecPtrTy, CommonVecPtrTy); +} + /// Test whether a slice of an alloca is valid for integer widening. /// /// This implements the necessary checking for the \c isIntegerWideningViable @@ -3108,6 +3162,7 @@ private: // emit dbg.assign intrinsics for mem intrinsics storing through non- // constant geps, or storing a variable number of bytes. assert(at::getAssignmentMarkers(&II).empty() && + at::getDPVAssignmentMarkers(&II).empty() && "AT: Unexpected link to non-const GEP"); deleteIfTriviallyDead(OldPtr); return false; @@ -3254,11 +3309,13 @@ private: Value *AdjustedPtr = getNewAllocaSlicePtr(IRB, OldPtr->getType()); if (IsDest) { // Update the address component of linked dbg.assigns. - for (auto *DAI : at::getAssignmentMarkers(&II)) { - if (llvm::is_contained(DAI->location_ops(), II.getDest()) || - DAI->getAddress() == II.getDest()) - DAI->replaceVariableLocationOp(II.getDest(), AdjustedPtr); - } + auto UpdateAssignAddress = [&](auto *DbgAssign) { + if (llvm::is_contained(DbgAssign->location_ops(), II.getDest()) || + DbgAssign->getAddress() == II.getDest()) + DbgAssign->replaceVariableLocationOp(II.getDest(), AdjustedPtr); + }; + for_each(at::getAssignmentMarkers(&II), UpdateAssignAddress); + for_each(at::getDPVAssignmentMarkers(&II), UpdateAssignAddress); II.setDest(AdjustedPtr); II.setDestAlignment(SliceAlign); } else { @@ -3842,6 +3899,7 @@ private: DL); } else { assert(at::getAssignmentMarkers(Store).empty() && + at::getDPVAssignmentMarkers(Store).empty() && "AT: unexpected debug.assign linked to store through " "unbounded GEP"); } @@ -4861,10 +4919,22 @@ static void insertNewDbgInst(DIBuilder &DIB, DPValue *Orig, AllocaInst *NewAddr, DIExpression *NewFragmentExpr, Instruction *BeforeInst) { (void)DIB; - DPValue *New = new DPValue(ValueAsMetadata::get(NewAddr), Orig->getVariable(), - NewFragmentExpr, Orig->getDebugLoc(), - DPValue::LocationType::Declare); - BeforeInst->getParent()->insertDPValueBefore(New, BeforeInst->getIterator()); + if (Orig->isDbgDeclare()) { + DPValue *DPV = DPValue::createDPVDeclare( + NewAddr, Orig->getVariable(), NewFragmentExpr, Orig->getDebugLoc()); + BeforeInst->getParent()->insertDPValueBefore(DPV, + BeforeInst->getIterator()); + return; + } + if (!NewAddr->hasMetadata(LLVMContext::MD_DIAssignID)) { + NewAddr->setMetadata(LLVMContext::MD_DIAssignID, + DIAssignID::getDistinct(NewAddr->getContext())); + } + auto *NewAssign = DPValue::createLinkedDPVAssign( + NewAddr, Orig->getValue(), Orig->getVariable(), NewFragmentExpr, NewAddr, + Orig->getAddressExpression(), Orig->getDebugLoc()); + LLVM_DEBUG(dbgs() << "Created new DPVAssign: " << *NewAssign << "\n"); + (void)NewAssign; } /// Walks the slices of an alloca and form partitions based on them, @@ -5021,9 +5091,6 @@ bool SROA::splitAlloca(AllocaInst &AI, AllocaSlices &AS) { // Remove any existing intrinsics on the new alloca describing // the variable fragment. - SmallVector FragDbgDeclares; - SmallVector FragDPVs; - findDbgDeclares(FragDbgDeclares, Fragment.Alloca, &FragDPVs); auto RemoveOne = [DbgVariable](auto *OldDII) { auto SameVariableFragment = [](const auto *LHS, const auto *RHS) { return LHS->getVariable() == RHS->getVariable() && @@ -5033,8 +5100,8 @@ bool SROA::splitAlloca(AllocaInst &AI, AllocaSlices &AS) { if (SameVariableFragment(OldDII, DbgVariable)) OldDII->eraseFromParent(); }; - for_each(FragDbgDeclares, RemoveOne); - for_each(FragDPVs, RemoveOne); + for_each(findDbgDeclares(Fragment.Alloca), RemoveOne); + for_each(findDPVDeclares(Fragment.Alloca), RemoveOne); insertNewDbgInst(DIB, DbgVariable, Fragment.Alloca, FragmentExpr, &AI); } @@ -5042,12 +5109,10 @@ bool SROA::splitAlloca(AllocaInst &AI, AllocaSlices &AS) { // Migrate debug information from the old alloca to the new alloca(s) // and the individual partitions. - SmallVector DbgDeclares; - SmallVector DPValues; - findDbgDeclares(DbgDeclares, &AI, &DPValues); - for_each(DbgDeclares, MigrateOne); - for_each(DPValues, MigrateOne); + for_each(findDbgDeclares(&AI), MigrateOne); + for_each(findDPVDeclares(&AI), MigrateOne); for_each(at::getAssignmentMarkers(&AI), MigrateOne); + for_each(at::getDPVAssignmentMarkers(&AI), MigrateOne); return Changed; } @@ -5169,12 +5234,9 @@ bool SROA::deleteDeadInstructions( // not be able to find it. if (AllocaInst *AI = dyn_cast(I)) { DeletedAllocas.insert(AI); - SmallVector DbgDeclares; - SmallVector DPValues; - findDbgDeclares(DbgDeclares, AI, &DPValues); - for (DbgDeclareInst *OldDII : DbgDeclares) + for (DbgDeclareInst *OldDII : findDbgDeclares(AI)) OldDII->eraseFromParent(); - for (DPValue *OldDII : DPValues) + for (DPValue *OldDII : findDPVDeclares(AI)) OldDII->eraseFromParent(); } @@ -5271,8 +5333,9 @@ std::pair SROA::runSROA(Function &F) { "Should not have modified the CFG when told to preserve it."); if (Changed && isAssignmentTrackingEnabled(*F.getParent())) { - for (auto &BB : F) + for (auto &BB : F) { RemoveRedundantDbgInstrs(&BB); + } } return {Changed, CFGChanged}; diff --git a/llvm/lib/Transforms/Scalar/SeparateConstOffsetFromGEP.cpp b/llvm/lib/Transforms/Scalar/SeparateConstOffsetFromGEP.cpp index d2fed11445e..17c466f38c9 100644 --- a/llvm/lib/Transforms/Scalar/SeparateConstOffsetFromGEP.cpp +++ b/llvm/lib/Transforms/Scalar/SeparateConstOffsetFromGEP.cpp @@ -896,8 +896,7 @@ void SeparateConstOffsetFromGEP::lowerToSingleIndexGEPs( } } // Create an ugly GEP with a single index for each index. - ResultPtr = - Builder.CreateGEP(Builder.getInt8Ty(), ResultPtr, Idx, "uglygep"); + ResultPtr = Builder.CreatePtrAdd(ResultPtr, Idx, "uglygep"); if (FirstResult == nullptr) FirstResult = ResultPtr; } @@ -906,8 +905,7 @@ void SeparateConstOffsetFromGEP::lowerToSingleIndexGEPs( // Create a GEP with the constant offset index. if (AccumulativeByteOffset != 0) { Value *Offset = ConstantInt::get(PtrIndexTy, AccumulativeByteOffset); - ResultPtr = - Builder.CreateGEP(Builder.getInt8Ty(), ResultPtr, Offset, "uglygep"); + ResultPtr = Builder.CreatePtrAdd(ResultPtr, Offset, "uglygep"); } else isSwapCandidate = false; @@ -1107,9 +1105,8 @@ bool SeparateConstOffsetFromGEP::splitGEP(GetElementPtrInst *GEP) { Type *PtrIdxTy = DL->getIndexType(GEP->getType()); IRBuilder<> Builder(GEP); - NewGEP = cast(Builder.CreateGEP( - Builder.getInt8Ty(), NewGEP, - {ConstantInt::get(PtrIdxTy, AccumulativeByteOffset, true)}, + NewGEP = cast(Builder.CreatePtrAdd( + NewGEP, ConstantInt::get(PtrIdxTy, AccumulativeByteOffset, true), GEP->getName(), GEPWasInBounds)); NewGEP->copyMetadata(*GEP); diff --git a/llvm/lib/Transforms/Scalar/StraightLineStrengthReduce.cpp b/llvm/lib/Transforms/Scalar/StraightLineStrengthReduce.cpp index 2cce6eb2234..75910d7b698 100644 --- a/llvm/lib/Transforms/Scalar/StraightLineStrengthReduce.cpp +++ b/llvm/lib/Transforms/Scalar/StraightLineStrengthReduce.cpp @@ -656,8 +656,7 @@ void StraightLineStrengthReduce::rewriteCandidateWithBasis( case Candidate::GEP: { bool InBounds = cast(C.Ins)->isInBounds(); // C = (char *)Basis + Bump - Reduced = - Builder.CreateGEP(Builder.getInt8Ty(), Basis.Ins, Bump, "", InBounds); + Reduced = Builder.CreatePtrAdd(Basis.Ins, Bump, "", InBounds); break; } default: diff --git a/llvm/lib/Transforms/Utils/BasicBlockUtils.cpp b/llvm/lib/Transforms/Utils/BasicBlockUtils.cpp index 8b5a6d61841..ec0482ac2cd 100644 --- a/llvm/lib/Transforms/Utils/BasicBlockUtils.cpp +++ b/llvm/lib/Transforms/Utils/BasicBlockUtils.cpp @@ -405,10 +405,17 @@ static bool DPValuesRemoveRedundantDbgInstrsUsingBackwardScan(BasicBlock *BB) { // If the same variable fragment is described more than once it is enough // to keep the last one (i.e. the first found since we for reverse // iteration). - // FIXME: add assignment tracking support (see parallel implementation - // below). - if (!R.second) - ToBeRemoved.push_back(&DPV); + if (R.second) + continue; + + if (DPV.isDbgAssign()) { + // Don't delete dbg.assign intrinsics that are linked to instructions. + if (!at::getAssignmentInsts(&DPV).empty()) + continue; + // Unlinked dbg.assign intrinsics can be treated like dbg.values. + } + + ToBeRemoved.push_back(&DPV); continue; } // Sequence with consecutive dbg.value instrs ended. Clear the map to @@ -495,14 +502,25 @@ static bool DPValuesRemoveRedundantDbgInstrsUsingForwardScan(BasicBlock *BB) { DebugVariable Key(DPV.getVariable(), std::nullopt, DPV.getDebugLoc()->getInlinedAt()); auto VMI = VariableMap.find(Key); + // A dbg.assign with no linked instructions can be treated like a + // dbg.value (i.e. can be deleted). + bool IsDbgValueKind = + (!DPV.isDbgAssign() || at::getAssignmentInsts(&DPV).empty()); + // Update the map if we found a new value/expression describing the // variable, or if the variable wasn't mapped already. SmallVector Values(DPV.location_ops()); if (VMI == VariableMap.end() || VMI->second.first != Values || VMI->second.second != DPV.getExpression()) { - VariableMap[Key] = {Values, DPV.getExpression()}; + if (IsDbgValueKind) + VariableMap[Key] = {Values, DPV.getExpression()}; + else + VariableMap[Key] = {Values, nullptr}; continue; } + // Don't delete dbg.assign intrinsics that are linked to instructions. + if (!IsDbgValueKind) + continue; // Found an identical mapping. Remember the instruction for later removal. ToBeRemoved.push_back(&DPV); } @@ -514,6 +532,42 @@ static bool DPValuesRemoveRedundantDbgInstrsUsingForwardScan(BasicBlock *BB) { return !ToBeRemoved.empty(); } +static bool DPValuesRemoveUndefDbgAssignsFromEntryBlock(BasicBlock *BB) { + assert(BB->isEntryBlock() && "expected entry block"); + SmallVector ToBeRemoved; + DenseSet SeenDefForAggregate; + // Returns the DebugVariable for DVI with no fragment info. + auto GetAggregateVariable = [](const DPValue &DPV) { + return DebugVariable(DPV.getVariable(), std::nullopt, + DPV.getDebugLoc().getInlinedAt()); + }; + + // Remove undef dbg.assign intrinsics that are encountered before + // any non-undef intrinsics from the entry block. + for (auto &I : *BB) { + for (DPValue &DPV : I.getDbgValueRange()) { + if (!DPV.isDbgValue() && !DPV.isDbgAssign()) + continue; + bool IsDbgValueKind = + (DPV.isDbgValue() || at::getAssignmentInsts(&DPV).empty()); + DebugVariable Aggregate = GetAggregateVariable(DPV); + if (!SeenDefForAggregate.contains(Aggregate)) { + bool IsKill = DPV.isKillLocation() && IsDbgValueKind; + if (!IsKill) { + SeenDefForAggregate.insert(Aggregate); + } else if (DPV.isDbgAssign()) { + ToBeRemoved.push_back(&DPV); + } + } + } + } + + for (DPValue *DPV : ToBeRemoved) + DPV->eraseFromParent(); + + return !ToBeRemoved.empty(); +} + static bool removeRedundantDbgInstrsUsingForwardScan(BasicBlock *BB) { if (BB->IsNewDbgInfoFormat) return DPValuesRemoveRedundantDbgInstrsUsingForwardScan(BB); @@ -536,7 +590,7 @@ static bool removeRedundantDbgInstrsUsingForwardScan(BasicBlock *BB) { SmallVector Values(DVI->getValues()); if (VMI == VariableMap.end() || VMI->second.first != Values || VMI->second.second != DVI->getExpression()) { - // Use a sentinal value (nullptr) for the DIExpression when we see a + // Use a sentinel value (nullptr) for the DIExpression when we see a // linked dbg.assign so that the next debug intrinsic will never match // it (i.e. always treat linked dbg.assigns as if they're unique). if (IsDbgValueKind) @@ -578,7 +632,10 @@ static bool removeRedundantDbgInstrsUsingForwardScan(BasicBlock *BB) { /// then (only) the instruction marked with (*) can be removed. /// Possible improvements: /// - Keep track of non-overlapping fragments. -static bool remomveUndefDbgAssignsFromEntryBlock(BasicBlock *BB) { +static bool removeUndefDbgAssignsFromEntryBlock(BasicBlock *BB) { + if (BB->IsNewDbgInfoFormat) + return DPValuesRemoveUndefDbgAssignsFromEntryBlock(BB); + assert(BB->isEntryBlock() && "expected entry block"); SmallVector ToBeRemoved; DenseSet SeenDefForAggregate; @@ -629,7 +686,7 @@ bool llvm::RemoveRedundantDbgInstrs(BasicBlock *BB) { MadeChanges |= removeRedundantDbgInstrsUsingBackwardScan(BB); if (BB->isEntryBlock() && isAssignmentTrackingEnabled(*BB->getParent()->getParent())) - MadeChanges |= remomveUndefDbgAssignsFromEntryBlock(BB); + MadeChanges |= removeUndefDbgAssignsFromEntryBlock(BB); MadeChanges |= removeRedundantDbgInstrsUsingForwardScan(BB); if (MadeChanges) diff --git a/llvm/lib/Transforms/Utils/CodeExtractor.cpp b/llvm/lib/Transforms/Utils/CodeExtractor.cpp index f5abed0dd51..27811188345 100644 --- a/llvm/lib/Transforms/Utils/CodeExtractor.cpp +++ b/llvm/lib/Transforms/Utils/CodeExtractor.cpp @@ -1589,11 +1589,14 @@ static void fixupDebugInfoPostExtraction(Function &OldFunc, Function &NewFunc, for (auto &DPV : I.getDbgValueRange()) { // Apply the two updates that dbg.values get: invalid operands, and // variable metadata fixup. - // FIXME: support dbg.assign form of DPValues. if (any_of(DPV.location_ops(), IsInvalidLocation)) { DPVsToDelete.push_back(&DPV); continue; } + if (DPV.isDbgAssign() && IsInvalidLocation(DPV.getAddress())) { + DPVsToDelete.push_back(&DPV); + continue; + } if (!DPV.getDebugLoc().getInlinedAt()) DPV.setVariable(GetUpdatedDIVariable(DPV.getVariable())); DPV.setDebugLoc(DebugLoc::replaceInlinedAtSubprogram(DPV.getDebugLoc(), @@ -1735,13 +1738,9 @@ CodeExtractor::extractCodeRegion(const CodeExtractorAnalysisCache &CEAC, NumExitBlocks = ExitBlocks.size(); for (BasicBlock *Block : Blocks) { - Instruction *TI = Block->getTerminator(); - for (unsigned i = 0, e = TI->getNumSuccessors(); i != e; ++i) { - if (Blocks.count(TI->getSuccessor(i))) - continue; - BasicBlock *OldTarget = TI->getSuccessor(i); - OldTargets.push_back(OldTarget); - } + for (BasicBlock *OldTarget : successors(Block)) + if (!Blocks.contains(OldTarget)) + OldTargets.push_back(OldTarget); } // If we have to split PHI nodes of the entry or exit blocks, do so now. diff --git a/llvm/lib/Transforms/Utils/InjectTLIMappings.cpp b/llvm/lib/Transforms/Utils/InjectTLIMappings.cpp index ea313563066..9bfac2ac916 100644 --- a/llvm/lib/Transforms/Utils/InjectTLIMappings.cpp +++ b/llvm/lib/Transforms/Utils/InjectTLIMappings.cpp @@ -19,6 +19,7 @@ #include "llvm/Analysis/TargetLibraryInfo.h" #include "llvm/Analysis/VectorUtils.h" #include "llvm/IR/InstIterator.h" +#include "llvm/IR/VFABIDemangler.h" #include "llvm/Transforms/Utils/ModuleUtils.h" using namespace llvm; diff --git a/llvm/lib/Transforms/Utils/InlineFunction.cpp b/llvm/lib/Transforms/Utils/InlineFunction.cpp index 39d5f6e53c1..d4d4bf5ebdf 100644 --- a/llvm/lib/Transforms/Utils/InlineFunction.cpp +++ b/llvm/lib/Transforms/Utils/InlineFunction.cpp @@ -1789,13 +1789,15 @@ static at::StorageToVarsMap collectEscapedLocals(const DataLayout &DL, continue; // Find all local variables associated with the backing storage. - for (auto *DAI : at::getAssignmentMarkers(Base)) { + auto CollectAssignsForStorage = [&](auto *DbgAssign) { // Skip variables from inlined functions - they are not local variables. - if (DAI->getDebugLoc().getInlinedAt()) - continue; - LLVM_DEBUG(errs() << " > DEF : " << *DAI << "\n"); - EscapedLocals[Base].insert(at::VarRecord(DAI)); - } + if (DbgAssign->getDebugLoc().getInlinedAt()) + return; + LLVM_DEBUG(errs() << " > DEF : " << *DbgAssign << "\n"); + EscapedLocals[Base].insert(at::VarRecord(DbgAssign)); + }; + for_each(at::getAssignmentMarkers(Base), CollectAssignsForStorage); + for_each(at::getDPVAssignmentMarkers(Base), CollectAssignsForStorage); } return EscapedLocals; } @@ -1827,6 +1829,10 @@ static void fixupAssignments(Function::iterator Start, Function::iterator End) { // attachment or use, replace it with a new version. for (auto BBI = Start; BBI != End; ++BBI) { for (Instruction &I : *BBI) { + for (DPValue &DPV : I.getDbgValueRange()) { + if (DPV.isDbgAssign()) + DPV.setAssignId(GetNewID(DPV.getAssignID())); + } if (auto *ID = I.getMetadata(LLVMContext::MD_DIAssignID)) I.setMetadata(LLVMContext::MD_DIAssignID, GetNewID(ID)); else if (auto *DAI = dyn_cast(&I)) diff --git a/llvm/lib/Transforms/Utils/Local.cpp b/llvm/lib/Transforms/Utils/Local.cpp index b9cad764aae..459e3d98059 100644 --- a/llvm/lib/Transforms/Utils/Local.cpp +++ b/llvm/lib/Transforms/Utils/Local.cpp @@ -1724,20 +1724,6 @@ void llvm::ConvertDebugDeclareToDebugValue(DbgVariableIntrinsic *DII, SI->getIterator()); } -namespace llvm { -// RemoveDIs: duplicate the getDebugValueLoc method using DPValues instead of -// dbg.value intrinsics. In llvm namespace so that it overloads the -// DbgVariableIntrinsic version. -static DebugLoc getDebugValueLoc(DPValue *DPV) { - // Original dbg.declare must have a location. - const DebugLoc &DeclareLoc = DPV->getDebugLoc(); - MDNode *Scope = DeclareLoc.getScope(); - DILocation *InlinedAt = DeclareLoc.getInlinedAt(); - // Produce an unknown location with the correct scope / inlinedAt fields. - return DILocation::get(DPV->getContext(), 0, 0, Scope, InlinedAt); -} -} // namespace llvm - /// Inserts a llvm.dbg.value intrinsic before a load of an alloca'd value /// that has an associated llvm.dbg.declare intrinsic. void llvm::ConvertDebugDeclareToDebugValue(DbgVariableIntrinsic *DII, @@ -1767,7 +1753,7 @@ void llvm::ConvertDebugDeclareToDebugValue(DbgVariableIntrinsic *DII, void llvm::ConvertDebugDeclareToDebugValue(DPValue *DPV, StoreInst *SI, DIBuilder &Builder) { - assert(DPV->isAddressOfVariable()); + assert(DPV->isAddressOfVariable() || DPV->isDbgAssign()); auto *DIVar = DPV->getVariable(); assert(DIVar && "Missing variable"); auto *DIExpr = DPV->getExpression(); @@ -2130,9 +2116,8 @@ void llvm::insertDebugValuesForPHIs(BasicBlock *BB, bool llvm::replaceDbgDeclare(Value *Address, Value *NewAddress, DIBuilder &Builder, uint8_t DIExprFlags, int Offset) { - SmallVector DbgDeclares; - SmallVector DPValues; - findDbgDeclares(DbgDeclares, Address, &DPValues); + TinyPtrVector DbgDeclares = findDbgDeclares(Address); + TinyPtrVector DPVDeclares = findDPVDeclares(Address); auto ReplaceOne = [&](auto *DII) { assert(DII->getVariable() && "Missing variable"); @@ -2143,9 +2128,9 @@ bool llvm::replaceDbgDeclare(Value *Address, Value *NewAddress, }; for_each(DbgDeclares, ReplaceOne); - for_each(DPValues, ReplaceOne); + for_each(DPVDeclares, ReplaceOne); - return !DbgDeclares.empty() || !DPValues.empty(); + return !DbgDeclares.empty() || !DPVDeclares.empty(); } static void updateOneDbgValueForAlloca(const DebugLoc &Loc, @@ -2204,14 +2189,13 @@ void llvm::salvageDebugInfo(Instruction &I) { salvageDebugInfoForDbgValues(I, DbgUsers, DPUsers); } -/// Salvage the address component of \p DAI. -static void salvageDbgAssignAddress(DbgAssignIntrinsic *DAI) { - Instruction *I = dyn_cast(DAI->getAddress()); +template static void salvageDbgAssignAddress(T *Assign) { + Instruction *I = dyn_cast(Assign->getAddress()); // Only instructions can be salvaged at the moment. if (!I) return; - assert(!DAI->getAddressExpression()->getFragmentInfo().has_value() && + assert(!Assign->getAddressExpression()->getFragmentInfo().has_value() && "address-expression shouldn't have fragment info"); // The address component of a dbg.assign cannot be variadic. @@ -2225,16 +2209,16 @@ static void salvageDbgAssignAddress(DbgAssignIntrinsic *DAI) { return; DIExpression *SalvagedExpr = DIExpression::appendOpsToArg( - DAI->getAddressExpression(), Ops, 0, /*StackValue=*/false); + Assign->getAddressExpression(), Ops, 0, /*StackValue=*/false); assert(!SalvagedExpr->getFragmentInfo().has_value() && "address-expression shouldn't have fragment info"); // Salvage succeeds if no additional values are required. if (AdditionalValues.empty()) { - DAI->setAddress(NewV); - DAI->setAddressExpression(SalvagedExpr); + Assign->setAddress(NewV); + Assign->setAddressExpression(SalvagedExpr); } else { - DAI->setKillAddress(); + Assign->setKillAddress(); } } @@ -2308,10 +2292,19 @@ void llvm::salvageDebugInfoForDbgValues( } // Duplicate of above block for DPValues. for (auto *DPV : DPUsers) { + if (DPV->isDbgAssign()) { + if (DPV->getAddress() == &I) { + salvageDbgAssignAddress(DPV); + Salvaged = true; + } + if (DPV->getValue() != &I) + continue; + } + // Do not add DW_OP_stack_value for DbgDeclare and DbgAddr, because they // are implicitly pointing out the value as a DWARF memory location // description. - bool StackValue = DPV->getType() == DPValue::LocationType::Value; + bool StackValue = DPV->getType() != DPValue::LocationType::Declare; auto DPVLocation = DPV->location_ops(); assert( is_contained(DPVLocation, &I) && @@ -2345,7 +2338,7 @@ void llvm::salvageDebugInfoForDbgValues( SalvagedExpr->getNumElements() <= MaxExpressionSize; if (AdditionalValues.empty() && IsValidSalvageExpr) { DPV->setExpression(SalvagedExpr); - } else if (DPV->getType() == DPValue::LocationType::Value && + } else if (DPV->getType() != DPValue::LocationType::Declare && IsValidSalvageExpr && DPV->getNumVariableLocationOps() + AdditionalValues.size() <= MaxDebugArgs) { @@ -2355,8 +2348,7 @@ void llvm::salvageDebugInfoForDbgValues( // currently only valid for stack value expressions. // Also do not salvage if the resulting DIArgList would contain an // unreasonably large number of values. - Value *Undef = UndefValue::get(I.getOperand(0)->getType()); - DPV->replaceVariableLocationOp(I.getOperand(0), Undef); + DPV->setKillLocation(); } LLVM_DEBUG(dbgs() << "SALVAGE: " << DPV << '\n'); Salvaged = true; diff --git a/llvm/lib/Transforms/Utils/MemoryOpRemark.cpp b/llvm/lib/Transforms/Utils/MemoryOpRemark.cpp index 47c6bcbaf26..d671a9373bf 100644 --- a/llvm/lib/Transforms/Utils/MemoryOpRemark.cpp +++ b/llvm/lib/Transforms/Utils/MemoryOpRemark.cpp @@ -321,9 +321,6 @@ void MemoryOpRemark::visitVariable(const Value *V, bool FoundDI = false; // Try to get an llvm.dbg.declare, which has a DILocalVariable giving us the // real debug info name and size of the variable. - SmallVector DbgDeclares; - SmallVector DPValues; - findDbgDeclares(DbgDeclares, const_cast(V), &DPValues); auto FindDI = [&](const auto *DVI) { if (DILocalVariable *DILV = DVI->getVariable()) { std::optional DISize = getSizeInBytes(DILV->getSizeInBits()); @@ -334,8 +331,8 @@ void MemoryOpRemark::visitVariable(const Value *V, } } }; - for_each(DbgDeclares, FindDI); - for_each(DPValues, FindDI); + for_each(findDbgDeclares(const_cast(V)), FindDI); + for_each(findDPVDeclares(const_cast(V)), FindDI); if (FoundDI) { assert(!Result.empty()); diff --git a/llvm/lib/Transforms/Utils/ModuleUtils.cpp b/llvm/lib/Transforms/Utils/ModuleUtils.cpp index 7de0959ca57..209a6a34a3c 100644 --- a/llvm/lib/Transforms/Utils/ModuleUtils.cpp +++ b/llvm/lib/Transforms/Utils/ModuleUtils.cpp @@ -329,35 +329,6 @@ std::string llvm::getUniqueModuleId(Module *M) { return ("." + Str).str(); } -void VFABI::setVectorVariantNames(CallInst *CI, - ArrayRef VariantMappings) { - if (VariantMappings.empty()) - return; - - SmallString<256> Buffer; - llvm::raw_svector_ostream Out(Buffer); - for (const std::string &VariantMapping : VariantMappings) - Out << VariantMapping << ","; - // Get rid of the trailing ','. - assert(!Buffer.str().empty() && "Must have at least one char."); - Buffer.pop_back(); - - Module *M = CI->getModule(); -#ifndef NDEBUG - for (const std::string &VariantMapping : VariantMappings) { - LLVM_DEBUG(dbgs() << "VFABI: adding mapping '" << VariantMapping << "'\n"); - std::optional VI = - VFABI::tryDemangleForVFABI(VariantMapping, CI->getFunctionType()); - assert(VI && "Cannot add an invalid VFABI name."); - assert(M->getNamedValue(VI->VectorName) && - "Cannot add variant to attribute: " - "vector function declaration is missing."); - } -#endif - CI->addFnAttr( - Attribute::get(M->getContext(), MappingsAttrName, Buffer.str())); -} - void llvm::embedBufferInModule(Module &M, MemoryBufferRef Buf, StringRef SectionName, Align Alignment) { // Embed the memory buffer into the module. diff --git a/llvm/lib/Transforms/Utils/MoveAutoInit.cpp b/llvm/lib/Transforms/Utils/MoveAutoInit.cpp index a977ad87b79..9a5dba219ce 100644 --- a/llvm/lib/Transforms/Utils/MoveAutoInit.cpp +++ b/llvm/lib/Transforms/Utils/MoveAutoInit.cpp @@ -164,6 +164,9 @@ static bool runMoveAutoInit(Function &F, DominatorTree &DT, MemorySSA &MSSA) { if (TransitiveSuccessors.count(Pred)) continue; + if (!DT.isReachableFromEntry(Pred)) + continue; + DominatingPredecessor = DominatingPredecessor ? DT.findNearestCommonDominator(DominatingPredecessor, Pred) @@ -178,9 +181,10 @@ static bool runMoveAutoInit(Function &F, DominatorTree &DT, MemorySSA &MSSA) { // CatchSwitchInst blocks can only have one instruction, so they are not // good candidates for insertion. - while (isa(UsersDominator->getFirstInsertionPt())) { + while (isa(UsersDominator->getFirstNonPHI())) { for (BasicBlock *Pred : predecessors(UsersDominator)) - UsersDominator = DT.findNearestCommonDominator(UsersDominator, Pred); + if (DT.isReachableFromEntry(Pred)) + UsersDominator = DT.findNearestCommonDominator(UsersDominator, Pred); } // We finally found a place where I can be moved while not introducing extra diff --git a/llvm/lib/Transforms/Utils/NameAnonGlobals.cpp b/llvm/lib/Transforms/Utils/NameAnonGlobals.cpp index f41a14cdfbe..9655cb9cf6f 100644 --- a/llvm/lib/Transforms/Utils/NameAnonGlobals.cpp +++ b/llvm/lib/Transforms/Utils/NameAnonGlobals.cpp @@ -54,7 +54,7 @@ public: Hasher.final(Hash); SmallString<32> Result; MD5::stringifyResult(Hash, Result); - TheHash = std::string(Result.str()); + TheHash = std::string(Result); return TheHash; } }; diff --git a/llvm/lib/Transforms/Utils/PromoteMemoryToRegister.cpp b/llvm/lib/Transforms/Utils/PromoteMemoryToRegister.cpp index 717b6d301c8..88b05aab8db 100644 --- a/llvm/lib/Transforms/Utils/PromoteMemoryToRegister.cpp +++ b/llvm/lib/Transforms/Utils/PromoteMemoryToRegister.cpp @@ -101,12 +101,30 @@ bool llvm::isAllocaPromotable(const AllocaInst *AI) { namespace { +static DPValue *createDebugValue(DIBuilder &DIB, Value *NewValue, + DILocalVariable *Variable, + DIExpression *Expression, const DILocation *DI, + DPValue *InsertBefore) { + (void)DIB; + return DPValue::createDPValue(NewValue, Variable, Expression, DI, + *InsertBefore); +} +static DbgValueInst *createDebugValue(DIBuilder &DIB, Value *NewValue, + DILocalVariable *Variable, + DIExpression *Expression, + const DILocation *DI, + Instruction *InsertBefore) { + return static_cast(DIB.insertDbgValueIntrinsic( + NewValue, Variable, Expression, DI, InsertBefore)); +} + /// Helper for updating assignment tracking debug info when promoting allocas. class AssignmentTrackingInfo { /// DbgAssignIntrinsics linked to the alloca with at most one per variable /// fragment. (i.e. not be a comprehensive set if there are multiple /// dbg.assigns for one variable fragment). SmallVector DbgAssigns; + SmallVector DPVAssigns; public: void init(AllocaInst *AI) { @@ -115,16 +133,21 @@ public: if (Vars.insert(DebugVariable(DAI)).second) DbgAssigns.push_back(DAI); } + for (DPValue *DPV : at::getDPVAssignmentMarkers(AI)) { + if (Vars.insert(DebugVariable(DPV)).second) + DPVAssigns.push_back(DPV); + } } /// Update assignment tracking debug info given for the to-be-deleted store /// \p ToDelete that stores to this alloca. - void updateForDeletedStore( - StoreInst *ToDelete, DIBuilder &DIB, - SmallSet *DbgAssignsToDelete) const { + void + updateForDeletedStore(StoreInst *ToDelete, DIBuilder &DIB, + SmallSet *DbgAssignsToDelete, + SmallSet *DPVAssignsToDelete) const { // There's nothing to do if the alloca doesn't have any variables using // assignment tracking. - if (DbgAssigns.empty()) + if (DbgAssigns.empty() && DPVAssigns.empty()) return; // Insert a dbg.value where the linked dbg.assign is and remember to delete @@ -134,13 +157,17 @@ public: // dbg.assign for each variable fragment for the untracked store handling // (after this loop). SmallSet VarHasDbgAssignForStore; - for (DbgAssignIntrinsic *DAI : at::getAssignmentMarkers(ToDelete)) { - VarHasDbgAssignForStore.insert(DebugVariableAggregate(DAI)); - DbgAssignsToDelete->insert(DAI); - DIB.insertDbgValueIntrinsic(DAI->getValue(), DAI->getVariable(), - DAI->getExpression(), DAI->getDebugLoc(), - DAI); - } + auto InsertValueForAssign = [&](auto *DbgAssign, auto *&AssignList) { + VarHasDbgAssignForStore.insert(DebugVariableAggregate(DbgAssign)); + AssignList->insert(DbgAssign); + createDebugValue(DIB, DbgAssign->getValue(), DbgAssign->getVariable(), + DbgAssign->getExpression(), DbgAssign->getDebugLoc(), + DbgAssign); + }; + for (auto *Assign : at::getAssignmentMarkers(ToDelete)) + InsertValueForAssign(Assign, DbgAssignsToDelete); + for (auto *Assign : at::getDPVAssignmentMarkers(ToDelete)) + InsertValueForAssign(Assign, DPVAssignsToDelete); // It's possible for variables using assignment tracking to have no // dbg.assign linked to this store. These are variables in DbgAssigns that @@ -150,11 +177,13 @@ public: // cannot be represented using assignment tracking (non-const offset or // size) or one that is trackable but has had its DIAssignID attachment // dropped accidentally. - for (auto *DAI : DbgAssigns) { - if (VarHasDbgAssignForStore.contains(DebugVariableAggregate(DAI))) - continue; - ConvertDebugDeclareToDebugValue(DAI, ToDelete, DIB); - } + auto ConvertUnlinkedAssignToValue = [&](auto *Assign) { + if (VarHasDbgAssignForStore.contains(DebugVariableAggregate(Assign))) + return; + ConvertDebugDeclareToDebugValue(Assign, ToDelete, DIB); + }; + for_each(DbgAssigns, ConvertUnlinkedAssignToValue); + for_each(DPVAssigns, ConvertUnlinkedAssignToValue); } /// Update assignment tracking debug info given for the newly inserted PHI \p @@ -165,10 +194,15 @@ public: // debug-phi. for (auto *DAI : DbgAssigns) ConvertDebugDeclareToDebugValue(DAI, NewPhi, DIB); + for (auto *DPV : DPVAssigns) + ConvertDebugDeclareToDebugValue(DPV, NewPhi, DIB); } - void clear() { DbgAssigns.clear(); } - bool empty() { return DbgAssigns.empty(); } + void clear() { + DbgAssigns.clear(); + DPVAssigns.clear(); + } + bool empty() { return DbgAssigns.empty() && DPVAssigns.empty(); } }; struct AllocaInfo { @@ -229,11 +263,15 @@ struct AllocaInfo { } } DbgUserVec AllDbgUsers; - findDbgUsers(AllDbgUsers, AI, &DPUsers); + SmallVector AllDPUsers; + findDbgUsers(AllDbgUsers, AI, &AllDPUsers); std::copy_if(AllDbgUsers.begin(), AllDbgUsers.end(), std::back_inserter(DbgUsers), [](DbgVariableIntrinsic *DII) { return !isa(DII); }); + std::copy_if(AllDPUsers.begin(), AllDPUsers.end(), + std::back_inserter(DPUsers), + [](DPValue *DPV) { return !DPV->isDbgAssign(); }); AssignmentTracking.init(AI); } }; @@ -341,6 +379,7 @@ struct PromoteMem2Reg { /// A set of dbg.assigns to delete because they've been demoted to /// dbg.values. Call cleanUpDbgAssigns to delete them. SmallSet DbgAssignsToDelete; + SmallSet DPVAssignsToDelete; /// The set of basic blocks the renamer has already visited. SmallPtrSet Visited; @@ -390,6 +429,9 @@ private: for (auto *DAI : DbgAssignsToDelete) DAI->eraseFromParent(); DbgAssignsToDelete.clear(); + for (auto *DPV : DPVAssignsToDelete) + DPV->eraseFromParent(); + DPVAssignsToDelete.clear(); } }; @@ -462,10 +504,12 @@ static void removeIntrinsicUsers(AllocaInst *AI) { /// false there were some loads which were not dominated by the single store /// and thus must be phi-ed with undef. We fall back to the standard alloca /// promotion algorithm in that case. -static bool rewriteSingleStoreAlloca( - AllocaInst *AI, AllocaInfo &Info, LargeBlockInfo &LBI, const DataLayout &DL, - DominatorTree &DT, AssumptionCache *AC, - SmallSet *DbgAssignsToDelete) { +static bool +rewriteSingleStoreAlloca(AllocaInst *AI, AllocaInfo &Info, LargeBlockInfo &LBI, + const DataLayout &DL, DominatorTree &DT, + AssumptionCache *AC, + SmallSet *DbgAssignsToDelete, + SmallSet *DPVAssignsToDelete) { StoreInst *OnlyStore = Info.OnlyStore; bool StoringGlobalVal = !isa(OnlyStore->getOperand(0)); BasicBlock *StoreBB = OnlyStore->getParent(); @@ -525,8 +569,8 @@ static bool rewriteSingleStoreAlloca( DIBuilder DIB(*AI->getModule(), /*AllowUnresolved*/ false); // Update assignment tracking info for the store we're going to delete. - Info.AssignmentTracking.updateForDeletedStore(Info.OnlyStore, DIB, - DbgAssignsToDelete); + Info.AssignmentTracking.updateForDeletedStore( + Info.OnlyStore, DIB, DbgAssignsToDelete, DPVAssignsToDelete); // Record debuginfo for the store and remove the declaration's // debuginfo. @@ -570,10 +614,12 @@ static bool rewriteSingleStoreAlloca( /// use(t); /// *A = 42; /// } -static bool promoteSingleBlockAlloca( - AllocaInst *AI, const AllocaInfo &Info, LargeBlockInfo &LBI, - const DataLayout &DL, DominatorTree &DT, AssumptionCache *AC, - SmallSet *DbgAssignsToDelete) { +static bool +promoteSingleBlockAlloca(AllocaInst *AI, const AllocaInfo &Info, + LargeBlockInfo &LBI, const DataLayout &DL, + DominatorTree &DT, AssumptionCache *AC, + SmallSet *DbgAssignsToDelete, + SmallSet *DPVAssignsToDelete) { // The trickiest case to handle is when we have large blocks. Because of this, // this code is optimized assuming that large blocks happen. This does not // significantly pessimize the small block case. This uses LargeBlockInfo to @@ -637,8 +683,8 @@ static bool promoteSingleBlockAlloca( while (!AI->use_empty()) { StoreInst *SI = cast(AI->user_back()); // Update assignment tracking info for the store we're going to delete. - Info.AssignmentTracking.updateForDeletedStore(SI, DIB, DbgAssignsToDelete); - + Info.AssignmentTracking.updateForDeletedStore(SI, DIB, DbgAssignsToDelete, + DPVAssignsToDelete); // Record debuginfo for the store before removing it. auto DbgUpdateForStore = [&](auto &Container) { for (auto *DbgItem : Container) { @@ -710,7 +756,7 @@ void PromoteMem2Reg::run() { // it that are directly dominated by the definition with the value stored. if (Info.DefiningBlocks.size() == 1) { if (rewriteSingleStoreAlloca(AI, Info, LBI, SQ.DL, DT, AC, - &DbgAssignsToDelete)) { + &DbgAssignsToDelete, &DPVAssignsToDelete)) { // The alloca has been processed, move on. RemoveFromAllocasList(AllocaNum); ++NumSingleStore; @@ -722,7 +768,7 @@ void PromoteMem2Reg::run() { // linear sweep over the block to eliminate it. if (Info.OnlyUsedInOneBlock && promoteSingleBlockAlloca(AI, Info, LBI, SQ.DL, DT, AC, - &DbgAssignsToDelete)) { + &DbgAssignsToDelete, &DPVAssignsToDelete)) { // The alloca has been processed, move on. RemoveFromAllocasList(AllocaNum); continue; @@ -1128,8 +1174,8 @@ NextIteration: // Record debuginfo for the store before removing it. IncomingLocs[AllocaNo] = SI->getDebugLoc(); - AllocaATInfo[AllocaNo].updateForDeletedStore(SI, DIB, - &DbgAssignsToDelete); + AllocaATInfo[AllocaNo].updateForDeletedStore(SI, DIB, &DbgAssignsToDelete, + &DPVAssignsToDelete); auto ConvertDbgDeclares = [&](auto &Container) { for (auto *DbgItem : Container) if (DbgItem->isAddressOfVariable()) diff --git a/llvm/lib/Transforms/Utils/ScalarEvolutionExpander.cpp b/llvm/lib/Transforms/Utils/ScalarEvolutionExpander.cpp index cd3ac317cd2..a1d7f0f9ba0 100644 --- a/llvm/lib/Transforms/Utils/ScalarEvolutionExpander.cpp +++ b/llvm/lib/Transforms/Utils/ScalarEvolutionExpander.cpp @@ -169,12 +169,8 @@ Value *SCEVExpander::InsertNoopCastOfTo(Value *V, Type *Ty) { // during expansion. if (Op == Instruction::IntToPtr) { auto *PtrTy = cast(Ty); - if (DL.isNonIntegralPointerType(PtrTy)) { - assert(DL.getTypeAllocSize(Builder.getInt8Ty()) == 1 && - "alloc size of i8 must by 1 byte for the GEP to be correct"); - return Builder.CreateGEP( - Builder.getInt8Ty(), Constant::getNullValue(PtrTy), V, "scevgep"); - } + if (DL.isNonIntegralPointerType(PtrTy)) + return Builder.CreatePtrAdd(Constant::getNullValue(PtrTy), V, "scevgep"); } // Short-circuit unnecessary bitcasts. if (Op == Instruction::BitCast) { @@ -321,7 +317,7 @@ Value *SCEVExpander::expandAddToGEP(const SCEV *Offset, Value *V) { // Fold a GEP with constant operands. if (Constant *CLHS = dyn_cast(V)) if (Constant *CRHS = dyn_cast(Idx)) - return Builder.CreateGEP(Builder.getInt8Ty(), CLHS, CRHS); + return Builder.CreatePtrAdd(CLHS, CRHS); // Do a quick scan to see if we have this GEP nearby. If so, reuse it. unsigned ScanLimit = 6; @@ -358,7 +354,7 @@ Value *SCEVExpander::expandAddToGEP(const SCEV *Offset, Value *V) { } // Emit a GEP. - return Builder.CreateGEP(Builder.getInt8Ty(), V, Idx, "scevgep"); + return Builder.CreatePtrAdd(V, Idx, "scevgep"); } /// PickMostRelevantLoop - Given two loops pick the one that's most relevant for @@ -2123,9 +2119,9 @@ Value *SCEVExpander::generateOverflowCheck(const SCEVAddRecExpr *AR, if (isa(ARTy)) { Value *NegMulV = Builder.CreateNeg(MulV); if (NeedPosCheck) - Add = Builder.CreateGEP(Builder.getInt8Ty(), StartValue, MulV); + Add = Builder.CreatePtrAdd(StartValue, MulV); if (NeedNegCheck) - Sub = Builder.CreateGEP(Builder.getInt8Ty(), StartValue, NegMulV); + Sub = Builder.CreatePtrAdd(StartValue, NegMulV); } else { if (NeedPosCheck) Add = Builder.CreateAdd(StartValue, MulV); diff --git a/llvm/lib/Transforms/Utils/SimplifyCFG.cpp b/llvm/lib/Transforms/Utils/SimplifyCFG.cpp index 7515e539e7f..13eae549b2c 100644 --- a/llvm/lib/Transforms/Utils/SimplifyCFG.cpp +++ b/llvm/lib/Transforms/Utils/SimplifyCFG.cpp @@ -1770,6 +1770,11 @@ bool SimplifyCFGOpt::hoistSuccIdenticalTerminatorToSwitchOrIf( Locs.push_back(I1->getDebugLoc()); for (auto *OtherSuccTI : OtherSuccTIs) Locs.push_back(OtherSuccTI->getDebugLoc()); + // Also clone DPValues from the existing terminator, and all others (to + // duplicate existing hoisting behaviour). + NT->cloneDebugInfoFrom(I1); + for (Instruction *OtherSuccTI : OtherSuccTIs) + NT->cloneDebugInfoFrom(OtherSuccTI); NT->setDebugLoc(DILocation::getMergedLocations(Locs)); // PHIs created below will adopt NT's merged DebugLoc. @@ -3101,10 +3106,12 @@ bool SimplifyCFGOpt::SpeculativelyExecuteBB(BranchInst *BI, // %merge = select %cond, %two, %one // store %merge, %x.dest, !DIAssignID !2 // dbg.assign %merge, "x", ..., !2 - for (auto *DAI : at::getAssignmentMarkers(SpeculatedStore)) { - if (llvm::is_contained(DAI->location_ops(), OrigV)) - DAI->replaceVariableLocationOp(OrigV, S); - } + auto replaceVariable = [OrigV, S](auto *DbgAssign) { + if (llvm::is_contained(DbgAssign->location_ops(), OrigV)) + DbgAssign->replaceVariableLocationOp(OrigV, S); + }; + for_each(at::getAssignmentMarkers(SpeculatedStore), replaceVariable); + for_each(at::getDPVAssignmentMarkers(SpeculatedStore), replaceVariable); } // Metadata can be dependent on the condition we are hoisting above. @@ -3133,7 +3140,9 @@ bool SimplifyCFGOpt::SpeculativelyExecuteBB(BranchInst *BI, // instructions, in the same way that dbg.value intrinsics are dropped at the // end of this block. for (auto &It : make_range(ThenBB->begin(), ThenBB->end())) - It.dropDbgValues(); + for (DPValue &DPV : make_early_inc_range(It.getDbgValueRange())) + if (!DPV.isDbgAssign()) + It.dropOneDbgValue(&DPV); BB->splice(BI->getIterator(), ThenBB, ThenBB->begin(), std::prev(ThenBB->end())); @@ -5414,13 +5423,11 @@ static bool CasesAreContiguous(SmallVectorImpl &Cases) { } static void createUnreachableSwitchDefault(SwitchInst *Switch, - DomTreeUpdater *DTU, - bool RemoveOrigDefaultBlock = true) { + DomTreeUpdater *DTU) { LLVM_DEBUG(dbgs() << "SimplifyCFG: switch default is dead.\n"); auto *BB = Switch->getParent(); auto *OrigDefaultBlock = Switch->getDefaultDest(); - if (RemoveOrigDefaultBlock) - OrigDefaultBlock->removePredecessor(BB); + OrigDefaultBlock->removePredecessor(BB); BasicBlock *NewDefaultBlock = BasicBlock::Create( BB->getContext(), BB->getName() + ".unreachabledefault", BB->getParent(), OrigDefaultBlock); @@ -5429,8 +5436,7 @@ static void createUnreachableSwitchDefault(SwitchInst *Switch, if (DTU) { SmallVector Updates; Updates.push_back({DominatorTree::Insert, BB, &*NewDefaultBlock}); - if (RemoveOrigDefaultBlock && - !is_contained(successors(BB), OrigDefaultBlock)) + if (!is_contained(successors(BB), OrigDefaultBlock)) Updates.push_back({DominatorTree::Delete, BB, &*OrigDefaultBlock}); DTU->applyUpdates(Updates); } @@ -5612,28 +5618,10 @@ static bool eliminateDeadSwitchCases(SwitchInst *SI, DomTreeUpdater *DTU, Known.getBitWidth() - (Known.Zero | Known.One).popcount(); assert(NumUnknownBits <= Known.getBitWidth()); if (HasDefault && DeadCases.empty() && - NumUnknownBits < 64 /* avoid overflow */) { - uint64_t AllNumCases = 1ULL << NumUnknownBits; - if (SI->getNumCases() == AllNumCases) { - createUnreachableSwitchDefault(SI, DTU); - return true; - } - // When only one case value is missing, replace default with that case. - // Eliminating the default branch will provide more opportunities for - // optimization, such as lookup tables. - if (SI->getNumCases() == AllNumCases - 1) { - assert(NumUnknownBits > 1 && "Should be canonicalized to a branch"); - uint64_t MissingCaseVal = 0; - for (const auto &Case : SI->cases()) - MissingCaseVal ^= Case.getCaseValue()->getValue().getLimitedValue(); - auto *MissingCase = - cast(ConstantInt::get(Cond->getType(), MissingCaseVal)); - SwitchInstProfUpdateWrapper SIW(*SI); - SIW.addCase(MissingCase, SI->getDefaultDest(), SIW.getSuccessorWeight(0)); - createUnreachableSwitchDefault(SI, DTU, /*RemoveOrigDefaultBlock*/ false); - SIW.setSuccessorWeight(0, 0); - return true; - } + NumUnknownBits < 64 /* avoid overflow */ && + SI->getNumCases() == (1ULL << NumUnknownBits)) { + createUnreachableSwitchDefault(SI, DTU); + return true; } if (DeadCases.empty()) diff --git a/llvm/lib/Transforms/Utils/SimplifyIndVar.cpp b/llvm/lib/Transforms/Utils/SimplifyIndVar.cpp index 42e7c4006b4..0ed3324a27b 100644 --- a/llvm/lib/Transforms/Utils/SimplifyIndVar.cpp +++ b/llvm/lib/Transforms/Utils/SimplifyIndVar.cpp @@ -1753,7 +1753,7 @@ Instruction *WidenIV::widenIVUse(WidenIV::NarrowIVDefUse DU, SCEVExpander &Rewri } // This narrow use can be widened by a sext if it's non-negative or its narrow - // def was widended by a sext. Same for zext. + // def was widened by a sext. Same for zext. auto canWidenBySExt = [&]() { return DU.NeverNegative || getExtendKind(DU.NarrowDef) == ExtendKind::Sign; }; diff --git a/llvm/lib/Transforms/Utils/SimplifyLibCalls.cpp b/llvm/lib/Transforms/Utils/SimplifyLibCalls.cpp index a7cd68e860e..52eef9ab58a 100644 --- a/llvm/lib/Transforms/Utils/SimplifyLibCalls.cpp +++ b/llvm/lib/Transforms/Utils/SimplifyLibCalls.cpp @@ -2495,13 +2495,17 @@ Value *LibCallSimplifier::optimizeLog(CallInst *Log, IRBuilderBase &B) { // log(pow(x,y)) -> y*log(x) AttributeList NoAttrs; - if (ArgLb == PowLb || ArgID == Intrinsic::pow) { + if (ArgLb == PowLb || ArgID == Intrinsic::pow || ArgID == Intrinsic::powi) { Value *LogX = Log->doesNotAccessMemory() ? B.CreateCall(Intrinsic::getDeclaration(Mod, LogID, Ty), Arg->getOperand(0), "log") : emitUnaryFloatFnCall(Arg->getOperand(0), TLI, LogNm, B, NoAttrs); - Value *MulY = B.CreateFMul(Arg->getArgOperand(1), LogX, "mul"); + Value *Y = Arg->getArgOperand(1); + // Cast exponent to FP if integer. + if (ArgID == Intrinsic::powi) + Y = B.CreateSIToFP(Y, Ty, "cast"); + Value *MulY = B.CreateFMul(Y, LogX, "mul"); // Since pow() may have side effects, e.g. errno, // dead code elimination may not be trusted to remove it. substituteInParent(Arg, MulY); diff --git a/llvm/lib/Transforms/Utils/ValueMapper.cpp b/llvm/lib/Transforms/Utils/ValueMapper.cpp index 71d0f09e477..380541ffdd4 100644 --- a/llvm/lib/Transforms/Utils/ValueMapper.cpp +++ b/llvm/lib/Transforms/Utils/ValueMapper.cpp @@ -544,6 +544,16 @@ void Mapper::remapDPValue(DPValue &V) { V.setVariable(cast(MappedVar)); V.setDebugLoc(DebugLoc(cast(MappedDILoc))); + bool IgnoreMissingLocals = Flags & RF_IgnoreMissingLocals; + + if (V.isDbgAssign()) { + auto *NewAddr = mapValue(V.getAddress()); + if (!IgnoreMissingLocals && !NewAddr) + V.setKillAddress(); + else if (NewAddr) + V.setAddress(NewAddr); + } + // Find Value operands and remap those. SmallVector Vals, NewVals; for (Value *Val : V.location_ops()) @@ -555,8 +565,6 @@ void Mapper::remapDPValue(DPValue &V) { if (Vals == NewVals) return; - bool IgnoreMissingLocals = Flags & RF_IgnoreMissingLocals; - // Otherwise, do some replacement. if (!IgnoreMissingLocals && llvm::any_of(NewVals, [&](Value *V) { return V == nullptr; })) { diff --git a/llvm/lib/Transforms/Vectorize/LoopVectorizationPlanner.h b/llvm/lib/Transforms/Vectorize/LoopVectorizationPlanner.h index cff72ae263d..a7ebf78e54c 100644 --- a/llvm/lib/Transforms/Vectorize/LoopVectorizationPlanner.h +++ b/llvm/lib/Transforms/Vectorize/LoopVectorizationPlanner.h @@ -148,26 +148,27 @@ public: VPInstruction *createOverflowingOp(unsigned Opcode, std::initializer_list Operands, VPRecipeWithIRFlags::WrapFlagsTy WrapFlags, - DebugLoc DL, const Twine &Name = "") { + DebugLoc DL = {}, const Twine &Name = "") { return tryInsertInstruction( new VPInstruction(Opcode, Operands, WrapFlags, DL, Name)); } - VPValue *createNot(VPValue *Operand, DebugLoc DL, const Twine &Name = "") { + VPValue *createNot(VPValue *Operand, DebugLoc DL = {}, + const Twine &Name = "") { return createInstruction(VPInstruction::Not, {Operand}, DL, Name); } - VPValue *createAnd(VPValue *LHS, VPValue *RHS, DebugLoc DL, + VPValue *createAnd(VPValue *LHS, VPValue *RHS, DebugLoc DL = {}, const Twine &Name = "") { return createInstruction(Instruction::BinaryOps::And, {LHS, RHS}, DL, Name); } - VPValue *createOr(VPValue *LHS, VPValue *RHS, DebugLoc DL, + VPValue *createOr(VPValue *LHS, VPValue *RHS, DebugLoc DL = {}, const Twine &Name = "") { return createInstruction(Instruction::BinaryOps::Or, {LHS, RHS}, DL, Name); } VPValue *createSelect(VPValue *Cond, VPValue *TrueVal, VPValue *FalseVal, - DebugLoc DL, const Twine &Name = "", + DebugLoc DL = {}, const Twine &Name = "", std::optional FMFs = std::nullopt) { auto *Select = FMFs ? new VPInstruction(Instruction::Select, {Cond, TrueVal, FalseVal}, diff --git a/llvm/lib/Transforms/Vectorize/LoopVectorize.cpp b/llvm/lib/Transforms/Vectorize/LoopVectorize.cpp index 9743fa0e740..6ca93e15719 100644 --- a/llvm/lib/Transforms/Vectorize/LoopVectorize.cpp +++ b/llvm/lib/Transforms/Vectorize/LoopVectorize.cpp @@ -2346,9 +2346,8 @@ emitTransformedIndex(IRBuilderBase &B, Value *Index, Value *StartValue, auto *Offset = CreateMul(Index, Step); return CreateAdd(StartValue, Offset); } - case InductionDescriptor::IK_PtrInduction: { - return B.CreateGEP(B.getInt8Ty(), StartValue, CreateMul(Index, Step)); - } + case InductionDescriptor::IK_PtrInduction: + return B.CreatePtrAdd(StartValue, CreateMul(Index, Step)); case InductionDescriptor::IK_FpInduction: { assert(!isa(Index->getType()) && "Vector indices not supported for FP inductions yet"); @@ -6950,10 +6949,25 @@ LoopVectorizationCostModel::getInstructionCost(Instruction *I, ElementCount VF, Op2Info.Kind = TargetTransformInfo::OK_UniformValue; SmallVector Operands(I->operand_values()); - return TTI.getArithmeticInstrCost( + auto InstrCost = TTI.getArithmeticInstrCost( I->getOpcode(), VectorTy, CostKind, {TargetTransformInfo::OK_AnyValue, TargetTransformInfo::OP_None}, Op2Info, Operands, I); + + // Some targets can replace frem with vector library calls. + InstructionCost VecCallCost = InstructionCost::getInvalid(); + if (I->getOpcode() == Instruction::FRem) { + LibFunc Func; + if (TLI->getLibFunc(I->getOpcode(), I->getType(), Func) && + TLI->isFunctionVectorizable(TLI->getName(Func), VF)) { + SmallVector OpTypes; + for (auto &Op : I->operands()) + OpTypes.push_back(Op->getType()); + VecCallCost = + TTI.getCallInstrCost(nullptr, VectorTy, OpTypes, CostKind); + } + } + return std::min(InstrCost, VecCallCost); } case Instruction::FNeg: { return TTI.getArithmeticInstrCost( @@ -8247,7 +8261,8 @@ VPWidenCallRecipe *VPRecipeBuilder::tryToWidenCall(CallInst *CI, }, Range); if (ShouldUseVectorIntrinsic) - return new VPWidenCallRecipe(*CI, make_range(Ops.begin(), Ops.end()), ID); + return new VPWidenCallRecipe(*CI, make_range(Ops.begin(), Ops.end()), ID, + CI->getDebugLoc()); Function *Variant = nullptr; std::optional MaskPos; @@ -8300,7 +8315,8 @@ VPWidenCallRecipe *VPRecipeBuilder::tryToWidenCall(CallInst *CI, } return new VPWidenCallRecipe(*CI, make_range(Ops.begin(), Ops.end()), - Intrinsic::not_intrinsic, Variant); + Intrinsic::not_intrinsic, CI->getDebugLoc(), + Variant); } return nullptr; @@ -8949,16 +8965,17 @@ void LoopVectorizationPlanner::adjustRecipesForReductions( "AnyOf reductions are not allowed for in-loop reductions"); // Collect the chain of "link" recipes for the reduction starting at PhiR. - SetVector Worklist; + SetVector Worklist; Worklist.insert(PhiR); for (unsigned I = 0; I != Worklist.size(); ++I) { - VPRecipeBase *Cur = Worklist[I]; - for (VPUser *U : Cur->getVPSingleValue()->users()) { - auto *UserRecipe = dyn_cast(U); - if (!UserRecipe) + VPSingleDefRecipe *Cur = Worklist[I]; + for (VPUser *U : Cur->users()) { + auto *UserRecipe = dyn_cast(U); + if (!UserRecipe) { + assert(isa(U) && + "U must either be a VPSingleDef or VPLiveOut"); continue; - assert(UserRecipe->getNumDefinedValues() == 1 && - "recipes must define exactly one result value"); + } Worklist.insert(UserRecipe); } } @@ -8968,10 +8985,8 @@ void LoopVectorizationPlanner::adjustRecipesForReductions( // (PreviousLink) to tell which of the two operands of a Link will remain // scalar and which will be reduced. For minmax by select(cmp), Link will be // the select instructions. - VPRecipeBase *PreviousLink = PhiR; // Aka Worklist[0]. - for (VPRecipeBase *CurrentLink : Worklist.getArrayRef().drop_front()) { - VPValue *PreviousLinkV = PreviousLink->getVPSingleValue(); - + VPSingleDefRecipe *PreviousLink = PhiR; // Aka Worklist[0]. + for (VPSingleDefRecipe *CurrentLink : Worklist.getArrayRef().drop_front()) { Instruction *CurrentLinkI = CurrentLink->getUnderlyingInstr(); // Index of the first operand which holds a non-mask vector operand. @@ -8986,7 +9001,7 @@ void LoopVectorizationPlanner::adjustRecipesForReductions( "Expected instruction to be a call to the llvm.fmuladd intrinsic"); assert(((MinVF.isScalar() && isa(CurrentLink)) || isa(CurrentLink)) && - CurrentLink->getOperand(2) == PreviousLinkV && + CurrentLink->getOperand(2) == PreviousLink && "expected a call where the previous link is the added operand"); // If the instruction is a call to the llvm.fmuladd intrinsic then we @@ -9017,15 +9032,15 @@ void LoopVectorizationPlanner::adjustRecipesForReductions( // Note that for non-commutable operands (cmp-selects), the semantics of // the cmp-select are captured in the recurrence kind. unsigned VecOpId = - CurrentLink->getOperand(IndexOfFirstOperand) == PreviousLinkV + CurrentLink->getOperand(IndexOfFirstOperand) == PreviousLink ? IndexOfFirstOperand + 1 : IndexOfFirstOperand; VecOp = CurrentLink->getOperand(VecOpId); - assert(VecOp != PreviousLinkV && + assert(VecOp != PreviousLink && CurrentLink->getOperand(CurrentLink->getNumOperands() - 1 - (VecOpId - IndexOfFirstOperand)) == - PreviousLinkV && - "PreviousLinkV must be the operand other than VecOp"); + PreviousLink && + "PreviousLink must be the operand other than VecOp"); } BasicBlock *BB = CurrentLinkI->getParent(); @@ -9037,19 +9052,19 @@ void LoopVectorizationPlanner::adjustRecipesForReductions( } VPReductionRecipe *RedRecipe = new VPReductionRecipe( - RdxDesc, CurrentLinkI, PreviousLinkV, VecOp, CondOp); + RdxDesc, CurrentLinkI, PreviousLink, VecOp, CondOp); // Append the recipe to the end of the VPBasicBlock because we need to // ensure that it comes after all of it's inputs, including CondOp. // Note that this transformation may leave over dead recipes (including // CurrentLink), which will be cleaned by a later VPlan transform. LinkVPBB->appendRecipe(RedRecipe); - CurrentLink->getVPSingleValue()->replaceAllUsesWith(RedRecipe); + CurrentLink->replaceAllUsesWith(RedRecipe); PreviousLink = RedRecipe; } } - Builder.setInsertPoint(&*LatchVPBB->begin()); - for (VPRecipeBase &R : - Plan->getVectorLoopRegion()->getEntryBasicBlock()->phis()) { + Builder.setInsertPoint(&*LatchVPBB->begin()); + for (VPRecipeBase &R : + Plan->getVectorLoopRegion()->getEntryBasicBlock()->phis()) { VPReductionPHIRecipe *PhiR = dyn_cast(&R); if (!PhiR) continue; diff --git a/llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp b/llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp index 055fbb00871..601d2454c1e 100644 --- a/llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp +++ b/llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp @@ -7379,6 +7379,8 @@ class BoUpSLP::ShuffleCostEstimator : public BaseShuffleAnalysis { continue; if (Idx >= static_cast(CommonVF)) Idx = E1Mask[Idx - CommonVF] + VF; + else + Idx = E1Mask[Idx]; } CommonVF = VF; } @@ -12986,8 +12988,8 @@ void BoUpSLP::scheduleBlock(BlockScheduling *BS) { for (ScheduleData *BundleMember = Picked; BundleMember; BundleMember = BundleMember->NextInBundle) { Instruction *PickedInst = BundleMember->Inst; - if (PickedInst->getNextNode() != LastScheduledInst) - PickedInst->moveBefore(LastScheduledInst); + if (PickedInst->getNextNonDebugInstruction() != LastScheduledInst) + PickedInst->moveAfter(LastScheduledInst->getPrevNode()); LastScheduledInst = PickedInst; } @@ -13181,7 +13183,7 @@ void BoUpSLP::computeMinimumValueSizes() { // We only attempt to truncate integer expressions. auto &TreeRoot = VectorizableTree[0]->Scalars; auto *TreeRootIT = dyn_cast(TreeRoot[0]->getType()); - if (!TreeRootIT) + if (!TreeRootIT || VectorizableTree.front()->State == TreeEntry::NeedToGather) return; // Ensure the roots of the vectorizable tree don't form a cycle. @@ -14792,8 +14794,17 @@ public: LocalExternallyUsedValues[RdxVal]; // Update LocalExternallyUsedValues for the scalar, replaced by // extractelement instructions. + DenseMap ReplacementToExternal; + for (const std::pair &Pair : ReplacedExternals) + ReplacementToExternal.try_emplace(Pair.second, Pair.first); for (const std::pair &Pair : ReplacedExternals) { - auto *It = ExternallyUsedValues.find(Pair.first); + Value *Ext = Pair.first; + auto RIt = ReplacementToExternal.find(Ext); + while (RIt != ReplacementToExternal.end()) { + Ext = RIt->second; + RIt = ReplacementToExternal.find(Ext); + } + auto *It = ExternallyUsedValues.find(Ext); if (It == ExternallyUsedValues.end()) continue; LocalExternallyUsedValues[Pair.second].append(It->second); @@ -15214,6 +15225,19 @@ private: assert(IsSupportedHorRdxIdentityOp && "The optimization of matched scalar identity horizontal reductions " "must be supported."); + auto *VTy = cast(VectorizedValue->getType()); + if (VTy->getElementType() != VL.front()->getType()) { + VectorizedValue = Builder.CreateIntCast( + VectorizedValue, + FixedVectorType::get(VL.front()->getType(), VTy->getNumElements()), + any_of(VL, [&](Value *R) { + KnownBits Known = computeKnownBits( + R, cast(ReductionOps.front().front()) + ->getModule() + ->getDataLayout()); + return !Known.isNonNegative(); + })); + } switch (RdxKind) { case RecurKind::Add: { // root = mul prev_root, <1, 1, n, 1> @@ -16217,10 +16241,13 @@ bool SLPVectorizerPass::vectorizeGEPIndices(BasicBlock *BB, BoUpSLP &R) { SetVector Candidates(GEPList.begin(), GEPList.end()); // Some of the candidates may have already been vectorized after we - // initially collected them. If so, they are marked as deleted, so remove - // them from the set of candidates. - Candidates.remove_if( - [&R](Value *I) { return R.isDeleted(cast(I)); }); + // initially collected them or their index is optimized to constant value. + // If so, they are marked as deleted, so remove them from the set of + // candidates. + Candidates.remove_if([&R](Value *I) { + return R.isDeleted(cast(I)) || + isa(cast(I)->idx_begin()->get()); + }); // Remove from the set of candidates all pairs of getelementptrs with // constant differences. Such getelementptrs are likely not good diff --git a/llvm/lib/Transforms/Vectorize/VPlan.cpp b/llvm/lib/Transforms/Vectorize/VPlan.cpp index b6e56c47c22..3eeb1a6948f 100644 --- a/llvm/lib/Transforms/Vectorize/VPlan.cpp +++ b/llvm/lib/Transforms/Vectorize/VPlan.cpp @@ -1136,29 +1136,18 @@ void VPlanIngredient::print(raw_ostream &O) const { template void DomTreeBuilder::Calculate(VPDominatorTree &DT); void VPValue::replaceAllUsesWith(VPValue *New) { - if (this == New) - return; - for (unsigned J = 0; J < getNumUsers();) { - VPUser *User = Users[J]; - bool RemovedUser = false; - for (unsigned I = 0, E = User->getNumOperands(); I < E; ++I) - if (User->getOperand(I) == this) { - User->setOperand(I, New); - RemovedUser = true; - } - // If a user got removed after updating the current user, the next user to - // update will be moved to the current position, so we only need to - // increment the index if the number of users did not change. - if (!RemovedUser) - J++; - } + replaceUsesWithIf(New, [](VPUser &, unsigned) { return true; }); } void VPValue::replaceUsesWithIf( VPValue *New, llvm::function_ref ShouldReplace) { + // Note that this early exit is required for correctness; the implementation + // below relies on the number of users for this VPValue to decrease, which + // isn't the case if this == New. if (this == New) return; + for (unsigned J = 0; J < getNumUsers();) { VPUser *User = Users[J]; bool RemovedUser = false; diff --git a/llvm/lib/Transforms/Vectorize/VPlan.h b/llvm/lib/Transforms/Vectorize/VPlan.h index 4b4f4911eb6..0c6214868d8 100644 --- a/llvm/lib/Transforms/Vectorize/VPlan.h +++ b/llvm/lib/Transforms/Vectorize/VPlan.h @@ -12,10 +12,12 @@ /// VPBlockBase, together implementing a Hierarchical CFG; /// 2. Pure virtual VPRecipeBase serving as the base class for recipes contained /// within VPBasicBlocks; -/// 3. VPInstruction, a concrete Recipe and VPUser modeling a single planned +/// 3. Pure virtual VPSingleDefRecipe serving as a base class for recipes that +/// also inherit from VPValue. +/// 4. VPInstruction, a concrete Recipe and VPUser modeling a single planned /// instruction; -/// 4. The VPlan class holding a candidate for vectorization; -/// 5. The VPlanPrinter class providing a way to print a plan in dot format; +/// 5. The VPlan class holding a candidate for vectorization; +/// 6. The VPlanPrinter class providing a way to print a plan in dot format; /// These are documented in docs/VectorizationPlan.rst. // //===----------------------------------------------------------------------===// @@ -700,8 +702,8 @@ public: /// VPRecipeBase is a base class modeling a sequence of one or more output IR /// instructions. VPRecipeBase owns the VPValues it defines through VPDef /// and is responsible for deleting its defined values. Single-value -/// VPRecipeBases that also inherit from VPValue must make sure to inherit from -/// VPRecipeBase before VPValue. +/// recipes must inherit from VPSingleDef instead of inheriting from both +/// VPRecipeBase and VPValue separately. class VPRecipeBase : public ilist_node_with_parent, public VPDef, public VPUser { @@ -762,15 +764,6 @@ public: /// \returns an iterator pointing to the element after the erased one iplist::iterator eraseFromParent(); - /// Returns the underlying instruction, if the recipe is a VPValue or nullptr - /// otherwise. - Instruction *getUnderlyingInstr() { - return cast(getVPSingleValue()->getUnderlyingValue()); - } - const Instruction *getUnderlyingInstr() const { - return cast(getVPSingleValue()->getUnderlyingValue()); - } - /// Method to support type inquiry through isa, cast, and dyn_cast. static inline bool classof(const VPDef *D) { // All VPDefs are also VPRecipeBases. @@ -819,10 +812,80 @@ public: } \ static inline bool classof(const VPRecipeBase *R) { \ return R->getVPDefID() == VPDefID; \ + } \ + static inline bool classof(const VPSingleDefRecipe *R) { \ + return R->getVPDefID() == VPDefID; \ } +/// VPSingleDef is a base class for recipes for modeling a sequence of one or +/// more output IR that define a single result VPValue. +/// Note that VPRecipeBase must be inherited from before VPValue. +class VPSingleDefRecipe : public VPRecipeBase, public VPValue { +public: + template + VPSingleDefRecipe(const unsigned char SC, IterT Operands, DebugLoc DL = {}) + : VPRecipeBase(SC, Operands, DL), VPValue(this) {} + + VPSingleDefRecipe(const unsigned char SC, ArrayRef Operands, + DebugLoc DL = {}) + : VPRecipeBase(SC, Operands, DL), VPValue(this) {} + + template + VPSingleDefRecipe(const unsigned char SC, IterT Operands, Value *UV, + DebugLoc DL = {}) + : VPRecipeBase(SC, Operands, DL), VPValue(this, UV) {} + + static inline bool classof(const VPRecipeBase *R) { + switch (R->getVPDefID()) { + case VPRecipeBase::VPDerivedIVSC: + case VPRecipeBase::VPExpandSCEVSC: + case VPRecipeBase::VPInstructionSC: + case VPRecipeBase::VPReductionSC: + case VPRecipeBase::VPReplicateSC: + case VPRecipeBase::VPScalarIVStepsSC: + case VPRecipeBase::VPVectorPointerSC: + case VPRecipeBase::VPWidenCallSC: + case VPRecipeBase::VPWidenCanonicalIVSC: + case VPRecipeBase::VPWidenCastSC: + case VPRecipeBase::VPWidenGEPSC: + case VPRecipeBase::VPWidenSC: + case VPRecipeBase::VPWidenSelectSC: + case VPRecipeBase::VPBlendSC: + case VPRecipeBase::VPPredInstPHISC: + case VPRecipeBase::VPCanonicalIVPHISC: + case VPRecipeBase::VPActiveLaneMaskPHISC: + case VPRecipeBase::VPFirstOrderRecurrencePHISC: + case VPRecipeBase::VPWidenPHISC: + case VPRecipeBase::VPWidenIntOrFpInductionSC: + case VPRecipeBase::VPWidenPointerInductionSC: + case VPRecipeBase::VPReductionPHISC: + return true; + case VPRecipeBase::VPInterleaveSC: + case VPRecipeBase::VPBranchOnMaskSC: + case VPRecipeBase::VPWidenMemoryInstructionSC: + // TODO: Widened stores don't define a value, but widened loads do. Split + // the recipes to be able to make widened loads VPSingleDefRecipes. + return false; + } + llvm_unreachable("Unhandled VPDefID"); + } + + static inline bool classof(const VPUser *U) { + auto *R = dyn_cast(U); + return R && classof(R); + } + + /// Returns the underlying instruction. + Instruction *getUnderlyingInstr() { + return cast(getUnderlyingValue()); + } + const Instruction *getUnderlyingInstr() const { + return cast(getUnderlyingValue()); + } +}; + /// Class to record LLVM IR flag for a recipe along with it. -class VPRecipeWithIRFlags : public VPRecipeBase { +class VPRecipeWithIRFlags : public VPSingleDefRecipe { enum class OperationType : unsigned char { Cmp, OverflowingBinOp, @@ -886,14 +949,14 @@ private: public: template VPRecipeWithIRFlags(const unsigned char SC, IterT Operands, DebugLoc DL = {}) - : VPRecipeBase(SC, Operands, DL) { + : VPSingleDefRecipe(SC, Operands, DL) { OpType = OperationType::Other; AllFlags = 0; } template VPRecipeWithIRFlags(const unsigned char SC, IterT Operands, Instruction &I) - : VPRecipeWithIRFlags(SC, Operands, I.getDebugLoc()) { + : VPSingleDefRecipe(SC, Operands, &I, I.getDebugLoc()) { if (auto *Op = dyn_cast(&I)) { OpType = OperationType::Cmp; CmpPredicate = Op->getPredicate(); @@ -915,32 +978,35 @@ public: } else if (auto *Op = dyn_cast(&I)) { OpType = OperationType::FPMathOp; FMFs = Op->getFastMathFlags(); + } else { + OpType = OperationType::Other; + AllFlags = 0; } } template VPRecipeWithIRFlags(const unsigned char SC, IterT Operands, CmpInst::Predicate Pred, DebugLoc DL = {}) - : VPRecipeBase(SC, Operands, DL), OpType(OperationType::Cmp), + : VPSingleDefRecipe(SC, Operands, DL), OpType(OperationType::Cmp), CmpPredicate(Pred) {} template VPRecipeWithIRFlags(const unsigned char SC, IterT Operands, WrapFlagsTy WrapFlags, DebugLoc DL = {}) - : VPRecipeBase(SC, Operands, DL), OpType(OperationType::OverflowingBinOp), - WrapFlags(WrapFlags) {} + : VPSingleDefRecipe(SC, Operands, DL), + OpType(OperationType::OverflowingBinOp), WrapFlags(WrapFlags) {} template VPRecipeWithIRFlags(const unsigned char SC, IterT Operands, FastMathFlags FMFs, DebugLoc DL = {}) - : VPRecipeBase(SC, Operands, DL), OpType(OperationType::FPMathOp), + : VPSingleDefRecipe(SC, Operands, DL), OpType(OperationType::FPMathOp), FMFs(FMFs) {} protected: template VPRecipeWithIRFlags(const unsigned char SC, IterT Operands, GEPFlagsTy GEPFlags, DebugLoc DL = {}) - : VPRecipeBase(SC, Operands, DL), OpType(OperationType::GEPOp), + : VPSingleDefRecipe(SC, Operands, DL), OpType(OperationType::GEPOp), GEPFlags(GEPFlags) {} public: @@ -1056,7 +1122,7 @@ public: /// While as any Recipe it may generate a sequence of IR instructions when /// executed, these instructions would always form a single-def expression as /// the VPInstruction is also a single def-use vertex. -class VPInstruction : public VPRecipeWithIRFlags, public VPValue { +class VPInstruction : public VPRecipeWithIRFlags { friend class VPlanSlp; public: @@ -1103,7 +1169,7 @@ public: VPInstruction(unsigned Opcode, ArrayRef Operands, DebugLoc DL, const Twine &Name = "") : VPRecipeWithIRFlags(VPDef::VPInstructionSC, Operands, DL), - VPValue(this), Opcode(Opcode), Name(Name.str()) {} + Opcode(Opcode), Name(Name.str()) {} VPInstruction(unsigned Opcode, std::initializer_list Operands, DebugLoc DL = {}, const Twine &Name = "") @@ -1115,7 +1181,7 @@ public: VPInstruction(unsigned Opcode, std::initializer_list Operands, WrapFlagsTy WrapFlags, DebugLoc DL = {}, const Twine &Name = "") : VPRecipeWithIRFlags(VPDef::VPInstructionSC, Operands, WrapFlags, DL), - VPValue(this), Opcode(Opcode), Name(Name.str()) {} + Opcode(Opcode), Name(Name.str()) {} VPInstruction(unsigned Opcode, std::initializer_list Operands, FastMathFlags FMFs, DebugLoc DL = {}, const Twine &Name = ""); @@ -1205,13 +1271,13 @@ public: /// VPWidenRecipe is a recipe for producing a copy of vector type its /// ingredient. This recipe covers most of the traditional vectorization cases /// where each ingredient transforms into a vectorized version of itself. -class VPWidenRecipe : public VPRecipeWithIRFlags, public VPValue { +class VPWidenRecipe : public VPRecipeWithIRFlags { unsigned Opcode; public: template VPWidenRecipe(Instruction &I, iterator_range Operands) - : VPRecipeWithIRFlags(VPDef::VPWidenSC, Operands, I), VPValue(this, &I), + : VPRecipeWithIRFlags(VPDef::VPWidenSC, Operands, I), Opcode(I.getOpcode()) {} ~VPWidenRecipe() override = default; @@ -1231,7 +1297,7 @@ public: }; /// VPWidenCastRecipe is a recipe to create vector cast instructions. -class VPWidenCastRecipe : public VPRecipeWithIRFlags, public VPValue { +class VPWidenCastRecipe : public VPRecipeWithIRFlags { /// Cast instruction opcode. Instruction::CastOps Opcode; @@ -1241,8 +1307,8 @@ class VPWidenCastRecipe : public VPRecipeWithIRFlags, public VPValue { public: VPWidenCastRecipe(Instruction::CastOps Opcode, VPValue *Op, Type *ResultTy, CastInst &UI) - : VPRecipeWithIRFlags(VPDef::VPWidenCastSC, Op, UI), VPValue(this, &UI), - Opcode(Opcode), ResultTy(ResultTy) { + : VPRecipeWithIRFlags(VPDef::VPWidenCastSC, Op, UI), Opcode(Opcode), + ResultTy(ResultTy) { assert(UI.getOpcode() == Opcode && "opcode of underlying cast doesn't match"); assert(UI.getType() == ResultTy && @@ -1250,8 +1316,8 @@ public: } VPWidenCastRecipe(Instruction::CastOps Opcode, VPValue *Op, Type *ResultTy) - : VPRecipeWithIRFlags(VPDef::VPWidenCastSC, Op), VPValue(this, nullptr), - Opcode(Opcode), ResultTy(ResultTy) {} + : VPRecipeWithIRFlags(VPDef::VPWidenCastSC, Op), Opcode(Opcode), + ResultTy(ResultTy) {} ~VPWidenCastRecipe() override = default; @@ -1273,7 +1339,7 @@ public: }; /// A recipe for widening Call instructions. -class VPWidenCallRecipe : public VPRecipeBase, public VPValue { +class VPWidenCallRecipe : public VPSingleDefRecipe { /// ID of the vector intrinsic to call when widening the call. If set the /// Intrinsic::not_intrinsic, a library call will be used instead. Intrinsic::ID VectorIntrinsicID; @@ -1286,9 +1352,9 @@ class VPWidenCallRecipe : public VPRecipeBase, public VPValue { public: template VPWidenCallRecipe(CallInst &I, iterator_range CallArguments, - Intrinsic::ID VectorIntrinsicID, + Intrinsic::ID VectorIntrinsicID, DebugLoc DL = {}, Function *Variant = nullptr) - : VPRecipeBase(VPDef::VPWidenCallSC, CallArguments), VPValue(this, &I), + : VPSingleDefRecipe(VPDef::VPWidenCallSC, CallArguments, &I, DL), VectorIntrinsicID(VectorIntrinsicID), Variant(Variant) {} ~VPWidenCallRecipe() override = default; @@ -1306,11 +1372,11 @@ public: }; /// A recipe for widening select instructions. -struct VPWidenSelectRecipe : public VPRecipeBase, public VPValue { +struct VPWidenSelectRecipe : public VPSingleDefRecipe { template VPWidenSelectRecipe(SelectInst &I, iterator_range Operands) - : VPRecipeBase(VPDef::VPWidenSelectSC, Operands, I.getDebugLoc()), - VPValue(this, &I) {} + : VPSingleDefRecipe(VPDef::VPWidenSelectSC, Operands, &I, + I.getDebugLoc()) {} ~VPWidenSelectRecipe() override = default; @@ -1335,7 +1401,7 @@ struct VPWidenSelectRecipe : public VPRecipeBase, public VPValue { }; /// A recipe for handling GEP instructions. -class VPWidenGEPRecipe : public VPRecipeWithIRFlags, public VPValue { +class VPWidenGEPRecipe : public VPRecipeWithIRFlags { bool isPointerLoopInvariant() const { return getOperand(0)->isDefinedOutsideVectorRegions(); } @@ -1353,8 +1419,7 @@ class VPWidenGEPRecipe : public VPRecipeWithIRFlags, public VPValue { public: template VPWidenGEPRecipe(GetElementPtrInst *GEP, iterator_range Operands) - : VPRecipeWithIRFlags(VPDef::VPWidenGEPSC, Operands, *GEP), - VPValue(this, GEP) {} + : VPRecipeWithIRFlags(VPDef::VPWidenGEPSC, Operands, *GEP) {} ~VPWidenGEPRecipe() override = default; @@ -1373,7 +1438,7 @@ public: /// A recipe to compute the pointers for widened memory accesses of IndexTy for /// all parts. If IsReverse is true, compute pointers for accessing the input in /// reverse order per part. -class VPVectorPointerRecipe : public VPRecipeWithIRFlags, public VPValue { +class VPVectorPointerRecipe : public VPRecipeWithIRFlags { Type *IndexedTy; bool IsReverse; @@ -1382,7 +1447,7 @@ public: bool IsInBounds, DebugLoc DL) : VPRecipeWithIRFlags(VPDef::VPVectorPointerSC, ArrayRef(Ptr), GEPFlagsTy(IsInBounds), DL), - VPValue(this), IndexedTy(IndexedTy), IsReverse(IsReverse) {} + IndexedTy(IndexedTy), IsReverse(IsReverse) {} VP_CLASSOF_IMPL(VPDef::VPVectorPointerSC) @@ -1424,11 +1489,11 @@ public: /// * VPWidenPointerInductionRecipe: Generate vector and scalar values for a /// pointer induction. Produces either a vector PHI per-part or scalar values /// per-lane based on the canonical induction. -class VPHeaderPHIRecipe : public VPRecipeBase, public VPValue { +class VPHeaderPHIRecipe : public VPSingleDefRecipe { protected: VPHeaderPHIRecipe(unsigned char VPDefID, Instruction *UnderlyingInstr, VPValue *Start = nullptr, DebugLoc DL = {}) - : VPRecipeBase(VPDefID, {}, DL), VPValue(this, UnderlyingInstr) { + : VPSingleDefRecipe(VPDefID, ArrayRef(), UnderlyingInstr, DL) { if (Start) addOperand(Start); } @@ -1709,14 +1774,13 @@ public: /// A recipe for vectorizing a phi-node as a sequence of mask-based select /// instructions. -class VPBlendRecipe : public VPRecipeBase, public VPValue { +class VPBlendRecipe : public VPSingleDefRecipe { public: /// The blend operation is a User of the incoming values and of their /// respective masks, ordered [I0, M0, I1, M1, ...]. Note that a single value /// might be incoming with a full mask for which there is no VPValue. VPBlendRecipe(PHINode *Phi, ArrayRef Operands) - : VPRecipeBase(VPDef::VPBlendSC, Operands, Phi->getDebugLoc()), - VPValue(this, Phi) { + : VPSingleDefRecipe(VPDef::VPBlendSC, Operands, Phi, Phi->getDebugLoc()) { assert(Operands.size() > 0 && ((Operands.size() == 1) || (Operands.size() % 2 == 0)) && "Expected either a single incoming value or a positive even number " @@ -1843,14 +1907,15 @@ public: /// A recipe to represent inloop reduction operations, performing a reduction on /// a vector operand into a scalar value, and adding the result to a chain. /// The Operands are {ChainOp, VecOp, [Condition]}. -class VPReductionRecipe : public VPRecipeBase, public VPValue { +class VPReductionRecipe : public VPSingleDefRecipe { /// The recurrence decriptor for the reduction in question. const RecurrenceDescriptor &RdxDesc; public: VPReductionRecipe(const RecurrenceDescriptor &R, Instruction *I, VPValue *ChainOp, VPValue *VecOp, VPValue *CondOp) - : VPRecipeBase(VPDef::VPReductionSC, {ChainOp, VecOp}), VPValue(this, I), + : VPSingleDefRecipe(VPDef::VPReductionSC, + ArrayRef({ChainOp, VecOp}), I), RdxDesc(R) { if (CondOp) addOperand(CondOp); @@ -1883,7 +1948,7 @@ public: /// copies of the original scalar type, one per lane, instead of producing a /// single copy of widened type for all lanes. If the instruction is known to be /// uniform only one copy, per lane zero, will be generated. -class VPReplicateRecipe : public VPRecipeWithIRFlags, public VPValue { +class VPReplicateRecipe : public VPRecipeWithIRFlags { /// Indicator if only a single replica per lane is needed. bool IsUniform; @@ -1895,7 +1960,7 @@ public: VPReplicateRecipe(Instruction *I, iterator_range Operands, bool IsUniform, VPValue *Mask = nullptr) : VPRecipeWithIRFlags(VPDef::VPReplicateSC, Operands, *I), - VPValue(this, I), IsUniform(IsUniform), IsPredicated(Mask) { + IsUniform(IsUniform), IsPredicated(Mask) { if (Mask) addOperand(Mask); } @@ -1993,12 +2058,12 @@ public: /// order to merge values that are set under such a branch and feed their uses. /// The phi nodes can be scalar or vector depending on the users of the value. /// This recipe works in concert with VPBranchOnMaskRecipe. -class VPPredInstPHIRecipe : public VPRecipeBase, public VPValue { +class VPPredInstPHIRecipe : public VPSingleDefRecipe { public: /// Construct a VPPredInstPHIRecipe given \p PredInst whose value needs a phi /// nodes after merging back from a Branch-on-Mask. VPPredInstPHIRecipe(VPValue *PredV) - : VPRecipeBase(VPDef::VPPredInstPHISC, PredV), VPValue(this) {} + : VPSingleDefRecipe(VPDef::VPPredInstPHISC, PredV) {} ~VPPredInstPHIRecipe() override = default; VP_CLASSOF_IMPL(VPDef::VPPredInstPHISC) @@ -2119,14 +2184,13 @@ public: }; /// Recipe to expand a SCEV expression. -class VPExpandSCEVRecipe : public VPRecipeBase, public VPValue { +class VPExpandSCEVRecipe : public VPSingleDefRecipe { const SCEV *Expr; ScalarEvolution &SE; public: VPExpandSCEVRecipe(const SCEV *Expr, ScalarEvolution &SE) - : VPRecipeBase(VPDef::VPExpandSCEVSC, {}), VPValue(this), Expr(Expr), - SE(SE) {} + : VPSingleDefRecipe(VPDef::VPExpandSCEVSC, {}), Expr(Expr), SE(SE) {} ~VPExpandSCEVRecipe() override = default; @@ -2225,11 +2289,10 @@ public: }; /// A Recipe for widening the canonical induction variable of the vector loop. -class VPWidenCanonicalIVRecipe : public VPRecipeBase, public VPValue { +class VPWidenCanonicalIVRecipe : public VPSingleDefRecipe { public: VPWidenCanonicalIVRecipe(VPCanonicalIVPHIRecipe *CanonicalIV) - : VPRecipeBase(VPDef::VPWidenCanonicalIVSC, {CanonicalIV}), - VPValue(this) {} + : VPSingleDefRecipe(VPDef::VPWidenCanonicalIVSC, {CanonicalIV}) {} ~VPWidenCanonicalIVRecipe() override = default; @@ -2256,7 +2319,7 @@ public: /// A recipe for converting the canonical IV value to the corresponding value of /// an IV with different start and step values, using Start + CanonicalIV * /// Step. -class VPDerivedIVRecipe : public VPRecipeBase, public VPValue { +class VPDerivedIVRecipe : public VPSingleDefRecipe { /// If not nullptr, the result of the induction will get truncated to /// TruncResultTy. Type *TruncResultTy; @@ -2271,8 +2334,8 @@ public: VPDerivedIVRecipe(const InductionDescriptor &IndDesc, VPValue *Start, VPCanonicalIVPHIRecipe *CanonicalIV, VPValue *Step, Type *TruncResultTy) - : VPRecipeBase(VPDef::VPDerivedIVSC, {Start, CanonicalIV, Step}), - VPValue(this), TruncResultTy(TruncResultTy), Kind(IndDesc.getKind()), + : VPSingleDefRecipe(VPDef::VPDerivedIVSC, {Start, CanonicalIV, Step}), + TruncResultTy(TruncResultTy), Kind(IndDesc.getKind()), FPBinOp(dyn_cast_or_null(IndDesc.getInductionBinOp())) { } @@ -2309,7 +2372,7 @@ public: /// A recipe for handling phi nodes of integer and floating-point inductions, /// producing their scalar values. -class VPScalarIVStepsRecipe : public VPRecipeWithIRFlags, public VPValue { +class VPScalarIVStepsRecipe : public VPRecipeWithIRFlags { Instruction::BinaryOps InductionOpcode; public: @@ -2317,7 +2380,7 @@ public: Instruction::BinaryOps Opcode, FastMathFlags FMFs) : VPRecipeWithIRFlags(VPDef::VPScalarIVStepsSC, ArrayRef({IV, Step}), FMFs), - VPValue(this), InductionOpcode(Opcode) {} + InductionOpcode(Opcode) {} VPScalarIVStepsRecipe(const InductionDescriptor &IndDesc, VPValue *IV, VPValue *Step) diff --git a/llvm/lib/Transforms/Vectorize/VPlanHCFGBuilder.cpp b/llvm/lib/Transforms/Vectorize/VPlanHCFGBuilder.cpp index f950d4740e4..94456bf858d 100644 --- a/llvm/lib/Transforms/Vectorize/VPlanHCFGBuilder.cpp +++ b/llvm/lib/Transforms/Vectorize/VPlanHCFGBuilder.cpp @@ -283,7 +283,7 @@ VPValue *PlainCFGBuilder::getOrCreateVPOperand(Value *IRVal) { void PlainCFGBuilder::createVPInstructionsForVPBB(VPBasicBlock *VPBB, BasicBlock *BB) { VPIRBuilder.setInsertPoint(VPBB); - for (Instruction &InstRef : *BB) { + for (Instruction &InstRef : BB->instructionsWithoutDebug(false)) { Instruction *Inst = &InstRef; // There shouldn't be any VPValue for Inst at this point. Otherwise, we diff --git a/llvm/lib/Transforms/Vectorize/VPlanRecipes.cpp b/llvm/lib/Transforms/Vectorize/VPlanRecipes.cpp index 1f844bce231..bbeb5da2cfe 100644 --- a/llvm/lib/Transforms/Vectorize/VPlanRecipes.cpp +++ b/llvm/lib/Transforms/Vectorize/VPlanRecipes.cpp @@ -258,7 +258,7 @@ VPInstruction::VPInstruction(unsigned Opcode, CmpInst::Predicate Pred, const Twine &Name) : VPRecipeWithIRFlags(VPDef::VPInstructionSC, ArrayRef({A, B}), Pred, DL), - VPValue(this), Opcode(Opcode), Name(Name.str()) { + Opcode(Opcode), Name(Name.str()) { assert(Opcode == Instruction::ICmp && "only ICmp predicates supported at the moment"); } @@ -267,7 +267,7 @@ VPInstruction::VPInstruction(unsigned Opcode, std::initializer_list Operands, FastMathFlags FMFs, DebugLoc DL, const Twine &Name) : VPRecipeWithIRFlags(VPDef::VPInstructionSC, Operands, FMFs, DL), - VPValue(this), Opcode(Opcode), Name(Name.str()) { + Opcode(Opcode), Name(Name.str()) { // Make sure the VPInstruction is a floating-point operation. assert(isFPMathOp() && "this op can't take fast-math flags"); } @@ -580,7 +580,7 @@ void VPWidenCallRecipe::execute(VPTransformState &State) { auto &CI = *cast(getUnderlyingInstr()); assert(!isa(CI) && "DbgInfoIntrinsic should have been dropped during VPlan construction"); - State.setDebugLocFrom(CI.getDebugLoc()); + State.setDebugLocFrom(getDebugLoc()); bool UseIntrinsic = VectorIntrinsicID != Intrinsic::not_intrinsic; FunctionType *VFTy = nullptr; @@ -1712,16 +1712,20 @@ void VPFirstOrderRecurrencePHIRecipe::print(raw_ostream &O, const Twine &Indent, #endif void VPReductionPHIRecipe::execute(VPTransformState &State) { - PHINode *PN = cast(getUnderlyingValue()); auto &Builder = State.Builder; + // Reductions do not have to start at zero. They can start with + // any loop invariant values. + VPValue *StartVPV = getStartValue(); + Value *StartV = StartVPV->getLiveInIRValue(); + // In order to support recurrences we need to be able to vectorize Phi nodes. // Phi nodes have cycles, so we need to vectorize them in two stages. This is // stage #1: We create a new vector PHI node with no incoming edges. We'll use // this value when we vectorize all of the instructions that use the PHI. bool ScalarPHI = State.VF.isScalar() || IsInLoop; - Type *VecTy = - ScalarPHI ? PN->getType() : VectorType::get(PN->getType(), State.VF); + Type *VecTy = ScalarPHI ? StartV->getType() + : VectorType::get(StartV->getType(), State.VF); BasicBlock *HeaderBB = State.CFG.PrevBB; assert(State.CurrentVectorLoop->getHeader() == HeaderBB && @@ -1735,11 +1739,6 @@ void VPReductionPHIRecipe::execute(VPTransformState &State) { BasicBlock *VectorPH = State.CFG.getPreheaderBBFor(this); - // Reductions do not have to start at zero. They can start with - // any loop invariant values. - VPValue *StartVPV = getStartValue(); - Value *StartV = StartVPV->getLiveInIRValue(); - Value *Iden = nullptr; RecurKind RK = RdxDesc.getRecurrenceKind(); if (RecurrenceDescriptor::isMinMaxRecurrenceKind(RK) || diff --git a/llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp b/llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp index 5c430620a2d..8e6b48cdb2c 100644 --- a/llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp +++ b/llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp @@ -74,9 +74,9 @@ void VPlanTransforms::VPInstructionsToVPRecipes( } else if (GetElementPtrInst *GEP = dyn_cast(Inst)) { NewRecipe = new VPWidenGEPRecipe(GEP, Ingredient.operands()); } else if (CallInst *CI = dyn_cast(Inst)) { - NewRecipe = - new VPWidenCallRecipe(*CI, drop_end(Ingredient.operands()), - getVectorIntrinsicIDForCall(CI, &TLI)); + NewRecipe = new VPWidenCallRecipe( + *CI, drop_end(Ingredient.operands()), + getVectorIntrinsicIDForCall(CI, &TLI), CI->getDebugLoc()); } else if (SelectInst *SI = dyn_cast(Inst)) { NewRecipe = new VPWidenSelectRecipe(*SI, Ingredient.operands()); } else if (auto *CI = dyn_cast(Inst)) { @@ -103,7 +103,7 @@ static bool sinkScalarOperands(VPlan &Plan) { bool Changed = false; // First, collect the operands of all recipes in replicate blocks as seeds for // sinking. - SetVector> WorkList; + SetVector> WorkList; for (VPRegionBlock *VPR : VPBlockUtils::blocksOnly(Iter)) { VPBasicBlock *EntryVPBB = VPR->getEntryBasicBlock(); if (!VPR->isReplicator() || EntryVPBB->getSuccessors().size() != 2) @@ -113,7 +113,8 @@ static bool sinkScalarOperands(VPlan &Plan) { continue; for (auto &Recipe : *VPBB) { for (VPValue *Op : Recipe.operands()) - if (auto *Def = Op->getDefiningRecipe()) + if (auto *Def = + dyn_cast_or_null(Op->getDefiningRecipe())) WorkList.insert(std::make_pair(VPBB, Def)); } } @@ -122,7 +123,7 @@ static bool sinkScalarOperands(VPlan &Plan) { // Try to sink each replicate or scalar IV steps recipe in the worklist. for (unsigned I = 0; I != WorkList.size(); ++I) { VPBasicBlock *SinkTo; - VPRecipeBase *SinkCandidate; + VPSingleDefRecipe *SinkCandidate; std::tie(SinkTo, SinkCandidate) = WorkList[I]; if (SinkCandidate->getParent() == SinkTo || SinkCandidate->mayHaveSideEffects() || @@ -146,12 +147,11 @@ static bool sinkScalarOperands(VPlan &Plan) { return false; if (UI->getParent() == SinkTo) return true; - NeedsDuplicating = - UI->onlyFirstLaneUsed(SinkCandidate->getVPSingleValue()); + NeedsDuplicating = UI->onlyFirstLaneUsed(SinkCandidate); // We only know how to duplicate VPRecipeRecipes for now. return NeedsDuplicating && isa(SinkCandidate); }; - if (!all_of(SinkCandidate->getVPSingleValue()->users(), CanSinkWithUser)) + if (!all_of(SinkCandidate->users(), CanSinkWithUser)) continue; if (NeedsDuplicating) { @@ -163,14 +163,14 @@ static bool sinkScalarOperands(VPlan &Plan) { // TODO: add ".cloned" suffix to name of Clone's VPValue. Clone->insertBefore(SinkCandidate); - SinkCandidate->getVPSingleValue()->replaceUsesWithIf( - Clone, [SinkTo](VPUser &U, unsigned) { - return cast(&U)->getParent() != SinkTo; - }); + SinkCandidate->replaceUsesWithIf(Clone, [SinkTo](VPUser &U, unsigned) { + return cast(&U)->getParent() != SinkTo; + }); } SinkCandidate->moveBefore(*SinkTo, SinkTo->getFirstNonPhi()); for (VPValue *Op : SinkCandidate->operands()) - if (auto *Def = Op->getDefiningRecipe()) + if (auto *Def = + dyn_cast_or_null(Op->getDefiningRecipe())) WorkList.insert(std::make_pair(SinkTo, Def)); Changed = true; } @@ -412,16 +412,15 @@ void VPlanTransforms::removeRedundantInductionCasts(VPlan &Plan) { auto &Casts = IV->getInductionDescriptor().getCastInsts(); VPValue *FindMyCast = IV; for (Instruction *IRCast : reverse(Casts)) { - VPRecipeBase *FoundUserCast = nullptr; + VPSingleDefRecipe *FoundUserCast = nullptr; for (auto *U : FindMyCast->users()) { - auto *UserCast = cast(U); - if (UserCast->getNumDefinedValues() == 1 && - UserCast->getVPSingleValue()->getUnderlyingValue() == IRCast) { + auto *UserCast = dyn_cast(U); + if (UserCast && UserCast->getUnderlyingValue() == IRCast) { FoundUserCast = UserCast; break; } } - FindMyCast = FoundUserCast->getVPSingleValue(); + FindMyCast = FoundUserCast; } FindMyCast->replaceAllUsesWith(IV); } @@ -895,7 +894,10 @@ void VPlanTransforms::truncateToMinimalBitwidths( vp_depth_first_deep(Plan.getVectorLoopRegion()))) { for (VPRecipeBase &R : make_early_inc_range(*VPBB)) { if (!isa(&R)) + VPWidenSelectRecipe, VPWidenMemoryInstructionRecipe>(&R)) + continue; + if (isa(&R) && + cast(&R)->isStore()) continue; VPValue *ResultVPV = R.getVPSingleValue(); @@ -948,6 +950,23 @@ void VPlanTransforms::truncateToMinimalBitwidths( auto *NewResTy = IntegerType::get(Ctx, NewResSizeInBits); + // Any wrapping introduced by shrinking this operation shouldn't be + // considered undefined behavior. So, we can't unconditionally copy + // arithmetic wrapping flags to VPW. + if (auto *VPW = dyn_cast(&R)) + VPW->dropPoisonGeneratingFlags(); + + // Extend result to original width. + auto *Ext = new VPWidenCastRecipe(Instruction::ZExt, ResultVPV, OldResTy); + Ext->insertAfter(&R); + ResultVPV->replaceAllUsesWith(Ext); + Ext->setOperand(0, ResultVPV); + + if (isa(&R)) { + assert(!cast(&R)->isStore() && "stores cannot be narrowed"); + continue; + } + // Shrink operands by introducing truncates as needed. unsigned StartIdx = isa(&R) ? 1 : 0; for (unsigned Idx = StartIdx; Idx != R.getNumOperands(); ++Idx) { @@ -979,17 +998,6 @@ void VPlanTransforms::truncateToMinimalBitwidths( } } - // Any wrapping introduced by shrinking this operation shouldn't be - // considered undefined behavior. So, we can't unconditionally copy - // arithmetic wrapping flags to VPW. - if (auto *VPW = dyn_cast(&R)) - VPW->dropPoisonGeneratingFlags(); - - // Extend result to original width. - auto *Ext = new VPWidenCastRecipe(Instruction::ZExt, ResultVPV, OldResTy); - Ext->insertAfter(&R); - ResultVPV->replaceAllUsesWith(Ext); - Ext->setOperand(0, ResultVPV); } } @@ -1130,7 +1138,7 @@ void VPlanTransforms::addActiveLaneMask( "Must have widened canonical IV when tail folding!"); auto *WideCanonicalIV = cast(*FoundWidenCanonicalIVUser); - VPRecipeBase *LaneMask; + VPSingleDefRecipe *LaneMask; if (UseActiveLaneMaskForControlFlow) { LaneMask = addVPLaneMaskPhiAndUpdateExitBranch( Plan, DataAndControlFlowWithoutRuntimeCheck); @@ -1155,7 +1163,7 @@ void VPlanTransforms::addActiveLaneMask( assert(CompareToReplace->getOperand(0) == WideCanonicalIV && "WidenCanonicalIV must be the first operand of the compare"); - CompareToReplace->replaceAllUsesWith(LaneMask->getVPSingleValue()); + CompareToReplace->replaceAllUsesWith(LaneMask); CompareToReplace->eraseFromParent(); } } diff --git a/llvm/lib/WindowsDriver/MSVCPaths.cpp b/llvm/lib/WindowsDriver/MSVCPaths.cpp index 1c070bf1bf7..634cfcb15f1 100644 --- a/llvm/lib/WindowsDriver/MSVCPaths.cpp +++ b/llvm/lib/WindowsDriver/MSVCPaths.cpp @@ -114,7 +114,7 @@ static bool getWindowsSDKDirViaCommandLine( else llvm::sys::path::append( SDKPath, getHighestNumericTupleInDirectory(VFS, SDKPath)); - Path = std::string(SDKPath.str()); + Path = std::string(SDKPath); } else { Path = WinSdkDir->str(); } @@ -328,7 +328,7 @@ bool appendArchToWindowsSDKLibPath(int SDKMajor, SmallString<128> LibPath, } } - path = std::string(LibPath.str()); + path = std::string(LibPath); return true; } @@ -383,7 +383,7 @@ std::string getSubDirectoryPath(SubDirectoryType Type, ToolsetLayout VSLayout, sys::path::append(Path, "lib", SubdirName); break; } - return std::string(Path.str()); + return std::string(Path); } bool useUniversalCRT(ToolsetLayout VSLayout, const std::string &VCToolChainPath, @@ -491,7 +491,7 @@ bool findVCToolChainViaCommandLine(vfs::FileSystem &VFS, else ToolsVersion = getHighestNumericTupleInDirectory(VFS, ToolsPath); sys::path::append(ToolsPath, ToolsVersion); - Path = std::string(ToolsPath.str()); + Path = std::string(ToolsPath); } else { Path = VCToolsDir->str(); } @@ -720,7 +720,7 @@ bool findVCToolChainViaRegistry(std::string &Path, ToolsetLayout &VSLayout) { SmallString<256> VCPath(StringRef(VSInstallPath.c_str(), pos)); sys::path::append(VCPath, "VC"); - Path = std::string(VCPath.str()); + Path = std::string(VCPath); VSLayout = ToolsetLayout::OlderVS; return true; } diff --git a/llvm/lib/XRay/Trace.cpp b/llvm/lib/XRay/Trace.cpp index b870adf5654..74515b16417 100644 --- a/llvm/lib/XRay/Trace.cpp +++ b/llvm/lib/XRay/Trace.cpp @@ -51,6 +51,9 @@ Error loadNaiveFormatLog(StringRef Data, bool IsLittleEndian, return FileHeaderOrError.takeError(); FileHeader = std::move(FileHeaderOrError.get()); + size_t NumReservations = llvm::divideCeil(Reader.size() - OffsetPtr, 32U); + Records.reserve(NumReservations); + // Each record after the header will be 32 bytes, in the following format: // // (2) uint16 : record type diff --git a/llvm/tools/bugpoint/ExecutionDriver.cpp b/llvm/tools/bugpoint/ExecutionDriver.cpp index 2b06e8f3b36..18187ad97dd 100644 --- a/llvm/tools/bugpoint/ExecutionDriver.cpp +++ b/llvm/tools/bugpoint/ExecutionDriver.cpp @@ -299,7 +299,7 @@ Expected BugDriver::executeProgram(const Module &Program, << "!\n"; exit(1); } - BitcodeFile = std::string(UniqueFilename.str()); + BitcodeFile = std::string(UniqueFilename); if (writeProgramToFile(BitcodeFile, UniqueFD, Program)) { errs() << ToolName << ": Error emitting bitcode to file '" << BitcodeFile @@ -324,7 +324,7 @@ Expected BugDriver::executeProgram(const Module &Program, << "\n"; exit(1); } - OutputFile = std::string(UniqueFile.str()); + OutputFile = std::string(UniqueFile); // Figure out which shared objects to run, if any. std::vector SharedObjs(AdditionalSOs); diff --git a/llvm/tools/bugpoint/Miscompilation.cpp b/llvm/tools/bugpoint/Miscompilation.cpp index 130c6fabd2d..22806bab83e 100644 --- a/llvm/tools/bugpoint/Miscompilation.cpp +++ b/llvm/tools/bugpoint/Miscompilation.cpp @@ -956,8 +956,7 @@ static Expected TestCodeGenerator(BugDriver &BD, << "Error making unique filename: " << EC.message() << "\n"; exit(1); } - if (BD.writeProgramToFile(std::string(TestModuleBC.str()), TestModuleFD, - *Test)) { + if (BD.writeProgramToFile(std::string(TestModuleBC), TestModuleFD, *Test)) { errs() << "Error writing bitcode to `" << TestModuleBC.str() << "'\nExiting."; exit(1); @@ -976,8 +975,7 @@ static Expected TestCodeGenerator(BugDriver &BD, exit(1); } - if (BD.writeProgramToFile(std::string(SafeModuleBC.str()), SafeModuleFD, - *Safe)) { + if (BD.writeProgramToFile(std::string(SafeModuleBC), SafeModuleFD, *Safe)) { errs() << "Error writing bitcode to `" << SafeModuleBC << "'\nExiting."; exit(1); } @@ -985,7 +983,7 @@ static Expected TestCodeGenerator(BugDriver &BD, FileRemover SafeModuleBCRemover(SafeModuleBC.str(), !SaveTemps); Expected SharedObject = - BD.compileSharedObject(std::string(SafeModuleBC.str())); + BD.compileSharedObject(std::string(SafeModuleBC)); if (Error E = SharedObject.takeError()) return std::move(E); @@ -994,7 +992,7 @@ static Expected TestCodeGenerator(BugDriver &BD, // Run the code generator on the `Test' code, loading the shared library. // The function returns whether or not the new output differs from reference. Expected Result = BD.diffProgram( - BD.getProgram(), std::string(TestModuleBC.str()), *SharedObject, false); + BD.getProgram(), std::string(TestModuleBC), *SharedObject, false); if (Error E = Result.takeError()) return std::move(E); @@ -1051,8 +1049,7 @@ Error BugDriver::debugCodeGenerator() { exit(1); } - if (writeProgramToFile(std::string(TestModuleBC.str()), TestModuleFD, - *ToCodeGen)) { + if (writeProgramToFile(std::string(TestModuleBC), TestModuleFD, *ToCodeGen)) { errs() << "Error writing bitcode to `" << TestModuleBC << "'\nExiting."; exit(1); } @@ -1068,13 +1065,13 @@ Error BugDriver::debugCodeGenerator() { exit(1); } - if (writeProgramToFile(std::string(SafeModuleBC.str()), SafeModuleFD, + if (writeProgramToFile(std::string(SafeModuleBC), SafeModuleFD, *ToNotCodeGen)) { errs() << "Error writing bitcode to `" << SafeModuleBC << "'\nExiting."; exit(1); } Expected SharedObject = - compileSharedObject(std::string(SafeModuleBC.str())); + compileSharedObject(std::string(SafeModuleBC)); if (Error E = SharedObject.takeError()) return E; diff --git a/llvm/tools/bugpoint/OptimizerDriver.cpp b/llvm/tools/bugpoint/OptimizerDriver.cpp index f7239f5dc61..ce324594724 100644 --- a/llvm/tools/bugpoint/OptimizerDriver.cpp +++ b/llvm/tools/bugpoint/OptimizerDriver.cpp @@ -141,7 +141,7 @@ bool BugDriver::runPasses(Module &Program, << ": Error making unique filename: " << EC.message() << "\n"; return true; } - OutputFilename = std::string(UniqueFilename.str()); + OutputFilename = std::string(UniqueFilename); // set up the input file name Expected Temp = diff --git a/llvm/tools/bugpoint/ToolRunner.cpp b/llvm/tools/bugpoint/ToolRunner.cpp index c6733aecd31..e45c89b746a 100644 --- a/llvm/tools/bugpoint/ToolRunner.cpp +++ b/llvm/tools/bugpoint/ToolRunner.cpp @@ -442,7 +442,7 @@ Expected LLC::OutputCode(const std::string &Bitcode, errs() << "Error making unique filename: " << EC.message() << "\n"; exit(1); } - OutputAsmFile = std::string(UniqueFile.str()); + OutputAsmFile = std::string(UniqueFile); std::vector LLCArgs; LLCArgs.push_back(LLCPath); @@ -772,7 +772,7 @@ Error CC::MakeSharedObject(const std::string &InputFile, FileType fileType, errs() << "Error making unique filename: " << EC.message() << "\n"; exit(1); } - OutputFile = std::string(UniqueFilename.str()); + OutputFile = std::string(UniqueFilename); std::vector CCArgs; diff --git a/llvm/tools/llc/NewPMDriver.cpp b/llvm/tools/llc/NewPMDriver.cpp new file mode 100644 index 00000000000..13020f3dd07 --- /dev/null +++ b/llvm/tools/llc/NewPMDriver.cpp @@ -0,0 +1,236 @@ +//===- NewPMDriver.cpp - Driver for llc using new PM ----------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// +/// \file +/// +/// This file is just a split of the code that logically belongs in llc.cpp but +/// that includes the new pass manager headers. +/// +//===----------------------------------------------------------------------===// + +#include "NewPMDriver.h" +#include "llvm/Analysis/CGSCCPassManager.h" +#include "llvm/Analysis/TargetLibraryInfo.h" +#include "llvm/CodeGen/CodeGenPassBuilder.h" +#include "llvm/CodeGen/CommandFlags.h" +#include "llvm/CodeGen/MIRParser/MIRParser.h" +#include "llvm/CodeGen/MIRPrinter.h" +#include "llvm/CodeGen/MachineModuleInfo.h" +#include "llvm/CodeGen/MachinePassManager.h" +#include "llvm/CodeGen/TargetPassConfig.h" +#include "llvm/IR/DiagnosticInfo.h" +#include "llvm/IR/DiagnosticPrinter.h" +#include "llvm/IR/IRPrintingPasses.h" +#include "llvm/IR/LLVMContext.h" +#include "llvm/IR/Module.h" +#include "llvm/IR/PassManager.h" +#include "llvm/IR/Verifier.h" +#include "llvm/IRReader/IRReader.h" +#include "llvm/Passes/PassBuilder.h" +#include "llvm/Passes/StandardInstrumentations.h" +#include "llvm/Support/CommandLine.h" +#include "llvm/Support/Debug.h" +#include "llvm/Support/Error.h" +#include "llvm/Support/ErrorHandling.h" +#include "llvm/Support/FormattedStream.h" +#include "llvm/Support/ToolOutputFile.h" +#include "llvm/Support/WithColor.h" +#include "llvm/Target/CGPassBuilderOption.h" +#include "llvm/Target/TargetMachine.h" +#include "llvm/Target/TargetOptions.h" +#include "llvm/Transforms/Scalar/LoopPassManager.h" +#include "llvm/Transforms/Utils/Cloning.h" + +namespace llvm { +extern cl::opt PrintPipelinePasses; +} // namespace llvm + +using namespace llvm; + +static cl::opt + RegAlloc("regalloc-npm", + cl::desc("Register allocator to use for new pass manager"), + cl::Hidden, cl::init("default")); + +static cl::opt + DebugPM("debug-pass-manager", cl::Hidden, + cl::desc("Print pass management debugging information")); + +bool LLCDiagnosticHandler::handleDiagnostics(const DiagnosticInfo &DI) { + DiagnosticHandler::handleDiagnostics(DI); + if (DI.getKind() == llvm::DK_SrcMgr) { + const auto &DISM = cast(DI); + const SMDiagnostic &SMD = DISM.getSMDiag(); + + SMD.print(nullptr, errs()); + + // For testing purposes, we print the LocCookie here. + if (DISM.isInlineAsmDiag() && DISM.getLocCookie()) + WithColor::note() << "!srcloc = " << DISM.getLocCookie() << "\n"; + + return true; + } + + if (auto *Remark = dyn_cast(&DI)) + if (!Remark->isEnabled()) + return true; + + DiagnosticPrinterRawOStream DP(errs()); + errs() << LLVMContext::getDiagnosticMessagePrefix(DI.getSeverity()) << ": "; + DI.print(DP); + errs() << "\n"; + return true; +} + +static llvm::ExitOnError ExitOnErr; + +static void RunPasses(bool BOS, ToolOutputFile *Out, Module *M, + LLVMContext &Context, SmallString<0> &Buffer, + ModulePassManager *MPM, ModuleAnalysisManager *MAM, + MachineFunctionPassManager &MFPM, + MachineFunctionAnalysisManager &MFAM) { + assert(M && "invalid input module!"); + + // Before executing passes, print the final values of the LLVM options. + cl::PrintOptionValues(); + + if (MPM) { + assert(MAM && "expect a ModuleAnalysisManager!"); + MPM->run(*M, *MAM); + } + + ExitOnErr(MFPM.run(*M, MFAM)); + + if (Context.getDiagHandlerPtr()->HasErrors) + exit(1); + + if (BOS) + Out->os() << Buffer; +} + +int llvm::compileModuleWithNewPM( + StringRef Arg0, std::unique_ptr M, std::unique_ptr MIR, + std::unique_ptr Target, std::unique_ptr Out, + std::unique_ptr DwoOut, LLVMContext &Context, + const TargetLibraryInfoImpl &TLII, bool NoVerify, StringRef PassPipeline, + CodeGenFileType FileType) { + + if (!PassPipeline.empty() && TargetPassConfig::hasLimitedCodeGenPipeline()) { + WithColor::warning(errs(), Arg0) + << "--passes cannot be used with " + << TargetPassConfig::getLimitedCodeGenPipelineReason() << ".\n"; + return 1; + } + + LLVMTargetMachine &LLVMTM = static_cast(*Target); + + raw_pwrite_stream *OS = &Out->os(); + + // Manually do the buffering rather than using buffer_ostream, + // so we can memcmp the contents in CompileTwice mode in future. + SmallString<0> Buffer; + std::unique_ptr BOS; + if ((codegen::getFileType() != CodeGenFileType::AssemblyFile && + !Out->os().supportsSeeking())) { + BOS = std::make_unique(Buffer); + OS = BOS.get(); + } + + // Fetch options from TargetPassConfig + CGPassBuilderOption Opt = getCGPassBuilderOption(); + Opt.DisableVerify = NoVerify; + Opt.DebugPM = DebugPM; + Opt.RegAlloc = RegAlloc; + + PassInstrumentationCallbacks PIC; + StandardInstrumentations SI(Context, Opt.DebugPM); + SI.registerCallbacks(PIC); + registerCodeGenCallback(PIC, LLVMTM); + + LoopAnalysisManager LAM; + FunctionAnalysisManager FAM; + CGSCCAnalysisManager CGAM; + ModuleAnalysisManager MAM; + PassBuilder PB(Target.get(), PipelineTuningOptions(), std::nullopt, &PIC); + PB.registerModuleAnalyses(MAM); + PB.registerCGSCCAnalyses(CGAM); + PB.registerFunctionAnalyses(FAM); + PB.registerLoopAnalyses(LAM); + PB.crossRegisterProxies(LAM, FAM, CGAM, MAM); + + FAM.registerPass([&] { return TargetLibraryAnalysis(TLII); }); + MAM.registerPass([&] { return MachineModuleAnalysis(&LLVMTM); }); + + MachineFunctionAnalysisManager MFAM(FAM, MAM); + + if (!PassPipeline.empty()) { + // Construct a custom pass pipeline that starts after instruction + // selection. + + if (!MIR) { + WithColor::warning(errs(), Arg0) << "-passes is for .mir file only.\n"; + return 1; + } + + MachineFunctionPassManager MFPM; + ExitOnErr(PB.parsePassPipeline(MFPM, PassPipeline)); + MFPM.addPass(PrintMIRPass(*OS)); + MFPM.addPass(FreeMachineFunctionPass()); + + auto &MMI = MFAM.getResult(*M); + if (MIR->parseMachineFunctions(*M, MMI)) + return 1; + + RunPasses(BOS.get(), Out.get(), M.get(), Context, Buffer, nullptr, nullptr, + MFPM, MFAM); + } else { + ModulePassManager MPM; + MachineFunctionPassManager MFPM; + + ExitOnErr(LLVMTM.buildCodeGenPipeline(MPM, MFPM, MFAM, *OS, + DwoOut ? &DwoOut->os() : nullptr, + FileType, Opt, &PIC)); + + auto StartStopInfo = TargetPassConfig::getStartStopInfo(PIC); + assert(StartStopInfo && "Expect StartStopInfo!"); + // Add IR or MIR printing pass according the pass type. + + if (auto StopPassName = StartStopInfo->StopPass; !StopPassName.empty()) { + MFPM.addPass(PrintMIRPass(*OS)); + MFPM.addPass(FreeMachineFunctionPass()); + } + + if (PrintPipelinePasses) { + std::string IRPipeline; + raw_string_ostream IRSOS(IRPipeline); + MPM.printPipeline(IRSOS, [&PIC](StringRef ClassName) { + auto PassName = PIC.getPassNameForClassName(ClassName); + return PassName.empty() ? ClassName : PassName; + }); + outs() << "IR pipeline: " << IRPipeline << '\n'; + + std::string MIRPipeline; + raw_string_ostream MIRSOS(MIRPipeline); + MFPM.printPipeline(MIRSOS, [&PIC](StringRef ClassName) { + auto PassName = PIC.getPassNameForClassName(ClassName); + return PassName.empty() ? ClassName : PassName; + }); + outs() << "MIR pipeline: " << MIRPipeline << '\n'; + return 0; + } + + RunPasses(BOS.get(), Out.get(), M.get(), Context, Buffer, &MPM, &MAM, MFPM, + MFAM); + } + + // Declare success. + Out->keep(); + if (DwoOut) + DwoOut->keep(); + + return 0; +} diff --git a/llvm/tools/llc/NewPMDriver.h b/llvm/tools/llc/NewPMDriver.h new file mode 100644 index 00000000000..b0beeaf596c --- /dev/null +++ b/llvm/tools/llc/NewPMDriver.h @@ -0,0 +1,49 @@ +//===- NewPMDriver.h - Function to drive llc with the new PM ----*- C++ -*-===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// +/// \file +/// +/// A single function which is called to drive the llc behavior for the new +/// PassManager. +/// +/// This is only in a separate TU with a header to avoid including all of the +/// old pass manager headers and the new pass manager headers into the same +/// file. Eventually all of the routines here will get folded back into +/// llc.cpp. +/// +//===----------------------------------------------------------------------===// +#ifndef LLVM_TOOLS_LLC_NEWPMDRIVER_H +#define LLVM_TOOLS_LLC_NEWPMDRIVER_H + +#include "llvm/IR/DiagnosticHandler.h" +#include "llvm/Support/CodeGen.h" +#include +#include + +namespace llvm { +class Module; +class TargetLibraryInfoImpl; +class TargetMachine; +class ToolOutputFile; +class LLVMContext; +class MIRParser; + +struct LLCDiagnosticHandler : public DiagnosticHandler { + bool handleDiagnostics(const DiagnosticInfo &DI) override; +}; + +int compileModuleWithNewPM(StringRef Arg0, std::unique_ptr M, + std::unique_ptr MIR, + std::unique_ptr Target, + std::unique_ptr Out, + std::unique_ptr DwoOut, + LLVMContext &Context, + const TargetLibraryInfoImpl &TLII, bool NoVerify, + StringRef PassPipeline, CodeGenFileType FileType); +} // namespace llvm + +#endif diff --git a/llvm/tools/llc/llc.cpp b/llvm/tools/llc/llc.cpp index 4a1957588a2..3e2567c441d 100644 --- a/llvm/tools/llc/llc.cpp +++ b/llvm/tools/llc/llc.cpp @@ -7,11 +7,12 @@ //===----------------------------------------------------------------------===// // // This is the llc code generator driver. It provides a convenient -// command-line interface for generating native assembly-language code -// or C code, given LLVM bitcode. +// command-line interface for generating an assembly file or a relocatable file, +// given LLVM bitcode. // //===----------------------------------------------------------------------===// +#include "NewPMDriver.h" #include "llvm/ADT/STLExtras.h" #include "llvm/ADT/ScopeExit.h" #include "llvm/Analysis/TargetLibraryInfo.h" @@ -186,10 +187,25 @@ static cl::opt RemarksFormat( cl::desc("The format used for serializing remarks (default: YAML)"), cl::value_desc("format"), cl::init("yaml")); +static cl::opt EnableNewPassManager( + "enable-new-pm", cl::desc("Enable the new pass manager"), cl::init(false)); + +// This flag specifies a textual description of the optimization pass pipeline +// to run over the module. This flag switches opt to use the new pass manager +// infrastructure, completely disabling all of the flags specific to the old +// pass management. +static cl::opt PassPipeline( + "passes", + cl::desc( + "A textual description of the pass pipeline. To have analysis passes " + "available before a certain pass, add 'require'.")); +static cl::alias PassPipeline2("p", cl::aliasopt(PassPipeline), + cl::desc("Alias for -passes")); + static cl::opt TryUseNewDbgInfoFormat( "try-experimental-debuginfo-iterators", cl::desc("Enable debuginfo iterator positions, if they're built in"), - cl::init(false)); + cl::init(false), cl::Hidden); extern cl::opt UseNewDbgInfoFormat; @@ -258,15 +274,7 @@ static std::unique_ptr GetOutputStream(const char *TargetName, switch (codegen::getFileType()) { case CodeGenFileType::AssemblyFile: - if (TargetName[0] == 'c') { - if (TargetName[1] == 0) - OutputFilename += ".cbe.c"; - else if (TargetName[1] == 'p' && TargetName[2] == 'p') - OutputFilename += ".cpp"; - else - OutputFilename += ".s"; - } else - OutputFilename += ".s"; + OutputFilename += ".s"; break; case CodeGenFileType::ObjectFile: if (OS == Triple::Win32) @@ -306,34 +314,6 @@ static std::unique_ptr GetOutputStream(const char *TargetName, return FDOut; } -struct LLCDiagnosticHandler : public DiagnosticHandler { - bool handleDiagnostics(const DiagnosticInfo &DI) override { - DiagnosticHandler::handleDiagnostics(DI); - if (DI.getKind() == llvm::DK_SrcMgr) { - const auto &DISM = cast(DI); - const SMDiagnostic &SMD = DISM.getSMDiag(); - - SMD.print(nullptr, errs()); - - // For testing purposes, we print the LocCookie here. - if (DISM.isInlineAsmDiag() && DISM.getLocCookie()) - WithColor::note() << "!srcloc = " << DISM.getLocCookie() << "\n"; - - return true; - } - - if (auto *Remark = dyn_cast(&DI)) - if (!Remark->isEnabled()) - return true; - - DiagnosticPrinterRawOStream DP(errs()); - errs() << LLVMContext::getDiagnosticMessagePrefix(DI.getSeverity()) << ": "; - DI.print(DP); - errs() << "\n"; - return true; - } -}; - // main - Entry point for the llc compiler. // int main(int argc, char **argv) { @@ -377,6 +357,13 @@ int main(int argc, char **argv) { cl::ParseCommandLineOptions(argc, argv, "llvm system compiler\n"); + if (!PassPipeline.empty() && !getRunPassNames().empty()) { + errs() << "The `llc -run-pass=...` syntax for the new pass manager is " + "not supported, please use `llc -passes=` (or the `-p` " + "alias for a more concise version).\n"; + return 1; + } + // RemoveDIs debug-info transition: tests may request that we /try/ to use the // new debug-info format, if it's built in. #ifdef EXPERIMENTAL_DEBUGINFO_ITERATORS @@ -642,16 +629,12 @@ static int compileModule(char **argv, LLVMContext &Context) { reportError(EC.message(), SplitDwarfOutputFile); } - // Build up all of the passes that we want to do to the module. - legacy::PassManager PM; - // Add an appropriate TargetLibraryInfo pass for the module's triple. TargetLibraryInfoImpl TLII(Triple(M->getTargetTriple())); // The -disable-simplify-libcalls flag actually disables all builtin optzns. if (DisableSimplifyLibCalls) TLII.disableAllFunctions(); - PM.add(new TargetLibraryInfoWrapperPass(TLII)); // Verify module immediately to catch problems before doInitialization() is // called on any passes. @@ -667,6 +650,17 @@ static int compileModule(char **argv, LLVMContext &Context) { WithColor::warning(errs(), argv[0]) << ": warning: ignoring -mc-relax-all because filetype != obj"; + if (EnableNewPassManager || !PassPipeline.empty()) { + return compileModuleWithNewPM(argv[0], std::move(M), std::move(MIR), + std::move(Target), std::move(Out), + std::move(DwoOut), Context, TLII, NoVerify, + PassPipeline, codegen::getFileType()); + } + + // Build up all of the passes that we want to do to the module. + legacy::PassManager PM; + PM.add(new TargetLibraryInfoWrapperPass(TLII)); + { raw_pwrite_stream *OS = &Out->os(); @@ -700,7 +694,7 @@ static int compileModule(char **argv, LLVMContext &Context) { if (TPC.hasLimitedCodeGenPipeline()) { WithColor::warning(errs(), argv[0]) << "run-pass cannot be used with " - << TPC.getLimitedCodeGenPipelineReason(" and ") << ".\n"; + << TPC.getLimitedCodeGenPipelineReason() << ".\n"; delete PTPC; delete MMIWP; return 1; diff --git a/llvm/tools/lli/ExecutionUtils.cpp b/llvm/tools/lli/ExecutionUtils.cpp deleted file mode 100644 index b6cc3bb174d..00000000000 --- a/llvm/tools/lli/ExecutionUtils.cpp +++ /dev/null @@ -1,122 +0,0 @@ -//===---- ExecutionUtils.cpp - Utilities for executing functions in lli ---===// -// -// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. -// See https://llvm.org/LICENSE.txt for license information. -// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception -// -//===----------------------------------------------------------------------===// - -#include "ExecutionUtils.h" - -#include "llvm/ExecutionEngine/Orc/TargetProcess/JITLoaderGDB.h" -#include "llvm/Support/FileSystem.h" -#include "llvm/Support/FormatVariadic.h" -#include "llvm/Support/raw_ostream.h" - -#include -#include - -namespace llvm { - -template static void outsv(const char *Fmt, Ts &&...Vals) { - outs() << formatv(Fmt, Vals...); -} - -static const char *actionFlagToStr(uint32_t ActionFlag) { - switch (ActionFlag) { - case JIT_NOACTION: - return "JIT_NOACTION"; - case JIT_REGISTER_FN: - return "JIT_REGISTER_FN"; - case JIT_UNREGISTER_FN: - return "JIT_UNREGISTER_FN"; - } - return ""; -} - -// Declarations follow the GDB JIT interface (version 1, 2009) and must match -// those of the DYLD used for testing. -// -// Sample output: -// -// Reading __jit_debug_descriptor at 0x0000000000404048 -// -// Version: 0 -// Action: JIT_REGISTER_FN -// -// Entry Symbol File Size Previous Entry -// [ 0] 0x0000000000451290 0x0000000000002000 200 0x0000000000000000 -// [ 1] 0x0000000000451260 0x0000000000001000 100 0x0000000000451290 -// ... -// -static void dumpDebugDescriptor(void *Addr) { - outsv("Reading __jit_debug_descriptor at {0}\n\n", Addr); - - jit_descriptor *Descriptor = reinterpret_cast(Addr); - outsv("Version: {0}\n", Descriptor->version); - outsv("Action: {0}\n\n", actionFlagToStr(Descriptor->action_flag)); - outsv("{0,11} {1,24} {2,15} {3,14}\n", "Entry", "Symbol File", "Size", - "Previous Entry"); - - unsigned Idx = 0; - for (auto *Entry = Descriptor->first_entry; Entry; Entry = Entry->next_entry) - outsv("[{0,2}] {1:X16} {2:X16} {3,8:D} {4}\n", Idx++, Entry, - reinterpret_cast(Entry->symfile_addr), - Entry->symfile_size, Entry->prev_entry); -} - -static LLIBuiltinFunctionGenerator *Generator = nullptr; - -static void dumpDebugObjects(void *Addr) { - jit_descriptor *Descriptor = reinterpret_cast(Addr); - for (auto *Entry = Descriptor->first_entry; Entry; Entry = Entry->next_entry) - Generator->appendDebugObject(Entry->symfile_addr, Entry->symfile_size); -} - -LLIBuiltinFunctionGenerator::LLIBuiltinFunctionGenerator( - std::vector Enabled, orc::MangleAndInterner &Mangle) - : TestOut(nullptr) { - Generator = this; - for (BuiltinFunctionKind F : Enabled) { - switch (F) { - case BuiltinFunctionKind::DumpDebugDescriptor: - expose(Mangle("__dump_jit_debug_descriptor"), &dumpDebugDescriptor); - break; - case BuiltinFunctionKind::DumpDebugObjects: - expose(Mangle("__dump_jit_debug_objects"), &dumpDebugObjects); - TestOut = createToolOutput(); - break; - } - } -} - -Error LLIBuiltinFunctionGenerator::tryToGenerate( - orc::LookupState &LS, orc::LookupKind K, orc::JITDylib &JD, - orc::JITDylibLookupFlags JDLookupFlags, - const orc::SymbolLookupSet &Symbols) { - orc::SymbolMap NewSymbols; - for (const auto &NameFlags : Symbols) { - auto It = BuiltinFunctions.find(NameFlags.first); - if (It != BuiltinFunctions.end()) - NewSymbols.insert(*It); - } - - if (NewSymbols.empty()) - return Error::success(); - - return JD.define(absoluteSymbols(std::move(NewSymbols))); -} - -// static -std::unique_ptr -LLIBuiltinFunctionGenerator::createToolOutput() { - std::error_code EC; - auto TestOut = std::make_unique("-", EC, sys::fs::OF_None); - if (EC) { - errs() << "Error creating tool output file: " << EC.message() << '\n'; - exit(1); - } - return TestOut; -} - -} // namespace llvm diff --git a/llvm/tools/lli/ExecutionUtils.h b/llvm/tools/lli/ExecutionUtils.h deleted file mode 100644 index 6bf9cd58e03..00000000000 --- a/llvm/tools/lli/ExecutionUtils.h +++ /dev/null @@ -1,60 +0,0 @@ -//===- ExecutionUtils.h - Utilities for executing code in lli ---*- C++ -*-===// -// -// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. -// See https://llvm.org/LICENSE.txt for license information. -// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception -// -//===----------------------------------------------------------------------===// -// -// Contains utilities for executing code in lli. -// -//===----------------------------------------------------------------------===// - -#ifndef LLVM_TOOLS_LLI_EXECUTIONUTILS_H -#define LLVM_TOOLS_LLI_EXECUTIONUTILS_H - -#include "llvm/ExecutionEngine/JITSymbol.h" -#include "llvm/ExecutionEngine/Orc/Core.h" -#include "llvm/ExecutionEngine/Orc/Mangling.h" -#include "llvm/Support/Error.h" -#include "llvm/Support/ToolOutputFile.h" - -#include -#include - -namespace llvm { - -enum class BuiltinFunctionKind { - DumpDebugDescriptor, - DumpDebugObjects, -}; - -// Utility class to expose symbols for special-purpose functions to the JIT. -class LLIBuiltinFunctionGenerator : public orc::DefinitionGenerator { -public: - LLIBuiltinFunctionGenerator(std::vector Enabled, - orc::MangleAndInterner &Mangle); - - Error tryToGenerate(orc::LookupState &LS, orc::LookupKind K, - orc::JITDylib &JD, orc::JITDylibLookupFlags JDLookupFlags, - const orc::SymbolLookupSet &Symbols) override; - - void appendDebugObject(const char *Addr, size_t Size) { - TestOut->os().write(Addr, Size); - } - -private: - orc::SymbolMap BuiltinFunctions; - std::unique_ptr TestOut; - - template void expose(orc::SymbolStringPtr Name, T *Handler) { - BuiltinFunctions[Name] = {orc::ExecutorAddr::fromPtr(Handler), - JITSymbolFlags::Exported}; - } - - static std::unique_ptr createToolOutput(); -}; - -} // end namespace llvm - -#endif // LLVM_TOOLS_LLI_EXECUTIONUTILS_H diff --git a/llvm/tools/lli/lli.cpp b/llvm/tools/lli/lli.cpp index 8a7ea2d3d0c..905ec23de45 100644 --- a/llvm/tools/lli/lli.cpp +++ b/llvm/tools/lli/lli.cpp @@ -12,7 +12,6 @@ // //===----------------------------------------------------------------------===// -#include "ExecutionUtils.h" #include "ForwardingMemoryManager.h" #include "llvm/ADT/StringExtras.h" #include "llvm/Bitcode/BitcodeReader.h" @@ -33,6 +32,7 @@ #include "llvm/ExecutionEngine/Orc/ExecutionUtils.h" #include "llvm/ExecutionEngine/Orc/JITTargetMachineBuilder.h" #include "llvm/ExecutionEngine/Orc/LLJIT.h" +#include "llvm/ExecutionEngine/Orc/ObjectTransformLayer.h" #include "llvm/ExecutionEngine/Orc/RTDyldObjectLinkingLayer.h" #include "llvm/ExecutionEngine/Orc/SimpleRemoteEPC.h" #include "llvm/ExecutionEngine/Orc/SymbolStringPool.h" @@ -62,6 +62,7 @@ #include "llvm/Support/Program.h" #include "llvm/Support/SourceMgr.h" #include "llvm/Support/TargetSelect.h" +#include "llvm/Support/ToolOutputFile.h" #include "llvm/Support/WithColor.h" #include "llvm/Support/raw_ostream.h" #include "llvm/TargetParser/Triple.h" @@ -254,35 +255,29 @@ namespace { NoDump, DumpFuncsToStdOut, DumpModsToStdOut, - DumpModsToDisk + DumpModsToDisk, + DumpDebugDescriptor, + DumpDebugObjects, }; cl::opt OrcDumpKind( "orc-lazy-debug", cl::desc("Debug dumping for the orc-lazy JIT."), cl::init(DumpKind::NoDump), - cl::values(clEnumValN(DumpKind::NoDump, "no-dump", - "Don't dump anything."), - clEnumValN(DumpKind::DumpFuncsToStdOut, "funcs-to-stdout", - "Dump function names to stdout."), - clEnumValN(DumpKind::DumpModsToStdOut, "mods-to-stdout", - "Dump modules to stdout."), - clEnumValN(DumpKind::DumpModsToDisk, "mods-to-disk", - "Dump modules to the current " - "working directory. (WARNING: " - "will overwrite existing files).")), - cl::Hidden); - - cl::list GenerateBuiltinFunctions( - "generate", - cl::desc("Provide built-in functions for access by JITed code " - "(jit-kind=orc-lazy only)"), - cl::values(clEnumValN(BuiltinFunctionKind::DumpDebugDescriptor, - "__dump_jit_debug_descriptor", - "Dump __jit_debug_descriptor contents to stdout"), - clEnumValN(BuiltinFunctionKind::DumpDebugObjects, - "__dump_jit_debug_objects", - "Dump __jit_debug_descriptor in-memory debug " - "objects as tool output")), + cl::values( + clEnumValN(DumpKind::NoDump, "no-dump", "Don't dump anything."), + clEnumValN(DumpKind::DumpFuncsToStdOut, "funcs-to-stdout", + "Dump function names to stdout."), + clEnumValN(DumpKind::DumpModsToStdOut, "mods-to-stdout", + "Dump modules to stdout."), + clEnumValN(DumpKind::DumpModsToDisk, "mods-to-disk", + "Dump modules to the current " + "working directory. (WARNING: " + "will overwrite existing files)."), + clEnumValN(DumpKind::DumpDebugDescriptor, "jit-debug-descriptor", + "Dump __jit_debug_descriptor contents to stdout"), + clEnumValN(DumpKind::DumpDebugObjects, "jit-debug-objects", + "Dump __jit_debug_descriptor in-memory debug " + "objects as tool output")), cl::Hidden); ExitOnError ExitOnErr; @@ -756,9 +751,41 @@ int main(int argc, char **argv, char * const *envp) { return Result; } -static std::function createDebugDumper() { +// JITLink debug support plugins put information about JITed code in this GDB +// JIT Interface global from OrcTargetProcess. +extern "C" struct jit_descriptor __jit_debug_descriptor; + +static struct jit_code_entry * +findNextDebugDescriptorEntry(struct jit_code_entry *Latest) { + if (Latest == nullptr) + return __jit_debug_descriptor.first_entry; + if (Latest->next_entry) + return Latest->next_entry; + return nullptr; +} + +static ToolOutputFile &claimToolOutput() { + static std::unique_ptr ToolOutput = nullptr; + if (ToolOutput) { + WithColor::error(errs(), "lli") + << "Can not claim stdout for tool output twice\n"; + exit(1); + } + std::error_code EC; + ToolOutput = std::make_unique("-", EC, sys::fs::OF_None); + if (EC) { + WithColor::error(errs(), "lli") + << "Failed to create tool output file: " << EC.message() << "\n"; + exit(1); + } + return *ToolOutput; +} + +static std::function createIRDebugDumper() { switch (OrcDumpKind) { case DumpKind::NoDump: + case DumpKind::DumpDebugDescriptor: + case DumpKind::DumpDebugObjects: return [](Module &M) {}; case DumpKind::DumpFuncsToStdOut: @@ -800,6 +827,43 @@ static std::function createDebugDumper() { llvm_unreachable("Unknown DumpKind"); } +static std::function createObjDebugDumper() { + switch (OrcDumpKind) { + case DumpKind::NoDump: + case DumpKind::DumpFuncsToStdOut: + case DumpKind::DumpModsToStdOut: + case DumpKind::DumpModsToDisk: + return [](MemoryBuffer &) {}; + + case DumpKind::DumpDebugDescriptor: { + // Dump the empty descriptor at startup once + fprintf(stderr, "jit_debug_descriptor 0x%016" PRIx64 "\n", + pointerToJITTargetAddress(__jit_debug_descriptor.first_entry)); + return [](MemoryBuffer &) { + // Dump new entries as they appear + static struct jit_code_entry *Latest = nullptr; + while (auto *NewEntry = findNextDebugDescriptorEntry(Latest)) { + fprintf(stderr, "jit_debug_descriptor 0x%016" PRIx64 "\n", + pointerToJITTargetAddress(NewEntry)); + Latest = NewEntry; + } + }; + } + + case DumpKind::DumpDebugObjects: { + return [](MemoryBuffer &Obj) { + static struct jit_code_entry *Latest = nullptr; + static ToolOutputFile &ToolOutput = claimToolOutput(); + while (auto *NewEntry = findNextDebugDescriptorEntry(Latest)) { + ToolOutput.os().write(NewEntry->symfile_addr, NewEntry->symfile_size); + Latest = NewEntry; + } + }; + } + } + llvm_unreachable("Unknown DumpKind"); +} + Error loadDylibs() { for (const auto &Dylib : Dylibs) { std::string ErrMsg; @@ -1001,8 +1065,7 @@ int runOrcJIT(const char *ProgName) { if (PerModuleLazy) J->setPartitionFunction(orc::CompileOnDemandLayer::compileWholeModule); - auto Dump = createDebugDumper(); - + auto IRDump = createIRDebugDumper(); J->getIRTransformLayer().setTransform( [&](orc::ThreadSafeModule TSM, const orc::MaterializationResponsibility &R) { @@ -1011,18 +1074,18 @@ int runOrcJIT(const char *ProgName) { dbgs() << "Bad module: " << &M << "\n"; exit(1); } - Dump(M); + IRDump(M); }); return TSM; }); - if (GenerateBuiltinFunctions.size() > 0) { - // Add LLI builtins. - orc::MangleAndInterner Mangle(J->getExecutionSession(), J->getDataLayout()); - J->getMainJITDylib().addGenerator( - std::make_unique(GenerateBuiltinFunctions, - Mangle)); - } + auto ObjDump = createObjDebugDumper(); + J->getObjTransformLayer().setTransform( + [&](std::unique_ptr Obj) + -> Expected> { + ObjDump(*Obj); + return std::move(Obj); + }); // If this is a Mingw or Cygwin executor then we need to alias __main to // orc_rt_int_void_return_0. diff --git a/llvm/tools/llvm-ar/llvm-ar.cpp b/llvm/tools/llvm-ar/llvm-ar.cpp index 299b7856ec0..c8800303bc1 100644 --- a/llvm/tools/llvm-ar/llvm-ar.cpp +++ b/llvm/tools/llvm-ar/llvm-ar.cpp @@ -25,7 +25,6 @@ #include "llvm/Support/FileSystem.h" #include "llvm/Support/Format.h" #include "llvm/Support/FormatVariadic.h" -#include "llvm/Support/InitLLVM.h" #include "llvm/Support/LLVMDriver.h" #include "llvm/Support/LineIterator.h" #include "llvm/Support/MemoryBuffer.h" @@ -1500,7 +1499,6 @@ static int ranlib_main(int argc, char **argv) { } int llvm_ar_main(int argc, char **argv, const llvm::ToolContext &) { - InitLLVM X(argc, argv); ToolName = argv[0]; llvm::InitializeAllTargetInfos(); diff --git a/llvm/tools/llvm-cov/SourceCoverageView.cpp b/llvm/tools/llvm-cov/SourceCoverageView.cpp index c910edd1db7..71edd5fec42 100644 --- a/llvm/tools/llvm-cov/SourceCoverageView.cpp +++ b/llvm/tools/llvm-cov/SourceCoverageView.cpp @@ -48,7 +48,7 @@ std::string CoveragePrinter::getOutputPath(StringRef Path, StringRef Extension, sys::path::append(FullPath, PathFilename); sys::path::native(FullPath); - return std::string(FullPath.str()); + return std::string(FullPath); } Expected @@ -130,6 +130,8 @@ bool SourceCoverageView::shouldRenderRegionMarkers( const auto *CurSeg = Segments[I]; if (!CurSeg->IsRegionEntry || CurSeg->Count == LCS.getExecutionCount()) continue; + if (!CurSeg->HasCount) // don't show tooltips for SkippedRegions + continue; return true; } return false; @@ -163,7 +165,7 @@ std::string SourceCoverageView::getSourceName() const { SmallString<128> SourceText(SourceName); sys::path::remove_dots(SourceText, /*remove_dot_dot=*/true); sys::path::native(SourceText); - return std::string(SourceText.str()); + return std::string(SourceText); } void SourceCoverageView::addExpansion( diff --git a/llvm/tools/llvm-cov/gcov.cpp b/llvm/tools/llvm-cov/gcov.cpp index 9a1ebebc87f..00ea12415b2 100644 --- a/llvm/tools/llvm-cov/gcov.cpp +++ b/llvm/tools/llvm-cov/gcov.cpp @@ -35,12 +35,10 @@ static void reportCoverage(StringRef SourceFile, StringRef ObjectDir, // A file was given. Ignore the source file and look next to this file. sys::path::replace_extension(CoverageFileStem, ""); - std::string GCNO = InputGCNO.empty() - ? std::string(CoverageFileStem.str()) + ".gcno" - : InputGCNO; - std::string GCDA = InputGCDA.empty() - ? std::string(CoverageFileStem.str()) + ".gcda" - : InputGCDA; + std::string GCNO = + InputGCNO.empty() ? std::string(CoverageFileStem) + ".gcno" : InputGCNO; + std::string GCDA = + InputGCDA.empty() ? std::string(CoverageFileStem) + ".gcda" : InputGCDA; GCOVFile GF; // Open .gcda and .gcda without requiring a NUL terminator. The concurrent diff --git a/llvm/tools/llvm-cxxfilt/llvm-cxxfilt.cpp b/llvm/tools/llvm-cxxfilt/llvm-cxxfilt.cpp index 26a1f2f4afe..d63f507619a 100644 --- a/llvm/tools/llvm-cxxfilt/llvm-cxxfilt.cpp +++ b/llvm/tools/llvm-cxxfilt/llvm-cxxfilt.cpp @@ -13,7 +13,6 @@ #include "llvm/Option/ArgList.h" #include "llvm/Option/Option.h" #include "llvm/Support/CommandLine.h" -#include "llvm/Support/InitLLVM.h" #include "llvm/Support/LLVMDriver.h" #include "llvm/Support/WithColor.h" #include "llvm/Support/raw_ostream.h" @@ -146,7 +145,6 @@ static void demangleLine(llvm::raw_ostream &OS, StringRef Mangled, bool Split) { } int llvm_cxxfilt_main(int argc, char **argv, const llvm::ToolContext &) { - InitLLVM X(argc, argv); BumpPtrAllocator A; StringSaver Saver(A); CxxfiltOptTable Tbl; diff --git a/llvm/tools/llvm-diff/lib/DifferenceEngine.cpp b/llvm/tools/llvm-diff/lib/DifferenceEngine.cpp index 0d4d82e5cad..64b5051af14 100644 --- a/llvm/tools/llvm-diff/lib/DifferenceEngine.cpp +++ b/llvm/tools/llvm-diff/lib/DifferenceEngine.cpp @@ -214,11 +214,9 @@ class FunctionDifferenceEngine { }; unsigned getUnprocPredCount(const BasicBlock *Block) const { - unsigned Count = 0; - for (const_pred_iterator I = pred_begin(Block), E = pred_end(Block); I != E; - ++I) - if (!Blocks.count(*I)) Count++; - return Count; + return llvm::count_if(predecessors(Block), [&](const BasicBlock *Pred) { + return !Blocks.contains(Pred); + }); } typedef std::pair BlockPair; diff --git a/llvm/tools/llvm-dwarfdump/llvm-dwarfdump.cpp b/llvm/tools/llvm-dwarfdump/llvm-dwarfdump.cpp index 8180ad2138f..941df4eb184 100644 --- a/llvm/tools/llvm-dwarfdump/llvm-dwarfdump.cpp +++ b/llvm/tools/llvm-dwarfdump/llvm-dwarfdump.cpp @@ -181,6 +181,13 @@ static opt FindAllApple( static opt IgnoreCase("ignore-case", desc("Ignore case distinctions when using --name."), value_desc("i"), cat(DwarfDumpCategory)); +static opt DumpNonSkeleton( + "dwo", + desc("Dump the non skeleton DIE in the .dwo or .dwp file after dumping the " + "skeleton DIE from the main executable. This allows dumping the .dwo " + "files with resolved addresses."), + value_desc("d"), cat(DwarfDumpCategory)); + static alias IgnoreCaseAlias("i", desc("Alias for --ignore-case."), aliasopt(IgnoreCase), cl::NotHidden); static list Name( @@ -315,6 +322,7 @@ static DIDumpOptions getDumpOpts(DWARFContext &C) { DumpOpts.ShowForm = ShowForm; DumpOpts.SummarizeTypes = SummarizeTypes; DumpOpts.Verbose = Verbose; + DumpOpts.DumpNonSkeleton = DumpNonSkeleton; DumpOpts.RecoverableErrorHandler = C.getRecoverableErrorHandler(); // In -verify mode, print DIEs without children in error messages. if (Verify) { @@ -390,15 +398,27 @@ static void filterByName( const StringSet<> &Names, DWARFContext::unit_iterator_range CUs, raw_ostream &OS, std::function GetNameForDWARFReg) { - for (const auto &CU : CUs) - for (const auto &Entry : CU->dies()) { - DWARFDie Die = {CU.get(), &Entry}; + auto filterDieNames = [&](DWARFUnit *Unit) { + for (const auto &Entry : Unit->dies()) { + DWARFDie Die = {Unit, &Entry}; if (const char *Name = Die.getName(DINameKind::ShortName)) if (filterByName(Names, Die, Name, OS, GetNameForDWARFReg)) continue; if (const char *Name = Die.getName(DINameKind::LinkageName)) filterByName(Names, Die, Name, OS, GetNameForDWARFReg); } + }; + for (const auto &CU : CUs) { + filterDieNames(CU.get()); + if (DumpNonSkeleton) { + // If we have split DWARF, then recurse down into the .dwo files as well. + DWARFDie CUDie = CU->getUnitDIE(false); + DWARFDie CUNonSkeletonDie = CU->getNonSkeletonUnitDIE(false); + // If we have a DWO file, we need to search it as well + if (CUNonSkeletonDie && CUDie != CUNonSkeletonDie) + filterDieNames(CUNonSkeletonDie.getDwarfUnit()); + } + } } static void getDies(DWARFContext &DICtx, const AppleAcceleratorTable &Accel, @@ -499,7 +519,7 @@ static void findAllApple( /// information or probably display all matched entries, or something else... static bool lookup(ObjectFile &Obj, DWARFContext &DICtx, uint64_t Address, raw_ostream &OS) { - auto DIEsForAddr = DICtx.getDIEsForAddress(Lookup); + auto DIEsForAddr = DICtx.getDIEsForAddress(Lookup, DumpNonSkeleton); if (!DIEsForAddr) return false; diff --git a/llvm/tools/llvm-dwarfutil/DebugInfoLinker.cpp b/llvm/tools/llvm-dwarfutil/DebugInfoLinker.cpp index d6504992b56..bd17f3c4a65 100644 --- a/llvm/tools/llvm-dwarfutil/DebugInfoLinker.cpp +++ b/llvm/tools/llvm-dwarfutil/DebugInfoLinker.cpp @@ -80,8 +80,8 @@ public: // should be renamed into has valid address ranges bool hasValidRelocs() override { return HasValidAddressRanges; } - std::optional - getSubprogramRelocAdjustment(const DWARFDie &DIE) override { + std::optional getSubprogramRelocAdjustment(const DWARFDie &DIE, + bool Verbose) override { assert((DIE.getTag() == dwarf::DW_TAG_subprogram || DIE.getTag() == dwarf::DW_TAG_label) && "Wrong type of input die"); @@ -101,7 +101,7 @@ public: std::optional getExprOpAddressRelocAdjustment(DWARFUnit &U, const DWARFExpression::Operation &Op, - uint64_t, uint64_t) override { + uint64_t, uint64_t, bool Verbose) override { switch (Op.getCode()) { default: { assert(false && "Specified operation does not have address operand"); @@ -336,9 +336,26 @@ Error linkDebugInfoImpl(object::ObjectFile &File, const Options &Options, Linker::createLinker(ReportErr, ReportWarn); Triple TargetTriple = File.makeTriple(); - if (Error Err = DebugInfoLinker->createEmitter( - TargetTriple, Linker::OutputFileType::Object, OutStream)) - return Err; + std::unique_ptr Streamer; + if (Expected> StreamerOrErr = + classic::DwarfStreamer::createStreamer( + TargetTriple, Linker::OutputFileType::Object, OutStream, nullptr, + ReportWarn)) + Streamer = std::move(*StreamerOrErr); + else + return StreamerOrErr.takeError(); + + if constexpr (std::is_same::value) { + DebugInfoLinker->setOutputDWARFHandler( + TargetTriple, + [&](std::shared_ptr + Section) { + Streamer->emitSectionContents(Section->getContents(), + Section->getKind()); + }); + } else + DebugInfoLinker->setOutputDWARFEmitter(Streamer.get()); DebugInfoLinker->setEstimatedObjfilesAmount(1); DebugInfoLinker->setNumThreads(Options.NumThreads); @@ -445,13 +462,13 @@ Error linkDebugInfoImpl(object::ObjectFile &File, const Options &Options, if (Error Err = DebugInfoLinker->link()) return Err; - DebugInfoLinker->getEmitter()->finish(); + Streamer->finish(); return Error::success(); } Error linkDebugInfo(object::ObjectFile &File, const Options &Options, raw_pwrite_stream &OutStream) { - if (Options.UseLLVMDWARFLinker) + if (Options.UseDWARFLinkerParallel) return linkDebugInfoImpl(File, Options, OutStream); else return linkDebugInfoImpl(File, Options, OutStream); diff --git a/llvm/tools/llvm-dwarfutil/Options.h b/llvm/tools/llvm-dwarfutil/Options.h index caa35d3c457..e3cfa421da9 100644 --- a/llvm/tools/llvm-dwarfutil/Options.h +++ b/llvm/tools/llvm-dwarfutil/Options.h @@ -40,7 +40,7 @@ struct Options { bool Verbose = false; int NumThreads = 0; bool Verify = false; - bool UseLLVMDWARFLinker = false; + bool UseDWARFLinkerParallel = false; DwarfUtilAccelKind AccelTableKind = DwarfUtilAccelKind::None; std::string getSeparateDebugFileName() const { diff --git a/llvm/tools/llvm-dwarfutil/Options.td b/llvm/tools/llvm-dwarfutil/Options.td index 26b9ac678b6..85606bd4d58 100644 --- a/llvm/tools/llvm-dwarfutil/Options.td +++ b/llvm/tools/llvm-dwarfutil/Options.td @@ -22,7 +22,7 @@ def h : Flag<["-"], "h">, def linker: Separate<["--", "-"], "linker">, MetaVarName<"">, - HelpText<"Specify the desired type of DWARF linker. Defaults to 'apple'">; + HelpText<"Specify the desired type of DWARF linker. Defaults to 'classic'">; def: Joined<["--", "-"], "linker=">, Alias; defm odr_deduplication : BB<"odr-deduplication", diff --git a/llvm/tools/llvm-dwarfutil/llvm-dwarfutil.cpp b/llvm/tools/llvm-dwarfutil/llvm-dwarfutil.cpp index e09060abb62..7b777b1845f 100644 --- a/llvm/tools/llvm-dwarfutil/llvm-dwarfutil.cpp +++ b/llvm/tools/llvm-dwarfutil/llvm-dwarfutil.cpp @@ -118,10 +118,10 @@ static Error validateAndSetOptions(opt::InputArgList &Args, Options &Options) { if (opt::Arg *LinkerKind = Args.getLastArg(OPT_linker)) { StringRef S = LinkerKind->getValue(); - if (S == "apple") - Options.UseLLVMDWARFLinker = false; - else if (S == "llvm") - Options.UseLLVMDWARFLinker = true; + if (S == "classic") + Options.UseDWARFLinkerParallel = false; + else if (S == "parallel") + Options.UseDWARFLinkerParallel = true; else return createStringError( std::errc::invalid_argument, diff --git a/llvm/tools/llvm-dwp/llvm-dwp.cpp b/llvm/tools/llvm-dwp/llvm-dwp.cpp index a6b8643a590..81556b3ad4b 100644 --- a/llvm/tools/llvm-dwp/llvm-dwp.cpp +++ b/llvm/tools/llvm-dwp/llvm-dwp.cpp @@ -27,7 +27,6 @@ #include "llvm/Option/Option.h" #include "llvm/Support/CommandLine.h" #include "llvm/Support/FileSystem.h" -#include "llvm/Support/InitLLVM.h" #include "llvm/Support/LLVMDriver.h" #include "llvm/Support/MemoryBuffer.h" #include "llvm/Support/TargetSelect.h" @@ -120,8 +119,6 @@ static Expected readTargetTriple(StringRef FileName) { } int llvm_dwp_main(int argc, char **argv, const llvm::ToolContext &) { - InitLLVM X(argc, argv); - DwpOptTable Tbl; llvm::BumpPtrAllocator A; llvm::StringSaver Saver{A}; diff --git a/llvm/tools/llvm-lto/llvm-lto.cpp b/llvm/tools/llvm-lto/llvm-lto.cpp index 4141aa85d08..735b3763f5b 100644 --- a/llvm/tools/llvm-lto/llvm-lto.cpp +++ b/llvm/tools/llvm-lto/llvm-lto.cpp @@ -526,7 +526,7 @@ static std::string getThinLTOOutputFile(StringRef Path, StringRef OldPrefix, if (std::error_code EC = llvm::sys::fs::create_directories(ParentPath)) error(EC, "error creating the directory '" + ParentPath + "'"); } - return std::string(NewPath.str()); + return std::string(NewPath); } namespace thinlto { diff --git a/llvm/tools/llvm-nm/llvm-nm.cpp b/llvm/tools/llvm-nm/llvm-nm.cpp index 19ee5374979..da5998b70ea 100644 --- a/llvm/tools/llvm-nm/llvm-nm.cpp +++ b/llvm/tools/llvm-nm/llvm-nm.cpp @@ -42,7 +42,6 @@ #include "llvm/Support/CommandLine.h" #include "llvm/Support/FileSystem.h" #include "llvm/Support/Format.h" -#include "llvm/Support/InitLLVM.h" #include "llvm/Support/LLVMDriver.h" #include "llvm/Support/MemoryBuffer.h" #include "llvm/Support/Program.h" @@ -2405,7 +2404,6 @@ exportSymbolNamesFromFiles(const std::vector &InputFilenames) { } int llvm_nm_main(int argc, char **argv, const llvm::ToolContext &) { - InitLLVM X(argc, argv); BumpPtrAllocator A; StringSaver Saver(A); NmOptTable Tbl; diff --git a/llvm/tools/llvm-objcopy/llvm-objcopy.cpp b/llvm/tools/llvm-objcopy/llvm-objcopy.cpp index 558359eca3c..730f423daa1 100644 --- a/llvm/tools/llvm-objcopy/llvm-objcopy.cpp +++ b/llvm/tools/llvm-objcopy/llvm-objcopy.cpp @@ -42,7 +42,6 @@ #include "llvm/Support/ErrorHandling.h" #include "llvm/Support/ErrorOr.h" #include "llvm/Support/FileUtilities.h" -#include "llvm/Support/InitLLVM.h" #include "llvm/Support/LLVMDriver.h" #include "llvm/Support/Memory.h" #include "llvm/Support/Path.h" @@ -224,7 +223,6 @@ static Error executeObjcopy(ConfigManager &ConfigMgr) { } int llvm_objcopy_main(int argc, char **argv, const llvm::ToolContext &) { - InitLLVM X(argc, argv); ToolName = argv[0]; // Expand response files. diff --git a/llvm/tools/llvm-objdump/llvm-objdump.cpp b/llvm/tools/llvm-objdump/llvm-objdump.cpp index 7467a6062b5..22b427f5765 100644 --- a/llvm/tools/llvm-objdump/llvm-objdump.cpp +++ b/llvm/tools/llvm-objdump/llvm-objdump.cpp @@ -71,7 +71,6 @@ #include "llvm/Support/Format.h" #include "llvm/Support/FormatVariadic.h" #include "llvm/Support/GraphWriter.h" -#include "llvm/Support/InitLLVM.h" #include "llvm/Support/LLVMDriver.h" #include "llvm/Support/MemoryBuffer.h" #include "llvm/Support/SourceMgr.h" @@ -1264,10 +1263,57 @@ static SymbolInfoTy createDummySymbolInfo(const ObjectFile &Obj, return SymbolInfoTy(Addr, Name, Type); } -static void -collectBBAddrMapLabels(const std::unordered_map &AddrToBBAddrMap, - uint64_t SectionAddr, uint64_t Start, uint64_t End, - std::unordered_map> &Labels) { +struct BBAddrMapLabel { + std::string BlockLabel; + std::string PGOAnalysis; +}; + +static std::string constructPGOLabelString(const PGOAnalysisMap &PGOMap, + size_t BBEntryIndex) { + std::string PGOString; + raw_string_ostream PGOSS(PGOString); + + PGOSS << " ("; + if (PGOMap.FeatEnable.FuncEntryCount && BBEntryIndex == 0) { + PGOSS << "Entry count: " << Twine(PGOMap.FuncEntryCount); + if (PGOMap.FeatEnable.BBFreq || PGOMap.FeatEnable.BrProb) { + PGOSS << ", "; + } + } + + if (PGOMap.FeatEnable.BBFreq || PGOMap.FeatEnable.BrProb) { + assert(BBEntryIndex < PGOMap.BBEntries.size() && + "Expected PGOAnalysisMap and BBAddrMap to have the same entires"); + const PGOAnalysisMap::PGOBBEntry &PGOBBEntry = + PGOMap.BBEntries[BBEntryIndex]; + + if (PGOMap.FeatEnable.BBFreq) { + PGOSS << "Frequency: " << Twine(PGOBBEntry.BlockFreq.getFrequency()); + if (PGOMap.FeatEnable.BrProb && PGOBBEntry.Successors.size() > 0) { + PGOSS << ", "; + } + } + if (PGOMap.FeatEnable.BrProb && PGOBBEntry.Successors.size() > 0) { + PGOSS << "Successors: "; + interleaveComma( + PGOBBEntry.Successors, PGOSS, + [&PGOSS](const PGOAnalysisMap::PGOBBEntry::SuccessorEntry &SE) { + PGOSS << "BB" << SE.ID << ":"; + PGOSS.write_hex(SE.Prob.getNumerator()); + }); + } + } + PGOSS << ")"; + + return PGOString; +} + +static void collectBBAddrMapLabels( + const std::unordered_map &AddrToBBAddrMap, + const std::unordered_map &AddrToPGOAnalysisMap, + uint64_t SectionAddr, uint64_t Start, uint64_t End, + std::unordered_map> &Labels, + const StringRef FileName) { if (AddrToBBAddrMap.empty()) return; Labels.clear(); @@ -1276,11 +1322,21 @@ collectBBAddrMapLabels(const std::unordered_map &AddrToBBAd auto Iter = AddrToBBAddrMap.find(StartAddress); if (Iter == AddrToBBAddrMap.end()) return; - for (const BBAddrMap::BBEntry &BBEntry : Iter->second.getBBEntries()) { + auto PGOIter = AddrToPGOAnalysisMap.find(StartAddress); + + for (size_t I = 0; I < Iter->second.getBBEntries().size(); ++I) { + const BBAddrMap::BBEntry &BBEntry = Iter->second.getBBEntries()[I]; uint64_t BBAddress = BBEntry.Offset + Iter->second.getFunctionAddress(); if (BBAddress >= EndAddress) continue; - Labels[BBAddress].push_back(("BB" + Twine(BBEntry.ID)).str()); + + std::string LabelString = ("BB" + Twine(BBEntry.ID)).str(); + std::string PGOString; + + if (PGOIter != AddrToPGOAnalysisMap.end()) + PGOString = constructPGOLabelString(PGOIter->second, I); + + Labels[BBAddress].push_back({LabelString, PGOString}); } } @@ -1638,18 +1694,24 @@ disassembleObject(ObjectFile &Obj, const ObjectFile &DbgObj, LLVM_DEBUG(LVP.dump()); std::unordered_map AddrToBBAddrMap; + std::unordered_map AddrToPGOAnalysisMap; auto ReadBBAddrMap = [&](std::optional SectionIndex = std::nullopt) { AddrToBBAddrMap.clear(); if (const auto *Elf = dyn_cast(&Obj)) { - auto BBAddrMapsOrErr = Elf->readBBAddrMap(SectionIndex); + std::vector PGOAnalyses; + auto BBAddrMapsOrErr = Elf->readBBAddrMap(SectionIndex, &PGOAnalyses); if (!BBAddrMapsOrErr) { reportWarning(toString(BBAddrMapsOrErr.takeError()), Obj.getFileName()); return; } - for (auto &FunctionBBAddrMap : *BBAddrMapsOrErr) - AddrToBBAddrMap.emplace(FunctionBBAddrMap.Addr, - std::move(FunctionBBAddrMap)); + for (const auto &[FunctionBBAddrMap, FunctionPGOAnalysis] : + zip_equal(*std::move(BBAddrMapsOrErr), std::move(PGOAnalyses))) { + uint64_t Addr = FunctionBBAddrMap.Addr; + AddrToBBAddrMap.emplace(Addr, std::move(FunctionBBAddrMap)); + if (FunctionPGOAnalysis.FeatEnable.anyEnabled()) + AddrToPGOAnalysisMap.emplace(Addr, std::move(FunctionPGOAnalysis)); + } } }; @@ -1978,14 +2040,15 @@ disassembleObject(ObjectFile &Obj, const ObjectFile &DbgObj, FOS.SetUnbuffered(); std::unordered_map AllLabels; - std::unordered_map> BBAddrMapLabels; + std::unordered_map> BBAddrMapLabels; if (SymbolizeOperands) { collectLocalBranchTargets(Bytes, DT->InstrAnalysis.get(), DT->DisAsm.get(), DT->InstPrinter.get(), PrimaryTarget.SubtargetInfo.get(), SectionAddr, Index, End, AllLabels); - collectBBAddrMapLabels(AddrToBBAddrMap, SectionAddr, Index, End, - BBAddrMapLabels); + collectBBAddrMapLabels(AddrToBBAddrMap, AddrToPGOAnalysisMap, + SectionAddr, Index, End, BBAddrMapLabels, + FileName); } if (DT->InstrAnalysis) @@ -2083,8 +2146,9 @@ disassembleObject(ObjectFile &Obj, const ObjectFile &DbgObj, // Print local label if there's any. auto Iter1 = BBAddrMapLabels.find(SectionAddr + Index); if (Iter1 != BBAddrMapLabels.end()) { - for (StringRef Label : Iter1->second) - FOS << "<" << Label << ">:\n"; + for (const auto &BBLabel : Iter1->second) + FOS << "<" << BBLabel.BlockLabel << ">" << BBLabel.PGOAnalysis + << ":\n"; } else { auto Iter2 = AllLabels.find(SectionAddr + Index); if (Iter2 != AllLabels.end()) @@ -2261,7 +2325,7 @@ disassembleObject(ObjectFile &Obj, const ObjectFile &DbgObj, } else if (!Disp) { *TargetOS << TargetName; } else if (BBAddrMapLabelAvailable) { - *TargetOS << BBAddrMapLabels[Target].front(); + *TargetOS << BBAddrMapLabels[Target].front().BlockLabel; } else if (LabelAvailable) { *TargetOS << AllLabels[Target]; } else { @@ -2277,7 +2341,8 @@ disassembleObject(ObjectFile &Obj, const ObjectFile &DbgObj, } } else if (BBAddrMapLabelAvailable) { - *TargetOS << " <" << BBAddrMapLabels[Target].front() << ">"; + *TargetOS << " <" << BBAddrMapLabels[Target].front().BlockLabel + << ">"; } else if (LabelAvailable) { *TargetOS << " <" << AllLabels[Target] << ">"; } @@ -3417,7 +3482,6 @@ static void parseObjdumpOptions(const llvm::opt::InputArgList &InputArgs) { int llvm_objdump_main(int argc, char **argv, const llvm::ToolContext &) { using namespace llvm; - InitLLVM X(argc, argv); ToolName = argv[0]; std::unique_ptr T; diff --git a/llvm/tools/llvm-pdbutil/llvm-pdbutil.cpp b/llvm/tools/llvm-pdbutil/llvm-pdbutil.cpp index 5810c70a664..9da14cc52d6 100644 --- a/llvm/tools/llvm-pdbutil/llvm-pdbutil.cpp +++ b/llvm/tools/llvm-pdbutil/llvm-pdbutil.cpp @@ -1574,7 +1574,7 @@ int main(int Argc, const char **Argv) { if (opts::yaml2pdb::YamlPdbOutputFile.empty()) { SmallString<16> OutputFilename(opts::yaml2pdb::InputFilename.getValue()); sys::path::replace_extension(OutputFilename, ".pdb"); - opts::yaml2pdb::YamlPdbOutputFile = std::string(OutputFilename.str()); + opts::yaml2pdb::YamlPdbOutputFile = std::string(OutputFilename); } yamlToPdb(opts::yaml2pdb::InputFilename); } else if (opts::DiaDumpSubcommand) { diff --git a/llvm/tools/llvm-profdata/llvm-profdata.cpp b/llvm/tools/llvm-profdata/llvm-profdata.cpp index 05e96f48cf1..239aa1c93a2 100644 --- a/llvm/tools/llvm-profdata/llvm-profdata.cpp +++ b/llvm/tools/llvm-profdata/llvm-profdata.cpp @@ -30,11 +30,11 @@ #include "llvm/Support/FileSystem.h" #include "llvm/Support/Format.h" #include "llvm/Support/FormattedStream.h" -#include "llvm/Support/InitLLVM.h" #include "llvm/Support/LLVMDriver.h" #include "llvm/Support/MD5.h" #include "llvm/Support/MemoryBuffer.h" #include "llvm/Support/Path.h" +#include "llvm/Support/Regex.h" #include "llvm/Support/ThreadPool.h" #include "llvm/Support/Threading.h" #include "llvm/Support/VirtualFileSystem.h" @@ -132,9 +132,11 @@ cl::opt cl::sub(MergeSubcommand)); cl::opt FuncNameFilter( "function", - cl::desc("Details for matching functions. For overlapping CSSPGO, this " - "takes a function name with calling context."), - cl::sub(ShowSubcommand), cl::sub(OverlapSubcommand)); + cl::desc("Only functions matching the filter are shown in the output. For " + "overlapping CSSPGO, this takes a function name with calling " + "context."), + cl::sub(ShowSubcommand), cl::sub(OverlapSubcommand), + cl::sub(MergeSubcommand)); // TODO: Consider creating a template class (e.g., MergeOption, ShowOption) to // factor out the common cl::sub in cl::opt constructor for subcommand-specific @@ -244,6 +246,10 @@ cl::opt TemporalProfMaxTraceLength( cl::sub(MergeSubcommand), cl::desc("The maximum length of a single temporal profile trace " "(default: 10000)")); +cl::opt FuncNameNegativeFilter( + "no-function", cl::init(""), + cl::sub(MergeSubcommand), + cl::desc("Exclude functions matching the filter from the output.")); cl::opt FailMode("failure-mode", cl::init(failIfAnyAreInvalid), @@ -760,6 +766,62 @@ static void mergeWriterContexts(WriterContext *Dst, WriterContext *Src) { }); } +static StringRef +getFuncName(const StringMap::value_type &Val) { + return Val.first(); +} + +static std::string +getFuncName(const SampleProfileMap::value_type &Val) { + return Val.second.getContext().toString(); +} + +template +static void filterFunctions(T &ProfileMap) { + bool hasFilter = !FuncNameFilter.empty(); + bool hasNegativeFilter = !FuncNameNegativeFilter.empty(); + if (!hasFilter && !hasNegativeFilter) + return; + + // If filter starts with '?' it is MSVC mangled name, not a regex. + llvm::Regex ProbablyMSVCMangledName("[?@$_0-9A-Za-z]+"); + if (hasFilter && FuncNameFilter[0] == '?' && + ProbablyMSVCMangledName.match(FuncNameFilter)) + FuncNameFilter = llvm::Regex::escape(FuncNameFilter); + if (hasNegativeFilter && FuncNameNegativeFilter[0] == '?' && + ProbablyMSVCMangledName.match(FuncNameNegativeFilter)) + FuncNameNegativeFilter = llvm::Regex::escape(FuncNameNegativeFilter); + + size_t Count = ProfileMap.size(); + llvm::Regex Pattern(FuncNameFilter); + llvm::Regex NegativePattern(FuncNameNegativeFilter); + std::string Error; + if (hasFilter && !Pattern.isValid(Error)) + exitWithError(Error); + if (hasNegativeFilter && !NegativePattern.isValid(Error)) + exitWithError(Error); + + // Handle MD5 profile, so it is still able to match using the original name. + std::string MD5Name = std::to_string(llvm::MD5Hash(FuncNameFilter)); + std::string NegativeMD5Name = + std::to_string(llvm::MD5Hash(FuncNameNegativeFilter)); + + for (auto I = ProfileMap.begin(); I != ProfileMap.end();) { + auto Tmp = I++; + const auto &FuncName = getFuncName(*Tmp); + // Negative filter has higher precedence than positive filter. + if ((hasNegativeFilter && + (NegativePattern.match(FuncName) || + (FunctionSamples::UseMD5 && NegativeMD5Name == FuncName))) || + (hasFilter && !(Pattern.match(FuncName) || + (FunctionSamples::UseMD5 && MD5Name == FuncName)))) + ProfileMap.erase(Tmp); + } + + llvm::dbgs() << Count - ProfileMap.size() << " of " << Count << " functions " + << "in the original profile are filtered.\n"; +} + static void writeInstrProfile(StringRef OutputFilename, ProfileFormat OutputFormat, InstrProfWriter &Writer) { @@ -879,6 +941,8 @@ static void mergeInstrProfile(const WeightedFileVector &Inputs, (NumErrors > 0 && FailMode == failIfAnyAreInvalid)) exitWithError("no profile can be merged"); + filterFunctions(Contexts[0]->Writer.getProfileData()); + writeInstrProfile(OutputFilename, OutputFormat, Contexts[0]->Writer); } @@ -1460,6 +1524,8 @@ static void mergeSampleProfile(const WeightedFileVector &Inputs, ProfileIsCS = FunctionSamples::ProfileIsCS = false; } + filterFunctions(ProfileMap); + auto WriterOrErr = SampleProfileWriter::create(OutputFilename, FormatMap[OutputFormat]); if (std::error_code EC = WriterOrErr.getError()) @@ -3176,7 +3242,6 @@ static int order_main(int argc, const char *argv[]) { int llvm_profdata_main(int argc, char **argvNonConst, const llvm::ToolContext &) { const char **argv = const_cast(argvNonConst); - InitLLVM X(argc, argv); StringRef ProgName(sys::path::filename(argv[0])); diff --git a/llvm/tools/llvm-readobj/COFFImportDumper.cpp b/llvm/tools/llvm-readobj/COFFImportDumper.cpp index c9d5e82263d..8aedc310ae3 100644 --- a/llvm/tools/llvm-readobj/COFFImportDumper.cpp +++ b/llvm/tools/llvm-readobj/COFFImportDumper.cpp @@ -23,7 +23,7 @@ namespace llvm { void dumpCOFFImportFile(const COFFImportFile *File, ScopedPrinter &Writer) { Writer.startLine() << '\n'; Writer.printString("File", File->getFileName()); - Writer.printString("Format", "COFF-import-file"); + Writer.printString("Format", File->getFileFormatName()); const coff_import_header *H = File->getCOFFImportHeader(); switch (H->getType()) { diff --git a/llvm/tools/llvm-readobj/llvm-readobj.cpp b/llvm/tools/llvm-readobj/llvm-readobj.cpp index ca633ceff90..f9d605d3524 100644 --- a/llvm/tools/llvm-readobj/llvm-readobj.cpp +++ b/llvm/tools/llvm-readobj/llvm-readobj.cpp @@ -42,7 +42,6 @@ #include "llvm/Support/Errc.h" #include "llvm/Support/FileSystem.h" #include "llvm/Support/FormatVariadic.h" -#include "llvm/Support/InitLLVM.h" #include "llvm/Support/LLVMDriver.h" #include "llvm/Support/Path.h" #include "llvm/Support/ScopedPrinter.h" @@ -633,7 +632,6 @@ std::unique_ptr createWriter() { } int llvm_readobj_main(int argc, char **argv, const llvm::ToolContext &) { - InitLLVM X(argc, argv); BumpPtrAllocator A; StringSaver Saver(A); ReadobjOptTable Tbl; diff --git a/llvm/tools/llvm-rtdyld/llvm-rtdyld.cpp b/llvm/tools/llvm-rtdyld/llvm-rtdyld.cpp index 107b555a99f..4cb76f43474 100644 --- a/llvm/tools/llvm-rtdyld/llvm-rtdyld.cpp +++ b/llvm/tools/llvm-rtdyld/llvm-rtdyld.cpp @@ -926,7 +926,8 @@ static int linkAndVerify() { }; auto GetStubInfo = [&Dyld, &StubMap](StringRef StubContainer, - StringRef SymbolName) + StringRef SymbolName, + StringRef KindNameFilter) -> Expected { if (!StubMap.count(StubContainer)) return make_error("Stub container not found: " + @@ -947,6 +948,11 @@ static int linkAndVerify() { return StubMemInfo; }; + auto GetGOTInfo = [&GetStubInfo](StringRef StubContainer, + StringRef SymbolName) { + return GetStubInfo(StubContainer, SymbolName, ""); + }; + // We will initialize this below once we have the first object file and can // know the endianness. std::unique_ptr Checker; @@ -977,8 +983,7 @@ static int linkAndVerify() { if (!Checker) Checker = std::make_unique( - IsSymbolValid, GetSymbolInfo, GetSectionInfo, GetStubInfo, - GetStubInfo, + IsSymbolValid, GetSymbolInfo, GetSectionInfo, GetStubInfo, GetGOTInfo, Obj.isLittleEndian() ? llvm::endianness::little : llvm::endianness::big, TheTriple, MCPU, SubtargetFeatures(), dbgs()); diff --git a/llvm/tools/llvm-size/llvm-size.cpp b/llvm/tools/llvm-size/llvm-size.cpp index c0d1a1b104b..78b207eeeb1 100644 --- a/llvm/tools/llvm-size/llvm-size.cpp +++ b/llvm/tools/llvm-size/llvm-size.cpp @@ -25,7 +25,6 @@ #include "llvm/Support/CommandLine.h" #include "llvm/Support/FileSystem.h" #include "llvm/Support/Format.h" -#include "llvm/Support/InitLLVM.h" #include "llvm/Support/LLVMDriver.h" #include "llvm/Support/MemoryBuffer.h" #include "llvm/Support/WithColor.h" @@ -863,7 +862,6 @@ static void printBerkeleyTotals() { } int llvm_size_main(int argc, char **argv, const llvm::ToolContext &) { - InitLLVM X(argc, argv); BumpPtrAllocator A; StringSaver Saver(A); SizeOptTable Tbl; diff --git a/llvm/tools/llvm-symbolizer/llvm-symbolizer.cpp b/llvm/tools/llvm-symbolizer/llvm-symbolizer.cpp index 74cc2da4e1c..b98bdbc388f 100644 --- a/llvm/tools/llvm-symbolizer/llvm-symbolizer.cpp +++ b/llvm/tools/llvm-symbolizer/llvm-symbolizer.cpp @@ -34,7 +34,6 @@ #include "llvm/Support/Debug.h" #include "llvm/Support/Errc.h" #include "llvm/Support/FileSystem.h" -#include "llvm/Support/InitLLVM.h" #include "llvm/Support/LLVMDriver.h" #include "llvm/Support/Path.h" #include "llvm/Support/StringSaver.h" @@ -462,7 +461,6 @@ static void filterMarkup(const opt::InputArgList &Args, LLVMSymbolizer &Symboliz } int llvm_symbolizer_main(int argc, char **argv, const llvm::ToolContext &) { - InitLLVM X(argc, argv); sys::InitializeCOMRAII COM(sys::COMThreadingMode::MultiThreaded); ToolName = argv[0]; diff --git a/llvm/tools/opt/opt.cpp b/llvm/tools/opt/opt.cpp index c649e6ecddc..8c0e98976e6 100644 --- a/llvm/tools/opt/opt.cpp +++ b/llvm/tools/opt/opt.cpp @@ -282,7 +282,7 @@ static cl::list static cl::opt TryUseNewDbgInfoFormat( "try-experimental-debuginfo-iterators", cl::desc("Enable debuginfo iterator positions, if they're built in"), - cl::init(false)); + cl::init(false), cl::Hidden); extern cl::opt UseNewDbgInfoFormat; diff --git a/llvm/utils/TableGen/CodeGenTarget.cpp b/llvm/utils/TableGen/CodeGenTarget.cpp index 53efa66f9df..37fa30349ee 100644 --- a/llvm/utils/TableGen/CodeGenTarget.cpp +++ b/llvm/utils/TableGen/CodeGenTarget.cpp @@ -291,6 +291,7 @@ CodeGenTarget::CodeGenTarget(RecordKeeper &records) if (Targets.size() != 1) PrintFatalError("Multiple subclasses of Target defined!"); TargetRec = Targets[0]; + MacroFusions = Records.getAllDerivedDefinitions("Fusion"); } CodeGenTarget::~CodeGenTarget() { diff --git a/llvm/utils/TableGen/CodeGenTarget.h b/llvm/utils/TableGen/CodeGenTarget.h index a2b559d53b1..d7388dceca3 100644 --- a/llvm/utils/TableGen/CodeGenTarget.h +++ b/llvm/utils/TableGen/CodeGenTarget.h @@ -64,6 +64,8 @@ class CodeGenTarget { mutable std::vector RegAltNameIndices; mutable SmallVector LegalValueTypes; CodeGenHwModes CGH; + std::vector MacroFusions; + void ReadRegAltNameIndices() const; void ReadInstructions() const; void ReadLegalValueTypes() const; @@ -149,6 +151,10 @@ public: const CodeGenHwModes &getHwModes() const { return CGH; } + bool hasMacroFusion() const { return !MacroFusions.empty(); } + + const std::vector getMacroFusions() const { return MacroFusions; } + private: DenseMap> & getInstructions() const { diff --git a/llvm/utils/TableGen/DAGISelMatcherEmitter.cpp b/llvm/utils/TableGen/DAGISelMatcherEmitter.cpp index a3e2facf948..455183987b7 100644 --- a/llvm/utils/TableGen/DAGISelMatcherEmitter.cpp +++ b/llvm/utils/TableGen/DAGISelMatcherEmitter.cpp @@ -52,9 +52,8 @@ class MatcherTableEmitter { SmallVector OpcodeCounts; - DenseMap NodePredicateMap; - std::vector NodePredicates; - std::vector NodePredicatesWithOperands; + std::vector NodePredicates; + std::vector NodePredicatesWithOperands; // We de-duplicate the predicates by code string, and use this map to track // all the patterns with "identical" predicates. @@ -85,9 +84,11 @@ public: MatcherTableEmitter(const Matcher *TheMatcher, const CodeGenDAGPatterns &cgp) : CGP(cgp), OpcodeCounts(Matcher::HighestKind + 1, 0) { // Record the usage of ComplexPattern. - DenseMap ComplexPatternUsage; + MapVector ComplexPatternUsage; // Record the usage of PatternPredicate. - std::map PatternPredicateUsage; + MapVector PatternPredicateUsage; + // Record the usage of Predicate. + MapVector PredicateUsage; // Iterate the whole MatcherTable once and do some statistics. std::function Statistic = [&](const Matcher *N) { @@ -105,6 +106,8 @@ public: ++ComplexPatternUsage[&CPM->getPattern()]; else if (auto *CPPM = dyn_cast(N)) ++PatternPredicateUsage[CPPM->getPredicate()]; + else if (auto *PM = dyn_cast(N)) + ++PredicateUsage[PM->getPredicate().getOrigPatFragRecord()]; N = N->getNext(); } }; @@ -113,18 +116,54 @@ public: // Sort ComplexPatterns by usage. std::vector> ComplexPatternList( ComplexPatternUsage.begin(), ComplexPatternUsage.end()); - sort(ComplexPatternList, - [](const auto &A, const auto &B) { return A.second > B.second; }); + stable_sort(ComplexPatternList, [](const auto &A, const auto &B) { + return A.second > B.second; + }); for (const auto &ComplexPattern : ComplexPatternList) ComplexPatterns.push_back(ComplexPattern.first); // Sort PatternPredicates by usage. std::vector> PatternPredicateList( PatternPredicateUsage.begin(), PatternPredicateUsage.end()); - sort(PatternPredicateList, - [](const auto &A, const auto &B) { return A.second > B.second; }); + stable_sort(PatternPredicateList, [](const auto &A, const auto &B) { + return A.second > B.second; + }); for (const auto &PatternPredicate : PatternPredicateList) PatternPredicates.push_back(PatternPredicate.first); + + // Sort Predicates by usage. + // Merge predicates with same code. + for (const auto &Usage : PredicateUsage) { + TreePattern *TP = Usage.first; + TreePredicateFn Pred(TP); + NodePredicatesByCodeToRun[Pred.getCodeToRunOnSDNode()].push_back(TP); + } + + std::vector> PredicateList; + // Sum the usage. + for (auto &Predicate : NodePredicatesByCodeToRun) { + TinyPtrVector &TPs = Predicate.second; + stable_sort(TPs, [](const auto *A, const auto *B) { + return A->getRecord()->getName() < B->getRecord()->getName(); + }); + unsigned Uses = 0; + for (TreePattern *TP : TPs) + Uses += PredicateUsage[TP]; + + // We only add the first predicate here since they are with the same code. + PredicateList.push_back({TPs[0], Uses}); + } + + stable_sort(PredicateList, [](const auto &A, const auto &B) { + return A.second > B.second; + }); + for (const auto &Predicate : PredicateList) { + TreePattern *TP = Predicate.first; + if (TreePredicateFn(TP).usesOperands()) + NodePredicatesWithOperands.push_back(TP); + else + NodePredicates.push_back(TP); + } } unsigned EmitMatcherList(const Matcher *N, const unsigned Indent, @@ -139,7 +178,7 @@ public: void EmitPatternMatchTable(raw_ostream &OS); private: - void EmitNodePredicatesFunction(const std::vector &Preds, + void EmitNodePredicatesFunction(const std::vector &Preds, StringRef Decl, raw_ostream &OS); unsigned SizeMatcher(Matcher *N, raw_ostream &OS); @@ -148,33 +187,13 @@ private: raw_ostream &OS); unsigned getNodePredicate(TreePredicateFn Pred) { - TreePattern *TP = Pred.getOrigPatFragRecord(); - unsigned &Entry = NodePredicateMap[TP]; - if (Entry == 0) { - TinyPtrVector &SameCodePreds = - NodePredicatesByCodeToRun[Pred.getCodeToRunOnSDNode()]; - if (SameCodePreds.empty()) { - // We've never seen a predicate with the same code: allocate an entry. - if (Pred.usesOperands()) { - NodePredicatesWithOperands.push_back(Pred); - Entry = NodePredicatesWithOperands.size(); - } else { - NodePredicates.push_back(Pred); - Entry = NodePredicates.size(); - } - } else { - // We did see an identical predicate: re-use it. - Entry = NodePredicateMap[SameCodePreds.front()]; - assert(Entry != 0); - assert(TreePredicateFn(SameCodePreds.front()).usesOperands() == - Pred.usesOperands() && - "PatFrags with some code must have same usesOperands setting"); - } - // In both cases, we've never seen this particular predicate before, so - // mark it in the list of predicates sharing the same code. - SameCodePreds.push_back(TP); - } - return Entry-1; + // We use the first predicate. + TreePattern *PredPat = + NodePredicatesByCodeToRun[Pred.getCodeToRunOnSDNode()][0]; + return Pred.usesOperands() + ? llvm::find(NodePredicatesWithOperands, PredPat) - + NodePredicatesWithOperands.begin() + : llvm::find(NodePredicates, PredPat) - NodePredicates.begin(); } unsigned getPatternPredicate(StringRef PredName) { @@ -529,6 +548,7 @@ EmitMatcher(const Matcher *N, const unsigned Indent, unsigned CurrentIdx, case Matcher::CheckPredicate: { TreePredicateFn Pred = cast(N)->getPredicate(); unsigned OperandBytes = 0; + unsigned PredNo = getNodePredicate(Pred); if (Pred.usesOperands()) { unsigned NumOps = cast(N)->getNumOperands(); @@ -537,10 +557,15 @@ EmitMatcher(const Matcher *N, const unsigned Indent, unsigned CurrentIdx, OS << cast(N)->getOperandNo(i) << ", "; OperandBytes = 1 + NumOps; } else { - OS << "OPC_CheckPredicate, "; + if (PredNo < 8) { + OperandBytes = -1; + OS << "OPC_CheckPredicate" << PredNo << ", "; + } else + OS << "OPC_CheckPredicate, "; } - OS << getNodePredicate(Pred) << ','; + if (PredNo >= 8 || Pred.usesOperands()) + OS << PredNo << ','; if (!OmitComments) OS << " // " << Pred.getFnName(); OS << '\n'; @@ -1029,8 +1054,7 @@ EmitMatcherList(const Matcher *N, const unsigned Indent, unsigned CurrentIdx, } void MatcherTableEmitter::EmitNodePredicatesFunction( - const std::vector &Preds, StringRef Decl, - raw_ostream &OS) { + const std::vector &Preds, StringRef Decl, raw_ostream &OS) { if (Preds.empty()) return; @@ -1040,7 +1064,7 @@ void MatcherTableEmitter::EmitNodePredicatesFunction( OS << " default: llvm_unreachable(\"Invalid predicate in table?\");\n"; for (unsigned i = 0, e = Preds.size(); i != e; ++i) { // Emit the predicate code corresponding to this pattern. - const TreePredicateFn PredFn = Preds[i]; + TreePredicateFn PredFn(Preds[i]); assert(!PredFn.isAlwaysTrue() && "No code in this predicate"); std::string PredFnCodeStr = PredFn.getCodeToRunOnSDNode(); diff --git a/llvm/utils/TableGen/GlobalISel/CodeExpander.cpp b/llvm/utils/TableGen/GlobalISel/CodeExpander.cpp index 20f98bef488..b0baf194baf 100644 --- a/llvm/utils/TableGen/GlobalISel/CodeExpander.cpp +++ b/llvm/utils/TableGen/GlobalISel/CodeExpander.cpp @@ -31,9 +31,8 @@ void CodeExpander::emit(raw_ostream &OS) const { OS << Current.substr(0, Pos); Current = Current.substr(Pos); - if (Current.starts_with("\n")) { + if (Current.consume_front("\n")) { OS << "\n" << Indent; - Current = Current.drop_front(1); continue; } @@ -43,10 +42,8 @@ void CodeExpander::emit(raw_ostream &OS) const { continue; } - if (Current.starts_with("\\")) { - Current = Current.drop_front(1); + if (Current.consume_front("\\")) continue; - } if (Current.starts_with("${")) { StringRef StartVar = Current; diff --git a/llvm/utils/TableGen/GlobalISelCombinerEmitter.cpp b/llvm/utils/TableGen/GlobalISelCombinerEmitter.cpp index c092772386e..124e416eea2 100644 --- a/llvm/utils/TableGen/GlobalISelCombinerEmitter.cpp +++ b/llvm/utils/TableGen/GlobalISelCombinerEmitter.cpp @@ -2185,6 +2185,11 @@ bool CombineRuleBuilder::emitApplyPatterns(CodeExpansions &CE, RuleMatcher &M) { } } + // Erase the root. + unsigned RootInsnID = + M.getInsnVarID(M.getInstructionMatcher(MatchRoot->getName())); + M.addAction(RootInsnID); + return true; } @@ -2418,12 +2423,6 @@ bool CombineRuleBuilder::emitBuiltinApplyPattern( // checkSemantics should have ensured that we can only rewrite the root. // Ensure we're deleting it. assert(MatchOpTable.getDef(Old) == MatchRoot); - // TODO: We could avoid adding the action again if it's already in. The - // MatchTable is smart enough to only emit one opcode even if - // EraseInstAction is present multiple times. I think searching for a copy - // is more expensive than just blindly adding it though. - M.addAction(/*InsnID*/ 0); - return true; } } diff --git a/llvm/utils/TableGen/GlobalISelEmitter.cpp b/llvm/utils/TableGen/GlobalISelEmitter.cpp index c204b9819dc..39dece85f7c 100644 --- a/llvm/utils/TableGen/GlobalISelEmitter.cpp +++ b/llvm/utils/TableGen/GlobalISelEmitter.cpp @@ -1972,6 +1972,10 @@ Expected GlobalISelEmitter::runOnPattern(const PatternToMatch &P) { DstMIBuilder.addRenderer(Dst->getName()); M.addAction(0, 0, RC); + // Erase the root. + unsigned RootInsnID = M.getInsnVarID(InsnMatcher); + M.addAction(RootInsnID); + // We're done with this pattern! It's eligible for GISel emission; return // it. ++NumPatternImported; @@ -2099,14 +2103,7 @@ Expected GlobalISelEmitter::runOnPattern(const PatternToMatch &P) { M.addAction( 0, 0, Target.getRegisterClass(DstIOpRec)); - - // We're done with this pattern! It's eligible for GISel emission; return - // it. - ++NumPatternImported; - return std::move(M); - } - - if (DstIName == "EXTRACT_SUBREG") { + } else if (DstIName == "EXTRACT_SUBREG") { auto SuperClass = inferRegClassFromPattern(Dst->getChild(0)); if (!SuperClass) return failedImport( @@ -2136,14 +2133,7 @@ Expected GlobalISelEmitter::runOnPattern(const PatternToMatch &P) { M.addAction(0, 0, *SrcRCDstRCPair->second); M.addAction(0, 1, *SrcRCDstRCPair->first); - - // We're done with this pattern! It's eligible for GISel emission; return - // it. - ++NumPatternImported; - return std::move(M); - } - - if (DstIName == "INSERT_SUBREG") { + } else if (DstIName == "INSERT_SUBREG") { assert(Src->getExtTypes().size() == 1 && "Expected Src of INSERT_SUBREG to have one result type"); // We need to constrain the destination, a super regsister source, and a @@ -2160,11 +2150,7 @@ Expected GlobalISelEmitter::runOnPattern(const PatternToMatch &P) { M.addAction(0, 0, **SuperClass); M.addAction(0, 1, **SuperClass); M.addAction(0, 2, **SubClass); - ++NumPatternImported; - return std::move(M); - } - - if (DstIName == "SUBREG_TO_REG") { + } else if (DstIName == "SUBREG_TO_REG") { // We need to constrain the destination and subregister source. assert(Src->getExtTypes().size() == 1 && "Expected Src of SUBREG_TO_REG to have one result type"); @@ -2184,11 +2170,7 @@ Expected GlobalISelEmitter::runOnPattern(const PatternToMatch &P) { "Cannot infer register class for SUBREG_TO_REG operand #0"); M.addAction(0, 0, **SuperClass); M.addAction(0, 2, **SubClass); - ++NumPatternImported; - return std::move(M); - } - - if (DstIName == "REG_SEQUENCE") { + } else if (DstIName == "REG_SEQUENCE") { auto SuperClass = inferRegClassFromPattern(Dst->getChild(0)); M.addAction(0, 0, **SuperClass); @@ -2207,12 +2189,13 @@ Expected GlobalISelEmitter::runOnPattern(const PatternToMatch &P) { M.addAction(0, I, *SrcRCDstRCPair->second); } - - ++NumPatternImported; - return std::move(M); + } else { + M.addAction(0); } - M.addAction(0); + // Erase the root. + unsigned RootInsnID = M.getInsnVarID(InsnMatcher); + M.addAction(RootInsnID); // We're done with this pattern! It's eligible for GISel emission; return it. ++NumPatternImported; diff --git a/llvm/utils/TableGen/GlobalISelMatchTable.cpp b/llvm/utils/TableGen/GlobalISelMatchTable.cpp index 349598266aa..1ae8e30da2f 100644 --- a/llvm/utils/TableGen/GlobalISelMatchTable.cpp +++ b/llvm/utils/TableGen/GlobalISelMatchTable.cpp @@ -2172,6 +2172,9 @@ void BuildMIAction::emitActionOpcodes(MatchTable &Table, } AddMIFlags(); + + // Mark the mutated instruction as erased. + Rule.tryEraseInsnID(RecycleInsnID); return; } @@ -2223,12 +2226,6 @@ void BuildMIAction::emitActionOpcodes(MatchTable &Table, } AddMIFlags(); - - // FIXME: This is a hack but it's sufficient for ISel. We'll need to do - // better for combines. Particularly when there are multiple match - // roots. - if (InsnID == 0) - EraseInstAction::emitActionOpcodes(Table, Rule, /*InsnID*/ 0); } //===- BuildConstantAction ------------------------------------------------===// diff --git a/llvm/utils/TableGen/SubtargetEmitter.cpp b/llvm/utils/TableGen/SubtargetEmitter.cpp index f7a7172d61f..39225182a4c 100644 --- a/llvm/utils/TableGen/SubtargetEmitter.cpp +++ b/llvm/utils/TableGen/SubtargetEmitter.cpp @@ -133,6 +133,7 @@ class SubtargetEmitter { void EmitMCInstrAnalysisPredicateFunctions(raw_ostream &OS); void EmitSchedModel(raw_ostream &OS); + void emitGetMacroFusions(const std::string &ClassName, raw_ostream &OS); void EmitHwModeCheck(const std::string &ClassName, raw_ostream &OS); void ParseFeaturesFunction(raw_ostream &OS); @@ -1786,6 +1787,24 @@ void SubtargetEmitter::EmitHwModeCheck(const std::string &ClassName, OS << " return 0;\n}\n"; } +void SubtargetEmitter::emitGetMacroFusions(const std::string &ClassName, + raw_ostream &OS) { + if (!TGT.hasMacroFusion()) + return; + + OS << "std::vector " << ClassName + << "::getMacroFusions() const {\n"; + OS.indent(2) << "std::vector Fusions;\n"; + for (auto *Fusion : TGT.getMacroFusions()) { + std::string Name = Fusion->getNameInitAsString(); + OS.indent(2) << "if (hasFeature(" << Target << "::" << Name + << ")) Fusions.push_back(llvm::is" << Name << ");\n"; + } + + OS.indent(2) << "return Fusions;\n"; + OS << "}\n"; +} + // Produces a subtarget specific function for parsing // the subtarget features string. void SubtargetEmitter::ParseFeaturesFunction(raw_ostream &OS) { @@ -1987,6 +2006,9 @@ void SubtargetEmitter::run(raw_ostream &OS) { << " const;\n"; if (TGT.getHwModes().getNumModeIds() > 1) OS << " unsigned getHwMode() const override;\n"; + if (TGT.hasMacroFusion()) + OS << " std::vector getMacroFusions() const " + "override;\n"; STIPredicateExpander PE(Target); PE.setByRef(false); @@ -2044,6 +2066,7 @@ void SubtargetEmitter::run(raw_ostream &OS) { EmitSchedModelHelpers(ClassName, OS); EmitHwModeCheck(ClassName, OS); + emitGetMacroFusions(ClassName, OS); OS << "} // end namespace llvm\n\n"; diff --git a/llvm/utils/TableGen/X86CompressEVEXTablesEmitter.cpp b/llvm/utils/TableGen/X86CompressEVEXTablesEmitter.cpp index aa8527e7538..fef8dc7236f 100644 --- a/llvm/utils/TableGen/X86CompressEVEXTablesEmitter.cpp +++ b/llvm/utils/TableGen/X86CompressEVEXTablesEmitter.cpp @@ -46,8 +46,12 @@ class X86CompressEVEXTablesEmitter { typedef std::pair Entry; + typedef std::map> + PredicateInstMap; std::vector Table; + // Hold all compressed instructions that need to check predicate + PredicateInstMap PredicateInsts; public: X86CompressEVEXTablesEmitter(RecordKeeper &R) : Records(R), Target(R) {} @@ -58,12 +62,15 @@ public: private: // Prints the given table as a C++ array of type X86CompressEVEXTableEntry void printTable(const std::vector &Table, raw_ostream &OS); + // Prints function which checks target feature for compressed instructions. + void printCheckPredicate(const PredicateInstMap &PredicateInsts, + raw_ostream &OS); }; void X86CompressEVEXTablesEmitter::printTable(const std::vector &Table, raw_ostream &OS) { - OS << "static const X86CompressEVEXTableEntry X86CompressEVEXTable[] = { \n"; + OS << "static const X86CompressEVEXTableEntry X86CompressEVEXTable[] = {\n"; // Print all entries added to the table for (const auto &Pair : Table) @@ -73,6 +80,22 @@ void X86CompressEVEXTablesEmitter::printTable(const std::vector &Table, OS << "};\n\n"; } +void X86CompressEVEXTablesEmitter::printCheckPredicate( + const PredicateInstMap &PredicateInsts, raw_ostream &OS) { + + OS << "static bool checkPredicate(unsigned Opc, const X86Subtarget *Subtarget) {\n" + << " switch (Opc) {\n" + << " default: return true;\n"; + for (const auto &[Key, Val] : PredicateInsts) { + for (const auto &Inst : Val) + OS << " case X86::" << Inst->TheDef->getName() << ":\n"; + OS << " return " << Key->getValueAsString("CondString") << ";\n"; + } + + OS << " }\n"; + OS << "}\n\n"; +} + static uint8_t byteFromBitsInit(const BitsInit *B) { unsigned N = B->getNumBits(); assert(N <= 8 && "Field is too large for uint8_t!"); @@ -196,9 +219,18 @@ void X86CompressEVEXTablesEmitter::run(raw_ostream &OS) { continue; Table.push_back(std::make_pair(Inst, NewInst)); + auto Predicates = NewInst->TheDef->getValueAsListOfDefs("Predicates"); + auto It = llvm::find_if(Predicates, [](const Record *R) { + StringRef Name = R->getName(); + return Name == "HasAVXNECONVERT" || Name == "HasAVXVNNI" || + Name == "HasAVXIFMA"; + }); + if(It!= Predicates.end()) + PredicateInsts[*It].push_back(NewInst); } printTable(Table, OS); + printCheckPredicate(PredicateInsts, OS); } } // namespace diff --git a/openmp/runtime/src/include/omp_lib.h.var b/openmp/runtime/src/include/omp_lib.h.var index d20aade6ef8..617f2321676 100644 --- a/openmp/runtime/src/include/omp_lib.h.var +++ b/openmp/runtime/src/include/omp_lib.h.var @@ -741,10 +741,10 @@ integer(c_int), value :: device_num end function - function omp_target_memset_async(ptr, val, count, device_num, & - depobj_count, depobj_list) bind(c) + function omp_target_memset_async(ptr, val, count, device_num, & + & depobj_count, depobj_list) bind(c) use, intrinsic :: iso_c_binding, only : c_ptr, c_int, c_size_t - use omp_lib_kinds + import type(c_ptr) :: omp_target_memset_async type(c_ptr), value :: ptr integer(c_int), value :: val diff --git a/openmp/runtime/src/kmp_affinity.cpp b/openmp/runtime/src/kmp_affinity.cpp index 7009730a49b..6a41d34b023 100644 --- a/openmp/runtime/src/kmp_affinity.cpp +++ b/openmp/runtime/src/kmp_affinity.cpp @@ -127,8 +127,12 @@ const char *__kmp_hw_get_catalog_string(kmp_hw_t type, bool plural) { return ((plural) ? KMP_I18N_STR(Threads) : KMP_I18N_STR(Thread)); case KMP_HW_PROC_GROUP: return ((plural) ? KMP_I18N_STR(ProcGroups) : KMP_I18N_STR(ProcGroup)); + case KMP_HW_UNKNOWN: + case KMP_HW_LAST: + return KMP_I18N_STR(Unknown); } - return KMP_I18N_STR(Unknown); + KMP_ASSERT2(false, "Unhandled kmp_hw_t enumeration"); + KMP_BUILTIN_UNREACHABLE; } const char *__kmp_hw_get_keyword(kmp_hw_t type, bool plural) { @@ -157,13 +161,18 @@ const char *__kmp_hw_get_keyword(kmp_hw_t type, bool plural) { return ((plural) ? "threads" : "thread"); case KMP_HW_PROC_GROUP: return ((plural) ? "proc_groups" : "proc_group"); + case KMP_HW_UNKNOWN: + case KMP_HW_LAST: + return ((plural) ? "unknowns" : "unknown"); } - return ((plural) ? "unknowns" : "unknown"); + KMP_ASSERT2(false, "Unhandled kmp_hw_t enumeration"); + KMP_BUILTIN_UNREACHABLE; } const char *__kmp_hw_get_core_type_string(kmp_hw_core_type_t type) { switch (type) { case KMP_HW_CORE_TYPE_UNKNOWN: + case KMP_HW_MAX_NUM_CORE_TYPES: return "unknown"; #if KMP_ARCH_X86 || KMP_ARCH_X86_64 case KMP_HW_CORE_TYPE_ATOM: @@ -172,7 +181,8 @@ const char *__kmp_hw_get_core_type_string(kmp_hw_core_type_t type) { return "Intel(R) Core(TM) processor"; #endif } - return "unknown"; + KMP_ASSERT2(false, "Unhandled kmp_hw_core_type_t enumeration"); + KMP_BUILTIN_UNREACHABLE; } #if KMP_AFFINITY_SUPPORTED @@ -1238,17 +1248,18 @@ bool kmp_topology_t::filter_hw_subset() { struct core_type_indexer { int operator()(const kmp_hw_thread_t &t) const { switch (t.attrs.get_core_type()) { + case KMP_HW_CORE_TYPE_UNKNOWN: + case KMP_HW_MAX_NUM_CORE_TYPES: + return 0; #if KMP_ARCH_X86 || KMP_ARCH_X86_64 case KMP_HW_CORE_TYPE_ATOM: return 1; case KMP_HW_CORE_TYPE_CORE: return 2; #endif - case KMP_HW_CORE_TYPE_UNKNOWN: - return 0; } - KMP_ASSERT(0); - return 0; + KMP_ASSERT2(false, "Unhandled kmp_hw_thread_t enumeration"); + KMP_BUILTIN_UNREACHABLE; } }; struct core_eff_indexer { diff --git a/openmp/runtime/src/kmp_barrier.cpp b/openmp/runtime/src/kmp_barrier.cpp index 281b8e9c288..e9ab15f1723 100644 --- a/openmp/runtime/src/kmp_barrier.cpp +++ b/openmp/runtime/src/kmp_barrier.cpp @@ -2403,11 +2403,11 @@ void __kmp_fork_barrier(int gtid, int tid) { #if USE_ITT_BUILD void *itt_sync_obj = NULL; #endif /* USE_ITT_BUILD */ +#ifdef KMP_DEBUG if (team) - - KA_TRACE(10, ("__kmp_fork_barrier: T#%d(%d:%d) has arrived\n", gtid, - (team != NULL) ? team->t.t_id : -1, tid)); - + KA_TRACE(10, ("__kmp_fork_barrier: T#%d(%d:%d) has arrived\n", gtid, + (team != NULL) ? team->t.t_id : -1, tid)); +#endif // th_team pointer only valid for primary thread here if (KMP_MASTER_TID(tid)) { #if USE_ITT_BUILD && USE_ITT_NOTIFY diff --git a/openmp/runtime/src/kmp_io.cpp b/openmp/runtime/src/kmp_io.cpp index 578e6e671cd..0c52662bc23 100644 --- a/openmp/runtime/src/kmp_io.cpp +++ b/openmp/runtime/src/kmp_io.cpp @@ -50,24 +50,6 @@ static HANDLE __kmp_stderr = NULL; static int __kmp_console_exists = FALSE; static kmp_str_buf_t __kmp_console_buf; -static int is_console(void) { - char buffer[128]; - DWORD rc = 0; - DWORD err = 0; - // Try to get console title. - SetLastError(0); - // GetConsoleTitle does not reset last error in case of success or short - // buffer, so we need to clear it explicitly. - rc = GetConsoleTitle(buffer, sizeof(buffer)); - if (rc == 0) { - // rc == 0 means getting console title failed. Let us find out why. - err = GetLastError(); - // err == 0 means buffer too short (we suppose console exists). - // In Window applications we usually have err == 6 (invalid handle). - } - return rc > 0 || err == 0; -} - void __kmp_close_console(void) { /* wait until user presses return before closing window */ /* TODO only close if a window was opened */ @@ -84,7 +66,6 @@ void __kmp_close_console(void) { static void __kmp_redirect_output(void) { __kmp_acquire_bootstrap_lock(&__kmp_console_lock); - (void)is_console; if (!__kmp_console_exists) { HANDLE ho; HANDLE he; diff --git a/openmp/runtime/src/kmp_os.h b/openmp/runtime/src/kmp_os.h index 6862fd89b63..a0552dd930a 100644 --- a/openmp/runtime/src/kmp_os.h +++ b/openmp/runtime/src/kmp_os.h @@ -306,6 +306,8 @@ template <> struct traits_t { !KMP_MIC) #if KMP_OS_WINDOWS +// Don't include everything related to NT status code, we'll do that explicitly +#define WIN32_NO_STATUS #include static inline int KMP_GET_PAGE_SIZE(void) { @@ -1297,4 +1299,18 @@ extern void *__kmp_lookup_symbol(const char *name, bool next = false); #define KMP_DLSYM_NEXT(name) dlsym(RTLD_NEXT, name) #endif +// MSVC doesn't have this, but clang/clang-cl does. +#ifndef __has_builtin +#define __has_builtin(x) 0 +#endif + +// Same as LLVM_BUILTIN_UNREACHABLE. States that it is UB to reach this point. +#if __has_builtin(__builtin_unreachable) || defined(__GNUC__) +#define KMP_BUILTIN_UNREACHABLE __builtin_unreachable() +#elif defined(_MSC_VER) +#define KMP_BUILTIN_UNREACHABLE __assume(false) +#else +#define KMP_BUILTIN_UNREACHABLE +#endif + #endif /* KMP_OS_H */ diff --git a/openmp/runtime/src/kmp_settings.cpp b/openmp/runtime/src/kmp_settings.cpp index 30a4c05fe76..d2157b10b78 100644 --- a/openmp/runtime/src/kmp_settings.cpp +++ b/openmp/runtime/src/kmp_settings.cpp @@ -873,6 +873,10 @@ static void __kmp_stg_print_wait_policy(kmp_str_buf_t *buffer, char const *name, case library_throughput: { value = "PASSIVE"; } break; + case library_none: + case library_serial: { + value = NULL; + } break; } } else { switch (__kmp_library) { @@ -885,6 +889,9 @@ static void __kmp_stg_print_wait_policy(kmp_str_buf_t *buffer, char const *name, case library_throughput: { value = "throughput"; } break; + case library_none: { + value = NULL; + } break; } } if (value != NULL) { @@ -2004,6 +2011,7 @@ static inline const char * __kmp_hw_get_core_type_keyword(kmp_hw_core_type_t type) { switch (type) { case KMP_HW_CORE_TYPE_UNKNOWN: + case KMP_HW_MAX_NUM_CORE_TYPES: return "unknown"; #if KMP_ARCH_X86 || KMP_ARCH_X86_64 case KMP_HW_CORE_TYPE_ATOM: @@ -2012,7 +2020,8 @@ __kmp_hw_get_core_type_keyword(kmp_hw_core_type_t type) { return "intel_core"; #endif } - return "unknown"; + KMP_ASSERT2(false, "Unhandled kmp_hw_core_type_t enumeration"); + KMP_BUILTIN_UNREACHABLE; } #if KMP_AFFINITY_SUPPORTED @@ -4428,6 +4437,10 @@ static void __kmp_stg_print_omp_schedule(kmp_str_buf_t *buffer, case kmp_sch_auto: __kmp_str_buf_print(buffer, "%s,%d'\n", "auto", __kmp_chunk); break; + default: + KMP_ASSERT2(false, "Unhandled sched_type enumeration"); + KMP_BUILTIN_UNREACHABLE; + break; } } else { switch (sched) { @@ -4453,6 +4466,10 @@ static void __kmp_stg_print_omp_schedule(kmp_str_buf_t *buffer, case kmp_sch_auto: __kmp_str_buf_print(buffer, "%s'\n", "auto"); break; + default: + KMP_ASSERT2(false, "Unhandled sched_type enumeration"); + KMP_BUILTIN_UNREACHABLE; + break; } } } // __kmp_stg_print_omp_schedule diff --git a/openmp/runtime/src/kmp_wait_release.h b/openmp/runtime/src/kmp_wait_release.h index 3fcae5687d1..12d5d0677a9 100644 --- a/openmp/runtime/src/kmp_wait_release.h +++ b/openmp/runtime/src/kmp_wait_release.h @@ -1038,15 +1038,9 @@ static inline void __kmp_null_resume_wrapper(kmp_info_t *thr) { case flag_oncore: __kmp_resume_oncore(gtid, RCAST(kmp_flag_oncore *, flag)); break; -#ifdef KMP_DEBUG case flag_unset: KF_TRACE(100, ("__kmp_null_resume_wrapper: flag type %d is unset\n", type)); break; - default: - KF_TRACE(100, ("__kmp_null_resume_wrapper: flag type %d does not match any " - "known flag type\n", - type)); -#endif } } diff --git a/openmp/runtime/src/z_Windows_NT_util.cpp b/openmp/runtime/src/z_Windows_NT_util.cpp index 9e264ab45b8..d75b48b2c1b 100644 --- a/openmp/runtime/src/z_Windows_NT_util.cpp +++ b/openmp/runtime/src/z_Windows_NT_util.cpp @@ -22,6 +22,7 @@ number of running threads in the system. */ #include // UNICODE_STRING +#undef WIN32_NO_STATUS #include #include #ifdef _MSC_VER @@ -1635,7 +1636,7 @@ int __kmp_get_load_balance(int max) { // threads on all cores. So, we don't consider the running threads of this // process. if (pid != 0) { - for (int i = 0; i < num; ++i) { + for (ULONG i = 0; i < num; ++i) { THREAD_STATE state = spi->Threads[i].State; // Count threads that have Ready or Running state. // !!! TODO: Why comment does not match the code???