From 79c1a0199fef91b73be95c7fea26dc2a17d8b38a Mon Sep 17 00:00:00 2001 From: Conrad Meyer Date: Thu, 29 Oct 2015 04:16:28 +0000 Subject: [PATCH] ntb: Do not attempt to set write-combining on MWs AMD64 pmap assumes ranges will be in the DMAP, which isn't necessarily true for NTB memory windows (especially 64-bit BARs). Suggested by: pmap_change_attr_locked -> kassert_panic Sponsored by: EMC / Isilon Storage Division --- sys/dev/ntb/ntb_hw/ntb_hw.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/sys/dev/ntb/ntb_hw/ntb_hw.c b/sys/dev/ntb/ntb_hw/ntb_hw.c index e918d263ea5..f5dbc3290d2 100644 --- a/sys/dev/ntb/ntb_hw/ntb_hw.c +++ b/sys/dev/ntb/ntb_hw/ntb_hw.c @@ -755,9 +755,13 @@ map_memory_window_bar(struct ntb_softc *ntb, struct ntb_pci_bar_info *bar) save_bar_parameters(bar); } +#if 0 /* XXX: amd64 pmap_change_attr() assumes region lies in DMAP. */ /* Mark bar region as write combining to improve performance. */ rc = pmap_change_attr((vm_offset_t)bar->vbase, bar->size, VM_MEMATTR_WRITE_COMBINING); +#else + rc = EINVAL; +#endif print_map_success(ntb, bar, "mw"); if (rc == 0) device_printf(ntb->device,