From 75c4ab0ae9fb8914fdff77cc6fbb2181541ddbad Mon Sep 17 00:00:00 2001 From: Pyun YongHyeon Date: Sun, 29 Nov 2009 19:58:35 +0000 Subject: [PATCH] MFC r199012: Add preliminary Yukon Ultra 2 support(88E8057). The controller looks very similar to Yukon EC Ultra. Tested by: kalin m ( kalin <> el dot net ) --- sys/dev/msk/if_msk.c | 14 ++++++++++++-- sys/dev/msk/if_mskreg.h | 3 +++ 2 files changed, 15 insertions(+), 2 deletions(-) diff --git a/sys/dev/msk/if_msk.c b/sys/dev/msk/if_msk.c index 061d8c79d46..6afd4e04353 100644 --- a/sys/dev/msk/if_msk.c +++ b/sys/dev/msk/if_msk.c @@ -222,6 +222,8 @@ static struct msk_product { "Marvell Yukon 88E8071 Gigabit Ethernet" }, { VENDORID_MARVELL, DEVICEID_MRVL_436C, "Marvell Yukon 88E8072 Gigabit Ethernet" }, + { VENDORID_MARVELL, DEVICEID_MRVL_4380, + "Marvell Yukon 88E8057 Gigabit Ethernet" }, { VENDORID_DLINK, DEVICEID_DLINK_DGE550SX, "D-Link 550SX Gigabit Ethernet" }, { VENDORID_DLINK, DEVICEID_DLINK_DGE560SX, @@ -236,7 +238,9 @@ static const char *model_name[] = { "Yukon EX", "Yukon EC", "Yukon FE", - "Yukon FE+" + "Yukon FE+", + "Yukon Supreme", + "Yukon Ultra 2" }; static int mskc_probe(device_t); @@ -1143,6 +1147,7 @@ msk_phy_power(struct msk_softc *sc, int mode) case CHIP_ID_YUKON_EC_U: case CHIP_ID_YUKON_EX: case CHIP_ID_YUKON_FE_P: + case CHIP_ID_YUKON_UL_2: CSR_WRITE_2(sc, B0_CTST, Y2_HW_WOL_OFF); /* Enable all clocks. */ @@ -1646,7 +1651,8 @@ mskc_attach(device_t dev) sc->msk_hw_rev = (CSR_READ_1(sc, B2_MAC_CFG) >> 4) & 0x0f; /* Bail out if chip is not recognized. */ if (sc->msk_hw_id < CHIP_ID_YUKON_XL || - sc->msk_hw_id > CHIP_ID_YUKON_FE_P) { + sc->msk_hw_id > CHIP_ID_YUKON_UL_2 || + sc->msk_hw_id == CHIP_ID_YUKON_SUPR) { device_printf(dev, "unknown device: id=0x%02x, rev=0x%02x\n", sc->msk_hw_id, sc->msk_hw_rev); mtx_destroy(&sc->msk_mtx); @@ -1745,6 +1751,10 @@ mskc_attach(device_t dev) sc->msk_clock = 156; /* 156 Mhz */ sc->msk_pflags |= MSK_FLAG_JUMBO; break; + case CHIP_ID_YUKON_UL_2: + sc->msk_clock = 156; /* 156 Mhz */ + sc->msk_pflags |= MSK_FLAG_JUMBO; + break; default: sc->msk_clock = 156; /* 156 Mhz */ break; diff --git a/sys/dev/msk/if_mskreg.h b/sys/dev/msk/if_mskreg.h index b42a01fe1a5..2f4e2164584 100644 --- a/sys/dev/msk/if_mskreg.h +++ b/sys/dev/msk/if_mskreg.h @@ -144,6 +144,7 @@ #define DEVICEID_MRVL_436A 0x436A #define DEVICEID_MRVL_436B 0x436B #define DEVICEID_MRVL_436C 0x436C +#define DEVICEID_MRVL_4380 0x4380 /* * D-Link gigabit ethernet device ID @@ -891,6 +892,8 @@ #define CHIP_ID_YUKON_EC 0xb6 /* Chip ID for YUKON-2 EC */ #define CHIP_ID_YUKON_FE 0xb7 /* Chip ID for YUKON-2 FE */ #define CHIP_ID_YUKON_FE_P 0xb8 /* Chip ID for YUKON-2 FE+ */ +#define CHIP_ID_YUKON_SUPR 0xb9 /* Chip ID for YUKON-2 Supreme */ +#define CHIP_ID_YUKON_UL_2 0xba /* Chip ID for YUKON-2 Ultra 2 */ #define CHIP_REV_YU_XL_A0 0 /* Chip Rev. for Yukon-2 A0 */ #define CHIP_REV_YU_XL_A1 1 /* Chip Rev. for Yukon-2 A1 */