From 752a2fe776fafe55c05928fc214df95d20d9f120 Mon Sep 17 00:00:00 2001
From: "Jayachandran C." <jchandra@FreeBSD.org>
Date: Tue, 27 Mar 2012 07:51:42 +0000
Subject: [PATCH] Update the L1D cache flush sequence when enabling threads.

Added more comments to the code.
---
 sys/mips/nlm/mpreset.S | 14 +++++++-------
 1 file changed, 7 insertions(+), 7 deletions(-)

diff --git a/sys/mips/nlm/mpreset.S b/sys/mips/nlm/mpreset.S
index b35df6350a3..cd05e759cd8 100644
--- a/sys/mips/nlm/mpreset.S
+++ b/sys/mips/nlm/mpreset.S
@@ -55,24 +55,24 @@
 	.set	noreorder
 	li	$8, LSU_DEBUG_DATA0 /* use register number to handle */
 	li	$9, LSU_DEBUG_ADDR  /* different ABIs */
-	li	t2, 0
-	li	t3, 0x200
+	li	t2, 0		/* index */
+	li	t3, 0x1000	/* loop count, 512 sets * 8 whatever? */
 1:
 	sll	v0, t2, 5
 	MTCR(0, 8)
-	ori	v1, v0, 0x3
+	ori	v1, v0, 0x3	/* way0 | write_enable | write_active */
 	MTCR(3, 9)
 2:
 	MFCR(3, 9)
-	andi	v1, 0x1
+	andi	v1, 0x1		/* wait for write_active == 0 */
 	bnez	v1, 2b
 	nop
 	MTCR(0, 8)
-	ori	v1, v0, 0x7
+	ori	v1, v0, 0x7	/* way1 | write_enable | write_active */
 	MTCR(3, 9)
 3:
 	MFCR(3, 9)
-	andi	v1, 0x1
+	andi	v1, 0x1		/* wait for write_active == 0 */
 	bnez	v1, 3b
 	nop
 	addi	t2, 1
@@ -195,7 +195,7 @@ LEAF(xlp_enable_threads)
 	mfc0	t1, MIPS_COP_0_STATUS
 
 	move	sp, t0		/* Restore the real SP */
-	jr	ra
+	jr.hb	ra
 	nop
 END(xlp_enable_threads)
 #endif