mirror of
https://github.com/opnsense/src.git
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Add initial support for the RK356X SOC Ethernet QoS controller (DesignWare)
Eqos driver works in all combinations of single/double ports with different layout.
This commit is contained in:
Søren Schmidt
Ganbold Tsagaankhuu
parent
777e472cd8
commit
702b53dd2a
6 changed files with 2008 additions and 0 deletions
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@ -208,6 +208,10 @@ dev/dwc/if_dwc_if.m optional fdt dwc_rk soc_rockchip_rk3328 | fdt dwc_rk soc_
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dev/enetc/enetc_mdio.c optional enetc soc_nxp_ls
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dev/enetc/if_enetc.c optional enetc iflib pci fdt soc_nxp_ls
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dev/eqos/if_eqos.c optional eqos
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dev/eqos/if_eqos_if.m optional eqos
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dev/eqos/if_eqos_fdt.c optional eqos fdt
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dev/etherswitch/felix/felix.c optional enetc etherswitch fdt felix pci soc_nxp_ls
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dev/firmware/arm/scmi.c optional fdt scmi
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1292
sys/dev/eqos/if_eqos.c
Normal file
1292
sys/dev/eqos/if_eqos.c
Normal file
File diff suppressed because it is too large
Load diff
255
sys/dev/eqos/if_eqos_fdt.c
Normal file
255
sys/dev/eqos/if_eqos_fdt.c
Normal file
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@ -0,0 +1,255 @@
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/*-
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* SPDX-License-Identifier: BSD-2-Clause-FreeBSD
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*
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* Copyright (c) 2022 Soren Schmidt <sos@deepcore.dk>
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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||||
* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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||||
* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* $Id: eqos_fdt.c 1049 2022-12-03 14:25:46Z sos $
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*/
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#include "opt_platform.h"
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#include <sys/cdefs.h>
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#include <sys/param.h>
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#include <sys/bus.h>
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#include <sys/kernel.h>
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#include <sys/module.h>
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#include <sys/systm.h>
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#include <sys/endian.h>
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#include <sys/hash.h>
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#include <sys/gpio.h>
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#include <sys/rman.h>
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#include <sys/socket.h>
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#include <machine/bus.h>
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#include <net/if.h>
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#include <net/if_media.h>
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#include <dev/mii/mii.h>
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#include <dev/mii/miivar.h>
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#include <dev/ofw/ofw_bus.h>
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#include <dev/ofw/ofw_bus_subr.h>
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#include <dev/extres/hwreset/hwreset.h>
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#include <dev/extres/regulator/regulator.h>
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#include <dev/extres/syscon/syscon.h>
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#include <dev/eqos/if_eqos_var.h>
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#include "if_eqos_if.h"
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#include "syscon_if.h"
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#include "gpio_if.h"
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#include "rk_otp_if.h"
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#define RK356XGMAC0 0xfe2a0000
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#define RK356XGMAC1 0xfe010000
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#define RK3588GMAC0 0xfe1b0000
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#define RK3588GMAC1 0xfe1c0000
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#define EQOS_GRF_GMAC0 0x0380
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#define EQOS_GRF_GMAC1 0x0388
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#define EQOS_CON0_OFFSET 0
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#define EQOS_CON1_OFFSET 4
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#define EQOS_GMAC_PHY_INTF_SEL_RGMII 0x00fc0010
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#define EQOS_GMAC_PHY_INTF_SEL_RMII 0x00fc0040
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#define EQOS_GMAC_RXCLK_DLY_ENABLE 0x00020002
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#define EQOS_GMAC_RXCLK_DLY_DISABLE 0x00020000
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#define EQOS_GMAC_TXCLK_DLY_ENABLE 0x00010001
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#define EQOS_GMAC_TXCLK_DLY_DISABLE 0x00010000
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#define EQOS_GMAC_CLK_RX_DL_CFG(val) (0x7f000000 | val << 8)
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#define EQOS_GMAC_CLK_TX_DL_CFG(val) (0x007f0000 | val)
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#define WR4(sc, o, v) bus_write_4(sc->res[EQOS_RES_MEM], (o), (v))
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static const struct ofw_compat_data compat_data[] = {
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{"snps,dwmac-4.20a", 1},
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{ NULL, 0 }
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};
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static int
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eqos_phy_reset(device_t dev)
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{
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pcell_t gpio_prop[4];
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pcell_t delay_prop[3];
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phandle_t node, gpio_node;
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device_t gpio;
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uint32_t pin, flags;
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uint32_t pin_value;
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node = ofw_bus_get_node(dev);
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if (OF_getencprop(node, "snps,reset-gpio",
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gpio_prop, sizeof(gpio_prop)) <= 0)
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return (0);
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if (OF_getencprop(node, "snps,reset-delays-us",
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delay_prop, sizeof(delay_prop)) <= 0) {
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device_printf(dev,
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"Wrong property for snps,reset-delays-us");
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return (ENXIO);
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}
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gpio_node = OF_node_from_xref(gpio_prop[0]);
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if ((gpio = OF_device_from_xref(gpio_prop[0])) == NULL) {
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device_printf(dev,
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"Can't find gpio controller for phy reset\n");
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return (ENXIO);
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}
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if (GPIO_MAP_GPIOS(gpio, node, gpio_node,
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nitems(gpio_prop) - 1,
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gpio_prop + 1, &pin, &flags) != 0) {
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device_printf(dev, "Can't map gpio for phy reset\n");
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return (ENXIO);
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}
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pin_value = GPIO_PIN_LOW;
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if (OF_hasprop(node, "snps,reset-active-low"))
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pin_value = GPIO_PIN_HIGH;
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GPIO_PIN_SETFLAGS(gpio, pin, GPIO_PIN_OUTPUT);
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GPIO_PIN_SET(gpio, pin, pin_value);
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DELAY(delay_prop[0]);
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GPIO_PIN_SET(gpio, pin, !pin_value);
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DELAY(delay_prop[1]);
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GPIO_PIN_SET(gpio, pin, pin_value);
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DELAY(delay_prop[2]);
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return (0);
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}
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static int
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eqos_fdt_init(device_t dev)
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{
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struct eqos_softc *sc = device_get_softc(dev);
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phandle_t node = ofw_bus_get_node(dev);
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hwreset_t eqos_reset;
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regulator_t eqos_supply;
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uint32_t rx_delay, tx_delay;
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uint8_t buffer[16];
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if (OF_hasprop(node, "rockchip,grf") &&
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syscon_get_by_ofw_property(dev, node, "rockchip,grf", &sc->grf)) {
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device_printf(dev, "cannot get grf driver handle\n");
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return (ENXIO);
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}
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/* figure out if gmac0 or gmac1 offset */
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switch (rman_get_start(sc->res[EQOS_RES_MEM])) {
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case RK356XGMAC0: /* RK356X gmac0 */
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sc->grf_offset = EQOS_GRF_GMAC0;
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break;
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case RK356XGMAC1: /* RK356X gmac1 */
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sc->grf_offset = EQOS_GRF_GMAC1;
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break;
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case RK3588GMAC0: /* RK3588 gmac0 */
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case RK3588GMAC1: /* RK3588 gmac1 */
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default:
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device_printf(dev, "Unknown eqos address\n");
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return (ENXIO);
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}
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if (hwreset_get_by_ofw_idx(dev, node, 0, &eqos_reset)) {
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device_printf(dev, "cannot get reset\n");
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return (ENXIO);
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}
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else
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hwreset_assert(eqos_reset);
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sc->csr_clock = 125000000;
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sc->csr_clock_range = GMAC_MAC_MDIO_ADDRESS_CR_100_150;
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if (OF_getencprop(node, "tx_delay", &tx_delay, sizeof(tx_delay)) <= 0)
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tx_delay = 0x30;
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if (OF_getencprop(node, "rx_delay", &rx_delay, sizeof(rx_delay)) <= 0)
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rx_delay = 0x10;
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SYSCON_WRITE_4(sc->grf, sc->grf_offset + EQOS_CON0_OFFSET,
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EQOS_GMAC_CLK_RX_DL_CFG(rx_delay) |
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EQOS_GMAC_CLK_TX_DL_CFG(tx_delay));
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SYSCON_WRITE_4(sc->grf, sc->grf_offset + EQOS_CON1_OFFSET,
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EQOS_GMAC_PHY_INTF_SEL_RGMII |
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EQOS_GMAC_RXCLK_DLY_ENABLE |
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EQOS_GMAC_TXCLK_DLY_ENABLE);
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if (!regulator_get_by_ofw_property(dev, 0, "phy-supply",
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&eqos_supply)) {
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if (regulator_enable(eqos_supply))
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device_printf(dev, "cannot enable 'phy' regulator\n");
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}
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else
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device_printf(dev, "no phy-supply property\n");
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if (eqos_phy_reset(dev))
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return (ENXIO);
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if (eqos_reset)
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hwreset_deassert(eqos_reset);
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/* set the MAC address if we have OTP data handy */
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if (!RK_OTP_READ(dev, buffer, 0, sizeof(buffer))) {
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uint32_t mac;
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mac = hash32_buf(buffer, sizeof(buffer), HASHINIT);
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WR4(sc, GMAC_MAC_ADDRESS0_LOW,
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htobe32((mac & 0xffffff00) | 0x22));
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mac = hash32_buf(buffer, sizeof(buffer), mac);
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WR4(sc, GMAC_MAC_ADDRESS0_HIGH,
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htobe16((mac & 0x0000ffff) + (device_get_unit(dev) << 8)));
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}
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return (0);
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}
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static int
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eqos_fdt_probe(device_t dev)
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{
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if (!ofw_bus_status_okay(dev))
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return (ENXIO);
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if (ofw_bus_search_compatible(dev, compat_data)->ocd_data == 0)
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return (ENXIO);
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device_set_desc(dev, "DesignWare EQOS Gigabit ethernet");
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return (BUS_PROBE_DEFAULT);
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}
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static device_method_t eqos_fdt_methods[] = {
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/* Device interface */
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DEVMETHOD(device_probe, eqos_fdt_probe),
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/* EQOS interface */
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DEVMETHOD(eqos_init, eqos_fdt_init),
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DEVMETHOD_END
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};
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DEFINE_CLASS_1(eqos, eqos_fdt_driver, eqos_fdt_methods,
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sizeof(struct eqos_softc), eqos_driver);
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DRIVER_MODULE(eqos, simplebus, eqos_fdt_driver, 0, 0);
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MODULE_DEPEND(eqos, ether, 1, 1, 1);
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MODULE_DEPEND(eqos, miibus, 1, 1, 1);
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63
sys/dev/eqos/if_eqos_if.m
Normal file
63
sys/dev/eqos/if_eqos_if.m
Normal file
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@ -0,0 +1,63 @@
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#-
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# SPDX-License-Identifier: BSD-2-Clause-FreeBSD
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#
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# Copyright (c) 2022 Soren Schmidt <sos@deepcore.dk>
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# All rights reserved.
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#
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# Redistribution and use in source and binary forms, with or without
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# modification, are permitted provided that the following conditions
|
||||
# are met:
|
||||
# 1. Redistributions of source code must retain the above copyright
|
||||
# notice, this list of conditions and the following disclaimer.
|
||||
# 2. Redistributions in binary form must reproduce the above copyright
|
||||
# notice, this list of conditions and the following disclaimer in the
|
||||
# documentation and/or other materials provided with the distribution.
|
||||
#
|
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# THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
|
||||
# ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
# ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
|
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# FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
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# DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
|
||||
# OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
|
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# HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
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# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
|
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# OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
|
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# SUCH DAMAGE.
|
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#
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# $Id: eqos_if.m 921 2022-08-09 18:38:11Z sos $
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#
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INTERFACE eqos;
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CODE {
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static int
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eqos_default_init(device_t dev)
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{
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return (0);
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}
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static int
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eqos_default_set_speed(device_t dev, int speed)
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{
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return (0);
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}
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};
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HEADER {
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};
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#
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# Initialize SoC specific registers.
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#
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METHOD int init {
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device_t dev;
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} DEFAULT eqos_default_init;
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#
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# Signal media change to a specific hardware
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#
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METHOD int set_speed {
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device_t dev;
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int speed;
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} DEFAULT eqos_default_set_speed;
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295
sys/dev/eqos/if_eqos_reg.h
Normal file
295
sys/dev/eqos/if_eqos_reg.h
Normal file
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@ -0,0 +1,295 @@
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/*-
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* SPDX-License-Identifier: BSD-2-Clause-FreeBSD
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*
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* Copyright (c) 2022 Jared McNeill <jmcneill@invisible.ca>
|
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* All rights reserved.
|
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*
|
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* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
|
||||
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
|
||||
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
|
||||
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
|
||||
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
|
||||
* SUCH DAMAGE.
|
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*
|
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* $Id: eqos_reg.h 921 2022-08-09 18:38:11Z sos $
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*/
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/*
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* DesignWare Ethernet Quality-of-Service controller
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*/
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#ifndef _EQOS_REG_H
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#define _EQOS_REG_H
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#define GMAC_MAC_CONFIGURATION 0x0000
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#define GMAC_MAC_CONFIGURATION_CST (1U << 21)
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#define GMAC_MAC_CONFIGURATION_ACS (1U << 20)
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#define GMAC_MAC_CONFIGURATION_BE (1U << 18)
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#define GMAC_MAC_CONFIGURATION_JD (1U << 17)
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#define GMAC_MAC_CONFIGURATION_JE (1U << 16)
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#define GMAC_MAC_CONFIGURATION_PS (1U << 15)
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#define GMAC_MAC_CONFIGURATION_FES (1U << 14)
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#define GMAC_MAC_CONFIGURATION_DM (1U << 13)
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#define GMAC_MAC_CONFIGURATION_DCRS (1U << 9)
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#define GMAC_MAC_CONFIGURATION_TE (1U << 1)
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#define GMAC_MAC_CONFIGURATION_RE (1U << 0)
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#define GMAC_MAC_EXT_CONFIGURATION 0x0004
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#define GMAC_MAC_PACKET_FILTER 0x0008
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#define GMAC_MAC_PACKET_FILTER_HPF (1U << 10)
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#define GMAC_MAC_PACKET_FILTER_PCF_MASK (3U << 6)
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#define GMAC_MAC_PACKET_FILTER_PCF_ALL (2U << 6)
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#define GMAC_MAC_PACKET_FILTER_DBF (1U << 5)
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#define GMAC_MAC_PACKET_FILTER_PM (1U << 4)
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#define GMAC_MAC_PACKET_FILTER_HMC (1U << 2)
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#define GMAC_MAC_PACKET_FILTER_HUC (1U << 1)
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#define GMAC_MAC_PACKET_FILTER_PR (1U << 0)
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#define GMAC_MAC_WATCHDOG_TIMEOUT 0x000C
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#define GMAC_MAC_HASH_TABLE_REG0 0x0010
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#define GMAC_MAC_HASH_TABLE_REG1 0x0014
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#define GMAC_MAC_VLAN_TAG 0x0050
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#define GMAC_MAC_Q0_TX_FLOW_CTRL 0x0070
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#define GMAC_MAC_Q0_TX_FLOW_CTRL_PT_SHIFT 16
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#define GMAC_MAC_Q0_TX_FLOW_CTRL_TFE (1U << 1)
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#define GMAC_MAC_RX_FLOW_CTRL 0x0090
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#define GMAC_MAC_RX_FLOW_CTRL_RFE (1U << 0)
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#define GMAC_RXQ_CTRL0 0x00A0
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#define GMAC_RXQ_CTRL0_EN_MASK 0x3
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#define GMAC_RXQ_CTRL0_EN_DCB 0x2
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#define GMAC_RXQ_CTRL1 0x00A4
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#define GMAC_MAC_INTERRUPT_STATUS 0x00B0
|
||||
#define GMAC_MAC_INTERRUPT_ENABLE 0x00B4
|
||||
#define GMAC_MAC_RX_TX_STATUS 0x00B8
|
||||
#define GMAC_MAC_RX_TX_STATUS_RWT (1U << 8)
|
||||
#define GMAC_MAC_RX_TX_STATUS_EXCOL (1U << 5)
|
||||
#define GMAC_MAC_RX_TX_STATUS_LCOL (1U << 4)
|
||||
#define GMAC_MAC_RX_TX_STATUS_EXDEF (1U << 3)
|
||||
#define GMAC_MAC_RX_TX_STATUS_LCARR (1U << 2)
|
||||
#define GMAC_MAC_RX_TX_STATUS_NCARR (1U << 1)
|
||||
#define GMAC_MAC_RX_TX_STATUS_TJT (1U << 0)
|
||||
#define GMAC_MAC_PMT_CONTROL_STATUS 0x00C0
|
||||
#define GMAC_MAC_RWK_PACKET_FILTER 0x00C4
|
||||
#define GMAC_MAC_LPI_CONTROL_STATUS 0x00D0
|
||||
#define GMAC_MAC_LPI_TIMERS_CONTROL 0x00D4
|
||||
#define GMAC_MAC_LPI_ENTRY_TIMER 0x00D8
|
||||
#define GMAC_MAC_1US_TIC_COUNTER 0x00DC
|
||||
#define GMAC_MAC_PHYIF_CONTROL_STATUS 0x00F8
|
||||
#define GMAC_MAC_VERSION 0x0110
|
||||
#define GMAC_MAC_VERSION_USERVER_SHIFT 8
|
||||
#define GMAC_MAC_VERSION_USERVER_MASK (0xFFU << GMAC_MAC_VERSION_USERVER_SHIFT)
|
||||
#define GMAC_MAC_VERSION_SNPSVER_MASK 0xFFU
|
||||
#define GMAC_MAC_DEBUG 0x0114
|
||||
#define GMAC_MAC_HW_FEATURE(n) (0x011C + 0x4 * (n))
|
||||
#define GMAC_MAC_HW_FEATURE1_ADDR64_SHIFT 14
|
||||
#define GMAC_MAC_HW_FEATURE1_ADDR64_MASK (0x3U << GMAC_MAC_HW_FEATURE1_ADDR64_SHIFT)
|
||||
#define GMAC_MAC_HW_FEATURE1_ADDR64_32BIT (0x0U << GMAC_MAC_HW_FEATURE1_ADDR64_SHIFT)
|
||||
#define GMAC_MAC_MDIO_ADDRESS 0x0200
|
||||
#define GMAC_MAC_MDIO_ADDRESS_PA_SHIFT 21
|
||||
#define GMAC_MAC_MDIO_ADDRESS_RDA_SHIFT 16
|
||||
#define GMAC_MAC_MDIO_ADDRESS_CR_SHIFT 8
|
||||
#define GMAC_MAC_MDIO_ADDRESS_CR_MASK (0x7U << GMAC_MAC_MDIO_ADDRESS_CR_SHIFT)
|
||||
#define GMAC_MAC_MDIO_ADDRESS_CR_60_100 (0U << GMAC_MAC_MDIO_ADDRESS_CR_SHIFT)
|
||||
#define GMAC_MAC_MDIO_ADDRESS_CR_100_150 (1U << GMAC_MAC_MDIO_ADDRESS_CR_SHIFT)
|
||||
#define GMAC_MAC_MDIO_ADDRESS_CR_20_35 (2U << GMAC_MAC_MDIO_ADDRESS_CR_SHIFT)
|
||||
#define GMAC_MAC_MDIO_ADDRESS_CR_35_60 (3U << GMAC_MAC_MDIO_ADDRESS_CR_SHIFT)
|
||||
#define GMAC_MAC_MDIO_ADDRESS_CR_150_250 (4U << GMAC_MAC_MDIO_ADDRESS_CR_SHIFT)
|
||||
#define GMAC_MAC_MDIO_ADDRESS_CR_250_300 (5U << GMAC_MAC_MDIO_ADDRESS_CR_SHIFT)
|
||||
#define GMAC_MAC_MDIO_ADDRESS_CR_300_500 (6U << GMAC_MAC_MDIO_ADDRESS_CR_SHIFT)
|
||||
#define GMAC_MAC_MDIO_ADDRESS_CR_500_800 (7U << GMAC_MAC_MDIO_ADDRESS_CR_SHIFT)
|
||||
#define GMAC_MAC_MDIO_ADDRESS_SKAP (1U << 4)
|
||||
#define GMAC_MAC_MDIO_ADDRESS_GOC_SHIFT 2
|
||||
#define GMAC_MAC_MDIO_ADDRESS_GOC_READ (3U << GMAC_MAC_MDIO_ADDRESS_GOC_SHIFT)
|
||||
#define GMAC_MAC_MDIO_ADDRESS_GOC_WRITE (1U << GMAC_MAC_MDIO_ADDRESS_GOC_SHIFT)
|
||||
#define GMAC_MAC_MDIO_ADDRESS_C45E (1U << 1)
|
||||
#define GMAC_MAC_MDIO_ADDRESS_GB (1U << 0)
|
||||
#define GMAC_MAC_MDIO_DATA 0x0204
|
||||
#define GMAC_MAC_CSR_SW_CTRL 0x0230
|
||||
#define GMAC_MAC_ADDRESS0_HIGH 0x0300
|
||||
#define GMAC_MAC_ADDRESS0_LOW 0x0304
|
||||
#define GMAC_MMC_CONTROL 0x0700
|
||||
#define GMAC_MMC_CONTROL_UCDBC (1U << 8)
|
||||
#define GMAC_MMC_CONTROL_CNTPRSTLVL (1U << 5)
|
||||
#define GMAC_MMC_CONTROL_CNTPRST (1U << 4)
|
||||
#define GMAC_MMC_CONTROL_CNTFREEZ (1U << 3)
|
||||
#define GMAC_MMC_CONTROL_RSTONRD (1U << 2)
|
||||
#define GMAC_MMC_CONTROL_CNTSTOPRO (1U << 1)
|
||||
#define GMAC_MMC_CONTROL_CNTRST (1U << 0)
|
||||
#define GMAC_MMC_RX_INTERRUPT 0x0704
|
||||
#define GMAC_MMC_TX_INTERRUPT 0x0708
|
||||
#define GMAC_MMC_RX_INTERRUPT_MASK 0x070C
|
||||
#define GMAC_MMC_TX_INTERRUPT_MASK 0x0710
|
||||
#define GMAC_TX_OCTET_COUNT_GOOD_BAD 0x0714
|
||||
#define GMAC_TX_PACKET_COUNT_GOOD_BAD 0x0718
|
||||
#define GMAC_TX_UNDERFLOW_ERROR_PACKETS 0x0748
|
||||
#define GMAC_TX_CARRIER_ERROR_PACKETS 0x0760
|
||||
#define GMAC_TX_OCTET_COUNT_GOOD 0x0764
|
||||
#define GMAC_TX_PACKET_COUNT_GOOD 0x0768
|
||||
#define GMAC_RX_PACKETS_COUNT_GOOD_BAD 0x0780
|
||||
#define GMAC_RX_OCTET_COUNT_GOOD_BAD 0x0784
|
||||
#define GMAC_RX_OCTET_COUNT_GOOD 0x0788
|
||||
#define GMAC_RX_MULTICAST_PACKETS_GOOD 0x0790
|
||||
#define GMAC_RX_CRC_ERROR_PACKETS 0x0794
|
||||
#define GMAC_RX_LENGTH_ERROR_PACKETS 0x07C8
|
||||
#define GMAC_RX_FIFO_OVERFLOW_PACKETS 0x07D4
|
||||
#define GMAC_MMC_IPC_RX_INTERRUPT_MASK 0x0800
|
||||
#define GMAC_MMC_IPC_RX_INTERRUPT 0x0808
|
||||
#define GMAC_RXIPV4_GOOD_PACKETS 0x0810
|
||||
#define GMAC_RXIPV4_HEADER_ERROR_PACKETS 0x0814
|
||||
#define GMAC_RXIPV6_GOOD_PACKETS 0x0824
|
||||
#define GMAC_RXIPV6_HEADER_ERROR_PACKETS 0x0828
|
||||
#define GMAC_RXUDP_ERROR_PACKETS 0x0834
|
||||
#define GMAC_RXTCP_ERROR_PACKETS 0x083C
|
||||
#define GMAC_RXICMP_ERROR_PACKETS 0x0844
|
||||
#define GMAC_RXIPV4_HEADER_ERROR_OCTETS 0x0854
|
||||
#define GMAC_RXIPV6_HEADER_ERROR_OCTETS 0x0868
|
||||
#define GMAC_RXUDP_ERROR_OCTETS 0x0874
|
||||
#define GMAC_RXTCP_ERROR_OCTETS 0x087C
|
||||
#define GMAC_RXICMP_ERROR_OCTETS 0x0884
|
||||
#define GMAC_MAC_TIMESTAMP_CONTROL 0x0B00
|
||||
#define GMAC_MAC_SUB_SECOND_INCREMENT 0x0B04
|
||||
#define GMAC_MAC_SYSTEM_TIME_SECS 0x0B08
|
||||
#define GMAC_MAC_SYSTEM_TIME_NS 0x0B0C
|
||||
#define GMAC_MAC_SYS_TIME_SECS_UPDATE 0x0B10
|
||||
#define GMAC_MAC_SYS_TIME_NS_UPDATE 0x0B14
|
||||
#define GMAC_MAC_TIMESTAMP_ADDEND 0x0B18
|
||||
#define GMAC_MAC_TIMESTAMP_STATUS 0x0B20
|
||||
#define GMAC_MAC_TX_TS_STATUS_NS 0x0B30
|
||||
#define GMAC_MAC_TX_TS_STATUS_SECS 0x0B34
|
||||
#define GMAC_MAC_AUXILIARY_CONTROL 0x0B40
|
||||
#define GMAC_MAC_AUXILIARY_TS_NS 0x0B48
|
||||
#define GMAC_MAC_AUXILIARY_TS_SECS 0x0B4C
|
||||
#define GMAC_MAC_TS_INGRESS_CORR_NS 0x0B58
|
||||
#define GMAC_MAC_TS_EGRESS_CORR_NS 0x0B5C
|
||||
#define GMAC_MAC_TS_INGRESS_LATENCY 0x0B68
|
||||
#define GMAC_MAC_TS_EGRESS_LATENCY 0x0B6C
|
||||
#define GMAC_MAC_PPS_CONTROL 0x0B70
|
||||
#define GMAC_MTL_DBG_CTL 0x0C08
|
||||
#define GMAC_MTL_DBG_STS 0x0C0C
|
||||
#define GMAC_MTL_FIFO_DEBUG_DATA 0x0C10
|
||||
#define GMAC_MTL_INTERRUPT_STATUS 0x0C20
|
||||
#define GMAC_MTL_INTERRUPT_STATUS_DBGIS (1U << 17)
|
||||
#define GMAC_MTL_INTERRUPT_STATUS_Q0IS (1U << 0)
|
||||
#define GMAC_MTL_TXQ0_OPERATION_MODE 0x0D00
|
||||
#define GMAC_MTL_TXQ0_OPERATION_MODE_TXQEN_SHIFT 2
|
||||
#define GMAC_MTL_TXQ0_OPERATION_MODE_TXQEN_MASK (0x3U << GMAC_MTL_TXQ0_OPERATION_MODE_TXQEN_SHIFT)
|
||||
#define GMAC_MTL_TXQ0_OPERATION_MODE_TXQEN_EN (2U << GMAC_MTL_TXQ0_OPERATION_MODE_TXQEN_SHIFT)
|
||||
#define GMAC_MTL_TXQ0_OPERATION_MODE_TSF (1U << 1)
|
||||
#define GMAC_MTL_TXQ0_OPERATION_MODE_FTQ (1U << 0)
|
||||
#define GMAC_MTL_TXQ0_UNDERFLOW 0x0D04
|
||||
#define GMAC_MTL_TXQ0_DEBUG 0x0D08
|
||||
#define GMAC_MTL_Q0_INTERRUPT_CTRL_STATUS 0x0D2C
|
||||
#define GMAC_MTL_Q0_INTERRUPT_CTRL_STATUS_RXOIE (1U << 24)
|
||||
#define GMAC_MTL_Q0_INTERRUPT_CTRL_STATUS_RXOVFIS (1U << 16)
|
||||
#define GMAC_MTL_Q0_INTERRUPT_CTRL_STATUS_TXUIE (1U << 8)
|
||||
#define GMAC_MTL_Q0_INTERRUPT_CTRL_STATUS_TXUNFIS (1U << 0)
|
||||
#define GMAC_MTL_RXQ0_OPERATION_MODE 0x0D30
|
||||
#define GMAC_MTL_RXQ0_OPERATION_MODE_RSF (1U << 5)
|
||||
#define GMAC_MTL_RXQ0_OPERATION_MODE_FEP (1U << 4)
|
||||
#define GMAC_MTL_RXQ0_OPERATION_MODE_FUP (1U << 3)
|
||||
#define GMAC_MTL_RXQ0_MISS_PKT_OVF_CNT 0x0D34
|
||||
#define GMAC_MTL_RXQ0_DEBUG 0x0D38
|
||||
#define GMAC_DMA_MODE 0x1000
|
||||
#define GMAC_DMA_MODE_SWR (1U << 0)
|
||||
#define GMAC_DMA_SYSBUS_MODE 0x1004
|
||||
#define GMAC_DMA_SYSBUS_MODE_WR_OSR_LMT_SHIFT 24
|
||||
#define GMAC_DMA_SYSBUS_MODE_WR_OSR_LMT_MASK (0x3U << GMAC_DMA_SYSBUS_MODE_WR_OSR_LMT_SHIFT)
|
||||
#define GMAC_DMA_SYSBUS_MODE_RD_OSR_LMT_SHIFT 16
|
||||
#define GMAC_DMA_SYSBUS_MODE_RD_OSR_LMT_MASK (0x7U << GMAC_DMA_SYSBUS_MODE_RD_OSR_LMT_SHIFT)
|
||||
#define GMAC_DMA_SYSBUS_MODE_MB (1U << 14)
|
||||
#define GMAC_DMA_SYSBUS_MODE_EAME (1U << 11)
|
||||
#define GMAC_DMA_SYSBUS_MODE_BLEN16 (1U << 3)
|
||||
#define GMAC_DMA_SYSBUS_MODE_BLEN8 (1U << 2)
|
||||
#define GMAC_DMA_SYSBUS_MODE_BLEN4 (1U << 1)
|
||||
#define GMAC_DMA_SYSBUS_MODE_FB (1U << 0)
|
||||
#define GMAC_DMA_INTERRUPT_STATUS 0x1008
|
||||
#define GMAC_DMA_DEBUG_STATUS0 0x100C
|
||||
#define GMAC_AXI_LPI_ENTRY_INTERVAL 0x1040
|
||||
#define GMAC_RWK_FILTERn_BYTE_MASK(n) (0x10C0 + 0x4 * (n))
|
||||
#define GMAC_RWK_FILTER01_CRC 0x10D0
|
||||
#define GMAC_RWK_FILTER23_CRC 0x10D4
|
||||
#define GMAC_RWK_FILTER_OFFSET 0x10D8
|
||||
#define GMAC_RWK_FILTER_COMMAND 0x10DC
|
||||
#define GMAC_DMA_CHAN0_CONTROL 0x1100
|
||||
#define GMAC_DMA_CHAN0_CONTROL_DSL_SHIFT 18
|
||||
#define GMAC_DMA_CHAN0_CONTROL_DSL_MASK (0x7U << GMAC_DMA_CHAN0_CONTROL_DSL_SHIFT)
|
||||
#define GMAC_DMA_CHAN0_CONTROL_PBLX8 (1U << 16)
|
||||
#define GMAC_DMA_CHAN0_TX_CONTROL 0x1104
|
||||
#define GMAC_DMA_CHAN0_TX_CONTROL_OSP (1U << 4)
|
||||
#define GMAC_DMA_CHAN0_TX_CONTROL_START (1U << 0)
|
||||
#define GMAC_DMA_CHAN0_RX_CONTROL 0x1108
|
||||
#define GMAC_DMA_CHAN0_RX_CONTROL_RBSZ_SHIFT 1
|
||||
#define GMAC_DMA_CHAN0_RX_CONTROL_RBSZ_MASK (0x3FFFU << GMAC_DMA_CHAN0_RX_CONTROL_RBSZ_SHIFT)
|
||||
#define GMAC_DMA_CHAN0_RX_CONTROL_START (1U << 0)
|
||||
#define GMAC_DMA_CHAN0_TX_BASE_ADDR_HI 0x1110
|
||||
#define GMAC_DMA_CHAN0_TX_BASE_ADDR 0x1114
|
||||
#define GMAC_DMA_CHAN0_RX_BASE_ADDR_HI 0x1118
|
||||
#define GMAC_DMA_CHAN0_RX_BASE_ADDR 0x111C
|
||||
#define GMAC_DMA_CHAN0_TX_END_ADDR 0x1120
|
||||
#define GMAC_DMA_CHAN0_RX_END_ADDR 0x1128
|
||||
#define GMAC_DMA_CHAN0_TX_RING_LEN 0x112C
|
||||
#define GMAC_DMA_CHAN0_RX_RING_LEN 0x1130
|
||||
#define GMAC_DMA_CHAN0_INTR_ENABLE 0x1134
|
||||
#define GMAC_DMA_CHAN0_INTR_ENABLE_NIE (1U << 15)
|
||||
#define GMAC_DMA_CHAN0_INTR_ENABLE_AIE (1U << 14)
|
||||
#define GMAC_DMA_CHAN0_INTR_ENABLE_CDE (1U << 13)
|
||||
#define GMAC_DMA_CHAN0_INTR_ENABLE_FBE (1U << 12)
|
||||
#define GMAC_DMA_CHAN0_INTR_ENABLE_ERI (1U << 11)
|
||||
#define GMAC_DMA_CHAN0_INTR_ENABLE_ETI (1U << 10)
|
||||
#define GMAC_DMA_CHAN0_INTR_ENABLE_RWT (1U << 9)
|
||||
#define GMAC_DMA_CHAN0_INTR_ENABLE_RPS (1U << 8)
|
||||
#define GMAC_DMA_CHAN0_INTR_ENABLE_RBU (1U << 7)
|
||||
#define GMAC_DMA_CHAN0_INTR_ENABLE_RIE (1U << 6)
|
||||
#define GMAC_DMA_CHAN0_INTR_ENABLE_TPU (1U << 2)
|
||||
#define GMAC_DMA_CHAN0_INTR_ENABLE_TPS (1U << 1)
|
||||
#define GMAC_DMA_CHAN0_INTR_ENABLE_TIE (1U << 0)
|
||||
#define GMAC_DMA_CHAN0_RX_WATCHDOG 0x1138
|
||||
#define GMAC_DMA_CHAN0_SLOT_CTRL_STATUS 0x113C
|
||||
#define GMAC_DMA_CHAN0_CUR_TX_DESC 0x1144
|
||||
#define GMAC_DMA_CHAN0_CUR_RX_DESC 0x114C
|
||||
#define GMAC_DMA_CHAN0_CUR_TX_BUF_ADDR 0x1154
|
||||
#define GMAC_DMA_CHAN0_CUR_RX_BUF_ADDR 0x115C
|
||||
#define GMAC_DMA_CHAN0_STATUS 0x1160
|
||||
#define GMAC_DMA_CHAN0_STATUS_NIS (1U << 15)
|
||||
#define GMAC_DMA_CHAN0_STATUS_AIS (1U << 14)
|
||||
#define GMAC_DMA_CHAN0_STATUS_CDE (1U << 13)
|
||||
#define GMAC_DMA_CHAN0_STATUS_FB (1U << 12)
|
||||
#define GMAC_DMA_CHAN0_STATUS_ERI (1U << 11)
|
||||
#define GMAC_DMA_CHAN0_STATUS_ETI (1U << 10)
|
||||
#define GMAC_DMA_CHAN0_STATUS_RWT (1U << 9)
|
||||
#define GMAC_DMA_CHAN0_STATUS_RPS (1U << 8)
|
||||
#define GMAC_DMA_CHAN0_STATUS_RBU (1U << 7)
|
||||
#define GMAC_DMA_CHAN0_STATUS_RI (1U << 6)
|
||||
#define GMAC_DMA_CHAN0_STATUS_TPU (1U << 2)
|
||||
#define GMAC_DMA_CHAN0_STATUS_TPS (1U << 1)
|
||||
#define GMAC_DMA_CHAN0_STATUS_TI (1U << 0)
|
||||
|
||||
#define EQOS_TDES2_IOC (1U << 31)
|
||||
#define EQOS_TDES3_OWN (1U << 31)
|
||||
#define EQOS_TDES3_FD (1U << 29)
|
||||
#define EQOS_TDES3_LD (1U << 28)
|
||||
#define EQOS_TDES3_DE (1U << 23)
|
||||
#define EQOS_TDES3_OE (1U << 21)
|
||||
#define EQOS_TDES3_ES (1U << 15)
|
||||
|
||||
#define EQOS_RDES3_OWN (1U << 31)
|
||||
#define EQOS_RDES3_IOC (1U << 30)
|
||||
#define EQOS_RDES3_BUF1V (1U << 24)
|
||||
#define EQOS_RDES3_GP (1U << 23)
|
||||
#define EQOS_RDES3_OE (1U << 21)
|
||||
#define EQOS_RDES3_RE (1U << 20)
|
||||
#define EQOS_RDES3_LENGTH_MASK 0x7FFFU
|
||||
|
||||
#endif
|
||||
99
sys/dev/eqos/if_eqos_var.h
Normal file
99
sys/dev/eqos/if_eqos_var.h
Normal file
|
|
@ -0,0 +1,99 @@
|
|||
/*-
|
||||
* SPDX-License-Identifier: BSD-2-Clause-FreeBSD
|
||||
*
|
||||
* Copyright (c) 2022 Soren Schmidt <sos@deepcore.dk>
|
||||
* Copyright (c) 2022 Jared McNeill <jmcneill@invisible.ca>
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
|
||||
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
|
||||
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
|
||||
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
|
||||
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
|
||||
* SUCH DAMAGE.
|
||||
*
|
||||
* $Id: eqos_var.h 1009 2022-11-15 20:17:35Z sos $
|
||||
*/
|
||||
|
||||
/*
|
||||
* DesignWare Ethernet Quality-of-Service controller
|
||||
*/
|
||||
|
||||
#ifndef _EQOS_VAR_H
|
||||
#define _EQOS_VAR_H
|
||||
|
||||
#include <dev/eqos/if_eqos_reg.h>
|
||||
|
||||
#define EQOS_DMA_DESC_COUNT 256
|
||||
|
||||
#define EQOS_RES_MEM 0
|
||||
#define EQOS_RES_IRQ0 1
|
||||
#define EQOS_RES_COUNT 2
|
||||
|
||||
#define EQOS_INTR_FLAGS (INTR_TYPE_NET | INTR_MPSAFE)
|
||||
|
||||
struct eqos_dma_desc {
|
||||
uint32_t des0;
|
||||
uint32_t des1;
|
||||
uint32_t des2;
|
||||
uint32_t des3;
|
||||
} __packed;
|
||||
|
||||
struct eqos_bufmap {
|
||||
bus_dmamap_t map;
|
||||
struct mbuf *mbuf;
|
||||
};
|
||||
|
||||
struct eqos_ring {
|
||||
bus_dma_tag_t desc_tag;
|
||||
bus_dmamap_t desc_map;
|
||||
struct eqos_dma_desc *desc_ring;
|
||||
bus_addr_t desc_ring_paddr;
|
||||
|
||||
bus_dma_tag_t buf_tag;
|
||||
struct eqos_bufmap buf_map[EQOS_DMA_DESC_COUNT];
|
||||
|
||||
u_int head;
|
||||
u_int tail;
|
||||
};
|
||||
|
||||
struct eqos_softc {
|
||||
device_t dev;
|
||||
struct resource *res[EQOS_RES_COUNT];
|
||||
void *irq_handle;
|
||||
#ifdef FDT
|
||||
struct syscon *grf;
|
||||
int grf_offset;
|
||||
#endif
|
||||
uint32_t csr_clock;
|
||||
uint32_t csr_clock_range;
|
||||
uint32_t hw_feature[4];
|
||||
bool link_up;
|
||||
int tx_watchdog;
|
||||
|
||||
struct ifnet *ifp;
|
||||
device_t miibus;
|
||||
struct mtx lock;
|
||||
struct callout callout;
|
||||
|
||||
struct eqos_ring tx;
|
||||
struct eqos_ring rx;
|
||||
};
|
||||
|
||||
DECLARE_CLASS(eqos_driver);
|
||||
|
||||
#endif
|
||||
Loading…
Reference in a new issue