From 6ef699a0a614f2cf0410cdc21df2671604cd462a Mon Sep 17 00:00:00 2001 From: Adrian Chadd Date: Thu, 27 Jan 2011 02:56:03 +0000 Subject: [PATCH] Writing to the analog registers on the AR9220 (Merlin PCI) seems to require a delay. This, along with an initval change which will appear in a subsequent commit, fixes bus panics that I have been seing with the AR9220 on a Routerstation Pro (AR7161 MIPS board.) Obtained from: Linux ath9k PR: kern/154220 --- sys/dev/ath/ath_hal/ah.c | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/sys/dev/ath/ath_hal/ah.c b/sys/dev/ath/ath_hal/ah.c index 47dec1f4ea8..fb170e5da74 100644 --- a/sys/dev/ath/ath_hal/ah.c +++ b/sys/dev/ath/ath_hal/ah.c @@ -858,6 +858,11 @@ ath_hal_ini_write(struct ath_hal *ah, const HAL_INI_ARRAY *ia, for (r = 0; r < ia->rows; r++) { OS_REG_WRITE(ah, HAL_INI_VAL(ia, r, 0), HAL_INI_VAL(ia, r, col)); + + /* Analog shift register delay seems needed for Merlin - PR kern/154220 */ + if (HAL_INI_VAL(ia, r, 0) >= 0x7800 && HAL_INI_VAL(ia, r, 0) < 0x78a0) + OS_DELAY(100); + DMA_YIELD(regWr); } return regWr; @@ -881,6 +886,10 @@ ath_hal_ini_bank_write(struct ath_hal *ah, const HAL_INI_ARRAY *ia, for (r = 0; r < ia->rows; r++) { OS_REG_WRITE(ah, HAL_INI_VAL(ia, r, 0), data[r]); + + /* Analog shift register delay seems needed for Merlin - PR kern/154220 */ + if (HAL_INI_VAL(ia, r, 0) >= 0x7800 && HAL_INI_VAL(ia, r, 0) < 0x78a0) + OS_DELAY(100); DMA_YIELD(regWr); } return regWr;