From 6e5eac8cc04224b6cd480a2384fcc53d255c7d63 Mon Sep 17 00:00:00 2001 From: Emmanuel Vadot Date: Mon, 30 Sep 2019 15:01:09 +0000 Subject: [PATCH] arm64: rockchip: rk_clk_pll: Check mode on recalc If the pll is in slow or deep slow mode return the correct frequency. --- sys/arm64/rockchip/clk/rk_clk_pll.c | 17 ++++++++++++++++- 1 file changed, 16 insertions(+), 1 deletion(-) diff --git a/sys/arm64/rockchip/clk/rk_clk_pll.c b/sys/arm64/rockchip/clk/rk_clk_pll.c index a7c92123b35..641a6af4084 100644 --- a/sys/arm64/rockchip/clk/rk_clk_pll.c +++ b/sys/arm64/rockchip/clk/rk_clk_pll.c @@ -367,7 +367,7 @@ rk3399_clk_pll_recalc(struct clknode *clk, uint64_t *freq) uint32_t postdiv1, postdiv2, fracdiv; uint32_t con1, con2, con3, con4; uint64_t foutvco; - + uint32_t mode; sc = clknode_get_softc(clk); DEVICE_LOCK(clk); @@ -377,6 +377,21 @@ rk3399_clk_pll_recalc(struct clknode *clk, uint64_t *freq) READ4(clk, sc->base_offset + 0xC, &con4); DEVICE_UNLOCK(clk); + /* + * if we are in slow mode the output freq + * is the parent one, the 24Mhz external oscillator + * if we are in deep mode the output freq is 32.768khz + */ + mode = (con4 & RK3399_CLK_PLL_MODE_MASK) >> RK3399_CLK_PLL_MODE_SHIFT; + if (mode == RK3399_CLK_PLL_MODE_SLOW) { + dprintf("pll in slow mode, con4=%x\n", con4); + return (0); + } else if (mode == RK3399_CLK_PLL_MODE_DEEPSLOW) { + dprintf("pll in deep slow, con4=%x\n", con4); + *freq = 32768; + return (0); + } + dprintf("con0: %x\n", con1); dprintf("con1: %x\n", con2); dprintf("con2: %x\n", con3);