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hyperv/vmbus: Rework SynIC setup and teardown
- Avoid bit fields. - Fix SINT setup (preserve required bits). MFC after: 1 week Sponsored by: Microsoft OSTC Differential Revision: https://reviews.freebsd.org/D6529
This commit is contained in:
Sepherosa Ziehau
parent
c1d5ebc5a4
commit
6d6baea80d
2 changed files with 94 additions and 71 deletions
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@ -61,6 +61,7 @@ __FBSDID("$FreeBSD$");
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#include <dev/hyperv/include/hyperv.h>
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#include <dev/hyperv/vmbus/hv_vmbus_priv.h>
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#include <dev/hyperv/vmbus/hyperv_reg.h>
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#include <dev/hyperv/vmbus/vmbus_var.h>
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#include <contrib/dev/acpica/include/acpi.h>
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@ -210,100 +211,97 @@ static void
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vmbus_synic_setup(void *xsc)
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{
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struct vmbus_softc *sc = xsc;
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int cpu;
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hv_vmbus_synic_simp simp;
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hv_vmbus_synic_siefp siefp;
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hv_vmbus_synic_scontrol sctrl;
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hv_vmbus_synic_sint shared_sint;
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cpu = PCPU_GET(cpuid);
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int cpu = curcpu;
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uint64_t val, orig;
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uint32_t sint;
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/*
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* Setup the Synic's message page
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* Save virtual processor id.
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*/
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simp.as_uint64_t = rdmsr(HV_X64_MSR_SIMP);
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simp.u.simp_enabled = 1;
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simp.u.base_simp_gpa =
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VMBUS_PCPU_GET(sc, message_dma.hv_paddr, cpu) >> PAGE_SHIFT;
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wrmsr(HV_X64_MSR_SIMP, simp.as_uint64_t);
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VMBUS_PCPU_GET(sc, vcpuid, cpu) = rdmsr(MSR_HV_VP_INDEX);
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/*
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* Setup the Synic's event page
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* Setup the SynIC message.
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*/
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siefp.as_uint64_t = rdmsr(HV_X64_MSR_SIEFP);
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siefp.u.siefp_enabled = 1;
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siefp.u.base_siefp_gpa =
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VMBUS_PCPU_GET(sc, event_flag_dma.hv_paddr, cpu) >> PAGE_SHIFT;
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wrmsr(HV_X64_MSR_SIEFP, siefp.as_uint64_t);
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/*HV_SHARED_SINT_IDT_VECTOR + 0x20; */
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shared_sint.as_uint64_t = 0;
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shared_sint.u.vector = sc->vmbus_idtvec;
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shared_sint.u.masked = FALSE;
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shared_sint.u.auto_eoi = TRUE;
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wrmsr(HV_X64_MSR_SINT0 + HV_VMBUS_MESSAGE_SINT,
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shared_sint.as_uint64_t);
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wrmsr(HV_X64_MSR_SINT0 + HV_VMBUS_TIMER_SINT,
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shared_sint.as_uint64_t);
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/* Enable the global synic bit */
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sctrl.as_uint64_t = rdmsr(HV_X64_MSR_SCONTROL);
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sctrl.u.enable = 1;
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wrmsr(HV_X64_MSR_SCONTROL, sctrl.as_uint64_t);
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orig = rdmsr(MSR_HV_SIMP);
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val = MSR_HV_SIMP_ENABLE | (orig & MSR_HV_SIMP_RSVD_MASK) |
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((VMBUS_PCPU_GET(sc, message_dma.hv_paddr, cpu) >> PAGE_SHIFT) <<
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MSR_HV_SIMP_PGSHIFT);
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wrmsr(MSR_HV_SIMP, val);
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/*
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* Set up the cpuid mapping from Hyper-V to FreeBSD.
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* The array is indexed using FreeBSD cpuid.
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* Setup the SynIC event flags.
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*/
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VMBUS_PCPU_GET(sc, vcpuid, cpu) = rdmsr(HV_X64_MSR_VP_INDEX);
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orig = rdmsr(MSR_HV_SIEFP);
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val = MSR_HV_SIEFP_ENABLE | (orig & MSR_HV_SIEFP_RSVD_MASK) |
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((VMBUS_PCPU_GET(sc, event_flag_dma.hv_paddr, cpu) >> PAGE_SHIFT) <<
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MSR_HV_SIEFP_PGSHIFT);
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wrmsr(MSR_HV_SIEFP, val);
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/*
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* Configure and unmask SINT for message and event flags.
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*/
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sint = MSR_HV_SINT0 + HV_VMBUS_MESSAGE_SINT;
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orig = rdmsr(sint);
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val = sc->vmbus_idtvec | MSR_HV_SINT_AUTOEOI |
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(orig & MSR_HV_SINT_RSVD_MASK);
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wrmsr(sint, val);
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/*
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* Configure and unmask SINT for timer.
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*/
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sint = MSR_HV_SINT0 + HV_VMBUS_TIMER_SINT;
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orig = rdmsr(sint);
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val = sc->vmbus_idtvec | MSR_HV_SINT_AUTOEOI |
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(orig & MSR_HV_SINT_RSVD_MASK);
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wrmsr(sint, val);
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/*
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* All done; enable SynIC.
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*/
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orig = rdmsr(MSR_HV_SCONTROL);
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val = MSR_HV_SCTRL_ENABLE | (orig & MSR_HV_SCTRL_RSVD_MASK);
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wrmsr(MSR_HV_SCONTROL, val);
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}
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static void
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vmbus_synic_teardown(void *arg)
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{
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hv_vmbus_synic_sint shared_sint;
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hv_vmbus_synic_simp simp;
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hv_vmbus_synic_siefp siefp;
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shared_sint.as_uint64_t = rdmsr(
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HV_X64_MSR_SINT0 + HV_VMBUS_MESSAGE_SINT);
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shared_sint.u.masked = 1;
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uint64_t orig;
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uint32_t sint;
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/*
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* Disable the interrupt 0
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* Disable SynIC.
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*/
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wrmsr(
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HV_X64_MSR_SINT0 + HV_VMBUS_MESSAGE_SINT,
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shared_sint.as_uint64_t);
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shared_sint.as_uint64_t = rdmsr(
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HV_X64_MSR_SINT0 + HV_VMBUS_TIMER_SINT);
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shared_sint.u.masked = 1;
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orig = rdmsr(MSR_HV_SCONTROL);
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wrmsr(MSR_HV_SCONTROL, (orig & MSR_HV_SCTRL_RSVD_MASK));
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/*
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* Disable the interrupt 1
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* Mask message and event flags SINT.
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*/
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wrmsr(
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HV_X64_MSR_SINT0 + HV_VMBUS_TIMER_SINT,
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shared_sint.as_uint64_t);
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simp.as_uint64_t = rdmsr(HV_X64_MSR_SIMP);
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simp.u.simp_enabled = 0;
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simp.u.base_simp_gpa = 0;
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sint = MSR_HV_SINT0 + HV_VMBUS_MESSAGE_SINT;
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orig = rdmsr(sint);
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wrmsr(sint, orig | MSR_HV_SINT_MASKED);
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wrmsr(HV_X64_MSR_SIMP, simp.as_uint64_t);
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/*
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* Mask timer SINT.
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*/
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sint = MSR_HV_SINT0 + HV_VMBUS_TIMER_SINT;
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orig = rdmsr(sint);
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wrmsr(sint, orig | MSR_HV_SINT_MASKED);
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siefp.as_uint64_t = rdmsr(HV_X64_MSR_SIEFP);
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siefp.u.siefp_enabled = 0;
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siefp.u.base_siefp_gpa = 0;
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/*
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* Teardown SynIC message.
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*/
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orig = rdmsr(MSR_HV_SIMP);
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wrmsr(MSR_HV_SIMP, (orig & MSR_HV_SIMP_RSVD_MASK));
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wrmsr(HV_X64_MSR_SIEFP, siefp.as_uint64_t);
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/*
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* Teardown SynIC event flags.
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*/
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orig = rdmsr(MSR_HV_SIEFP);
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wrmsr(MSR_HV_SIEFP, (orig & MSR_HV_SIEFP_RSVD_MASK));
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}
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static int
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@ -34,4 +34,29 @@
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#define MSR_HV_HYPERCALL_RSVD_MASK 0x0ffeULL
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#define MSR_HV_HYPERCALL_PGSHIFT 12
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#define MSR_HV_VP_INDEX 0x40000002
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#define MSR_HV_SCONTROL 0x40000080
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#define MSR_HV_SCTRL_ENABLE 0x0001ULL
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#define MSR_HV_SCTRL_RSVD_MASK 0xfffffffffffffffeULL
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#define MSR_HV_SIEFP 0x40000082
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#define MSR_HV_SIEFP_ENABLE 0x0001ULL
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#define MSR_HV_SIEFP_RSVD_MASK 0x0ffeULL
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#define MSR_HV_SIEFP_PGSHIFT 12
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#define MSR_HV_SIMP 0x40000083
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#define MSR_HV_SIMP_ENABLE 0x0001ULL
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#define MSR_HV_SIMP_RSVD_MASK 0x0ffeULL
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#define MSR_HV_SIMP_PGSHIFT 12
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#define MSR_HV_SINT0 0x40000090
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#define MSR_HV_SINT_VECTOR_MASK 0x00ffULL
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#define MSR_HV_SINT_RSVD1_MASK 0xff00ULL
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#define MSR_HV_SINT_MASKED 0x00010000ULL
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#define MSR_HV_SINT_AUTOEOI 0x00020000ULL
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#define MSR_HV_SINT_RSVD2_MASK 0xfffffffffffc0000ULL
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#define MSR_HV_SINT_RSVD_MASK (MSR_HV_SINT_RSVD1_MASK | \
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MSR_HV_SINT_RSVD2_MASK)
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#endif /* !_HYPERV_REG_H_ */
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