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Add the implementation of basic bus_space_read/write functions.
Sponsored by: DARPA, AFRL Sponsored by: HEIF5
This commit is contained in:
Ruslan Bukin
parent
39fe39bca9
commit
6c0d33bcb3
2 changed files with 183 additions and 12 deletions
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@ -1,4 +1,5 @@
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/*-
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* Copyright (c) 2014 Andrew Turner
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* Copyright (c) 2015 Ruslan Bukin <br@bsdpad.com>
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* All rights reserved.
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*
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@ -42,27 +43,108 @@ __FBSDID("$FreeBSD$");
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#include <machine/bus.h>
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uint8_t generic_bs_r_1(void *, bus_space_handle_t, bus_size_t);
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uint16_t generic_bs_r_2(void *, bus_space_handle_t, bus_size_t);
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uint32_t generic_bs_r_4(void *, bus_space_handle_t, bus_size_t);
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uint64_t generic_bs_r_8(void *, bus_space_handle_t, bus_size_t);
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void generic_bs_rm_1(void *, bus_space_handle_t, bus_size_t, uint8_t *,
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bus_size_t);
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void generic_bs_rm_2(void *, bus_space_handle_t, bus_size_t, uint16_t *,
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bus_size_t);
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void generic_bs_rm_4(void *, bus_space_handle_t, bus_size_t, uint32_t *,
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bus_size_t);
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void generic_bs_rm_8(void *, bus_space_handle_t, bus_size_t, uint64_t *,
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bus_size_t);
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void generic_bs_rr_1(void *, bus_space_handle_t, bus_size_t, uint8_t *,
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bus_size_t);
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void generic_bs_rr_2(void *, bus_space_handle_t, bus_size_t, uint16_t *,
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bus_size_t);
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void generic_bs_rr_4(void *, bus_space_handle_t, bus_size_t, uint32_t *,
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bus_size_t);
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void generic_bs_rr_8(void *, bus_space_handle_t, bus_size_t, uint64_t *,
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bus_size_t);
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void generic_bs_w_1(void *, bus_space_handle_t, bus_size_t, uint8_t);
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void generic_bs_w_2(void *, bus_space_handle_t, bus_size_t, uint16_t);
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void generic_bs_w_4(void *, bus_space_handle_t, bus_size_t, uint32_t);
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void generic_bs_w_8(void *, bus_space_handle_t, bus_size_t, uint64_t);
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void generic_bs_wm_1(void *, bus_space_handle_t, bus_size_t, const uint8_t *,
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bus_size_t);
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void generic_bs_wm_2(void *, bus_space_handle_t, bus_size_t, const uint16_t *,
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bus_size_t);
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void generic_bs_wm_4(void *, bus_space_handle_t, bus_size_t, const uint32_t *,
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bus_size_t);
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void generic_bs_wm_8(void *, bus_space_handle_t, bus_size_t, const uint64_t *,
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bus_size_t);
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void generic_bs_wr_1(void *, bus_space_handle_t, bus_size_t, const uint8_t *,
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bus_size_t);
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void generic_bs_wr_2(void *, bus_space_handle_t, bus_size_t, const uint16_t *,
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bus_size_t);
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void generic_bs_wr_4(void *, bus_space_handle_t, bus_size_t, const uint32_t *,
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bus_size_t);
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void generic_bs_wr_8(void *, bus_space_handle_t, bus_size_t, const uint64_t *,
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bus_size_t);
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static int
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generic_bs_map(void *t, bus_addr_t bpa, bus_size_t size, int flags,
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bus_space_handle_t *bshp)
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{
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void *va;
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va = pmap_mapdev(bpa, size);
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if (va == NULL)
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return (ENOMEM);
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*bshp = (bus_space_handle_t)va;
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return (0);
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}
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static void
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generic_bs_unmap(void *t, bus_space_handle_t bsh, bus_size_t size)
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{
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pmap_unmapdev(bsh, size);
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}
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static void
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generic_bs_barrier(void *t, bus_space_handle_t bsh, bus_size_t offset,
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bus_size_t size, int flags)
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{
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}
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static int
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generic_bs_subregion(void *t, bus_space_handle_t bsh, bus_size_t offset,
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bus_size_t size, bus_space_handle_t *nbshp)
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{
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*nbshp = bsh + offset;
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return (0);
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}
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struct bus_space memmap_bus = {
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/* cookie */
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.bs_cookie = NULL,
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/* mapping/unmapping */
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.bs_map = NULL,
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.bs_unmap = NULL,
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.bs_subregion = NULL,
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.bs_map = generic_bs_map,
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.bs_unmap = generic_bs_unmap,
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.bs_subregion = generic_bs_subregion,
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/* allocation/deallocation */
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.bs_alloc = NULL,
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.bs_free = NULL,
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/* barrier */
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.bs_barrier = NULL,
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.bs_barrier = generic_bs_barrier,
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/* read single */
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.bs_r_1 = NULL,
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.bs_r_2 = NULL,
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.bs_r_4 = NULL,
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.bs_r_8 = NULL,
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.bs_r_1 = generic_bs_r_1,
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.bs_r_2 = generic_bs_r_2,
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.bs_r_4 = generic_bs_r_4,
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.bs_r_8 = generic_bs_r_8,
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/* read multiple */
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.bs_rm_1 = NULL,
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@ -71,10 +153,10 @@ struct bus_space memmap_bus = {
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.bs_rm_8 = NULL,
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/* write single */
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.bs_w_1 = NULL,
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.bs_w_2 = NULL,
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.bs_w_4 = NULL,
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.bs_w_8 = NULL,
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.bs_w_1 = generic_bs_w_1,
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.bs_w_2 = generic_bs_w_2,
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.bs_w_4 = generic_bs_w_4,
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.bs_w_8 = generic_bs_w_8,
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/* write multiple */
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.bs_wm_1 = NULL,
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@ -142,3 +224,7 @@ struct bus_space memmap_bus = {
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.bs_wr_4_s = NULL,
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.bs_wr_8_s = NULL,
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};
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#ifdef FDT
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bus_space_tag_t fdtbus_bs_tag = &memmap_bus;
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#endif
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85
sys/riscv/riscv/bus_space_asm.S
Normal file
85
sys/riscv/riscv/bus_space_asm.S
Normal file
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@ -0,0 +1,85 @@
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/*-
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* Copyright (c) 2016 Ruslan Bukin <br@bsdpad.com>
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* All rights reserved.
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*
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* Portions of this software were developed by SRI International and the
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* University of Cambridge Computer Laboratory under DARPA/AFRL contract
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* FA8750-10-C-0237 ("CTSRD"), as part of the DARPA CRASH research programme.
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*
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* Portions of this software were developed by the University of Cambridge
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* Computer Laboratory as part of the CTSRD Project, with support from the
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* UK Higher Education Innovation Fund (HEIF).
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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#include <machine/asm.h>
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__FBSDID("$FreeBSD$");
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ENTRY(generic_bs_r_1)
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add a3, a1, a2
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lb a0, 0(a3)
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ret
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END(generic_bs_r_1)
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ENTRY(generic_bs_r_2)
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add a3, a1, a2
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lh a0, 0(a3)
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ret
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END(generic_bs_r_2)
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ENTRY(generic_bs_r_4)
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add a3, a1, a2
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lw a0, 0(a3)
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ret
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END(generic_bs_r_4)
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ENTRY(generic_bs_r_8)
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add a3, a1, a2
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ld a0, 0(a3)
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ret
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END(generic_bs_r_8)
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ENTRY(generic_bs_w_1)
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add a4, a1, a2
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sb a3, 0(a4)
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ret
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END(generic_bs_w_1)
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ENTRY(generic_bs_w_2)
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add a4, a1, a2
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sh a3, 0(a4)
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ret
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END(generic_bs_w_2)
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ENTRY(generic_bs_w_4)
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add a4, a1, a2
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sw a3, 0(a4)
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ret
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END(generic_bs_w_4)
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ENTRY(generic_bs_w_8)
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add a4, a1, a2
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sd a3, 0(a4)
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ret
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END(generic_bs_w_8)
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