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https://github.com/opnsense/src.git
synced 2026-02-20 00:11:07 -05:00
Fix a multicast handling regression on VT6105M introduced in
vr(4) overhauling(r177050). It seems that filtering multicast addresses with multicast CAM entries require accessing 'CAM enable bit' for each CAM entry. Subsequent accessing multicast CAM control register without toggling the 'CAM enable bit' seem to no effects. In order to fix that separate CAM setup from CAM mask configuration and CAM entry modification. While I'm here add VLAN CAM filtering feature which will be enabled in future(FreeBSD now can receive VLAN id insertion/removal event from vlan(4) on the fly). For VT6105M hardware, explicitly disable VLAN hardware tag insertion/stripping and enable VLAN CAM filtering for VLAN id 0. This shall make non-VLAN frames set VR_RXSTAT_VIDHIT bit in Rx status word. Added multicast/VLAN CAM address definition to header file. PR: kern/125010, kern/125024 MFC after: 1 week
This commit is contained in:
Pyun YongHyeon
parent
0a76b25957
commit
6b284b784a
2 changed files with 60 additions and 25 deletions
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@ -186,7 +186,8 @@ static int vr_miibus_writereg(device_t, int, int, int);
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static void vr_miibus_statchg(device_t);
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static void vr_link_task(void *, int);
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static int vr_setperf(struct vr_softc *, int, uint8_t *);
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static void vr_cam_mask(struct vr_softc *, uint32_t, int);
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static int vr_cam_data(struct vr_softc *, int, int, uint8_t *);
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static void vr_set_filter(struct vr_softc *);
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static void vr_reset(const struct vr_softc *);
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static int vr_tx_ring_init(struct vr_softc *);
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@ -394,27 +395,44 @@ vr_link_task(void *arg, int pending)
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VR_UNLOCK(sc);
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}
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/*
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* Copy the address 'mac' into the perfect RX filter entry at
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* offset 'idx.' The perfect filter only has 32 entries so do
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* some sanity tests.
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*/
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static void
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vr_cam_mask(struct vr_softc *sc, uint32_t mask, int type)
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{
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if (type == VR_MCAST_CAM)
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CSR_WRITE_1(sc, VR_CAMCTL, VR_CAMCTL_ENA | VR_CAMCTL_MCAST);
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else
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CSR_WRITE_1(sc, VR_CAMCTL, VR_CAMCTL_ENA | VR_CAMCTL_VLAN);
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CSR_WRITE_4(sc, VR_CAMMASK, mask);
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CSR_WRITE_1(sc, VR_CAMCTL, 0);
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}
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static int
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vr_setperf(struct vr_softc *sc, int idx, uint8_t *mac)
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vr_cam_data(struct vr_softc *sc, int type, int idx, uint8_t *mac)
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{
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int i;
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if (idx < 0 || idx >= VR_CAM_MCAST_CNT || mac == NULL)
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return (EINVAL);
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if (type == VR_MCAST_CAM) {
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if (idx < 0 || idx >= VR_CAM_MCAST_CNT || mac == NULL)
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return (EINVAL);
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CSR_WRITE_1(sc, VR_CAMCTL, VR_CAMCTL_ENA | VR_CAMCTL_MCAST);
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} else
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CSR_WRITE_1(sc, VR_CAMCTL, VR_CAMCTL_ENA | VR_CAMCTL_VLAN);
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/* Set CAM entry address. */
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CSR_WRITE_1(sc, VR_CAMADDR, idx);
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/* Set CAM entry data. */
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for (i = 0; i < ETHER_ADDR_LEN; i++)
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CSR_WRITE_1(sc, VR_MAR0 + i, mac[i]);
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if (type == VR_MCAST_CAM) {
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for (i = 0; i < ETHER_ADDR_LEN; i++)
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CSR_WRITE_1(sc, VR_MCAM0 + i, mac[i]);
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} else {
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CSR_WRITE_1(sc, VR_VCAM0, mac[0]);
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CSR_WRITE_1(sc, VR_VCAM1, mac[1]);
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}
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DELAY(10);
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/* Write CAM and wait for self-clear of VR_CAMCTL_WRITE bit. */
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CSR_WRITE_1(sc, VR_CAMCTL,
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VR_CAMCTL_ENA | VR_CAMCTL_MCAST | VR_CAMCTL_WRITE);
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CSR_WRITE_1(sc, VR_CAMCTL, VR_CAMCTL_ENA | VR_CAMCTL_WRITE);
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for (i = 0; i < VR_TIMEOUT; i++) {
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DELAY(1);
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if ((CSR_READ_1(sc, VR_CAMCTL) & VR_CAMCTL_WRITE) == 0)
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@ -424,6 +442,7 @@ vr_setperf(struct vr_softc *sc, int idx, uint8_t *mac)
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if (i == VR_TIMEOUT)
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device_printf(sc->vr_dev, "%s: setting CAM filter timeout!\n",
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__func__);
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CSR_WRITE_1(sc, VR_CAMCTL, 0);
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return (i == VR_TIMEOUT ? ETIMEDOUT : 0);
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}
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@ -461,6 +480,7 @@ vr_set_filter(struct vr_softc *sc)
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/* Now program new ones. */
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error = 0;
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mcnt = 0;
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IF_ADDR_LOCK(ifp);
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if ((sc->vr_quirks & VR_Q_CAM) != 0) {
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/*
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@ -468,12 +488,10 @@ vr_set_filter(struct vr_softc *sc)
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* 32 entries multicast perfect filter.
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*/
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cam_mask = 0;
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mcnt = 0;
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CSR_WRITE_1(sc, VR_CAMCTL, VR_CAMCTL_ENA | VR_CAMCTL_MCAST);
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TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
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if (ifma->ifma_addr->sa_family != AF_LINK)
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continue;
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error = vr_setperf(sc, mcnt,
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error = vr_cam_data(sc, VR_MCAST_CAM, mcnt,
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LLADDR((struct sockaddr_dl *)ifma->ifma_addr));
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if (error != 0) {
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cam_mask = 0;
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@ -482,19 +500,16 @@ vr_set_filter(struct vr_softc *sc)
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cam_mask |= 1 << mcnt;
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mcnt++;
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}
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/* Enable multicast CAM entries depending on mask. */
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CSR_WRITE_1(sc, VR_CAMMASK, cam_mask);
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/* Accessing CAM done. */
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CSR_WRITE_1(sc, VR_CAMCTL, 0);
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vr_cam_mask(sc, VR_MCAST_CAM, cam_mask);
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}
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mcnt = 0;
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if ((sc->vr_quirks & VR_Q_CAM) == 0 || error != 0) {
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/*
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* If there are too many multicast addresses or
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* setting multicast CAM filter failed, use hash
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* table based filtering.
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*/
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mcnt = 0;
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TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
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if (ifma->ifma_addr->sa_family != AF_LINK)
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continue;
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@ -2031,11 +2046,19 @@ vr_init_locked(struct vr_softc *sc)
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/* Init tx descriptors. */
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vr_tx_ring_init(sc);
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/* Disable all VLAN CAM entries. */
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if ((sc->vr_quirks & VR_Q_CAM) != 0) {
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CSR_WRITE_1(sc, VR_CAMCTL, VR_CAMCTL_ENA | VR_CAMCTL_VLAN);
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CSR_WRITE_1(sc, VR_CAMMASK, 0);
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CSR_WRITE_1(sc, VR_CAMCTL, 0);
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uint8_t vcam[2] = { 0, 0 };
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/* Disable VLAN hardware tag insertion/stripping. */
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VR_CLRBIT(sc, VR_TXCFG, VR_TXCFG_TXTAGEN | VR_TXCFG_RXTAGCTL);
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/* Disable VLAN hardware filtering. */
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VR_CLRBIT(sc, VR_BCR1, VR_BCR1_VLANFILT_ENB);
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/* Disable all CAM entries. */
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vr_cam_mask(sc, VR_MCAST_CAM, 0);
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vr_cam_mask(sc, VR_VLAN_CAM, 0);
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/* Enable the first VLAN CAM. */
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vr_cam_data(sc, VR_VLAN_CAM, 0, vcam);
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vr_cam_mask(sc, VR_VLAN_CAM, 1);
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}
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/*
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@ -47,6 +47,14 @@
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#define VR_IMR 0x0E /* interrupt mask register */
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#define VR_MAR0 0x10 /* multicast hash 0 */
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#define VR_MAR1 0x14 /* multicast hash 1 */
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#define VR_MCAM0 0x10
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#define VR_MCAM1 0x11
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#define VR_MCAM2 0x12
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#define VR_MCAM3 0x13
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#define VR_MCAM4 0x14
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#define VR_MCAM5 0x15
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#define VR_VCAM0 0x16
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#define VR_VCAM1 0x17
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#define VR_RXADDR 0x18 /* rx descriptor list start addr */
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#define VR_TXADDR 0x1C /* tx descriptor list start addr */
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#define VR_CURRXDESC0 0x20
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@ -368,6 +376,7 @@
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#define VR_BCR1_TXTHRESH512BYTES 0x20
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#define VR_BCR1_TXTHRESH1024BYTES 0x28
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#define VR_BCR1_TXTHRESHSTORENFWD 0x38
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#define VR_BCR1_VLANFILT_ENB 0x80 /* VT6105M */
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/*
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* CAMCTL register bits. (VT6105M only)
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@ -751,3 +760,6 @@ struct vr_softc {
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#define VR_SETBIT16(sc, reg, x) CSR_WRITE_2(sc, reg, CSR_READ_2(sc, reg) | (x))
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#define VR_CLRBIT16(sc, reg, x) CSR_WRITE_2(sc, reg, CSR_READ_2(sc, reg) & ~(x))
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#define VR_MCAST_CAM 0
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#define VR_VLAN_CAM 1
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