From 6930f97474e409808ca5e220c2b3a86805f786b8 Mon Sep 17 00:00:00 2001
From: Michal Meloun <mmel@FreeBSD.org>
Date: Tue, 9 Feb 2021 11:36:36 +0100
Subject: [PATCH] arm32: Align arguments of sync_icache() syscall to cacheline
 size.

Otherwise, we may miss synchronization of the last cacheline.
MFC after:	3 days

(cherry picked from commit ec090f4a67654fa541e6d97fd5f74d3f66c1c0d0)
---
 sys/arm/arm/sys_machdep.c | 9 +++------
 1 file changed, 3 insertions(+), 6 deletions(-)

diff --git a/sys/arm/arm/sys_machdep.c b/sys/arm/arm/sys_machdep.c
index d33ac75ad73..fc424d0fad3 100644
--- a/sys/arm/arm/sys_machdep.c
+++ b/sys/arm/arm/sys_machdep.c
@@ -68,12 +68,9 @@ sync_icache(uintptr_t addr, size_t len)
 	size_t size;
 	vm_offset_t rv;
 
-	/*
-	 * Align starting address to even number because value of "1"
-	 * is used as return value for success.
-	 */
-	len += addr & 1;
-	addr &= ~1;
+	 /* Align starting address to cacheline size */
+	len += addr & cpuinfo.dcache_line_mask;
+	addr &= ~cpuinfo.dcache_line_mask;
 
 	/* Break whole range to pages. */
 	do {