From 6632cb429fe1e554583a7cb521aee024d59b4417 Mon Sep 17 00:00:00 2001 From: Adrian Chadd Date: Fri, 4 May 2012 02:26:15 +0000 Subject: [PATCH] Disable setting the MII port speed. This seems to break at least my test board here (AR71xx + AR8316 switch PHY). Since I do have a whole sleuth of "normal" PHY boards (with an AR71xx on a normal PHY port), I'll do some further testing with those to determine whether this is a general issue, or whether it's limited to the behaviour of the "fake" dedicated PHY port mode on these atheros switches. --- sys/mips/atheros/if_arge.c | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/sys/mips/atheros/if_arge.c b/sys/mips/atheros/if_arge.c index c463e1ebba9..6c6398299e0 100644 --- a/sys/mips/atheros/if_arge.c +++ b/sys/mips/atheros/if_arge.c @@ -932,7 +932,19 @@ arge_set_pll(struct arge_softc *sc, int media, int duplex) ar71xx_device_set_pll_ge(sc->arge_mac_unit, if_speed, pll); /* set MII registers */ + /* + * This was introduced to match what the Linux ag71xx ethernet + * driver does. For the AR71xx case, it does set the port + * MII speed. However, if this is done, non-gigabit speeds + * are not at all reliable when speaking via RGMII through + * 'bridge' PHY port that's pretending to be a local PHY. + * + * Until that gets root caused, and until an AR71xx + normal + * PHY board is tested, leave this disabled. + */ +#if 0 ar71xx_device_set_mii_speed(sc->arge_mac_unit, if_speed); +#endif }