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Move Mediatek/Ralink PCIe to NEW_PCIB
This revision fixes minor issues and moves the Mediatek/Ralink PCIe support to use NEW_PCIB. https://svnweb.freebsd.org/changeset/base/297849 is the other part of this changeset. Approved by: adrian (mentor) Sponsored by: Smartcom - Bulgaria AD Differential Revision: https://reviews.freebsd.org/D5908
This commit is contained in:
Stanislav Galabov
parent
a82ccc6f1e
commit
6573205a07
2 changed files with 69 additions and 303 deletions
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@ -21,15 +21,6 @@
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* The pci allocator parts are based on code from sys/dev/arm/mv/:
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*
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* Copyright (c) 2008 MARVELL INTERNATIONAL LTD.
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* Copyright (c) 2010 The FreeBSD Foundation
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* Copyright (c) 2010-2012 Semihalf
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* All rights reserved.
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*
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* Developed by Semihalf.
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*/
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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@ -72,6 +63,7 @@ __FBSDID("$FreeBSD$");
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#include <mips/mediatek/mtk_sysctl.h>
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#include <mips/mediatek/fdt_reset.h>
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#include "ofw_bus_if.h"
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#include "pcib_if.h"
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#include "pic_if.h"
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@ -98,7 +90,6 @@ static void mtk_pcie_phy_setup_slots(device_t);
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struct mtx mtk_pci_mtx;
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MTX_SYSINIT(mtk_pci_mtx, &mtk_pci_mtx, "MTK PCIe mutex", MTX_SPIN);
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static int mtk_pcib_init(device_t, int, int);
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static int mtk_pci_intr(void *);
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static struct mtk_pci_softc *mt_sc = NULL;
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@ -340,9 +331,6 @@ mtk_pci_attach(device_t dev)
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}
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}
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/* Do generic PCIe initialization and resource allocation */
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mtk_pcib_init(dev, 0, PCI_SLOTMAX);
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/* Attach our PCI child so bus enumeration can start */
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if (device_add_child(dev, "pci", -1) == NULL) {
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device_printf(dev, "could not attach pci bus\n");
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@ -426,6 +414,9 @@ mtk_pci_alloc_resource(device_t bus, device_t child, int type, int *rid,
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struct rman *rm;
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switch (type) {
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case PCI_RES_BUS:
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return pci_domain_alloc_bus(0, child, rid, start, end, count,
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flags);
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case SYS_RES_IRQ:
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rm = &sc->sc_irq_rman;
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break;
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@ -456,6 +447,47 @@ mtk_pci_alloc_resource(device_t bus, device_t child, int type, int *rid,
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return (rv);
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}
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static int
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mtk_pci_release_resource(device_t bus, device_t child, int type, int rid,
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struct resource *res)
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{
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if (type == PCI_RES_BUS)
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return (pci_domain_release_bus(0, child, rid, res));
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return (bus_generic_release_resource(bus, child, type, rid, res));
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}
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static int
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mtk_pci_adjust_resource(device_t bus, device_t child, int type,
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struct resource *res, rman_res_t start, rman_res_t end)
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{
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struct mtk_pci_softc *sc = device_get_softc(bus);
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struct rman *rm;
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switch (type) {
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case PCI_RES_BUS:
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return pci_domain_adjust_bus(0, child, res, start, end);
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case SYS_RES_IRQ:
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rm = &sc->sc_irq_rman;
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break;
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case SYS_RES_IOPORT:
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rm = &sc->sc_io_rman;
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break;
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case SYS_RES_MEMORY:
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rm = &sc->sc_mem_rman;
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break;
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default:
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rm = NULL;
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break;
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}
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if (rm != NULL)
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return (rman_adjust_resource(res, start, end));
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return (bus_generic_adjust_resource(bus, child, type, res, start, end));
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}
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static inline int
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mtk_idx_to_irq(int idx)
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{
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@ -643,22 +675,15 @@ mtk_pci_write_config(device_t dev, u_int bus, u_int slot, u_int func,
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mtx_unlock_spin(&mtk_pci_mtx);
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}
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#if 0
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/* We take care of interrupt routing in the allocator code below */
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static int
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mtk_pci_route_interrupt(device_t pcib, device_t device, int pin)
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{
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//struct mtk_pci_softc *sc = device_get_softc(pcib);
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int bus, sl, dev;
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if (1) return PCI_INVALID_IRQ;
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bus = pci_get_bus(device);
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sl = pci_get_slot(device);
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dev = pci_get_device(device);
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printf("%s: for %d:%d:%d, int = %d\n", __FUNCTION__, bus, sl, dev, pin);
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if (bus != 0)
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panic("Unexpected bus number %d\n", bus);
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@ -672,7 +697,6 @@ mtk_pci_route_interrupt(device_t pcib, device_t device, int pin)
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return (-1);
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}
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#endif
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static device_method_t mtk_pci_methods[] = {
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/* Device interface */
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@ -686,7 +710,8 @@ static device_method_t mtk_pci_methods[] = {
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DEVMETHOD(bus_read_ivar, mtk_pci_read_ivar),
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DEVMETHOD(bus_write_ivar, mtk_pci_write_ivar),
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DEVMETHOD(bus_alloc_resource, mtk_pci_alloc_resource),
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DEVMETHOD(bus_release_resource, bus_generic_release_resource),
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DEVMETHOD(bus_release_resource, mtk_pci_release_resource),
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DEVMETHOD(bus_adjust_resource, mtk_pci_adjust_resource),
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DEVMETHOD(bus_activate_resource, bus_generic_activate_resource),
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DEVMETHOD(bus_deactivate_resource, bus_generic_deactivate_resource),
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DEVMETHOD(bus_setup_intr, mtk_pci_setup_intr),
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@ -696,9 +721,14 @@ static device_method_t mtk_pci_methods[] = {
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DEVMETHOD(pcib_maxslots, mtk_pci_maxslots),
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DEVMETHOD(pcib_read_config, mtk_pci_read_config),
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DEVMETHOD(pcib_write_config, mtk_pci_write_config),
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#if 0
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DEVMETHOD(pcib_route_interrupt, mtk_pci_route_interrupt),
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#endif
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/* OFW bus interface */
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DEVMETHOD(ofw_bus_get_compat, ofw_bus_gen_get_compat),
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DEVMETHOD(ofw_bus_get_model, ofw_bus_gen_get_model),
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DEVMETHOD(ofw_bus_get_name, ofw_bus_gen_get_name),
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DEVMETHOD(ofw_bus_get_node, ofw_bus_gen_get_node),
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DEVMETHOD(ofw_bus_get_type, ofw_bus_gen_get_type),
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DEVMETHOD_END
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};
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@ -713,276 +743,6 @@ static devclass_t mtk_pci_devclass;
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DRIVER_MODULE(mtk_pci, simplebus, mtk_pci_driver, mtk_pci_devclass, 0, 0);
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/* Resource allocation code */
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static inline uint32_t
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pcib_bit_get(uint32_t *map, uint32_t bit)
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{
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uint32_t n = bit / BITS_PER_UINT32;
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bit = bit % BITS_PER_UINT32;
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return (map[n] & (1 << bit));
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}
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static inline void
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pcib_bit_set(uint32_t *map, uint32_t bit)
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{
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uint32_t n = bit / BITS_PER_UINT32;
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bit = bit % BITS_PER_UINT32;
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map[n] |= (1 << bit);
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}
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static inline uint32_t
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pcib_map_check(uint32_t *map, uint32_t start, uint32_t bits)
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{
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uint32_t i;
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for (i = start; i < start + bits; i++)
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if (pcib_bit_get(map, i))
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return (0);
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return (1);
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}
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static inline void
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pcib_map_set(uint32_t *map, uint32_t start, uint32_t bits)
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{
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uint32_t i;
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for (i = start; i < start + bits; i++)
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pcib_bit_set(map, i);
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}
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static bus_addr_t
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pcib_alloc(device_t dev, uint32_t smask)
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{
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struct mtk_pci_softc *sc = device_get_softc(dev);
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uint32_t bits, bits_limit, i, *map, min_alloc, size;
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bus_addr_t addr = 0;
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bus_addr_t base;
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if (smask & 1) {
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base = sc->sc_io_base;
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min_alloc = PCI_MIN_IO_ALLOC;
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bits_limit = sc->sc_io_size / min_alloc;
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map = sc->sc_io_map;
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smask &= ~0x3;
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} else {
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base = sc->sc_mem_base;
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min_alloc = PCI_MIN_MEM_ALLOC;
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bits_limit = sc->sc_mem_size / min_alloc;
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map = sc->sc_mem_map;
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smask &= ~0xF;
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}
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size = ~smask + 1;
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bits = size / min_alloc;
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for (i = 0; i + bits <= bits_limit; i+= bits)
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if (pcib_map_check(map, i, bits)) {
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pcib_map_set(map, i, bits);
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addr = base + (i * min_alloc);
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return (addr);
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}
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return (addr);
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}
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static int
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mtk_pcib_init_bar(device_t dev, int bus, int slot, int func, int barno)
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{
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uint32_t addr, bar;
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int reg, width;
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reg = PCIR_BAR(barno);
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mtk_pci_write_config(dev, bus, slot, func, reg, ~0, 4);
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bar = mtk_pci_read_config(dev, bus, slot, func, reg, 4);
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if (bar == 0)
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return (1);
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/* Calculate BAR size: 64 or 32 bit (in 32-bit units) */
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width = ((bar & 7) == 4) ? 2 : 1;
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addr = pcib_alloc(dev, bar);
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if (!addr)
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return (-1);
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if (bootverbose)
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printf("PCI %u:%u:%u: reg %x: smask=%08x: addr=%08x\n",
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bus, slot, func, reg, bar, addr);
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mtk_pci_write_config(dev, bus, slot, func, reg, addr, 4);
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if (width == 2)
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mtk_pci_write_config(dev, bus, slot, func, reg + 4, 0, 4);
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return (width);
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}
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static int
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mtk_pcib_init_all_bars(device_t dev, int bus, int slot, int func,
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int hdrtype)
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{
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int maxbar, bar, i;
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maxbar = (hdrtype & PCIM_HDRTYPE) ? 0 : 6;
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bar = 0;
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while (bar < maxbar) {
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i = mtk_pcib_init_bar(dev, bus, slot, func, bar);
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bar += i;
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if (i < 0) {
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device_printf(dev, "PCI IO/Memory space exhausted\n");
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return (ENOMEM);
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}
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}
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return (0);
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}
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static void
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mtk_pcib_init_bridge(device_t dev, int bus, int slot, int func)
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{
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struct mtk_pci_softc *sc = device_get_softc(dev);
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bus_addr_t io_base, mem_base;
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uint32_t io_limit, mem_limit;
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int secbus;
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if (bus == 0 && !mtk_pci_slot_has_link(dev, slot)) {
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sc->sc_cur_secbus++;
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device_printf(dev, "Skip bus %d due to no link\n",
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sc->sc_cur_secbus);
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return;
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}
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io_base = sc->sc_io_base;
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io_limit = io_base + sc->sc_io_size - 1;
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mem_base = sc->sc_mem_base;
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mem_limit = mem_base + sc->sc_mem_size - 1;
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mtk_pci_write_config(dev, bus, slot, func, PCIR_IOBASEL_1,
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io_base >> 8, 1);
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mtk_pci_write_config(dev, bus, slot, func, PCIR_IOBASEH_1,
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io_base >> 16, 2);
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mtk_pci_write_config(dev, bus, slot, func, PCIR_IOLIMITL_1,
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io_limit >> 8, 1);
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mtk_pci_write_config(dev, bus, slot, func, PCIR_IOLIMITH_1,
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io_limit >> 16, 2);
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mtk_pci_write_config(dev, bus, slot, func, PCIR_MEMBASE_1,
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mem_base >> 16, 2);
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mtk_pci_write_config(dev, bus, slot, func, PCIR_MEMLIMIT_1,
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mem_limit >> 16, 2);
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mtk_pci_write_config(dev, bus, slot, func, PCIR_PMBASEL_1,
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0x10, 2);
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mtk_pci_write_config(dev, bus, slot, func, PCIR_PMBASEH_1,
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0x0, 4);
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mtk_pci_write_config(dev, bus, slot, func, PCIR_PMLIMITL_1,
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0xF, 2);
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mtk_pci_write_config(dev, bus, slot, func, PCIR_PMLIMITH_1,
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0x0, 4);
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mtk_pci_write_config(dev, bus, slot, func, PCIR_INTLINE, 0xff, 1);
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secbus = mtk_pci_read_config(dev, bus, slot, func, PCIR_SECBUS_1, 1);
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if (secbus == 0) {
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sc->sc_cur_secbus++;
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mtk_pci_write_config(dev, bus, slot, func, PCIR_SECBUS_1,
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sc->sc_cur_secbus, 1);
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mtk_pci_write_config(dev, bus, slot, func, PCIR_SUBBUS_1,
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sc->sc_cur_secbus, 1);
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secbus = sc->sc_cur_secbus;
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}
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mtk_pcib_init(dev, secbus, PCI_SLOTMAX);
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}
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static uint8_t
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mtk_pci_get_int(device_t dev, int bus, int slot)
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{
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if (slot != 0)
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return (PCI_INVALID_IRQ);
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switch (bus) {
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case 1:
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return (MTK_PCIE0_IRQ);
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case 2:
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return (MTK_PCIE1_IRQ);
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case 3:
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return (MTK_PCIE2_IRQ);
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default:
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device_printf(dev, "Bus %d out of range\n", slot);
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return (PCI_INVALID_IRQ);
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}
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/* Unreachable */
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return (PCI_INVALID_IRQ);
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}
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static int
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mtk_pcib_init(device_t dev, int bus, int maxslot)
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{
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int slot, func, maxfunc, error;
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uint8_t hdrtype, command, class, subclass;
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for (slot = 0; slot <= maxslot; slot++) {
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maxfunc = 0;
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for (func = 0; func <= maxfunc; func++) {
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hdrtype = mtk_pci_read_config(dev, bus, slot, func,
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PCIR_HDRTYPE, 1);
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if ((hdrtype & PCIM_HDRTYPE) > PCI_MAXHDRTYPE)
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continue;
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if (func == 0 && (hdrtype & PCIM_MFDEV))
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maxfunc = PCI_FUNCMAX;
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command = mtk_pci_read_config(dev, bus, slot, func,
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PCIR_COMMAND, 1);
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command &= ~(PCIM_CMD_MEMEN | PCIM_CMD_PORTEN);
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mtk_pci_write_config(dev, bus, slot, func,
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PCIR_COMMAND, command, 1);
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error = mtk_pcib_init_all_bars(dev, bus, slot, func,
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hdrtype);
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if (error)
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return (error);
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command |= PCIM_CMD_BUSMASTEREN | PCIM_CMD_MEMEN |
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PCIM_CMD_PORTEN;
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mtk_pci_write_config(dev, bus, slot, func,
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PCIR_COMMAND, command, 1);
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mtk_pci_write_config(dev, bus, slot, func,
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PCIR_CACHELNSZ, 16, 1);
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class = mtk_pci_read_config(dev, bus, slot, func,
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PCIR_CLASS, 1);
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subclass = mtk_pci_read_config(dev, bus, slot, func,
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PCIR_SUBCLASS, 1);
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if (class != PCIC_BRIDGE ||
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subclass != PCIS_BRIDGE_PCI) {
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uint8_t val;
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val = mtk_pci_get_int(dev, bus, slot);
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mtk_pci_write_config(dev, bus, slot, func,
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PCIR_INTLINE, val, 1); /* XXX */
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continue;
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}
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mtk_pcib_init_bridge(dev, bus, slot, func);
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}
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}
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return (0);
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}
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/* Our interrupt handler */
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static int
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mtk_pci_intr(void *arg)
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@ -1467,6 +1227,8 @@ mtk_pcie_phy_setup_slots(device_t dev)
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/* If slot has link - mark it */
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if (MT_READ32(sc, MTK_PCIE_STATUS(i)) & 1)
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sc->pcie_link_status |= (1<<i);
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else
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continue;
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/* Generic slot configuration follows */
|
||||
|
||||
|
|
@ -1484,6 +1246,18 @@ mtk_pcie_phy_setup_slots(device_t dev)
|
|||
val = mtk_pci_read_config(dev, 0, i, 0, 0x70c, 4);
|
||||
val &= ~(0xff << 8);
|
||||
val |= (0x50 << 8);
|
||||
mtk_pci_write_config(dev, 0, i, 0, 0x4, val, 4);
|
||||
mtk_pci_write_config(dev, 0, i, 0, 0x70c, val, 4);
|
||||
|
||||
mtk_pci_write_config(dev, 0, i, 0, PCIR_IOBASEL_1, 0xff, 1);
|
||||
mtk_pci_write_config(dev, 0, i, 0, PCIR_IOBASEH_1, 0xffff, 2);
|
||||
mtk_pci_write_config(dev, 0, i, 0, PCIR_IOLIMITL_1, 0, 1);
|
||||
mtk_pci_write_config(dev, 0, i, 0, PCIR_IOLIMITH_1, 0, 2);
|
||||
mtk_pci_write_config(dev, 0, i, 0, PCIR_MEMBASE_1, 0xffff, 2);
|
||||
mtk_pci_write_config(dev, 0, i, 0, PCIR_MEMLIMIT_1, 0, 2);
|
||||
mtk_pci_write_config(dev, 0, i, 0, PCIR_PMBASEL_1, 0xffff, 2);
|
||||
mtk_pci_write_config(dev, 0, i, 0, PCIR_PMBASEH_1, 0xffffffff,
|
||||
4);
|
||||
mtk_pci_write_config(dev, 0, i, 0, PCIR_PMLIMITL_1, 0, 2);
|
||||
mtk_pci_write_config(dev, 0, i, 0, PCIR_PMLIMITH_1, 0, 4);
|
||||
}
|
||||
}
|
||||
|
|
|
|||
|
|
@ -28,10 +28,6 @@
|
|||
#ifndef __MTK_PCIE_H__
|
||||
#define __MTK_PCIE_H__
|
||||
|
||||
#define PCI_MIN_IO_ALLOC 4
|
||||
#define PCI_MIN_MEM_ALLOC 16
|
||||
#define BITS_PER_UINT32 (NBBY * sizeof(uint32_t))
|
||||
|
||||
#define MTK_PCI_NIRQS 3
|
||||
#define MTK_PCI_BASESLOT 0
|
||||
|
||||
|
|
@ -54,13 +50,9 @@ struct mtk_pci_softc {
|
|||
|
||||
bus_addr_t sc_mem_base;
|
||||
bus_addr_t sc_mem_size;
|
||||
uint32_t sc_mem_map[(256*1024*1024) /
|
||||
(PCI_MIN_MEM_ALLOC * BITS_PER_UINT32)];
|
||||
|
||||
bus_addr_t sc_io_base;
|
||||
bus_addr_t sc_io_size;
|
||||
uint32_t sc_io_map[(16*1024*1024) /
|
||||
(PCI_MIN_IO_ALLOC * BITS_PER_UINT32)];
|
||||
|
||||
struct intr_event *sc_eventstab[MTK_PCI_NIRQS];
|
||||
|
||||
|
|
|
|||
Loading…
Reference in a new issue