From 6308db659f2ad45b30bbf1d9c47abdc97d14ebb0 Mon Sep 17 00:00:00 2001 From: Konstantin Belousov Date: Thu, 24 Oct 2024 02:21:11 +0300 Subject: [PATCH] x86 specialreg: add bit masks definitions for EFER features listed in AMD64 APM vol.2 rev. 3.42. Sponsored by: The FreeBSD Foundation MFC after: 1 week --- sys/x86/include/specialreg.h | 3 +++ 1 file changed, 3 insertions(+) diff --git a/sys/x86/include/specialreg.h b/sys/x86/include/specialreg.h index 197ae4bba7a..ab172ec54ff 100644 --- a/sys/x86/include/specialreg.h +++ b/sys/x86/include/specialreg.h @@ -105,6 +105,9 @@ #define EFER_FFXSR 0x000004000 /* Fast FXSAVE/FSRSTOR */ #define EFER_TCE 0x000008000 /* Translation Cache Extension */ #define EFER_MCOMMIT 0x000020000 /* Enable MCOMMIT (AMD) */ +#define EFER_INTWB 0x000040000 /* Interruptible WBINVD */ +#define EFER_UAIE 0x000100000 /* Upper Address Ignore */ +#define EFER_AIBRSE 0x000200000 /* Automatic IBRS */ /* * Intel Extended Features registers