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Fix the definitions for memory bank sizes, which I somehow got wrong.

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The constant I was using was correct, but I mislabeled it as 256K when
it should have been 512K. This doesn't actually change the code, but
it clarifies things somewhat.

Submitted by:	Chuck Cranor <chuck@research.att.com>
This commit is contained in:
Bill Paul 2001-04-26 16:40:45 +00:00
parent 7a72decc2e
commit 6263665f87
4 changed files with 14 additions and 4 deletions
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2
sys/dev/ti/if_ti.c
View file

@ -1173,7 +1173,7 @@ static int ti_chipinit(sc)
/* Do special setup for Tigon 2. */
if (sc->ti_hwrev == TI_HWREV_TIGON_II) {
TI_SETBIT(sc, TI_CPU_CTL_B, TI_CPUSTATE_HALT);
TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_SRAM_BANK_256K);
TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_SRAM_BANK_512K);
TI_SETBIT(sc, TI_MISC_CONF, TI_MCR_SRAM_SYNCHRONOUS);
}

7
sys/dev/ti/if_tireg.h
View file

@ -143,7 +143,6 @@
* Miscelaneous Local Control register.
*/
#define TI_MLC_EE_WRITE_ENB 0x00000010
#define TI_MLC_SRAM_BANK_256K 0x00000200
#define TI_MLC_SRAM_BANK_SIZE 0x00000300 /* Tigon 2 only */
#define TI_MLC_LOCALADDR_21 0x00004000
#define TI_MLC_LOCALADDR_22 0x00008000
@ -153,6 +152,12 @@
#define TI_MLC_EE_DOUT 0x00400000
#define TI_MLC_EE_DIN 0x00800000
/* Possible memory sizes. */
#define TI_MLC_SRAM_BANK_DISA 0x00000000
#define TI_MLC_SRAM_BANK_1024K 0x00000100
#define TI_MLC_SRAM_BANK_512K 0x00000200
#define TI_MLC_SRAM_BANK_256K 0x00000300
/*
* Offset of MAC address inside EEPROM.
*/

2
sys/pci/if_ti.c
View file

@ -1173,7 +1173,7 @@ static int ti_chipinit(sc)
/* Do special setup for Tigon 2. */
if (sc->ti_hwrev == TI_HWREV_TIGON_II) {
TI_SETBIT(sc, TI_CPU_CTL_B, TI_CPUSTATE_HALT);
TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_SRAM_BANK_256K);
TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_SRAM_BANK_512K);
TI_SETBIT(sc, TI_MISC_CONF, TI_MCR_SRAM_SYNCHRONOUS);
}

7
sys/pci/if_tireg.h
View file

@ -143,7 +143,6 @@
* Miscelaneous Local Control register.
*/
#define TI_MLC_EE_WRITE_ENB 0x00000010
#define TI_MLC_SRAM_BANK_256K 0x00000200
#define TI_MLC_SRAM_BANK_SIZE 0x00000300 /* Tigon 2 only */
#define TI_MLC_LOCALADDR_21 0x00004000
#define TI_MLC_LOCALADDR_22 0x00008000
@ -153,6 +152,12 @@
#define TI_MLC_EE_DOUT 0x00400000
#define TI_MLC_EE_DIN 0x00800000
/* Possible memory sizes. */
#define TI_MLC_SRAM_BANK_DISA 0x00000000
#define TI_MLC_SRAM_BANK_1024K 0x00000100
#define TI_MLC_SRAM_BANK_512K 0x00000200
#define TI_MLC_SRAM_BANK_256K 0x00000300
/*
* Offset of MAC address inside EEPROM.
*/