diff --git a/sys/mips/rmi/board.c b/sys/mips/rmi/board.c
index ac36755a1d8..ea5f3c9c4f2 100644
--- a/sys/mips/rmi/board.c
+++ b/sys/mips/rmi/board.c
@@ -38,9 +38,9 @@ __FBSDID("$FreeBSD$");
 
 #include <machine/cpufunc.h>
 #include <mips/rmi/msgring.h>
+#include <mips/rmi/rmi_boot_info.h>
 #include <mips/rmi/board.h>
 #include <mips/rmi/pic.h>
-#include <mips/rmi/shared_structs.h>
 
 static int xlr_rxstn_to_txstn_map[128] = {
 	[0 ... 7] = TX_STN_CPU_0,
diff --git a/sys/mips/rmi/board.h b/sys/mips/rmi/board.h
index ed2c04533f9..814eba1f74b 100644
--- a/sys/mips/rmi/board.h
+++ b/sys/mips/rmi/board.h
@@ -104,10 +104,10 @@ xlr_processor_id(void)
  * These should come up in PCI device mode (not yet)
  */
 static __inline__ int
-xlr_board_pci(void)
+xlr_board_pci(int board_major)
 {
-	return ((xlr_boot1_info.board_major_version == RMI_XLR_BOARD_ARIZONA_III) ||
-		(xlr_boot1_info.board_major_version == RMI_XLR_BOARD_ARIZONA_V));
+	return ((board_major == RMI_XLR_BOARD_ARIZONA_III) ||
+		(board_major == RMI_XLR_BOARD_ARIZONA_V));
 }
 
 static __inline__ int
diff --git a/sys/mips/rmi/clock.c b/sys/mips/rmi/clock.c
deleted file mode 100644
index c123edf589e..00000000000
--- a/sys/mips/rmi/clock.c
+++ /dev/null
@@ -1,356 +0,0 @@
-/*-
- * Copyright (c) 2003-2009 RMI Corporation
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in the
- *    documentation and/or other materials provided with the distribution.
- * 3. Neither the name of RMI Corporation, nor the names of its contributors,
- *    may be used to endorse or promote products derived from this software
- *    without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
- *
- * RMI_BSD 
- */
-
-#include <sys/cdefs.h>		/* RCS ID & Copyright macro defns */
-__FBSDID("$FreeBSD$");
-
-#include <sys/param.h>
-#include <sys/kernel.h>
-#include <sys/lock.h>
-#include <sys/mutex.h>
-#include <sys/queue.h>
-#include <sys/smp.h>
-#include <sys/sysctl.h>
-#include <sys/systm.h>
-#include <sys/timetc.h>
-
-#include <sys/module.h>
-#include <sys/stdint.h>
-
-#include <sys/bus.h>
-#include <sys/rman.h>
-#include <sys/systm.h>
-#include <sys/clock.h>
-
-#include <machine/clock.h>
-#include <machine/md_var.h>
-#include <machine/hwfunc.h>
-#include <machine/intr_machdep.h>
-
-#include <mips/rmi/iomap.h>
-#include <mips/rmi/clock.h>
-#include <mips/rmi/interrupt.h>
-#include <mips/rmi/pic.h>
-#include <mips/rmi/shared_structs.h>
-
-#ifdef XLR_PERFMON
-#include <mips/rmi/perfmon.h>
-#endif
-
-uint64_t counter_freq;
-uint64_t cycles_per_tick;
-uint64_t cycles_per_usec;
-uint64_t cycles_per_sec;
-uint64_t cycles_per_hz;
-
-u_int32_t counter_upper = 0;
-u_int32_t counter_lower_last = 0;
-
-#define STAT_PROF_CLOCK_SCALE_FACTOR 8
-
-static int scale_factor;
-static int count_scale_factor[32];
-
-uint64_t
-platform_get_frequency()
-{
-	return XLR_PIC_HZ;
-}
-
-void
-mips_timer_early_init(uint64_t clock_hz)
-{
-	/* Initialize clock early so that we can use DELAY sooner */
-	counter_freq = clock_hz;
-	cycles_per_usec = (clock_hz / (1000 * 1000));
-
-}
-
-/*
-* count_compare_clockhandler:
-*
-* Handle the clock interrupt when count becomes equal to
-* compare.
-*/
-int
-count_compare_clockhandler(struct trapframe *tf)
-{
-	int cpu = PCPU_GET(cpuid);
-	uint32_t cycles;
-
-	critical_enter();
-
-	if (cpu == 0) {
-		mips_wr_compare(0);
-	} else {
-		count_scale_factor[cpu]++;
-		cycles = mips_rd_count();
-		cycles += XLR_CPU_HZ / hz;
-		mips_wr_compare(cycles);
-
-		hardclock_cpu(TRAPF_USERMODE(tf));
-		if (count_scale_factor[cpu] == STAT_PROF_CLOCK_SCALE_FACTOR) {
-			statclock(TRAPF_USERMODE(tf));
-			if (profprocs != 0) {
-				profclock(TRAPF_USERMODE(tf), tf->pc);
-			}
-			count_scale_factor[cpu] = 0;
-		}
-		/* If needed , handle count compare tick skew here */
-	}
-
-	critical_exit();
-	return (FILTER_HANDLED);
-}
-
-unsigned long clock_tick_foo=0;
-
-int
-pic_hardclockhandler(struct trapframe *tf)
-{
-	int cpu = PCPU_GET(cpuid);
-
-	critical_enter();
-
-	if (cpu == 0) {
-		scale_factor++;
-		clock_tick_foo++;
-/*
-		if ((clock_tick_foo % 10000) == 0) {
-			printf("Clock tick foo at %ld\n", clock_tick_foo);
-		}
-*/
-		hardclock(TRAPF_USERMODE(tf), tf->pc);
-		if (scale_factor == STAT_PROF_CLOCK_SCALE_FACTOR) {
-			statclock(TRAPF_USERMODE(tf));
-			if (profprocs != 0) {
-				profclock(TRAPF_USERMODE(tf), tf->pc);
-			}
-			scale_factor = 0;
-		}
-#ifdef XLR_PERFMON
-		if (xlr_perfmon_started)
-			xlr_perfmon_clockhandler();
-#endif
-
-	} else {
-		/* If needed , handle count compare tick skew here */
-	}
-	critical_exit();
-	return (FILTER_HANDLED);
-}
-
-int
-pic_timecounthandler(struct trapframe *tf)
-{
-	return (FILTER_HANDLED);
-}
-
-void
-rmi_early_counter_init()
-{
-	int cpu = PCPU_GET(cpuid);
-	xlr_reg_t *mmio = xlr_io_mmio(XLR_IO_PIC_OFFSET);
-
-	/*
-	 * We do this to get the PIC time counter running right after system
-	 * start. Otherwise the DELAY() function will not be able to work
-	 * since it won't have a TC to read.
-	 */
-	xlr_write_reg(mmio, PIC_TIMER_6_MAXVAL_0, (0xffffffff & 0xffffffff));
-	xlr_write_reg(mmio, PIC_TIMER_6_MAXVAL_1, (0xffffffff & 0xffffffff));
-	xlr_write_reg(mmio, PIC_IRT_0_TIMER_6, (1 << cpu));
-	xlr_write_reg(mmio, PIC_IRT_1_TIMER_6, (1 << 31) | (0 << 30) | (1 << 6) | (PIC_TIMER_6_IRQ));
-	pic_update_control(1 << (8 + 6), 0);
-}
-
-void tick_init(void);
-
-void
-platform_initclocks(void)
-{
-	int cpu = PCPU_GET(cpuid);
-	void *cookie;
-
-	/*
-	 * Note: Passing #3 as NULL ensures that clockhandler gets called
-	 * with trapframe
-	 */
-	/* profiling/process accounting timer interrupt for non-zero cpus */
-	cpu_establish_hardintr("compare",
-	    (driver_filter_t *) count_compare_clockhandler,
-	    NULL,
-	    NULL,
-	    IRQ_TIMER,
-	    INTR_TYPE_CLK | INTR_FAST, &cookie);
-
-	/* timekeeping timer interrupt for cpu 0 */
-	cpu_establish_hardintr("hardclk",
-	    (driver_filter_t *) pic_hardclockhandler,
-	    NULL,
-	    NULL,
-	    PIC_TIMER_7_IRQ,
-	    INTR_TYPE_CLK | INTR_FAST,
-	    &cookie);
-
-	/* this is used by timecounter */
-	cpu_establish_hardintr("timecount",
-	    (driver_filter_t *) pic_timecounthandler, NULL,
-	    NULL, PIC_TIMER_6_IRQ, INTR_TYPE_CLK | INTR_FAST,
-	    &cookie);
-
-	if (cpu == 0) {
-		__uint64_t maxval = XLR_PIC_HZ / hz;
-		xlr_reg_t *mmio = xlr_io_mmio(XLR_IO_PIC_OFFSET);
-
-		stathz = hz / STAT_PROF_CLOCK_SCALE_FACTOR;
-		profhz = stathz;
-
-		/* Setup PIC Interrupt */
-
-		if (rmi_spin_mutex_safe)
-			mtx_lock_spin(&xlr_pic_lock);
-		xlr_write_reg(mmio, PIC_TIMER_7_MAXVAL_0, (maxval & 0xffffffff));	/* 0x100 + 7 */
-		xlr_write_reg(mmio, PIC_TIMER_7_MAXVAL_1, (maxval >> 32) & 0xffffffff);	/* 0x110 + 7 */
-		/* 0x40 + 8 */
-		/* reg 40 is lower bits 31-0  and holds CPU mask */
-		xlr_write_reg(mmio, PIC_IRT_0_TIMER_7, (1 << cpu));
-		/* 0x80 + 8 */
-		/* Reg 80 is upper bits 63-32 and holds                              */
-		/* Valid   Edge    Local    IRQ */
-		xlr_write_reg(mmio, PIC_IRT_1_TIMER_7, (1 << 31) | (0 << 30) | (1 << 6) | (PIC_TIMER_7_IRQ));
-
-		pic_update_control(1 << (8 + 7), 1);
-		xlr_write_reg(mmio, PIC_TIMER_6_MAXVAL_0, (0xffffffff & 0xffffffff));
-		xlr_write_reg(mmio, PIC_TIMER_6_MAXVAL_1, (0xffffffff & 0xffffffff));
-		xlr_write_reg(mmio, PIC_IRT_0_TIMER_6, (1 << cpu));
-		xlr_write_reg(mmio, PIC_IRT_1_TIMER_6, (1 << 31) | (0 << 30) | (1 << 6) | (PIC_TIMER_6_IRQ));
-		pic_update_control(1 << (8 + 6), 1);
-		if (rmi_spin_mutex_safe)
-			mtx_unlock_spin(&xlr_pic_lock);
-	} else {
-		/* Setup count-compare interrupt for vcpu[1-31] */
-		mips_wr_compare((xlr_boot1_info.cpu_frequency) / hz);
-	}
-	tick_init();
-}
-
-unsigned
-__attribute__((no_instrument_function))
-platform_get_timecount(struct timecounter *tc __unused)
-{
-	xlr_reg_t *mmio = xlr_io_mmio(XLR_IO_PIC_OFFSET);
-
-	return 0xffffffffU - xlr_read_reg(mmio, PIC_TIMER_6_COUNTER_0);
-}
-
-void
-DELAY(int n)
-{
-	uint32_t cur, last, delta, usecs;
-
-	/*
-	 * This works by polling the timer and counting the number of
-	 * microseconds that go by.
-	 */
-	last = platform_get_timecount(NULL);
-	delta = usecs = 0;
-
-	while (n > usecs) {
-		cur = platform_get_timecount(NULL);
-
-		/* Check to see if the timer has wrapped around. */
-		if (cur < last)
-			delta += (cur + (cycles_per_hz - last));
-		else
-			delta += (cur - last);
-
-		last = cur;
-
-		if (delta >= cycles_per_usec) {
-			usecs += delta / cycles_per_usec;
-			delta %= cycles_per_usec;
-		}
-	}
-}
-
-static
-uint64_t
-read_pic_counter(void)
-{
-	xlr_reg_t *mmio = xlr_io_mmio(XLR_IO_PIC_OFFSET);
-	uint32_t lower, upper;
-	uint64_t tc;
-
-	/*
-	 * Pull the value of the 64 bit counter which is stored in PIC
-	 * register 120+N and 130+N
-	 */
-	upper = 0xffffffffU - xlr_read_reg(mmio, PIC_TIMER_6_COUNTER_1);
-	lower = 0xffffffffU - xlr_read_reg(mmio, PIC_TIMER_6_COUNTER_0);
-	tc = (((uint64_t) upper << 32) | (uint64_t) lower);
-	return (tc);
-}
-
-extern struct timecounter counter_timecounter;
-
-void
-mips_timer_init_params(uint64_t platform_counter_freq, int double_count)
-{
-
-	/*
-	 * XXX: Do not use printf here: uart code 8250 may use DELAY so this
-	 * function should  be called before cninit.
-	 */
-	counter_freq = platform_counter_freq;
-	/*
-	 * XXX: Some MIPS32 cores update the Count register only every two
-	 * pipeline cycles.
-	 */
-	if (double_count != 0)
-		counter_freq /= 2;
-
-	cycles_per_tick = counter_freq / 1000;
-	cycles_per_hz = counter_freq / hz;
-	cycles_per_usec = counter_freq / (1 * 1000 * 1000);
-	cycles_per_sec = counter_freq;
-
-	counter_timecounter.tc_frequency = counter_freq;
-	printf("hz=%d cyl_per_hz:%jd cyl_per_usec:%jd freq:%jd cyl_per_hz:%jd cyl_per_sec:%jd\n",
-	    hz,
-	    cycles_per_tick,
-	    cycles_per_usec,
-	    counter_freq,
-	    cycles_per_hz,
-	    cycles_per_sec
-	    );
-	set_cputicker(read_pic_counter, counter_freq, 1);
-}
diff --git a/sys/mips/rmi/clock.h b/sys/mips/rmi/clock.h
deleted file mode 100644
index c0675810fc8..00000000000
--- a/sys/mips/rmi/clock.h
+++ /dev/null
@@ -1,41 +0,0 @@
-/*-
- * Copyright (c) 2003-2009 RMI Corporation
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in the
- *    documentation and/or other materials provided with the distribution.
- * 3. Neither the name of RMI Corporation, nor the names of its contributors,
- *    may be used to endorse or promote products derived from this software
- *    without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
- *
- * RMI_BSD */
-#ifndef _RMI_CLOCK_H_
-#define _RMI_CLOCK_H_
-
-#define XLR_PIC_HZ 66000000U
-#define XLR_CPU_HZ (xlr_boot1_info.cpu_frequency)
-
-int count_compare_clockhandler(struct trapframe *);
-int pic_hardclockhandler(struct trapframe *);
-int pic_timecounthandler(struct trapframe *);
-void rmi_early_counter_init(void);
-
-#endif				/* _RMI_CLOCK_H_ */
diff --git a/sys/mips/rmi/debug.h b/sys/mips/rmi/debug.h
index b5ec144cc2c..53f1cb21dc0 100644
--- a/sys/mips/rmi/debug.h
+++ b/sys/mips/rmi/debug.h
@@ -26,7 +26,9 @@
  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  * SUCH DAMAGE.
  *
- * RMI_BSD */
+ * RMI_BSD
+ * $FreeBSD$
+ */
 #ifndef _RMI_DEBUG_H_
 #define _RMI_DEBUG_H_
 
diff --git a/sys/mips/rmi/dev/nlge/if_nlge.c b/sys/mips/rmi/dev/nlge/if_nlge.c
index ec476ad7fbe..cdf5ffccbf7 100644
--- a/sys/mips/rmi/dev/nlge/if_nlge.c
+++ b/sys/mips/rmi/dev/nlge/if_nlge.c
@@ -104,10 +104,9 @@ __FBSDID("$FreeBSD$");
 #include <mips/rmi/iomap.h>
 #include <mips/rmi/debug.h>
 #include <mips/rmi/pic.h>
-#include <mips/rmi/xlrconfig.h>
-#include <mips/rmi/shared_structs.h>
 #include <mips/rmi/board.h>
 #include <mips/rmi/rmi_mips_exts.h>
+#include <mips/rmi/rmi_boot_info.h>
 #include <mips/rmi/dev/xlr/atx_cpld.h>
 #include <mips/rmi/dev/xlr/xgmac_mdio.h>
 
@@ -209,7 +208,7 @@ static int	prepare_fmn_message(struct nlge_softc *sc,
     uint64_t fr_stid, struct nlge_tx_desc **tx_desc);
 
 static void	release_mbuf(uint64_t phy_addr);
-static void 	release_tx_desc(struct msgrng_msg *msg, int rel_buf);
+static void 	release_tx_desc(struct msgrng_msg *msg);
 static int	send_fmn_msg_tx(struct nlge_softc *, struct msgrng_msg *,
     uint32_t n_entries);
 
@@ -679,7 +678,7 @@ nlge_msgring_handler(int bucket, int size, int code, int stid,
 
 	if (ctrl == CTRL_REG_FREE || ctrl == CTRL_JUMBO_FREE) {
 		if (is_p2p)
-			release_tx_desc(msg, 1);
+			release_tx_desc(msg);
 		else {
 			release_mbuf(msg->msg0 & 0xffffffffffULL);
 		}
@@ -725,7 +724,7 @@ nlge_start_locked(struct ifnet *ifp, struct nlge_softc *sc)
 
 	cpu = xlr_core_id();	
 	tid = xlr_thr_id();
-	fr_stid = (cpu << 3) + tid + 4;	/* Each CPU has 8 buckets. */
+	fr_stid = cpu * 8 + tid + 4;
 
 	if (!(ifp->if_drv_flags & IFF_DRV_RUNNING)) {
 		return;
@@ -1909,9 +1908,9 @@ prepare_fmn_message(struct nlge_softc *sc, struct msgrng_msg *fmn_msg,
 
 		while (len) {
 			if (msg_sz == (FMN_SZ - 1)) {
-				p2p = uma_zalloc(nl_tx_desc_zone, M_NOWAIT);
-			if (p2p == NULL)
-				return 2;
+				p2p = uma_zalloc(nl_tx_desc_zone, M_WAITOK);
+				if (p2p == NULL)
+					return 2;
 				/*
 				 * As we currently use xlr_paddr_lw on a 32-bit
 				 * OS, both the pointers are laid out in one
@@ -1929,7 +1928,7 @@ prepare_fmn_message(struct nlge_softc *sc, struct msgrng_msg *fmn_msg,
 				return 1;
 			}
 			paddr = vtophys(buf);
-			frag_sz = PAGE_SIZE - (buf & PAGE_MASK) ;
+			frag_sz = PAGE_SIZE - (buf & PAGE_MASK);
 			if (len < frag_sz)
 				frag_sz = len;
 			*cur_p2d++ = (127ULL << 54) | ((uint64_t)frag_sz << 40)
@@ -1993,7 +1992,7 @@ release_mbuf(uint64_t phy_addr)
 }
 
 static void
-release_tx_desc(struct msgrng_msg *msg, int rel_buf)
+release_tx_desc(struct msgrng_msg *msg)
 {
 	vm_paddr_t	paddr;
 	uint64_t	temp;
@@ -2005,17 +2004,12 @@ release_tx_desc(struct msgrng_msg *msg, int rel_buf)
 	paddr += (XLR_MAX_TX_FRAGS * sizeof(uint64_t));
 	sr = xlr_enable_kx();
 	temp = xlr_paddr_lw(paddr);
-	mips_wr_status(sr);
 	tx_desc = (struct nlge_tx_desc*)((intptr_t) temp);
-
-	if (rel_buf) {
-		paddr += sizeof(void *);
-		sr = xlr_enable_kx();
-		temp = xlr_paddr_lw(paddr);
-		mips_wr_status(sr);
-		m = (struct mbuf *)((intptr_t) temp);
-		m_freem(m);
-	}
+	paddr += sizeof(void *);
+	temp = xlr_paddr_lw(paddr);
+	mips_wr_status(sr);
+	m = (struct mbuf *)((intptr_t) temp);
+	m_freem(m);
 
 	uma_zfree(nl_tx_desc_zone, tx_desc);
 }
diff --git a/sys/mips/rmi/dev/xlr/rge.c b/sys/mips/rmi/dev/xlr/rge.c
index 979543bd9b7..9e0bef7a9df 100644
--- a/sys/mips/rmi/dev/xlr/rge.c
+++ b/sys/mips/rmi/dev/xlr/rge.c
@@ -55,6 +55,7 @@ __FBSDID("$FreeBSD$");
 #include <sys/rman.h>
 #include <sys/taskqueue.h>
 #include <sys/smp.h>
+#include <sys/sysctl.h>
 
 #include <net/if.h>
 #include <net/if_arp.h>
@@ -63,7 +64,6 @@ __FBSDID("$FreeBSD$");
 #include <net/if_media.h>
 
 #include <net/bpf.h>
-
 #include <net/if_types.h>
 #include <net/if_vlan_var.h>
 
@@ -87,27 +87,23 @@ __FBSDID("$FreeBSD$");
 #include <machine/cpuregs.h>
 #include <machine/bus.h>	/* */
 #include <machine/resource.h>
-#include <mips/rmi/interrupt.h>
-#include <mips/rmi/msgring.h>
-#include <mips/rmi/iomap.h>
-#include <mips/rmi/debug.h>
-#include <mips/rmi/pic.h>
-#include <mips/rmi/xlrconfig.h>
-#include <mips/rmi/shared_structs.h>
-#include <mips/rmi/board.h>
-
-#include <mips/rmi/dev/xlr/atx_cpld.h>
-#include <mips/rmi/dev/xlr/xgmac_mdio.h>
 
 #include <dev/mii/mii.h>
 #include <dev/mii/miivar.h>
 #include <dev/mii/brgphyreg.h>
 
-#include <sys/sysctl.h>
+#include <mips/rmi/interrupt.h>
+#include <mips/rmi/msgring.h>
+#include <mips/rmi/iomap.h>
+#include <mips/rmi/debug.h>
+#include <mips/rmi/pic.h>
+#include <mips/rmi/rmi_mips_exts.h>
+#include <mips/rmi/rmi_boot_info.h>
+#include <mips/rmi/board.h>
+#include <mips/rmi/dev/xlr/atx_cpld.h>
+#include <mips/rmi/dev/xlr/xgmac_mdio.h>
 #include <mips/rmi/dev/xlr/rge.h>
 
-/* #include "opt_rge.h" */
-
 #include "miibus_if.h"
 
 MODULE_DEPEND(rge, ether, 1, 1, 1);
diff --git a/sys/mips/rmi/interrupt.h b/sys/mips/rmi/interrupt.h
index 8573338e45d..76bbe5afa2e 100644
--- a/sys/mips/rmi/interrupt.h
+++ b/sys/mips/rmi/interrupt.h
@@ -25,8 +25,10 @@
  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  * SUCH DAMAGE.
- *__FBSDID("$FreeBSD$")
- * RMI_BSD */
+ *
+ * RMI_BSD
+ * $FreeBSD$
+ */
 #ifndef _RMI_INTERRUPT_H_
 #define _RMI_INTERRUPT_H_
 
diff --git a/sys/mips/rmi/intr_machdep.c b/sys/mips/rmi/intr_machdep.c
index cf6df1ddbe3..04f6cde02eb 100644
--- a/sys/mips/rmi/intr_machdep.c
+++ b/sys/mips/rmi/intr_machdep.c
@@ -44,9 +44,9 @@ __FBSDID("$FreeBSD$");
 #include <machine/md_var.h>
 #include <machine/trap.h>
 #include <machine/hwfunc.h>
-#include <mips/rmi/xlrconfig.h>
+
+#include <mips/rmi/rmi_mips_exts.h>
 #include <mips/rmi/interrupt.h>
-#include <mips/rmi/clock.h>
 #include <mips/rmi/pic.h>
 
 struct xlr_intrsrc {
diff --git a/sys/mips/rmi/iodi.c b/sys/mips/rmi/iodi.c
index be6856421ed..d8cb081e24c 100644
--- a/sys/mips/rmi/iodi.c
+++ b/sys/mips/rmi/iodi.c
@@ -40,6 +40,7 @@ __FBSDID("$FreeBSD$");
 #include <sys/lock.h>
 #include <sys/mutex.h>
 #include <sys/reboot.h>
+#include <sys/rman.h>
 #include <sys/types.h>
 #include <sys/malloc.h>
 #include <sys/bus.h>
@@ -48,28 +49,17 @@ __FBSDID("$FreeBSD$");
 
 #include <machine/cpu.h>
 #include <machine/bus.h>
-#include <machine/bus.h>
-#include <machine/intr_machdep.h>
-#include <mips/rmi/iomap.h>
-#include <mips/rmi/pic.h>
-#include <mips/rmi/shared_structs.h>
-#include <mips/rmi/board.h>
-#include <sys/rman.h>
-
-
 #include <machine/param.h>
 #include <machine/intr_machdep.h>
 #include <machine/clock.h>	/* for DELAY */
-#include <machine/bus.h>
 #include <machine/resource.h>
+
+#include <mips/rmi/board.h>
+#include <mips/rmi/pic.h>
 #include <mips/rmi/interrupt.h>
 #include <mips/rmi/msgring.h>
 #include <mips/rmi/iomap.h>
-#include <mips/rmi/debug.h>
-#include <mips/rmi/pic.h>
-#include <mips/rmi/xlrconfig.h>
-#include <mips/rmi/shared_structs.h>
-#include <mips/rmi/board.h>
+#include <mips/rmi/rmi_mips_exts.h>
 
 #include <mips/rmi/dev/xlr/atx_cpld.h>
 #include <mips/rmi/dev/xlr/xgmac_mdio.h>
diff --git a/sys/mips/rmi/iomap.h b/sys/mips/rmi/iomap.h
index afc52bf712f..72756d25483 100644
--- a/sys/mips/rmi/iomap.h
+++ b/sys/mips/rmi/iomap.h
@@ -26,7 +26,9 @@
  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  * SUCH DAMAGE.
  *
- * RMI_BSD */
+ * RMI_BSD
+ * $FreeBSD$
+ */
 #ifndef _RMI_IOMAP_H_
 #define _RMI_IOMAP_H_
 
diff --git a/sys/mips/rmi/msgring.h b/sys/mips/rmi/msgring.h
index 33b23629074..6d9fd108a3d 100644
--- a/sys/mips/rmi/msgring.h
+++ b/sys/mips/rmi/msgring.h
@@ -25,13 +25,15 @@
  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  * SUCH DAMAGE.
- * $FreeBSD$
  *
- * RMI_BSD */
+ * RMI_BSD
+ * $FreeBSD$
+ */
 #ifndef _RMI_MSGRING_H_
 #define _RMI_MSGRING_H_
 
-#include <mips/rmi/xlrconfig.h>
+#include <sys/types.h>
+#include <mips/rmi/rmi_mips_exts.h>
 
 #define MSGRNG_TX_BUF_REG 0
 #define MSGRNG_RX_BUF_REG 1
@@ -368,9 +370,6 @@ message_send(unsigned int size, unsigned int code,
 
 	dest = ((size - 1) << 16) | (code << 8) | (stid);
 
-	//dbg_msg("Sending msg<%Lx,%Lx,%Lx,%Lx> to dest = %x\n",
-	    //msg->msg0, msg->msg1, msg->msg2, msg->msg3, dest);
-
 	msgrng_send(dest);
 
 	for (i = 0; i < 16; i++) {
diff --git a/sys/mips/rmi/pic.h b/sys/mips/rmi/pic.h
index 3c777d8f5d7..8a3dd1f8b1d 100644
--- a/sys/mips/rmi/pic.h
+++ b/sys/mips/rmi/pic.h
@@ -25,9 +25,10 @@
  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  * SUCH DAMAGE.
- * __FBSDID("$FreeBSD$");
  *
- * RMI_BSD */
+ * RMI_BSD
+ * $FreeBSD$
+ */
 #ifndef _RMI_PIC_H_
 #define	_RMI_PIC_H_
 
diff --git a/sys/mips/rmi/shared_structs.h b/sys/mips/rmi/rmi_boot_info.h
similarity index 96%
rename from sys/mips/rmi/shared_structs.h
rename to sys/mips/rmi/rmi_boot_info.h
index 6e5ecd43cea..38c81bd395d 100644
--- a/sys/mips/rmi/shared_structs.h
+++ b/sys/mips/rmi/rmi_boot_info.h
@@ -26,13 +26,12 @@
  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  * SUCH DAMAGE.
  *
- * RMI_BSD */
+ * RMI_BSD
+ * $FreeBSD$
+ */
 #ifndef _SHARED_STRUCTS_H
 #define _SHARED_STRUCTS_H
 
-/* If you make any changes to the below structs, shared_structs_offsets.h
- * should be regenerated
- */
 #define BOOT1_INFO_VERSION 0x0001
 
 struct boot1_info {
diff --git a/sys/mips/rmi/rmi_mips_exts.h b/sys/mips/rmi/rmi_mips_exts.h
index 824381ac906..75e4a00047f 100644
--- a/sys/mips/rmi/rmi_mips_exts.h
+++ b/sys/mips/rmi/rmi_mips_exts.h
@@ -26,27 +26,12 @@
  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  * SUCH DAMAGE.
  *
- * RMI_BSD */
+ * RMI_BSD
+ * $FreeBSD$
+ */
 #ifndef __MIPS_EXTS_H__
 #define __MIPS_EXTS_H__
 
-#define enable_KX(flags)   __asm__ __volatile__ (          \
-		".set push\n"              \
-		".set noat\n"               \
-		".set noreorder\n"     \
-		"mfc0 %0, $12\n\t"             \
-		"ori $1, %0, 0x81\n\t"   \
-		"xori $1, 1\n\t"      \
-		"mtc0 $1, $12\n"       \
-		".set pop\n"          \
-		: "=r"(flags) )
-
-#define disable_KX(flags)   __asm__ __volatile__ (          \
-		".set push\n"              \
-		"mtc0 %0, $12\n"       \
-		".set pop\n"          \
-		: : "r"(flags) )
-
 #define CPU_BLOCKID_IFU      0
 #define CPU_BLOCKID_ICU      1
 #define CPU_BLOCKID_IEU      2
@@ -140,5 +125,327 @@ static __inline__ void write_64bit_phnx_ctrl_reg(int block, int reg,unsigned lon
 		);
 }
 
+#define read_c0_register32(reg, sel)                            \
+({ unsigned int __rv;                                           \
+        __asm__ __volatile__(                                   \
+        ".set\tpush\n\t"                                        \
+        ".set mips32\n\t"                                       \
+        "mfc0\t%0,$%1,%2\n\t"                                   \
+        ".set\tpop"                                             \
+        : "=r" (__rv) : "i" (reg), "i" (sel) );                 \
+        __rv;})
+
+#define write_c0_register32(reg,  sel, value)                   \
+        __asm__ __volatile__(                                   \
+        ".set\tpush\n\t"                                        \
+        ".set mips32\n\t"                                       \
+        "mtc0\t%0,$%1,%2\n\t"                                   \
+        ".set\tpop"                                             \
+        : : "r" (value), "i" (reg), "i" (sel) );
+
+#define read_c0_register64(reg, sel)                            \
+   ({ unsigned int __high, __low;                               \
+        __asm__ __volatile__(                                   \
+        ".set\tpush\n\t"                                        \
+        ".set mips64\n\t"                                       \
+        "dmfc0\t $8, $%2, %3\n\t"                               \
+        "dsrl32\t%0, $8, 0\n\t"                                 \
+        "dsll32\t$8, $8, 0\n\t"                                 \
+        "dsrl32\t%1, $8, 0\n\t"                                 \
+        ".set\tpop"                                             \
+        : "=r"(__high), "=r"(__low): "i"(reg), "i"(sel): "$8" );\
+        (((unsigned long long)__high << 32) | __low);})
+
+#define write_c0_register64(reg, sel, value)                    \
+ do{                                                            \
+       unsigned int __high = val>>32;                           \
+       unsigned int __low = val & 0xffffffff;                   \
+        __asm__ __volatile__(                                   \
+        ".set\tpush\n\t"                                        \
+        ".set mips64\n\t"                                       \
+        "dsll32\t$8, %1, 0\n\t"                                 \
+        "dsll32\t$9, %0, 0\n\t"                                 \
+        "or\t    $8, $8, $9\n\t"                                \
+        "dmtc0\t $8, $%2, %3\n\t"                               \
+        ".set\tpop"                                             \
+        :: "r"(high), "r"(low),  "i"(reg), "i"(sel):"$8", "$9");\
+   } while(0)
+
+#define read_c2_register32(reg, sel)                            \
+({ unsigned int __rv;                                           \
+        __asm__ __volatile__(                                   \
+        ".set\tpush\n\t"                                        \
+        ".set mips32\n\t"                                       \
+        "mfc2\t%0,$%1,%2\n\t"                                   \
+        ".set\tpop"                                             \
+        : "=r" (__rv) : "i" (reg), "i" (sel) );                 \
+        __rv;})
+
+#define write_c2_register32(reg,  sel, value)                   \
+        __asm__ __volatile__(                                   \
+        ".set\tpush\n\t"                                        \
+        ".set mips32\n\t"                                       \
+        "mtc2\t%0,$%1,%2\n\t"                                   \
+        ".set\tpop"                                             \
+        : : "r" (value), "i" (reg), "i" (sel) );
+
+#define read_c2_register64(reg, sel)                            \
+   ({ unsigned int __high, __low;                               \
+        __asm__ __volatile__(                                   \
+        ".set mips64\n\t"                                       \
+        "dmfc2\t $8, $%2, %3\n\t"                               \
+        "dsrl32\t%0, $8, 0\n\t"                                 \
+        "dsll32\t$8, $8, 0\n\t"                                 \
+        "dsrl32\t%1, $8, 0\n\t"                                 \
+        ".set\tmips0"                                           \
+        : "=r"(__high), "=r"(__low): "i"(reg), "i"(sel): "$8" );\
+        (((unsigned long long)__high << 32) | __low);})
+
+#define write_c2_register64(reg, sel, value)                    \
+ do{                                                            \
+       unsigned int __high = value>>32;                         \
+       unsigned int __low = value & 0xffffffff;                 \
+        __asm__ __volatile__(                                   \
+        ".set mips64\n\t"                                       \
+        "dsll32\t$8, %1, 0\n\t"                                 \
+        "dsll32\t$9, %0, 0\n\t"                                 \
+        "dsrl32\t$8, $8, 0\n\t"                                 \
+        "or\t    $8, $8, $9\n\t"                                \
+        "dmtc2\t $8, $%2, %3\n\t"                               \
+        ".set\tmips0"                                           \
+        :: "r"(__high), "r"(__low),                             \
+           "i"(reg), "i"(sel)                                   \
+        :"$8", "$9");                                           \
+   } while(0)
+
+#define xlr_cpu_id()                                            \
+({int __id;                                                     \
+ __asm__ __volatile__ (                                         \
+           ".set push\n"                                        \
+           ".set noreorder\n"                                   \
+           "mfc0 $8, $15, 1\n"                                  \
+           "andi %0, $8, 0x1f\n"                                \
+           ".set pop\n"                                         \
+           : "=r" (__id) : : "$8");                             \
+ __id;})
+
+#define xlr_core_id()                                           \
+({int __id;                                                     \
+ __asm__ __volatile__ (                                         \
+           ".set push\n"                                        \
+           ".set noreorder\n"                                   \
+           "mfc0 $8, $15, 1\n"                                  \
+           "andi %0, $8, 0x1f\n"                                \
+           ".set pop\n"                                         \
+           : "=r" (__id) : : "$8");                             \
+ __id/4;})
+
+#define xlr_thr_id()                                            \
+({int __id;                                                     \
+ __asm__ __volatile__ (                                         \
+           ".set push\n"                                        \
+           ".set noreorder\n"                                   \
+           "mfc0 $8, $15, 1\n"                                  \
+           "andi %0, $8, 0x3\n"                                 \
+           ".set pop\n"                                         \
+           : "=r" (__id) : : "$8");                             \
+ __id;})
+
+
+/* Additional registers on the XLR */
+#define MIPS_COP_0_OSSCRATCH   22
+
+#define XLR_CACHELINE_SIZE 32
+
+#define XLR_MAX_CORES 8
+
+/* functions to write to and read from the extended
+ * cp0 registers.
+ * EIRR : Extended Interrupt Request Register
+ *        cp0 register 9 sel 6
+ *        bits 0...7 are same as cause register 8...15
+ * EIMR : Extended Interrupt Mask Register
+ *        cp0 register 9 sel 7
+ *        bits 0...7 are same as status register 8...15
+ */
+
+static inline uint64_t 
+read_c0_eirr64(void)
+{
+	__uint32_t high, low;
+
+	__asm__ __volatile__(
+	            ".set push\n"
+	            ".set noreorder\n"
+	            ".set noat\n"
+	            ".set mips4\n"
+
+	            ".word 0x40214806  \n\t"
+	            "nop               \n\t"
+	            "dsra32 %0, $1, 0  \n\t"
+	            "sll    %1, $1, 0  \n\t"
+
+	            ".set pop\n"
+
+	    :       "=r"(high), "=r"(low)
+	);
+
+	return (((__uint64_t) high) << 32) | low;
+}
+
+static inline __uint64_t 
+read_c0_eimr64(void)
+{
+	__uint32_t high, low;
+
+	__asm__ __volatile__(
+	            ".set push\n"
+	            ".set noreorder\n"
+	            ".set noat\n"
+	            ".set mips4\n"
+
+	            ".word 0x40214807  \n\t"
+	            "nop               \n\t"
+	            "dsra32 %0, $1, 0  \n\t"
+	            "sll    %1, $1, 0  \n\t"
+
+	            ".set pop\n"
+
+	    :       "=r"(high), "=r"(low)
+	);
+
+	return (((__uint64_t) high) << 32) | low;
+}
+
+static inline void 
+write_c0_eirr64(__uint64_t value)
+{
+	__uint32_t low, high;
+
+	high = value >> 32;
+	low = value & 0xffffffff;
+
+	__asm__ __volatile__(
+	            ".set push\n"
+	            ".set noreorder\n"
+	            ".set noat\n"
+	            ".set mips4\n\t"
+
+	            "dsll32 $2, %1, 0  \n\t"
+	            "dsll32 $1, %0, 0  \n\t"
+	            "dsrl32 $2, $2, 0  \n\t"
+	            "or     $1, $1, $2 \n\t"
+	            ".word  0x40a14806 \n\t"
+	            "nop               \n\t"
+
+	            ".set pop\n"
+
+	    :
+	    :       "r"(high), "r"(low)
+	    :       "$1", "$2");
+}
+
+static inline void 
+write_c0_eimr64(__uint64_t value)
+{
+	__uint32_t low, high;
+
+	high = value >> 32;
+	low = value & 0xffffffff;
+
+	__asm__ __volatile__(
+	            ".set push\n"
+	            ".set noreorder\n"
+	            ".set noat\n"
+	            ".set mips4\n\t"
+
+	            "dsll32 $2, %1, 0  \n\t"
+	            "dsll32 $1, %0, 0  \n\t"
+	            "dsrl32 $2, $2, 0  \n\t"
+	            "or     $1, $1, $2 \n\t"
+	            ".word  0x40a14807 \n\t"
+	            "nop               \n\t"
+
+	            ".set pop\n"
+
+	    :
+	    :       "r"(high), "r"(low)
+	    :       "$1", "$2");
+}
+
+static __inline__ int 
+xlr_test_and_set(int *lock)
+{
+	int oldval = 0;
+
+	__asm__ __volatile__(".set push\n"
+	            ".set noreorder\n"
+	            "move $9, %2\n"
+	            "li $8, 1\n"
+	    //      "swapw $8, $9\n"
+	            ".word 0x71280014\n"
+	            "move %1, $8\n"
+	            ".set pop\n"
+	    :       "+m"(*lock), "=r"(oldval)
+	    :       "r"((unsigned long)lock)
+	    :       "$8", "$9"
+	);
+
+	return (oldval == 0 ? 1 /* success */ : 0 /* failure */ );
+}
+
+static __inline__ uint32_t 
+xlr_mfcr(uint32_t reg)
+{
+	uint32_t val;
+
+	__asm__ __volatile__(
+	            "move   $8, %1\n"
+	            ".word  0x71090018\n"
+	            "move   %0, $9\n"
+	    :       "=r"(val)
+	    :       "r"(reg):"$8", "$9");
+
+	return val;
+}
+
+static __inline__ void 
+xlr_mtcr(uint32_t reg, uint32_t val)
+{
+	__asm__ __volatile__(
+	            "move   $8, %1\n"
+	            "move   $9, %0\n"
+	            ".word  0x71090019\n"
+	    ::      "r"(val), "r"(reg)
+	    :       "$8", "$9");
+}
+
+static __inline__ uint32_t
+xlr_paddr_lw(uint64_t paddr)
+{
+        uint32_t high, low, tmp;
+
+        high = 0x98000000 | (paddr >> 32);
+        low = paddr & 0xffffffff;
+
+        __asm__ __volatile__(
+                    ".set push         \n\t"
+                    ".set mips64       \n\t"
+                    "dsll32 %1, %1, 0  \n\t"
+                    "dsll32 %2, %2, 0  \n\t"  /* get rid of the */
+                    "dsrl32 %2, %2, 0  \n\t"  /* sign extend */
+                    "or     %1, %1, %2 \n\t"
+                    "lw     %0, 0(%1)  \n\t"
+                    ".set pop           \n"
+            :       "=r"(tmp)
+            :       "r"(high), "r"(low));
+
+	return tmp;
+}
+
+/* for cpuid to hardware thread id mapping */
+extern uint32_t xlr_hw_thread_mask;
+extern int xlr_cpuid_to_hwtid[];
+extern int xlr_hwtid_to_cpuid[];
 
 #endif
diff --git a/sys/mips/rmi/shared_structs_func.h b/sys/mips/rmi/shared_structs_func.h
deleted file mode 100644
index be964140835..00000000000
--- a/sys/mips/rmi/shared_structs_func.h
+++ /dev/null
@@ -1,54 +0,0 @@
-/*-
- * Copyright (c) 2003-2009 RMI Corporation
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in the
- *    documentation and/or other materials provided with the distribution.
- * 3. Neither the name of RMI Corporation, nor the names of its contributors,
- *    may be used to endorse or promote products derived from this software
- *    without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
- *
- * RMI_BSD */
-/* DO NOT EDIT THIS FILE
- * This file has been autogenerated by ./gen_struct_offsets
- */
-#ifndef _SHARED_STRUCTS_FUNC_H
-#define _SHARED_STRUCTS_FUNC_H
-
-/* struct boot1_info function prototypes */
-#define boot1_info_uart_print_func(info_ptr, ...) ((void (*)(const char *, ...))(unsigned long)(info_ptr->uart_print))( __VA_ARGS__ )
-#define boot1_info_led_output_func(info_ptr, ...) ((void (*)(int))(unsigned long)(info_ptr->led_output))( __VA_ARGS__ )
-#define boot1_info_init_func(info_ptr, ...) ((void (*)(void))(unsigned long)(info_ptr->init))( __VA_ARGS__ )
-#define boot1_info_exit_func(info_ptr, ...) ((void (*)(void))(unsigned long)(info_ptr->exit))( __VA_ARGS__ )
-#define boot1_info_warm_reset_func(info_ptr, ...) ((void (*)(void))(unsigned long)(info_ptr->warm_reset))( __VA_ARGS__ )
-#define boot1_info_wakeup_func(info_ptr, ...) ((int (*)(void *, void *, unsigned int))(unsigned long)(info_ptr->wakeup))( __VA_ARGS__ )
-#define boot1_info_master_reentry_fn_func(info_ptr, ...) ((void (*)(void *))(unsigned long)(info_ptr->master_reentry_fn))( __VA_ARGS__ )
-#define boot1_info_slave_reentry_fn_func(info_ptr, ...) ((void (*)(void *))(unsigned long)(info_ptr->slave_reentry_fn))( __VA_ARGS__ )
-#define boot1_info_uart_putchar_func(info_ptr, ...) ((void (*)(char))(unsigned long)(info_ptr->uart_putchar))( __VA_ARGS__ )
-#define boot1_info_uart_getchar_func(info_ptr, ...) ((char (*)(void))(unsigned long)(info_ptr->uart_getchar))( __VA_ARGS__ )
-#define boot1_info_malloc_func(info_ptr, ...) ((void *(*)(size_t))(unsigned long)(info_ptr->malloc))( __VA_ARGS__ )
-#define boot1_info_free_func(info_ptr, ...) ((void (*)(void *))(unsigned long)(info_ptr->free))( __VA_ARGS__ )
-#define boot1_info_alloc_pbuf_func(info_ptr, ...) ((struct packet *(*)(void))(unsigned long)(info_ptr->alloc_pbuf))( __VA_ARGS__ )
-#define boot1_info_free_pbuf_func(info_ptr, ...) ((void (*)(struct packet *))(unsigned long)(info_ptr->free_pbuf))( __VA_ARGS__ )
-#define boot1_info_wakeup_os_func(info_ptr, ...) ((int (*)(void *, void *, unsigned int))(unsigned long)(info_ptr->wakeup_os))( __VA_ARGS__ )
-
-
-#endif
diff --git a/sys/mips/rmi/shared_structs_offsets.h b/sys/mips/rmi/shared_structs_offsets.h
deleted file mode 100644
index 605c735356c..00000000000
--- a/sys/mips/rmi/shared_structs_offsets.h
+++ /dev/null
@@ -1,76 +0,0 @@
-/*-
- * Copyright (c) 2003-2009 RMI Corporation
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in the
- *    documentation and/or other materials provided with the distribution.
- * 3. Neither the name of RMI Corporation, nor the names of its contributors,
- *    may be used to endorse or promote products derived from this software
- *    without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
- *
- * RMI_BSD */
-/* DO NOT EDIT THIS FILE
- * This file has been autogenerated by ./gen_struct_offsets
- */
-#ifndef _SHARED_STRUCTS_OFFSETS_H
-#define _SHARED_STRUCTS_OFFSETS_H
-
-/* struct boot1_info offsets */
-#define boot1_info_boot_level_off 0
-#define boot1_info_io_base_off 8
-#define boot1_info_output_device_off 16
-#define boot1_info_uart_print_off 24
-#define boot1_info_led_output_off 32
-#define boot1_info_init_off 40
-#define boot1_info_exit_off 48
-#define boot1_info_warm_reset_off 56
-#define boot1_info_wakeup_off 64
-#define boot1_info_cpu_online_map_off 72
-#define boot1_info_master_reentry_sp_off 80
-#define boot1_info_master_reentry_gp_off 88
-#define boot1_info_master_reentry_fn_off 96
-#define boot1_info_slave_reentry_fn_off 104
-#define boot1_info_magic_dword_off 112
-#define boot1_info_uart_putchar_off 120
-#define boot1_info_size_off 128
-#define boot1_info_uart_getchar_off 136
-#define boot1_info_nmi_handler_off 144
-#define boot1_info_psb_version_off 152
-#define boot1_info_mac_addr_off 160
-#define boot1_info_cpu_frequency_off 168
-#define boot1_info_board_version_off 176
-#define boot1_info_malloc_off 184
-#define boot1_info_free_off 192
-#define boot1_info_alloc_pbuf_off 200
-#define boot1_info_free_pbuf_off 208
-#define boot1_info_psb_os_cpu_map_off 216
-#define boot1_info_userapp_cpu_map_off 224
-#define boot1_info_wakeup_os_off 232
-#define boot1_info_psb_mem_map_off 240
-
-/* struct boot1_info size */
-#define boot1_info_size 248
-
-/* boot1_info version */
-#define boot1_info_version 1
-
-
-#endif
diff --git a/sys/mips/rmi/xlr_machdep.c b/sys/mips/rmi/xlr_machdep.c
index dec8bc6bbf4..fcbba2c9dd6 100644
--- a/sys/mips/rmi/xlr_machdep.c
+++ b/sys/mips/rmi/xlr_machdep.c
@@ -66,15 +66,14 @@ __FBSDID("$FreeBSD$");
 #include <machine/fls64.h>
 #include <machine/intr_machdep.h>
 #include <machine/smp.h>
-#include <mips/rmi/rmi_mips_exts.h>
 
 #include <mips/rmi/iomap.h>
-#include <mips/rmi/clock.h>
 #include <mips/rmi/msgring.h>
-#include <mips/rmi/xlrconfig.h>
 #include <mips/rmi/interrupt.h>
 #include <mips/rmi/pic.h>
 #include <mips/rmi/board.h>
+#include <mips/rmi/rmi_mips_exts.h>
+#include <mips/rmi/rmi_boot_info.h>
 
 void mpwait(void);
 unsigned long xlr_io_base = (unsigned long)(DEFAULT_XLR_IO_BASE);
diff --git a/sys/mips/rmi/xlr_pci.c b/sys/mips/rmi/xlr_pci.c
index aa1458929a8..a7d3510eaaf 100644
--- a/sys/mips/rmi/xlr_pci.c
+++ b/sys/mips/rmi/xlr_pci.c
@@ -38,23 +38,24 @@ __FBSDID("$FreeBSD$");
 #include <sys/malloc.h>
 #include <sys/bus.h>
 #include <sys/endian.h>
-#include <machine/bus.h>
-#include <machine/md_var.h>
-#include <machine/intr_machdep.h>
-#include <mips/rmi/rmi_mips_exts.h>
-#include <mips/rmi/interrupt.h>
-#include <machine/cpuregs.h>
+#include <sys/rman.h>
+
 #include <vm/vm.h>
 #include <vm/vm_param.h>
 #include <vm/pmap.h>
 
-#include <sys/rman.h>
 #include <dev/pci/pcivar.h>
 #include <dev/pci/pcireg.h>
 
+#include <machine/bus.h>
+#include <machine/md_var.h>
+#include <machine/intr_machdep.h>
+#include <machine/cpuregs.h>
+
+#include <mips/rmi/rmi_mips_exts.h>
+#include <mips/rmi/interrupt.h>
 #include <mips/rmi/iomap.h>
 #include <mips/rmi/pic.h>
-#include <mips/rmi/shared_structs.h>
 #include <mips/rmi/board.h>
 #include <mips/rmi/pcibus.h>
 
diff --git a/sys/mips/rmi/xlrconfig.h b/sys/mips/rmi/xlrconfig.h
deleted file mode 100644
index 1b22f7cc6db..00000000000
--- a/sys/mips/rmi/xlrconfig.h
+++ /dev/null
@@ -1,360 +0,0 @@
-/*-
- * Copyright (c) 2003-2009 RMI Corporation
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in the
- *    documentation and/or other materials provided with the distribution.
- * 3. Neither the name of RMI Corporation, nor the names of its contributors,
- *    may be used to endorse or promote products derived from this software
- *    without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
-  __FBSDID("$FreeBSD$");
- *
- * RMI_BSD */
-#ifndef XLRCONFIG_H
-#define XLRCONFIG_H
-
-#include <sys/types.h>
-#include <mips/rmi/shared_structs.h>
-#include <mips/rmi/shared_structs_func.h>
-
-#define read_c0_register32(reg, sel)                            \
-({ unsigned int __rv;                                           \
-        __asm__ __volatile__(                                   \
-        ".set\tpush\n\t"                                        \
-        ".set mips32\n\t"                                       \
-        "mfc0\t%0,$%1,%2\n\t"                                   \
-        ".set\tpop"                                             \
-        : "=r" (__rv) : "i" (reg), "i" (sel) );                 \
-        __rv;})
-
-#define write_c0_register32(reg,  sel, value)                   \
-        __asm__ __volatile__(                                   \
-        ".set\tpush\n\t"                                        \
-        ".set mips32\n\t"                                       \
-        "mtc0\t%0,$%1,%2\n\t"                                   \
-        ".set\tpop"                                             \
-        : : "r" (value), "i" (reg), "i" (sel) );
-
-#define read_c0_register64(reg, sel)                            \
-   ({ unsigned int __high, __low;                               \
-        __asm__ __volatile__(                                   \
-        ".set\tpush\n\t"                                        \
-        ".set mips64\n\t"                                       \
-        "dmfc0\t $8, $%2, %3\n\t"                               \
-        "dsrl32\t%0, $8, 0\n\t"                                 \
-        "dsll32\t$8, $8, 0\n\t"                                 \
-        "dsrl32\t%1, $8, 0\n\t"                                 \
-        ".set\tpop"                                             \
-        : "=r"(__high), "=r"(__low): "i"(reg), "i"(sel): "$8" );\
-        (((unsigned long long)__high << 32) | __low);})
-
-#define write_c0_register64(reg, sel, value)                    \
- do{                                                            \
-       unsigned int __high = val>>32;                           \
-       unsigned int __low = val & 0xffffffff;                   \
-        __asm__ __volatile__(                                   \
-        ".set\tpush\n\t"                                        \
-        ".set mips64\n\t"                                       \
-        "dsll32\t$8, %1, 0\n\t"                                 \
-        "dsll32\t$9, %0, 0\n\t"                                 \
-        "or\t    $8, $8, $9\n\t"                                \
-        "dmtc0\t $8, $%2, %3\n\t"                               \
-        ".set\tpop"                                             \
-        :: "r"(high), "r"(low),  "i"(reg), "i"(sel):"$8", "$9");\
-   } while(0)
-
-#define read_c2_register32(reg, sel)                            \
-({ unsigned int __rv;                                           \
-        __asm__ __volatile__(                                   \
-        ".set\tpush\n\t"                                        \
-        ".set mips32\n\t"                                       \
-        "mfc2\t%0,$%1,%2\n\t"                                   \
-        ".set\tpop"                                             \
-        : "=r" (__rv) : "i" (reg), "i" (sel) );                 \
-        __rv;})
-
-#define write_c2_register32(reg,  sel, value)                   \
-        __asm__ __volatile__(                                   \
-        ".set\tpush\n\t"                                        \
-        ".set mips32\n\t"                                       \
-        "mtc2\t%0,$%1,%2\n\t"                                   \
-        ".set\tpop"                                             \
-        : : "r" (value), "i" (reg), "i" (sel) );
-
-#define read_c2_register64(reg, sel)                            \
-   ({ unsigned int __high, __low;                               \
-        __asm__ __volatile__(                                   \
-        ".set mips64\n\t"                                       \
-        "dmfc2\t $8, $%2, %3\n\t"                               \
-        "dsrl32\t%0, $8, 0\n\t"                                 \
-        "dsll32\t$8, $8, 0\n\t"                                 \
-        "dsrl32\t%1, $8, 0\n\t"                                 \
-        ".set\tmips0"                                           \
-        : "=r"(__high), "=r"(__low): "i"(reg), "i"(sel): "$8" );\
-        (((unsigned long long)__high << 32) | __low);})
-
-#define write_c2_register64(reg, sel, value)                    \
- do{                                                            \
-       unsigned int __high = value>>32;                         \
-       unsigned int __low = value & 0xffffffff;                 \
-        __asm__ __volatile__(                                   \
-        ".set mips64\n\t"                                       \
-        "dsll32\t$8, %1, 0\n\t"                                 \
-        "dsll32\t$9, %0, 0\n\t"                                 \
-        "dsrl32\t$8, $8, 0\n\t"                                 \
-        "or\t    $8, $8, $9\n\t"                                \
-        "dmtc2\t $8, $%2, %3\n\t"                               \
-        ".set\tmips0"                                           \
-        :: "r"(__high), "r"(__low),                             \
-           "i"(reg), "i"(sel)                                   \
-        :"$8", "$9");                                           \
-   } while(0)
-
-#define xlr_cpu_id()                                            \
-({int __id;                                                     \
- __asm__ __volatile__ (                                         \
-           ".set push\n"                                        \
-           ".set noreorder\n"                                   \
-           "mfc0 $8, $15, 1\n"                                  \
-           "andi %0, $8, 0x1f\n"                                \
-           ".set pop\n"                                         \
-           : "=r" (__id) : : "$8");                             \
- __id;})
-
-#define xlr_core_id()                                           \
-({int __id;                                                     \
- __asm__ __volatile__ (                                         \
-           ".set push\n"                                        \
-           ".set noreorder\n"                                   \
-           "mfc0 $8, $15, 1\n"                                  \
-           "andi %0, $8, 0x1f\n"                                \
-           ".set pop\n"                                         \
-           : "=r" (__id) : : "$8");                             \
- __id/4;})
-
-#define xlr_thr_id()                                            \
-({int __id;                                                     \
- __asm__ __volatile__ (                                         \
-           ".set push\n"                                        \
-           ".set noreorder\n"                                   \
-           "mfc0 $8, $15, 1\n"                                  \
-           "andi %0, $8, 0x3\n"                                 \
-           ".set pop\n"                                         \
-           : "=r" (__id) : : "$8");                             \
- __id;})
-
-
-/* Additional registers on the XLR */
-#define MIPS_COP_0_OSSCRATCH   22
-
-#define XLR_CACHELINE_SIZE 32
-
-#define XLR_MAX_CORES 8
-
-/* functions to write to and read from the extended
- * cp0 registers.
- * EIRR : Extended Interrupt Request Register
- *        cp0 register 9 sel 6
- *        bits 0...7 are same as cause register 8...15
- * EIMR : Extended Interrupt Mask Register
- *        cp0 register 9 sel 7
- *        bits 0...7 are same as status register 8...15
- */
-
-static inline uint64_t 
-read_c0_eirr64(void)
-{
-	__uint32_t high, low;
-
-	__asm__ __volatile__(
-	            ".set push\n"
-	            ".set noreorder\n"
-	            ".set noat\n"
-	            ".set mips4\n"
-
-	            ".word 0x40214806  \n\t"
-	            "nop               \n\t"
-	            "dsra32 %0, $1, 0  \n\t"
-	            "sll    %1, $1, 0  \n\t"
-
-	            ".set pop\n"
-
-	    :       "=r"(high), "=r"(low)
-	);
-
-	return (((__uint64_t) high) << 32) | low;
-}
-
-static inline __uint64_t 
-read_c0_eimr64(void)
-{
-	__uint32_t high, low;
-
-	__asm__ __volatile__(
-	            ".set push\n"
-	            ".set noreorder\n"
-	            ".set noat\n"
-	            ".set mips4\n"
-
-	            ".word 0x40214807  \n\t"
-	            "nop               \n\t"
-	            "dsra32 %0, $1, 0  \n\t"
-	            "sll    %1, $1, 0  \n\t"
-
-	            ".set pop\n"
-
-	    :       "=r"(high), "=r"(low)
-	);
-
-	return (((__uint64_t) high) << 32) | low;
-}
-
-static inline void 
-write_c0_eirr64(__uint64_t value)
-{
-	__uint32_t low, high;
-
-	high = value >> 32;
-	low = value & 0xffffffff;
-
-	__asm__ __volatile__(
-	            ".set push\n"
-	            ".set noreorder\n"
-	            ".set noat\n"
-	            ".set mips4\n\t"
-
-	            "dsll32 $2, %1, 0  \n\t"
-	            "dsll32 $1, %0, 0  \n\t"
-	            "dsrl32 $2, $2, 0  \n\t"
-	            "or     $1, $1, $2 \n\t"
-	            ".word  0x40a14806 \n\t"
-	            "nop               \n\t"
-
-	            ".set pop\n"
-
-	    :
-	    :       "r"(high), "r"(low)
-	    :       "$1", "$2");
-}
-
-static inline void 
-write_c0_eimr64(__uint64_t value)
-{
-	__uint32_t low, high;
-
-	high = value >> 32;
-	low = value & 0xffffffff;
-
-	__asm__ __volatile__(
-	            ".set push\n"
-	            ".set noreorder\n"
-	            ".set noat\n"
-	            ".set mips4\n\t"
-
-	            "dsll32 $2, %1, 0  \n\t"
-	            "dsll32 $1, %0, 0  \n\t"
-	            "dsrl32 $2, $2, 0  \n\t"
-	            "or     $1, $1, $2 \n\t"
-	            ".word  0x40a14807 \n\t"
-	            "nop               \n\t"
-
-	            ".set pop\n"
-
-	    :
-	    :       "r"(high), "r"(low)
-	    :       "$1", "$2");
-}
-
-static __inline__ int 
-xlr_test_and_set(int *lock)
-{
-	int oldval = 0;
-
-	__asm__ __volatile__(".set push\n"
-	            ".set noreorder\n"
-	            "move $9, %2\n"
-	            "li $8, 1\n"
-	    //      "swapw $8, $9\n"
-	            ".word 0x71280014\n"
-	            "move %1, $8\n"
-	            ".set pop\n"
-	    :       "+m"(*lock), "=r"(oldval)
-	    :       "r"((unsigned long)lock)
-	    :       "$8", "$9"
-	);
-
-	return (oldval == 0 ? 1 /* success */ : 0 /* failure */ );
-}
-
-static __inline__ uint32_t 
-xlr_mfcr(uint32_t reg)
-{
-	uint32_t val;
-
-	__asm__ __volatile__(
-	            "move   $8, %1\n"
-	            ".word  0x71090018\n"
-	            "move   %0, $9\n"
-	    :       "=r"(val)
-	    :       "r"(reg):"$8", "$9");
-
-	return val;
-}
-
-static __inline__ void 
-xlr_mtcr(uint32_t reg, uint32_t val)
-{
-	__asm__ __volatile__(
-	            "move   $8, %1\n"
-	            "move   $9, %0\n"
-	            ".word  0x71090019\n"
-	    ::      "r"(val), "r"(reg)
-	    :       "$8", "$9");
-}
-
-static __inline__ uint32_t
-xlr_paddr_lw(uint64_t paddr)
-{
-        uint32_t high, low, tmp;
-
-        high = 0x98000000 | (paddr >> 32);
-        low = paddr & 0xffffffff;
-
-        __asm__ __volatile__(
-                    ".set push         \n\t"
-                    ".set mips64       \n\t"
-                    "dsll32 %1, %1, 0  \n\t"
-                    "dsll32 %2, %2, 0  \n\t"  /* get rid of the */
-                    "dsrl32 %2, %2, 0  \n\t"  /* sign extend */
-                    "or     %1, %1, %2 \n\t"
-                    "lw     %0, 0(%1)  \n\t"
-                    ".set pop           \n"
-            :       "=r"(tmp)
-            :       "r"(high), "r"(low));
-
-	return tmp;
-}
-
-/* for cpuid to hardware thread id mapping */
-extern uint32_t xlr_hw_thread_mask;
-extern int xlr_cpuid_to_hwtid[];
-extern int xlr_hwtid_to_cpuid[];
-#endif