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Add PMC support for AMD Family CPUs
This commit is contained in:
Matt Macy
parent
17fffb23f6
commit
6044931335
6 changed files with 5549 additions and 0 deletions
1987
lib/libpmc/pmu-events/arch/x86/amdfam17h/cache.json
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1987
lib/libpmc/pmu-events/arch/x86/amdfam17h/cache.json
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File diff suppressed because it is too large
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739
lib/libpmc/pmu-events/arch/x86/amdfam17h/core.json
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739
lib/libpmc/pmu-events/arch/x86/amdfam17h/core.json
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@ -0,0 +1,739 @@
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[
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{
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"EventName": "ex_ret_instr",
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"EventCode": "0xc0",
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"BriefDescription": "Retired Instructions."
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},
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{
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"EventName": "ex_ret_cops",
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||||
"EventCode": "0xc1",
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||||
"BriefDescription": "The number of uOps retired. This includes all processor activity (instructions, exceptions, interrupts, microcode assists, etc.). The number of events logged per cycle can vary from 0 to 4."
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},
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{
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||||
"EventName": "ex_ret_brn",
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||||
"EventCode": "0xc2",
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||||
"BriefDescription": "The number of branch instructions retired. This includes all types of architectural control flow changes, including exceptions and interrupts."
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||||
},
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||||
{
|
||||
"EventName": "ex_ret_brn_misp",
|
||||
"EventCode": "0xc3",
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||||
"BriefDescription": "The number of branch instructions retired, of any type, that were not correctly predicted. This includes those for which prediction is not attempted (far control transfers, exceptions and interrupts)."
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},
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{
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||||
"EventName": "ex_ret_brn_tkn",
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||||
"EventCode": "0xc4",
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||||
"BriefDescription": "The number of taken branches that were retired. This includes all types of architectural control flow changes, including exceptions and interrupts."
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},
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||||
{
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"EventName": "ex_ret_brn_tkn_misp",
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||||
"EventCode": "0xc5",
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||||
"BriefDescription": "The number of retired taken branch instructions that were mispredicted."
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},
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{
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"EventName": "ex_ret_brn_far",
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"EventCode": "0xc6",
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"BriefDescription": "The number of far control transfers retired including far call/jump/return, IRET, SYSCALL and SYSRET, plus exceptions and interrupts. Far control transfers are not subject to branch prediction."
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},
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{
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"EventName": "ex_ret_brn_resync",
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"EventCode": "0xc7",
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"BriefDescription": "The number of resync branches. These reflect pipeline restarts due to certain microcode assists and events such as writes to the active instruction stream, among other things. Each occurrence reflects a restart penalty similar to a branch mispredict. This is relatively rare."
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},
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{
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"EventName": "ex_ret_near_ret",
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"EventCode": "0xc8",
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"BriefDescription": "The number of near return instructions (RET or RET Iw) retired."
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},
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{
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"EventName": "ex_ret_near_ret_mispred",
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"EventCode": "0xc9",
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"BriefDescription": "The number of near returns retired that were not correctly predicted by the return address predictor. Each such mispredict incurs the same penalty as a mispredicted conditional branch instruction."
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},
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{
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"EventName": "ex_ret_brn_ind_misp",
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"EventCode": "0xca",
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"BriefDescription": "Retired Indirect Branch Instructions Mispredicted."
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},
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{
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"EventName": "ex_ret_mmx_fp_instr.sse_instr",
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"EventCode": "0xcb",
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"BriefDescription": "SSE instructions (SSE, SSE2, SSE3, SSSE3, SSE4A, SSE41, SSE42, AVX).",
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"PublicDescription": "The number of MMX, SSE or x87 instructions retired. The UnitMask allows the selection of the individual classes of instructions as given in the table. Each increment represents one complete instruction. Since this event includes non-numeric instructions it is not suitable for measuring MFLOPS. SSE instructions (SSE, SSE2, SSE3, SSSE3, SSE4A, SSE41, SSE42, AVX).",
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"UMask": "0x4"
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},
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{
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"EventName": "ex_ret_mmx_fp_instr.mmx_instr",
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"EventCode": "0xcb",
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"BriefDescription": "MMX instructions.",
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"PublicDescription": "The number of MMX, SSE or x87 instructions retired. The UnitMask allows the selection of the individual classes of instructions as given in the table. Each increment represents one complete instruction. Since this event includes non-numeric instructions it is not suitable for measuring MFLOPS. MMX instructions.",
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"UMask": "0x2"
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},
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{
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"EventName": "ex_ret_mmx_fp_instr.x87_instr",
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"EventCode": "0xcb",
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"BriefDescription": "x87 instructions.",
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"PublicDescription": "The number of MMX, SSE or x87 instructions retired. The UnitMask allows the selection of the individual classes of instructions as given in the table. Each increment represents one complete instruction. Since this event includes non-numeric instructions it is not suitable for measuring MFLOPS. x87 instructions.",
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"UMask": "0x1"
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},
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{
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"EventName": "ex_ret_cond",
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"EventCode": "0xd1",
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"BriefDescription": "Retired Conditional Branch Instructions."
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},
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{
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"EventName": "ex_ret_cond_misp",
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"EventCode": "0xd2",
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"BriefDescription": "Retired Conditional Branch Instructions Mispredicted."
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},
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{
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"EventName": "ex_div_busy",
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"EventCode": "0xd3",
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"BriefDescription": "Div Cycles Busy count."
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},
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{
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"EventName": "ex_div_count",
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"EventCode": "0xd4",
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"BriefDescription": "Div Op Count."
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},
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{
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"EventName": "ex_tagged_ibs_ops.ibs_count_rollover",
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"EventCode": "0x1cf",
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"BriefDescription": "Number of times an op could not be tagged by IBS because of a previous tagged op that has not retired.",
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"PublicDescription": "Tagged IBS Ops. Number of times an op could not be tagged by IBS because of a previous tagged op that has not retired.",
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"UMask": "0x4"
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},
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{
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"EventName": "ex_tagged_ibs_ops.ibs_tagged_ops_ret",
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"EventCode": "0x1cf",
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"BriefDescription": "Number of Ops tagged by IBS that retired.",
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"PublicDescription": "Tagged IBS Ops. Number of Ops tagged by IBS that retired.",
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"UMask": "0x2"
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},
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{
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"EventName": "ex_tagged_ibs_ops.ibs_tagged_ops",
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"EventCode": "0x1cf",
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"BriefDescription": "Number of Ops tagged by IBS.",
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"PublicDescription": "Tagged IBS Ops. Number of Ops tagged by IBS.",
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"UMask": "0x1"
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},
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{
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"EventName": "ex_ret_fus_brnch_inst",
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"EventCode": "0x1d0",
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"BriefDescription": "The number of fused retired branch instructions retired per cycle. The number of events logged per cycle can vary from 0 to 3."
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}
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][
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{
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"EventName": "ex_ret_instr",
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"EventCode": "0xc0",
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"BriefDescription": "Retired Instructions."
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},
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{
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"EventName": "ex_ret_cops",
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"EventCode": "0xc1",
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"BriefDescription": "The number of uOps retired. This includes all processor activity (instructions, exceptions, interrupts, microcode assists, etc.). The number of events logged per cycle can vary from 0 to 4."
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},
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{
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"EventName": "ex_ret_brn",
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"EventCode": "0xc2",
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"BriefDescription": "The number of branch instructions retired. This includes all types of architectural control flow changes, including exceptions and interrupts."
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},
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{
|
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"EventName": "ex_ret_brn_misp",
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"EventCode": "0xc3",
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"BriefDescription": "The number of branch instructions retired, of any type, that were not correctly predicted. This includes those for which prediction is not attempted (far control transfers, exceptions and interrupts)."
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},
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{
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"EventName": "ex_ret_brn_tkn",
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"EventCode": "0xc4",
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"BriefDescription": "The number of taken branches that were retired. This includes all types of architectural control flow changes, including exceptions and interrupts."
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},
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{
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"EventName": "ex_ret_brn_tkn_misp",
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"EventCode": "0xc5",
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"BriefDescription": "The number of retired taken branch instructions that were mispredicted."
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},
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{
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"EventName": "ex_ret_brn_far",
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"EventCode": "0xc6",
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"BriefDescription": "The number of far control transfers retired including far call/jump/return, IRET, SYSCALL and SYSRET, plus exceptions and interrupts. Far control transfers are not subject to branch prediction."
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},
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{
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"EventName": "ex_ret_brn_resync",
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"EventCode": "0xc7",
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"BriefDescription": "The number of resync branches. These reflect pipeline restarts due to certain microcode assists and events such as writes to the active instruction stream, among other things. Each occurrence reflects a restart penalty similar to a branch mispredict. This is relatively rare."
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},
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{
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"EventName": "ex_ret_near_ret",
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"EventCode": "0xc8",
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"BriefDescription": "The number of near return instructions (RET or RET Iw) retired."
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},
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{
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"EventName": "ex_ret_near_ret_mispred",
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"EventCode": "0xc9",
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"BriefDescription": "The number of near returns retired that were not correctly predicted by the return address predictor. Each such mispredict incurs the same penalty as a mispredicted conditional branch instruction."
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},
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{
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"EventName": "ex_ret_brn_ind_misp",
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"EventCode": "0xca",
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"BriefDescription": "Retired Indirect Branch Instructions Mispredicted."
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},
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{
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"EventName": "ex_ret_mmx_fp_instr.sse_instr",
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"EventCode": "0xcb",
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"BriefDescription": "SSE instructions (SSE, SSE2, SSE3, SSSE3, SSE4A, SSE41, SSE42, AVX).",
|
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"PublicDescription": "The number of MMX, SSE or x87 instructions retired. The UnitMask allows the selection of the individual classes of instructions as given in the table. Each increment represents one complete instruction. Since this event includes non-numeric instructions it is not suitable for measuring MFLOPS. SSE instructions (SSE, SSE2, SSE3, SSSE3, SSE4A, SSE41, SSE42, AVX).",
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"UMask": "0x4"
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},
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{
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"EventName": "ex_ret_mmx_fp_instr.mmx_instr",
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"EventCode": "0xcb",
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"BriefDescription": "MMX instructions.",
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"PublicDescription": "The number of MMX, SSE or x87 instructions retired. The UnitMask allows the selection of the individual classes of instructions as given in the table. Each increment represents one complete instruction. Since this event includes non-numeric instructions it is not suitable for measuring MFLOPS. MMX instructions.",
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"UMask": "0x2"
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},
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{
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"EventName": "ex_ret_mmx_fp_instr.x87_instr",
|
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"EventCode": "0xcb",
|
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"BriefDescription": "x87 instructions.",
|
||||
"PublicDescription": "The number of MMX, SSE or x87 instructions retired. The UnitMask allows the selection of the individual classes of instructions as given in the table. Each increment represents one complete instruction. Since this event includes non-numeric instructions it is not suitable for measuring MFLOPS. x87 instructions.",
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"UMask": "0x1"
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},
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{
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"EventName": "ex_ret_cond",
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"EventCode": "0xd1",
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"BriefDescription": "Retired Conditional Branch Instructions."
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},
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{
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"EventName": "ex_ret_cond_misp",
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"EventCode": "0xd2",
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"BriefDescription": "Retired Conditional Branch Instructions Mispredicted."
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},
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{
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"EventName": "ex_div_busy",
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"EventCode": "0xd3",
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"BriefDescription": "Div Cycles Busy count."
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},
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{
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"EventName": "ex_div_count",
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"EventCode": "0xd4",
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"BriefDescription": "Div Op Count."
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},
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{
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"EventName": "ex_tagged_ibs_ops.ibs_count_rollover",
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"EventCode": "0x1cf",
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"BriefDescription": "Number of times an op could not be tagged by IBS because of a previous tagged op that has not retired.",
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||||
"PublicDescription": "Tagged IBS Ops. Number of times an op could not be tagged by IBS because of a previous tagged op that has not retired.",
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"UMask": "0x4"
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},
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{
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"EventName": "ex_tagged_ibs_ops.ibs_tagged_ops_ret",
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"EventCode": "0x1cf",
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"BriefDescription": "Number of Ops tagged by IBS that retired.",
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"PublicDescription": "Tagged IBS Ops. Number of Ops tagged by IBS that retired.",
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"UMask": "0x2"
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},
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{
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"EventName": "ex_tagged_ibs_ops.ibs_tagged_ops",
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"EventCode": "0x1cf",
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"BriefDescription": "Number of Ops tagged by IBS.",
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"PublicDescription": "Tagged IBS Ops. Number of Ops tagged by IBS.",
|
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"UMask": "0x1"
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},
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{
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"EventName": "ex_ret_fus_brnch_inst",
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"EventCode": "0x1d0",
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"BriefDescription": "The number of fused retired branch instructions retired per cycle. The number of events logged per cycle can vary from 0 to 3."
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}
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][
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{
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"EventName": "ex_ret_instr",
|
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"EventCode": "0xc0",
|
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"BriefDescription": "Retired Instructions."
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},
|
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{
|
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"EventName": "ex_ret_cops",
|
||||
"EventCode": "0xc1",
|
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"BriefDescription": "The number of uOps retired. This includes all processor activity (instructions, exceptions, interrupts, microcode assists, etc.). The number of events logged per cycle can vary from 0 to 4."
|
||||
},
|
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{
|
||||
"EventName": "ex_ret_brn",
|
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"EventCode": "0xc2",
|
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"BriefDescription": "The number of branch instructions retired. This includes all types of architectural control flow changes, including exceptions and interrupts."
|
||||
},
|
||||
{
|
||||
"EventName": "ex_ret_brn_misp",
|
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"EventCode": "0xc3",
|
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"BriefDescription": "The number of branch instructions retired, of any type, that were not correctly predicted. This includes those for which prediction is not attempted (far control transfers, exceptions and interrupts)."
|
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},
|
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{
|
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"EventName": "ex_ret_brn_tkn",
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"EventCode": "0xc4",
|
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"BriefDescription": "The number of taken branches that were retired. This includes all types of architectural control flow changes, including exceptions and interrupts."
|
||||
},
|
||||
{
|
||||
"EventName": "ex_ret_brn_tkn_misp",
|
||||
"EventCode": "0xc5",
|
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"BriefDescription": "The number of retired taken branch instructions that were mispredicted."
|
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},
|
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{
|
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"EventName": "ex_ret_brn_far",
|
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"EventCode": "0xc6",
|
||||
"BriefDescription": "The number of far control transfers retired including far call/jump/return, IRET, SYSCALL and SYSRET, plus exceptions and interrupts. Far control transfers are not subject to branch prediction."
|
||||
},
|
||||
{
|
||||
"EventName": "ex_ret_brn_resync",
|
||||
"EventCode": "0xc7",
|
||||
"BriefDescription": "The number of resync branches. These reflect pipeline restarts due to certain microcode assists and events such as writes to the active instruction stream, among other things. Each occurrence reflects a restart penalty similar to a branch mispredict. This is relatively rare."
|
||||
},
|
||||
{
|
||||
"EventName": "ex_ret_near_ret",
|
||||
"EventCode": "0xc8",
|
||||
"BriefDescription": "The number of near return instructions (RET or RET Iw) retired."
|
||||
},
|
||||
{
|
||||
"EventName": "ex_ret_near_ret_mispred",
|
||||
"EventCode": "0xc9",
|
||||
"BriefDescription": "The number of near returns retired that were not correctly predicted by the return address predictor. Each such mispredict incurs the same penalty as a mispredicted conditional branch instruction."
|
||||
},
|
||||
{
|
||||
"EventName": "ex_ret_brn_ind_misp",
|
||||
"EventCode": "0xca",
|
||||
"BriefDescription": "Retired Indirect Branch Instructions Mispredicted."
|
||||
},
|
||||
{
|
||||
"EventName": "ex_ret_mmx_fp_instr.sse_instr",
|
||||
"EventCode": "0xcb",
|
||||
"BriefDescription": "SSE instructions (SSE, SSE2, SSE3, SSSE3, SSE4A, SSE41, SSE42, AVX).",
|
||||
"PublicDescription": "The number of MMX, SSE or x87 instructions retired. The UnitMask allows the selection of the individual classes of instructions as given in the table. Each increment represents one complete instruction. Since this event includes non-numeric instructions it is not suitable for measuring MFLOPS. SSE instructions (SSE, SSE2, SSE3, SSSE3, SSE4A, SSE41, SSE42, AVX).",
|
||||
"UMask": "0x4"
|
||||
},
|
||||
{
|
||||
"EventName": "ex_ret_mmx_fp_instr.mmx_instr",
|
||||
"EventCode": "0xcb",
|
||||
"BriefDescription": "MMX instructions.",
|
||||
"PublicDescription": "The number of MMX, SSE or x87 instructions retired. The UnitMask allows the selection of the individual classes of instructions as given in the table. Each increment represents one complete instruction. Since this event includes non-numeric instructions it is not suitable for measuring MFLOPS. MMX instructions.",
|
||||
"UMask": "0x2"
|
||||
},
|
||||
{
|
||||
"EventName": "ex_ret_mmx_fp_instr.x87_instr",
|
||||
"EventCode": "0xcb",
|
||||
"BriefDescription": "x87 instructions.",
|
||||
"PublicDescription": "The number of MMX, SSE or x87 instructions retired. The UnitMask allows the selection of the individual classes of instructions as given in the table. Each increment represents one complete instruction. Since this event includes non-numeric instructions it is not suitable for measuring MFLOPS. x87 instructions.",
|
||||
"UMask": "0x1"
|
||||
},
|
||||
{
|
||||
"EventName": "ex_ret_cond",
|
||||
"EventCode": "0xd1",
|
||||
"BriefDescription": "Retired Conditional Branch Instructions."
|
||||
},
|
||||
{
|
||||
"EventName": "ex_ret_cond_misp",
|
||||
"EventCode": "0xd2",
|
||||
"BriefDescription": "Retired Conditional Branch Instructions Mispredicted."
|
||||
},
|
||||
{
|
||||
"EventName": "ex_div_busy",
|
||||
"EventCode": "0xd3",
|
||||
"BriefDescription": "Div Cycles Busy count."
|
||||
},
|
||||
{
|
||||
"EventName": "ex_div_count",
|
||||
"EventCode": "0xd4",
|
||||
"BriefDescription": "Div Op Count."
|
||||
},
|
||||
{
|
||||
"EventName": "ex_tagged_ibs_ops.ibs_count_rollover",
|
||||
"EventCode": "0x1cf",
|
||||
"BriefDescription": "Number of times an op could not be tagged by IBS because of a previous tagged op that has not retired.",
|
||||
"PublicDescription": "Tagged IBS Ops. Number of times an op could not be tagged by IBS because of a previous tagged op that has not retired.",
|
||||
"UMask": "0x4"
|
||||
},
|
||||
{
|
||||
"EventName": "ex_tagged_ibs_ops.ibs_tagged_ops_ret",
|
||||
"EventCode": "0x1cf",
|
||||
"BriefDescription": "Number of Ops tagged by IBS that retired.",
|
||||
"PublicDescription": "Tagged IBS Ops. Number of Ops tagged by IBS that retired.",
|
||||
"UMask": "0x2"
|
||||
},
|
||||
{
|
||||
"EventName": "ex_tagged_ibs_ops.ibs_tagged_ops",
|
||||
"EventCode": "0x1cf",
|
||||
"BriefDescription": "Number of Ops tagged by IBS.",
|
||||
"PublicDescription": "Tagged IBS Ops. Number of Ops tagged by IBS.",
|
||||
"UMask": "0x1"
|
||||
},
|
||||
{
|
||||
"EventName": "ex_ret_fus_brnch_inst",
|
||||
"EventCode": "0x1d0",
|
||||
"BriefDescription": "The number of fused retired branch instructions retired per cycle. The number of events logged per cycle can vary from 0 to 3."
|
||||
}
|
||||
][
|
||||
{
|
||||
"EventName": "ex_ret_instr",
|
||||
"EventCode": "0xc0",
|
||||
"BriefDescription": "Retired Instructions."
|
||||
},
|
||||
{
|
||||
"EventName": "ex_ret_cops",
|
||||
"EventCode": "0xc1",
|
||||
"BriefDescription": "The number of uOps retired. This includes all processor activity (instructions, exceptions, interrupts, microcode assists, etc.). The number of events logged per cycle can vary from 0 to 4."
|
||||
},
|
||||
{
|
||||
"EventName": "ex_ret_brn",
|
||||
"EventCode": "0xc2",
|
||||
"BriefDescription": "The number of branch instructions retired. This includes all types of architectural control flow changes, including exceptions and interrupts."
|
||||
},
|
||||
{
|
||||
"EventName": "ex_ret_brn_misp",
|
||||
"EventCode": "0xc3",
|
||||
"BriefDescription": "The number of branch instructions retired, of any type, that were not correctly predicted. This includes those for which prediction is not attempted (far control transfers, exceptions and interrupts)."
|
||||
},
|
||||
{
|
||||
"EventName": "ex_ret_brn_tkn",
|
||||
"EventCode": "0xc4",
|
||||
"BriefDescription": "The number of taken branches that were retired. This includes all types of architectural control flow changes, including exceptions and interrupts."
|
||||
},
|
||||
{
|
||||
"EventName": "ex_ret_brn_tkn_misp",
|
||||
"EventCode": "0xc5",
|
||||
"BriefDescription": "The number of retired taken branch instructions that were mispredicted."
|
||||
},
|
||||
{
|
||||
"EventName": "ex_ret_brn_far",
|
||||
"EventCode": "0xc6",
|
||||
"BriefDescription": "The number of far control transfers retired including far call/jump/return, IRET, SYSCALL and SYSRET, plus exceptions and interrupts. Far control transfers are not subject to branch prediction."
|
||||
},
|
||||
{
|
||||
"EventName": "ex_ret_brn_resync",
|
||||
"EventCode": "0xc7",
|
||||
"BriefDescription": "The number of resync branches. These reflect pipeline restarts due to certain microcode assists and events such as writes to the active instruction stream, among other things. Each occurrence reflects a restart penalty similar to a branch mispredict. This is relatively rare."
|
||||
},
|
||||
{
|
||||
"EventName": "ex_ret_near_ret",
|
||||
"EventCode": "0xc8",
|
||||
"BriefDescription": "The number of near return instructions (RET or RET Iw) retired."
|
||||
},
|
||||
{
|
||||
"EventName": "ex_ret_near_ret_mispred",
|
||||
"EventCode": "0xc9",
|
||||
"BriefDescription": "The number of near returns retired that were not correctly predicted by the return address predictor. Each such mispredict incurs the same penalty as a mispredicted conditional branch instruction."
|
||||
},
|
||||
{
|
||||
"EventName": "ex_ret_brn_ind_misp",
|
||||
"EventCode": "0xca",
|
||||
"BriefDescription": "Retired Indirect Branch Instructions Mispredicted."
|
||||
},
|
||||
{
|
||||
"EventName": "ex_ret_mmx_fp_instr.sse_instr",
|
||||
"EventCode": "0xcb",
|
||||
"BriefDescription": "SSE instructions (SSE, SSE2, SSE3, SSSE3, SSE4A, SSE41, SSE42, AVX).",
|
||||
"PublicDescription": "The number of MMX, SSE or x87 instructions retired. The UnitMask allows the selection of the individual classes of instructions as given in the table. Each increment represents one complete instruction. Since this event includes non-numeric instructions it is not suitable for measuring MFLOPS. SSE instructions (SSE, SSE2, SSE3, SSSE3, SSE4A, SSE41, SSE42, AVX).",
|
||||
"UMask": "0x4"
|
||||
},
|
||||
{
|
||||
"EventName": "ex_ret_mmx_fp_instr.mmx_instr",
|
||||
"EventCode": "0xcb",
|
||||
"BriefDescription": "MMX instructions.",
|
||||
"PublicDescription": "The number of MMX, SSE or x87 instructions retired. The UnitMask allows the selection of the individual classes of instructions as given in the table. Each increment represents one complete instruction. Since this event includes non-numeric instructions it is not suitable for measuring MFLOPS. MMX instructions.",
|
||||
"UMask": "0x2"
|
||||
},
|
||||
{
|
||||
"EventName": "ex_ret_mmx_fp_instr.x87_instr",
|
||||
"EventCode": "0xcb",
|
||||
"BriefDescription": "x87 instructions.",
|
||||
"PublicDescription": "The number of MMX, SSE or x87 instructions retired. The UnitMask allows the selection of the individual classes of instructions as given in the table. Each increment represents one complete instruction. Since this event includes non-numeric instructions it is not suitable for measuring MFLOPS. x87 instructions.",
|
||||
"UMask": "0x1"
|
||||
},
|
||||
{
|
||||
"EventName": "ex_ret_cond",
|
||||
"EventCode": "0xd1",
|
||||
"BriefDescription": "Retired Conditional Branch Instructions."
|
||||
},
|
||||
{
|
||||
"EventName": "ex_ret_cond_misp",
|
||||
"EventCode": "0xd2",
|
||||
"BriefDescription": "Retired Conditional Branch Instructions Mispredicted."
|
||||
},
|
||||
{
|
||||
"EventName": "ex_div_busy",
|
||||
"EventCode": "0xd3",
|
||||
"BriefDescription": "Div Cycles Busy count."
|
||||
},
|
||||
{
|
||||
"EventName": "ex_div_count",
|
||||
"EventCode": "0xd4",
|
||||
"BriefDescription": "Div Op Count."
|
||||
},
|
||||
{
|
||||
"EventName": "ex_tagged_ibs_ops.ibs_count_rollover",
|
||||
"EventCode": "0x1cf",
|
||||
"BriefDescription": "Number of times an op could not be tagged by IBS because of a previous tagged op that has not retired.",
|
||||
"PublicDescription": "Tagged IBS Ops. Number of times an op could not be tagged by IBS because of a previous tagged op that has not retired.",
|
||||
"UMask": "0x4"
|
||||
},
|
||||
{
|
||||
"EventName": "ex_tagged_ibs_ops.ibs_tagged_ops_ret",
|
||||
"EventCode": "0x1cf",
|
||||
"BriefDescription": "Number of Ops tagged by IBS that retired.",
|
||||
"PublicDescription": "Tagged IBS Ops. Number of Ops tagged by IBS that retired.",
|
||||
"UMask": "0x2"
|
||||
},
|
||||
{
|
||||
"EventName": "ex_tagged_ibs_ops.ibs_tagged_ops",
|
||||
"EventCode": "0x1cf",
|
||||
"BriefDescription": "Number of Ops tagged by IBS.",
|
||||
"PublicDescription": "Tagged IBS Ops. Number of Ops tagged by IBS.",
|
||||
"UMask": "0x1"
|
||||
},
|
||||
{
|
||||
"EventName": "ex_ret_fus_brnch_inst",
|
||||
"EventCode": "0x1d0",
|
||||
"BriefDescription": "The number of fused retired branch instructions retired per cycle. The number of events logged per cycle can vary from 0 to 3."
|
||||
}
|
||||
][
|
||||
{
|
||||
"EventName": "ex_ret_instr",
|
||||
"EventCode": "0xc0",
|
||||
"BriefDescription": "Retired Instructions."
|
||||
},
|
||||
{
|
||||
"EventName": "ex_ret_cops",
|
||||
"EventCode": "0xc1",
|
||||
"BriefDescription": "The number of uOps retired. This includes all processor activity (instructions, exceptions, interrupts, microcode assists, etc.). The number of events logged per cycle can vary from 0 to 4."
|
||||
},
|
||||
{
|
||||
"EventName": "ex_ret_brn",
|
||||
"EventCode": "0xc2",
|
||||
"BriefDescription": "The number of branch instructions retired. This includes all types of architectural control flow changes, including exceptions and interrupts."
|
||||
},
|
||||
{
|
||||
"EventName": "ex_ret_brn_misp",
|
||||
"EventCode": "0xc3",
|
||||
"BriefDescription": "The number of branch instructions retired, of any type, that were not correctly predicted. This includes those for which prediction is not attempted (far control transfers, exceptions and interrupts)."
|
||||
},
|
||||
{
|
||||
"EventName": "ex_ret_brn_tkn",
|
||||
"EventCode": "0xc4",
|
||||
"BriefDescription": "The number of taken branches that were retired. This includes all types of architectural control flow changes, including exceptions and interrupts."
|
||||
},
|
||||
{
|
||||
"EventName": "ex_ret_brn_tkn_misp",
|
||||
"EventCode": "0xc5",
|
||||
"BriefDescription": "The number of retired taken branch instructions that were mispredicted."
|
||||
},
|
||||
{
|
||||
"EventName": "ex_ret_brn_far",
|
||||
"EventCode": "0xc6",
|
||||
"BriefDescription": "The number of far control transfers retired including far call/jump/return, IRET, SYSCALL and SYSRET, plus exceptions and interrupts. Far control transfers are not subject to branch prediction."
|
||||
},
|
||||
{
|
||||
"EventName": "ex_ret_brn_resync",
|
||||
"EventCode": "0xc7",
|
||||
"BriefDescription": "The number of resync branches. These reflect pipeline restarts due to certain microcode assists and events such as writes to the active instruction stream, among other things. Each occurrence reflects a restart penalty similar to a branch mispredict. This is relatively rare."
|
||||
},
|
||||
{
|
||||
"EventName": "ex_ret_near_ret",
|
||||
"EventCode": "0xc8",
|
||||
"BriefDescription": "The number of near return instructions (RET or RET Iw) retired."
|
||||
},
|
||||
{
|
||||
"EventName": "ex_ret_near_ret_mispred",
|
||||
"EventCode": "0xc9",
|
||||
"BriefDescription": "The number of near returns retired that were not correctly predicted by the return address predictor. Each such mispredict incurs the same penalty as a mispredicted conditional branch instruction."
|
||||
},
|
||||
{
|
||||
"EventName": "ex_ret_brn_ind_misp",
|
||||
"EventCode": "0xca",
|
||||
"BriefDescription": "Retired Indirect Branch Instructions Mispredicted."
|
||||
},
|
||||
{
|
||||
"EventName": "ex_ret_mmx_fp_instr.sse_instr",
|
||||
"EventCode": "0xcb",
|
||||
"BriefDescription": "SSE instructions (SSE, SSE2, SSE3, SSSE3, SSE4A, SSE41, SSE42, AVX).",
|
||||
"PublicDescription": "The number of MMX, SSE or x87 instructions retired. The UnitMask allows the selection of the individual classes of instructions as given in the table. Each increment represents one complete instruction. Since this event includes non-numeric instructions it is not suitable for measuring MFLOPS. SSE instructions (SSE, SSE2, SSE3, SSSE3, SSE4A, SSE41, SSE42, AVX).",
|
||||
"UMask": "0x4"
|
||||
},
|
||||
{
|
||||
"EventName": "ex_ret_mmx_fp_instr.mmx_instr",
|
||||
"EventCode": "0xcb",
|
||||
"BriefDescription": "MMX instructions.",
|
||||
"PublicDescription": "The number of MMX, SSE or x87 instructions retired. The UnitMask allows the selection of the individual classes of instructions as given in the table. Each increment represents one complete instruction. Since this event includes non-numeric instructions it is not suitable for measuring MFLOPS. MMX instructions.",
|
||||
"UMask": "0x2"
|
||||
},
|
||||
{
|
||||
"EventName": "ex_ret_mmx_fp_instr.x87_instr",
|
||||
"EventCode": "0xcb",
|
||||
"BriefDescription": "x87 instructions.",
|
||||
"PublicDescription": "The number of MMX, SSE or x87 instructions retired. The UnitMask allows the selection of the individual classes of instructions as given in the table. Each increment represents one complete instruction. Since this event includes non-numeric instructions it is not suitable for measuring MFLOPS. x87 instructions.",
|
||||
"UMask": "0x1"
|
||||
},
|
||||
{
|
||||
"EventName": "ex_ret_cond",
|
||||
"EventCode": "0xd1",
|
||||
"BriefDescription": "Retired Conditional Branch Instructions."
|
||||
},
|
||||
{
|
||||
"EventName": "ex_ret_cond_misp",
|
||||
"EventCode": "0xd2",
|
||||
"BriefDescription": "Retired Conditional Branch Instructions Mispredicted."
|
||||
},
|
||||
{
|
||||
"EventName": "ex_div_busy",
|
||||
"EventCode": "0xd3",
|
||||
"BriefDescription": "Div Cycles Busy count."
|
||||
},
|
||||
{
|
||||
"EventName": "ex_div_count",
|
||||
"EventCode": "0xd4",
|
||||
"BriefDescription": "Div Op Count."
|
||||
},
|
||||
{
|
||||
"EventName": "ex_tagged_ibs_ops.ibs_count_rollover",
|
||||
"EventCode": "0x1cf",
|
||||
"BriefDescription": "Number of times an op could not be tagged by IBS because of a previous tagged op that has not retired.",
|
||||
"PublicDescription": "Tagged IBS Ops. Number of times an op could not be tagged by IBS because of a previous tagged op that has not retired.",
|
||||
"UMask": "0x4"
|
||||
},
|
||||
{
|
||||
"EventName": "ex_tagged_ibs_ops.ibs_tagged_ops_ret",
|
||||
"EventCode": "0x1cf",
|
||||
"BriefDescription": "Number of Ops tagged by IBS that retired.",
|
||||
"PublicDescription": "Tagged IBS Ops. Number of Ops tagged by IBS that retired.",
|
||||
"UMask": "0x2"
|
||||
},
|
||||
{
|
||||
"EventName": "ex_tagged_ibs_ops.ibs_tagged_ops",
|
||||
"EventCode": "0x1cf",
|
||||
"BriefDescription": "Number of Ops tagged by IBS.",
|
||||
"PublicDescription": "Tagged IBS Ops. Number of Ops tagged by IBS.",
|
||||
"UMask": "0x1"
|
||||
},
|
||||
{
|
||||
"EventName": "ex_ret_fus_brnch_inst",
|
||||
"EventCode": "0x1d0",
|
||||
"BriefDescription": "The number of fused retired branch instructions retired per cycle. The number of events logged per cycle can vary from 0 to 3."
|
||||
}
|
||||
][
|
||||
{
|
||||
"EventName": "ex_ret_instr",
|
||||
"EventCode": "0xc0",
|
||||
"BriefDescription": "Retired Instructions."
|
||||
},
|
||||
{
|
||||
"EventName": "ex_ret_cops",
|
||||
"EventCode": "0xc1",
|
||||
"BriefDescription": "The number of uOps retired. This includes all processor activity (instructions, exceptions, interrupts, microcode assists, etc.). The number of events logged per cycle can vary from 0 to 4."
|
||||
},
|
||||
{
|
||||
"EventName": "ex_ret_brn",
|
||||
"EventCode": "0xc2",
|
||||
"BriefDescription": "The number of branch instructions retired. This includes all types of architectural control flow changes, including exceptions and interrupts."
|
||||
},
|
||||
{
|
||||
"EventName": "ex_ret_brn_misp",
|
||||
"EventCode": "0xc3",
|
||||
"BriefDescription": "The number of branch instructions retired, of any type, that were not correctly predicted. This includes those for which prediction is not attempted (far control transfers, exceptions and interrupts)."
|
||||
},
|
||||
{
|
||||
"EventName": "ex_ret_brn_tkn",
|
||||
"EventCode": "0xc4",
|
||||
"BriefDescription": "The number of taken branches that were retired. This includes all types of architectural control flow changes, including exceptions and interrupts."
|
||||
},
|
||||
{
|
||||
"EventName": "ex_ret_brn_tkn_misp",
|
||||
"EventCode": "0xc5",
|
||||
"BriefDescription": "The number of retired taken branch instructions that were mispredicted."
|
||||
},
|
||||
{
|
||||
"EventName": "ex_ret_brn_far",
|
||||
"EventCode": "0xc6",
|
||||
"BriefDescription": "The number of far control transfers retired including far call/jump/return, IRET, SYSCALL and SYSRET, plus exceptions and interrupts. Far control transfers are not subject to branch prediction."
|
||||
},
|
||||
{
|
||||
"EventName": "ex_ret_brn_resync",
|
||||
"EventCode": "0xc7",
|
||||
"BriefDescription": "The number of resync branches. These reflect pipeline restarts due to certain microcode assists and events such as writes to the active instruction stream, among other things. Each occurrence reflects a restart penalty similar to a branch mispredict. This is relatively rare."
|
||||
},
|
||||
{
|
||||
"EventName": "ex_ret_near_ret",
|
||||
"EventCode": "0xc8",
|
||||
"BriefDescription": "The number of near return instructions (RET or RET Iw) retired."
|
||||
},
|
||||
{
|
||||
"EventName": "ex_ret_near_ret_mispred",
|
||||
"EventCode": "0xc9",
|
||||
"BriefDescription": "The number of near returns retired that were not correctly predicted by the return address predictor. Each such mispredict incurs the same penalty as a mispredicted conditional branch instruction."
|
||||
},
|
||||
{
|
||||
"EventName": "ex_ret_brn_ind_misp",
|
||||
"EventCode": "0xca",
|
||||
"BriefDescription": "Retired Indirect Branch Instructions Mispredicted."
|
||||
},
|
||||
{
|
||||
"EventName": "ex_ret_mmx_fp_instr.sse_instr",
|
||||
"EventCode": "0xcb",
|
||||
"BriefDescription": "SSE instructions (SSE, SSE2, SSE3, SSSE3, SSE4A, SSE41, SSE42, AVX).",
|
||||
"PublicDescription": "The number of MMX, SSE or x87 instructions retired. The UnitMask allows the selection of the individual classes of instructions as given in the table. Each increment represents one complete instruction. Since this event includes non-numeric instructions it is not suitable for measuring MFLOPS. SSE instructions (SSE, SSE2, SSE3, SSSE3, SSE4A, SSE41, SSE42, AVX).",
|
||||
"UMask": "0x4"
|
||||
},
|
||||
{
|
||||
"EventName": "ex_ret_mmx_fp_instr.mmx_instr",
|
||||
"EventCode": "0xcb",
|
||||
"BriefDescription": "MMX instructions.",
|
||||
"PublicDescription": "The number of MMX, SSE or x87 instructions retired. The UnitMask allows the selection of the individual classes of instructions as given in the table. Each increment represents one complete instruction. Since this event includes non-numeric instructions it is not suitable for measuring MFLOPS. MMX instructions.",
|
||||
"UMask": "0x2"
|
||||
},
|
||||
{
|
||||
"EventName": "ex_ret_mmx_fp_instr.x87_instr",
|
||||
"EventCode": "0xcb",
|
||||
"BriefDescription": "x87 instructions.",
|
||||
"PublicDescription": "The number of MMX, SSE or x87 instructions retired. The UnitMask allows the selection of the individual classes of instructions as given in the table. Each increment represents one complete instruction. Since this event includes non-numeric instructions it is not suitable for measuring MFLOPS. x87 instructions.",
|
||||
"UMask": "0x1"
|
||||
},
|
||||
{
|
||||
"EventName": "ex_ret_cond",
|
||||
"EventCode": "0xd1",
|
||||
"BriefDescription": "Retired Conditional Branch Instructions."
|
||||
},
|
||||
{
|
||||
"EventName": "ex_ret_cond_misp",
|
||||
"EventCode": "0xd2",
|
||||
"BriefDescription": "Retired Conditional Branch Instructions Mispredicted."
|
||||
},
|
||||
{
|
||||
"EventName": "ex_div_busy",
|
||||
"EventCode": "0xd3",
|
||||
"BriefDescription": "Div Cycles Busy count."
|
||||
},
|
||||
{
|
||||
"EventName": "ex_div_count",
|
||||
"EventCode": "0xd4",
|
||||
"BriefDescription": "Div Op Count."
|
||||
},
|
||||
{
|
||||
"EventName": "ex_tagged_ibs_ops.ibs_count_rollover",
|
||||
"EventCode": "0x1cf",
|
||||
"BriefDescription": "Number of times an op could not be tagged by IBS because of a previous tagged op that has not retired.",
|
||||
"PublicDescription": "Tagged IBS Ops. Number of times an op could not be tagged by IBS because of a previous tagged op that has not retired.",
|
||||
"UMask": "0x4"
|
||||
},
|
||||
{
|
||||
"EventName": "ex_tagged_ibs_ops.ibs_tagged_ops_ret",
|
||||
"EventCode": "0x1cf",
|
||||
"BriefDescription": "Number of Ops tagged by IBS that retired.",
|
||||
"PublicDescription": "Tagged IBS Ops. Number of Ops tagged by IBS that retired.",
|
||||
"UMask": "0x2"
|
||||
},
|
||||
{
|
||||
"EventName": "ex_tagged_ibs_ops.ibs_tagged_ops",
|
||||
"EventCode": "0x1cf",
|
||||
"BriefDescription": "Number of Ops tagged by IBS.",
|
||||
"PublicDescription": "Tagged IBS Ops. Number of Ops tagged by IBS.",
|
||||
"UMask": "0x1"
|
||||
},
|
||||
{
|
||||
"EventName": "ex_ret_fus_brnch_inst",
|
||||
"EventCode": "0x1d0",
|
||||
"BriefDescription": "The number of fused retired branch instructions retired per cycle. The number of events logged per cycle can vary from 0 to 3."
|
||||
}
|
||||
]
|
||||
1171
lib/libpmc/pmu-events/arch/x86/amdfam17h/floating-point.json
Normal file
1171
lib/libpmc/pmu-events/arch/x86/amdfam17h/floating-point.json
Normal file
File diff suppressed because it is too large
Load diff
1345
lib/libpmc/pmu-events/arch/x86/amdfam17h/memory.json
Normal file
1345
lib/libpmc/pmu-events/arch/x86/amdfam17h/memory.json
Normal file
File diff suppressed because it is too large
Load diff
306
lib/libpmc/pmu-events/arch/x86/amdfam17h/other.json
Normal file
306
lib/libpmc/pmu-events/arch/x86/amdfam17h/other.json
Normal file
|
|
@ -0,0 +1,306 @@
|
|||
[
|
||||
{
|
||||
"EventName": "de_dis_dispatch_token_stalls0.retire_token_stall",
|
||||
"EventCode": "0xaf",
|
||||
"BriefDescription": "RETIRE Tokens unavailable.",
|
||||
"PublicDescription": "Cycles where a dispatch group is valid but does not get dispatched due to a token stall. RETIRE Tokens unavailable.",
|
||||
"UMask": "0x40"
|
||||
},
|
||||
{
|
||||
"EventName": "de_dis_dispatch_token_stalls0.agsq_token_stall",
|
||||
"EventCode": "0xaf",
|
||||
"BriefDescription": "AGSQ Tokens unavailable.",
|
||||
"PublicDescription": "Cycles where a dispatch group is valid but does not get dispatched due to a token stall. AGSQ Tokens unavailable.",
|
||||
"UMask": "0x20"
|
||||
},
|
||||
{
|
||||
"EventName": "de_dis_dispatch_token_stalls0.alu_token_stall",
|
||||
"EventCode": "0xaf",
|
||||
"BriefDescription": "ALU tokens total unavailable.",
|
||||
"PublicDescription": "Cycles where a dispatch group is valid but does not get dispatched due to a token stall. ALU tokens total unavailable.",
|
||||
"UMask": "0x10"
|
||||
},
|
||||
{
|
||||
"EventName": "de_dis_dispatch_token_stalls0.alsq3_0_token_stall",
|
||||
"EventCode": "0xaf",
|
||||
"BriefDescription": "Cycles where a dispatch group is valid but does not get dispatched due to a token stall.",
|
||||
"PublicDescription": "Cycles where a dispatch group is valid but does not get dispatched due to a token stall.",
|
||||
"UMask": "0x8"
|
||||
},
|
||||
{
|
||||
"EventName": "de_dis_dispatch_token_stalls0.alsq3_token_stall",
|
||||
"EventCode": "0xaf",
|
||||
"BriefDescription": "ALSQ 3 Tokens unavailable.",
|
||||
"PublicDescription": "Cycles where a dispatch group is valid but does not get dispatched due to a token stall. ALSQ 3 Tokens unavailable.",
|
||||
"UMask": "0x4"
|
||||
},
|
||||
{
|
||||
"EventName": "de_dis_dispatch_token_stalls0.alsq2_token_stall",
|
||||
"EventCode": "0xaf",
|
||||
"BriefDescription": "ALSQ 2 Tokens unavailable.",
|
||||
"PublicDescription": "Cycles where a dispatch group is valid but does not get dispatched due to a token stall. ALSQ 2 Tokens unavailable.",
|
||||
"UMask": "0x2"
|
||||
},
|
||||
{
|
||||
"EventName": "de_dis_dispatch_token_stalls0.alsq1_token_stall",
|
||||
"EventCode": "0xaf",
|
||||
"BriefDescription": "ALSQ 1 Tokens unavailable.",
|
||||
"PublicDescription": "Cycles where a dispatch group is valid but does not get dispatched due to a token stall. ALSQ 1 Tokens unavailable.",
|
||||
"UMask": "0x1"
|
||||
}
|
||||
]
|
||||
[
|
||||
{
|
||||
"EventName": "de_dis_dispatch_token_stalls0.retire_token_stall",
|
||||
"EventCode": "0xaf",
|
||||
"BriefDescription": "RETIRE Tokens unavailable.",
|
||||
"PublicDescription": "Cycles where a dispatch group is valid but does not get dispatched due to a token stall. RETIRE Tokens unavailable.",
|
||||
"UMask": "0x40"
|
||||
},
|
||||
{
|
||||
"EventName": "de_dis_dispatch_token_stalls0.agsq_token_stall",
|
||||
"EventCode": "0xaf",
|
||||
"BriefDescription": "AGSQ Tokens unavailable.",
|
||||
"PublicDescription": "Cycles where a dispatch group is valid but does not get dispatched due to a token stall. AGSQ Tokens unavailable.",
|
||||
"UMask": "0x20"
|
||||
},
|
||||
{
|
||||
"EventName": "de_dis_dispatch_token_stalls0.alu_token_stall",
|
||||
"EventCode": "0xaf",
|
||||
"BriefDescription": "ALU tokens total unavailable.",
|
||||
"PublicDescription": "Cycles where a dispatch group is valid but does not get dispatched due to a token stall. ALU tokens total unavailable.",
|
||||
"UMask": "0x10"
|
||||
},
|
||||
{
|
||||
"EventName": "de_dis_dispatch_token_stalls0.alsq3_0_token_stall",
|
||||
"EventCode": "0xaf",
|
||||
"BriefDescription": "Cycles where a dispatch group is valid but does not get dispatched due to a token stall.",
|
||||
"PublicDescription": "Cycles where a dispatch group is valid but does not get dispatched due to a token stall.",
|
||||
"UMask": "0x8"
|
||||
},
|
||||
{
|
||||
"EventName": "de_dis_dispatch_token_stalls0.alsq3_token_stall",
|
||||
"EventCode": "0xaf",
|
||||
"BriefDescription": "ALSQ 3 Tokens unavailable.",
|
||||
"PublicDescription": "Cycles where a dispatch group is valid but does not get dispatched due to a token stall. ALSQ 3 Tokens unavailable.",
|
||||
"UMask": "0x4"
|
||||
},
|
||||
{
|
||||
"EventName": "de_dis_dispatch_token_stalls0.alsq2_token_stall",
|
||||
"EventCode": "0xaf",
|
||||
"BriefDescription": "ALSQ 2 Tokens unavailable.",
|
||||
"PublicDescription": "Cycles where a dispatch group is valid but does not get dispatched due to a token stall. ALSQ 2 Tokens unavailable.",
|
||||
"UMask": "0x2"
|
||||
},
|
||||
{
|
||||
"EventName": "de_dis_dispatch_token_stalls0.alsq1_token_stall",
|
||||
"EventCode": "0xaf",
|
||||
"BriefDescription": "ALSQ 1 Tokens unavailable.",
|
||||
"PublicDescription": "Cycles where a dispatch group is valid but does not get dispatched due to a token stall. ALSQ 1 Tokens unavailable.",
|
||||
"UMask": "0x1"
|
||||
}
|
||||
]
|
||||
[
|
||||
{
|
||||
"EventName": "de_dis_dispatch_token_stalls0.retire_token_stall",
|
||||
"EventCode": "0xaf",
|
||||
"BriefDescription": "RETIRE Tokens unavailable.",
|
||||
"PublicDescription": "Cycles where a dispatch group is valid but does not get dispatched due to a token stall. RETIRE Tokens unavailable.",
|
||||
"UMask": "0x40"
|
||||
},
|
||||
{
|
||||
"EventName": "de_dis_dispatch_token_stalls0.agsq_token_stall",
|
||||
"EventCode": "0xaf",
|
||||
"BriefDescription": "AGSQ Tokens unavailable.",
|
||||
"PublicDescription": "Cycles where a dispatch group is valid but does not get dispatched due to a token stall. AGSQ Tokens unavailable.",
|
||||
"UMask": "0x20"
|
||||
},
|
||||
{
|
||||
"EventName": "de_dis_dispatch_token_stalls0.alu_token_stall",
|
||||
"EventCode": "0xaf",
|
||||
"BriefDescription": "ALU tokens total unavailable.",
|
||||
"PublicDescription": "Cycles where a dispatch group is valid but does not get dispatched due to a token stall. ALU tokens total unavailable.",
|
||||
"UMask": "0x10"
|
||||
},
|
||||
{
|
||||
"EventName": "de_dis_dispatch_token_stalls0.alsq3_0_token_stall",
|
||||
"EventCode": "0xaf",
|
||||
"BriefDescription": "Cycles where a dispatch group is valid but does not get dispatched due to a token stall.",
|
||||
"PublicDescription": "Cycles where a dispatch group is valid but does not get dispatched due to a token stall.",
|
||||
"UMask": "0x8"
|
||||
},
|
||||
{
|
||||
"EventName": "de_dis_dispatch_token_stalls0.alsq3_token_stall",
|
||||
"EventCode": "0xaf",
|
||||
"BriefDescription": "ALSQ 3 Tokens unavailable.",
|
||||
"PublicDescription": "Cycles where a dispatch group is valid but does not get dispatched due to a token stall. ALSQ 3 Tokens unavailable.",
|
||||
"UMask": "0x4"
|
||||
},
|
||||
{
|
||||
"EventName": "de_dis_dispatch_token_stalls0.alsq2_token_stall",
|
||||
"EventCode": "0xaf",
|
||||
"BriefDescription": "ALSQ 2 Tokens unavailable.",
|
||||
"PublicDescription": "Cycles where a dispatch group is valid but does not get dispatched due to a token stall. ALSQ 2 Tokens unavailable.",
|
||||
"UMask": "0x2"
|
||||
},
|
||||
{
|
||||
"EventName": "de_dis_dispatch_token_stalls0.alsq1_token_stall",
|
||||
"EventCode": "0xaf",
|
||||
"BriefDescription": "ALSQ 1 Tokens unavailable.",
|
||||
"PublicDescription": "Cycles where a dispatch group is valid but does not get dispatched due to a token stall. ALSQ 1 Tokens unavailable.",
|
||||
"UMask": "0x1"
|
||||
}
|
||||
]
|
||||
[
|
||||
{
|
||||
"EventName": "de_dis_dispatch_token_stalls0.retire_token_stall",
|
||||
"EventCode": "0xaf",
|
||||
"BriefDescription": "RETIRE Tokens unavailable.",
|
||||
"PublicDescription": "Cycles where a dispatch group is valid but does not get dispatched due to a token stall. RETIRE Tokens unavailable.",
|
||||
"UMask": "0x40"
|
||||
},
|
||||
{
|
||||
"EventName": "de_dis_dispatch_token_stalls0.agsq_token_stall",
|
||||
"EventCode": "0xaf",
|
||||
"BriefDescription": "AGSQ Tokens unavailable.",
|
||||
"PublicDescription": "Cycles where a dispatch group is valid but does not get dispatched due to a token stall. AGSQ Tokens unavailable.",
|
||||
"UMask": "0x20"
|
||||
},
|
||||
{
|
||||
"EventName": "de_dis_dispatch_token_stalls0.alu_token_stall",
|
||||
"EventCode": "0xaf",
|
||||
"BriefDescription": "ALU tokens total unavailable.",
|
||||
"PublicDescription": "Cycles where a dispatch group is valid but does not get dispatched due to a token stall. ALU tokens total unavailable.",
|
||||
"UMask": "0x10"
|
||||
},
|
||||
{
|
||||
"EventName": "de_dis_dispatch_token_stalls0.alsq3_0_token_stall",
|
||||
"EventCode": "0xaf",
|
||||
"BriefDescription": "Cycles where a dispatch group is valid but does not get dispatched due to a token stall.",
|
||||
"PublicDescription": "Cycles where a dispatch group is valid but does not get dispatched due to a token stall.",
|
||||
"UMask": "0x8"
|
||||
},
|
||||
{
|
||||
"EventName": "de_dis_dispatch_token_stalls0.alsq3_token_stall",
|
||||
"EventCode": "0xaf",
|
||||
"BriefDescription": "ALSQ 3 Tokens unavailable.",
|
||||
"PublicDescription": "Cycles where a dispatch group is valid but does not get dispatched due to a token stall. ALSQ 3 Tokens unavailable.",
|
||||
"UMask": "0x4"
|
||||
},
|
||||
{
|
||||
"EventName": "de_dis_dispatch_token_stalls0.alsq2_token_stall",
|
||||
"EventCode": "0xaf",
|
||||
"BriefDescription": "ALSQ 2 Tokens unavailable.",
|
||||
"PublicDescription": "Cycles where a dispatch group is valid but does not get dispatched due to a token stall. ALSQ 2 Tokens unavailable.",
|
||||
"UMask": "0x2"
|
||||
},
|
||||
{
|
||||
"EventName": "de_dis_dispatch_token_stalls0.alsq1_token_stall",
|
||||
"EventCode": "0xaf",
|
||||
"BriefDescription": "ALSQ 1 Tokens unavailable.",
|
||||
"PublicDescription": "Cycles where a dispatch group is valid but does not get dispatched due to a token stall. ALSQ 1 Tokens unavailable.",
|
||||
"UMask": "0x1"
|
||||
}
|
||||
]
|
||||
[
|
||||
{
|
||||
"EventName": "de_dis_dispatch_token_stalls0.retire_token_stall",
|
||||
"EventCode": "0xaf",
|
||||
"BriefDescription": "RETIRE Tokens unavailable.",
|
||||
"PublicDescription": "Cycles where a dispatch group is valid but does not get dispatched due to a token stall. RETIRE Tokens unavailable.",
|
||||
"UMask": "0x40"
|
||||
},
|
||||
{
|
||||
"EventName": "de_dis_dispatch_token_stalls0.agsq_token_stall",
|
||||
"EventCode": "0xaf",
|
||||
"BriefDescription": "AGSQ Tokens unavailable.",
|
||||
"PublicDescription": "Cycles where a dispatch group is valid but does not get dispatched due to a token stall. AGSQ Tokens unavailable.",
|
||||
"UMask": "0x20"
|
||||
},
|
||||
{
|
||||
"EventName": "de_dis_dispatch_token_stalls0.alu_token_stall",
|
||||
"EventCode": "0xaf",
|
||||
"BriefDescription": "ALU tokens total unavailable.",
|
||||
"PublicDescription": "Cycles where a dispatch group is valid but does not get dispatched due to a token stall. ALU tokens total unavailable.",
|
||||
"UMask": "0x10"
|
||||
},
|
||||
{
|
||||
"EventName": "de_dis_dispatch_token_stalls0.alsq3_0_token_stall",
|
||||
"EventCode": "0xaf",
|
||||
"BriefDescription": "Cycles where a dispatch group is valid but does not get dispatched due to a token stall.",
|
||||
"PublicDescription": "Cycles where a dispatch group is valid but does not get dispatched due to a token stall.",
|
||||
"UMask": "0x8"
|
||||
},
|
||||
{
|
||||
"EventName": "de_dis_dispatch_token_stalls0.alsq3_token_stall",
|
||||
"EventCode": "0xaf",
|
||||
"BriefDescription": "ALSQ 3 Tokens unavailable.",
|
||||
"PublicDescription": "Cycles where a dispatch group is valid but does not get dispatched due to a token stall. ALSQ 3 Tokens unavailable.",
|
||||
"UMask": "0x4"
|
||||
},
|
||||
{
|
||||
"EventName": "de_dis_dispatch_token_stalls0.alsq2_token_stall",
|
||||
"EventCode": "0xaf",
|
||||
"BriefDescription": "ALSQ 2 Tokens unavailable.",
|
||||
"PublicDescription": "Cycles where a dispatch group is valid but does not get dispatched due to a token stall. ALSQ 2 Tokens unavailable.",
|
||||
"UMask": "0x2"
|
||||
},
|
||||
{
|
||||
"EventName": "de_dis_dispatch_token_stalls0.alsq1_token_stall",
|
||||
"EventCode": "0xaf",
|
||||
"BriefDescription": "ALSQ 1 Tokens unavailable.",
|
||||
"PublicDescription": "Cycles where a dispatch group is valid but does not get dispatched due to a token stall. ALSQ 1 Tokens unavailable.",
|
||||
"UMask": "0x1"
|
||||
}
|
||||
]
|
||||
[
|
||||
{
|
||||
"EventName": "de_dis_dispatch_token_stalls0.retire_token_stall",
|
||||
"EventCode": "0xaf",
|
||||
"BriefDescription": "RETIRE Tokens unavailable.",
|
||||
"PublicDescription": "Cycles where a dispatch group is valid but does not get dispatched due to a token stall. RETIRE Tokens unavailable.",
|
||||
"UMask": "0x40"
|
||||
},
|
||||
{
|
||||
"EventName": "de_dis_dispatch_token_stalls0.agsq_token_stall",
|
||||
"EventCode": "0xaf",
|
||||
"BriefDescription": "AGSQ Tokens unavailable.",
|
||||
"PublicDescription": "Cycles where a dispatch group is valid but does not get dispatched due to a token stall. AGSQ Tokens unavailable.",
|
||||
"UMask": "0x20"
|
||||
},
|
||||
{
|
||||
"EventName": "de_dis_dispatch_token_stalls0.alu_token_stall",
|
||||
"EventCode": "0xaf",
|
||||
"BriefDescription": "ALU tokens total unavailable.",
|
||||
"PublicDescription": "Cycles where a dispatch group is valid but does not get dispatched due to a token stall. ALU tokens total unavailable.",
|
||||
"UMask": "0x10"
|
||||
},
|
||||
{
|
||||
"EventName": "de_dis_dispatch_token_stalls0.alsq3_0_token_stall",
|
||||
"EventCode": "0xaf",
|
||||
"BriefDescription": "Cycles where a dispatch group is valid but does not get dispatched due to a token stall.",
|
||||
"PublicDescription": "Cycles where a dispatch group is valid but does not get dispatched due to a token stall.",
|
||||
"UMask": "0x8"
|
||||
},
|
||||
{
|
||||
"EventName": "de_dis_dispatch_token_stalls0.alsq3_token_stall",
|
||||
"EventCode": "0xaf",
|
||||
"BriefDescription": "ALSQ 3 Tokens unavailable.",
|
||||
"PublicDescription": "Cycles where a dispatch group is valid but does not get dispatched due to a token stall. ALSQ 3 Tokens unavailable.",
|
||||
"UMask": "0x4"
|
||||
},
|
||||
{
|
||||
"EventName": "de_dis_dispatch_token_stalls0.alsq2_token_stall",
|
||||
"EventCode": "0xaf",
|
||||
"BriefDescription": "ALSQ 2 Tokens unavailable.",
|
||||
"PublicDescription": "Cycles where a dispatch group is valid but does not get dispatched due to a token stall. ALSQ 2 Tokens unavailable.",
|
||||
"UMask": "0x2"
|
||||
},
|
||||
{
|
||||
"EventName": "de_dis_dispatch_token_stalls0.alsq1_token_stall",
|
||||
"EventCode": "0xaf",
|
||||
"BriefDescription": "ALSQ 1 Tokens unavailable.",
|
||||
"PublicDescription": "Cycles where a dispatch group is valid but does not get dispatched due to a token stall. ALSQ 1 Tokens unavailable.",
|
||||
"UMask": "0x1"
|
||||
}
|
||||
]
|
||||
|
|
@ -36,3 +36,4 @@ GenuineIntel-6-2C,v2,westmereep-dp,core
|
|||
GenuineIntel-6-25,v2,westmereep-sp,core
|
||||
GenuineIntel-6-2F,v2,westmereex,core
|
||||
GenuineIntel-6-55,v1,skylakex,core
|
||||
AuthenticAMD-23-[[:xdigit:]]+,v1,amdfam17h,core
|
||||
|
Loading…
Reference in a new issue