diff --git a/sys/mips/atheros/ar933x_chip.c b/sys/mips/atheros/ar933x_chip.c new file mode 100644 index 00000000000..c997d8e44b5 --- /dev/null +++ b/sys/mips/atheros/ar933x_chip.c @@ -0,0 +1,268 @@ +/*- + * Copyright (c) 2012 Adrian Chadd + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +#include +__FBSDID("$FreeBSD$"); + +#include "opt_ddb.h" + +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include + +#include + +#include +#include +#include +#include +#include +#include +#include + +#include +#include + +#include +#include + +#include +#include + +static void +ar933x_chip_detect_mem_size(void) +{ +} + +static void +ar933x_chip_detect_sys_frequency(void) +{ + uint32_t clock_ctrl; + uint32_t cpu_config; + uint32_t freq; + uint32_t t; + + t = ATH_READ_REG(AR933X_RESET_REG_BOOTSTRAP); + if (t & AR933X_BOOTSTRAP_REF_CLK_40) + u_ar71xx_refclk = (40 * 1000 * 1000); + else + u_ar71xx_refclk = (25 * 1000 * 1000); + + clock_ctrl = ATH_READ_REG(AR933X_PLL_CLOCK_CTRL_REG); + if (clock_ctrl & AR933X_PLL_CLOCK_CTRL_BYPASS) { + u_ar71xx_cpu_freq = u_ar71xx_refclk; + u_ar71xx_ahb_freq = u_ar71xx_refclk; + u_ar71xx_ddr_freq = u_ar71xx_refclk; + } else { + cpu_config = ATH_READ_REG(AR933X_PLL_CPU_CONFIG_REG); + + t = (cpu_config >> AR933X_PLL_CPU_CONFIG_REFDIV_SHIFT) & + AR933X_PLL_CPU_CONFIG_REFDIV_MASK; + freq = u_ar71xx_refclk / t; + + t = (cpu_config >> AR933X_PLL_CPU_CONFIG_NINT_SHIFT) & + AR933X_PLL_CPU_CONFIG_NINT_MASK; + freq *= t; + + t = (cpu_config >> AR933X_PLL_CPU_CONFIG_OUTDIV_SHIFT) & + AR933X_PLL_CPU_CONFIG_OUTDIV_MASK; + if (t == 0) + t = 1; + + freq >>= t; + + t = ((clock_ctrl >> AR933X_PLL_CLOCK_CTRL_CPU_DIV_SHIFT) & + AR933X_PLL_CLOCK_CTRL_CPU_DIV_MASK) + 1; + u_ar71xx_cpu_freq = freq / t; + + t = ((clock_ctrl >> AR933X_PLL_CLOCK_CTRL_DDR_DIV_SHIFT) & + AR933X_PLL_CLOCK_CTRL_DDR_DIV_MASK) + 1; + u_ar71xx_ddr_freq = freq / t; + + t = ((clock_ctrl >> AR933X_PLL_CLOCK_CTRL_AHB_DIV_SHIFT) & + AR933X_PLL_CLOCK_CTRL_AHB_DIV_MASK) + 1; + u_ar71xx_ahb_freq = freq / t; + } +} + +static void +ar933x_chip_device_stop(uint32_t mask) +{ + uint32_t mask_inv, reg; + + mask_inv = mask; + reg = ATH_READ_REG(AR933X_RESET_REG_RESET_MODULE); + reg |= mask; + reg &= ~mask_inv; + ATH_WRITE_REG(AR933X_RESET_REG_RESET_MODULE, reg); +} + +static void +ar933x_chip_device_start(uint32_t mask) +{ + uint32_t mask_inv, reg; + + mask_inv = mask; + reg = ATH_READ_REG(AR933X_RESET_REG_RESET_MODULE); + reg &= ~mask; + reg |= mask_inv; + ATH_WRITE_REG(AR933X_RESET_REG_RESET_MODULE, reg); +} + +static int +ar933x_chip_device_stopped(uint32_t mask) +{ + uint32_t reg; + + reg = ATH_READ_REG(AR933X_RESET_REG_RESET_MODULE); + return ((reg & mask) == mask); +} + +static void +ar933x_chip_set_mii_speed(uint32_t unit, uint32_t speed) +{ + + /* XXX TODO */ + return; +} + +/* + * XXX TODO !! + */ +static void +ar933x_chip_set_pll_ge(int unit, int speed, uint32_t pll) +{ + + switch (unit) { + case 0: + /* XXX TODO */ + break; + case 1: + /* XXX TODO */ + break; + default: + printf("%s: invalid PLL set for arge unit: %d\n", + __func__, unit); + return; + } +} + +static void +ar933x_chip_ddr_flush_ge(int unit) +{ + + switch (unit) { + case 0: + ar71xx_ddr_flush(AR933X_DDR_REG_FLUSH_GE0); + break; + case 1: + ar71xx_ddr_flush(AR933X_DDR_REG_FLUSH_GE1); + break; + default: + printf("%s: invalid DDR flush for arge unit: %d\n", + __func__, unit); + return; + } +} + +static void +ar933x_chip_ddr_flush_ip2(void) +{ + + ar71xx_ddr_flush(AR933X_DDR_REG_FLUSH_WMAC); +} + +static uint32_t +ar933x_chip_get_eth_pll(unsigned int mac, int speed) +{ + + return (0); +} + +static void +ar933x_chip_init_usb_peripheral(void) +{ +#if 0 + switch (ar71xx_soc) { + case AR71XX_SOC_AR7240: + ar71xx_device_stop(AR724X_RESET_MODULE_USB_OHCI_DLL | + AR724X_RESET_USB_HOST); + DELAY(1000); + + ar71xx_device_start(AR724X_RESET_MODULE_USB_OHCI_DLL | + AR724X_RESET_USB_HOST); + DELAY(1000); + + /* + * WAR for HW bug. Here it adjusts the duration + * between two SOFS. + */ + ATH_WRITE_REG(AR71XX_USB_CTRL_FLADJ, + (3 << USB_CTRL_FLADJ_A0_SHIFT)); + + break; + + case AR71XX_SOC_AR7241: + case AR71XX_SOC_AR7242: + ar71xx_device_start(AR724X_RESET_MODULE_USB_OHCI_DLL); + DELAY(100); + + ar71xx_device_start(AR724X_RESET_USB_HOST); + DELAY(100); + + ar71xx_device_start(AR724X_RESET_USB_PHY); + DELAY(100); + + break; + + default: + break; + } +#endif +} + +struct ar71xx_cpu_def ar933x_chip_def = { + &ar933x_chip_detect_mem_size, + &ar933x_chip_detect_sys_frequency, + &ar933x_chip_device_stop, + &ar933x_chip_device_start, + &ar933x_chip_device_stopped, + &ar933x_chip_set_pll_ge, + &ar933x_chip_set_mii_speed, + &ar71xx_chip_set_mii_if, + &ar933x_chip_ddr_flush_ge, + &ar933x_chip_get_eth_pll, + &ar933x_chip_ddr_flush_ip2, + &ar933x_chip_init_usb_peripheral +}; diff --git a/sys/mips/atheros/ar933x_chip.h b/sys/mips/atheros/ar933x_chip.h new file mode 100644 index 00000000000..925b781750c --- /dev/null +++ b/sys/mips/atheros/ar933x_chip.h @@ -0,0 +1,34 @@ +/*- + * Copyright (c) 2012 Adrian Chadd + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +/* $FreeBSD$ */ + +#ifndef __AR933X_CHIP_H__ +#define __AR933X_CHIP_H__ + +extern struct ar71xx_cpu_def ar933x_chip_def; + +#endif diff --git a/sys/mips/atheros/ar933x_uart.h b/sys/mips/atheros/ar933x_uart.h new file mode 100644 index 00000000000..992b152e055 --- /dev/null +++ b/sys/mips/atheros/ar933x_uart.h @@ -0,0 +1,88 @@ +/*- + * Copyright (c) 2012 Adrian Chadd + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * $FreeBSD$ + */ + +/* + * Atheros AR933x SoC UART registers + */ +#ifndef __AR933X_UART_H__ +#define __AR933X_UART_H__ + +#define AR933X_UART_REGS_SIZE 20 +#define AR933X_UART_FIFO_SIZE 16 + +#define AR933X_UART_DATA_REG 0x00 +#define AR933X_UART_CS_REG 0x04 +#define AR933X_UART_CLOCK_REG 0x08 +#define AR933X_UART_INT_REG 0x0c +#define AR933X_UART_INT_EN_REG 0x10 + +#define AR933X_UART_DATA_TX_RX_MASK 0xff +#define AR933X_UART_DATA_RX_CSR (1 << 8) +#define AR933X_UART_DATA_TX_CSR (1 << 9) + +#define AR933X_UART_CS_PARITY_S 0 +#define AR933X_UART_CS_PARITY_M 0x3 +#define AR933X_UART_CS_PARITY_NONE 0 +#define AR933X_UART_CS_PARITY_ODD 1 +#define AR933X_UART_CS_PARITY_EVEN 2 +#define AR933X_UART_CS_IF_MODE_S 2 +#define AR933X_UART_CS_IF_MODE_M 0x3 +#define AR933X_UART_CS_IF_MODE_NONE 0 +#define AR933X_UART_CS_IF_MODE_DTE 1 +#define AR933X_UART_CS_IF_MODE_DCE 2 +#define AR933X_UART_CS_FLOW_CTRL_S 4 +#define AR933X_UART_CS_FLOW_CTRL_M 0x3 +#define AR933X_UART_CS_DMA_EN (1 << 6) +#define AR933X_UART_CS_TX_READY_ORIDE (1 << 7) +#define AR933X_UART_CS_RX_READY_ORIDE (1 << 8) +#define AR933X_UART_CS_TX_READY (1 << 9) +#define AR933X_UART_CS_RX_BREAK (1 << 10) +#define AR933X_UART_CS_TX_BREAK (1 << 11) +#define AR933X_UART_CS_HOST_INT (1 << 12) +#define AR933X_UART_CS_HOST_INT_EN (1 << 13) +#define AR933X_UART_CS_TX_BUSY (1 << 14) +#define AR933X_UART_CS_RX_BUSY (1 << 15) + +#define AR933X_UART_CLOCK_STEP_M 0xffff +#define AR933X_UART_CLOCK_SCALE_M 0xfff +#define AR933X_UART_CLOCK_SCALE_S 16 +#define AR933X_UART_CLOCK_STEP_M 0xffff + +#define AR933X_UART_INT_RX_VALID (1 << 0) +#define AR933X_UART_INT_TX_READY (1 << 1) +#define AR933X_UART_INT_RX_FRAMING_ERR (1 << 2) +#define AR933X_UART_INT_RX_OFLOW_ERR (1 << 3) +#define AR933X_UART_INT_TX_OFLOW_ERR (1 << 4) +#define AR933X_UART_INT_RX_PARITY_ERR (1 << 5) +#define AR933X_UART_INT_RX_BREAK_ON (1 << 6) +#define AR933X_UART_INT_RX_BREAK_OFF (1 << 7) +#define AR933X_UART_INT_RX_FULL (1 << 8) +#define AR933X_UART_INT_TX_EMPTY (1 << 9) +#define AR933X_UART_INT_ALLINTS 0x3ff + +#endif /* __AR933X_UART_H__ */ diff --git a/sys/mips/atheros/ar933xreg.h b/sys/mips/atheros/ar933xreg.h new file mode 100644 index 00000000000..7a6ef836e9d --- /dev/null +++ b/sys/mips/atheros/ar933xreg.h @@ -0,0 +1,78 @@ +/*- + * Copyright (c) 2012 Adrian Chadd + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * $FreeBSD$ + */ + +#ifndef __AR93XX_REG_H__ +#define __AR93XX_REG_H__ + +#define REV_ID_MAJOR_AR9330 0x0110 +#define REV_ID_MAJOR_AR9331 0x1110 + +#define AR933X_REV_ID_REVISION_MASK 0x3 + +#define AR933X_GPIO_COUNT 30 + +#define AR933X_UART_BASE (AR71XX_APB_BASE + 0x00020000) +#define AR933X_UART_SIZE 0x14 +#define AR933X_WMAC_BASE (AR71XX_APB_BASE + 0x00100000) +#define AR933X_WMAC_SIZE 0x20000 +#define AR933X_EHCI_BASE 0x1b000000 +#define AR933X_EHCI_SIZE 0x1000 + +#define AR933X_DDR_REG_FLUSH_GE0 (AR71XX_APB_BASE + 0x7c) +#define AR933X_DDR_REG_FLUSH_GE1 (AR71XX_APB_BASE + 0x80) +#define AR933X_DDR_REG_FLUSH_USB (AR71XX_APB_BASE + 0x84) +#define AR933X_DDR_REG_FLUSH_WMAC (AR71XX_APB_BASE + 0x88) + +#define AR933X_PLL_CPU_CONFIG_REG (AR71XX_PLL_CPU_BASE + 0x00) +#define AR933X_PLL_CLOCK_CTRL_REG (AR71XX_PLL_CPU_BASE + 0x08) + +#define AR933X_PLL_CPU_CONFIG_NINT_SHIFT 10 +#define AR933X_PLL_CPU_CONFIG_NINT_MASK 0x3f +#define AR933X_PLL_CPU_CONFIG_REFDIV_SHIFT 16 +#define AR933X_PLL_CPU_CONFIG_REFDIV_MASK 0x1f +#define AR933X_PLL_CPU_CONFIG_OUTDIV_SHIFT 23 +#define AR933X_PLL_CPU_CONFIG_OUTDIV_MASK 0x7 + +#define AR933X_PLL_CLOCK_CTRL_BYPASS (1 << 2) +#define AR933X_PLL_CLOCK_CTRL_CPU_DIV_SHIFT 5 +#define AR933X_PLL_CLOCK_CTRL_CPU_DIV_MASK 0x3 +#define AR933X_PLL_CLOCK_CTRL_DDR_DIV_SHIFT 10 +#define AR933X_PLL_CLOCK_CTRL_DDR_DIV_MASK 0x3 +#define AR933X_PLL_CLOCK_CTRL_AHB_DIV_SHIFT 15 +#define AR933X_PLL_CLOCK_CTRL_AHB_DIV_MASK 0x7 + +#define AR933X_RESET_REG_RESET_MODULE (AR71XX_RST_BLOCK_BASE + 0x1c) +#define AR933X_RESET_REG_BOOTSTRAP (AR71XX_RST_BLOCK_BASE + 0xac) +#define AR933X_RESET_WMAC (1 << 11) +#define AR933X_RESET_USB_HOST (1 << 5) +#define AR933X_RESET_USB_PHY (1 << 4) +#define AR933X_RESET_USBSUS_OVERRIDE (1 << 3) + +#define AR933X_BOOTSTRAP_REF_CLK_40 (1 << 0) + +#endif /* __AR93XX_REG_H__ */