diff --git a/sys/arm64/rockchip/clk/rk3399_cru.c b/sys/arm64/rockchip/clk/rk3399_cru.c
index aa5558290ea..dbc1d0aa911 100644
--- a/sys/arm64/rockchip/clk/rk3399_cru.c
+++ b/sys/arm64/rockchip/clk/rk3399_cru.c
@@ -764,6 +764,7 @@ static struct rk_clk_pll_def lpll = {
 	.gate_shift = 0,
 	.flags = RK_CLK_PLL_HAVE_GATE,
 	.rates = rk3399_pll_rates,
+	.normal_mode = true,
 };
 
 static struct rk_clk_pll_def bpll = {
@@ -778,6 +779,7 @@ static struct rk_clk_pll_def bpll = {
 	.gate_shift = 1,
 	.flags = RK_CLK_PLL_HAVE_GATE,
 	.rates = rk3399_pll_rates,
+	.normal_mode = true,
 };
 
 static struct rk_clk_pll_def dpll = {
diff --git a/sys/arm64/rockchip/clk/rk_clk_pll.c b/sys/arm64/rockchip/clk/rk_clk_pll.c
index 3c5e2669428..a7c92123b35 100644
--- a/sys/arm64/rockchip/clk/rk_clk_pll.c
+++ b/sys/arm64/rockchip/clk/rk_clk_pll.c
@@ -54,6 +54,8 @@ struct rk_clk_pll_sc {
 
 	struct rk_clk_pll_rate	*rates;
 	struct rk_clk_pll_rate	*frac_rates;
+
+	bool			normal_mode;
 };
 
 #define	WRITE4(_clk, off, val)					\
@@ -344,11 +346,13 @@ rk3399_clk_pll_init(struct clknode *clk, device_t dev)
 
 	sc = clknode_get_softc(clk);
 
-	/* Setting to normal mode */
-	reg = RK3399_CLK_PLL_MODE_NORMAL << RK3399_CLK_PLL_MODE_SHIFT;
-	reg |= RK3399_CLK_PLL_MODE_MASK << RK_CLK_PLL_MASK_SHIFT;
-	WRITE4(clk, sc->base_offset + RK3399_CLK_PLL_MODE_OFFSET,
-	    reg | RK3399_CLK_PLL_WRITE_MASK);
+	if (sc->normal_mode) {
+		/* Setting to normal mode */
+		reg = RK3399_CLK_PLL_MODE_NORMAL << RK3399_CLK_PLL_MODE_SHIFT;
+		reg |= RK3399_CLK_PLL_MODE_MASK << RK_CLK_PLL_MASK_SHIFT;
+		WRITE4(clk, sc->base_offset + RK3399_CLK_PLL_MODE_OFFSET,
+		    reg | RK3399_CLK_PLL_WRITE_MASK);
+	}
 
 	clknode_init_parent_idx(clk, 0);
 
@@ -521,6 +525,7 @@ rk3399_clk_pll_register(struct clkdom *clkdom, struct rk_clk_pll_def *clkdef)
 	sc->flags = clkdef->flags;
 	sc->rates = clkdef->rates;
 	sc->frac_rates = clkdef->frac_rates;
+	sc->normal_mode = clkdef->normal_mode;
 
 	clknode_register(clkdom, clk);
 
diff --git a/sys/arm64/rockchip/clk/rk_clk_pll.h b/sys/arm64/rockchip/clk/rk_clk_pll.h
index 400601c219b..c0b60cf0c18 100644
--- a/sys/arm64/rockchip/clk/rk_clk_pll.h
+++ b/sys/arm64/rockchip/clk/rk_clk_pll.h
@@ -57,6 +57,8 @@ struct rk_clk_pll_def {
 
 	struct rk_clk_pll_rate	*rates;
 	struct rk_clk_pll_rate	*frac_rates;
+
+	bool			normal_mode;
 };
 
 #define	RK_CLK_PLL_HAVE_GATE	0x1