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https://github.com/opnsense/src.git
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rtwn(4): add IQ calibration support for RTL8188E*
Tested with: * RTL8188EE, STA mode. * RTL8188EU, STA mode. MFC after: 4 days
This commit is contained in:
Andriy Voskoboinyk
parent
db70ff37a0
commit
58d3c148fd
2 changed files with 330 additions and 2 deletions
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@ -1,5 +1,5 @@
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/*-
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* Copyright (c) 2016 Andriy Voskoboinyk <avos@FreeBSD.org>
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* Copyright (c) 2016-2019 Andriy Voskoboinyk <avos@FreeBSD.org>
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*
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* Permission to use, copy, modify, and distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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@ -42,16 +42,343 @@ __FBSDID("$FreeBSD$");
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#include <dev/rtwn/if_rtwnreg.h>
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#include <dev/rtwn/if_rtwnvar.h>
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#include <dev/rtwn/if_rtwn_debug.h>
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#include <dev/rtwn/rtl8188e/r88e.h>
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#include <dev/rtwn/rtl8188e/r88e_reg.h>
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/* Registers to save and restore during IQ calibration. */
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struct r88e_iq_cal_reg_vals {
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uint32_t adda[16];
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uint8_t txpause;
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uint8_t bcn_ctrl[2];
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uint32_t gpio_muxcfg;
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uint32_t cck0_afesetting;
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uint32_t ofdm0_trxpathena;
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uint32_t ofdm0_trmuxpar;
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uint32_t fpga0_rfifacesw0;
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uint32_t fpga0_rfifacesw1;
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uint32_t fpga0_rfifaceoe0;
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uint32_t fpga0_rfifaceoe1;
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uint32_t config_ant0;
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uint32_t config_ant1;
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};
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static int
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r88e_iq_calib_chain(struct rtwn_softc *sc, uint16_t tx[2], uint16_t rx[2])
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{
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uint32_t status;
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/* Set Rx IQ calibration mode table. */
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rtwn_bb_write(sc, R92C_FPGA0_IQK, 0);
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rtwn_rf_write(sc, 0, R88E_RF_WE_LUT, 0x800a0);
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rtwn_rf_write(sc, 0, R92C_RF_RCK_OS, 0x30000);
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rtwn_rf_write(sc, 0, R92C_RF_TXPA_G(0), 0xf);
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rtwn_rf_write(sc, 0, R92C_RF_TXPA_G(1), 0xf117b);
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rtwn_bb_write(sc, R92C_FPGA0_IQK, 0x80800000);
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/* IQ calibration settings. */
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rtwn_bb_write(sc, R92C_TX_IQK, 0x01007c00);
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rtwn_bb_write(sc, R92C_RX_IQK, 0x81004800);
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/* IQ calibration settings for chain 0. */
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rtwn_bb_write(sc, R92C_TX_IQK_TONE(0), 0x10008c1c);
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rtwn_bb_write(sc, R92C_RX_IQK_TONE(0), 0x30008c1c);
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rtwn_bb_write(sc, R92C_TX_IQK_PI(0), 0x82160804);
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rtwn_bb_write(sc, R92C_RX_IQK_PI(0), 0x28160000);
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/* LO calibration settings. */
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rtwn_bb_write(sc, R92C_IQK_AGC_RSP, 0x0046a911);
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/* We're doing LO and IQ calibration in one shot. */
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rtwn_bb_write(sc, R92C_IQK_AGC_PTS, 0xf9000000);
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rtwn_bb_write(sc, R92C_IQK_AGC_PTS, 0xf8000000);
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/* Give LO and IQ calibrations the time to complete. */
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rtwn_delay(sc, 10000);
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/* Read IQ calibration status. */
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status = rtwn_bb_read(sc, R92C_RX_POWER_IQK_AFTER(0));
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if (status & (1 << 28))
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return (0); /* Tx failed. */
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/* Read Tx IQ calibration results. */
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tx[0] = MS(rtwn_bb_read(sc, R92C_TX_POWER_IQK_BEFORE(0)),
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R92C_POWER_IQK_RESULT);
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tx[1] = MS(rtwn_bb_read(sc, R92C_TX_POWER_IQK_AFTER(0)),
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R92C_POWER_IQK_RESULT);
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if (tx[0] == 0x142 || tx[1] == 0x042)
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return (0); /* Tx failed. */
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rtwn_bb_write(sc, R92C_TX_IQK, 0x80007c00 | (tx[0] << 16) | tx[1]);
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/* Set Rx IQ calibration mode table. */
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rtwn_bb_write(sc, R92C_FPGA0_IQK, 0);
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rtwn_rf_write(sc, 0, R88E_RF_WE_LUT, 0x800a0);
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rtwn_rf_write(sc, 0, R92C_RF_RCK_OS, 0x30000);
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rtwn_rf_write(sc, 0, R92C_RF_TXPA_G(0), 0xf);
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rtwn_rf_write(sc, 0, R92C_RF_TXPA_G(1), 0xf7ffa);
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rtwn_bb_write(sc, R92C_FPGA0_IQK, 0x80800000);
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/* IQ calibration settings. */
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rtwn_bb_write(sc, R92C_RX_IQK, 0x01004800);
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/* IQ calibration settings for chain 0. */
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rtwn_bb_write(sc, R92C_TX_IQK_TONE(0), 0x30008c1c);
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rtwn_bb_write(sc, R92C_RX_IQK_TONE(0), 0x10008c1c);
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rtwn_bb_write(sc, R92C_TX_IQK_PI(0), 0x82160c05);
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rtwn_bb_write(sc, R92C_RX_IQK_PI(0), 0x28160c05);
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/* LO calibration settings. */
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rtwn_bb_write(sc, R92C_IQK_AGC_RSP, 0x0046a911);
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/* We're doing LO and IQ calibration in one shot. */
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rtwn_bb_write(sc, R92C_IQK_AGC_PTS, 0xf9000000);
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rtwn_bb_write(sc, R92C_IQK_AGC_PTS, 0xf8000000);
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/* Give LO and IQ calibrations the time to complete. */
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rtwn_delay(sc, 10000);
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/* Read IQ calibration status. */
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status = rtwn_bb_read(sc, R92C_RX_POWER_IQK_AFTER(0));
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if (status & (1 << 27))
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return (1); /* Rx failed. */
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/* Read Rx IQ calibration results. */
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rx[0] = MS(rtwn_bb_read(sc, R92C_RX_POWER_IQK_BEFORE(0)),
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R92C_POWER_IQK_RESULT);
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rx[1] = MS(status, R92C_POWER_IQK_RESULT);
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if (rx[0] == 0x132 || rx[1] == 0x036)
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return (1); /* Rx failed. */
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return (3); /* Both Tx and Rx succeeded. */
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}
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static void
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r88e_iq_calib_run(struct rtwn_softc *sc, int n, uint16_t tx[2],
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uint16_t rx[2], struct r88e_iq_cal_reg_vals *vals)
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{
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/* Registers to save and restore during IQ calibration. */
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static const uint16_t reg_adda[16] = {
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0x85c, 0xe6c, 0xe70, 0xe74,
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0xe78, 0xe7c, 0xe80, 0xe84,
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0xe88, 0xe8c, 0xed0, 0xed4,
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0xed8, 0xedc, 0xee0, 0xeec
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};
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int i;
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uint32_t hssi_param1;
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if (n == 0) {
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for (i = 0; i < nitems(reg_adda); i++)
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vals->adda[i] = rtwn_bb_read(sc, reg_adda[i]);
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vals->txpause = rtwn_read_1(sc, R92C_TXPAUSE);
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vals->bcn_ctrl[0] = rtwn_read_1(sc, R92C_BCN_CTRL(0));
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vals->bcn_ctrl[1] = rtwn_read_1(sc, R92C_BCN_CTRL(1));
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vals->gpio_muxcfg = rtwn_read_4(sc, R92C_GPIO_MUXCFG);
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}
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rtwn_bb_write(sc, reg_adda[0], 0x0b1b25a0);
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for (i = 1; i < nitems(reg_adda); i++)
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rtwn_bb_write(sc, reg_adda[i], 0x0bdb25a0);
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hssi_param1 = rtwn_bb_read(sc, R92C_HSSI_PARAM1(0));
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if (!(hssi_param1 & R92C_HSSI_PARAM1_PI)) {
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rtwn_bb_write(sc, R92C_HSSI_PARAM1(0),
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hssi_param1 | R92C_HSSI_PARAM1_PI);
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rtwn_bb_write(sc, R92C_HSSI_PARAM1(1),
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hssi_param1 | R92C_HSSI_PARAM1_PI);
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}
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if (n == 0) {
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vals->cck0_afesetting = rtwn_bb_read(sc, R92C_CCK0_AFESETTING);
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vals->ofdm0_trxpathena =
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rtwn_bb_read(sc, R92C_OFDM0_TRXPATHENA);
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vals->ofdm0_trmuxpar = rtwn_bb_read(sc, R92C_OFDM0_TRMUXPAR);
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vals->fpga0_rfifacesw0 =
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rtwn_bb_read(sc, R92C_FPGA0_RFIFACESW(0));
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vals->fpga0_rfifacesw1 =
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rtwn_bb_read(sc, R92C_FPGA0_RFIFACESW(1));
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vals->fpga0_rfifaceoe0 =
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rtwn_bb_read(sc, R92C_FPGA0_RFIFACEOE(0));
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vals->fpga0_rfifaceoe1 =
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rtwn_bb_read(sc, R92C_FPGA0_RFIFACEOE(1));
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vals->config_ant0 = rtwn_bb_read(sc, R92C_CONFIG_ANT(0));
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vals->config_ant1 = rtwn_bb_read(sc, R92C_CONFIG_ANT(1));
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}
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rtwn_bb_setbits(sc, R92C_CCK0_AFESETTING, 0, 0x0f000000);
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rtwn_bb_write(sc, R92C_OFDM0_TRXPATHENA, 0x03a05600);
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rtwn_bb_write(sc, R92C_OFDM0_TRMUXPAR, 0x000800e4);
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rtwn_bb_write(sc, R92C_FPGA0_RFIFACESW(1), 0x22204000);
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rtwn_bb_setbits(sc, R92C_FPGA0_RFIFACESW(0), 0, 0x04000400);
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rtwn_bb_setbits(sc, R92C_FPGA0_RFIFACEOE(0), 0x400, 0);
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rtwn_bb_setbits(sc, R92C_FPGA0_RFIFACEOE(1), 0x400, 0);
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rtwn_write_1(sc, R92C_TXPAUSE,
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R92C_TX_QUEUE_AC | R92C_TX_QUEUE_MGT | R92C_TX_QUEUE_HIGH);
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rtwn_write_1(sc, R92C_BCN_CTRL(0),
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vals->bcn_ctrl[0] & ~R92C_BCN_CTRL_EN_BCN);
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rtwn_write_1(sc, R92C_BCN_CTRL(1),
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vals->bcn_ctrl[1] & ~R92C_BCN_CTRL_EN_BCN);
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rtwn_write_1(sc, R92C_GPIO_MUXCFG,
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vals->gpio_muxcfg & ~R92C_GPIO_MUXCFG_ENBT);
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rtwn_bb_write(sc, R92C_CONFIG_ANT(0), 0x0f600000);
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rtwn_bb_write(sc, R92C_FPGA0_IQK, 0x80800000);
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rtwn_bb_write(sc, R92C_TX_IQK, 0x01007c00);
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rtwn_bb_write(sc, R92C_RX_IQK, 0x01004800);
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/* Run IQ calibration twice. */
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for (i = 0; i < 2; i++) {
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int ret;
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ret = r88e_iq_calib_chain(sc, tx, rx);
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if (ret == 0) {
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RTWN_DPRINTF(sc, RTWN_DEBUG_CALIB, "%s: Tx failed.\n",
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__func__);
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tx[0] = 0xff;
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tx[1] = 0xff;
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rx[0] = 0xff;
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rx[1] = 0xff;
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} else if (ret == 1) {
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RTWN_DPRINTF(sc, RTWN_DEBUG_CALIB, "%s: Rx failed.\n",
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__func__);
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rx[0] = 0xff;
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rx[1] = 0xff;
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} else if (ret == 3) {
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RTWN_DPRINTF(sc, RTWN_DEBUG_CALIB, "%s: Both Tx and Rx"
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" succeeded.\n", __func__);
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}
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}
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RTWN_DPRINTF(sc, RTWN_DEBUG_CALIB,
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"%s: results for run %d: tx[0] 0x%x, tx[1] 0x%x, rx[0] 0x%x, "
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"rx[1] 0x%x\n", __func__, n, tx[0], tx[1], rx[0], rx[1]);
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rtwn_bb_write(sc, R92C_CCK0_AFESETTING, vals->cck0_afesetting);
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rtwn_bb_write(sc, R92C_OFDM0_TRXPATHENA, vals->ofdm0_trxpathena);
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rtwn_bb_write(sc, R92C_FPGA0_RFIFACESW(0), vals->fpga0_rfifacesw0);
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rtwn_bb_write(sc, R92C_FPGA0_RFIFACESW(1), vals->fpga0_rfifacesw1);
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rtwn_bb_write(sc, R92C_OFDM0_TRMUXPAR, vals->ofdm0_trmuxpar);
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rtwn_bb_write(sc, R92C_FPGA0_RFIFACEOE(0), vals->fpga0_rfifaceoe0);
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rtwn_bb_write(sc, R92C_FPGA0_RFIFACEOE(1), vals->fpga0_rfifaceoe1);
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rtwn_bb_write(sc, R92C_CONFIG_ANT(0), vals->config_ant0);
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rtwn_bb_write(sc, R92C_CONFIG_ANT(1), vals->config_ant1);
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rtwn_bb_write(sc, R92C_FPGA0_IQK, 0);
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rtwn_bb_write(sc, R92C_LSSI_PARAM(0), 0x00032ed3);
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if (n != 0) {
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if (!(hssi_param1 & R92C_HSSI_PARAM1_PI)) {
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rtwn_bb_write(sc, R92C_HSSI_PARAM1(0), hssi_param1);
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rtwn_bb_write(sc, R92C_HSSI_PARAM1(1), hssi_param1);
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}
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for (i = 0; i < nitems(reg_adda); i++)
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rtwn_bb_write(sc, reg_adda[i], vals->adda[i]);
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rtwn_write_1(sc, R92C_TXPAUSE, vals->txpause);
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rtwn_write_1(sc, R92C_BCN_CTRL(0), vals->bcn_ctrl[0]);
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rtwn_write_1(sc, R92C_BCN_CTRL(1), vals->bcn_ctrl[1]);
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rtwn_write_4(sc, R92C_GPIO_MUXCFG, vals->gpio_muxcfg);
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}
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}
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#define RTWN_IQ_CAL_MAX_TOLERANCE 5
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static int
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r88e_iq_calib_compare_results(struct rtwn_softc *sc, uint16_t tx1[2],
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uint16_t rx1[2], uint16_t tx2[2], uint16_t rx2[2])
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{
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int i, tx_ok, rx_ok;
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tx_ok = rx_ok = 0;
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for (i = 0; i < 2; i++) {
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if (tx1[i] == 0xff || tx2[i] == 0xff ||
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rx1[i] == 0xff || rx2[i] == 0xff)
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continue;
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tx_ok = (abs(tx1[i] - tx2[i]) <= RTWN_IQ_CAL_MAX_TOLERANCE);
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rx_ok = (abs(rx1[i] - rx2[i]) <= RTWN_IQ_CAL_MAX_TOLERANCE);
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}
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return (tx_ok && rx_ok);
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}
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#undef RTWN_IQ_CAL_MAX_TOLERANCE
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static void
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r88e_iq_calib_write_results(struct rtwn_softc *sc, uint16_t tx[2],
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uint16_t rx[2])
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{
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uint32_t reg, val, x;
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long y, tx_c;
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if (tx[0] == 0xff || tx[1] == 0xff)
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return;
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reg = rtwn_bb_read(sc, R92C_OFDM0_TXIQIMBALANCE(0));
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val = ((reg >> 22) & 0x3ff);
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x = tx[0];
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if (x & 0x00000200)
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x |= 0xfffffc00;
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reg = (((x * val) >> 8) & 0x3ff);
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rtwn_bb_setbits(sc, R92C_OFDM0_TXIQIMBALANCE(0), 0x3ff, reg);
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rtwn_bb_setbits(sc, R92C_OFDM0_ECCATHRESHOLD, 0x80000000,
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((x * val) & 0x80) << 24);
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y = tx[1];
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if (y & 0x00000200)
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y |= 0xfffffc00;
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tx_c = (y * val) >> 8;
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rtwn_bb_setbits(sc, R92C_OFDM0_TXAFE(0), 0xf0000000,
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(tx_c & 0x3c0) << 22);
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rtwn_bb_setbits(sc, R92C_OFDM0_TXIQIMBALANCE(0), 0x003f0000,
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(tx_c & 0x3f) << 16);
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rtwn_bb_setbits(sc, R92C_OFDM0_ECCATHRESHOLD, 0x20000000,
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((y * val) & 0x80) << 22);
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if (rx[0] == 0xff || rx[1] == 0xff)
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return;
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rtwn_bb_setbits(sc, R92C_OFDM0_RXIQIMBALANCE(0), 0x3ff,
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rx[0] & 0x3ff);
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rtwn_bb_setbits(sc, R92C_OFDM0_RXIQIMBALANCE(0), 0xfc00,
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(rx[1] & 0x3f) << 10);
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rtwn_bb_setbits(sc, R92C_OFDM0_RXIQEXTANTA, 0xf0000000,
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(rx[1] & 0x3c0) << 22);
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}
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#define RTWN_IQ_CAL_NRUN 3
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void
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r88e_iq_calib(struct rtwn_softc *sc)
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{
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/* XXX TODO */
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struct r88e_iq_cal_reg_vals vals;
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uint16_t tx[RTWN_IQ_CAL_NRUN][2], rx[RTWN_IQ_CAL_NRUN][2];
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int n, valid;
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KASSERT(sc->ntxchains == 1,
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("%s: only 1T1R configuration is supported!\n", __func__));
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valid = 0;
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for (n = 0; n < RTWN_IQ_CAL_NRUN; n++) {
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r88e_iq_calib_run(sc, n, tx[n], rx[n], &vals);
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if (n == 0)
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continue;
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/* Valid results remain stable after consecutive runs. */
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valid = r88e_iq_calib_compare_results(sc, tx[n - 1],
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rx[n - 1], tx[n], rx[n]);
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if (valid)
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break;
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}
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if (valid)
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r88e_iq_calib_write_results(sc, tx[n], rx[n]);
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}
|
||||
#undef RTWN_IQ_CAL_NRUN
|
||||
|
||||
void
|
||||
r88e_temp_measure(struct rtwn_softc *sc)
|
||||
|
|
|
|||
|
|
@ -79,6 +79,7 @@
|
|||
* RF (6052) registers.
|
||||
*/
|
||||
#define R88E_RF_T_METER 0x42
|
||||
#define R88E_RF_WE_LUT 0xef
|
||||
|
||||
/* Bits for R92C_RF_CHNLBW. */
|
||||
#define R88E_RF_CHNLBW_BW20 0x00c00
|
||||
|
|
|
|||
Loading…
Reference in a new issue