diff --git a/sys/mips/cavium/octe/ethernet-defines.h b/sys/mips/cavium/octe/ethernet-defines.h
index 52260dc7645..21929777be4 100644
--- a/sys/mips/cavium/octe/ethernet-defines.h
+++ b/sys/mips/cavium/octe/ethernet-defines.h
@@ -79,8 +79,6 @@ AND WITH ALL FAULTS AND CAVIUM  NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR W
 #define USE_MULTICORE_RECEIVE 0
 #endif
 
-#define IP_PROTOCOL_TCP             6
-#define IP_PROTOCOL_UDP             0x11
 #define FAU_NUM_PACKET_BUFFERS_TO_FREE (CVMX_FAU_REG_END - sizeof(uint32_t))
 #define TOTAL_NUMBER_OF_PORTS       (CVMX_PIP_NUM_INPUT_PORTS+1)
 
diff --git a/sys/mips/cavium/octe/ethernet.c b/sys/mips/cavium/octe/ethernet.c
index 2717d2c2d4f..24ff9795a35 100644
--- a/sys/mips/cavium/octe/ethernet.c
+++ b/sys/mips/cavium/octe/ethernet.c
@@ -235,15 +235,16 @@ static void cvm_oct_configure_common_hw(device_t bus)
 	if (USE_MULTICORE_RECEIVE) {
 		critical_enter();
 		{
-			int cpu;
-			for (cpu = 0; cpu < mp_maxid; cpu++) {
-				if (!CPU_ABSENT(cpu) &&
-				   (cpu != PCPU_GET(cpuid))) {
-					cvmx_ciu_intx0_t en;
-					en.u64 = cvmx_read_csr(CVMX_CIU_INTX_EN0(cpu*2));
-					en.s.workq |= (1<<pow_receive_group);
-					cvmx_write_csr(CVMX_CIU_INTX_EN0(cpu*2), en.u64);
-				}
+			cvmx_ciu_intx0_t en;
+			int core;
+
+			CPU_FOREACH(core) {
+				if (core == PCPU_GET(cpuid))
+					continue;
+
+				en.u64 = cvmx_read_csr(CVMX_CIU_INTX_EN0(core*2));
+				en.s.workq |= (1<<pow_receive_group);
+				cvmx_write_csr(CVMX_CIU_INTX_EN0(core*2), en.u64);
 			}
 		}
 		critical_exit();