mirror of
https://github.com/opnsense/src.git
synced 2026-06-08 16:22:46 -04:00
Import support for ATI Radeon R600 and R700 series chips.
Tested on an HD3850 (RV670) on loan from Warren Block. Currently, you need one of the following for this to be useful: x11-drivers/xf86-video-radeonhd-devel (not tested) xf86-video-ati from git (EXA works, xv is too fast) xf86-video-radeonhd from git (EXA works, xv works) There is no 3d support available from dri just yet. MFC after: 2 weeks
This commit is contained in:
Robert Noland
parent
663963b1d2
commit
4fcda8938e
10 changed files with 26950 additions and 383 deletions
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@ -801,6 +801,7 @@ dev/drm/r128_irq.c optional r128drm
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dev/drm/r128_state.c optional r128drm \
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compile-with "${NORMAL_C} -finline-limit=13500"
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dev/drm/r300_cmdbuf.c optional radeondrm
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dev/drm/r600_cp.c optional radeondrm
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dev/drm/radeon_cp.c optional radeondrm
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dev/drm/radeon_drv.c optional radeondrm
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dev/drm/radeon_irq.c optional radeondrm
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@ -240,12 +240,123 @@
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{0x1002, 0x7297, CHIP_RV560|RADEON_NEW_MEMMAP, "ATI RV560"}, \
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{0x1002, 0x7834, CHIP_RS300|RADEON_IS_IGP|RADEON_NEW_MEMMAP, "ATI Radeon RS350 9000/9100 IGP"}, \
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{0x1002, 0x7835, CHIP_RS300|RADEON_IS_IGP|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP, "ATI Radeon RS350 Mobility IGP"}, \
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{0x1002, 0x793f, CHIP_RS600|RADEON_IS_IGP|RADEON_NEW_MEMMAP, "ATI Radeon X1200"}, \
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{0x1002, 0x7941, CHIP_RS600|RADEON_IS_IGP|RADEON_NEW_MEMMAP, "ATI Radeon X1200"}, \
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{0x1002, 0x7942, CHIP_RS600|RADEON_IS_IGP|RADEON_NEW_MEMMAP, "ATI Radeon X1200"}, \
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{0x1002, 0x791e, CHIP_RS690|RADEON_IS_IGP|RADEON_NEW_MEMMAP|RADEON_IS_IGPGART, "ATI Radeon RS690 X1250 IGP"}, \
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{0x1002, 0x791f, CHIP_RS690|RADEON_IS_IGP|RADEON_NEW_MEMMAP|RADEON_IS_IGPGART, "ATI Radeon RS690 X1270 IGP"}, \
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{0x1002, 0x796c, CHIP_RS740|RADEON_IS_IGP|RADEON_NEW_MEMMAP|RADEON_IS_IGPGART, "ATI Radeon RS740 HD2100 IGP"}, \
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{0x1002, 0x796d, CHIP_RS740|RADEON_IS_IGP|RADEON_NEW_MEMMAP|RADEON_IS_IGPGART, "ATI Radeon RS740 HD2100 IGP"}, \
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{0x1002, 0x796e, CHIP_RS740|RADEON_IS_IGP|RADEON_NEW_MEMMAP|RADEON_IS_IGPGART, "ATI Radeon RS740 HD2100 IGP"}, \
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{0x1002, 0x796f, CHIP_RS740|RADEON_IS_IGP|RADEON_NEW_MEMMAP|RADEON_IS_IGPGART, "ATI Radeon RS740 HD2100 IGP"}, \
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{0x1002, 0x9400, CHIP_R600|RADEON_NEW_MEMMAP, "ATI Radeon HD 2900 XT"}, \
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{0x1002, 0x9401, CHIP_R600|RADEON_NEW_MEMMAP, "ATI Radeon HD 2900 XT"}, \
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{0x1002, 0x9402, CHIP_R600|RADEON_NEW_MEMMAP, "ATI Radeon HD 2900 XT"}, \
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{0x1002, 0x9403, CHIP_R600|RADEON_NEW_MEMMAP, "ATI Radeon HD 2900 Pro"}, \
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{0x1002, 0x9405, CHIP_R600|RADEON_NEW_MEMMAP, "ATI Radeon HD 2900 GT"}, \
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{0x1002, 0x940A, CHIP_R600|RADEON_NEW_MEMMAP, "ATI FireGL V8650"}, \
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{0x1002, 0x940B, CHIP_R600|RADEON_NEW_MEMMAP, "ATI FireGL V8600"}, \
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{0x1002, 0x940F, CHIP_R600|RADEON_NEW_MEMMAP, "ATI FireGL V7600"}, \
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{0x1002, 0x94C0, CHIP_RV610|RADEON_NEW_MEMMAP, "RV610"}, \
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{0x1002, 0x94C1, CHIP_RV610|RADEON_NEW_MEMMAP, "Radeon HD 2400 XT"}, \
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{0x1002, 0x94C3, CHIP_RV610|RADEON_NEW_MEMMAP, "Radeon HD 2400 Pro"}, \
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{0x1002, 0x94C4, CHIP_RV610|RADEON_NEW_MEMMAP, "Radeon HD 2400 PRO AGP"}, \
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{0x1002, 0x94C5, CHIP_RV610|RADEON_NEW_MEMMAP, "FireGL V4000"}, \
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{0x1002, 0x94C6, CHIP_RV610|RADEON_NEW_MEMMAP, "RV610"}, \
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{0x1002, 0x94C7, CHIP_RV610|RADEON_NEW_MEMMAP, "ATI Radeon HD 2350"}, \
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{0x1002, 0x94C8, CHIP_RV610|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP, "ATI Mobility Radeon HD 2400 XT"}, \
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{0x1002, 0x94C9, CHIP_RV610|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP, "ATI Mobility Radeon HD 2400"}, \
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{0x1002, 0x94CB, CHIP_RV610|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP, "ATI RADEON E2400"}, \
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{0x1002, 0x94CC, CHIP_RV610|RADEON_NEW_MEMMAP, "ATI RV610"}, \
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{0x1002, 0x94CD, CHIP_RV610|RADEON_NEW_MEMMAP, "ATI FireMV 2260"}, \
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{0x1002, 0x9500, CHIP_RV670|RADEON_NEW_MEMMAP, "ATI RV670"}, \
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{0x1002, 0x9501, CHIP_RV670|RADEON_NEW_MEMMAP, "ATI Radeon HD3870"}, \
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{0x1002, 0x9504, CHIP_RV670|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP, "ATI Mobility Radeon HD 3850"}, \
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{0x1002, 0x9505, CHIP_RV670|RADEON_NEW_MEMMAP, "ATI Radeon HD3850"}, \
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{0x1002, 0x9506, CHIP_RV670|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP, "ATI Mobility Radeon HD 3850 X2"}, \
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{0x1002, 0x9507, CHIP_RV670|RADEON_NEW_MEMMAP, "ATI RV670"}, \
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{0x1002, 0x9508, CHIP_RV670|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP, "ATI Mobility Radeon HD 3870"}, \
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{0x1002, 0x9509, CHIP_RV670|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP, "ATI Mobility Radeon HD 3870 X2"}, \
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{0x1002, 0x950F, CHIP_RV670|RADEON_NEW_MEMMAP, "ATI Radeon HD3870 X2"}, \
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{0x1002, 0x9511, CHIP_RV670|RADEON_NEW_MEMMAP, "ATI FireGL V7700"}, \
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{0x1002, 0x9515, CHIP_RV670|RADEON_NEW_MEMMAP, "ATI Radeon HD3850"}, \
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{0x1002, 0x9517, CHIP_RV670|RADEON_NEW_MEMMAP, "ATI Radeon HD3690"}, \
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{0x1002, 0x9519, CHIP_RV670|RADEON_NEW_MEMMAP, "AMD Firestream 9170"}, \
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{0x1002, 0x9580, CHIP_RV630|RADEON_NEW_MEMMAP, "ATI RV630"}, \
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{0x1002, 0x9581, CHIP_RV630|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP, "ATI Mobility Radeon HD 2600"}, \
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{0x1002, 0x9583, CHIP_RV630|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP, "ATI Mobility Radeon HD 2600 XT"}, \
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{0x1002, 0x9586, CHIP_RV630|RADEON_NEW_MEMMAP, "ATI Radeon HD 2600 XT AGP"}, \
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{0x1002, 0x9587, CHIP_RV630|RADEON_NEW_MEMMAP, "ATI Radeon HD 2600 Pro AGP"}, \
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{0x1002, 0x9588, CHIP_RV630|RADEON_NEW_MEMMAP, "ATI Radeon HD 2600 XT"}, \
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{0x1002, 0x9589, CHIP_RV630|RADEON_NEW_MEMMAP, "ATI Radeon HD 2600 Pro"}, \
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{0x1002, 0x958A, CHIP_RV630|RADEON_NEW_MEMMAP, "ATI Gemini RV630"}, \
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{0x1002, 0x958B, CHIP_RV630|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP, "ATI Gemini Mobility Radeon HD 2600 XT"}, \
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{0x1002, 0x958C, CHIP_RV630|RADEON_NEW_MEMMAP, "ATI FireGL V5600"}, \
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{0x1002, 0x958D, CHIP_RV630|RADEON_NEW_MEMMAP, "ATI FireGL V3600"}, \
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{0x1002, 0x958E, CHIP_RV630|RADEON_NEW_MEMMAP, "ATI Radeon HD 2600 LE"}, \
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{0x1002, 0x958F, CHIP_RV630|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP, "ATI Mobility FireGL Graphics Processor"}, \
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{0x1002, 0x95C0, CHIP_RV620|RADEON_NEW_MEMMAP, "ATI Radeon HD 3470"}, \
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{0x1002, 0x95C5, CHIP_RV620|RADEON_NEW_MEMMAP, "ATI Radeon HD 3450"}, \
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{0x1002, 0x95C6, CHIP_RV620|RADEON_NEW_MEMMAP, "ATI Radeon HD 3450"}, \
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{0x1002, 0x95C7, CHIP_RV620|RADEON_NEW_MEMMAP, "ATI Radeon HD 3430"}, \
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{0x1002, 0x95C9, CHIP_RV620|RADEON_NEW_MEMMAP, "ATI Radeon HD 3450"}, \
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{0x1002, 0x95C2, CHIP_RV620|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP, "ATI Mobility Radeon HD 3430"}, \
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{0x1002, 0x95C4, CHIP_RV620|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP, "ATI Mobility Radeon HD 3400 Series"}, \
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{0x1002, 0x95CC, CHIP_RV620|RADEON_NEW_MEMMAP, "ATI FirePro V3700"}, \
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{0x1002, 0x95CD, CHIP_RV620|RADEON_NEW_MEMMAP, "ATI FireMV 2450"}, \
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{0x1002, 0x95CE, CHIP_RV620|RADEON_NEW_MEMMAP, "ATI FireMV 2260"}, \
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{0x1002, 0x95CF, CHIP_RV620|RADEON_NEW_MEMMAP, "ATI FireMV 2260"}, \
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{0x1002, 0x9590, CHIP_RV635|RADEON_NEW_MEMMAP, "ATI ATI Radeon HD 3600 Series"}, \
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{0x1002, 0x9596, CHIP_RV635|RADEON_NEW_MEMMAP, "ATI ATI Radeon HD 3650 AGP"}, \
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{0x1002, 0x9597, CHIP_RV635|RADEON_NEW_MEMMAP, "ATI ATI Radeon HD 3600 PRO"}, \
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{0x1002, 0x9598, CHIP_RV635|RADEON_NEW_MEMMAP, "ATI ATI Radeon HD 3600 XT"}, \
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{0x1002, 0x9599, CHIP_RV635|RADEON_NEW_MEMMAP, "ATI ATI Radeon HD 3600 PRO"}, \
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{0x1002, 0x9591, CHIP_RV635|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP, "ATI Mobility Radeon HD 3650"}, \
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{0x1002, 0x9593, CHIP_RV635|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP, "ATI Mobility Radeon HD 3670"}, \
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{0x1002, 0x9595, CHIP_RV635|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP, "ATI Mobility FireGL V5700"}, \
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{0x1002, 0x959B, CHIP_RV635|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP, "ATI Mobility FireGL V5725"}, \
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{0x1002, 0x9610, CHIP_RS780|RADEON_NEW_MEMMAP|RADEON_IS_IGP, "ATI Radeon HD 3200 Graphics"}, \
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{0x1002, 0x9611, CHIP_RS780|RADEON_NEW_MEMMAP|RADEON_IS_IGP, "ATI Radeon 3100 Graphics"}, \
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{0x1002, 0x9612, CHIP_RS780|RADEON_NEW_MEMMAP|RADEON_IS_IGP, "ATI Radeon HD 3200 Graphics"}, \
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{0x1002, 0x9613, CHIP_RS780|RADEON_NEW_MEMMAP|RADEON_IS_IGP, "ATI Radeon 3100 Graphics"}, \
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{0x1002, 0x9614, CHIP_RS780|RADEON_NEW_MEMMAP|RADEON_IS_IGP, "ATI Radeon 3300 Graphics"}, \
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{0x1002, 0x9440, CHIP_RV770|RADEON_NEW_MEMMAP, "ATI Radeon 4800 Series"}, \
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{0x1002, 0x9441, CHIP_RV770|RADEON_NEW_MEMMAP, "ATI Radeon 4870 X2"}, \
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{0x1002, 0x9442, CHIP_RV770|RADEON_NEW_MEMMAP, "ATI Radeon 4800 Series"}, \
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{0x1002, 0x944C, CHIP_RV770|RADEON_NEW_MEMMAP, "ATI Radeon 4800 Series"}, \
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{0x1002, 0x9450, CHIP_RV770|RADEON_NEW_MEMMAP, "AMD FireStream 9270"}, \
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{0x1002, 0x9452, CHIP_RV770|RADEON_NEW_MEMMAP, "AMD FireStream 9250"}, \
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{0x1002, 0x9444, CHIP_RV770|RADEON_NEW_MEMMAP, "ATI FirePro V8750 (FireGL)"}, \
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{0x1002, 0x9446, CHIP_RV770|RADEON_NEW_MEMMAP, "ATI FirePro V7760 (FireGL)"}, \
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{0x1002, 0x9456, CHIP_RV770|RADEON_NEW_MEMMAP, "ATI FirePro V8700 (FireGL)"}, \
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{0x1002, 0x944E, CHIP_RV770|RADEON_NEW_MEMMAP, "ATI FirePro RV770"}, \
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{0x1002, 0x944A, CHIP_RV770|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP, "ATI Mobility Radeon HD 4850"}, \
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{0x1002, 0x944B, CHIP_RV770|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP, "ATI Mobility Radeon HD 4850 X2"}, \
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{0x1002, 0x945A, CHIP_RV770|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP, "ATI Mobility Radeon HD 4870"}, \
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{0x1002, 0x945B, CHIP_RV770|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP, "ATI Mobility Radeon M98"}, \
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{0x1002, 0x946A, CHIP_RV770|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP, "ATI FirePro M7750"}, \
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{0x1002, 0x946B, CHIP_RV770|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP, "ATI M98"}, \
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{0x1002, 0x947A, CHIP_RV770|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP, "ATI M98"}, \
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{0x1002, 0x947B, CHIP_RV770|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP, "ATI M98"}, \
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{0x1002, 0x9487, CHIP_RV730|RADEON_NEW_MEMMAP, "ATI Radeon RV730 (AGP)"}, \
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{0x1002, 0x948F, CHIP_RV730|RADEON_NEW_MEMMAP, "ATI Radeon RV730 (AGP)"}, \
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{0x1002, 0x9490, CHIP_RV730|RADEON_NEW_MEMMAP, "ATI Radeon HD 4670"}, \
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{0x1002, 0x9498, CHIP_RV730|RADEON_NEW_MEMMAP, "ATI Radeon HD 4650"}, \
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{0x1002, 0x9480, CHIP_RV730|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP, "ATI Mobility Radeon HD 4650"}, \
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{0x1002, 0x9488, CHIP_RV730|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP, "ATI Mobility Radeon HD 4670"}, \
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{0x1002, 0x9489, CHIP_RV730|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP, "ATI FirePro M5750"}, \
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{0x1002, 0x9491, CHIP_RV730|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP, "ATI RADEON E4600"}, \
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{0x1002, 0x949C, CHIP_RV730|RADEON_NEW_MEMMAP, "ATI FirePro V7750 (FireGL)"}, \
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{0x1002, 0x949E, CHIP_RV730|RADEON_NEW_MEMMAP, "ATI FirePro V5700 (FireGL)"}, \
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{0x1002, 0x949F, CHIP_RV730|RADEON_NEW_MEMMAP, "ATI FirePro V3750 (FireGL)"}, \
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{0x1002, 0x9540, CHIP_RV710|RADEON_NEW_MEMMAP, "ATI Radeon HD 4550"}, \
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{0x1002, 0x9541, CHIP_RV710|RADEON_NEW_MEMMAP, "ATI Radeon RV710"}, \
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{0x1002, 0x9542, CHIP_RV710|RADEON_NEW_MEMMAP, "ATI Radeon RV710"}, \
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{0x1002, 0x954E, CHIP_RV710|RADEON_NEW_MEMMAP, "ATI Radeon RV710"}, \
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{0x1002, 0x954F, CHIP_RV710|RADEON_NEW_MEMMAP, "ATI Radeon HD 4350"}, \
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{0x1002, 0x9552, CHIP_RV710|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP, "ATI Mobility Radeon 4300 Series"}, \
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{0x1002, 0x9553, CHIP_RV710|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP, "ATI Mobility Radeon 4500 Series"}, \
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{0x1002, 0x9555, CHIP_RV710|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP, "ATI Mobility Radeon 4500 Series"}, \
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{0, 0, 0, NULL}
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#define r128_PCI_IDS \
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2258
sys/dev/drm/r600_cp.c
Normal file
2258
sys/dev/drm/r600_cp.c
Normal file
File diff suppressed because it is too large
Load diff
23295
sys/dev/drm/r600_microcode.h
Normal file
23295
sys/dev/drm/r600_microcode.h
Normal file
File diff suppressed because it is too large
Load diff
File diff suppressed because it is too large
Load diff
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@ -306,6 +306,7 @@ typedef union {
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#define RADEON_INDEX_PRIM_OFFSET 20
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#define RADEON_SCRATCH_REG_OFFSET 32
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#define R600_SCRATCH_REG_OFFSET 256
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#define RADEON_NR_SAREA_CLIPRECTS 12
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@ -529,7 +530,8 @@ typedef struct drm_radeon_init {
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RADEON_INIT_CP = 0x01,
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RADEON_CLEANUP_CP = 0x02,
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RADEON_INIT_R200_CP = 0x03,
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RADEON_INIT_R300_CP = 0x04
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RADEON_INIT_R300_CP = 0x04,
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RADEON_INIT_R600_CP = 0x05,
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} func;
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unsigned long sarea_priv_offset;
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int is_pci; /* for overriding only */
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@ -655,6 +657,9 @@ typedef struct drm_radeon_indirect {
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int discard;
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} drm_radeon_indirect_t;
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#define RADEON_INDIRECT_DISCARD (1 << 0)
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#define RADEON_INDIRECT_NOFLUSH (1 << 1)
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/* enum for card type parameters */
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#define RADEON_CARD_PCI 0
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#define RADEON_CARD_AGP 1
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File diff suppressed because it is too large
Load diff
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@ -68,7 +68,7 @@ int radeon_enable_vblank(struct drm_device *dev, int crtc)
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{
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drm_radeon_private_t *dev_priv = dev->dev_private;
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if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RS690) {
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if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RS600) {
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switch (crtc) {
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case 0:
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r500_vbl_irq_set_state(dev, R500_D1MODE_INT_MASK, 1);
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@ -103,7 +103,7 @@ void radeon_disable_vblank(struct drm_device *dev, int crtc)
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{
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drm_radeon_private_t *dev_priv = dev->dev_private;
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if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RS690) {
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if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RS600) {
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switch (crtc) {
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case 0:
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r500_vbl_irq_set_state(dev, R500_D1MODE_INT_MASK, 0);
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@ -138,7 +138,7 @@ static __inline__ u32 radeon_acknowledge_irqs(drm_radeon_private_t * dev_priv, u
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u32 irq_mask = RADEON_SW_INT_TEST;
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*r500_disp_int = 0;
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if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RS690) {
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if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RS600) {
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/* vbl interrupts in a different place */
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if (irqs & R500_DISPLAY_INT_STATUS) {
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@ -208,7 +208,7 @@ irqreturn_t radeon_driver_irq_handler(DRM_IRQ_ARGS)
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DRM_WAKEUP(&dev_priv->swi_queue);
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/* VBLANK interrupt */
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if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RS690) {
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if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RS600) {
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if (r500_disp_int & R500_D1_VBLANK_INTERRUPT)
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drm_handle_vblank(dev, 0);
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if (r500_disp_int & R500_D2_VBLANK_INTERRUPT)
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@ -298,7 +298,7 @@ u32 radeon_get_vblank_counter(struct drm_device *dev, int crtc)
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return -EINVAL;
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}
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|
||||
if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RS690) {
|
||||
if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RS600) {
|
||||
if (crtc == 0)
|
||||
return RADEON_READ(R500_D1CRTC_FRAME_COUNT);
|
||||
else
|
||||
|
|
@ -360,7 +360,7 @@ void radeon_driver_irq_preinstall(struct drm_device * dev)
|
|||
u32 dummy;
|
||||
|
||||
/* Disable *all* interrupts */
|
||||
if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RS690)
|
||||
if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RS600)
|
||||
RADEON_WRITE(R500_DxMODE_INT_MASK, 0);
|
||||
RADEON_WRITE(RADEON_GEN_INT_CNTL, 0);
|
||||
|
||||
|
|
@ -392,7 +392,7 @@ void radeon_driver_irq_uninstall(struct drm_device * dev)
|
|||
|
||||
dev_priv->irq_enabled = 0;
|
||||
|
||||
if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RS690)
|
||||
if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RS600)
|
||||
RADEON_WRITE(R500_DxMODE_INT_MASK, 0);
|
||||
/* Disable *all* interrupts */
|
||||
RADEON_WRITE(RADEON_GEN_INT_CNTL, 0);
|
||||
|
|
|
|||
|
|
@ -1,4 +1,3 @@
|
|||
/* radeon_state.c -- State support for Radeon -*- linux-c -*- */
|
||||
/*-
|
||||
* Copyright 2000 VA Linux Systems, Inc., Fremont, California.
|
||||
* All Rights Reserved.
|
||||
|
|
@ -43,7 +42,7 @@ __FBSDID("$FreeBSD$");
|
|||
static __inline__ int radeon_check_and_fixup_offset(drm_radeon_private_t *
|
||||
dev_priv,
|
||||
struct drm_file *file_priv,
|
||||
u32 * offset)
|
||||
u32 *offset)
|
||||
{
|
||||
u64 off = *offset;
|
||||
u32 fb_end = dev_priv->fb_location + dev_priv->fb_size - 1;
|
||||
|
|
@ -308,9 +307,8 @@ static __inline__ int radeon_check_and_fixup_packet3(drm_radeon_private_t *
|
|||
case RADEON_CP_3D_DRAW_INDX_2:
|
||||
case RADEON_3D_CLEAR_HIZ:
|
||||
/* safe but r200 only */
|
||||
if ((dev_priv->chip_family < CHIP_R200) ||
|
||||
(dev_priv->chip_family > CHIP_RV280)) {
|
||||
DRM_ERROR("Invalid 3d packet for non r200-class chip\n");
|
||||
if (dev_priv->microcode_version != UCODE_R200) {
|
||||
DRM_ERROR("Invalid 3d packet for r100-class chip\n");
|
||||
return -EINVAL;
|
||||
}
|
||||
break;
|
||||
|
|
@ -363,8 +361,8 @@ static __inline__ int radeon_check_and_fixup_packet3(drm_radeon_private_t *
|
|||
break;
|
||||
|
||||
case RADEON_3D_RNDR_GEN_INDX_PRIM:
|
||||
if (dev_priv->chip_family > CHIP_RS200) {
|
||||
DRM_ERROR("Invalid 3d packet for non-r100-class chip\n");
|
||||
if (dev_priv->microcode_version != UCODE_R100) {
|
||||
DRM_ERROR("Invalid 3d packet for r200-class chip\n");
|
||||
return -EINVAL;
|
||||
}
|
||||
if (radeon_check_and_fixup_offset(dev_priv, file_priv, &cmd[1])) {
|
||||
|
|
@ -374,10 +372,8 @@ static __inline__ int radeon_check_and_fixup_packet3(drm_radeon_private_t *
|
|||
break;
|
||||
|
||||
case RADEON_CP_INDX_BUFFER:
|
||||
/* safe but r200 only */
|
||||
if ((dev_priv->chip_family < CHIP_R200) ||
|
||||
(dev_priv->chip_family > CHIP_RV280)) {
|
||||
DRM_ERROR("Invalid 3d packet for non-r200-class chip\n");
|
||||
if (dev_priv->microcode_version != UCODE_R200) {
|
||||
DRM_ERROR("Invalid 3d packet for r100-class chip\n");
|
||||
return -EINVAL;
|
||||
}
|
||||
if ((cmd[1] & 0x8000ffff) != 0x80000810) {
|
||||
|
|
@ -796,7 +792,7 @@ static void radeon_clear_box(drm_radeon_private_t * dev_priv,
|
|||
ADVANCE_RING();
|
||||
}
|
||||
|
||||
static void radeon_cp_performance_boxes(drm_radeon_private_t * dev_priv)
|
||||
static void radeon_cp_performance_boxes(drm_radeon_private_t *dev_priv)
|
||||
{
|
||||
/* Collapse various things into a wait flag -- trying to
|
||||
* guess if userspase slept -- better just to have them tell us.
|
||||
|
|
@ -870,7 +866,7 @@ static void radeon_cp_dispatch_clear(struct drm_device * dev,
|
|||
|
||||
dev_priv->stats.clears++;
|
||||
|
||||
if (dev_priv->sarea_priv->pfCurrentPage == 1) {
|
||||
if (sarea_priv->pfCurrentPage == 1) {
|
||||
unsigned int tmp = flags;
|
||||
|
||||
flags &= ~(RADEON_FRONT | RADEON_BACK);
|
||||
|
|
@ -896,7 +892,7 @@ static void radeon_cp_dispatch_clear(struct drm_device * dev,
|
|||
|
||||
/* Make sure we restore the 3D state next time.
|
||||
*/
|
||||
dev_priv->sarea_priv->ctx_owner = 0;
|
||||
sarea_priv->ctx_owner = 0;
|
||||
|
||||
for (i = 0; i < nbox; i++) {
|
||||
int x = pbox[i].x1;
|
||||
|
|
@ -973,7 +969,7 @@ static void radeon_cp_dispatch_clear(struct drm_device * dev,
|
|||
/* Make sure we restore the 3D state next time.
|
||||
* we haven't touched any "normal" state - still need this?
|
||||
*/
|
||||
dev_priv->sarea_priv->ctx_owner = 0;
|
||||
sarea_priv->ctx_owner = 0;
|
||||
|
||||
if ((dev_priv->flags & RADEON_HAS_HIERZ)
|
||||
&& (flags & RADEON_USE_HIERZ)) {
|
||||
|
|
@ -1021,7 +1017,7 @@ static void radeon_cp_dispatch_clear(struct drm_device * dev,
|
|||
int tileoffset, nrtilesx, nrtilesy, j;
|
||||
/* it looks like r200 needs rv-style clears, at least if hierz is not enabled? */
|
||||
if ((dev_priv->flags & RADEON_HAS_HIERZ)
|
||||
&& (dev_priv->chip_family < CHIP_R200)) {
|
||||
&& !(dev_priv->microcode_version == UCODE_R200)) {
|
||||
/* FIXME : figure this out for r200 (when hierz is enabled). Or
|
||||
maybe r200 actually doesn't need to put the low-res z value into
|
||||
the tile cache like r100, but just needs to clear the hi-level z-buffer?
|
||||
|
|
@ -1050,8 +1046,7 @@ static void radeon_cp_dispatch_clear(struct drm_device * dev,
|
|||
ADVANCE_RING();
|
||||
tileoffset += depthpixperline >> 6;
|
||||
}
|
||||
} else if ((dev_priv->chip_family >= CHIP_R200) &&
|
||||
(dev_priv->chip_family <= CHIP_RV280)) {
|
||||
} else if (dev_priv->microcode_version == UCODE_R200) {
|
||||
/* works for rv250. */
|
||||
/* find first macro tile (8x2 4x4 z-pixels on rv250) */
|
||||
tileoffset =
|
||||
|
|
@ -1106,8 +1101,7 @@ static void radeon_cp_dispatch_clear(struct drm_device * dev,
|
|||
|
||||
/* TODO don't always clear all hi-level z tiles */
|
||||
if ((dev_priv->flags & RADEON_HAS_HIERZ)
|
||||
&& ((dev_priv->chip_family >= CHIP_R200) &&
|
||||
(dev_priv->chip_family <= CHIP_RV280))
|
||||
&& (dev_priv->microcode_version == UCODE_R200)
|
||||
&& (flags & RADEON_USE_HIERZ))
|
||||
/* r100 and cards without hierarchical z-buffer have no high-level z-buffer */
|
||||
/* FIXME : the mask supposedly contains low-res z values. So can't set
|
||||
|
|
@ -1127,9 +1121,8 @@ static void radeon_cp_dispatch_clear(struct drm_device * dev,
|
|||
* rendering a quad into just those buffers. Thus, we have to
|
||||
* make sure the 3D engine is configured correctly.
|
||||
*/
|
||||
else if ((dev_priv->chip_family >= CHIP_R200) &&
|
||||
(dev_priv->chip_family <= CHIP_RV280) &&
|
||||
(flags & (RADEON_DEPTH | RADEON_STENCIL))) {
|
||||
else if ((dev_priv->microcode_version == UCODE_R200) &&
|
||||
(flags & (RADEON_DEPTH | RADEON_STENCIL))) {
|
||||
|
||||
int tempPP_CNTL;
|
||||
int tempRE_CNTL;
|
||||
|
|
@ -1223,7 +1216,7 @@ static void radeon_cp_dispatch_clear(struct drm_device * dev,
|
|||
|
||||
/* Make sure we restore the 3D state next time.
|
||||
*/
|
||||
dev_priv->sarea_priv->ctx_owner = 0;
|
||||
sarea_priv->ctx_owner = 0;
|
||||
|
||||
for (i = 0; i < nbox; i++) {
|
||||
|
||||
|
|
@ -1294,7 +1287,7 @@ static void radeon_cp_dispatch_clear(struct drm_device * dev,
|
|||
|
||||
/* Make sure we restore the 3D state next time.
|
||||
*/
|
||||
dev_priv->sarea_priv->ctx_owner = 0;
|
||||
sarea_priv->ctx_owner = 0;
|
||||
|
||||
for (i = 0; i < nbox; i++) {
|
||||
|
||||
|
|
@ -1337,17 +1330,17 @@ static void radeon_cp_dispatch_clear(struct drm_device * dev,
|
|||
* wait on this value before performing the clear ioctl. We
|
||||
* need this because the card's so damned fast...
|
||||
*/
|
||||
dev_priv->sarea_priv->last_clear++;
|
||||
sarea_priv->last_clear++;
|
||||
|
||||
BEGIN_RING(4);
|
||||
|
||||
RADEON_CLEAR_AGE(dev_priv->sarea_priv->last_clear);
|
||||
RADEON_CLEAR_AGE(sarea_priv->last_clear);
|
||||
RADEON_WAIT_UNTIL_IDLE();
|
||||
|
||||
ADVANCE_RING();
|
||||
}
|
||||
|
||||
static void radeon_cp_dispatch_swap(struct drm_device * dev)
|
||||
static void radeon_cp_dispatch_swap(struct drm_device *dev)
|
||||
{
|
||||
drm_radeon_private_t *dev_priv = dev->dev_private;
|
||||
drm_radeon_sarea_t *sarea_priv = dev_priv->sarea_priv;
|
||||
|
|
@ -1394,7 +1387,7 @@ static void radeon_cp_dispatch_swap(struct drm_device * dev)
|
|||
/* Make this work even if front & back are flipped:
|
||||
*/
|
||||
OUT_RING(CP_PACKET0(RADEON_SRC_PITCH_OFFSET, 1));
|
||||
if (dev_priv->sarea_priv->pfCurrentPage == 0) {
|
||||
if (sarea_priv->pfCurrentPage == 0) {
|
||||
OUT_RING(dev_priv->back_pitch_offset);
|
||||
OUT_RING(dev_priv->front_pitch_offset);
|
||||
} else {
|
||||
|
|
@ -1414,20 +1407,20 @@ static void radeon_cp_dispatch_swap(struct drm_device * dev)
|
|||
* throttle the framerate by waiting for this value before
|
||||
* performing the swapbuffer ioctl.
|
||||
*/
|
||||
dev_priv->sarea_priv->last_frame++;
|
||||
sarea_priv->last_frame++;
|
||||
|
||||
BEGIN_RING(4);
|
||||
|
||||
RADEON_FRAME_AGE(dev_priv->sarea_priv->last_frame);
|
||||
RADEON_FRAME_AGE(sarea_priv->last_frame);
|
||||
RADEON_WAIT_UNTIL_2D_IDLE();
|
||||
|
||||
ADVANCE_RING();
|
||||
}
|
||||
|
||||
static void radeon_cp_dispatch_flip(struct drm_device * dev)
|
||||
static void radeon_cp_dispatch_flip(struct drm_device *dev)
|
||||
{
|
||||
drm_radeon_private_t *dev_priv = dev->dev_private;
|
||||
struct drm_sarea *sarea = (struct drm_sarea *) dev_priv->sarea->handle;
|
||||
struct drm_sarea *sarea = (struct drm_sarea *)dev_priv->sarea->handle;
|
||||
int offset = (dev_priv->sarea_priv->pfCurrentPage == 1)
|
||||
? dev_priv->front_offset : dev_priv->back_offset;
|
||||
RING_LOCALS;
|
||||
|
|
@ -1548,7 +1541,7 @@ static void radeon_cp_dispatch_vertex(struct drm_device * dev,
|
|||
} while (i < nbox);
|
||||
}
|
||||
|
||||
static void radeon_cp_discard_buffer(struct drm_device * dev, struct drm_buf * buf)
|
||||
static void radeon_cp_discard_buffer(struct drm_device *dev, struct drm_buf *buf)
|
||||
{
|
||||
drm_radeon_private_t *dev_priv = dev->dev_private;
|
||||
drm_radeon_buf_priv_t *buf_priv = buf->dev_private;
|
||||
|
|
@ -1557,9 +1550,15 @@ static void radeon_cp_discard_buffer(struct drm_device * dev, struct drm_buf * b
|
|||
buf_priv->age = ++dev_priv->sarea_priv->last_dispatch;
|
||||
|
||||
/* Emit the vertex buffer age */
|
||||
BEGIN_RING(2);
|
||||
RADEON_DISPATCH_AGE(buf_priv->age);
|
||||
ADVANCE_RING();
|
||||
if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600) {
|
||||
BEGIN_RING(3);
|
||||
R600_DISPATCH_AGE(buf_priv->age);
|
||||
ADVANCE_RING();
|
||||
} else {
|
||||
BEGIN_RING(2);
|
||||
RADEON_DISPATCH_AGE(buf_priv->age);
|
||||
ADVANCE_RING();
|
||||
}
|
||||
|
||||
buf->pending = 1;
|
||||
buf->used = 0;
|
||||
|
|
@ -1599,7 +1598,7 @@ static void radeon_cp_dispatch_indirect(struct drm_device * dev,
|
|||
}
|
||||
}
|
||||
|
||||
static void radeon_cp_dispatch_indices(struct drm_device * dev,
|
||||
static void radeon_cp_dispatch_indices(struct drm_device *dev,
|
||||
struct drm_buf * elt_buf,
|
||||
drm_radeon_tcl_prim_t * prim)
|
||||
{
|
||||
|
|
@ -2099,11 +2098,6 @@ static int radeon_surface_alloc(struct drm_device *dev, void *data, struct drm_f
|
|||
drm_radeon_private_t *dev_priv = dev->dev_private;
|
||||
drm_radeon_surface_alloc_t *alloc = data;
|
||||
|
||||
if (!dev_priv) {
|
||||
DRM_ERROR("called with no initialization\n");
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
if (alloc_surface(alloc, dev_priv, file_priv) == -1)
|
||||
return -EINVAL;
|
||||
else
|
||||
|
|
@ -2115,11 +2109,6 @@ static int radeon_surface_free(struct drm_device *dev, void *data, struct drm_fi
|
|||
drm_radeon_private_t *dev_priv = dev->dev_private;
|
||||
drm_radeon_surface_free_t *memfree = data;
|
||||
|
||||
if (!dev_priv) {
|
||||
DRM_ERROR("called with no initialization\n");
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
if (free_surface(file_priv, dev_priv, memfree->address))
|
||||
return -EINVAL;
|
||||
else
|
||||
|
|
@ -2153,7 +2142,7 @@ static int radeon_cp_clear(struct drm_device *dev, void *data, struct drm_file *
|
|||
|
||||
/* Not sure why this isn't set all the time:
|
||||
*/
|
||||
static int radeon_do_init_pageflip(struct drm_device * dev)
|
||||
static int radeon_do_init_pageflip(struct drm_device *dev)
|
||||
{
|
||||
drm_radeon_private_t *dev_priv = dev->dev_private;
|
||||
RING_LOCALS;
|
||||
|
|
@ -2203,6 +2192,7 @@ static int radeon_cp_swap(struct drm_device *dev, void *data, struct drm_file *f
|
|||
{
|
||||
drm_radeon_private_t *dev_priv = dev->dev_private;
|
||||
drm_radeon_sarea_t *sarea_priv = dev_priv->sarea_priv;
|
||||
|
||||
DRM_DEBUG("\n");
|
||||
|
||||
LOCK_TEST_WITH_RETURN(dev, file_priv);
|
||||
|
|
@ -2213,7 +2203,7 @@ static int radeon_cp_swap(struct drm_device *dev, void *data, struct drm_file *f
|
|||
sarea_priv->nbox = RADEON_NR_SAREA_CLIPRECTS;
|
||||
|
||||
radeon_cp_dispatch_swap(dev);
|
||||
dev_priv->sarea_priv->ctx_owner = 0;
|
||||
sarea_priv->ctx_owner = 0;
|
||||
|
||||
COMMIT_RING();
|
||||
return 0;
|
||||
|
|
@ -2230,11 +2220,6 @@ static int radeon_cp_vertex(struct drm_device *dev, void *data, struct drm_file
|
|||
|
||||
LOCK_TEST_WITH_RETURN(dev, file_priv);
|
||||
|
||||
if (!dev_priv) {
|
||||
DRM_ERROR("called with no initialization\n");
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
sarea_priv = dev_priv->sarea_priv;
|
||||
|
||||
DRM_DEBUG("pid=%d index=%d count=%d discard=%d\n",
|
||||
|
|
@ -2289,7 +2274,7 @@ static int radeon_cp_vertex(struct drm_device *dev, void *data, struct drm_file
|
|||
prim.finish = vertex->count; /* unused */
|
||||
prim.prim = vertex->prim;
|
||||
prim.numverts = vertex->count;
|
||||
prim.vc_format = dev_priv->sarea_priv->vc_format;
|
||||
prim.vc_format = sarea_priv->vc_format;
|
||||
|
||||
radeon_cp_dispatch_vertex(dev, buf, &prim);
|
||||
}
|
||||
|
|
@ -2314,10 +2299,6 @@ static int radeon_cp_indices(struct drm_device *dev, void *data, struct drm_file
|
|||
|
||||
LOCK_TEST_WITH_RETURN(dev, file_priv);
|
||||
|
||||
if (!dev_priv) {
|
||||
DRM_ERROR("called with no initialization\n");
|
||||
return -EINVAL;
|
||||
}
|
||||
sarea_priv = dev_priv->sarea_priv;
|
||||
|
||||
DRM_DEBUG("pid=%d index=%d start=%d end=%d discard=%d\n",
|
||||
|
|
@ -2385,7 +2366,7 @@ static int radeon_cp_indices(struct drm_device *dev, void *data, struct drm_file
|
|||
prim.prim = elts->prim;
|
||||
prim.offset = 0; /* offset from start of dma buffers */
|
||||
prim.numverts = RADEON_MAX_VB_VERTS; /* duh */
|
||||
prim.vc_format = dev_priv->sarea_priv->vc_format;
|
||||
prim.vc_format = sarea_priv->vc_format;
|
||||
|
||||
radeon_cp_dispatch_indices(dev, buf, &prim);
|
||||
if (elts->discard) {
|
||||
|
|
@ -2490,24 +2471,25 @@ static int radeon_cp_indirect(struct drm_device *dev, void *data, struct drm_fil
|
|||
|
||||
buf->used = indirect->end;
|
||||
|
||||
/* Wait for the 3D stream to idle before the indirect buffer
|
||||
* containing 2D acceleration commands is processed.
|
||||
*/
|
||||
BEGIN_RING(2);
|
||||
|
||||
RADEON_WAIT_UNTIL_3D_IDLE();
|
||||
|
||||
ADVANCE_RING();
|
||||
|
||||
/* Dispatch the indirect buffer full of commands from the
|
||||
* X server. This is insecure and is thus only available to
|
||||
* privileged clients.
|
||||
*/
|
||||
radeon_cp_dispatch_indirect(dev, buf, indirect->start, indirect->end);
|
||||
if (indirect->discard) {
|
||||
radeon_cp_discard_buffer(dev, buf);
|
||||
if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
|
||||
r600_cp_dispatch_indirect(dev, buf, indirect->start, indirect->end);
|
||||
else {
|
||||
/* Wait for the 3D stream to idle before the indirect buffer
|
||||
* containing 2D acceleration commands is processed.
|
||||
*/
|
||||
BEGIN_RING(2);
|
||||
RADEON_WAIT_UNTIL_3D_IDLE();
|
||||
ADVANCE_RING();
|
||||
radeon_cp_dispatch_indirect(dev, buf, indirect->start, indirect->end);
|
||||
}
|
||||
|
||||
if (indirect->discard)
|
||||
radeon_cp_discard_buffer(dev, buf);
|
||||
|
||||
COMMIT_RING();
|
||||
return 0;
|
||||
}
|
||||
|
|
@ -2524,11 +2506,6 @@ static int radeon_cp_vertex2(struct drm_device *dev, void *data, struct drm_file
|
|||
|
||||
LOCK_TEST_WITH_RETURN(dev, file_priv);
|
||||
|
||||
if (!dev_priv) {
|
||||
DRM_ERROR("called with no initialization\n");
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
sarea_priv = dev_priv->sarea_priv;
|
||||
|
||||
DRM_DEBUG("pid=%d index=%d discard=%d\n",
|
||||
|
|
@ -2719,10 +2696,10 @@ static __inline__ int radeon_emit_veclinear(drm_radeon_private_t *dev_priv,
|
|||
int start = header.veclinear.addr_lo | (header.veclinear.addr_hi << 8);
|
||||
RING_LOCALS;
|
||||
|
||||
if (!sz)
|
||||
return 0;
|
||||
if (sz * 4 > cmdbuf->bufsz)
|
||||
return -EINVAL;
|
||||
if (!sz)
|
||||
return 0;
|
||||
if (sz * 4 > cmdbuf->bufsz)
|
||||
return -EINVAL;
|
||||
|
||||
BEGIN_RING(5 + sz);
|
||||
OUT_RING_REG(RADEON_SE_TCL_STATE_FLUSH, 0);
|
||||
|
|
@ -2867,11 +2844,6 @@ static int radeon_cp_cmdbuf(struct drm_device *dev, void *data, struct drm_file
|
|||
|
||||
LOCK_TEST_WITH_RETURN(dev, file_priv);
|
||||
|
||||
if (!dev_priv) {
|
||||
DRM_ERROR("called with no initialization\n");
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
RING_SPACE_TEST_WITH_RETURN(dev_priv);
|
||||
VB_AGE_TEST_WITH_RETURN(dev_priv);
|
||||
|
||||
|
|
@ -2898,7 +2870,7 @@ static int radeon_cp_cmdbuf(struct drm_device *dev, void *data, struct drm_file
|
|||
|
||||
orig_nbox = cmdbuf->nbox;
|
||||
|
||||
if (dev_priv->chip_family >= CHIP_R300) {
|
||||
if (dev_priv->microcode_version == UCODE_R300) {
|
||||
int temp;
|
||||
temp = r300_do_cp_cmdbuf(dev, file_priv, cmdbuf);
|
||||
|
||||
|
|
@ -3028,11 +3000,6 @@ static int radeon_cp_getparam(struct drm_device *dev, void *data, struct drm_fil
|
|||
drm_radeon_getparam_t *param = data;
|
||||
int value;
|
||||
|
||||
if (!dev_priv) {
|
||||
DRM_ERROR("called with no initialization\n");
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
DRM_DEBUG("pid=%d\n", DRM_CURRENTPID);
|
||||
|
||||
switch (param->param) {
|
||||
|
|
@ -3041,14 +3008,14 @@ static int radeon_cp_getparam(struct drm_device *dev, void *data, struct drm_fil
|
|||
break;
|
||||
case RADEON_PARAM_LAST_FRAME:
|
||||
dev_priv->stats.last_frame_reads++;
|
||||
value = GET_SCRATCH(0);
|
||||
value = GET_SCRATCH(dev_priv, 0);
|
||||
break;
|
||||
case RADEON_PARAM_LAST_DISPATCH:
|
||||
value = GET_SCRATCH(1);
|
||||
value = GET_SCRATCH(dev_priv, 1);
|
||||
break;
|
||||
case RADEON_PARAM_LAST_CLEAR:
|
||||
dev_priv->stats.last_clear_reads++;
|
||||
value = GET_SCRATCH(2);
|
||||
value = GET_SCRATCH(dev_priv, 2);
|
||||
break;
|
||||
case RADEON_PARAM_IRQ_NR:
|
||||
value = dev->irq;
|
||||
|
|
@ -3083,9 +3050,11 @@ static int radeon_cp_getparam(struct drm_device *dev, void *data, struct drm_fil
|
|||
case RADEON_PARAM_SCRATCH_OFFSET:
|
||||
if (!dev_priv->writeback_works)
|
||||
return -EINVAL;
|
||||
value = RADEON_SCRATCH_REG_OFFSET;
|
||||
if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
|
||||
value = R600_SCRATCH_REG_OFFSET;
|
||||
else
|
||||
value = RADEON_SCRATCH_REG_OFFSET;
|
||||
break;
|
||||
|
||||
case RADEON_PARAM_CARD_TYPE:
|
||||
if (dev_priv->flags & RADEON_IS_PCIE)
|
||||
value = RADEON_CARD_PCIE;
|
||||
|
|
@ -3104,7 +3073,7 @@ static int radeon_cp_getparam(struct drm_device *dev, void *data, struct drm_fil
|
|||
value = dev_priv->num_gb_pipes;
|
||||
break;
|
||||
default:
|
||||
DRM_DEBUG( "Invalid parameter %d\n", param->param );
|
||||
DRM_DEBUG("Invalid parameter %d\n", param->param);
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
|
|
@ -3122,11 +3091,6 @@ static int radeon_cp_setparam(struct drm_device *dev, void *data, struct drm_fil
|
|||
drm_radeon_setparam_t *sp = data;
|
||||
struct drm_radeon_driver_file_fields *radeon_priv;
|
||||
|
||||
if (!dev_priv) {
|
||||
DRM_ERROR("called with no initialization\n");
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
switch (sp->param) {
|
||||
case RADEON_SETPARAM_FB_LOCATION:
|
||||
radeon_priv = file_priv->driver_priv;
|
||||
|
|
@ -3178,8 +3142,7 @@ static int radeon_cp_setparam(struct drm_device *dev, void *data, struct drm_fil
|
|||
*
|
||||
* DRM infrastructure takes care of reclaiming dma buffers.
|
||||
*/
|
||||
void radeon_driver_preclose(struct drm_device *dev,
|
||||
struct drm_file *file_priv)
|
||||
void radeon_driver_preclose(struct drm_device *dev, struct drm_file *file_priv)
|
||||
{
|
||||
if (dev->dev_private) {
|
||||
drm_radeon_private_t *dev_priv = dev->dev_private;
|
||||
|
|
@ -3192,14 +3155,7 @@ void radeon_driver_preclose(struct drm_device *dev,
|
|||
|
||||
void radeon_driver_lastclose(struct drm_device *dev)
|
||||
{
|
||||
if (dev->dev_private) {
|
||||
drm_radeon_private_t *dev_priv = dev->dev_private;
|
||||
|
||||
if (dev_priv->sarea_priv &&
|
||||
dev_priv->sarea_priv->pfCurrentPage != 0)
|
||||
radeon_cp_dispatch_flip(dev);
|
||||
}
|
||||
|
||||
radeon_surfaces_release(PCIGART_FILE_PRIV, dev->dev_private);
|
||||
radeon_do_release(dev);
|
||||
}
|
||||
|
||||
|
|
@ -3248,7 +3204,7 @@ struct drm_ioctl_desc radeon_ioctls[] = {
|
|||
DRM_IOCTL_DEF(DRM_RADEON_INDICES, radeon_cp_indices, DRM_AUTH),
|
||||
DRM_IOCTL_DEF(DRM_RADEON_TEXTURE, radeon_cp_texture, DRM_AUTH),
|
||||
DRM_IOCTL_DEF(DRM_RADEON_STIPPLE, radeon_cp_stipple, DRM_AUTH),
|
||||
DRM_IOCTL_DEF(DRM_RADEON_INDIRECT, radeon_cp_indirect, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
|
||||
DRM_IOCTL_DEF(DRM_RADEON_INDIRECT, radeon_cp_indirect, DRM_AUTH|DRM_ROOT_ONLY),
|
||||
DRM_IOCTL_DEF(DRM_RADEON_VERTEX2, radeon_cp_vertex2, DRM_AUTH),
|
||||
DRM_IOCTL_DEF(DRM_RADEON_CMDBUF, radeon_cp_cmdbuf, DRM_AUTH),
|
||||
DRM_IOCTL_DEF(DRM_RADEON_GETPARAM, radeon_cp_getparam, DRM_AUTH),
|
||||
|
|
|
|||
|
|
@ -2,7 +2,7 @@
|
|||
|
||||
.PATH: ${.CURDIR}/../../../dev/drm
|
||||
KMOD = radeon
|
||||
SRCS = r300_cmdbuf.c radeon_cp.c radeon_drv.c radeon_irq.c \
|
||||
SRCS = r300_cmdbuf.c r600_cp.c radeon_cp.c radeon_drv.c radeon_irq.c \
|
||||
radeon_mem.c radeon_state.c
|
||||
SRCS +=device_if.h bus_if.h pci_if.h opt_drm.h
|
||||
|
||||
|
|
|
|||
Loading…
Reference in a new issue