From 4f82af24f1113a7df224daded227d4e9de582c0b Mon Sep 17 00:00:00 2001 From: Konstantin Belousov Date: Mon, 16 Sep 2024 20:57:23 +0300 Subject: [PATCH] amd64 pmap: do not set PG_G for usermode pmap pml5 kernel entry Sponsored by: Advanced Micro Devices (AMD) Sponsored by: The FreeBSD Foundation MFC after: 1 week --- sys/amd64/amd64/pmap.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/sys/amd64/amd64/pmap.c b/sys/amd64/amd64/pmap.c index f7e3ef4233e..fd4697a266e 100644 --- a/sys/amd64/amd64/pmap.c +++ b/sys/amd64/amd64/pmap.c @@ -4375,7 +4375,7 @@ pmap_pinit_pml5(vm_page_t pml5pg) * entering all existing kernel mappings into level 5 table. */ pm_pml5[pmap_pml5e_index(UPT_MAX_ADDRESS)] = KPML4phys | X86_PG_V | - X86_PG_RW | X86_PG_A | X86_PG_M | pg_g | + X86_PG_RW | X86_PG_A | X86_PG_M | pmap_cache_bits(kernel_pmap, VM_MEMATTR_DEFAULT, false); /* @@ -4412,7 +4412,7 @@ pmap_pinit_pml5_pti(vm_page_t pml5pgu) */ pm_pml5u[pmap_pml5e_index(UPT_MAX_ADDRESS)] = pmap_kextract((vm_offset_t)pti_pml4) | - X86_PG_V | X86_PG_RW | X86_PG_A | X86_PG_M | pg_g | + X86_PG_V | X86_PG_RW | X86_PG_A | X86_PG_M | pmap_cache_bits(kernel_pmap, VM_MEMATTR_DEFAULT, false); }