diff --git a/sys/arm64/rockchip/clk/rk_clk_pll.c b/sys/arm64/rockchip/clk/rk_clk_pll.c
index 19ae9fd4926..0023d73d45a 100644
--- a/sys/arm64/rockchip/clk/rk_clk_pll.c
+++ b/sys/arm64/rockchip/clk/rk_clk_pll.c
@@ -427,7 +427,7 @@ rk3399_clk_pll_set_freq(struct clknode *clk, uint64_t fparent, uint64_t *fout,
 	/* Setting to slow mode during frequency change */
 	reg = RK3399_CLK_PLL_MODE_SLOW << RK3399_CLK_PLL_MODE_SHIFT;
 	reg |= RK3399_CLK_PLL_MODE_MASK << RK_CLK_PLL_MASK_SHIFT;
-	WRITE4(clk, sc->mode_reg, reg);
+	WRITE4(clk, sc->base_offset + 0xC, reg);
 
 	/* Setting fbdiv */
 	READ4(clk, sc->base_offset, &reg);