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Make some UART consoles to not spin wait for data to be sent.
At least with Tx FIFO enabled it shows me ~10% reduction of verbose boot time with serial console at 115200 baud. Reviewed by: marcel MFC after: 2 weeks
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parent
9f665e12ce
commit
4e352a4583
2 changed files with 15 additions and 11 deletions
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@ -345,9 +345,6 @@ lpc_ns8250_putc(struct uart_bas *bas, int c)
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DELAY(4);
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uart_setreg(bas, REG_DATA, c);
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uart_barrier(bas);
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limit = 250000;
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while ((uart_getreg(bas, REG_LSR) & LSR_TEMT) == 0 && --limit)
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DELAY(4);
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}
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static int
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@ -890,8 +887,13 @@ lpc_ns8250_bus_transmit(struct uart_softc *sc)
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bas = &sc->sc_bas;
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uart_lock(sc->sc_hwmtx);
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while ((uart_getreg(bas, REG_LSR) & LSR_THRE) == 0)
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;
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if (sc->sc_txdatasz > 1) {
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if ((uart_getreg(bas, REG_LSR) & LSR_TEMT) == 0)
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ns8250_drain(bas, UART_DRAIN_TRANSMITTER);
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} else {
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while ((uart_getreg(bas, REG_LSR) & LSR_THRE) == 0)
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DELAY(4);
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}
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for (i = 0; i < sc->sc_txdatasz; i++) {
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uart_setreg(bas, REG_DATA, sc->sc_txbuf[i]);
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uart_barrier(bas);
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@ -315,7 +315,7 @@ ns8250_init(struct uart_bas *bas, int baudrate, int databits, int stopbits,
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/* Disable the FIFO (if present). */
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val = 0;
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#ifdef CPU_XBURST
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val = FCR_UART_ON;
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val |= FCR_UART_ON;
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#endif
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uart_setreg(bas, REG_FCR, val);
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uart_barrier(bas);
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@ -346,9 +346,6 @@ ns8250_putc(struct uart_bas *bas, int c)
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DELAY(4);
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uart_setreg(bas, REG_DATA, c);
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uart_barrier(bas);
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limit = 250000;
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while ((uart_getreg(bas, REG_LSR) & LSR_TEMT) == 0 && --limit)
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DELAY(4);
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}
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static int
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@ -999,8 +996,13 @@ ns8250_bus_transmit(struct uart_softc *sc)
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bas = &sc->sc_bas;
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uart_lock(sc->sc_hwmtx);
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while ((uart_getreg(bas, REG_LSR) & LSR_THRE) == 0)
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;
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if (sc->sc_txdatasz > 1) {
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if ((uart_getreg(bas, REG_LSR) & LSR_TEMT) == 0)
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ns8250_drain(bas, UART_DRAIN_TRANSMITTER);
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} else {
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while ((uart_getreg(bas, REG_LSR) & LSR_THRE) == 0)
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DELAY(4);
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}
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for (i = 0; i < sc->sc_txdatasz; i++) {
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uart_setreg(bas, REG_DATA, sc->sc_txbuf[i]);
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uart_barrier(bas);
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