mirror of
https://github.com/opnsense/src.git
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Adda new common GIC header to handle the common parts of the GICv2 and
GICv3 drivers. For now it just contains common distributor registers. Obtained from: ABT Systems Ltd Sponsored by: The FreeBSD Foundation
This commit is contained in:
Andrew Turner
parent
3cbaf64f2e
commit
4d7d72fb23
2 changed files with 102 additions and 47 deletions
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@ -67,6 +67,7 @@ __FBSDID("$FreeBSD$");
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#endif
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#include <arm/arm/gic.h>
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#include <arm/arm/gic_common.h>
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#ifdef INTRNG
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#include "pic_if.h"
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@ -76,20 +77,6 @@ __FBSDID("$FreeBSD$");
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/* We are using GICv2 register naming */
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/* Distributor Registers */
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#define GICD_CTLR 0x000 /* v1 ICDDCR */
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#define GICD_TYPER 0x004 /* v1 ICDICTR */
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#define GICD_IIDR 0x008 /* v1 ICDIIDR */
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#define GICD_IGROUPR(n) (0x0080 + ((n) * 4)) /* v1 ICDISER */
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#define GICD_ISENABLER(n) (0x0100 + ((n) * 4)) /* v1 ICDISER */
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#define GICD_ICENABLER(n) (0x0180 + ((n) * 4)) /* v1 ICDICER */
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#define GICD_ISPENDR(n) (0x0200 + ((n) * 4)) /* v1 ICDISPR */
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#define GICD_ICPENDR(n) (0x0280 + ((n) * 4)) /* v1 ICDICPR */
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#define GICD_ICACTIVER(n) (0x0380 + ((n) * 4)) /* v1 ICDABR */
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#define GICD_IPRIORITYR(n) (0x0400 + ((n) * 4)) /* v1 ICDIPR */
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#define GICD_ITARGETSR(n) (0x0800 + ((n) * 4)) /* v1 ICDIPTR */
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#define GICD_ICFGR(n) (0x0C00 + ((n) * 4)) /* v1 ICDICFR */
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#define GICD_SGIR(n) (0x0F00 + ((n) * 4)) /* v1 ICDSGIR */
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#define GICD_SGI_TARGET_SHIFT 16
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/* CPU Registers */
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#define GICC_CTLR 0x0000 /* v1 ICCICR */
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@ -107,14 +94,6 @@ __FBSDID("$FreeBSD$");
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#define GIC_SUPPORT_SECEXT(_sc) \
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((_sc->typer & GICD_TYPER_SECURITYEXT) == GICD_TYPER_SECURITYEXT)
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/* First bit is a polarity bit (0 - low, 1 - high) */
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#define GICD_ICFGR_POL_LOW (0 << 0)
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#define GICD_ICFGR_POL_HIGH (1 << 0)
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#define GICD_ICFGR_POL_MASK 0x1
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/* Second bit is a trigger bit (0 - level, 1 - edge) */
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#define GICD_ICFGR_TRIG_LVL (0 << 1)
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#define GICD_ICFGR_TRIG_EDGE (1 << 1)
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#define GICD_ICFGR_TRIG_MASK 0x2
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#ifndef GIC_DEFAULT_ICFGR_INIT
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#define GIC_DEFAULT_ICFGR_INIT 0x00000000
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@ -192,14 +171,14 @@ static inline void
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gic_irq_unmask(struct arm_gic_softc *sc, u_int irq)
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{
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gic_d_write_4(sc, GICD_ISENABLER(irq >> 5), (1UL << (irq & 0x1F)));
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gic_d_write_4(sc, GICD_ISENABLER(irq), (1UL << (irq & 0x1F)));
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}
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static inline void
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gic_irq_mask(struct arm_gic_softc *sc, u_int irq)
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{
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gic_d_write_4(sc, GICD_ICENABLER(irq >> 5), (1UL << (irq & 0x1F)));
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gic_d_write_4(sc, GICD_ICENABLER(irq), (1UL << (irq & 0x1F)));
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}
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#endif
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@ -239,11 +218,11 @@ arm_gic_init_secondary(device_t dev)
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arm_gic_map[cpu] = gic_cpu_mask(sc);
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for (irq = 0; irq < sc->nirqs; irq += 4)
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gic_d_write_4(sc, GICD_IPRIORITYR(irq >> 2), 0);
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gic_d_write_4(sc, GICD_IPRIORITYR(irq), 0);
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/* Set all the interrupts to be in Group 0 (secure) */
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for (irq = 0; GIC_SUPPORT_SECEXT(sc) && irq < sc->nirqs; irq += 32) {
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gic_d_write_4(sc, GICD_IGROUPR(irq >> 5), 0);
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gic_d_write_4(sc, GICD_IGROUPR(irq), 0);
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}
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/* Enable CPU interface */
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@ -276,11 +255,11 @@ arm_gic_init_secondary(device_t dev)
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arm_gic_map[PCPU_GET(cpuid)] = gic_cpu_mask(sc);
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for (i = 0; i < sc->nirqs; i += 4)
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gic_d_write_4(sc, GICD_IPRIORITYR(i >> 2), 0);
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gic_d_write_4(sc, GICD_IPRIORITYR(i), 0);
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/* Set all the interrupts to be in Group 0 (secure) */
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for (i = 0; GIC_SUPPORT_SECEXT(sc) && i < sc->nirqs; i += 32) {
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gic_d_write_4(sc, GICD_IGROUPR(i >> 5), 0);
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gic_d_write_4(sc, GICD_IGROUPR(i), 0);
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}
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/* Enable CPU interface */
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@ -295,9 +274,9 @@ arm_gic_init_secondary(device_t dev)
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/*
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* Activate the timer interrupts: virtual, secure, and non-secure.
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*/
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gic_d_write_4(sc, GICD_ISENABLER(27 >> 5), (1UL << (27 & 0x1F)));
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gic_d_write_4(sc, GICD_ISENABLER(29 >> 5), (1UL << (29 & 0x1F)));
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gic_d_write_4(sc, GICD_ISENABLER(30 >> 5), (1UL << (30 & 0x1F)));
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gic_d_write_4(sc, GICD_ISENABLER(27), (1UL << (27 & 0x1F)));
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gic_d_write_4(sc, GICD_ISENABLER(29), (1UL << (29 & 0x1F)));
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gic_d_write_4(sc, GICD_ISENABLER(30), (1UL << (30 & 0x1F)));
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}
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#endif /* INTRNG */
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#endif /* SMP */
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@ -484,18 +463,19 @@ arm_gic_attach(device_t dev)
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#endif
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icciidr = gic_c_read_4(sc, GICC_IIDR);
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device_printf(dev,"pn 0x%x, arch 0x%x, rev 0x%x, implementer 0x%x irqs %u\n",
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icciidr>>20, (icciidr>>16) & 0xF, (icciidr>>12) & 0xf,
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(icciidr & 0xfff), sc->nirqs);
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device_printf(dev,
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"pn 0x%x, arch 0x%x, rev 0x%x, implementer 0x%x irqs %u\n",
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GICD_IIDR_PROD(icciidr), GICD_IIDR_VAR(icciidr),
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GICD_IIDR_REV(icciidr), GICD_IIDR_IMPL(icciidr), sc->nirqs);
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/* Set all global interrupts to be level triggered, active low. */
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for (i = 32; i < sc->nirqs; i += 16) {
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gic_d_write_4(sc, GICD_ICFGR(i >> 4), GIC_DEFAULT_ICFGR_INIT);
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gic_d_write_4(sc, GICD_ICFGR(i), GIC_DEFAULT_ICFGR_INIT);
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}
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/* Disable all interrupts. */
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for (i = 32; i < sc->nirqs; i += 32) {
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gic_d_write_4(sc, GICD_ICENABLER(i >> 5), 0xFFFFFFFF);
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gic_d_write_4(sc, GICD_ICENABLER(i), 0xFFFFFFFF);
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}
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/* Find the current cpu mask */
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@ -507,15 +487,15 @@ arm_gic_attach(device_t dev)
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mask |= mask << 16;
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for (i = 0; i < sc->nirqs; i += 4) {
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gic_d_write_4(sc, GICD_IPRIORITYR(i >> 2), 0);
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gic_d_write_4(sc, GICD_IPRIORITYR(i), 0);
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if (i > 32) {
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gic_d_write_4(sc, GICD_ITARGETSR(i >> 2), mask);
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gic_d_write_4(sc, GICD_ITARGETSR(i), mask);
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}
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}
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/* Set all the interrupts to be in Group 0 (secure) */
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for (i = 0; GIC_SUPPORT_SECEXT(sc) && i < sc->nirqs; i += 32) {
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gic_d_write_4(sc, GICD_IGROUPR(i >> 5), 0);
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gic_d_write_4(sc, GICD_IGROUPR(i), 0);
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}
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/* Enable CPU interface */
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@ -725,7 +705,7 @@ gic_config(struct arm_gic_softc *sc, u_int irq, enum intr_trigger trig,
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mtx_lock_spin(&sc->mutex);
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reg = gic_d_read_4(sc, GICD_ICFGR(irq >> 4));
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reg = gic_d_read_4(sc, GICD_ICFGR(irq));
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mask = (reg >> 2*(irq % 16)) & 0x3;
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if (pol == INTR_POLARITY_LOW) {
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@ -747,7 +727,7 @@ gic_config(struct arm_gic_softc *sc, u_int irq, enum intr_trigger trig,
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/* Set mask */
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reg = reg & ~(0x3 << 2*(irq % 16));
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reg = reg | (mask << 2*(irq % 16));
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gic_d_write_4(sc, GICD_ICFGR(irq >> 4), reg);
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gic_d_write_4(sc, GICD_ICFGR(irq), reg);
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mtx_unlock_spin(&sc->mutex);
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}
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@ -1089,7 +1069,7 @@ arm_gic_ipi_send(device_t dev, struct intr_irqsrc *isrc, cpuset_t cpus,
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if (CPU_ISSET(i, &cpus))
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val |= arm_gic_map[i] << GICD_SGI_TARGET_SHIFT;
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gic_d_write_4(sc, GICD_SGIR(0), val | gi->gi_irq);
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gic_d_write_4(sc, GICD_SGIR, val | gi->gi_irq);
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}
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static int
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@ -1157,7 +1137,7 @@ arm_gic_config(device_t dev, int irq, enum intr_trigger trig,
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mtx_lock_spin(&sc->mutex);
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reg = gic_d_read_4(sc, GICD_ICFGR(irq >> 4));
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reg = gic_d_read_4(sc, GICD_ICFGR(irq));
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mask = (reg >> 2*(irq % 16)) & 0x3;
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if (pol == INTR_POLARITY_LOW) {
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@ -1179,7 +1159,7 @@ arm_gic_config(device_t dev, int irq, enum intr_trigger trig,
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/* Set mask */
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reg = reg & ~(0x3 << 2*(irq % 16));
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reg = reg | (mask << 2*(irq % 16));
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gic_d_write_4(sc, GICD_ICFGR(irq >> 4), reg);
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gic_d_write_4(sc, GICD_ICFGR(irq), reg);
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mtx_unlock_spin(&sc->mutex);
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@ -1196,7 +1176,7 @@ arm_gic_mask(device_t dev, int irq)
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{
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struct arm_gic_softc *sc = device_get_softc(dev);
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gic_d_write_4(sc, GICD_ICENABLER(irq >> 5), (1UL << (irq & 0x1F)));
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gic_d_write_4(sc, GICD_ICENABLER(irq), (1UL << (irq & 0x1F)));
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gic_c_write_4(sc, GICC_EOIR, irq); /* XXX - not allowed */
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}
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@ -1208,7 +1188,7 @@ arm_gic_unmask(device_t dev, int irq)
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if (irq > GIC_LAST_SGI)
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arm_irq_memory_barrier(irq);
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gic_d_write_4(sc, GICD_ISENABLER(irq >> 5), (1UL << (irq & 0x1F)));
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gic_d_write_4(sc, GICD_ISENABLER(irq), (1UL << (irq & 0x1F)));
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}
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#ifdef SMP
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@ -1222,7 +1202,7 @@ arm_gic_ipi_send(device_t dev, cpuset_t cpus, u_int ipi)
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if (CPU_ISSET(i, &cpus))
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val |= arm_gic_map[i] << GICD_SGI_TARGET_SHIFT;
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gic_d_write_4(sc, GICD_SGIR(0), val | ipi);
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gic_d_write_4(sc, GICD_SGIR, val | ipi);
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}
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static int
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75
sys/arm/arm/gic_common.h
Normal file
75
sys/arm/arm/gic_common.h
Normal file
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@ -0,0 +1,75 @@
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/*-
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* Copyright (c) 2016 The FreeBSD Foundation
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* All rights reserved.
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*
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* This software was developed by Andrew Turner under
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* the sponsorship of the FreeBSD Foundation.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* $FreeBSD$
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*/
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#ifndef _GIC_COMMON_H_
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#define _GIC_COMMON_H_
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/* Common register values */
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#define GICD_CTLR 0x0000 /* v1 ICDDCR */
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#define GICD_TYPER 0x0004 /* v1 ICDICTR */
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#define GICD_IIDR 0x0008 /* v1 ICDIIDR */
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#define GICD_IIDR_PROD_SHIFT 24
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#define GICD_IIDR_PROD_MASK 0xff000000
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#define GICD_IIDR_PROD(x) \
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(((x) & GICD_IIDR_PROD_MASK) >> GICD_IIDR_PROD_SHIFT)
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#define GICD_IIDR_VAR_SHIFT 16
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#define GICD_IIDR_VAR_MASK 0x000f0000
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#define GICD_IIDR_VAR(x) \
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(((x) & GICD_IIDR_VAR_MASK) >> GICD_IIDR_VAR_SHIFT)
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#define GICD_IIDR_REV_SHIFT 12
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#define GICD_IIDR_REV_MASK 0x0000f000
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#define GICD_IIDR_REV(x) \
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(((x) & GICD_IIDR_REV_MASK) >> GICD_IIDR_REV_SHIFT)
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#define GICD_IIDR_IMPL_SHIFT 0
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#define GICD_IIDR_IMPL_MASK 0x00000fff
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#define GICD_IIDR_IMPL(x) \
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(((x) & GICD_IIDR_IMPL_MASK) >> GICD_IIDR_IMPL_SHIFT)
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#define GICD_IGROUPR(n) (0x0080 + (((n) >> 5) * 4)) /* v1 ICDISER */
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#define GICD_ISENABLER(n) (0x0100 + (((n) >> 5) * 4)) /* v1 ICDISER */
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#define GICD_ICENABLER(n) (0x0180 + (((n) >> 5) * 4)) /* v1 ICDICER */
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#define GICD_ISPENDR(n) (0x0200 + (((n) >> 5) * 4)) /* v1 ICDISPR */
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#define GICD_ICPENDR(n) (0x0280 + (((n) >> 5) * 4)) /* v1 ICDICPR */
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#define GICD_ICACTIVER(n) (0x0380 + (((n) >> 5) * 4)) /* v1 ICDABR */
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#define GICD_IPRIORITYR(n) (0x0400 + (((n) >> 2) * 4)) /* v1 ICDIPR */
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#define GICD_ITARGETSR(n) (0x0800 + (((n) >> 2) * 4)) /* v1 ICDIPTR */
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#define GICD_ICFGR(n) (0x0C00 + (((n) >> 4) * 4)) /* v1 ICDICFR */
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/* First bit is a polarity bit (0 - low, 1 - high) */
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#define GICD_ICFGR_POL_LOW (0 << 0)
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#define GICD_ICFGR_POL_HIGH (1 << 0)
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#define GICD_ICFGR_POL_MASK 0x1
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/* Second bit is a trigger bit (0 - level, 1 - edge) */
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#define GICD_ICFGR_TRIG_LVL (0 << 1)
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#define GICD_ICFGR_TRIG_EDGE (1 << 1)
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#define GICD_ICFGR_TRIG_MASK 0x2
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#define GICD_SGIR 0x0F00 /* v1 ICDSGIR */
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#define GICD_SGI_TARGET_SHIFT 16
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#endif /* _GIC_COMMON_H_ */
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