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Change the x86 interrupt code to use FreeBSD CPU IDs (i.e. PCPU_GET(cpuid))

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rather than local APIC IDs to keep track of CPUs which can handle
interrupts.
This commit is contained in:
John Baldwin 2007-03-06 17:16:47 +00:00
parent 27d0a1a493
commit 4c5bec1161
10 changed files with 52 additions and 42 deletions
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30
sys/amd64/amd64/intr_machdep.c
View file

@ -52,6 +52,7 @@
#include <sys/systm.h>
#include <machine/clock.h>
#include <machine/intr_machdep.h>
#include <machine/smp.h>
#ifdef DDB
#include <ddb/ddb.h>
#endif
@ -429,8 +430,9 @@ DB_SHOW_COMMAND(irqs, db_show_irqs)
* allocate CPUs round-robin.
*/
static u_int cpu_apic_ids[MAXCPU];
static int current_cpu, num_cpus;
/* The BSP is always a valid target. */
static cpumask_t intr_cpus = (1 << 0);
static int current_cpu, num_cpus = 1;
static void
intr_assign_next_cpu(struct intsrc *isrc)
@ -443,25 +445,29 @@ intr_assign_next_cpu(struct intsrc *isrc)
*/
pic = isrc->is_pic;
apic_id = cpu_apic_ids[current_cpu];
current_cpu++;
if (current_cpu >= num_cpus)
current_cpu = 0;
pic->pic_assign_cpu(isrc, apic_id);
do {
current_cpu++;
if (current_cpu >= num_cpus)
current_cpu = 0;
} while (!(intr_cpus & (1 << current_cpu)));
}
/*
* Add a local APIC ID to our list of valid local APIC IDs that can
* be destinations of interrupts.
* Add a CPU to our mask of valid CPUs that can be destinations of
* interrupts.
*/
void
intr_add_cpu(u_int apic_id)
intr_add_cpu(u_int cpu)
{
if (cpu >= MAXCPU)
panic("%s: Invalid CPU ID", __func__);
if (bootverbose)
printf("INTR: Adding local APIC %d as a target\n", apic_id);
if (num_cpus >= MAXCPU)
panic("WARNING: Local APIC IDs exhausted!");
cpu_apic_ids[num_cpus] = apic_id;
printf("INTR: Adding local APIC %d as a target\n",
cpu_apic_ids[cpu]);
intr_cpus |= (1 << cpu);
num_cpus++;
}

1
sys/amd64/amd64/local_apic.c
View file

@ -220,7 +220,6 @@ lapic_init(vm_paddr_t addr)
/* Set BSP's per-CPU local APIC ID. */
PCPU_SET(apic_id, lapic_id());
intr_add_cpu(PCPU_GET(apic_id));
/* Local APIC timer interrupt. */
setidt(APIC_TIMER_INT, IDTVEC(timerint), SDT_SYSIGT, SEL_KPL, 0);

11
sys/amd64/amd64/mp_machdep.c
View file

@ -152,7 +152,7 @@ struct cpu_info {
int cpu_bsp:1;
int cpu_disabled:1;
} static cpu_info[MAXCPU];
static int cpu_apic_ids[MAXCPU];
int cpu_apic_ids[MAXCPU];
/* Holds pending bitmap based IPIs per CPU */
static volatile u_int cpu_ipi_pending[MAXCPU];
@ -625,10 +625,11 @@ init_secondary(void)
static void
set_interrupt_apic_ids(void)
{
u_int apic_id;
u_int i, apic_id;
for (apic_id = 0; apic_id < MAXCPU; apic_id++) {
if (!cpu_info[apic_id].cpu_present)
for (i = 0; i < MAXCPU; i++) {
apic_id = cpu_apic_ids[i];
if (apic_id == -1)
continue;
if (cpu_info[apic_id].cpu_bsp)
continue;
@ -640,7 +641,7 @@ set_interrupt_apic_ids(void)
apic_id % hyperthreading_cpus != 0)
continue;
intr_add_cpu(apic_id);
intr_add_cpu(i);
}
}

4
sys/amd64/include/intr_machdep.h
View file

@ -131,9 +131,7 @@ enum intr_trigger elcr_read_trigger(u_int irq);
void elcr_resume(void);
void elcr_write_trigger(u_int irq, enum intr_trigger trigger);
#ifdef SMP
void intr_add_cpu(u_int apic_id);
#else
#define intr_add_cpu(apic_id)
void intr_add_cpu(u_int cpu);
#endif
int intr_add_handler(const char *name, int vector, driver_filter_t filter,
driver_intr_t handler, void *arg, enum intr_type flags,

1
sys/amd64/include/smp.h
View file

@ -34,6 +34,7 @@ extern int mp_naps;
extern int boot_cpu_id;
extern struct pcb stoppcbs[];
extern struct mtx smp_tlb_mtx;
extern int cpu_apic_ids[];
/* IPI handlers */
inthand_t

30
sys/i386/i386/intr_machdep.c
View file

@ -51,6 +51,7 @@
#include <sys/systm.h>
#include <machine/clock.h>
#include <machine/intr_machdep.h>
#include <machine/smp.h>
#ifdef DDB
#include <ddb/ddb.h>
#endif
@ -395,8 +396,9 @@ DB_SHOW_COMMAND(irqs, db_show_irqs)
* allocate CPUs round-robin.
*/
static u_int cpu_apic_ids[MAXCPU];
static int current_cpu, num_cpus;
/* The BSP is always a valid target. */
static cpumask_t intr_cpus = (1 << 0);
static int current_cpu, num_cpus = 1;
static void
intr_assign_next_cpu(struct intsrc *isrc)
@ -409,25 +411,29 @@ intr_assign_next_cpu(struct intsrc *isrc)
*/
pic = isrc->is_pic;
apic_id = cpu_apic_ids[current_cpu];
current_cpu++;
if (current_cpu >= num_cpus)
current_cpu = 0;
pic->pic_assign_cpu(isrc, apic_id);
do {
current_cpu++;
if (current_cpu >= num_cpus)
current_cpu = 0;
} while (!(intr_cpus & (1 << current_cpu)));
}
/*
* Add a local APIC ID to our list of valid local APIC IDs that can
* be destinations of interrupts.
* Add a CPU to our mask of valid CPUs that can be destinations of
* interrupts.
*/
void
intr_add_cpu(u_int apic_id)
intr_add_cpu(u_int cpu)
{
if (cpu >= MAXCPU)
panic("%s: Invalid CPU ID", __func__);
if (bootverbose)
printf("INTR: Adding local APIC %d as a target\n", apic_id);
if (num_cpus >= MAXCPU)
panic("WARNING: Local APIC IDs exhausted!");
cpu_apic_ids[num_cpus] = apic_id;
printf("INTR: Adding local APIC %d as a target\n",
cpu_apic_ids[cpu]);
intr_cpus |= (1 << cpu);
num_cpus++;
}

1
sys/i386/i386/local_apic.c
View file

@ -221,7 +221,6 @@ lapic_init(vm_paddr_t addr)
/* Set BSP's per-CPU local APIC ID. */
PCPU_SET(apic_id, lapic_id());
intr_add_cpu(PCPU_GET(apic_id));
/* Local APIC timer interrupt. */
setidt(APIC_TIMER_INT, IDTVEC(timerint), SDT_SYS386IGT, SEL_KPL,

11
sys/i386/i386/mp_machdep.c
View file

@ -209,7 +209,7 @@ struct cpu_info {
int cpu_bsp:1;
int cpu_disabled:1;
} static cpu_info[MAXCPU];
static int cpu_apic_ids[MAXCPU];
int cpu_apic_ids[MAXCPU];
/* Holds pending bitmap based IPIs per CPU */
static volatile u_int cpu_ipi_pending[MAXCPU];
@ -668,10 +668,11 @@ init_secondary(void)
static void
set_interrupt_apic_ids(void)
{
u_int apic_id;
u_int i, apic_id;
for (apic_id = 0; apic_id < MAXCPU; apic_id++) {
if (!cpu_info[apic_id].cpu_present)
for (i = 0; i < MAXCPU; i++) {
apic_id = cpu_apic_ids[i];
if (apic_id == -1)
continue;
if (cpu_info[apic_id].cpu_bsp)
continue;
@ -683,7 +684,7 @@ set_interrupt_apic_ids(void)
apic_id % hyperthreading_cpus != 0)
continue;
intr_add_cpu(apic_id);
intr_add_cpu(i);
}
}

4
sys/i386/include/intr_machdep.h
View file

@ -128,9 +128,7 @@ enum intr_trigger elcr_read_trigger(u_int irq);
void elcr_resume(void);
void elcr_write_trigger(u_int irq, enum intr_trigger trigger);
#ifdef SMP
void intr_add_cpu(u_int apic_id);
#else
#define intr_add_cpu(apic_id)
void intr_add_cpu(u_int cpu);
#endif
int intr_add_handler(const char *name, int vector, driver_filter_t filter,
driver_intr_t handler, void *arg, enum intr_type flags, void **cookiep);

1
sys/i386/include/smp.h
View file

@ -35,6 +35,7 @@ extern int mp_naps;
extern int boot_cpu_id;
extern struct pcb stoppcbs[];
extern struct mtx smp_tlb_mtx;
extern int cpu_apic_ids[];
#ifdef COUNT_IPIS
extern u_long *ipi_invltlb_counts[MAXCPU];
extern u_long *ipi_invlrng_counts[MAXCPU];