mirror of
https://github.com/opnsense/src.git
synced 2026-05-28 04:12:45 -04:00
Add configuration for RISC-V ISA.
Reviewed by: emaste Sponsored by: DARPA, AFRL Sponsored by: HEIF5 Differential Revision: https://reviews.freebsd.org/D5020
This commit is contained in:
parent
60f9d31cd3
commit
47f9f6eb3a
2 changed files with 6 additions and 0 deletions
|
|
@ -253,6 +253,9 @@ typedef unsigned szind_t;
|
|||
# ifdef __powerpc__
|
||||
# define LG_QUANTUM 4
|
||||
# endif
|
||||
# ifdef __riscv__
|
||||
# define LG_QUANTUM 4
|
||||
# endif
|
||||
# ifdef __s390__
|
||||
# define LG_QUANTUM 4
|
||||
# endif
|
||||
|
|
|
|||
|
|
@ -52,6 +52,9 @@
|
|||
#elif defined(__powerpc__)
|
||||
# define LG_SIZEOF_PTR 2
|
||||
#endif
|
||||
#ifdef __riscv__
|
||||
# define LG_SIZEOF_PTR 3
|
||||
#endif
|
||||
|
||||
#ifndef JEMALLOC_TLS_MODEL
|
||||
# define JEMALLOC_TLS_MODEL /* Default. */
|
||||
|
|
|
|||
Loading…
Reference in a new issue