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Clear all ports interrupt status bits in single write. Clearing one by one

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causes additional MSIs messages sent if several ports asked for attention
same time. Time window before clearing is not important, as these interrupts
are level triggered by interrupt source.
This commit is contained in:
Alexander Motin 2009-12-21 21:27:56 +00:00
parent 28df1e77ee
commit 45e1aff18a
1 changed files with 6 additions and 8 deletions
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14
sys/dev/ahci/ahci.c
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@ -596,20 +596,18 @@ ahci_intr(void *data)
unit = irq->r_irq_rid - 1;
is = ATA_INL(ctlr->r_mem, AHCI_IS);
}
/* Some controllers have edge triggered IS. */
if (ctlr->quirks & AHCI_Q_EDGEIS)
ATA_OUTL(ctlr->r_mem, AHCI_IS, is);
for (; unit < ctlr->channels; unit++) {
if ((is & (1 << unit)) != 0 &&
(arg = ctlr->interrupt[unit].argument)) {
if (ctlr->quirks & AHCI_Q_EDGEIS) {
/* Some controller have edge triggered IS. */
ATA_OUTL(ctlr->r_mem, AHCI_IS, 1 << unit);
ctlr->interrupt[unit].function(arg);
} else {
/* but AHCI declares level triggered IS. */
ctlr->interrupt[unit].function(arg);
ATA_OUTL(ctlr->r_mem, AHCI_IS, 1 << unit);
}
}
}
/* AHCI declares level triggered IS. */
if (!(ctlr->quirks & AHCI_Q_EDGEIS))
ATA_OUTL(ctlr->r_mem, AHCI_IS, is);
}
/*