From 419146d94400d9419d7561626d2cce2ed6ca372b Mon Sep 17 00:00:00 2001
From: Bill Paul <wpaul@FreeBSD.org>
Date: Fri, 19 Jan 2001 23:55:07 +0000
Subject: [PATCH] Bug fixes that I've put together while working on a project
 in the office:

if_vr: handle the case where vr_encap() returns failure: bust out of the
       packet sending loop instead of panicking. Also add some missing
       newlines to some printf()s.

if_dc: The miibus_read and miibus_write methods keep swapping in and
       out of MII mode by fiddling with CSR6 for cards with MII PHYs.
       This is a hack to support the original Macronix 98713 card which
       has built-in NWAY that uses an MII-like management interface
       even though it uses serial transceivers. Conditionalize this
       so that we only do this on 98713 chips, since it does bad things
       to genuine tulip chips (and maybe other clones).
---
 sys/dev/dc/if_dc.c | 18 ++++++++++++------
 sys/dev/vr/if_vr.c | 10 +++++++---
 sys/pci/if_dc.c    | 18 ++++++++++++------
 sys/pci/if_vr.c    | 10 +++++++---
 4 files changed, 38 insertions(+), 18 deletions(-)

diff --git a/sys/dev/dc/if_dc.c b/sys/dev/dc/if_dc.c
index 3b5e91ad542..c27a45e823c 100644
--- a/sys/dev/dc/if_dc.c
+++ b/sys/dev/dc/if_dc.c
@@ -799,10 +799,13 @@ static int dc_miibus_readreg(dev, phy, reg)
 
 	frame.mii_phyaddr = phy;
 	frame.mii_regaddr = reg;
-	phy_reg = CSR_READ_4(sc, DC_NETCFG);
-	CSR_WRITE_4(sc, DC_NETCFG, phy_reg & ~DC_NETCFG_PORTSEL);
+	if (sc->dc_type == DC_TYPE_98713) {
+		phy_reg = CSR_READ_4(sc, DC_NETCFG);
+		CSR_WRITE_4(sc, DC_NETCFG, phy_reg & ~DC_NETCFG_PORTSEL);
+	}
 	dc_mii_readreg(sc, &frame);
-	CSR_WRITE_4(sc, DC_NETCFG, phy_reg);
+	if (sc->dc_type == DC_TYPE_98713)
+		CSR_WRITE_4(sc, DC_NETCFG, phy_reg);
 
 	return(frame.mii_data);
 }
@@ -869,10 +872,13 @@ static int dc_miibus_writereg(dev, phy, reg, data)
 	frame.mii_regaddr = reg;
 	frame.mii_data = data;
 
-	phy_reg = CSR_READ_4(sc, DC_NETCFG);
-	CSR_WRITE_4(sc, DC_NETCFG, phy_reg & ~DC_NETCFG_PORTSEL);
+	if (sc->dc_type == DC_TYPE_98713) {
+		phy_reg = CSR_READ_4(sc, DC_NETCFG);
+		CSR_WRITE_4(sc, DC_NETCFG, phy_reg & ~DC_NETCFG_PORTSEL);
+	}
 	dc_mii_writereg(sc, &frame);
-	CSR_WRITE_4(sc, DC_NETCFG, phy_reg);
+	if (sc->dc_type == DC_TYPE_98713)
+		CSR_WRITE_4(sc, DC_NETCFG, phy_reg);
 
 	return(0);
 }
diff --git a/sys/dev/vr/if_vr.c b/sys/dev/vr/if_vr.c
index 7c3729f8943..662e7be3456 100644
--- a/sys/dev/vr/if_vr.c
+++ b/sys/dev/vr/if_vr.c
@@ -1262,14 +1262,14 @@ static int vr_encap(sc, c, m_head)
 
 		MGETHDR(m_new, M_DONTWAIT, MT_DATA);
 		if (m_new == NULL) {
-			printf("vr%d: no memory for tx list", sc->vr_unit);
+			printf("vr%d: no memory for tx list\n", sc->vr_unit);
 			return(1);
 		}
 		if (m_head->m_pkthdr.len > MHLEN) {
 			MCLGET(m_new, M_DONTWAIT);
 			if (!(m_new->m_flags & M_EXT)) {
 				m_freem(m_new);
-				printf("vr%d: no memory for tx list",
+				printf("vr%d: no memory for tx list\n",
 						sc->vr_unit);
 				return(1);
 			}
@@ -1346,7 +1346,11 @@ static void vr_start(ifp)
 		sc->vr_cdata.vr_tx_free = cur_tx->vr_nextdesc;
 
 		/* Pack the data into the descriptor. */
-		vr_encap(sc, cur_tx, m_head);
+		if (vr_encap(sc, cur_tx, m_head)) {
+			IF_PREPEND(&ifp->if_snd, m_head);
+			cur_tx = NULL;
+			break;
+		}
 
 		if (cur_tx != start_tx)
 			VR_TXOWN(cur_tx) = VR_TXSTAT_OWN;
diff --git a/sys/pci/if_dc.c b/sys/pci/if_dc.c
index 3b5e91ad542..c27a45e823c 100644
--- a/sys/pci/if_dc.c
+++ b/sys/pci/if_dc.c
@@ -799,10 +799,13 @@ static int dc_miibus_readreg(dev, phy, reg)
 
 	frame.mii_phyaddr = phy;
 	frame.mii_regaddr = reg;
-	phy_reg = CSR_READ_4(sc, DC_NETCFG);
-	CSR_WRITE_4(sc, DC_NETCFG, phy_reg & ~DC_NETCFG_PORTSEL);
+	if (sc->dc_type == DC_TYPE_98713) {
+		phy_reg = CSR_READ_4(sc, DC_NETCFG);
+		CSR_WRITE_4(sc, DC_NETCFG, phy_reg & ~DC_NETCFG_PORTSEL);
+	}
 	dc_mii_readreg(sc, &frame);
-	CSR_WRITE_4(sc, DC_NETCFG, phy_reg);
+	if (sc->dc_type == DC_TYPE_98713)
+		CSR_WRITE_4(sc, DC_NETCFG, phy_reg);
 
 	return(frame.mii_data);
 }
@@ -869,10 +872,13 @@ static int dc_miibus_writereg(dev, phy, reg, data)
 	frame.mii_regaddr = reg;
 	frame.mii_data = data;
 
-	phy_reg = CSR_READ_4(sc, DC_NETCFG);
-	CSR_WRITE_4(sc, DC_NETCFG, phy_reg & ~DC_NETCFG_PORTSEL);
+	if (sc->dc_type == DC_TYPE_98713) {
+		phy_reg = CSR_READ_4(sc, DC_NETCFG);
+		CSR_WRITE_4(sc, DC_NETCFG, phy_reg & ~DC_NETCFG_PORTSEL);
+	}
 	dc_mii_writereg(sc, &frame);
-	CSR_WRITE_4(sc, DC_NETCFG, phy_reg);
+	if (sc->dc_type == DC_TYPE_98713)
+		CSR_WRITE_4(sc, DC_NETCFG, phy_reg);
 
 	return(0);
 }
diff --git a/sys/pci/if_vr.c b/sys/pci/if_vr.c
index 7c3729f8943..662e7be3456 100644
--- a/sys/pci/if_vr.c
+++ b/sys/pci/if_vr.c
@@ -1262,14 +1262,14 @@ static int vr_encap(sc, c, m_head)
 
 		MGETHDR(m_new, M_DONTWAIT, MT_DATA);
 		if (m_new == NULL) {
-			printf("vr%d: no memory for tx list", sc->vr_unit);
+			printf("vr%d: no memory for tx list\n", sc->vr_unit);
 			return(1);
 		}
 		if (m_head->m_pkthdr.len > MHLEN) {
 			MCLGET(m_new, M_DONTWAIT);
 			if (!(m_new->m_flags & M_EXT)) {
 				m_freem(m_new);
-				printf("vr%d: no memory for tx list",
+				printf("vr%d: no memory for tx list\n",
 						sc->vr_unit);
 				return(1);
 			}
@@ -1346,7 +1346,11 @@ static void vr_start(ifp)
 		sc->vr_cdata.vr_tx_free = cur_tx->vr_nextdesc;
 
 		/* Pack the data into the descriptor. */
-		vr_encap(sc, cur_tx, m_head);
+		if (vr_encap(sc, cur_tx, m_head)) {
+			IF_PREPEND(&ifp->if_snd, m_head);
+			cur_tx = NULL;
+			break;
+		}
 
 		if (cur_tx != start_tx)
 			VR_TXOWN(cur_tx) = VR_TXSTAT_OWN;