From 40e88de6c39ff86fd116e4de1be60cf0aa48dc74 Mon Sep 17 00:00:00 2001 From: Matt Jacob Date: Tue, 27 Jun 2000 19:15:43 +0000 Subject: [PATCH] Add mailbox bitmask macros (numbers of available mailbox registers based upon Qlogic chip type). Define maximum mailboxes. Add INT_PENDING_MASK macro. Change mailbox offset macro name. --- sys/dev/isp/ispreg.h | 10 +++++++++- 1 file changed, 9 insertions(+), 1 deletion(-) diff --git a/sys/dev/isp/ispreg.h b/sys/dev/isp/ispreg.h index 070ee84e8ee..44a8e1d9a75 100644 --- a/sys/dev/isp/ispreg.h +++ b/sys/dev/isp/ispreg.h @@ -225,6 +225,9 @@ #define INT_PENDING(isp, isr) (IS_FC(isp)? \ ((isr & BIU2100_ISR_RISC_INT) != 0) : ((isr & BIU_ISR_RISC_INT) != 0)) +#define INT_PENDING_MASK(isp) \ + (IS_FC(isp)? BIU2100_ISR_RISC_INT: BIU_ISR_RISC_INT) + /* BUS SEMAPHORE REGISTER */ #define BIU_SEMA_STATUS 0x0002 /* Semaphore Status Bit */ #define BIU_SEMA_LOCK 0x0001 /* Semaphore Lock Bit */ @@ -337,10 +340,15 @@ #define OUTMAILBOX6 (MBOX_BLOCK+0xC) #define OUTMAILBOX7 (MBOX_BLOCK+0xE) -#define OMBOX_OFFN(n) (MBOX_BLOCK + (n * 2)) +#define MBOX_OFF(n) (MBOX_BLOCK + ((n) << 1)) #define NMBOX(isp) \ (((((isp)->isp_type & ISP_HA_SCSI) >= ISP_HA_SCSI_1040A) || \ ((isp)->isp_type & ISP_HA_FC))? 8 : 6) +#define NMBOX_BMASK(isp) \ + (((((isp)->isp_type & ISP_HA_SCSI) >= ISP_HA_SCSI_1040A) || \ + ((isp)->isp_type & ISP_HA_FC))? 0xff : 0x3f) + +#define MAX_MAILBOX 8 /* * SXP Block Register Offsets