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cxgbe: catch up with the latest hardware-related definitions.
Obtained from: Chelsio Communications Sponsored by: Chelsio Communications
This commit is contained in:
Navdeep Parhar
parent
bfe2514a08
commit
40bf7442fa
8 changed files with 21237 additions and 86 deletions
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@ -813,7 +813,7 @@ struct adapter {
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struct mtx regwin_lock; /* for indirect reads and memory windows */
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an_handler_t an_handler __aligned(CACHE_LINE_SIZE);
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fw_msg_handler_t fw_msg_handler[5]; /* NUM_FW6_TYPES */
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fw_msg_handler_t fw_msg_handler[7]; /* NUM_FW6_TYPES */
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cpl_handler_t cpl_handler[0xef]; /* NUM_CPL_CMDS */
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#ifdef INVARIANTS
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@ -47,6 +47,7 @@ enum { MEM_EDC0, MEM_EDC1, MEM_MC, MEM_MC0 = MEM_MC, MEM_MC1 };
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enum {
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MEMWIN0_APERTURE = 2048,
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MEMWIN0_BASE = 0x1b800,
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MEMWIN1_APERTURE = 32768,
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MEMWIN1_BASE = 0x28000,
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@ -1,5 +1,5 @@
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/*-
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* Copyright (c) 2011 Chelsio Communications, Inc.
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* Copyright (c) 2011, 2016 Chelsio Communications, Inc.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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@ -265,6 +265,12 @@ enum {
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FLASH_CFG_START = FLASH_START(FLASH_CFG_START_SEC),
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FLASH_CFG_MAX_SIZE = FLASH_MAX_SIZE(FLASH_CFG_NSECS),
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/*
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* We don't support FLASH devices which can't support the full
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* standard set of sections which we need for normal operations.
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*/
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FLASH_MIN_SIZE = FLASH_CFG_START + FLASH_CFG_MAX_SIZE,
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/*
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* Sectors 32-63 are reserved for FLASH failover.
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*/
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@ -273,4 +279,9 @@ enum {
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#undef FLASH_START
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#undef FLASH_MAX_SIZE
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#define S_SGE_TIMESTAMP 0
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#define M_SGE_TIMESTAMP 0xfffffffffffffffULL
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#define V_SGE_TIMESTAMP(x) ((__u64)(x) << S_SGE_TIMESTAMP)
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#define G_SGE_TIMESTAMP(x) (((__u64)(x) >> S_SGE_TIMESTAMP) & M_SGE_TIMESTAMP)
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#endif /* __T4_HW_H */
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@ -1,5 +1,5 @@
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/*-
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* Copyright (c) 2011 Chelsio Communications, Inc.
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* Copyright (c) 2011, 2016 Chelsio Communications, Inc.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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@ -55,8 +55,9 @@ enum {
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CPL_BARRIER = 0x18,
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CPL_TID_RELEASE = 0x1A,
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CPL_TAG_READ_REQ = 0x1B,
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CPL_SRQ_TABLE_REQ = 0x1C,
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CPL_TX_PKT_FSO = 0x1E,
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CPL_TX_PKT_ISO = 0x1F,
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CPL_TX_DATA_ISO = 0x1F,
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CPL_CLOSE_LISTSRV_RPL = 0x20,
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CPL_ERROR = 0x21,
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@ -97,7 +98,7 @@ enum {
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CPL_RX_DATA_DDP = 0x42,
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CPL_SMT_READ_RPL = 0x43,
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CPL_PASS_ACCEPT_REQ = 0x44,
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CPL_RX2TX_PKT = 0x45,
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CPL_RX_ISCSI_CMP = 0x45,
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CPL_RX_FCOE_DDP = 0x46,
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CPL_FCOE_HDR = 0x47,
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CPL_T5_TRACE_PKT = 0x48,
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@ -124,6 +125,7 @@ enum {
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CPL_RDMA_ATOMIC_RPL = 0xAB,
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CPL_RDMA_IMM_DATA = 0xAC,
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CPL_RDMA_IMM_DATA_SE = 0xAD,
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CPL_RX_MPS_PKT = 0xAF,
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CPL_TRACE_PKT = 0xB0,
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CPL_RX2TX_DATA = 0xB1,
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@ -133,9 +135,11 @@ enum {
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CPL_FW4_MSG = 0xC0,
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CPL_FW4_PLD = 0xC1,
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CPL_FW4_ACK = 0xC3,
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CPL_SRQ_TABLE_RPL = 0xCC,
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CPL_FW6_MSG = 0xE0,
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CPL_FW6_PLD = 0xE1,
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CPL_TX_TNL_LSO = 0xEC,
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CPL_TX_PKT_LSO = 0xED,
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CPL_TX_PKT_XT = 0xEE,
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@ -145,6 +149,7 @@ enum {
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enum CPL_error {
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CPL_ERR_NONE = 0,
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CPL_ERR_TCAM_PARITY = 1,
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CPL_ERR_TCAM_MISS = 2,
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CPL_ERR_TCAM_FULL = 3,
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CPL_ERR_BAD_LENGTH = 15,
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CPL_ERR_BAD_ROUTE = 18,
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@ -164,8 +169,24 @@ enum CPL_error {
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CPL_ERR_WAIT_ARP_RPL = 41,
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CPL_ERR_ABORT_FAILED = 42,
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CPL_ERR_IWARP_FLM = 50,
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CPL_CONTAINS_READ_RPL = 60,
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CPL_CONTAINS_WRITE_RPL = 61,
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};
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/*
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* Some of the error codes above implicitly indicate that there is no TID
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* allocated with the result of an ACT_OPEN. We use this predicate to make
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* that explicit.
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*/
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static inline int act_open_has_tid(int status)
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{
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return (status != CPL_ERR_TCAM_PARITY &&
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status != CPL_ERR_TCAM_MISS &&
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status != CPL_ERR_TCAM_FULL &&
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status != CPL_ERR_CONN_EXIST_SYNRECV &&
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status != CPL_ERR_CONN_EXIST);
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}
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enum {
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CPL_CONN_POLICY_AUTO = 0,
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CPL_CONN_POLICY_ASK = 1,
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@ -337,6 +358,12 @@ struct rss_header {
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#define M_QNUM 0xFFFF
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#define G_QNUM(x) (((x) >> S_QNUM) & M_QNUM)
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#if defined(RSS_HDR_VLD) || defined(CHELSIO_FW)
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# define RSS_HDR struct rss_header rss_hdr;
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#else
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# define RSS_HDR
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#endif
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#ifndef CHELSIO_FW
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struct work_request_hdr {
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__be32 wr_hi;
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@ -358,11 +385,9 @@ struct work_request_hdr {
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# define WR_HDR struct work_request_hdr wr
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# define WR_HDR_SIZE sizeof(struct work_request_hdr)
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# define RSS_HDR
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#else
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# define WR_HDR
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# define WR_HDR_SIZE 0
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# define RSS_HDR struct rss_header rss_hdr;
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#endif
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/* option 0 fields */
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@ -480,6 +505,11 @@ struct work_request_hdr {
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#define V_CONN_POLICY(x) ((x) << S_CONN_POLICY)
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#define G_CONN_POLICY(x) (((x) >> S_CONN_POLICY) & M_CONN_POLICY)
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#define S_T5_FILT_INFO 24
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#define M_T5_FILT_INFO 0xffffffffffULL
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#define V_T5_FILT_INFO(x) ((x) << S_T5_FILT_INFO)
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#define G_T5_FILT_INFO(x) (((x) >> S_T5_FILT_INFO) & M_T5_FILT_INFO)
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#define S_FILT_INFO 28
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#define M_FILT_INFO 0xfffffffffULL
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#define V_FILT_INFO(x) ((x) << S_FILT_INFO)
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@ -518,6 +548,10 @@ struct work_request_hdr {
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#define V_CONG_CNTRL_VALID(x) ((x) << S_CONG_CNTRL_VALID)
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#define F_CONG_CNTRL_VALID V_CONG_CNTRL_VALID(1U)
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#define S_T5_ISS 18
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#define V_T5_ISS(x) ((x) << S_T5_ISS)
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#define F_T5_ISS V_T5_ISS(1U)
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#define S_PACE_VALID 19
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#define V_PACE_VALID(x) ((x) << S_PACE_VALID)
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#define F_PACE_VALID V_PACE_VALID(1U)
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@ -617,11 +651,30 @@ struct cpl_pass_establish {
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#define G_PASS_OPEN_TOS(x) (((x) >> S_PASS_OPEN_TOS) & M_PASS_OPEN_TOS)
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/* cpl_pass_establish.tcp_opt fields (also applies to act_open_establish) */
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#define G_TCPOPT_WSCALE_OK(x) (((x) >> 5) & 1)
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#define G_TCPOPT_SACK(x) (((x) >> 6) & 1)
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#define G_TCPOPT_TSTAMP(x) (((x) >> 7) & 1)
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#define G_TCPOPT_SND_WSCALE(x) (((x) >> 8) & 0xf)
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#define G_TCPOPT_MSS(x) (((x) >> 12) & 0xf)
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#define S_TCPOPT_WSCALE_OK 5
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#define M_TCPOPT_WSCALE_OK 0x1
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#define V_TCPOPT_WSCALE_OK(x) ((x) << S_TCPOPT_WSCALE_OK)
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#define G_TCPOPT_WSCALE_OK(x) (((x) >> S_TCPOPT_WSCALE_OK) & M_TCPOPT_WSCALE_OK)
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#define S_TCPOPT_SACK 6
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#define M_TCPOPT_SACK 0x1
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#define V_TCPOPT_SACK(x) ((x) << S_TCPOPT_SACK)
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#define G_TCPOPT_SACK(x) (((x) >> S_TCPOPT_SACK) & M_TCPOPT_SACK)
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#define S_TCPOPT_TSTAMP 7
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#define M_TCPOPT_TSTAMP 0x1
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#define V_TCPOPT_TSTAMP(x) ((x) << S_TCPOPT_TSTAMP)
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#define G_TCPOPT_TSTAMP(x) (((x) >> S_TCPOPT_TSTAMP) & M_TCPOPT_TSTAMP)
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#define S_TCPOPT_SND_WSCALE 8
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#define M_TCPOPT_SND_WSCALE 0xF
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#define V_TCPOPT_SND_WSCALE(x) ((x) << S_TCPOPT_SND_WSCALE)
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#define G_TCPOPT_SND_WSCALE(x) (((x) >> S_TCPOPT_SND_WSCALE) & M_TCPOPT_SND_WSCALE)
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#define S_TCPOPT_MSS 12
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#define M_TCPOPT_MSS 0xF
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#define V_TCPOPT_MSS(x) ((x) << S_TCPOPT_MSS)
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#define G_TCPOPT_MSS(x) (((x) >> S_TCPOPT_MSS) & M_TCPOPT_MSS)
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struct cpl_pass_accept_req {
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RSS_HDR
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@ -646,16 +699,29 @@ struct cpl_pass_accept_req {
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#define V_TCP_HDR_LEN(x) ((x) << S_TCP_HDR_LEN)
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#define G_TCP_HDR_LEN(x) (((x) >> S_TCP_HDR_LEN) & M_TCP_HDR_LEN)
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#define S_T6_TCP_HDR_LEN 8
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#define V_T6_TCP_HDR_LEN(x) ((x) << S_T6_TCP_HDR_LEN)
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#define G_T6_TCP_HDR_LEN(x) (((x) >> S_T6_TCP_HDR_LEN) & M_TCP_HDR_LEN)
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#define S_IP_HDR_LEN 16
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#define M_IP_HDR_LEN 0x3FF
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#define V_IP_HDR_LEN(x) ((x) << S_IP_HDR_LEN)
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#define G_IP_HDR_LEN(x) (((x) >> S_IP_HDR_LEN) & M_IP_HDR_LEN)
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#define S_T6_IP_HDR_LEN 14
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#define V_T6_IP_HDR_LEN(x) ((x) << S_T6_IP_HDR_LEN)
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#define G_T6_IP_HDR_LEN(x) (((x) >> S_T6_IP_HDR_LEN) & M_IP_HDR_LEN)
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#define S_ETH_HDR_LEN 26
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#define M_ETH_HDR_LEN 0x3F
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#define V_ETH_HDR_LEN(x) ((x) << S_ETH_HDR_LEN)
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#define G_ETH_HDR_LEN(x) (((x) >> S_ETH_HDR_LEN) & M_ETH_HDR_LEN)
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#define S_T6_ETH_HDR_LEN 24
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#define M_T6_ETH_HDR_LEN 0xFF
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#define V_T6_ETH_HDR_LEN(x) ((x) << S_T6_ETH_HDR_LEN)
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#define G_T6_ETH_HDR_LEN(x) (((x) >> S_T6_ETH_HDR_LEN) & M_T6_ETH_HDR_LEN)
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/* cpl_pass_accept_req.l2info fields */
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#define S_SYN_MAC_IDX 0
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#define M_SYN_MAC_IDX 0x1FF
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@ -684,7 +750,10 @@ struct cpl_t5_pass_accept_rpl {
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__be32 opt2;
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__be64 opt0;
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__be32 iss;
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__be32 rsvd;
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union {
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__be32 rsvd; /* T5 */
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__be32 opt3; /* T6 */
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} u;
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};
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struct cpl_act_open_req {
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@ -716,6 +785,26 @@ struct cpl_t5_act_open_req {
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__be64 params;
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};
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struct cpl_t6_act_open_req {
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WR_HDR;
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union opcode_tid ot;
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__be16 local_port;
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__be16 peer_port;
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__be32 local_ip;
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__be32 peer_ip;
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__be64 opt0;
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__be32 iss;
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__be32 opt2;
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__be64 params;
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__be32 rsvd2;
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__be32 opt3;
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};
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/* cpl_{t5,t6}_act_open_req.params field */
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#define S_AOPEN_FCOEMASK 0
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#define V_AOPEN_FCOEMASK(x) ((x) << S_AOPEN_FCOEMASK)
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#define F_AOPEN_FCOEMASK V_AOPEN_FCOEMASK(1U)
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struct cpl_act_open_req6 {
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WR_HDR;
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union opcode_tid ot;
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@ -745,6 +834,23 @@ struct cpl_t5_act_open_req6 {
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__be64 params;
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};
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struct cpl_t6_act_open_req6 {
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WR_HDR;
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union opcode_tid ot;
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__be16 local_port;
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__be16 peer_port;
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__be64 local_ip_hi;
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__be64 local_ip_lo;
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__be64 peer_ip_hi;
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__be64 peer_ip_lo;
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__be64 opt0;
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__be32 iss;
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__be32 opt2;
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__be64 params;
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__be32 rsvd2;
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__be32 opt3;
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};
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struct cpl_act_open_rpl {
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RSS_HDR
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union opcode_tid ot;
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@ -887,6 +993,11 @@ struct cpl_abort_req_rss {
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__u8 status;
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};
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/* cpl_abort_req status command code in case of T6,
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* bit[0] specifies whether to send RST (0) to remote peer or suppress it (1)
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* bit[1] indicates ABORT_REQ was sent after a CLOSE_CON_REQ
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* bit[2] specifies whether to disable the mmgr (1) or not (0)
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*/
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struct cpl_abort_req {
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WR_HDR;
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union opcode_tid ot;
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@ -978,10 +1089,14 @@ struct cpl_tx_data {
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#define G_TX_ULP_SUBMODE(x) (((x) >> S_TX_ULP_SUBMODE) & M_TX_ULP_SUBMODE)
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#define S_TX_ULP_MODE 10
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#define M_TX_ULP_MODE 0xF
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#define M_TX_ULP_MODE 0x7
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#define V_TX_ULP_MODE(x) ((x) << S_TX_ULP_MODE)
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#define G_TX_ULP_MODE(x) (((x) >> S_TX_ULP_MODE) & M_TX_ULP_MODE)
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#define S_TX_FORCE 13
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#define V_TX_FORCE(x) ((x) << S_TX_FORCE)
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#define F_TX_FORCE V_TX_FORCE(1U)
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#define S_TX_SHOVE 14
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#define V_TX_SHOVE(x) ((x) << S_TX_SHOVE)
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#define F_TX_SHOVE V_TX_SHOVE(1U)
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@ -1006,6 +1121,10 @@ struct cpl_tx_data {
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#define V_TX_TNL(x) ((x) << S_TX_TNL)
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#define F_TX_TNL V_TX_TNL(1U)
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#define S_T6_TX_FORCE 20
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#define V_T6_TX_FORCE(x) ((x) << S_T6_TX_FORCE)
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#define F_T6_TX_FORCE V_T6_TX_FORCE(1U)
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/* additional tx_data_wr.flags fields */
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#define S_TX_CPU_IDX 0
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#define M_TX_CPU_IDX 0x3F
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@ -1142,6 +1261,10 @@ struct cpl_tx_pkt {
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#define V_TXPKT_IPHDR_LEN(x) ((__u64)(x) << S_TXPKT_IPHDR_LEN)
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#define G_TXPKT_IPHDR_LEN(x) (((x) >> S_TXPKT_IPHDR_LEN) & M_TXPKT_IPHDR_LEN)
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#define M_T6_TXPKT_IPHDR_LEN 0xFFF
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#define G_T6_TXPKT_IPHDR_LEN(x) \
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(((x) >> S_TXPKT_IPHDR_LEN) & M_T6_TXPKT_IPHDR_LEN)
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#define S_TXPKT_CSUM_LOC 30
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#define M_TXPKT_CSUM_LOC 0x3FF
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#define V_TXPKT_CSUM_LOC(x) ((__u64)(x) << S_TXPKT_CSUM_LOC)
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@ -1152,6 +1275,12 @@ struct cpl_tx_pkt {
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#define V_TXPKT_ETHHDR_LEN(x) ((__u64)(x) << S_TXPKT_ETHHDR_LEN)
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#define G_TXPKT_ETHHDR_LEN(x) (((x) >> S_TXPKT_ETHHDR_LEN) & M_TXPKT_ETHHDR_LEN)
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#define S_T6_TXPKT_ETHHDR_LEN 32
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#define M_T6_TXPKT_ETHHDR_LEN 0xFF
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#define V_T6_TXPKT_ETHHDR_LEN(x) ((__u64)(x) << S_T6_TXPKT_ETHHDR_LEN)
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#define G_T6_TXPKT_ETHHDR_LEN(x) \
|
||||
(((x) >> S_T6_TXPKT_ETHHDR_LEN) & M_T6_TXPKT_ETHHDR_LEN)
|
||||
|
||||
#define S_TXPKT_CSUM_TYPE 40
|
||||
#define M_TXPKT_CSUM_TYPE 0xF
|
||||
#define V_TXPKT_CSUM_TYPE(x) ((__u64)(x) << S_TXPKT_CSUM_TYPE)
|
||||
|
|
@ -1296,38 +1425,83 @@ struct cpl_iscsi_hdr_no_rss {
|
|||
};
|
||||
|
||||
struct cpl_tx_data_iso {
|
||||
WR_HDR;
|
||||
__be32 iso_ctrl;
|
||||
__u8 rsvd;
|
||||
__be32 op_to_scsi;
|
||||
__u8 reserved1;
|
||||
__u8 ahs_len;
|
||||
__be16 mss;
|
||||
__be16 mpdu;
|
||||
__be32 burst_size;
|
||||
__be32 len;
|
||||
__be32 reserved2_seglen_offset;
|
||||
__be32 datasn_offset;
|
||||
__be32 buffer_offset;
|
||||
__be32 reserved3;
|
||||
|
||||
/* encapsulated CPL_TX_DATA follows here */
|
||||
};
|
||||
|
||||
/* cpl_tx_data_iso.iso_ctrl fields different from cpl_tx_pkt_lso.lso_ctrl */
|
||||
#define S_ISO_CPLHDR_LEN 18
|
||||
#define M_ISO_CPLHDR_LEN 0xF
|
||||
#define V_ISO_CPLHDR_LEN(x) ((x) << S_ISO_CPLHDR_LEN)
|
||||
#define G_ISO_CPLHDR_LEN(x) (((x) >> S_ISO_CPLHDR_LEN) & M_ISO_CPLHDR_LEN)
|
||||
/* cpl_tx_data_iso.op_to_scsi fields */
|
||||
#define S_CPL_TX_DATA_ISO_OP 24
|
||||
#define M_CPL_TX_DATA_ISO_OP 0xff
|
||||
#define V_CPL_TX_DATA_ISO_OP(x) ((x) << S_CPL_TX_DATA_ISO_OP)
|
||||
#define G_CPL_TX_DATA_ISO_OP(x) \
|
||||
(((x) >> S_CPL_TX_DATA_ISO_OP) & M_CPL_TX_DATA_ISO_OP)
|
||||
|
||||
#define S_ISO_HDR_CRC 17
|
||||
#define V_ISO_HDR_CRC(x) ((x) << S_ISO_HDR_CRC)
|
||||
#define F_ISO_HDR_CRC V_ISO_HDR_CRC(1U)
|
||||
#define S_CPL_TX_DATA_ISO_FIRST 23
|
||||
#define M_CPL_TX_DATA_ISO_FIRST 0x1
|
||||
#define V_CPL_TX_DATA_ISO_FIRST(x) ((x) << S_CPL_TX_DATA_ISO_FIRST)
|
||||
#define G_CPL_TX_DATA_ISO_FIRST(x) \
|
||||
(((x) >> S_CPL_TX_DATA_ISO_FIRST) & M_CPL_TX_DATA_ISO_FIRST)
|
||||
#define F_CPL_TX_DATA_ISO_FIRST V_CPL_TX_DATA_ISO_FIRST(1U)
|
||||
|
||||
#define S_ISO_DATA_CRC 16
|
||||
#define V_ISO_DATA_CRC(x) ((x) << S_ISO_DATA_CRC)
|
||||
#define F_ISO_DATA_CRC V_ISO_DATA_CRC(1U)
|
||||
#define S_CPL_TX_DATA_ISO_LAST 22
|
||||
#define M_CPL_TX_DATA_ISO_LAST 0x1
|
||||
#define V_CPL_TX_DATA_ISO_LAST(x) ((x) << S_CPL_TX_DATA_ISO_LAST)
|
||||
#define G_CPL_TX_DATA_ISO_LAST(x) \
|
||||
(((x) >> S_CPL_TX_DATA_ISO_LAST) & M_CPL_TX_DATA_ISO_LAST)
|
||||
#define F_CPL_TX_DATA_ISO_LAST V_CPL_TX_DATA_ISO_LAST(1U)
|
||||
|
||||
#define S_ISO_IMD_DATA_EN 15
|
||||
#define V_ISO_IMD_DATA_EN(x) ((x) << S_ISO_IMD_DATA_EN)
|
||||
#define F_ISO_IMD_DATA_EN V_ISO_IMD_DATA_EN(1U)
|
||||
#define S_CPL_TX_DATA_ISO_CPLHDRLEN 21
|
||||
#define M_CPL_TX_DATA_ISO_CPLHDRLEN 0x1
|
||||
#define V_CPL_TX_DATA_ISO_CPLHDRLEN(x) ((x) << S_CPL_TX_DATA_ISO_CPLHDRLEN)
|
||||
#define G_CPL_TX_DATA_ISO_CPLHDRLEN(x) \
|
||||
(((x) >> S_CPL_TX_DATA_ISO_CPLHDRLEN) & M_CPL_TX_DATA_ISO_CPLHDRLEN)
|
||||
#define F_CPL_TX_DATA_ISO_CPLHDRLEN V_CPL_TX_DATA_ISO_CPLHDRLEN(1U)
|
||||
|
||||
#define S_ISO_PDU_TYPE 13
|
||||
#define M_ISO_PDU_TYPE 0x3
|
||||
#define V_ISO_PDU_TYPE(x) ((x) << S_ISO_PDU_TYPE)
|
||||
#define G_ISO_PDU_TYPE(x) (((x) >> S_ISO_PDU_TYPE) & M_ISO_PDU_TYPE)
|
||||
#define S_CPL_TX_DATA_ISO_HDRCRC 20
|
||||
#define M_CPL_TX_DATA_ISO_HDRCRC 0x1
|
||||
#define V_CPL_TX_DATA_ISO_HDRCRC(x) ((x) << S_CPL_TX_DATA_ISO_HDRCRC)
|
||||
#define G_CPL_TX_DATA_ISO_HDRCRC(x) \
|
||||
(((x) >> S_CPL_TX_DATA_ISO_HDRCRC) & M_CPL_TX_DATA_ISO_HDRCRC)
|
||||
#define F_CPL_TX_DATA_ISO_HDRCRC V_CPL_TX_DATA_ISO_HDRCRC(1U)
|
||||
|
||||
#define S_CPL_TX_DATA_ISO_PLDCRC 19
|
||||
#define M_CPL_TX_DATA_ISO_PLDCRC 0x1
|
||||
#define V_CPL_TX_DATA_ISO_PLDCRC(x) ((x) << S_CPL_TX_DATA_ISO_PLDCRC)
|
||||
#define G_CPL_TX_DATA_ISO_PLDCRC(x) \
|
||||
(((x) >> S_CPL_TX_DATA_ISO_PLDCRC) & M_CPL_TX_DATA_ISO_PLDCRC)
|
||||
#define F_CPL_TX_DATA_ISO_PLDCRC V_CPL_TX_DATA_ISO_PLDCRC(1U)
|
||||
|
||||
#define S_CPL_TX_DATA_ISO_IMMEDIATE 18
|
||||
#define M_CPL_TX_DATA_ISO_IMMEDIATE 0x1
|
||||
#define V_CPL_TX_DATA_ISO_IMMEDIATE(x) ((x) << S_CPL_TX_DATA_ISO_IMMEDIATE)
|
||||
#define G_CPL_TX_DATA_ISO_IMMEDIATE(x) \
|
||||
(((x) >> S_CPL_TX_DATA_ISO_IMMEDIATE) & M_CPL_TX_DATA_ISO_IMMEDIATE)
|
||||
#define F_CPL_TX_DATA_ISO_IMMEDIATE V_CPL_TX_DATA_ISO_IMMEDIATE(1U)
|
||||
|
||||
#define S_CPL_TX_DATA_ISO_SCSI 16
|
||||
#define M_CPL_TX_DATA_ISO_SCSI 0x3
|
||||
#define V_CPL_TX_DATA_ISO_SCSI(x) ((x) << S_CPL_TX_DATA_ISO_SCSI)
|
||||
#define G_CPL_TX_DATA_ISO_SCSI(x) \
|
||||
(((x) >> S_CPL_TX_DATA_ISO_SCSI) & M_CPL_TX_DATA_ISO_SCSI)
|
||||
|
||||
/* cpl_tx_data_iso.reserved2_seglen_offset fields */
|
||||
#define S_CPL_TX_DATA_ISO_SEGLEN_OFFSET 0
|
||||
#define M_CPL_TX_DATA_ISO_SEGLEN_OFFSET 0xffffff
|
||||
#define V_CPL_TX_DATA_ISO_SEGLEN_OFFSET(x) \
|
||||
((x) << S_CPL_TX_DATA_ISO_SEGLEN_OFFSET)
|
||||
#define G_CPL_TX_DATA_ISO_SEGLEN_OFFSET(x) \
|
||||
(((x) >> S_CPL_TX_DATA_ISO_SEGLEN_OFFSET) & \
|
||||
M_CPL_TX_DATA_ISO_SEGLEN_OFFSET)
|
||||
|
||||
struct cpl_iscsi_hdr {
|
||||
RSS_HDR
|
||||
|
|
@ -1400,6 +1574,19 @@ struct cpl_fcoe_hdr {
|
|||
__be32 param;
|
||||
};
|
||||
|
||||
/* cpl_fcoe_hdr.rctl_fctl fields */
|
||||
#define S_FCOE_FCHDR_RCTL 24
|
||||
#define M_FCOE_FCHDR_RCTL 0xff
|
||||
#define V_FCOE_FCHDR_RCTL(x) ((x) << S_FCOE_FCHDR_RCTL)
|
||||
#define G_FCOE_FCHDR_RCTL(x) \
|
||||
(((x) >> S_FCOE_FCHDR_RCTL) & M_FCOE_FCHDR_RCTL)
|
||||
|
||||
#define S_FCOE_FCHDR_FCTL 0
|
||||
#define M_FCOE_FCHDR_FCTL 0xffffff
|
||||
#define V_FCOE_FCHDR_FCTL(x) ((x) << S_FCOE_FCHDR_FCTL)
|
||||
#define G_FCOE_FCHDR_FCTL(x) \
|
||||
(((x) >> S_FCOE_FCHDR_FCTL) & M_FCOE_FCHDR_FCTL)
|
||||
|
||||
struct cpl_fcoe_data {
|
||||
RSS_HDR
|
||||
union opcode_tid ot;
|
||||
|
|
@ -1527,6 +1714,19 @@ struct cpl_rx_iscsi_dif {
|
|||
__u8 rsvd1[4];
|
||||
};
|
||||
|
||||
struct cpl_rx_iscsi_cmp {
|
||||
RSS_HDR
|
||||
union opcode_tid ot;
|
||||
__be16 pdu_len_ddp;
|
||||
__be16 len;
|
||||
__be32 seq;
|
||||
__be16 urg;
|
||||
__u8 rsvd;
|
||||
__u8 status;
|
||||
__be32 ulp_crc;
|
||||
__be32 ddpvld;
|
||||
};
|
||||
|
||||
struct cpl_rx_fcoe_dif {
|
||||
RSS_HDR
|
||||
union opcode_tid ot;
|
||||
|
|
@ -1671,6 +1871,9 @@ struct cpl_rx_pkt {
|
|||
#define V_RX_T5_ETHHDR_LEN(x) ((x) << S_RX_T5_ETHHDR_LEN)
|
||||
#define G_RX_T5_ETHHDR_LEN(x) (((x) >> S_RX_T5_ETHHDR_LEN) & M_RX_T5_ETHHDR_LEN)
|
||||
|
||||
#define M_RX_T6_ETHHDR_LEN 0xFF
|
||||
#define G_RX_T6_ETHHDR_LEN(x) (((x) >> S_RX_ETHHDR_LEN) & M_RX_T6_ETHHDR_LEN)
|
||||
|
||||
#define S_RX_PKTYPE 5
|
||||
#define M_RX_PKTYPE 0x7
|
||||
#define V_RX_PKTYPE(x) ((x) << S_RX_PKTYPE)
|
||||
|
|
@ -1801,6 +2004,65 @@ struct cpl_rx_pkt {
|
|||
#define V_RXERR_PING(x) ((x) << S_RXERR_PING)
|
||||
#define F_RXERR_PING V_RXERR_PING(1U)
|
||||
|
||||
/* In T6, rx_pkt.err_vec indicates
|
||||
* RxError Error vector (16b) or
|
||||
* Encapsulating header length (8b),
|
||||
* Outer encapsulation type (2b) and
|
||||
* compressed error vector (6b) if CRxPktEnc is
|
||||
* enabled in TP_OUT_CONFIG
|
||||
*/
|
||||
|
||||
#define S_T6_COMPR_RXERR_VEC 0
|
||||
#define M_T6_COMPR_RXERR_VEC 0x3F
|
||||
#define V_T6_COMPR_RXERR_VEC(x) ((x) << S_T6_COMPR_RXERR_LEN)
|
||||
#define G_T6_COMPR_RXERR_VEC(x) \
|
||||
(((x) >> S_T6_COMPR_RXERR_VEC) & M_T6_COMPR_RXERR_VEC)
|
||||
|
||||
#define S_T6_COMPR_RXERR_MAC 0
|
||||
#define V_T6_COMPR_RXERR_MAC(x) ((x) << S_T6_COMPR_RXERR_MAC)
|
||||
#define F_T6_COMPR_RXERR_MAC V_T6_COMPR_RXERR_MAC(1U)
|
||||
|
||||
/* Logical OR of RX_ERROR_PKT_LEN, RX_ERROR_TCP_HDR_LEN
|
||||
* RX_ERROR_IP_HDR_LEN, RX_ERROR_ETH_HDR_LEN
|
||||
*/
|
||||
#define S_T6_COMPR_RXERR_LEN 1
|
||||
#define V_T6_COMPR_RXERR_LEN(x) ((x) << S_COMPR_T6_RXERR_LEN)
|
||||
#define F_T6_COMPR_RXERR_LEN V_COMPR_T6_RXERR_LEN(1U)
|
||||
|
||||
#define S_T6_COMPR_RXERR_TCP_OPT 2
|
||||
#define V_T6_COMPR_RXERR_TCP_OPT(x) ((x) << S_T6_COMPR_RXERR_TCP_OPT)
|
||||
#define F_T6_COMPR_RXERR_TCP_OPT V_T6_COMPR_RXERR_TCP_OPT(1U)
|
||||
|
||||
#define S_T6_COMPR_RXERR_IPV6_EXT 3
|
||||
#define V_T6_COMPR_RXERR_IPV6_EXT(x) ((x) << S_T6_COMPR_RXERR_IPV6_EXT)
|
||||
#define F_T6_COMPR_RXERR_IPV6_EXT V_T6_COMPR_RXERR_IPV6_EXT(1U)
|
||||
|
||||
/* Logical OR of RX_ERROR_CSUM, RX_ERROR_CSIP */
|
||||
#define S_T6_COMPR_RXERR_SUM 4
|
||||
#define V_T6_COMPR_RXERR_SUM(x) ((x) << S_T6_COMPR_RXERR_SUM)
|
||||
#define F_T6_COMPR_RXERR_SUM V_T6_COMPR_RXERR_SUM(1U)
|
||||
|
||||
/* Logical OR of RX_ERROR_FPMA, RX_ERROR_PING_DROP,
|
||||
* RX_ERROR_ATTACK, RX_ERROR_FRAG,RX_ERROR_IPVERSION
|
||||
*/
|
||||
#define S_T6_COMPR_RXERR_MISC 5
|
||||
#define V_T6_COMPR_RXERR_MISC(x) ((x) << S_T6_COMPR_RXERR_MISC)
|
||||
#define F_T6_COMPR_RXERR_MISC V_T6_COMPR_RXERR_MISC(1U)
|
||||
|
||||
#define S_T6_RX_TNL_TYPE 6
|
||||
#define M_T6_RX_TNL_TYPE 0x3
|
||||
#define V_T6_RX_TNL_TYPE(x) ((x) << S_T6_RX_TNL_TYPE)
|
||||
#define G_T6_RX_TNL_TYPE(x) (((x) >> S_T6_RX_TNL_TYPE) & M_T6_RX_TNL_TYPE)
|
||||
|
||||
#define RX_PKT_TNL_TYPE_NVGRE 1
|
||||
#define RX_PKT_TNL_TYPE_VXLAN 2
|
||||
#define RX_PKT_TNL_TYPE_GENEVE 3
|
||||
|
||||
#define S_T6_RX_TNLHDR_LEN 8
|
||||
#define M_T6_RX_TNLHDR_LEN 0xFF
|
||||
#define V_T6_RX_TNLHDR_LEN(x) ((x) << S_T6_RX_TNLHDR_LEN)
|
||||
#define G_T6_RX_TNLHDR_LEN(x) (((x) >> S_T6_RX_TNLHDR_LEN) & M_T6_RX_TNLHDR_LEN)
|
||||
|
||||
struct cpl_trace_pkt {
|
||||
RSS_HDR
|
||||
__u8 opcode;
|
||||
|
|
@ -1996,6 +2258,51 @@ struct cpl_l2t_read_rpl {
|
|||
__u8 dst_mac[6];
|
||||
};
|
||||
|
||||
struct cpl_srq_table_req {
|
||||
WR_HDR;
|
||||
union opcode_tid ot;
|
||||
__u8 status;
|
||||
__u8 rsvd[2];
|
||||
__u8 idx;
|
||||
__be64 rsvd_pdid;
|
||||
__be32 qlen_qbase;
|
||||
__be16 cur_msn;
|
||||
__be16 max_msn;
|
||||
};
|
||||
|
||||
struct cpl_srq_table_rpl {
|
||||
RSS_HDR
|
||||
union opcode_tid ot;
|
||||
__u8 status;
|
||||
__u8 rsvd[2];
|
||||
__u8 idx;
|
||||
__be64 rsvd_pdid;
|
||||
__be32 qlen_qbase;
|
||||
__be16 cur_msn;
|
||||
__be16 max_msn;
|
||||
};
|
||||
|
||||
/* cpl_srq_table_{req,rpl}.params fields */
|
||||
#define S_SRQT_QLEN 28
|
||||
#define M_SRQT_QLEN 0xF
|
||||
#define V_SRQT_QLEN(x) ((x) << S_SRQT_QLEN)
|
||||
#define G_SRQT_QLEN(x) (((x) >> S_SRQT_QLEN) & M_SRQT_QLEN)
|
||||
|
||||
#define S_SRQT_QBASE 0
|
||||
#define M_SRQT_QBASE 0x3FFFFFF
|
||||
#define V_SRQT_QBASE(x) ((x) << S_SRQT_QBASE)
|
||||
#define G_SRQT_QBASE(x) (((x) >> S_SRQT_QBASE) & M_SRQT_QBASE)
|
||||
|
||||
#define S_SRQT_PDID 0
|
||||
#define M_SRQT_PDID 0xFF
|
||||
#define V_SRQT_PDID(x) ((x) << S_SRQT_PDID)
|
||||
#define G_SRQT_PDID(x) (((x) >> S_SRQT_PDID) & M_SRQT_PDID)
|
||||
|
||||
#define S_SRQT_IDX 0
|
||||
#define M_SRQT_IDX 0xF
|
||||
#define V_SRQT_IDX(x) ((x) << S_SRQT_IDX)
|
||||
#define G_SRQT_IDX(x) (((x) >> S_SRQT_IDX) & M_SRQT_IDX)
|
||||
|
||||
struct cpl_smt_write_req {
|
||||
WR_HDR;
|
||||
union opcode_tid ot;
|
||||
|
|
@ -2006,6 +2313,17 @@ struct cpl_smt_write_req {
|
|||
__u8 src_mac0[6];
|
||||
};
|
||||
|
||||
struct cpl_t6_smt_write_req {
|
||||
WR_HDR;
|
||||
union opcode_tid ot;
|
||||
__be32 params;
|
||||
__be64 tag;
|
||||
__be16 pfvf0;
|
||||
__u8 src_mac0[6];
|
||||
__be32 local_ip;
|
||||
__be32 rsvd;
|
||||
};
|
||||
|
||||
struct cpl_smt_write_rpl {
|
||||
RSS_HDR
|
||||
union opcode_tid ot;
|
||||
|
|
@ -2042,6 +2360,9 @@ struct cpl_smt_read_rpl {
|
|||
#define V_SMTW_IDX(x) ((x) << S_SMTW_IDX)
|
||||
#define G_SMTW_IDX(x) (((x) >> S_SMTW_IDX) & M_SMTW_IDX)
|
||||
|
||||
#define M_T6_SMTW_IDX 0xFF
|
||||
#define G_T6_SMTW_IDX(x) (((x) >> S_SMTW_IDX) & M_T6_SMTW_IDX)
|
||||
|
||||
#define S_SMTW_NORPL 31
|
||||
#define V_SMTW_NORPL(x) ((x) << S_SMTW_NORPL)
|
||||
#define F_SMTW_NORPL V_SMTW_NORPL(1U)
|
||||
|
|
@ -2272,6 +2593,11 @@ struct cpl_sge_egr_update {
|
|||
};
|
||||
|
||||
/* cpl_sge_egr_update.ot fields */
|
||||
#define S_AUTOEQU 22
|
||||
#define M_AUTOEQU 0x1
|
||||
#define V_AUTOEQU(x) ((x) << S_AUTOEQU)
|
||||
#define G_AUTOEQU(x) (((x) >> S_AUTOEQU) & M_AUTOEQU)
|
||||
|
||||
#define S_EGR_QID 0
|
||||
#define M_EGR_QID 0x1FFFF
|
||||
#define V_EGR_QID(x) ((x) << S_EGR_QID)
|
||||
|
|
@ -2284,6 +2610,8 @@ enum {
|
|||
FW_TYPE_CQE = 2,
|
||||
FW_TYPE_OFLD_CONNECTION_WR_RPL = 3,
|
||||
FW_TYPE_RSSCPL = 4,
|
||||
FW_TYPE_WRERR_RPL = 5,
|
||||
FW_TYPE_PI_ERR = 6,
|
||||
};
|
||||
|
||||
struct cpl_fw2_pld {
|
||||
|
|
@ -2359,7 +2687,8 @@ enum {
|
|||
FW6_TYPE_CQE = FW_TYPE_CQE,
|
||||
FW6_TYPE_OFLD_CONNECTION_WR_RPL = FW_TYPE_OFLD_CONNECTION_WR_RPL,
|
||||
FW6_TYPE_RSSCPL = FW_TYPE_RSSCPL,
|
||||
|
||||
FW6_TYPE_WRERR_RPL = FW_TYPE_WRERR_RPL,
|
||||
FW6_TYPE_PI_ERR = FW_TYPE_PI_ERR,
|
||||
NUM_FW6_TYPES
|
||||
};
|
||||
|
||||
|
|
@ -2382,7 +2711,8 @@ enum {
|
|||
ULP_TX_SC_NOOP = 0x80,
|
||||
ULP_TX_SC_IMM = 0x81,
|
||||
ULP_TX_SC_DSGL = 0x82,
|
||||
ULP_TX_SC_ISGL = 0x83
|
||||
ULP_TX_SC_ISGL = 0x83,
|
||||
ULP_TX_SC_PICTRL = 0x84
|
||||
};
|
||||
|
||||
#define S_ULPTX_CMD 24
|
||||
|
|
@ -2455,6 +2785,10 @@ struct ulp_mem_io {
|
|||
#define V_T5_ULP_MEMIO_ORDER(x) ((x) << S_T5_ULP_MEMIO_ORDER)
|
||||
#define F_T5_ULP_MEMIO_ORDER V_T5_ULP_MEMIO_ORDER(1U)
|
||||
|
||||
#define S_T5_ULP_MEMIO_FID 4
|
||||
#define M_T5_ULP_MEMIO_FID 0x7ff
|
||||
#define V_T5_ULP_MEMIO_FID(x) ((x) << S_T5_ULP_MEMIO_FID)
|
||||
|
||||
/* ulp_mem_io.lock_addr fields */
|
||||
#define S_ULP_MEMIO_ADDR 0
|
||||
#define M_ULP_MEMIO_ADDR 0x7FFFFFF
|
||||
|
|
@ -2495,4 +2829,219 @@ struct ulp_txpkt {
|
|||
#define V_ULP_TXPKT_RO(x) ((x) << S_ULP_TXPKT_RO)
|
||||
#define F_ULP_TXPKT_RO V_ULP_TXPKT_RO(1U)
|
||||
|
||||
enum cpl_tx_tnl_lso_type {
|
||||
TX_TNL_TYPE_OPAQUE,
|
||||
TX_TNL_TYPE_NVGRE,
|
||||
TX_TNL_TYPE_VXLAN,
|
||||
TX_TNL_TYPE_GENEVE,
|
||||
};
|
||||
|
||||
struct cpl_tx_tnl_lso {
|
||||
__be32 op_to_IpIdSplitOut;
|
||||
__be16 IpIdOffsetOut;
|
||||
__be16 UdpLenSetOut_to_TnlHdrLen;
|
||||
__be64 r1;
|
||||
__be32 Flow_to_TcpHdrLen;
|
||||
__be16 IpIdOffset;
|
||||
__be16 IpIdSplit_to_Mss;
|
||||
__be32 TCPSeqOffset;
|
||||
__be32 EthLenOffset_Size;
|
||||
/* encapsulated CPL (TX_PKT_XT) follows here */
|
||||
};
|
||||
|
||||
#define S_CPL_TX_TNL_LSO_OPCODE 24
|
||||
#define M_CPL_TX_TNL_LSO_OPCODE 0xff
|
||||
#define V_CPL_TX_TNL_LSO_OPCODE(x) ((x) << S_CPL_TX_TNL_LSO_OPCODE)
|
||||
#define G_CPL_TX_TNL_LSO_OPCODE(x) \
|
||||
(((x) >> S_CPL_TX_TNL_LSO_OPCODE) & M_CPL_TX_TNL_LSO_OPCODE)
|
||||
|
||||
#define S_CPL_TX_TNL_LSO_FIRST 23
|
||||
#define M_CPL_TX_TNL_LSO_FIRST 0x1
|
||||
#define V_CPL_TX_TNL_LSO_FIRST(x) ((x) << S_CPL_TX_TNL_LSO_FIRST)
|
||||
#define G_CPL_TX_TNL_LSO_FIRST(x) \
|
||||
(((x) >> S_CPL_TX_TNL_LSO_FIRST) & M_CPL_TX_TNL_LSO_FIRST)
|
||||
#define F_CPL_TX_TNL_LSO_FIRST V_CPL_TX_TNL_LSO_FIRST(1U)
|
||||
|
||||
#define S_CPL_TX_TNL_LSO_LAST 22
|
||||
#define M_CPL_TX_TNL_LSO_LAST 0x1
|
||||
#define V_CPL_TX_TNL_LSO_LAST(x) ((x) << S_CPL_TX_TNL_LSO_LAST)
|
||||
#define G_CPL_TX_TNL_LSO_LAST(x) \
|
||||
(((x) >> S_CPL_TX_TNL_LSO_LAST) & M_CPL_TX_TNL_LSO_LAST)
|
||||
#define F_CPL_TX_TNL_LSO_LAST V_CPL_TX_TNL_LSO_LAST(1U)
|
||||
|
||||
#define S_CPL_TX_TNL_LSO_ETHHDRLENXOUT 21
|
||||
#define M_CPL_TX_TNL_LSO_ETHHDRLENXOUT 0x1
|
||||
#define V_CPL_TX_TNL_LSO_ETHHDRLENXOUT(x) \
|
||||
((x) << S_CPL_TX_TNL_LSO_ETHHDRLENXOUT)
|
||||
#define G_CPL_TX_TNL_LSO_ETHHDRLENXOUT(x) \
|
||||
(((x) >> S_CPL_TX_TNL_LSO_ETHHDRLENXOUT) & M_CPL_TX_TNL_LSO_ETHHDRLENXOUT)
|
||||
#define F_CPL_TX_TNL_LSO_ETHHDRLENXOUT V_CPL_TX_TNL_LSO_ETHHDRLENXOUT(1U)
|
||||
|
||||
#define S_CPL_TX_TNL_LSO_IPV6OUT 20
|
||||
#define M_CPL_TX_TNL_LSO_IPV6OUT 0x1
|
||||
#define V_CPL_TX_TNL_LSO_IPV6OUT(x) ((x) << S_CPL_TX_TNL_LSO_IPV6OUT)
|
||||
#define G_CPL_TX_TNL_LSO_IPV6OUT(x) \
|
||||
(((x) >> S_CPL_TX_TNL_LSO_IPV6OUT) & M_CPL_TX_TNL_LSO_IPV6OUT)
|
||||
#define F_CPL_TX_TNL_LSO_IPV6OUT V_CPL_TX_TNL_LSO_IPV6OUT(1U)
|
||||
|
||||
#define S_CPL_TX_TNL_LSO_ETHHDRLENOUT 16
|
||||
#define M_CPL_TX_TNL_LSO_ETHHDRLENOUT 0xf
|
||||
#define V_CPL_TX_TNL_LSO_ETHHDRLENOUT(x) \
|
||||
((x) << S_CPL_TX_TNL_LSO_ETHHDRLENOUT)
|
||||
#define G_CPL_TX_TNL_LSO_ETHHDRLENOUT(x) \
|
||||
(((x) >> S_CPL_TX_TNL_LSO_ETHHDRLENOUT) & M_CPL_TX_TNL_LSO_ETHHDRLENOUT)
|
||||
|
||||
#define S_CPL_TX_TNL_LSO_IPHDRLENOUT 4
|
||||
#define M_CPL_TX_TNL_LSO_IPHDRLENOUT 0xfff
|
||||
#define V_CPL_TX_TNL_LSO_IPHDRLENOUT(x) ((x) << S_CPL_TX_TNL_LSO_IPHDRLENOUT)
|
||||
#define G_CPL_TX_TNL_LSO_IPHDRLENOUT(x) \
|
||||
(((x) >> S_CPL_TX_TNL_LSO_IPHDRLENOUT) & M_CPL_TX_TNL_LSO_IPHDRLENOUT)
|
||||
|
||||
#define S_CPL_TX_TNL_LSO_IPHDRCHKOUT 3
|
||||
#define M_CPL_TX_TNL_LSO_IPHDRCHKOUT 0x1
|
||||
#define V_CPL_TX_TNL_LSO_IPHDRCHKOUT(x) ((x) << S_CPL_TX_TNL_LSO_IPHDRCHKOUT)
|
||||
#define G_CPL_TX_TNL_LSO_IPHDRCHKOUT(x) \
|
||||
(((x) >> S_CPL_TX_TNL_LSO_IPHDRCHKOUT) & M_CPL_TX_TNL_LSO_IPHDRCHKOUT)
|
||||
#define F_CPL_TX_TNL_LSO_IPHDRCHKOUT V_CPL_TX_TNL_LSO_IPHDRCHKOUT(1U)
|
||||
|
||||
#define S_CPL_TX_TNL_LSO_IPLENSETOUT 2
|
||||
#define M_CPL_TX_TNL_LSO_IPLENSETOUT 0x1
|
||||
#define V_CPL_TX_TNL_LSO_IPLENSETOUT(x) ((x) << S_CPL_TX_TNL_LSO_IPLENSETOUT)
|
||||
#define G_CPL_TX_TNL_LSO_IPLENSETOUT(x) \
|
||||
(((x) >> S_CPL_TX_TNL_LSO_IPLENSETOUT) & M_CPL_TX_TNL_LSO_IPLENSETOUT)
|
||||
#define F_CPL_TX_TNL_LSO_IPLENSETOUT V_CPL_TX_TNL_LSO_IPLENSETOUT(1U)
|
||||
|
||||
#define S_CPL_TX_TNL_LSO_IPIDINCOUT 1
|
||||
#define M_CPL_TX_TNL_LSO_IPIDINCOUT 0x1
|
||||
#define V_CPL_TX_TNL_LSO_IPIDINCOUT(x) ((x) << S_CPL_TX_TNL_LSO_IPIDINCOUT)
|
||||
#define G_CPL_TX_TNL_LSO_IPIDINCOUT(x) \
|
||||
(((x) >> S_CPL_TX_TNL_LSO_IPIDINCOUT) & M_CPL_TX_TNL_LSO_IPIDINCOUT)
|
||||
#define F_CPL_TX_TNL_LSO_IPIDINCOUT V_CPL_TX_TNL_LSO_IPIDINCOUT(1U)
|
||||
|
||||
#define S_CPL_TX_TNL_LSO_IPIDSPLITOUT 0
|
||||
#define M_CPL_TX_TNL_LSO_IPIDSPLITOUT 0x1
|
||||
#define V_CPL_TX_TNL_LSO_IPIDSPLITOUT(x) \
|
||||
((x) << S_CPL_TX_TNL_LSO_IPIDSPLITOUT)
|
||||
#define G_CPL_TX_TNL_LSO_IPIDSPLITOUT(x) \
|
||||
(((x) >> S_CPL_TX_TNL_LSO_IPIDSPLITOUT) & M_CPL_TX_TNL_LSO_IPIDSPLITOUT)
|
||||
#define F_CPL_TX_TNL_LSO_IPIDSPLITOUT V_CPL_TX_TNL_LSO_IPIDSPLITOUT(1U)
|
||||
|
||||
#define S_CPL_TX_TNL_LSO_UDPLENSETOUT 15
|
||||
#define M_CPL_TX_TNL_LSO_UDPLENSETOUT 0x1
|
||||
#define V_CPL_TX_TNL_LSO_UDPLENSETOUT(x) \
|
||||
((x) << S_CPL_TX_TNL_LSO_UDPLENSETOUT)
|
||||
#define G_CPL_TX_TNL_LSO_UDPLENSETOUT(x) \
|
||||
(((x) >> S_CPL_TX_TNL_LSO_UDPLENSETOUT) & M_CPL_TX_TNL_LSO_UDPLENSETOUT)
|
||||
#define F_CPL_TX_TNL_LSO_UDPLENSETOUT V_CPL_TX_TNL_LSO_UDPLENSETOUT(1U)
|
||||
|
||||
#define S_CPL_TX_TNL_LSO_UDPCHKCLROUT 14
|
||||
#define M_CPL_TX_TNL_LSO_UDPCHKCLROUT 0x1
|
||||
#define V_CPL_TX_TNL_LSO_UDPCHKCLROUT(x) \
|
||||
((x) << S_CPL_TX_TNL_LSO_UDPCHKCLROUT)
|
||||
#define G_CPL_TX_TNL_LSO_UDPCHKCLROUT(x) \
|
||||
(((x) >> S_CPL_TX_TNL_LSO_UDPCHKCLROUT) & M_CPL_TX_TNL_LSO_UDPCHKCLROUT)
|
||||
#define F_CPL_TX_TNL_LSO_UDPCHKCLROUT V_CPL_TX_TNL_LSO_UDPCHKCLROUT(1U)
|
||||
|
||||
#define S_CPL_TX_TNL_LSO_TNLTYPE 12
|
||||
#define M_CPL_TX_TNL_LSO_TNLTYPE 0x3
|
||||
#define V_CPL_TX_TNL_LSO_TNLTYPE(x) ((x) << S_CPL_TX_TNL_LSO_TNLTYPE)
|
||||
#define G_CPL_TX_TNL_LSO_TNLTYPE(x) \
|
||||
(((x) >> S_CPL_TX_TNL_LSO_TNLTYPE) & M_CPL_TX_TNL_LSO_TNLTYPE)
|
||||
|
||||
#define S_CPL_TX_TNL_LSO_TNLHDRLEN 0
|
||||
#define M_CPL_TX_TNL_LSO_TNLHDRLEN 0xfff
|
||||
#define V_CPL_TX_TNL_LSO_TNLHDRLEN(x) ((x) << S_CPL_TX_TNL_LSO_TNLHDRLEN)
|
||||
#define G_CPL_TX_TNL_LSO_TNLHDRLEN(x) \
|
||||
(((x) >> S_CPL_TX_TNL_LSO_TNLHDRLEN) & M_CPL_TX_TNL_LSO_TNLHDRLEN)
|
||||
|
||||
#define S_CPL_TX_TNL_LSO_FLOW 21
|
||||
#define M_CPL_TX_TNL_LSO_FLOW 0x1
|
||||
#define V_CPL_TX_TNL_LSO_FLOW(x) ((x) << S_CPL_TX_TNL_LSO_FLOW)
|
||||
#define G_CPL_TX_TNL_LSO_FLOW(x) \
|
||||
(((x) >> S_CPL_TX_TNL_LSO_FLOW) & M_CPL_TX_TNL_LSO_FLOW)
|
||||
#define F_CPL_TX_TNL_LSO_FLOW V_CPL_TX_TNL_LSO_FLOW(1U)
|
||||
|
||||
#define S_CPL_TX_TNL_LSO_IPV6 20
|
||||
#define M_CPL_TX_TNL_LSO_IPV6 0x1
|
||||
#define V_CPL_TX_TNL_LSO_IPV6(x) ((x) << S_CPL_TX_TNL_LSO_IPV6)
|
||||
#define G_CPL_TX_TNL_LSO_IPV6(x) \
|
||||
(((x) >> S_CPL_TX_TNL_LSO_IPV6) & M_CPL_TX_TNL_LSO_IPV6)
|
||||
#define F_CPL_TX_TNL_LSO_IPV6 V_CPL_TX_TNL_LSO_IPV6(1U)
|
||||
|
||||
#define S_CPL_TX_TNL_LSO_ETHHDRLEN 16
|
||||
#define M_CPL_TX_TNL_LSO_ETHHDRLEN 0xf
|
||||
#define V_CPL_TX_TNL_LSO_ETHHDRLEN(x) ((x) << S_CPL_TX_TNL_LSO_ETHHDRLEN)
|
||||
#define G_CPL_TX_TNL_LSO_ETHHDRLEN(x) \
|
||||
(((x) >> S_CPL_TX_TNL_LSO_ETHHDRLEN) & M_CPL_TX_TNL_LSO_ETHHDRLEN)
|
||||
|
||||
#define S_CPL_TX_TNL_LSO_IPHDRLEN 4
|
||||
#define M_CPL_TX_TNL_LSO_IPHDRLEN 0xfff
|
||||
#define V_CPL_TX_TNL_LSO_IPHDRLEN(x) ((x) << S_CPL_TX_TNL_LSO_IPHDRLEN)
|
||||
#define G_CPL_TX_TNL_LSO_IPHDRLEN(x) \
|
||||
(((x) >> S_CPL_TX_TNL_LSO_IPHDRLEN) & M_CPL_TX_TNL_LSO_IPHDRLEN)
|
||||
|
||||
#define S_CPL_TX_TNL_LSO_TCPHDRLEN 0
|
||||
#define M_CPL_TX_TNL_LSO_TCPHDRLEN 0xf
|
||||
#define V_CPL_TX_TNL_LSO_TCPHDRLEN(x) ((x) << S_CPL_TX_TNL_LSO_TCPHDRLEN)
|
||||
#define G_CPL_TX_TNL_LSO_TCPHDRLEN(x) \
|
||||
(((x) >> S_CPL_TX_TNL_LSO_TCPHDRLEN) & M_CPL_TX_TNL_LSO_TCPHDRLEN)
|
||||
|
||||
#define S_CPL_TX_TNL_LSO_IPIDSPLIT 15
|
||||
#define M_CPL_TX_TNL_LSO_IPIDSPLIT 0x1
|
||||
#define V_CPL_TX_TNL_LSO_IPIDSPLIT(x) ((x) << S_CPL_TX_TNL_LSO_IPIDSPLIT)
|
||||
#define G_CPL_TX_TNL_LSO_IPIDSPLIT(x) \
|
||||
(((x) >> S_CPL_TX_TNL_LSO_IPIDSPLIT) & M_CPL_TX_TNL_LSO_IPIDSPLIT)
|
||||
#define F_CPL_TX_TNL_LSO_IPIDSPLIT V_CPL_TX_TNL_LSO_IPIDSPLIT(1U)
|
||||
|
||||
#define S_CPL_TX_TNL_LSO_ETHHDRLENX 14
|
||||
#define M_CPL_TX_TNL_LSO_ETHHDRLENX 0x1
|
||||
#define V_CPL_TX_TNL_LSO_ETHHDRLENX(x) ((x) << S_CPL_TX_TNL_LSO_ETHHDRLENX)
|
||||
#define G_CPL_TX_TNL_LSO_ETHHDRLENX(x) \
|
||||
(((x) >> S_CPL_TX_TNL_LSO_ETHHDRLENX) & M_CPL_TX_TNL_LSO_ETHHDRLENX)
|
||||
#define F_CPL_TX_TNL_LSO_ETHHDRLENX V_CPL_TX_TNL_LSO_ETHHDRLENX(1U)
|
||||
|
||||
#define S_CPL_TX_TNL_LSO_MSS 0
|
||||
#define M_CPL_TX_TNL_LSO_MSS 0x3fff
|
||||
#define V_CPL_TX_TNL_LSO_MSS(x) ((x) << S_CPL_TX_TNL_LSO_MSS)
|
||||
#define G_CPL_TX_TNL_LSO_MSS(x) \
|
||||
(((x) >> S_CPL_TX_TNL_LSO_MSS) & M_CPL_TX_TNL_LSO_MSS)
|
||||
|
||||
#define S_CPL_TX_TNL_LSO_ETHLENOFFSET 28
|
||||
#define M_CPL_TX_TNL_LSO_ETHLENOFFSET 0xf
|
||||
#define V_CPL_TX_TNL_LSO_ETHLENOFFSET(x) \
|
||||
((x) << S_CPL_TX_TNL_LSO_ETHLENOFFSET)
|
||||
#define G_CPL_TX_TNL_LSO_ETHLENOFFSET(x) \
|
||||
(((x) >> S_CPL_TX_TNL_LSO_ETHLENOFFSET) & M_CPL_TX_TNL_LSO_ETHLENOFFSET)
|
||||
|
||||
#define S_CPL_TX_TNL_LSO_SIZE 0
|
||||
#define M_CPL_TX_TNL_LSO_SIZE 0xfffffff
|
||||
#define V_CPL_TX_TNL_LSO_SIZE(x) ((x) << S_CPL_TX_TNL_LSO_SIZE)
|
||||
#define G_CPL_TX_TNL_LSO_SIZE(x) \
|
||||
(((x) >> S_CPL_TX_TNL_LSO_SIZE) & M_CPL_TX_TNL_LSO_SIZE)
|
||||
|
||||
struct cpl_rx_mps_pkt {
|
||||
__be32 op_to_r1_hi;
|
||||
__be32 r1_lo_length;
|
||||
};
|
||||
|
||||
#define S_CPL_RX_MPS_PKT_OP 24
|
||||
#define M_CPL_RX_MPS_PKT_OP 0xff
|
||||
#define V_CPL_RX_MPS_PKT_OP(x) ((x) << S_CPL_RX_MPS_PKT_OP)
|
||||
#define G_CPL_RX_MPS_PKT_OP(x) \
|
||||
(((x) >> S_CPL_RX_MPS_PKT_OP) & M_CPL_RX_MPS_PKT_OP)
|
||||
|
||||
#define S_CPL_RX_MPS_PKT_TYPE 20
|
||||
#define M_CPL_RX_MPS_PKT_TYPE 0xf
|
||||
#define V_CPL_RX_MPS_PKT_TYPE(x) ((x) << S_CPL_RX_MPS_PKT_TYPE)
|
||||
#define G_CPL_RX_MPS_PKT_TYPE(x) \
|
||||
(((x) >> S_CPL_RX_MPS_PKT_TYPE) & M_CPL_RX_MPS_PKT_TYPE)
|
||||
|
||||
/*
|
||||
* Values for CPL_RX_MPS_PKT_TYPE, a bit-wise orthogonal field.
|
||||
*/
|
||||
#define X_CPL_RX_MPS_PKT_TYPE_PAUSE (1 << 0)
|
||||
#define X_CPL_RX_MPS_PKT_TYPE_PPP (1 << 1)
|
||||
#define X_CPL_RX_MPS_PKT_TYPE_QFC (1 << 2)
|
||||
#define X_CPL_RX_MPS_PKT_TYPE_PTP (1 << 3)
|
||||
|
||||
#endif /* T4_MSG_H */
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
|
|
@ -1,5 +1,5 @@
|
|||
/*-
|
||||
* Copyright (c) 2011 Chelsio Communications, Inc.
|
||||
* Copyright (c) 2011, 2016 Chelsio Communications, Inc.
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
|
|
@ -82,6 +82,16 @@
|
|||
#define X_INGPCIEBOUNDARY_2048B 6
|
||||
#define X_INGPCIEBOUNDARY_4096B 7
|
||||
|
||||
#define X_T6_INGPADBOUNDARY_SHIFT 3
|
||||
#define X_T6_INGPADBOUNDARY_8B 0
|
||||
#define X_T6_INGPADBOUNDARY_16B 1
|
||||
#define X_T6_INGPADBOUNDARY_32B 2
|
||||
#define X_T6_INGPADBOUNDARY_64B 3
|
||||
#define X_T6_INGPADBOUNDARY_128B 4
|
||||
#define X_T6_INGPADBOUNDARY_256B 5
|
||||
#define X_T6_INGPADBOUNDARY_512B 6
|
||||
#define X_T6_INGPADBOUNDARY_1024B 7
|
||||
|
||||
#define X_INGPADBOUNDARY_SHIFT 5
|
||||
#define X_INGPADBOUNDARY_32B 0
|
||||
#define X_INGPADBOUNDARY_64B 1
|
||||
|
|
@ -102,6 +112,17 @@
|
|||
#define X_EGRPCIEBOUNDARY_2048B 6
|
||||
#define X_EGRPCIEBOUNDARY_4096B 7
|
||||
|
||||
/* CONTROL2 register */
|
||||
#define X_INGPACKBOUNDARY_SHIFT 5 // *most* of the values ...
|
||||
#define X_INGPACKBOUNDARY_16B 0 // Note weird value!
|
||||
#define X_INGPACKBOUNDARY_64B 1
|
||||
#define X_INGPACKBOUNDARY_128B 2
|
||||
#define X_INGPACKBOUNDARY_256B 3
|
||||
#define X_INGPACKBOUNDARY_512B 4
|
||||
#define X_INGPACKBOUNDARY_1024B 5
|
||||
#define X_INGPACKBOUNDARY_2048B 6
|
||||
#define X_INGPACKBOUNDARY_4096B 7
|
||||
|
||||
/* GTS register */
|
||||
#define SGE_TIMERREGS 6
|
||||
#define X_TIMERREG_COUNTER0 0
|
||||
|
|
@ -177,6 +198,52 @@
|
|||
#define X_RSPD_TYPE_CPL 1
|
||||
#define X_RSPD_TYPE_INTR 2
|
||||
|
||||
/*
|
||||
* Context field definitions. This is by no means a complete list of SGE
|
||||
* Context fields. In the vast majority of cases the firmware initializes
|
||||
* things the way they need to be set up. But in a few small cases, we need
|
||||
* to compute new values and ship them off to the firmware to be applied to
|
||||
* the SGE Conexts ...
|
||||
*/
|
||||
|
||||
/*
|
||||
* Congestion Manager Definitions.
|
||||
*/
|
||||
#define S_CONMCTXT_CNGTPMODE 19
|
||||
#define M_CONMCTXT_CNGTPMODE 0x3
|
||||
#define V_CONMCTXT_CNGTPMODE(x) ((x) << S_CONMCTXT_CNGTPMODE)
|
||||
#define G_CONMCTXT_CNGTPMODE(x) \
|
||||
(((x) >> S_CONMCTXT_CNGTPMODE) & M_CONMCTXT_CNGTPMODE)
|
||||
#define S_CONMCTXT_CNGCHMAP 0
|
||||
#define M_CONMCTXT_CNGCHMAP 0xffff
|
||||
#define V_CONMCTXT_CNGCHMAP(x) ((x) << S_CONMCTXT_CNGCHMAP)
|
||||
#define G_CONMCTXT_CNGCHMAP(x) \
|
||||
(((x) >> S_CONMCTXT_CNGCHMAP) & M_CONMCTXT_CNGCHMAP)
|
||||
|
||||
#define X_CONMCTXT_CNGTPMODE_DISABLE 0
|
||||
#define X_CONMCTXT_CNGTPMODE_QUEUE 1
|
||||
#define X_CONMCTXT_CNGTPMODE_CHANNEL 2
|
||||
#define X_CONMCTXT_CNGTPMODE_BOTH 3
|
||||
|
||||
/*
|
||||
* T5 and later support a new BAR2-based doorbell mechanism for Egress Queues.
|
||||
* The User Doorbells are each 128 bytes in length with a Simple Doorbell at
|
||||
* offsets 8x and a Write Combining single 64-byte Egress Queue Unit
|
||||
* (X_IDXSIZE_UNIT) Gather Buffer interface at offset 64. For Ingress Queues,
|
||||
* we have a Going To Sleep register at offsets 8x+4.
|
||||
*
|
||||
* As noted above, we have many instances of the Simple Doorbell and Going To
|
||||
* Sleep registers at offsets 8x and 8x+4, respectively. We want to use a
|
||||
* non-64-byte aligned offset for the Simple Doorbell in order to attempt to
|
||||
* avoid buffering of the writes to the Simple Doorbell and we want to use a
|
||||
* non-contiguous offset for the Going To Sleep writes in order to avoid
|
||||
* possible combining between them.
|
||||
*/
|
||||
#define SGE_UDB_SIZE 128
|
||||
#define SGE_UDB_KDOORBELL 8
|
||||
#define SGE_UDB_GTS 20
|
||||
#define SGE_UDB_WCDOORBELL 64
|
||||
|
||||
/*
|
||||
* CIM definitions.
|
||||
* ================
|
||||
|
|
@ -188,6 +255,7 @@
|
|||
#define X_MBOWNER_NONE 0
|
||||
#define X_MBOWNER_FW 1
|
||||
#define X_MBOWNER_PL 2
|
||||
#define X_MBOWNER_FW_DEFERRED 3
|
||||
|
||||
/*
|
||||
* PCI-E definitions.
|
||||
|
|
@ -208,6 +276,9 @@
|
|||
* selects for a particular field being present. These fields, when present
|
||||
* in the Compressed Filter Tuple, have the following widths in bits.
|
||||
*/
|
||||
#define S_FT_FIRST S_FCOE
|
||||
#define S_FT_LAST S_FRAGMENTATION
|
||||
|
||||
#define W_FT_FCOE 1
|
||||
#define W_FT_PORT 3
|
||||
#define W_FT_VNIC_ID 17
|
||||
|
|
|
|||
|
|
@ -1,5 +1,5 @@
|
|||
/*-
|
||||
* Copyright (c) 2011 Chelsio Communications, Inc.
|
||||
* Copyright (c) 2011, 2016 Chelsio Communications, Inc.
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
|
|
@ -332,12 +332,19 @@
|
|||
#define M_TCB_PDU_HDR_LEN 0xffULL
|
||||
#define V_TCB_PDU_HDR_LEN(x) ((x) << S_TCB_PDU_HDR_LEN)
|
||||
|
||||
/* 1023:1001 */
|
||||
/* 1019:1001 */
|
||||
#define W_TCB_AUX1_SLUSH1 31
|
||||
#define S_TCB_AUX1_SLUSH1 9
|
||||
#define M_TCB_AUX1_SLUSH1 0x7fffffULL
|
||||
#define M_TCB_AUX1_SLUSH1 0x7ffffULL
|
||||
#define V_TCB_AUX1_SLUSH1(x) ((x) << S_TCB_AUX1_SLUSH1)
|
||||
|
||||
/* 1023:1020 */
|
||||
#define W_TCB_ULP_EXT 31
|
||||
#define S_TCP_ULP_EXT 28
|
||||
#define M_TCB_ULP_EXT 0xfULL
|
||||
#define V_TCB_ULP_EXT(x) ((x) << S_TCP_ULP_EXT)
|
||||
|
||||
|
||||
/* 840:832 */
|
||||
#define W_TCB_IRS_ULP 26
|
||||
#define S_TCB_IRS_ULP 0
|
||||
|
|
|
|||
|
|
@ -144,16 +144,6 @@ done:
|
|||
return (0);
|
||||
}
|
||||
|
||||
static inline int
|
||||
act_open_has_tid(unsigned int status)
|
||||
{
|
||||
|
||||
return (status != CPL_ERR_TCAM_FULL &&
|
||||
status != CPL_ERR_TCAM_PARITY &&
|
||||
status != CPL_ERR_CONN_EXIST &&
|
||||
status != CPL_ERR_ARP_MISS);
|
||||
}
|
||||
|
||||
/*
|
||||
* Convert an ACT_OPEN_RPL status to an errno.
|
||||
*/
|
||||
|
|
@ -257,7 +247,7 @@ calc_opt2a(struct socket *so, struct toepcb *toep)
|
|||
opt2 |= F_RX_COALESCE_VALID;
|
||||
else {
|
||||
opt2 |= F_T5_OPT_2_VALID;
|
||||
opt2 |= F_CONG_CNTRL_VALID; /* OPT_2_ISS really, for T5 */
|
||||
opt2 |= F_T5_ISS;
|
||||
}
|
||||
if (sc->tt.rx_coalesce)
|
||||
opt2 |= V_RX_COALESCE(M_RX_COALESCE);
|
||||
|
|
|
|||
Loading…
Reference in a new issue