diff --git a/lib/libc/riscv/Makefile.inc b/lib/libc/riscv/Makefile.inc
index d71a2f7f264..9df72b44a61 100644
--- a/lib/libc/riscv/Makefile.inc
+++ b/lib/libc/riscv/Makefile.inc
@@ -3,10 +3,6 @@
 # Machine dependent definitions for the RISC-V architecture.
 #
 
-.if ${MACHINE_ARCH:Mriscv*sf} != ""
-CFLAGS+=-DSOFTFLOAT
-.endif
-
 # Long double is quad precision
 GDTOASRCS+=strtorQ.c
 SRCS+=machdep_ldisQ.c
diff --git a/lib/libc/riscv/gen/_setjmp.S b/lib/libc/riscv/gen/_setjmp.S
index 4e82ae42085..4553f3dbb8b 100644
--- a/lib/libc/riscv/gen/_setjmp.S
+++ b/lib/libc/riscv/gen/_setjmp.S
@@ -61,7 +61,7 @@ ENTRY(_setjmp)
 	sd	ra, (12 * 8)(a0)
 	addi	a0, a0, (13 * 8)
 
-#if !defined(_STANDALONE) && !defined(SOFTFLOAT)
+#if !defined(_STANDALONE) && defined(__riscv_float_abi_double)
 	/* Store the fpe registers */
 	fsd	fs0, (0 * 16)(a0)
 	fsd	fs1, (1 * 16)(a0)
@@ -114,7 +114,7 @@ ENTRY(_longjmp)
 	ld	ra, (12 * 8)(a0)
 	addi	a0, a0, (13 * 8)
 
-#if !defined(_STANDALONE) && !defined(SOFTFLOAT)
+#if !defined(_STANDALONE) && defined(__riscv_float_abi_double)
 	/* Restore the fpe registers */
 	fld	fs0, (0 * 16)(a0)
 	fld	fs1, (1 * 16)(a0)
diff --git a/lib/libc/riscv/gen/fabs.S b/lib/libc/riscv/gen/fabs.S
index 7cd303336cf..44249252e9c 100644
--- a/lib/libc/riscv/gen/fabs.S
+++ b/lib/libc/riscv/gen/fabs.S
@@ -35,7 +35,7 @@
 #include <machine/asm.h>
 __FBSDID("$FreeBSD$");
 
-#ifndef SOFTFLOAT
+#ifdef __riscv_float_abi_double
 ENTRY(fabs)
 	fabs.d	fa0, fa0
 	ret
diff --git a/lib/libc/riscv/gen/flt_rounds.c b/lib/libc/riscv/gen/flt_rounds.c
index 13bb8b2a179..5dec6e45f40 100644
--- a/lib/libc/riscv/gen/flt_rounds.c
+++ b/lib/libc/riscv/gen/flt_rounds.c
@@ -40,7 +40,7 @@ __FBSDID("$FreeBSD$");
 #include <fenv.h>
 #include <float.h>
 
-#ifdef	SOFTFLOAT
+#ifdef __riscv_float_abi_soft
 #include "softfloat-for-gcc.h"
 #include "milieu.h"
 #include "softfloat.h"
@@ -51,7 +51,7 @@ __flt_rounds(void)
 {
 	uint64_t mode;
 
-#ifdef SOFTFLOAT
+#ifdef __riscv_float_abi_soft
 	mode = __softfloat_float_rounding_mode;
 #else
 	__asm __volatile("csrr %0, fcsr" : "=r" (mode));
diff --git a/lib/libc/riscv/gen/setjmp.S b/lib/libc/riscv/gen/setjmp.S
index 9d97b51de6b..bf3f13fb9a3 100644
--- a/lib/libc/riscv/gen/setjmp.S
+++ b/lib/libc/riscv/gen/setjmp.S
@@ -75,7 +75,7 @@ ENTRY(setjmp)
 	sd	ra, (12 * 8)(a0)
 	addi	a0, a0, (13 * 8)
 
-#ifndef SOFTFLOAT
+#ifdef __riscv_float_abi_double
 	/* Store the fpe registers */
 	fsd	fs0, (0 * 16)(a0)
 	fsd	fs1, (1 * 16)(a0)
@@ -144,7 +144,7 @@ ENTRY(longjmp)
 	ld	ra, (12 * 8)(a0)
 	addi	a0, a0, (13 * 8)
 
-#ifndef SOFTFLOAT
+#ifdef __riscv_float_abi_double
 	/* Restore the fpe registers */
 	fld	fs0, (0 * 16)(a0)
 	fld	fs1, (1 * 16)(a0)
diff --git a/lib/msun/riscv/Makefile.inc b/lib/msun/riscv/Makefile.inc
index cd624918bed..3e2cec12c38 100644
--- a/lib/msun/riscv/Makefile.inc
+++ b/lib/msun/riscv/Makefile.inc
@@ -1,8 +1,4 @@
 # $FreeBSD$
 
-.if ${MACHINE_ARCH:Mriscv*sf} != ""
-CFLAGS+=-DSOFTFLOAT
-.endif
-
 LDBL_PREC = 113
 SYM_MAPS += ${.CURDIR}/riscv/Symbol.map
diff --git a/lib/msun/riscv/fenv.c b/lib/msun/riscv/fenv.c
index 9bc0d7e3574..0be27502e3e 100644
--- a/lib/msun/riscv/fenv.c
+++ b/lib/msun/riscv/fenv.c
@@ -39,7 +39,7 @@
  */
 const fenv_t __fe_dfl_env = 0;
 
-#ifdef SOFTFLOAT
+#ifdef __riscv_float_abi_soft
 #define __set_env(env, flags, mask, rnd) env = ((flags) | (rnd) << 5)
 #define __env_flags(env)                ((env) & FE_ALL_EXCEPT)
 #define __env_mask(env)                 (0) /* No exception traps. */
diff --git a/lib/msun/riscv/fenv.h b/lib/msun/riscv/fenv.h
index e66aa1c5775..f9d840d156f 100644
--- a/lib/msun/riscv/fenv.h
+++ b/lib/msun/riscv/fenv.h
@@ -73,12 +73,20 @@ __BEGIN_DECLS
 extern const fenv_t	__fe_dfl_env;
 #define	FE_DFL_ENV	(&__fe_dfl_env)
 
-#ifndef SOFTFLOAT
+#if !defined(__riscv_float_abi_soft) && !defined(__riscv_float_abi_double)
+#if defined(__riscv_float_abi_single)
+#error single precision floating point ABI not supported
+#else
+#error compiler did not set soft/hard float macros
+#endif
+#endif
+
+#ifndef __riscv_float_abi_soft
 #define	__rfs(__fcsr)	__asm __volatile("csrr %0, fcsr" : "=r" (__fcsr))
 #define	__wfs(__fcsr)	__asm __volatile("csrw fcsr, %0" :: "r" (__fcsr))
 #endif
 
-#ifdef SOFTFLOAT
+#ifdef __riscv_float_abi_soft
 int feclearexcept(int __excepts);
 int fegetexceptflag(fexcept_t *__flagp, int __excepts);
 int fesetexceptflag(const fexcept_t *__flagp, int __excepts);
@@ -206,13 +214,13 @@ feupdateenv(const fenv_t *__envp)
 
 	return (0);
 }
-#endif /* !SOFTFLOAT */
+#endif /* !__riscv_float_abi_soft */
 
 #if __BSD_VISIBLE
 
 /* We currently provide no external definitions of the functions below. */
 
-#ifdef SOFTFLOAT
+#ifdef __riscv_float_abi_soft
 int feenableexcept(int __mask);
 int fedisableexcept(int __mask);
 int fegetexcept(void);
@@ -243,7 +251,7 @@ fegetexcept(void)
 
 	return (0);
 }
-#endif /* !SOFTFLOAT */
+#endif /* !__riscv_float_abi_soft */
 
 #endif /* __BSD_VISIBLE */