upstream/opnsense-src
1
0
Fork 0
mirror of https://github.com/opnsense/src.git synced 2026-05-28 04:12:45 -04:00
Code Issues Projects Releases Packages Wiki Activity Actions

Whitespace fixes in mips/include, remove unused 'struct tlb' from locore.h

Browse source 
PR:		misc/147471
This commit is contained in:
Jayachandran C. 2010-08-27 07:45:50 +00:00
parent 50e64c14a2
commit 37b3715cdb
6 changed files with 49 additions and 51 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

2
sys/mips/include/atomic.h
View file

@ -48,7 +48,7 @@
static __inline void
mips_sync(void)
{
__asm __volatile (".set noreorder\n\t"
__asm __volatile (".set noreorder\n\t"
"sync\n\t"
"nop\n\t"
"nop\n\t"

32
sys/mips/include/locore.h
View file

@ -24,15 +24,13 @@
*/
#ifndef _MIPS_LOCORE_H
#define _MIPS_LOCORE_H
#define _MIPS_LOCORE_H
#include <machine/cpufunc.h>
#include <machine/cpuregs.h>
#include <machine/frame.h>
#include <machine/md_var.h>
struct tlb;
/*
* CPU identification, from PRID register.
*/
@ -47,22 +45,22 @@ typedef int mips_prid_t;
#define MIPS_PRID_REV_MAJ(x) ((MIPS_PRID_REV(x) >> 4) & 0x0f)
/* MIPS32/64 */
#define MIPS_PRID_CID(x) (((x) >> 16) & 0x00ff) /* Company ID */
#define MIPS_PRID_CID_PREHISTORIC 0x00 /* Not MIPS32/64 */
#define MIPS_PRID_CID_MTI 0x01 /* MIPS Technologies, Inc. */
#define MIPS_PRID_CID_BROADCOM 0x02 /* Broadcom */
#define MIPS_PRID_CID_ALCHEMY 0x03 /* Alchemy Semiconductor */
#define MIPS_PRID_CID_SIBYTE 0x04 /* SiByte */
#define MIPS_PRID_CID_SANDCRAFT 0x05 /* SandCraft */
#define MIPS_PRID_CID_PHILIPS 0x06 /* Philips */
#define MIPS_PRID_CID_TOSHIBA 0x07 /* Toshiba */
#define MIPS_PRID_CID_LSI 0x08 /* LSI */
#define MIPS_PRID_CID(x) (((x) >> 16) & 0x00ff) /* Company ID */
#define MIPS_PRID_CID_PREHISTORIC 0x00 /* Not MIPS32/64 */
#define MIPS_PRID_CID_MTI 0x01 /* MIPS Technologies, Inc. */
#define MIPS_PRID_CID_BROADCOM 0x02 /* Broadcom */
#define MIPS_PRID_CID_ALCHEMY 0x03 /* Alchemy Semiconductor */
#define MIPS_PRID_CID_SIBYTE 0x04 /* SiByte */
#define MIPS_PRID_CID_SANDCRAFT 0x05 /* SandCraft */
#define MIPS_PRID_CID_PHILIPS 0x06 /* Philips */
#define MIPS_PRID_CID_TOSHIBA 0x07 /* Toshiba */
#define MIPS_PRID_CID_LSI 0x08 /* LSI */
/* 0x09 unannounced */
/* 0x0a unannounced */
#define MIPS_PRID_CID_LEXRA 0x0b /* Lexra */
#define MIPS_PRID_CID_RMI 0x0c /* RMI */
#define MIPS_PRID_CID_CAVIUM 0x0d /* Cavium */
#define MIPS_PRID_COPTS(x) (((x) >> 24) & 0x00ff) /* Company Options */
#define MIPS_PRID_CID_LEXRA 0x0b /* Lexra */
#define MIPS_PRID_CID_RMI 0x0c /* RMI */
#define MIPS_PRID_CID_CAVIUM 0x0d /* Cavium */
#define MIPS_PRID_COPTS(x) (((x) >> 24) & 0x00ff) /* Company Options */
#ifdef _KERNEL
#ifdef __HAVE_MIPS_MACHDEP_CACHE_CONFIG

2
sys/mips/include/memdev.h
View file

@ -28,7 +28,7 @@
*/
#define CDEV_MINOR_MEM 0
#define CDEV_MINOR_KMEM 1
#define CDEV_MINOR_KMEM 1
d_open_t memopen;
d_read_t memrw;

28
sys/mips/include/pcb.h
View file

@ -58,20 +58,20 @@ struct pcb
/* these match the regnum's in regnum.h
* used by switch.S
*/
#define PCB_REG_S0 0
#define PCB_REG_S1 1
#define PCB_REG_S2 2
#define PCB_REG_S3 3
#define PCB_REG_S4 4
#define PCB_REG_S5 5
#define PCB_REG_S6 6
#define PCB_REG_S7 7
#define PCB_REG_SP 8
#define PCB_REG_S8 9
#define PCB_REG_RA 10
#define PCB_REG_SR 11
#define PCB_REG_GP 12
#define PCB_REG_PC 13
#define PCB_REG_S0 0
#define PCB_REG_S1 1
#define PCB_REG_S2 2
#define PCB_REG_S3 3
#define PCB_REG_S4 4
#define PCB_REG_S5 5
#define PCB_REG_S6 6
#define PCB_REG_S7 7
#define PCB_REG_SP 8
#define PCB_REG_S8 9
#define PCB_REG_RA 10
#define PCB_REG_SR 11
#define PCB_REG_GP 12
#define PCB_REG_PC 13
#ifdef _KERNEL

28
sys/mips/include/regnum.h
View file

@ -46,20 +46,20 @@
* in pcb.h and is used by
* swtch.S
*/
#define PREG_S0 0
#define PREG_S1 1
#define PREG_S2 2
#define PREG_S3 3
#define PREG_S4 4
#define PREG_S5 5
#define PREG_S6 6
#define PREG_S7 7
#define PREG_SP 8
#define PREG_S8 9
#define PREG_RA 10
#define PREG_SR 11
#define PREG_GP 12
#define PREG_PC 13
#define PREG_S0 0
#define PREG_S1 1
#define PREG_S2 2
#define PREG_S3 3
#define PREG_S4 4
#define PREG_S5 5
#define PREG_S6 6
#define PREG_S7 7
#define PREG_SP 8
#define PREG_S8 9
#define PREG_RA 10
#define PREG_SR 11
#define PREG_GP 12
#define PREG_PC 13
/*
* Location of the saved registers relative to ZERO.

8
sys/mips/include/ucontext.h
View file

@ -48,13 +48,13 @@ typedef struct __mcontext {
int mc_onstack; /* sigstack state to restore */
register_t mc_pc; /* pc at time of signal */
register_t mc_regs[32]; /* processor regs 0 to 31 */
register_t sr; /* status register */
register_t mullo, mulhi; /* mullo and mulhi registers... */
register_t sr; /* status register */
register_t mullo, mulhi; /* mullo and mulhi registers... */
int mc_fpused; /* fp has been used */
f_register_t mc_fpregs[33]; /* fp regs 0 to 31 and csr */
register_t mc_fpc_eir; /* fp exception instruction reg */
void *mc_tls; /* pointer to TLS area */
int __spare__[8]; /* XXX reserved */
int __spare__[8]; /* XXX reserved */
} mcontext_t;
#endif
@ -101,7 +101,7 @@ typedef struct __mcontext {
#define UCR_SP UCTX_REG(29)
#define UCR_S8 UCTX_REG(30)
#define UCR_RA UCTX_REG(31)
#define UCR_SR UCTX_REG(32)
#define UCR_SR UCTX_REG(32)
#define UCR_MDLO UCTX_REG(33)
#define UCR_MDHI UCTX_REG(34)