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Remove 'cr' at the end of line.

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This commit is contained in:
Pyun YongHyeon 2008-08-12 00:55:03 +00:00
parent 104d1d8401
commit 366dbcbd4a
1 changed files with 20 additions and 20 deletions
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40
sys/dev/mii/brgphy.c
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@ -202,9 +202,9 @@ brgphy_attach(device_t dev)
* in effect, and therefore whether we have 5706C or
* 5706S.
*/
PHY_WRITE(sc, BRGPHY_MII_SHADOW_1C,
PHY_WRITE(sc, BRGPHY_MII_SHADOW_1C,
BRGPHY_SHADOW_1C_MODE_CTRL);
if (PHY_READ(sc, BRGPHY_MII_SHADOW_1C) &
if (PHY_READ(sc, BRGPHY_MII_SHADOW_1C) &
BRGPHY_SHADOW_1C_ENA_1000X) {
bsc->serdes_flags |= BRGPHY_5706S;
sc->mii_flags |= MIIF_HAVEFIBER;
@ -527,7 +527,7 @@ brgphy_status(struct mii_softc *sc)
mii->mii_media_active = IFM_ETHER;
bmsr = PHY_READ(sc, BRGPHY_MII_BMSR) | PHY_READ(sc, BRGPHY_MII_BMSR);
bmcr = PHY_READ(sc, BRGPHY_MII_BMCR);
bmcr = PHY_READ(sc, BRGPHY_MII_BMCR);
anar = PHY_READ(sc, BRGPHY_MII_ANAR);
anlpar = PHY_READ(sc, BRGPHY_MII_ANLPAR);
@ -652,7 +652,7 @@ brgphy_mii_phy_auto(struct mii_softc *sc)
BMSR_MEDIA_TO_ANAR(sc->mii_capabilities) | ANAR_CSMA |
BRGPHY_ANAR_ASP | BRGPHY_ANAR_PC);
} else {
PHY_WRITE(sc, BRGPHY_SERDES_ANAR, BRGPHY_SERDES_ANAR_FDX |
PHY_WRITE(sc, BRGPHY_SERDES_ANAR, BRGPHY_SERDES_ANAR_FDX |
BRGPHY_SERDES_ANAR_HDX | BRGPHY_SERDES_ANAR_BOTH_PAUSE);
}
@ -987,48 +987,48 @@ brgphy_reset(struct mii_softc *sc)
/* Store autoneg capabilities/results in digital block (Page 0) */
PHY_WRITE(sc, BRGPHY_5708S_BLOCK_ADDR, BRGPHY_5708S_DIG3_PG2);
PHY_WRITE(sc, BRGPHY_5708S_PG2_DIGCTL_3_0,
PHY_WRITE(sc, BRGPHY_5708S_PG2_DIGCTL_3_0,
BRGPHY_5708S_PG2_DIGCTL_3_0_USE_IEEE);
PHY_WRITE(sc, BRGPHY_5708S_BLOCK_ADDR, BRGPHY_5708S_DIG_PG0);
/* Enable fiber mode and autodetection */
PHY_WRITE(sc, BRGPHY_5708S_PG0_1000X_CTL1,
PHY_READ(sc, BRGPHY_5708S_PG0_1000X_CTL1) |
BRGPHY_5708S_PG0_1000X_CTL1_AUTODET_EN |
PHY_WRITE(sc, BRGPHY_5708S_PG0_1000X_CTL1,
PHY_READ(sc, BRGPHY_5708S_PG0_1000X_CTL1) |
BRGPHY_5708S_PG0_1000X_CTL1_AUTODET_EN |
BRGPHY_5708S_PG0_1000X_CTL1_FIBER_MODE);
/* Enable parallel detection */
PHY_WRITE(sc, BRGPHY_5708S_PG0_1000X_CTL2,
PHY_READ(sc, BRGPHY_5708S_PG0_1000X_CTL2) |
PHY_WRITE(sc, BRGPHY_5708S_PG0_1000X_CTL2,
PHY_READ(sc, BRGPHY_5708S_PG0_1000X_CTL2) |
BRGPHY_5708S_PG0_1000X_CTL2_PAR_DET_EN);
/* Advertise 2.5G support through next page during autoneg */
if (bce_sc->bce_phy_flags & BCE_PHY_2_5G_CAPABLE_FLAG)
PHY_WRITE(sc, BRGPHY_5708S_ANEG_NXT_PG_XMIT1,
PHY_READ(sc, BRGPHY_5708S_ANEG_NXT_PG_XMIT1) |
PHY_WRITE(sc, BRGPHY_5708S_ANEG_NXT_PG_XMIT1,
PHY_READ(sc, BRGPHY_5708S_ANEG_NXT_PG_XMIT1) |
BRGPHY_5708S_ANEG_NXT_PG_XMIT1_25G);
/* Increase TX signal amplitude */
if ((BCE_CHIP_ID(bce_sc) == BCE_CHIP_ID_5708_A0) ||
(BCE_CHIP_ID(bce_sc) == BCE_CHIP_ID_5708_B0) ||
(BCE_CHIP_ID(bce_sc) == BCE_CHIP_ID_5708_B1)) {
PHY_WRITE(sc, BRGPHY_5708S_BLOCK_ADDR,
PHY_WRITE(sc, BRGPHY_5708S_BLOCK_ADDR,
BRGPHY_5708S_TX_MISC_PG5);
PHY_WRITE(sc, BRGPHY_5708S_PG5_TXACTL1,
PHY_WRITE(sc, BRGPHY_5708S_PG5_TXACTL1,
PHY_READ(sc, BRGPHY_5708S_PG5_TXACTL1) & ~0x30);
PHY_WRITE(sc, BRGPHY_5708S_BLOCK_ADDR,
PHY_WRITE(sc, BRGPHY_5708S_BLOCK_ADDR,
BRGPHY_5708S_DIG_PG0);
}
/* Backplanes use special driver/pre-driver/pre-emphasis values. */
/* Backplanes use special driver/pre-driver/pre-emphasis values. */
if ((bce_sc->bce_shared_hw_cfg & BCE_SHARED_HW_CFG_PHY_BACKPLANE) &&
(bce_sc->bce_port_hw_cfg & BCE_PORT_HW_CFG_CFG_TXCTL3_MASK)) {
PHY_WRITE(sc, BRGPHY_5708S_BLOCK_ADDR,
PHY_WRITE(sc, BRGPHY_5708S_BLOCK_ADDR,
BRGPHY_5708S_TX_MISC_PG5);
PHY_WRITE(sc, BRGPHY_5708S_PG5_TXACTL3,
bce_sc->bce_port_hw_cfg &
PHY_WRITE(sc, BRGPHY_5708S_PG5_TXACTL3,
bce_sc->bce_port_hw_cfg &
BCE_PORT_HW_CFG_CFG_TXCTL3_MASK);
PHY_WRITE(sc, BRGPHY_5708S_BLOCK_ADDR,
PHY_WRITE(sc, BRGPHY_5708S_BLOCK_ADDR,
BRGPHY_5708S_DIG_PG0);
}
} else if (BCE_CHIP_NUM(bce_sc) == BCE_CHIP_NUM_5709) {