mirror of
https://github.com/opnsense/src.git
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xlpge : driver for XLP network accelerator
Features: - network driver for the four 10G interfaces and two management ports on XLP 8xx. - Support 4xx and 3xx variants of the processor. - Source code and firmware building for the 16 mips32r2 micro-code engines in the Network Accelerator. - Basic initialization code for Packet ordering Engine. Submitted by: Prabhath Raman (prabhath at netlogicmicro com) [refactored and fixed up for style by jchandra]
This commit is contained in:
Jayachandran C.
parent
6f33c108f7
commit
35011d20cb
23 changed files with 6861 additions and 7 deletions
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@ -71,6 +71,7 @@ device bpf
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# Network
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device miibus
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device ether
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device xlpge
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#device re
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device msk
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device em
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@ -44,16 +44,289 @@ __FBSDID("$FreeBSD$");
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#include <mips/nlm/hal/fmn.h>
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#include <mips/nlm/hal/pic.h>
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#include <mips/nlm/hal/sys.h>
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#include <mips/nlm/hal/nae.h>
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#include <mips/nlm/hal/uart.h>
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#include <mips/nlm/hal/poe.h>
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#include <mips/nlm/xlp.h>
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#include <mips/nlm/board.h>
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#include <mips/nlm/msgring.h>
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static uint8_t board_eeprom_buf[EEPROM_SIZE];
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static int board_eeprom_set;
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struct xlp_board_info xlp_board_info;
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struct vfbid_tbl {
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int vfbid;
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int dest_vc;
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};
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/* XXXJC : this should be derived from msg thread mask */
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static struct vfbid_tbl nlm_vfbid[] = {
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/* NULL FBID should map to cpu0 to detect NAE send msg errors */
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{127, 0}, /* NAE <-> NAE mappings */
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{51, 1019}, {50, 1018}, {49, 1017}, {48, 1016},
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{47, 1015}, {46, 1014}, {45, 1013}, {44, 1012},
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{43, 1011}, {42, 1010}, {41, 1009}, {40, 1008},
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{39, 1007}, {38, 1006}, {37, 1005}, {36, 1004},
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{35, 1003}, {34, 1002}, {33, 1001}, {32, 1000},
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/* NAE <-> CPU mappings, freeback got to vc 3 of each thread */
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{31, 127}, {30, 123}, {29, 119}, {28, 115},
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{27, 111}, {26, 107}, {25, 103}, {24, 99},
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{23, 95}, {22, 91}, {21, 87}, {20, 83},
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{19, 79}, {18, 75}, {17, 71}, {16, 67},
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{15, 63}, {14, 59}, {13, 55}, {12, 51},
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{11, 47}, {10, 43}, { 9, 39}, { 8, 35},
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{ 7, 31}, { 6, 27}, { 5, 23}, { 4, 19},
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{ 3, 15}, { 2, 11}, { 1, 7}, { 0, 3},
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};
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static struct vfbid_tbl nlm3xx_vfbid[] = {
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/* NULL FBID should map to cpu0 to detect NAE send msg errors */
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{127, 0}, /* NAE <-> NAE mappings */
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{39, 503}, {38, 502}, {37, 501}, {36, 500},
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{35, 499}, {34, 498}, {33, 497}, {32, 496},
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/* NAE <-> CPU mappings, freeback got to vc 3 of each thread */
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{31, 127}, {30, 123}, {29, 119}, {28, 115},
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{27, 111}, {26, 107}, {25, 103}, {24, 99},
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{23, 95}, {22, 91}, {21, 87}, {20, 83},
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{19, 79}, {18, 75}, {17, 71}, {16, 67},
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{15, 63}, {14, 59}, {13, 55}, {12, 51},
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{11, 47}, {10, 43}, { 9, 39}, { 8, 35},
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{ 7, 31}, { 6, 27}, { 5, 23}, { 4, 19},
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{ 3, 15}, { 2, 11}, { 1, 7}, { 0, 3},
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};
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int
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nlm_get_vfbid_mapping(int vfbid)
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{
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int i, nentries;
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struct vfbid_tbl *p;
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if (nlm_is_xlp3xx()) {
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nentries = sizeof(nlm3xx_vfbid)/sizeof(struct vfbid_tbl);
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p = nlm3xx_vfbid;
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} else {
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nentries = sizeof(nlm_vfbid)/sizeof(struct vfbid_tbl);
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p = nlm_vfbid;
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}
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for (i = 0; i < nentries; i++) {
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if (p[i].vfbid == vfbid)
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return (p[i].dest_vc);
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}
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return (-1);
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}
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int
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nlm_get_poe_distvec(int vec, uint32_t *distvec)
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{
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if (vec != 0)
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return (-1); /* we support just vec 0 */
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nlm_calc_poe_distvec(xlp_msg_thread_mask, 0, 0, 0,
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0x1 << XLPGE_RX_VC, distvec);
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return (0);
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}
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/*
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* All our knowledge of chip and board that cannot be detected by probing
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* at run-time goes here
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*/
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void
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xlpge_get_macaddr(uint8_t *macaddr)
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{
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if (board_eeprom_set == 0) {
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/* No luck, take some reasonable value */
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macaddr[0] = 0x00; macaddr[1] = 0x0f; macaddr[2] = 0x30;
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macaddr[3] = 0x20; macaddr[4] = 0x0d; macaddr[5] = 0x5b;
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} else
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memcpy(macaddr, &board_eeprom_buf[EEPROM_MACADDR_OFFSET],
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ETHER_ADDR_LEN);
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}
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static void
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nlm_setup_port_defaults(struct xlp_port_ivars *p)
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{
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p->loopback_mode = 0;
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p->num_channels = 1;
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p->free_desc_sizes = 2048;
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p->vlan_pri_en = 0;
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p->hw_parser_en = 1;
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p->ieee1588_userval = 0;
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p->ieee1588_ptpoff = 0;
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p->ieee1588_tmr1 = 0;
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p->ieee1588_tmr2 = 0;
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p->ieee1588_tmr3 = 0;
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p->ieee1588_inc_intg = 0;
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p->ieee1588_inc_den = 1;
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p->ieee1588_inc_num = 1;
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if (nlm_is_xlp3xx()) {
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p->stg2_fifo_size = XLP3XX_STG2_FIFO_SZ;
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p->eh_fifo_size = XLP3XX_EH_FIFO_SZ;
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p->frout_fifo_size = XLP3XX_FROUT_FIFO_SZ;
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p->ms_fifo_size = XLP3XX_MS_FIFO_SZ;
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p->pkt_fifo_size = XLP3XX_PKT_FIFO_SZ;
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p->pktlen_fifo_size = XLP3XX_PKTLEN_FIFO_SZ;
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p->max_stg2_offset = XLP3XX_MAX_STG2_OFFSET;
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p->max_eh_offset = XLP3XX_MAX_EH_OFFSET;
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p->max_frout_offset = XLP3XX_MAX_FREE_OUT_OFFSET;
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p->max_ms_offset = XLP3XX_MAX_MS_OFFSET;
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p->max_pmem_offset = XLP3XX_MAX_PMEM_OFFSET;
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p->stg1_2_credit = XLP3XX_STG1_2_CREDIT;
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p->stg2_eh_credit = XLP3XX_STG2_EH_CREDIT;
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p->stg2_frout_credit = XLP3XX_STG2_FROUT_CREDIT;
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p->stg2_ms_credit = XLP3XX_STG2_MS_CREDIT;
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} else {
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p->stg2_fifo_size = XLP8XX_STG2_FIFO_SZ;
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p->eh_fifo_size = XLP8XX_EH_FIFO_SZ;
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p->frout_fifo_size = XLP8XX_FROUT_FIFO_SZ;
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p->ms_fifo_size = XLP8XX_MS_FIFO_SZ;
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p->pkt_fifo_size = XLP8XX_PKT_FIFO_SZ;
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p->pktlen_fifo_size = XLP8XX_PKTLEN_FIFO_SZ;
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p->max_stg2_offset = XLP8XX_MAX_STG2_OFFSET;
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p->max_eh_offset = XLP8XX_MAX_EH_OFFSET;
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p->max_frout_offset = XLP8XX_MAX_FREE_OUT_OFFSET;
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p->max_ms_offset = XLP8XX_MAX_MS_OFFSET;
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p->max_pmem_offset = XLP8XX_MAX_PMEM_OFFSET;
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p->stg1_2_credit = XLP8XX_STG1_2_CREDIT;
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p->stg2_eh_credit = XLP8XX_STG2_EH_CREDIT;
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p->stg2_frout_credit = XLP8XX_STG2_FROUT_CREDIT;
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p->stg2_ms_credit = XLP8XX_STG2_MS_CREDIT;
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}
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switch (p->type) {
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case SGMIIC:
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p->num_free_descs = 52;
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p->iface_fifo_size = 13;
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p->rxbuf_size = 128;
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p->rx_slots_reqd = SGMII_CAL_SLOTS;
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p->tx_slots_reqd = SGMII_CAL_SLOTS;
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if (nlm_is_xlp3xx())
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p->pseq_fifo_size = 30;
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else
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p->pseq_fifo_size = 62;
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break;
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case ILC:
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p->num_free_descs = 150;
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p->rxbuf_size = 944;
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p->rx_slots_reqd = IL8_CAL_SLOTS;
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p->tx_slots_reqd = IL8_CAL_SLOTS;
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p->pseq_fifo_size = 225;
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p->iface_fifo_size = 55;
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break;
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case XAUIC:
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default:
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p->num_free_descs = 150;
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p->rxbuf_size = 944;
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p->rx_slots_reqd = XAUI_CAL_SLOTS;
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p->tx_slots_reqd = XAUI_CAL_SLOTS;
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if (nlm_is_xlp3xx()) {
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p->pseq_fifo_size = 120;
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p->iface_fifo_size = 52;
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} else {
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p->pseq_fifo_size = 225;
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p->iface_fifo_size = 55;
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}
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break;
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}
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}
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/* XLP 8XX evaluation boards have the following phy-addr
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* assignment. There are two external mdio buses in XLP --
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* bus 0 and bus 1. The management ports (16 and 17) are
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* on mdio bus 0 while blocks/complexes[0 to 3] are all
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* on mdio bus 1. The phy_addr on bus 0 (mgmt ports 16
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* and 17) match the port numbers.
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* These are the details:
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* block port phy_addr mdio_bus
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* ====================================
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* 0 0 4 1
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* 0 1 7 1
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* 0 2 6 1
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* 0 3 5 1
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* 1 0 8 1
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* 1 1 11 1
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* 1 2 10 1
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* 1 3 9 1
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* 2 0 0 1
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* 2 1 3 1
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* 2 2 2 1
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* 2 3 1 1
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* 3 0 12 1
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* 3 1 15 1
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* 3 2 14 1
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* 3 3 13 1
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*
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* 4 0 16 0
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* 4 1 17 0
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*
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* The XLP 3XX evaluation boards have the following phy-addr
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* assignments.
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* block port phy_addr mdio_bus
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* ====================================
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* 0 0 4 0
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* 0 1 7 0
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* 0 2 6 0
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* 0 3 5 0
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* 1 0 8 0
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* 1 1 11 0
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* 1 2 10 0
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* 1 3 9 0
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*/
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static void
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nlm_board_get_phyaddr(int block, int port, int *mdio, int *phyaddr)
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{
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/* XXXJC: this is a board feature, check for chip not proper */
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if (nlm_is_xlp3xx() || (nlm_is_xlp8xx() && block == 4))
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*mdio = 0;
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else
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*mdio = 1;
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switch (block) {
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case 0: switch (port) {
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case 0: *phyaddr = 4; break;
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case 1: *phyaddr = 7; break;
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case 2: *phyaddr = 6; break;
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case 3: *phyaddr = 5; break;
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}
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break;
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case 1: switch (port) {
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case 0: *phyaddr = 8; break;
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case 1: *phyaddr = 11; break;
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case 2: *phyaddr = 10; break;
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case 3: *phyaddr = 9; break;
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}
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break;
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case 2: switch (port) {
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case 0: *phyaddr = 0; break;
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case 1: *phyaddr = 3; break;
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case 2: *phyaddr = 2; break;
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case 3: *phyaddr = 1; break;
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}
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break;
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case 3: switch (port) {
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case 0: *phyaddr = 12; break;
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case 1: *phyaddr = 15; break;
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case 2: *phyaddr = 14; break;
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case 3: *phyaddr = 13; break;
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}
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break;
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case 4: switch (port) { /* management SGMII */
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case 0: *phyaddr = 16; break;
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case 1: *phyaddr = 17; break;
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}
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break;
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}
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}
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static void
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nlm_print_processor_info(void)
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{
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@ -105,12 +378,17 @@ static int
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nlm_setup_xlp_board(void)
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{
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struct xlp_board_info *boardp;
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int rv;
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struct xlp_node_info *nodep;
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struct xlp_nae_ivars *naep;
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struct xlp_block_ivars *blockp;
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struct xlp_port_ivars *portp;
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uint64_t cpldbase, nae_pcibase;
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int node, block, port, rv, dbtype, usecpld;
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uint8_t *b;
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/* start with a clean slate */
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boardp = &xlp_board_info;
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memset(boardp, 0, sizeof(*boardp));
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memset(boardp, 0, sizeof(xlp_board_info));
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boardp->nodemask = 0x1; /* only node 0 */
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nlm_print_processor_info();
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@ -129,6 +407,114 @@ nlm_setup_xlp_board(void)
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printf("Board Info: Error on EEPROM read (i2c@%d %#X).\n",
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EEPROM_I2CBUS, EEPROM_I2CADDR);
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/* XXXJC: check for boards with right CPLD, for now
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* 4xx PCI cards don't have CPLD with daughter
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* card info */
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usecpld = !nlm_is_xlp4xx();
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for (node = 0; node < XLP_MAX_NODES; node++) {
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if ((boardp->nodemask & (1 << node)) == 0)
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continue;
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nae_pcibase = nlm_get_nae_pcibase(node);
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nodep = &boardp->nodes[node];
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naep = &nodep->nae_ivars;
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naep->node = node;
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naep->nblocks = nae_num_complex(nae_pcibase);
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/* 3xx chips lie shamelessly about this */
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if (nlm_is_xlp3xx())
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naep->nblocks = naep->nblocks - 1;
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naep->blockmask = (1 << naep->nblocks) - 1; /* XXXJC: redundant */
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naep->xauimask = 0x0; /* set this based on daughter card */
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naep->sgmiimask = 0x0; /* set this based on daughter card */
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/* frequency at which network block runs */
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naep->freq = 500;
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/* CRC16 polynomial used for flow table generation */
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naep->flow_crc_poly = 0xffff;
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naep->hw_parser_en = 1;
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naep->prepad_en = 1;
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naep->prepad_size = 3; /* size in 16 byte units */
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naep->ieee_1588_en = 1;
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cpldbase = nlm_board_cpld_base(node, XLP_EVB_CPLD_CHIPSELECT);
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for (block = 0; block < naep->nblocks; block++) {
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blockp = &naep->block_ivars[block];
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blockp->block = block;
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if (usecpld)
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dbtype = nlm_board_cpld_dboard_type(cpldbase,
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block);
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else
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dbtype = DCARD_XAUI; /* default XAUI */
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if (block == 4) {
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/* management block 4 on 8xx */
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blockp->type = SGMIIC;
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blockp->portmask = 0x3;
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naep->sgmiimask |= (1 << block);
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} else {
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switch (dbtype) {
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case DCARD_ILAKEN:
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blockp->type = ILC;
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blockp->portmask = 0x1;
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naep->xauimask |= (1 << block);
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break;
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case DCARD_SGMII:
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blockp->type = SGMIIC;
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blockp->portmask = 0xf;
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naep->sgmiimask |= (1 << block);
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break;
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case DCARD_XAUI:
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default:
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blockp->type = XAUIC;
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blockp->portmask = 0x1;
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naep->xauimask |= (1 << block);
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break;
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}
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}
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for (port = 0; port < PORTS_PER_CMPLX; port++) {
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if ((blockp->portmask & (1 << port)) == 0)
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continue;
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portp = &blockp->port_ivars[port];
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nlm_board_get_phyaddr(block, port,
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&portp->mdio_bus, &portp->phy_addr);
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portp->port = port;
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portp->block = block;
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portp->node = node;
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portp->type = blockp->type;
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nlm_setup_port_defaults(portp);
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}
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}
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}
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/* pretty print network config */
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printf("Network config");
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if (usecpld)
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printf("(from CPLD@%d):\n", XLP_EVB_CPLD_CHIPSELECT);
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else
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printf("(defaults):\n");
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for (node = 0; node < XLP_MAX_NODES; node++) {
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if ((boardp->nodemask & (1 << node)) == 0)
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continue;
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nodep = &boardp->nodes[node];
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naep = &nodep->nae_ivars;
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printf(" NAE@%d Blocks: ", node);
|
||||
for (block = 0; block < naep->nblocks; block++) {
|
||||
char *s = "???";
|
||||
|
||||
blockp = &naep->block_ivars[block];
|
||||
switch (blockp->type) {
|
||||
case SGMIIC : s = "SGMII"; break;
|
||||
case XAUIC : s = "XAUI"; break;
|
||||
case ILC : s = "IL"; break;
|
||||
}
|
||||
printf(" [%d %s]", block, s);
|
||||
}
|
||||
printf("\n");
|
||||
}
|
||||
return (0);
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -32,9 +32,8 @@
|
|||
#ifndef __NLM_BOARD_H__
|
||||
#define __NLM_BOARD_H__
|
||||
|
||||
#define XLP_NAE_NBLOCKS 5
|
||||
#define XLP_NAE_NPORTS 4
|
||||
#define XLP_I2C_MAXDEVICES 8
|
||||
#define XLP_NAE_NBLOCKS 5
|
||||
#define XLP_NAE_NPORTS 4
|
||||
|
||||
/*
|
||||
* EVP board EEPROM info
|
||||
|
|
@ -44,13 +43,62 @@
|
|||
#define EEPROM_SIZE 48
|
||||
#define EEPROM_MACADDR_OFFSET 2
|
||||
|
||||
/*
|
||||
* EVP board CPLD chip select and daughter card info field
|
||||
*/
|
||||
#define XLP_EVB_CPLD_CHIPSELECT 2
|
||||
|
||||
#define DCARD_ILAKEN 0x0
|
||||
#define DCARD_SGMII 0x1
|
||||
#define DCARD_XAUI 0x2
|
||||
#define DCARD_NOT_PRSNT 0x3
|
||||
|
||||
#if !defined(LOCORE) && !defined(__ASSEMBLY__)
|
||||
/*
|
||||
* NAE configuration
|
||||
*/
|
||||
|
||||
struct xlp_port_ivars {
|
||||
int port;
|
||||
int block;
|
||||
int node;
|
||||
int type;
|
||||
int phy_addr;
|
||||
int mdio_bus;
|
||||
int loopback_mode;
|
||||
int num_channels;
|
||||
int free_desc_sizes;
|
||||
int num_free_descs;
|
||||
int pseq_fifo_size;
|
||||
int iface_fifo_size;
|
||||
int rxbuf_size;
|
||||
int rx_slots_reqd;
|
||||
int tx_slots_reqd;
|
||||
int vlan_pri_en;
|
||||
int stg2_fifo_size;
|
||||
int eh_fifo_size;
|
||||
int frout_fifo_size;
|
||||
int ms_fifo_size;
|
||||
int pkt_fifo_size;
|
||||
int pktlen_fifo_size;
|
||||
int max_stg2_offset;
|
||||
int max_eh_offset;
|
||||
int max_frout_offset;
|
||||
int max_ms_offset;
|
||||
int max_pmem_offset;
|
||||
int stg1_2_credit;
|
||||
int stg2_eh_credit;
|
||||
int stg2_frout_credit;
|
||||
int stg2_ms_credit;
|
||||
int hw_parser_en;
|
||||
u_int ieee1588_inc_intg;
|
||||
u_int ieee1588_inc_den;
|
||||
u_int ieee1588_inc_num;
|
||||
uint64_t ieee1588_userval;
|
||||
uint64_t ieee1588_ptpoff;
|
||||
uint64_t ieee1588_tmr1;
|
||||
uint64_t ieee1588_tmr2;
|
||||
uint64_t ieee1588_tmr3;
|
||||
};
|
||||
|
||||
struct xlp_block_ivars {
|
||||
|
|
@ -62,7 +110,16 @@ struct xlp_block_ivars {
|
|||
|
||||
struct xlp_nae_ivars {
|
||||
int node;
|
||||
int nblocks;
|
||||
u_int blockmask;
|
||||
u_int xauimask;
|
||||
u_int sgmiimask;
|
||||
int freq;
|
||||
u_int flow_crc_poly;
|
||||
u_int hw_parser_en;
|
||||
u_int prepad_en;
|
||||
u_int prepad_size; /* size in 16 byte units */
|
||||
u_int ieee_1588_en;
|
||||
struct xlp_block_ivars block_ivars[XLP_NAE_NBLOCKS];
|
||||
};
|
||||
|
||||
|
|
@ -73,8 +130,16 @@ struct xlp_board_info {
|
|||
} nodes[XLP_MAX_NODES];
|
||||
};
|
||||
|
||||
extern struct xlp_board_info xlp_board_info;
|
||||
|
||||
/* Network configuration */
|
||||
int nlm_get_vfbid_mapping(int);
|
||||
int nlm_get_poe_distvec(int vec, uint32_t *distvec);
|
||||
void xlpge_get_macaddr(uint8_t *macaddr);
|
||||
|
||||
int nlm_board_info_setup(void);
|
||||
|
||||
/* EEPROM & CPLD */
|
||||
int nlm_board_eeprom_read(int node, int i2cbus, int addr, int offs,
|
||||
uint8_t *buf,int sz);
|
||||
uint64_t nlm_board_cpld_base(int node, int chipselect);
|
||||
|
|
@ -82,6 +147,6 @@ int nlm_board_cpld_majorversion(uint64_t cpldbase);
|
|||
int nlm_board_cpld_minorversion(uint64_t cpldbase);
|
||||
void nlm_board_cpld_reset(uint64_t cpldbase);
|
||||
int nlm_board_cpld_dboard_type(uint64_t cpldbase, int slot);
|
||||
#endif
|
||||
|
||||
#endif
|
||||
#endif
|
||||
|
|
|
|||
301
sys/mips/nlm/dev/net/mdio.c
Normal file
301
sys/mips/nlm/dev/net/mdio.c
Normal file
|
|
@ -0,0 +1,301 @@
|
|||
/*-
|
||||
* Copyright (c) 2003-2012 Broadcom Corporation
|
||||
* All Rights Reserved
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY BROADCOM ``AS IS'' AND ANY EXPRESS OR
|
||||
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
* ARE DISCLAIMED. IN NO EVENT SHALL BROADCOM OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
|
||||
* BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
|
||||
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
|
||||
* OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
|
||||
* IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#include <sys/cdefs.h>
|
||||
__FBSDID("$FreeBSD$");
|
||||
#include <sys/types.h>
|
||||
#include <sys/systm.h>
|
||||
|
||||
#include <mips/nlm/hal/mips-extns.h>
|
||||
#include <mips/nlm/hal/haldefs.h>
|
||||
#include <mips/nlm/hal/iomap.h>
|
||||
#include <mips/nlm/hal/sys.h>
|
||||
#include <mips/nlm/hal/nae.h>
|
||||
#include <mips/nlm/hal/mdio.h>
|
||||
|
||||
/* Internal MDIO READ/WRITE Routines */
|
||||
int
|
||||
nlm_int_gmac_mdio_read(uint64_t nae_base, int bus, int block,
|
||||
int intf_type, int phyaddr, int regidx)
|
||||
{
|
||||
uint32_t mdio_ld_cmd;
|
||||
uint32_t ctrlval;
|
||||
|
||||
ctrlval = INT_MDIO_CTRL_SMP |
|
||||
(phyaddr << INT_MDIO_CTRL_PHYADDR_POS) |
|
||||
(regidx << INT_MDIO_CTRL_DEVTYPE_POS) |
|
||||
(2 << INT_MDIO_CTRL_OP_POS) |
|
||||
(1 << INT_MDIO_CTRL_ST_POS) |
|
||||
(7 << INT_MDIO_CTRL_XDIV_POS) |
|
||||
(2 << INT_MDIO_CTRL_TA_POS) |
|
||||
(2 << INT_MDIO_CTRL_MIIM_POS) |
|
||||
(1 << INT_MDIO_CTRL_MCDIV_POS);
|
||||
|
||||
mdio_ld_cmd = nlm_read_nae_reg(nae_base,
|
||||
NAE_REG(block, intf_type, (INT_MDIO_CTRL + bus * 4)));
|
||||
if (mdio_ld_cmd & INT_MDIO_CTRL_CMD_LOAD) {
|
||||
nlm_write_nae_reg(nae_base,
|
||||
NAE_REG(block, intf_type, (INT_MDIO_CTRL + bus*4)),
|
||||
(mdio_ld_cmd & ~INT_MDIO_CTRL_CMD_LOAD));
|
||||
}
|
||||
|
||||
nlm_write_nae_reg(nae_base,
|
||||
NAE_REG(block, intf_type, (INT_MDIO_CTRL + bus * 4)),
|
||||
ctrlval);
|
||||
|
||||
/* Toggle Load Cmd Bit */
|
||||
nlm_write_nae_reg(nae_base,
|
||||
NAE_REG(block, intf_type, (INT_MDIO_CTRL + bus * 4)),
|
||||
ctrlval | (1 << INT_MDIO_CTRL_LOAD_POS));
|
||||
|
||||
/* poll master busy bit until it is not busy */
|
||||
while(nlm_read_nae_reg(nae_base,
|
||||
NAE_REG(block, intf_type, (INT_MDIO_RD_STAT + bus * 4))) &
|
||||
INT_MDIO_STAT_MBSY) {
|
||||
}
|
||||
|
||||
nlm_write_nae_reg(nae_base,
|
||||
NAE_REG(block, intf_type, (INT_MDIO_CTRL + bus * 4)),
|
||||
ctrlval);
|
||||
|
||||
/* Read the data back */
|
||||
return nlm_read_nae_reg(nae_base,
|
||||
NAE_REG(block, intf_type, (INT_MDIO_RD_STAT + bus * 4)));
|
||||
}
|
||||
|
||||
/* Internal MDIO WRITE Routines */
|
||||
int
|
||||
nlm_int_gmac_mdio_write(uint64_t nae_base, int bus, int block,
|
||||
int intf_type, int phyaddr, int regidx, uint16_t val)
|
||||
{
|
||||
uint32_t mdio_ld_cmd;
|
||||
uint32_t ctrlval;
|
||||
|
||||
ctrlval = INT_MDIO_CTRL_SMP |
|
||||
(phyaddr << INT_MDIO_CTRL_PHYADDR_POS) |
|
||||
(regidx << INT_MDIO_CTRL_DEVTYPE_POS) |
|
||||
(1 << INT_MDIO_CTRL_OP_POS) |
|
||||
(1 << INT_MDIO_CTRL_ST_POS) |
|
||||
(7 << INT_MDIO_CTRL_XDIV_POS) |
|
||||
(2 << INT_MDIO_CTRL_TA_POS) |
|
||||
(1 << INT_MDIO_CTRL_MIIM_POS) |
|
||||
(1 << INT_MDIO_CTRL_MCDIV_POS);
|
||||
|
||||
mdio_ld_cmd = nlm_read_nae_reg(nae_base,
|
||||
NAE_REG(block, intf_type, (INT_MDIO_CTRL + bus * 4)));
|
||||
if (mdio_ld_cmd & INT_MDIO_CTRL_CMD_LOAD) {
|
||||
nlm_write_nae_reg(nae_base,
|
||||
NAE_REG(block, intf_type, (INT_MDIO_CTRL + bus*4)),
|
||||
(mdio_ld_cmd & ~INT_MDIO_CTRL_CMD_LOAD));
|
||||
}
|
||||
|
||||
/* load data into ctrl data reg */
|
||||
nlm_write_nae_reg(nae_base,
|
||||
NAE_REG(block, intf_type, (INT_MDIO_CTRL_DATA + bus * 4)),
|
||||
val);
|
||||
|
||||
nlm_write_nae_reg(nae_base,
|
||||
NAE_REG(block, intf_type, (INT_MDIO_CTRL + bus * 4)),
|
||||
ctrlval);
|
||||
|
||||
nlm_write_nae_reg(nae_base,
|
||||
NAE_REG(block, intf_type, (INT_MDIO_CTRL + bus * 4)),
|
||||
ctrlval | (1 << INT_MDIO_CTRL_LOAD_POS));
|
||||
|
||||
/* poll master busy bit until it is not busy */
|
||||
while(nlm_read_nae_reg(nae_base,
|
||||
NAE_REG(block, intf_type, (INT_MDIO_RD_STAT + bus * 4))) &
|
||||
INT_MDIO_STAT_MBSY) {
|
||||
}
|
||||
|
||||
nlm_write_nae_reg(nae_base,
|
||||
NAE_REG(block, intf_type, (INT_MDIO_CTRL + bus * 4)),
|
||||
ctrlval);
|
||||
|
||||
return (0);
|
||||
}
|
||||
|
||||
int
|
||||
nlm_int_gmac_mdio_reset(uint64_t nae_base, int bus, int block,
|
||||
int intf_type)
|
||||
{
|
||||
uint32_t val;
|
||||
|
||||
val = (7 << INT_MDIO_CTRL_XDIV_POS) |
|
||||
(1 << INT_MDIO_CTRL_MCDIV_POS);
|
||||
|
||||
nlm_write_nae_reg(nae_base,
|
||||
NAE_REG(block, intf_type, (INT_MDIO_CTRL + bus * 4)),
|
||||
val | INT_MDIO_CTRL_RST);
|
||||
|
||||
nlm_write_nae_reg(nae_base,
|
||||
NAE_REG(block, intf_type, (INT_MDIO_CTRL + bus * 4)),
|
||||
val);
|
||||
|
||||
return (0);
|
||||
}
|
||||
|
||||
/*
|
||||
* nae_gmac_mdio_read - Read sgmii phy register
|
||||
*
|
||||
* Input parameters:
|
||||
* bus - bus number, nae has two external gmac bus: 0 and 1
|
||||
* phyaddr - PHY's address
|
||||
* regidx - index of register to read
|
||||
*
|
||||
* Return value:
|
||||
* value read (16 bits), or 0xffffffff if an error occurred.
|
||||
*/
|
||||
int
|
||||
nlm_gmac_mdio_read(uint64_t nae_base, int bus, int block,
|
||||
int intf_type, int phyaddr, int regidx)
|
||||
{
|
||||
uint32_t mdio_ld_cmd;
|
||||
uint32_t val;
|
||||
|
||||
val = EXT_G_MDIO_CMD_SP |
|
||||
(phyaddr << EXT_G_MDIO_PHYADDR_POS) |
|
||||
(regidx << EXT_G_MDIO_REGADDR_POS) |
|
||||
EXT_G_MDIO_DIV;
|
||||
|
||||
mdio_ld_cmd = nlm_read_nae_reg(nae_base, NAE_REG(block, intf_type,
|
||||
(EXT_G0_MDIO_CTRL + bus * 4)));
|
||||
if (mdio_ld_cmd & EXT_G_MDIO_CMD_LCD) {
|
||||
nlm_write_nae_reg(nae_base,
|
||||
NAE_REG(block, intf_type, (EXT_G0_MDIO_CTRL+bus*4)),
|
||||
(mdio_ld_cmd & ~EXT_G_MDIO_CMD_LCD));
|
||||
while(nlm_read_nae_reg(nae_base,
|
||||
NAE_REG(block, intf_type,
|
||||
(EXT_G0_MDIO_RD_STAT + bus * 4))) &
|
||||
EXT_G_MDIO_STAT_MBSY);
|
||||
}
|
||||
|
||||
nlm_write_nae_reg(nae_base,
|
||||
NAE_REG(block, intf_type, (EXT_G0_MDIO_CTRL+bus*4)),
|
||||
val);
|
||||
|
||||
nlm_write_nae_reg(nae_base,
|
||||
NAE_REG(block, intf_type, (EXT_G0_MDIO_CTRL+bus*4)),
|
||||
val | (1<<18));
|
||||
|
||||
/* poll master busy bit until it is not busy */
|
||||
while(nlm_read_nae_reg(nae_base,
|
||||
NAE_REG(block, intf_type, (EXT_G0_MDIO_RD_STAT + bus * 4))) &
|
||||
EXT_G_MDIO_STAT_MBSY);
|
||||
|
||||
nlm_write_nae_reg(nae_base,
|
||||
NAE_REG(block, intf_type, (EXT_G0_MDIO_CTRL+bus*4)),
|
||||
val);
|
||||
|
||||
/* Read the data back */
|
||||
return nlm_read_nae_reg(nae_base,
|
||||
NAE_REG(block, intf_type, (EXT_G0_MDIO_RD_STAT + bus * 4)));
|
||||
}
|
||||
|
||||
/*
|
||||
* nae_gmac_mdio_write -Write sgmac mii PHY register.
|
||||
*
|
||||
* Input parameters:
|
||||
* bus - bus number, nae has two external gmac bus: 0 and 1
|
||||
* phyaddr - PHY to use
|
||||
* regidx - register within the PHY
|
||||
* val - data to write to register
|
||||
*
|
||||
* Return value:
|
||||
* 0 - success
|
||||
*/
|
||||
int
|
||||
nlm_gmac_mdio_write(uint64_t nae_base, int bus, int block,
|
||||
int intf_type, int phyaddr, int regidx, uint16_t val)
|
||||
{
|
||||
uint32_t mdio_ld_cmd;
|
||||
uint32_t ctrlval;
|
||||
|
||||
ctrlval = EXT_G_MDIO_CMD_SP |
|
||||
(phyaddr << EXT_G_MDIO_PHYADDR_POS) |
|
||||
(regidx << EXT_G_MDIO_REGADDR_POS) |
|
||||
EXT_G_MDIO_DIV;
|
||||
|
||||
mdio_ld_cmd = nlm_read_nae_reg(nae_base, NAE_REG(block, intf_type,
|
||||
(EXT_G0_MDIO_CTRL + bus * 4)));
|
||||
if (mdio_ld_cmd & EXT_G_MDIO_CMD_LCD) {
|
||||
nlm_write_nae_reg(nae_base,
|
||||
NAE_REG(block, intf_type, (EXT_G0_MDIO_CTRL+bus*4)),
|
||||
(mdio_ld_cmd & ~EXT_G_MDIO_CMD_LCD));
|
||||
while(nlm_read_nae_reg(nae_base,
|
||||
NAE_REG(block, intf_type,
|
||||
(EXT_G0_MDIO_RD_STAT + bus * 4))) &
|
||||
EXT_G_MDIO_STAT_MBSY);
|
||||
}
|
||||
|
||||
/* load data into ctrl data reg */
|
||||
nlm_write_nae_reg(nae_base,
|
||||
NAE_REG(block, intf_type, (EXT_G0_MDIO_CTRL_DATA+bus*4)),
|
||||
val);
|
||||
|
||||
nlm_write_nae_reg(nae_base,
|
||||
NAE_REG(block, intf_type, (EXT_G0_MDIO_CTRL+bus*4)),
|
||||
ctrlval);
|
||||
|
||||
nlm_write_nae_reg(nae_base,
|
||||
NAE_REG(block, intf_type, (EXT_G0_MDIO_CTRL+bus*4)),
|
||||
ctrlval | EXT_G_MDIO_CMD_LCD);
|
||||
|
||||
/* poll master busy bit until it is not busy */
|
||||
while(nlm_read_nae_reg(nae_base,
|
||||
NAE_REG(block, intf_type,
|
||||
(EXT_G0_MDIO_RD_STAT + bus * 4))) & EXT_G_MDIO_STAT_MBSY);
|
||||
|
||||
nlm_write_nae_reg(nae_base,
|
||||
NAE_REG(block, intf_type, (EXT_G0_MDIO_CTRL+bus*4)),
|
||||
ctrlval);
|
||||
|
||||
return (0);
|
||||
}
|
||||
|
||||
/*
|
||||
* nae_gmac_mdio_reset -Reset sgmii mdio module.
|
||||
*
|
||||
* Input parameters:
|
||||
* bus - bus number, nae has two external gmac bus: 0 and 1
|
||||
*
|
||||
* Return value:
|
||||
* 0 - success
|
||||
*/
|
||||
int
|
||||
nlm_gmac_mdio_reset(uint64_t nae_base, int bus, int block,
|
||||
int intf_type)
|
||||
{
|
||||
nlm_write_nae_reg(nae_base,
|
||||
NAE_REG(block, intf_type, (EXT_G0_MDIO_CTRL+bus*4)),
|
||||
EXT_G_MDIO_MMRST | EXT_G_MDIO_DIV);
|
||||
nlm_write_nae_reg(nae_base,
|
||||
NAE_REG(block, intf_type, (EXT_G0_MDIO_CTRL+bus*4)),
|
||||
EXT_G_MDIO_DIV);
|
||||
return (0);
|
||||
}
|
||||
1536
sys/mips/nlm/dev/net/nae.c
Normal file
1536
sys/mips/nlm/dev/net/nae.c
Normal file
File diff suppressed because it is too large
Load diff
216
sys/mips/nlm/dev/net/sgmii.c
Normal file
216
sys/mips/nlm/dev/net/sgmii.c
Normal file
|
|
@ -0,0 +1,216 @@
|
|||
/*-
|
||||
* Copyright (c) 2003-2012 Broadcom Corporation
|
||||
* All Rights Reserved
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY BROADCOM ``AS IS'' AND ANY EXPRESS OR
|
||||
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
* ARE DISCLAIMED. IN NO EVENT SHALL BROADCOM OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
|
||||
* BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
|
||||
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
|
||||
* OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
|
||||
* IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#include <sys/cdefs.h>
|
||||
__FBSDID("$FreeBSD$");
|
||||
#include <sys/types.h>
|
||||
#include <sys/systm.h>
|
||||
|
||||
#include <mips/nlm/hal/mips-extns.h>
|
||||
#include <mips/nlm/hal/haldefs.h>
|
||||
#include <mips/nlm/hal/iomap.h>
|
||||
#include <mips/nlm/hal/sys.h>
|
||||
#include <mips/nlm/hal/nae.h>
|
||||
#include <mips/nlm/hal/mdio.h>
|
||||
#include <mips/nlm/hal/sgmii.h>
|
||||
|
||||
void
|
||||
nlm_configure_sgmii_interface(uint64_t nae_base, int block, int port,
|
||||
int mtu, int loopback)
|
||||
{
|
||||
uint32_t data1, data2;
|
||||
|
||||
/* Apply a soft reset */
|
||||
data1 = (0x1 << 31); /* soft reset */
|
||||
if (loopback)
|
||||
data1 |= (0x01 << 8);
|
||||
data1 |= (0x01 << 2); /* Rx enable */
|
||||
data1 |= 0x01; /* Tx enable */
|
||||
nlm_write_nae_reg(nae_base, NAE_REG(block, port, MAC_CONF1), data1);
|
||||
|
||||
data2 = (0x7 << 12) | /* pre-amble length=7 */
|
||||
(0x2 << 8) | /* byteMode */
|
||||
0x1; /* fullDuplex */
|
||||
nlm_write_nae_reg(nae_base, NAE_REG(block, port, MAC_CONF2), data2);
|
||||
|
||||
/* Remove a soft reset */
|
||||
data1 &= ~(0x01 << 31);
|
||||
nlm_write_nae_reg(nae_base, NAE_REG(block, port, MAC_CONF1), data1);
|
||||
|
||||
/* setup sgmii max frame length */
|
||||
nlm_write_nae_reg(nae_base, SGMII_MAX_FRAME(block, port), mtu);
|
||||
}
|
||||
|
||||
void
|
||||
nlm_sgmii_pcs_init(uint64_t nae_base, uint32_t cplx_mask)
|
||||
{
|
||||
/* reset internal MDIO */
|
||||
nlm_int_gmac_mdio_reset(nae_base, 0, BLOCK_7, LANE_CFG);
|
||||
|
||||
/* reset external MDIO */
|
||||
nlm_gmac_mdio_reset(nae_base, 0, BLOCK_7, LANE_CFG);
|
||||
nlm_gmac_mdio_reset(nae_base, 1, BLOCK_7, LANE_CFG);
|
||||
|
||||
xlp_nae_config_lane_gmac(nae_base, cplx_mask);
|
||||
}
|
||||
|
||||
void
|
||||
nlm_nae_setup_mac(uint64_t nae_base, int nblock, int iface, int reset,
|
||||
int rx_en, int tx_en, int speed, int duplex)
|
||||
{
|
||||
uint32_t mac_cfg1, mac_cfg2, netwk_inf;
|
||||
|
||||
mac_cfg1 = nlm_read_nae_reg(nae_base,
|
||||
SGMII_MAC_CONF1(nblock,iface));
|
||||
mac_cfg2 = nlm_read_nae_reg(nae_base,
|
||||
SGMII_MAC_CONF2(nblock,iface));
|
||||
netwk_inf = nlm_read_nae_reg(nae_base,
|
||||
SGMII_NET_IFACE_CTRL(nblock, iface));
|
||||
|
||||
mac_cfg1 &= ~(0x1 << 31); /* remove reset */
|
||||
mac_cfg1 &= ~(0x1 << 2); /* remove rx */
|
||||
mac_cfg1 &= ~(0x1); /* remove tx */
|
||||
mac_cfg2 &= ~(0x3 << 8); /* remove interface mode bits */
|
||||
mac_cfg2 &= ~(0x1); /* remove duplex */
|
||||
netwk_inf &= ~(0x1 << 2); /* remove tx */
|
||||
netwk_inf &= ~(0x3); /* remove speed */
|
||||
|
||||
switch (speed) {
|
||||
case NLM_SGMII_SPEED_10:
|
||||
netwk_inf |= 0x0; /* 2.5 Mhz clock for 10 Mbps */
|
||||
mac_cfg2 |= (0x1 << 8); /* enable 10/100 Mbps */
|
||||
break;
|
||||
case NLM_SGMII_SPEED_100:
|
||||
netwk_inf |= 0x1; /* 25 Mhz clock for 100 Mbps */
|
||||
mac_cfg2 |= (0x1 << 8); /* enable 10/100 Mbps */
|
||||
break;
|
||||
default: /* make it as 1G */
|
||||
netwk_inf |= 0x2; /* 125 Mhz clock for 1G */
|
||||
mac_cfg2 |= (0x2 << 8); /* enable 1G */
|
||||
break;
|
||||
}
|
||||
|
||||
if (reset)
|
||||
mac_cfg1 |= (0x1 << 31); /* set reset */
|
||||
|
||||
if (rx_en)
|
||||
mac_cfg1 |= (0x1 << 2); /* set rx */
|
||||
|
||||
nlm_write_nae_reg(nae_base,
|
||||
SGMII_NET_IFACE_CTRL(nblock, iface),
|
||||
netwk_inf);
|
||||
|
||||
if (tx_en) {
|
||||
mac_cfg1 |= 0x1; /* set tx */
|
||||
netwk_inf |= (0x1 << 2); /* set tx */
|
||||
}
|
||||
|
||||
switch (duplex) {
|
||||
case NLM_SGMII_DUPLEX_HALF:
|
||||
/* duplexity is already set to half duplex */
|
||||
break;
|
||||
default:
|
||||
mac_cfg2 |= 0x1; /* set full duplex */
|
||||
}
|
||||
|
||||
nlm_write_nae_reg(nae_base, SGMII_MAC_CONF1(nblock, iface), mac_cfg1);
|
||||
nlm_write_nae_reg(nae_base, SGMII_MAC_CONF2(nblock, iface), mac_cfg2);
|
||||
nlm_write_nae_reg(nae_base, SGMII_NET_IFACE_CTRL(nblock, iface),
|
||||
netwk_inf);
|
||||
}
|
||||
|
||||
void
|
||||
nlm_nae_setup_rx_mode_sgmii(uint64_t base, int nblock, int iface, int port_type,
|
||||
int broadcast_en, int multicast_en, int pause_en, int promisc_en)
|
||||
{
|
||||
uint32_t val;
|
||||
|
||||
/* bit[17] of vlan_typefilter - allows packet matching in MAC.
|
||||
* When DA filtering is disabled, this bit and bit[16] should
|
||||
* be zero.
|
||||
* bit[16] of vlan_typefilter - Allows hash matching to be used
|
||||
* for DA filtering. When DA filtering is disabled, this bit and
|
||||
* bit[17] should be zero.
|
||||
* Both bits have to be set only if you want to turn on both
|
||||
* features / modes.
|
||||
*/
|
||||
if (promisc_en == 1) {
|
||||
val = nlm_read_nae_reg(base,
|
||||
SGMII_NETIOR_VLANTYPE_FILTER(nblock, iface));
|
||||
val &= (~(0x3 << 16));
|
||||
nlm_write_nae_reg(base,
|
||||
SGMII_NETIOR_VLANTYPE_FILTER(nblock, iface), val);
|
||||
} else {
|
||||
val = nlm_read_nae_reg(base,
|
||||
SGMII_NETIOR_VLANTYPE_FILTER(nblock, iface));
|
||||
val |= (0x1 << 17);
|
||||
nlm_write_nae_reg(base,
|
||||
SGMII_NETIOR_VLANTYPE_FILTER(nblock, iface), val);
|
||||
}
|
||||
|
||||
val = ((broadcast_en & 0x1) << 10) |
|
||||
((pause_en & 0x1) << 9) |
|
||||
((multicast_en & 0x1) << 8) |
|
||||
((promisc_en & 0x1) << 7) | /* unicast_enable - enables promisc mode */
|
||||
1; /* MAC address is always valid */
|
||||
|
||||
nlm_write_nae_reg(base, SGMII_MAC_FILTER_CONFIG(nblock, iface), val);
|
||||
|
||||
}
|
||||
|
||||
void
|
||||
nlm_nae_setup_mac_addr_sgmii(uint64_t base, int nblock, int iface,
|
||||
int port_type, uint8_t *mac_addr)
|
||||
{
|
||||
nlm_write_nae_reg(base,
|
||||
SGMII_MAC_ADDR0_LO(nblock, iface),
|
||||
(mac_addr[5] << 24) |
|
||||
(mac_addr[4] << 16) |
|
||||
(mac_addr[3] << 8) |
|
||||
mac_addr[2]);
|
||||
|
||||
nlm_write_nae_reg(base,
|
||||
SGMII_MAC_ADDR0_HI(nblock, iface),
|
||||
(mac_addr[1] << 24) |
|
||||
(mac_addr[0] << 16));
|
||||
|
||||
nlm_write_nae_reg(base,
|
||||
SGMII_MAC_ADDR_MASK0_LO(nblock, iface),
|
||||
0xffffffff);
|
||||
nlm_write_nae_reg(base,
|
||||
SGMII_MAC_ADDR_MASK0_HI(nblock, iface),
|
||||
0xffffffff);
|
||||
|
||||
nlm_nae_setup_rx_mode_sgmii(base, nblock, iface,
|
||||
SGMIIC,
|
||||
1, /* broadcast enabled */
|
||||
1, /* multicast enabled */
|
||||
0, /* do not accept pause frames */
|
||||
0 /* promisc mode disabled */
|
||||
);
|
||||
}
|
||||
66
sys/mips/nlm/dev/net/ucore/crt0_basic.S
Normal file
66
sys/mips/nlm/dev/net/ucore/crt0_basic.S
Normal file
|
|
@ -0,0 +1,66 @@
|
|||
/*-
|
||||
* Copyright (c) 2003-2012 Broadcom Corporation
|
||||
* All Rights Reserved
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY BROADCOM ``AS IS'' AND ANY EXPRESS OR
|
||||
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
* ARE DISCLAIMED. IN NO EVENT SHALL BROADCOM OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
|
||||
* BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
|
||||
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
|
||||
* OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
|
||||
* IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
* $FreeBSD$
|
||||
*/
|
||||
|
||||
#include <machine/asm.h>
|
||||
|
||||
.text
|
||||
.align 2
|
||||
.globl _start
|
||||
.ent _start
|
||||
_start:
|
||||
.set noreorder
|
||||
la gp, _gp
|
||||
.end _start
|
||||
|
||||
.globl __stack
|
||||
|
||||
.ent zerobss
|
||||
zerobss:
|
||||
la v0, _fbss
|
||||
la v1, _end
|
||||
3:
|
||||
sw zero, 0(v0)
|
||||
bltu v0,v1,3b
|
||||
addiu v0,v0,4 # executed in delay slot
|
||||
la sp, __stack # set stack pointer
|
||||
.end zerobss
|
||||
|
||||
.ent init
|
||||
init:
|
||||
addiu a1,sp,32 # argv = sp + 32
|
||||
addiu a2,sp,40 # envp = sp + 40
|
||||
sw zero,(a1) # argv[argc] = 0
|
||||
sw zero,(a2) # envp[0] = 0
|
||||
jal main # call the program start function
|
||||
move a0,zero # set argc to 0
|
||||
1: b 1b
|
||||
nop
|
||||
.end init
|
||||
|
||||
162
sys/mips/nlm/dev/net/ucore/ld.ucore.S
Normal file
162
sys/mips/nlm/dev/net/ucore/ld.ucore.S
Normal file
|
|
@ -0,0 +1,162 @@
|
|||
/*-
|
||||
* Copyright (c) 2003-2012 Broadcom Corporation
|
||||
* All Rights Reserved
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY BROADCOM ``AS IS'' AND ANY EXPRESS OR
|
||||
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
* ARE DISCLAIMED. IN NO EVENT SHALL BROADCOM OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
|
||||
* BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
|
||||
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
|
||||
* OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
|
||||
* IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
* $FreeBSD$
|
||||
*/
|
||||
|
||||
ENTRY(_start)
|
||||
OUTPUT_FORMAT(elf32-tradbigmips)
|
||||
__DYNAMIC = 0;
|
||||
|
||||
SECTIONS
|
||||
{
|
||||
. = 0x0;
|
||||
_loadaddr = . ;
|
||||
|
||||
/* ----------------------------------------- */
|
||||
|
||||
.text : {
|
||||
_ftext = . ;
|
||||
PROVIDE (eprol = .);
|
||||
_shim_reg = . ;
|
||||
*(.text)
|
||||
*(.text.*)
|
||||
*(.gnu.linkonce.t*)
|
||||
*(.mips16.fn.*)
|
||||
*(.mips16.call.*)
|
||||
}
|
||||
.init : {
|
||||
KEEP(*(.init))
|
||||
*(.init)
|
||||
}
|
||||
.fini : {
|
||||
*(.fini)
|
||||
}
|
||||
.rel.sdata : {
|
||||
PROVIDE (__runtime_reloc_start = .);
|
||||
*(.rel.sdata)
|
||||
PROVIDE (__runtime_reloc_stop = .);
|
||||
}
|
||||
PROVIDE (etext = .);
|
||||
.ctors :
|
||||
{
|
||||
KEEP (*crtbegin.o(.ctors))
|
||||
KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
|
||||
KEEP (*(SORT(.ctors.*)))
|
||||
KEEP (*(.ctors))
|
||||
}
|
||||
.dtors :
|
||||
{
|
||||
KEEP (*crtbegin.o(.dtors))
|
||||
KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
|
||||
KEEP (*(SORT(.dtors.*)))
|
||||
KEEP (*(.dtors))
|
||||
}
|
||||
. = .;
|
||||
.rodata : {
|
||||
*(.rdata)
|
||||
*(.rodata)
|
||||
*(.rodata.*)
|
||||
*(.gnu.linkonce.r*)
|
||||
}
|
||||
. = . + (0x1000 - .) ;
|
||||
|
||||
/* ----------------------------------------- */
|
||||
|
||||
. = 0x8000 ;
|
||||
magicstart = . ;
|
||||
.magicregs : {
|
||||
*(.magicregs)
|
||||
}
|
||||
magicend = . ;
|
||||
|
||||
/* ----------------------------------------- */
|
||||
|
||||
. = 0x18000 ;
|
||||
shmemstart = . ;
|
||||
.sharedmem : {
|
||||
*(.sharedmem)
|
||||
}
|
||||
shmemend = . ;
|
||||
|
||||
/* ----------------------------------------- */
|
||||
|
||||
. = 0xFF800 ;
|
||||
.data : {
|
||||
*(.data)
|
||||
*(.data.*)
|
||||
*(.gnu.linkonce.d*)
|
||||
}
|
||||
. = ALIGN(8);
|
||||
.lit8 : {
|
||||
*(.lit8)
|
||||
}
|
||||
.lit4 : {
|
||||
*(.lit4)
|
||||
}
|
||||
.sdata : {
|
||||
*(.sdata)
|
||||
*(.sdata.*)
|
||||
*(.gnu.linkonce.s*)
|
||||
}
|
||||
. = ALIGN (8);
|
||||
PROVIDE (edata = .);
|
||||
_edata = .;
|
||||
_fbss = .;
|
||||
.sbss : {
|
||||
*(.sbss)
|
||||
*(.scommon)
|
||||
}
|
||||
.bss : {
|
||||
_bss_start = . ;
|
||||
*(.bss)
|
||||
*(COMMON)
|
||||
}
|
||||
_bss_end = . ;
|
||||
_end = .;
|
||||
|
||||
_gp = . ;
|
||||
__global = _gp ;
|
||||
. = ALIGN (8);
|
||||
|
||||
PROVIDE(__stackmarker = .) ;
|
||||
|
||||
. = 0xFFA00 ;
|
||||
|
||||
/* 32 + 4(argc) + 4(argv), aligned to 64 */
|
||||
PROVIDE(__stack = . - 64);
|
||||
|
||||
/* ----------------------------------------- */
|
||||
|
||||
. = 0xFFE00 ;
|
||||
.pktbuf : {
|
||||
*(.pktbuf)
|
||||
}
|
||||
. = . + (0x100000 - .) ;
|
||||
|
||||
PROVIDE(_endaddr = 0x0 + 0x100000);
|
||||
}
|
||||
356
sys/mips/nlm/dev/net/ucore/ucore.h
Normal file
356
sys/mips/nlm/dev/net/ucore/ucore.h
Normal file
|
|
@ -0,0 +1,356 @@
|
|||
/*-
|
||||
* Copyright (c) 2003-2012 Broadcom Corporation
|
||||
* All Rights Reserved
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY BROADCOM ``AS IS'' AND ANY EXPRESS OR
|
||||
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
* ARE DISCLAIMED. IN NO EVENT SHALL BROADCOM OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
|
||||
* BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
|
||||
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
|
||||
* OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
|
||||
* IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
* $FreeBSD$
|
||||
*/
|
||||
#ifndef __NLM_UCORE_H__
|
||||
#define __NLM_UCORE_H__
|
||||
|
||||
/* Microcode registers */
|
||||
#define UCORE_OUTBUF_DONE 0x8000
|
||||
#define UCORE_RX_PKT_RDY 0x8004
|
||||
#define UCORE_RX_PKT_INFO 0x8008
|
||||
#define UCORE_CAM0 0x800c
|
||||
#define UCORE_CAM1 0x8010
|
||||
#define UCORE_CAM2 0x8014
|
||||
#define UCORE_CAM3 0x8018
|
||||
#define UCORE_CAM_RESULT 0x801c
|
||||
#define UCORE_CSUMINFO 0x8020
|
||||
#define UCORE_CRCINFO 0x8024
|
||||
#define UCORE_CRCPOS 0x8028
|
||||
#define UCORE_FR_FIFOEMPTY 0x802c
|
||||
#define UCORE_PKT_DISTR 0x8030
|
||||
|
||||
#define PACKET_MEMORY (0xFFE00)
|
||||
#define PACKET_DATA_OFFSET (64)
|
||||
#define SHARED_SCRATCH_MEM 0x18000
|
||||
|
||||
/* Distribution mode */
|
||||
#define VAL_PDM(x) (((x) & 0x7) << 0)
|
||||
|
||||
/* Dest distribution or distribution list */
|
||||
#define VAL_DEST(x) (((x) & 0x3ff) << 8)
|
||||
#define VAL_PDL(x) (((x) & 0xf) << 4)
|
||||
|
||||
/*output buffer done*/
|
||||
#define VAL_FSV(x) (x<<19)
|
||||
#define VAL_FFS(x) (x<<14)
|
||||
|
||||
#define FWD_DEST_ONLY 1
|
||||
#define FWD_ENQ_DIST_VEC 2
|
||||
#define FWD_ENQ_DEST 3
|
||||
#define FWD_DIST_VEC 4
|
||||
#define FWD_ENQ_DIST_VEC_SER 6
|
||||
#define FWD_ENQ_DEST_SER 7
|
||||
|
||||
#define USE_HASH_DST (1 << 20)
|
||||
|
||||
|
||||
#define NLM_DEFINE_UCORE(name, reg) \
|
||||
static __inline__ unsigned int nlm_read_ucore_##name(void) \
|
||||
{ \
|
||||
unsigned int __rv; \
|
||||
__asm__ __volatile__ ( \
|
||||
".set push\n" \
|
||||
".set noreorder\n" \
|
||||
".set mips32\n" \
|
||||
"li $8, %1\n" \
|
||||
"lw %0, ($8)\n" \
|
||||
".set pop\n" \
|
||||
: "=r" (__rv) \
|
||||
: "i" (reg) \
|
||||
: "$8" \
|
||||
); \
|
||||
return __rv; \
|
||||
} \
|
||||
\
|
||||
static __inline__ void nlm_write_ucore_##name(unsigned int val) \
|
||||
{ \
|
||||
__asm__ __volatile__( \
|
||||
".set push\n" \
|
||||
".set noreorder\n" \
|
||||
".set mips32\n" \
|
||||
"li $8, %1\n" \
|
||||
"sw %0, ($8)\n" \
|
||||
".set pop\n" \
|
||||
:: "r" (val), "i" (reg) \
|
||||
: "$8" \
|
||||
); \
|
||||
} struct __hack
|
||||
|
||||
|
||||
NLM_DEFINE_UCORE(obufdone, UCORE_OUTBUF_DONE);
|
||||
NLM_DEFINE_UCORE(rxpktrdy, UCORE_RX_PKT_RDY);
|
||||
NLM_DEFINE_UCORE(rxpktinfo, UCORE_RX_PKT_INFO);
|
||||
NLM_DEFINE_UCORE(cam0, UCORE_CAM0);
|
||||
NLM_DEFINE_UCORE(cam1, UCORE_CAM1);
|
||||
NLM_DEFINE_UCORE(cam2, UCORE_CAM2);
|
||||
NLM_DEFINE_UCORE(cam3, UCORE_CAM3);
|
||||
NLM_DEFINE_UCORE(camresult, UCORE_CAM_RESULT);
|
||||
NLM_DEFINE_UCORE(csuminfo, UCORE_CSUMINFO);
|
||||
NLM_DEFINE_UCORE(crcinfo, UCORE_CRCINFO);
|
||||
NLM_DEFINE_UCORE(crcpos, UCORE_CRCPOS);
|
||||
NLM_DEFINE_UCORE(freefifo_empty, UCORE_FR_FIFOEMPTY);
|
||||
NLM_DEFINE_UCORE(pktdistr, UCORE_PKT_DISTR);
|
||||
|
||||
/*
|
||||
* l3cachelines - number of cache lines to allocate into l3
|
||||
* fsv - 0 : use interface-id for selecting the free fifo pool
|
||||
* 1 : use free fifo pool selected by FFS field
|
||||
* ffs - selects which free fifo pool to use to take a free fifo
|
||||
* prepad_en - If this field is set to 1, part or all of the
|
||||
* 64 byte prepad seen by micro engines, is written
|
||||
* infront of every packet.
|
||||
* prepad_ovride - If this field is 1, the ucore system uses
|
||||
* prepad configuration defined in this register,
|
||||
* 0 means that it uses the configuration defined
|
||||
* in NAE RX_CONFIG register
|
||||
* prepad_size - number of 16 byte words in the 64-byte prepad
|
||||
* seen by micro engines and dma'ed to memory as
|
||||
* pkt prepad. This field is meaningful only if
|
||||
* prepad_en and prepad_ovride is set.
|
||||
* 0 : 1 word
|
||||
* 1 : 2 words
|
||||
* 2 : 3 words
|
||||
* 3 : 4 words
|
||||
* prepad[0-3]: writing 0 to this means that the 1st 16 byte offset
|
||||
* of prepad in micro engine, gets setup as prepad0/1/2/3.
|
||||
* prepad word.
|
||||
* 1 : means 2nd 16 byte chunk in prepad0/1/2/3
|
||||
* 2 : means 3rd 16 byte chunk in prepad0/1/2/3
|
||||
* 3 : means 4rth 16 byte chunk in prepad0/1/2/3
|
||||
* pkt_discard - packet will be discarded if this is set to 1
|
||||
* rd5 - value (single bit) to be inserted in bit 5, the unclassified
|
||||
* pkt bit of receive descriptor. If this bit is set, HPRE bit
|
||||
* should also be set in ucore_rxpktready register
|
||||
*/
|
||||
static __inline__ void
|
||||
nlm_ucore_pkt_done(int l3cachelines, int fsv, int ffs, int prepad_en,
|
||||
int prepad_ovride, int prepad_size, int prepad0, int prepad1,
|
||||
int prepad2, int prepad3, int pkt_discard, int rd5)
|
||||
{
|
||||
unsigned int val = 0;
|
||||
|
||||
val |= ((l3cachelines & 0xfff) << 20);
|
||||
val |= ((fsv & 0x1) << 19);
|
||||
val |= ((ffs & 0x1f) << 14);
|
||||
val |= ((prepad_en & 0x1) << 3);
|
||||
val |= ((prepad_ovride & 0x1) << 2);
|
||||
val |= ((prepad_size & 0x3) << 12);
|
||||
val |= ((prepad0 & 0x3) << 4);
|
||||
val |= ((prepad1 & 0x3) << 6);
|
||||
val |= ((prepad2 & 0x3) << 8);
|
||||
val |= ((prepad3 & 0x3) << 10);
|
||||
val |= ((pkt_discard & 0x1) << 1);
|
||||
val |= ((rd5 & 0x1) << 0);
|
||||
|
||||
nlm_write_ucore_obufdone(val);
|
||||
}
|
||||
|
||||
/* Get the class full vector field from POE.
|
||||
* The POE maintains a threshold for each class.
|
||||
* A bit in this field will be set corresponding to the class approaching
|
||||
* class full status.
|
||||
*/
|
||||
static __inline__ int
|
||||
nlm_ucore_get_rxpkt_poeclassfullvec(unsigned int pktrdy)
|
||||
{
|
||||
return ((pktrdy >> 24) & 0xff);
|
||||
}
|
||||
|
||||
/* This function returns 1 if the hardware parser extraction process
|
||||
* resulted in an error. Else, returns 0.
|
||||
*/
|
||||
static __inline__ int
|
||||
nlm_ucore_get_rxpkt_hwparsererr(unsigned int pktrdy)
|
||||
{
|
||||
return ((pktrdy >> 23) & 0x1);
|
||||
}
|
||||
|
||||
/* This function returns the context number assigned to incoming
|
||||
* packet
|
||||
*/
|
||||
static __inline__ int
|
||||
nlm_ucore_get_rxpkt_context(unsigned int pktrdy)
|
||||
{
|
||||
return ((pktrdy >> 13) & 0x3ff);
|
||||
}
|
||||
|
||||
/* this function returns the channel number of incoming packet,
|
||||
* and applies only to interlaken.
|
||||
*/
|
||||
static __inline__ int
|
||||
nlm_ucore_get_rxpkt_channel(unsigned int pktrdy)
|
||||
{
|
||||
return ((pktrdy >> 5) & 0xff);
|
||||
}
|
||||
|
||||
/* This function returns the interface number on which the pkt
|
||||
* was received
|
||||
*/
|
||||
static __inline__ int
|
||||
nlm_ucore_get_rxpkt_interface(unsigned int pktrdy)
|
||||
{
|
||||
return (pktrdy & 0x1f);
|
||||
}
|
||||
|
||||
/* This function returns 1 if end of packet (EOP) is set in
|
||||
* packet data.
|
||||
*/
|
||||
static __inline__ int
|
||||
nlm_ucore_get_rxpkt_eop(unsigned int rxpkt_info)
|
||||
{
|
||||
return ((rxpkt_info >> 9) & 0x1);
|
||||
}
|
||||
|
||||
/* This function returns packet length of received pkt */
|
||||
static __inline__ int
|
||||
nlm_ucore_get_rxpktlen(unsigned int rxpkt_info)
|
||||
{
|
||||
return (rxpkt_info & 0x1ff);
|
||||
}
|
||||
|
||||
/* this function sets up the ucore TCAM keys. */
|
||||
static __inline__ void
|
||||
nlm_ucore_setup_camkey(unsigned int cam_key0, unsigned int cam_key1,
|
||||
unsigned int cam_key2, unsigned int cam_key3)
|
||||
{
|
||||
nlm_write_ucore_cam0(cam_key0);
|
||||
nlm_write_ucore_cam1(cam_key1);
|
||||
nlm_write_ucore_cam2(cam_key2);
|
||||
nlm_write_ucore_cam3(cam_key3);
|
||||
}
|
||||
|
||||
/* This function checks if the cam result is valid or not.
|
||||
* If valid, it returns the result, else it returns 0.
|
||||
*/
|
||||
static __inline__ int
|
||||
nlm_ucore_get_cam_result(unsigned int cam_result)
|
||||
{
|
||||
if (((cam_result >> 15) & 0x1) == 1) /* valid result */
|
||||
return (cam_result & 0x3fff);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/* This function sets up the csum in ucore.
|
||||
* iphdr_start - defines the start of ip header (to check - is this byte
|
||||
* position???)
|
||||
* iphdr_len - This field is auto filled by h/w parser if zero, else
|
||||
* the value defined will be used.
|
||||
*/
|
||||
static __inline__ void
|
||||
nlm_ucore_csum_setup(int iphdr_start, int iphdr_len)
|
||||
{
|
||||
unsigned int val = 0;
|
||||
|
||||
val |= ((iphdr_len & 0xff) << 8);
|
||||
val |= (iphdr_len & 0xff);
|
||||
nlm_write_ucore_csuminfo(val);
|
||||
}
|
||||
|
||||
/* crcpos - position of crc in pkt. If crc position is within startcrc and
|
||||
* endcrc, zero out these bytes in the packet before computing crc. This
|
||||
* field is not needed for FCoE.
|
||||
* cps - If 1, uses the polynomial in RX_CRC_POLY1 of NAE register.
|
||||
* if 0, uses the polynomial in RX_CRC_POLY0 of NAE register.
|
||||
* fcoe - If this is 1, crc calculation starts from 'startCRC' and the CRC
|
||||
* engine ends calculation before the last byte.
|
||||
* cbm - if 1, enables crc byte mirroring, where bits within a byte will get
|
||||
* reversed (mirrored) during calculation of crc.
|
||||
* cfi - If 1, performs a final inversion of crc before comarison is done during
|
||||
* pkt reception.
|
||||
* startcrc - This field is always required for both FCoE and SCTP crc.
|
||||
* endcrc - This information needs to be setup only for SCTP. For FCoE this
|
||||
* information is provided by hardware.
|
||||
* valid - if set to 1, CRC status is placed into bit 2 of rx descriptor
|
||||
* if set to 0, TCP checksum status is placed into bit 2 of rx descriptor
|
||||
* keysize - defines the number of bytes in the pre-pad that contains the key
|
||||
*/
|
||||
static __inline__ void
|
||||
nlm_ucore_crc_setup(int crcpos, int cps, int cfi, int cbm, int fcoe,
|
||||
int keysize, int valid, int startcrc, int endcrc)
|
||||
{
|
||||
unsigned int val = 0;
|
||||
|
||||
val |= ((cfi & 0x1) << 20);
|
||||
val |= ((cbm & 0x1) << 19);
|
||||
val |= ((fcoe & 0x1) << 18);
|
||||
val |= ((cps & 0x1) << 16);
|
||||
val |= (crcpos & 0xffff);
|
||||
|
||||
nlm_write_ucore_crcpos(val);
|
||||
|
||||
val = 0;
|
||||
val |= ((keysize & 0x3f) << 25);
|
||||
val |= ((valid & 0x1) << 24);
|
||||
val |= ((endcrc & 0xffff) << 8);
|
||||
val |= (startcrc & 0xff);
|
||||
|
||||
nlm_write_ucore_crcinfo(val);
|
||||
}
|
||||
|
||||
/* This function returns a fifo empty vector, where each bit provides
|
||||
* the status of a fifo pool, where if the pool is empty the bit gets
|
||||
* set to 1.
|
||||
*/
|
||||
static __inline__ int
|
||||
nlm_ucore_get_fifoempty(unsigned int fifoempty)
|
||||
{
|
||||
return (fifoempty & 0xfffff);
|
||||
}
|
||||
|
||||
/* This function controls how POE will distribute the packet.
|
||||
* pdm - is the packet distribution mode, where
|
||||
* 0x0 - means packet distribution mode is not used
|
||||
* 0x1 - means forwarding based on destination only (no enqueue)
|
||||
* 0x2 - means forwarding based on FID and distr vector (enqueue)
|
||||
* 0x3 - means forwarding based on dest and FID (enqueue)
|
||||
* 0x4 - means forwarding based on distr vec (no enqueue)
|
||||
* 0x6 - means forward based on FID (enqueue), distr vec and serial mode
|
||||
* 0x7 - means forward based on FID (enqueue), dest and serial mode
|
||||
* mc3 - If 1, then the 3 most significant bits of distribution list are taken
|
||||
* from context->class_table
|
||||
* pdl - poe distribution list
|
||||
* dest - fixed destination setup
|
||||
* hash - if 1, use hash based destination
|
||||
*/
|
||||
static __inline__ void
|
||||
nlm_ucore_setup_poepktdistr(int pdm, int mc3, int pdl, int dest, int hash)
|
||||
{
|
||||
unsigned int val = 0;
|
||||
|
||||
val |= ((hash & 0x1) << 20);
|
||||
val |= ((dest & 0xfff) << 8);
|
||||
val |= ((pdl & 0xf) << 4);
|
||||
val |= ((mc3 & 0x1) << 3);
|
||||
val |= (pdm & 0x7);
|
||||
|
||||
nlm_write_ucore_pktdistr(val);
|
||||
}
|
||||
|
||||
#endif
|
||||
58
sys/mips/nlm/dev/net/ucore/ucore_app.c
Normal file
58
sys/mips/nlm/dev/net/ucore/ucore_app.c
Normal file
|
|
@ -0,0 +1,58 @@
|
|||
/*-
|
||||
* Copyright (c) 2003-2012 Broadcom Corporation
|
||||
* All Rights Reserved
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY BROADCOM ``AS IS'' AND ANY EXPRESS OR
|
||||
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
* ARE DISCLAIMED. IN NO EVENT SHALL BROADCOM OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
|
||||
* BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
|
||||
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
|
||||
* OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
|
||||
* IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
* $FreeBSD$
|
||||
*/
|
||||
|
||||
#include "ucore.h"
|
||||
|
||||
int main(void)
|
||||
{
|
||||
#if 0
|
||||
volatile unsigned int *pkt =
|
||||
(volatile unsigned int *) (PACKET_MEMORY + PACKET_DATA_OFFSET);
|
||||
int intf, hw_parser_error, context;
|
||||
#endif
|
||||
unsigned int pktrdy;
|
||||
int num_cachelines = 1518 >> 6; /* pktsize / L3 cacheline size */
|
||||
|
||||
|
||||
/* Spray packets to using distribution vector */
|
||||
while (1) {
|
||||
pktrdy = nlm_read_ucore_rxpktrdy();
|
||||
#if 0
|
||||
intf = pktrdy & 0x1f;
|
||||
context = (pktrdy >> 13) & 0x3ff;
|
||||
hw_parser_error = (pktrdy >> 23) & 0x1;
|
||||
#endif
|
||||
nlm_ucore_setup_poepktdistr(FWD_DIST_VEC, 0, 0, 0, 0);
|
||||
nlm_ucore_pkt_done(num_cachelines, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0);
|
||||
}
|
||||
|
||||
return (0);
|
||||
}
|
||||
251
sys/mips/nlm/dev/net/xaui.c
Normal file
251
sys/mips/nlm/dev/net/xaui.c
Normal file
|
|
@ -0,0 +1,251 @@
|
|||
/*-
|
||||
* Copyright (c) 2003-2012 Broadcom Corporation
|
||||
* All Rights Reserved
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY BROADCOM ``AS IS'' AND ANY EXPRESS OR
|
||||
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
* ARE DISCLAIMED. IN NO EVENT SHALL BROADCOM OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
|
||||
* BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
|
||||
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
|
||||
* OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
|
||||
* IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#include <sys/cdefs.h>
|
||||
__FBSDID("$FreeBSD$");
|
||||
#include <sys/types.h>
|
||||
#include <sys/systm.h>
|
||||
|
||||
#include <mips/nlm/hal/mips-extns.h>
|
||||
#include <mips/nlm/hal/haldefs.h>
|
||||
#include <mips/nlm/hal/iomap.h>
|
||||
#include <mips/nlm/hal/sys.h>
|
||||
#include <mips/nlm/hal/nae.h>
|
||||
#include <mips/nlm/hal/mdio.h>
|
||||
#include <mips/nlm/hal/sgmii.h>
|
||||
#include <mips/nlm/hal/xaui.h>
|
||||
|
||||
#include <mips/nlm/xlp.h>
|
||||
void
|
||||
nlm_xaui_pcs_init(uint64_t nae_base, int xaui_cplx_mask)
|
||||
{
|
||||
int block, lane_ctrl, reg;
|
||||
int cplx_lane_enable;
|
||||
int lane_enable = 0;
|
||||
uint32_t regval;
|
||||
|
||||
cplx_lane_enable = LM_XAUI |
|
||||
(LM_XAUI << 4) |
|
||||
(LM_XAUI << 8) |
|
||||
(LM_XAUI << 12);
|
||||
|
||||
if (xaui_cplx_mask == 0)
|
||||
return;
|
||||
|
||||
/* write 0x2 to enable SGMII for all lane */
|
||||
block = 7;
|
||||
|
||||
if (xaui_cplx_mask & 0x3) { /* Complexes 0, 1 */
|
||||
lane_enable = nlm_read_nae_reg(nae_base,
|
||||
NAE_REG(block, LANE_CFG, LANE_CFG_CPLX_0_1));
|
||||
if (xaui_cplx_mask & 0x1) { /* Complex 0 */
|
||||
lane_enable &= ~(0xFFFF);
|
||||
lane_enable |= cplx_lane_enable;
|
||||
}
|
||||
if (xaui_cplx_mask & 0x2) { /* Complex 1 */
|
||||
lane_enable &= ~(0xFFFF<<16);
|
||||
lane_enable |= (cplx_lane_enable << 16);
|
||||
}
|
||||
nlm_write_nae_reg(nae_base,
|
||||
NAE_REG(block, LANE_CFG, LANE_CFG_CPLX_0_1),
|
||||
lane_enable);
|
||||
}
|
||||
lane_enable = 0;
|
||||
if (xaui_cplx_mask & 0xc) { /* Complexes 2, 3 */
|
||||
lane_enable = nlm_read_nae_reg(nae_base,
|
||||
NAE_REG(block, LANE_CFG, LANE_CFG_CPLX_2_3));
|
||||
if (xaui_cplx_mask & 0x4) { /* Complex 2 */
|
||||
lane_enable &= ~(0xFFFF);
|
||||
lane_enable |= cplx_lane_enable;
|
||||
}
|
||||
if (xaui_cplx_mask & 0x8) { /* Complex 3 */
|
||||
lane_enable &= ~(0xFFFF<<16);
|
||||
lane_enable |= (cplx_lane_enable << 16);
|
||||
}
|
||||
nlm_write_nae_reg(nae_base,
|
||||
NAE_REG(block, LANE_CFG, LANE_CFG_CPLX_2_3),
|
||||
lane_enable);
|
||||
}
|
||||
|
||||
/* Bring txpll out of reset */
|
||||
for (block = 0; block < 4; block++) {
|
||||
if ((xaui_cplx_mask & (1 << block)) == 0)
|
||||
continue;
|
||||
|
||||
for (lane_ctrl = PHY_LANE_0_CTRL;
|
||||
lane_ctrl <= PHY_LANE_3_CTRL; lane_ctrl++) {
|
||||
if (!nlm_is_xlp8xx_ax())
|
||||
xlp_nae_lane_reset_txpll(nae_base,
|
||||
block, lane_ctrl, PHYMODE_XAUI);
|
||||
else
|
||||
xlp_ax_nae_lane_reset_txpll(nae_base, block,
|
||||
lane_ctrl, PHYMODE_XAUI);
|
||||
}
|
||||
}
|
||||
|
||||
/* Wait for Rx & TX clock stable */
|
||||
for (block = 0; block < 4; block++) {
|
||||
if ((xaui_cplx_mask & (1 << block)) == 0)
|
||||
continue;
|
||||
|
||||
for (lane_ctrl = PHY_LANE_0_CTRL;
|
||||
lane_ctrl <= PHY_LANE_3_CTRL; lane_ctrl++) {
|
||||
|
||||
reg = NAE_REG(block, PHY, lane_ctrl - 4);
|
||||
/* Wait for TX clock to be set */
|
||||
do {
|
||||
regval = nlm_read_nae_reg(nae_base, reg);
|
||||
} while ((regval & LANE_TX_CLK) == 0);
|
||||
|
||||
/* Wait for RX clock to be set */
|
||||
do {
|
||||
regval = nlm_read_nae_reg(nae_base, reg);
|
||||
} while ((regval & LANE_RX_CLK) == 0);
|
||||
|
||||
/* Wait for XAUI Lane fault to be cleared */
|
||||
do {
|
||||
regval = nlm_read_nae_reg(nae_base, reg);
|
||||
} while ((regval & XAUI_LANE_FAULT) != 0);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
void
|
||||
nlm_nae_setup_rx_mode_xaui(uint64_t base, int nblock, int iface, int port_type,
|
||||
int broadcast_en, int multicast_en, int pause_en, int promisc_en)
|
||||
{
|
||||
uint32_t val;
|
||||
|
||||
val = ((broadcast_en & 0x1) << 10) |
|
||||
((pause_en & 0x1) << 9) |
|
||||
((multicast_en & 0x1) << 8) |
|
||||
((promisc_en & 0x1) << 7) | /* unicast_enable - enables promisc mode */
|
||||
1; /* MAC address is always valid */
|
||||
|
||||
nlm_write_nae_reg(base, XAUI_MAC_FILTER_CFG(nblock), val);
|
||||
}
|
||||
|
||||
void
|
||||
nlm_nae_setup_mac_addr_xaui(uint64_t base, int nblock, int iface,
|
||||
int port_type, unsigned char *mac_addr)
|
||||
{
|
||||
nlm_write_nae_reg(base,
|
||||
XAUI_MAC_ADDR0_LO(nblock),
|
||||
(mac_addr[5] << 24) |
|
||||
(mac_addr[4] << 16) |
|
||||
(mac_addr[3] << 8) |
|
||||
mac_addr[2]);
|
||||
|
||||
nlm_write_nae_reg(base,
|
||||
XAUI_MAC_ADDR0_HI(nblock),
|
||||
(mac_addr[1] << 24) |
|
||||
(mac_addr[0] << 16));
|
||||
|
||||
nlm_write_nae_reg(base,
|
||||
XAUI_MAC_ADDR_MASK0_LO(nblock),
|
||||
0xffffffff);
|
||||
nlm_write_nae_reg(base,
|
||||
XAUI_MAC_ADDR_MASK0_HI(nblock),
|
||||
0xffffffff);
|
||||
|
||||
nlm_nae_setup_rx_mode_xaui(base, nblock, iface,
|
||||
XAUIC,
|
||||
1, /* broadcast enabled */
|
||||
1, /* multicast enabled */
|
||||
0, /* do not accept pause frames */
|
||||
0 /* promisc mode disabled */
|
||||
);
|
||||
}
|
||||
|
||||
void
|
||||
nlm_config_xaui_mtu(uint64_t nae_base, int nblock,
|
||||
int max_tx_frame_sz, int max_rx_frame_sz)
|
||||
{
|
||||
uint32_t tx_words = max_tx_frame_sz >> 2; /* max_tx_frame_sz / 4 */
|
||||
|
||||
/* write max frame length */
|
||||
nlm_write_nae_reg(nae_base,
|
||||
XAUI_MAX_FRAME_LEN(nblock),
|
||||
((tx_words & 0x3ff) << 16) | (max_rx_frame_sz & 0xffff));
|
||||
}
|
||||
|
||||
void
|
||||
nlm_config_xaui(uint64_t nae_base, int nblock,
|
||||
int max_tx_frame_sz, int max_rx_frame_sz, int vlan_pri_en)
|
||||
{
|
||||
uint32_t val;
|
||||
|
||||
val = nlm_read_nae_reg(nae_base, XAUI_NETIOR_XGMAC_CTRL1(nblock));
|
||||
val &= ~(0x1 << 11); /* clear soft reset */
|
||||
nlm_write_nae_reg(nae_base, XAUI_NETIOR_XGMAC_CTRL1(nblock), val);
|
||||
|
||||
val = nlm_read_nae_reg(nae_base, XAUI_NETIOR_XGMAC_CTRL1(nblock));
|
||||
val &= ~(0x3 << 11); /* clear soft reset and hard reset */
|
||||
nlm_write_nae_reg(nae_base, XAUI_NETIOR_XGMAC_CTRL1(nblock), val);
|
||||
nlm_write_nae_reg(nae_base, XAUI_CONFIG0(nblock), 0xffffffff);
|
||||
nlm_write_nae_reg(nae_base, XAUI_CONFIG0(nblock), 0);
|
||||
|
||||
/* Enable tx/rx frame */
|
||||
val = 0xF00010A8;
|
||||
val |= XAUI_CONFIG_LENCHK;
|
||||
val |= XAUI_CONFIG_GENFCS;
|
||||
val |= XAUI_CONFIG_PAD_64;
|
||||
val |= XAUI_CONFIG_TFEN;
|
||||
val |= XAUI_CONFIG_RFEN;
|
||||
nlm_write_nae_reg(nae_base, XAUI_CONFIG1(nblock), val);
|
||||
|
||||
/* write max frame length */
|
||||
nlm_config_xaui_mtu(nae_base, nblock, max_tx_frame_sz,
|
||||
max_rx_frame_sz);
|
||||
|
||||
/* set stats counter */
|
||||
val = nlm_read_nae_reg(nae_base, XAUI_NETIOR_XGMAC_CTRL1(nblock));
|
||||
val |= (0x1 << NETIOR_XGMAC_VLAN_DC_POS);
|
||||
val |= (0x1 << NETIOR_XGMAC_STATS_EN_POS);
|
||||
if (vlan_pri_en) {
|
||||
val |= (0x1 << NETIOR_XGMAC_TX_PFC_EN_POS);
|
||||
val |= (0x1 << NETIOR_XGMAC_RX_PFC_EN_POS);
|
||||
val |= (0x1 << NETIOR_XGMAC_TX_PAUSE_POS);
|
||||
} else {
|
||||
val &= ~(0x1 << NETIOR_XGMAC_TX_PFC_EN_POS);
|
||||
val |= (0x1 << NETIOR_XGMAC_TX_PAUSE_POS);
|
||||
}
|
||||
nlm_write_nae_reg(nae_base, XAUI_NETIOR_XGMAC_CTRL1(nblock), val);
|
||||
/* configure on / off timer */
|
||||
if (vlan_pri_en)
|
||||
val = 0xF1230000; /* PFC mode, offtimer = 0xf123, ontimer = 0 */
|
||||
else
|
||||
val = 0x0000F123; /* link level FC mode, offtimer = 0xf123 */
|
||||
nlm_write_nae_reg(nae_base, XAUI_NETIOR_XGMAC_CTRL2(nblock), val);
|
||||
|
||||
/* set xaui tx threshold */
|
||||
val = nlm_read_nae_reg(nae_base, XAUI_NETIOR_XGMAC_CTRL3(nblock));
|
||||
val &= ~(0x1f << 10);
|
||||
val |= ~(15 << 10);
|
||||
nlm_write_nae_reg(nae_base, XAUI_NETIOR_XGMAC_CTRL3(nblock), val);
|
||||
}
|
||||
1574
sys/mips/nlm/dev/net/xlpge.c
Normal file
1574
sys/mips/nlm/dev/net/xlpge.c
Normal file
File diff suppressed because it is too large
Load diff
135
sys/mips/nlm/dev/net/xlpge.h
Normal file
135
sys/mips/nlm/dev/net/xlpge.h
Normal file
|
|
@ -0,0 +1,135 @@
|
|||
/*-
|
||||
* Copyright (c) 2003-2012 Broadcom Corporation
|
||||
* All Rights Reserved
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY BROADCOM ``AS IS'' AND ANY EXPRESS OR
|
||||
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
* ARE DISCLAIMED. IN NO EVENT SHALL BROADCOM OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
|
||||
* BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
|
||||
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
|
||||
* OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
|
||||
* IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
* $FreeBSD$
|
||||
*/
|
||||
|
||||
#ifndef __XLPGE_H__
|
||||
#define __XLPGE_H__
|
||||
|
||||
#define NLM_XLPGE_TXQ_SIZE 1024
|
||||
#define MAC_CRC_LEN 4
|
||||
|
||||
enum xlpge_link_state {
|
||||
NLM_LINK_DOWN,
|
||||
NLM_LINK_UP
|
||||
};
|
||||
|
||||
enum xlpge_floctrl_status {
|
||||
NLM_FLOWCTRL_DISABLED,
|
||||
NLM_FLOWCTRL_ENABLED
|
||||
};
|
||||
|
||||
struct nlm_xlp_portdata {
|
||||
struct ifnet *xlpge_if;
|
||||
struct nlm_xlpge_softc *xlpge_sc;
|
||||
};
|
||||
|
||||
struct nlm_xlpnae_softc {
|
||||
device_t xlpnae_dev;
|
||||
int node; /* XLP Node id */
|
||||
uint64_t base; /* NAE IO base */
|
||||
uint64_t poe_base; /* POE IO base */
|
||||
uint64_t poedv_base; /* POE distribution vec IO base */
|
||||
|
||||
int freq; /* frequency of nae block */
|
||||
int flow_crc_poly; /* Flow CRC16 polynomial */
|
||||
int total_free_desc; /* total for node */
|
||||
int max_ports;
|
||||
int total_num_ports;
|
||||
int per_port_num_flows;
|
||||
|
||||
u_int nucores;
|
||||
u_int nblocks;
|
||||
u_int num_complex;
|
||||
u_int ncontexts;
|
||||
|
||||
/* Ingress side parameters */
|
||||
u_int num_desc; /* no of descriptors in each packet */
|
||||
u_int parser_threshold;/* threshold of entries above which */
|
||||
/* the parser sequencer is scheduled */
|
||||
/* NetIOR configs */
|
||||
u_int cmplx_type[8]; /* XXXJC: redundant? */
|
||||
struct nae_port_config *portcfg;
|
||||
u_int xauimask;
|
||||
u_int sgmiimask;
|
||||
u_int hw_parser_en;
|
||||
u_int prepad_en;
|
||||
u_int prepad_size;
|
||||
u_int driver_mode;
|
||||
u_int ieee_1588_en;
|
||||
};
|
||||
|
||||
struct nlm_xlpge_softc {
|
||||
struct ifnet *xlpge_if; /* should be first member */
|
||||
/* see - mii.c:miibus_attach() */
|
||||
device_t xlpge_dev;
|
||||
device_t mii_bus;
|
||||
struct nlm_xlpnae_softc *network_sc;
|
||||
uint64_t base_addr; /* NAE IO base */
|
||||
int node; /* node id (quickread) */
|
||||
int block; /* network block id (quickread) */
|
||||
int port; /* port id - among the 18 in XLP */
|
||||
int type; /* port type - see xlp_gmac_port_types */
|
||||
int valid; /* boolean: valid port or not */
|
||||
struct mii_data xlpge_mii;
|
||||
int nfree_desc; /* No of free descriptors sent to port */
|
||||
int phy_addr; /* PHY id for the interface */
|
||||
|
||||
int speed; /* Port speed */
|
||||
int duplexity; /* Port duplexity */
|
||||
int link; /* Port link status */
|
||||
int flowctrl; /* Port flow control setting */
|
||||
|
||||
unsigned char dev_addr[ETHER_ADDR_LEN];
|
||||
struct mtx sc_lock;
|
||||
int if_flags;
|
||||
struct nae_port_config *portcfg;
|
||||
struct callout xlpge_callout;
|
||||
int mdio_bus;
|
||||
int txq;
|
||||
int rxfreeq;
|
||||
int hw_parser_en;
|
||||
int prepad_en;
|
||||
int prepad_size;
|
||||
};
|
||||
|
||||
#define XLP_NTXFRAGS 16
|
||||
#define NULL_VFBID 127
|
||||
|
||||
struct xlpge_tx_desc {
|
||||
uint64_t frag[XLP_NTXFRAGS];
|
||||
};
|
||||
|
||||
#define XLPGE_LOCK_INIT(_sc, _name) \
|
||||
mtx_init(&(_sc)->sc_lock, _name, MTX_NETWORK_LOCK, MTX_DEF)
|
||||
#define XLPGE_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->sc_lock)
|
||||
#define XLPGE_LOCK(_sc) mtx_lock(&(_sc)->sc_lock)
|
||||
#define XLPGE_UNLOCK(_sc) mtx_unlock(&(_sc)->sc_lock)
|
||||
#define XLPGE_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->sc_lock, MA_OWNED)
|
||||
|
||||
#endif
|
||||
|
|
@ -17,6 +17,23 @@ mips/nlm/uart_pci_xlp.c optional uart
|
|||
mips/nlm/uart_cpu_xlp.c optional uart
|
||||
mips/nlm/usb_init.c optional usb
|
||||
#
|
||||
# Network driver and micro-core code
|
||||
#
|
||||
mips/nlm/dev/net/nae.c optional xlpge
|
||||
mips/nlm/dev/net/mdio.c optional xlpge
|
||||
mips/nlm/dev/net/sgmii.c optional xlpge
|
||||
mips/nlm/dev/net/xaui.c optional xlpge
|
||||
mips/nlm/dev/net/xlpge.c optional xlpge
|
||||
ucore_app.bin optional xlpge \
|
||||
compile-with "${CC} -march=mips32 -mabi=32 -msoft-float -I. -I$S -O3 -funroll-loops -finline-limit=20000 -fno-tree-loop-optimize -fomit-frame-pointer -mno-branch-likely -fno-pic -mno-abicalls -ffunction-sections -fdata-sections -G0 -Wall -Werror -c $S/$M/nlm/dev/net/ucore/crt0_basic.S $S/$M/nlm/dev/net/ucore/ucore_app.c && ${LD} -melf32btsmip_fbsd -d -warn-common -T$S/$M/nlm/dev/net/ucore/ld.ucore.S crt0_basic.o ucore_app.o -o ucore_app && ${OBJCOPY} -S -O binary -R .note -R .comment ucore_app ${.TARGET}" \
|
||||
no-obj no-implicit-rule before-depend \
|
||||
clean "crt0_basic.o ucore_app.o ucore_app ucore_app.bin"
|
||||
ucore_app_bin.h optional xlpge \
|
||||
dependency "ucore_app.bin" \
|
||||
compile-with "file2c -sx 'static char ucore_app_bin[] = {' '};' < ucore_app.bin > ${.TARGET}" \
|
||||
no-obj no-implicit-rule before-depend \
|
||||
clean "ucore_app_bin.h"
|
||||
#
|
||||
# Security Driver
|
||||
#
|
||||
mips/nlm/dev/sec/nlmsec.c optional nlmsec
|
||||
|
|
|
|||
70
sys/mips/nlm/hal/interlaken.h
Normal file
70
sys/mips/nlm/hal/interlaken.h
Normal file
|
|
@ -0,0 +1,70 @@
|
|||
/*-
|
||||
* Copyright (c) 2003-2012 Broadcom Corporation
|
||||
* All Rights Reserved
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY BROADCOM ``AS IS'' AND ANY EXPRESS OR
|
||||
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
* ARE DISCLAIMED. IN NO EVENT SHALL BROADCOM OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
|
||||
* BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
|
||||
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
|
||||
* OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
|
||||
* IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
* $FreeBSD$
|
||||
*/
|
||||
#ifndef __NLM_ILAKEN_H__
|
||||
#define __NLM_ILAKEN_H__
|
||||
|
||||
/**
|
||||
* @file_name interlaken.h
|
||||
* @author Netlogic Microsystems
|
||||
* @brief Basic definitions of XLP ILAKEN ports
|
||||
*/
|
||||
|
||||
#define ILK_TX_CONTROL(block) NAE_REG(block, 5, 0x00)
|
||||
#define ILK_TX_RATE_LIMIT(block) NAE_REG(block, 5, 0x01)
|
||||
#define ILK_TX_META_CTRL(block) NAE_REG(block, 5, 0x02)
|
||||
#define ILK_RX_CTRL(block) NAE_REG(block, 5, 0x03)
|
||||
#define ILK_RX_STATUS1(block) NAE_REG(block, 5, 0x04)
|
||||
#define ILK_RX_STATUS2(block) NAE_REG(block, 5, 0x05)
|
||||
#define ILK_GENERAL_CTRL1(block) NAE_REG(block, 5, 0x06)
|
||||
#define ILK_STATUS3(block) NAE_REG(block, 5, 0x07)
|
||||
#define ILK_RX_FC_TMAP0(block) NAE_REG(block, 5, 0x08)
|
||||
#define ILK_RX_FC_TMAP1(block) NAE_REG(block, 5, 0x09)
|
||||
#define ILK_RX_FC_TMAP2(block) NAE_REG(block, 5, 0x0a)
|
||||
#define ILK_RX_FC_TMAP3(block) NAE_REG(block, 5, 0x0b)
|
||||
#define ILK_RX_FC_TMAP4(block) NAE_REG(block, 5, 0x0c)
|
||||
#define ILK_RX_FC_TADDR(block) NAE_REG(block, 5, 0x0d)
|
||||
#define ILK_GENERAL_CTRL2(block) NAE_REG(block, 5, 0x0e)
|
||||
#define ILK_GENERAL_CTRL3(block) NAE_REG(block, 5, 0x0f)
|
||||
#define ILK_SMALL_COUNT0(block) NAE_REG(block, 5, 0x10)
|
||||
#define ILK_SMALL_COUNT1(block) NAE_REG(block, 5, 0x11)
|
||||
#define ILK_SMALL_COUNT2(block) NAE_REG(block, 5, 0x12)
|
||||
#define ILK_SMALL_COUNT3(block) NAE_REG(block, 5, 0x13)
|
||||
#define ILK_SMALL_COUNT4(block) NAE_REG(block, 5, 0x14)
|
||||
#define ILK_SMALL_COUNT5(block) NAE_REG(block, 5, 0x15)
|
||||
#define ILK_SMALL_COUNT6(block) NAE_REG(block, 5, 0x16)
|
||||
#define ILK_SMALL_COUNT7(block) NAE_REG(block, 5, 0x17)
|
||||
#define ILK_MID_COUNT0(block) NAE_REG(block, 5, 0x18)
|
||||
#define ILK_MID_COUNT1(block) NAE_REG(block, 5, 0x19)
|
||||
#define ILK_LARGE_COUNT0(block) NAE_REG(block, 5, 0x1a)
|
||||
#define ILK_LARGE_COUNT1(block) NAE_REG(block, 5, 0x1b)
|
||||
#define ILK_LARGE_COUNT_H0(block) NAE_REG(block, 5, 0x1c)
|
||||
#define ILK_LARGE_COUNT_H1(block) NAE_REG(block, 5, 0x1d)
|
||||
|
||||
#endif
|
||||
|
|
@ -186,7 +186,7 @@ nlm_irtnum(uint64_t pcibase)
|
|||
}
|
||||
|
||||
static __inline__ int
|
||||
nlm_uenginenum(uint64_t pcibase)
|
||||
nlm_num_uengines(uint64_t pcibase)
|
||||
{
|
||||
return nlm_read_reg(pcibase, XLP_PCI_UCODEINFO_REG);
|
||||
}
|
||||
|
|
|
|||
104
sys/mips/nlm/hal/mdio.h
Normal file
104
sys/mips/nlm/hal/mdio.h
Normal file
|
|
@ -0,0 +1,104 @@
|
|||
/*-
|
||||
* Copyright (c) 2003-2012 Broadcom Corporation
|
||||
* All Rights Reserved
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY BROADCOM ``AS IS'' AND ANY EXPRESS OR
|
||||
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
* ARE DISCLAIMED. IN NO EVENT SHALL BROADCOM OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
|
||||
* BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
|
||||
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
|
||||
* OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
|
||||
* IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
* $FreeBSD$
|
||||
*/
|
||||
|
||||
#ifndef __NLM_MDIO_H__
|
||||
#define __NLM_MDIO_H__
|
||||
|
||||
/**
|
||||
* @file_name mdio.h
|
||||
* @author Netlogic Microsystems
|
||||
* @brief Access functions for XLP MDIO
|
||||
*/
|
||||
#define INT_MDIO_CTRL 0x19
|
||||
#define INT_MDIO_CTRL_DATA 0x1A
|
||||
#define INT_MDIO_RD_STAT 0x1B
|
||||
#define INT_MDIO_LINK_STAT 0x1C
|
||||
#define EXT_G0_MDIO_CTRL 0x1D
|
||||
#define EXT_G1_MDIO_CTRL 0x21
|
||||
#define EXT_G0_MDIO_CTRL_DATA 0x1E
|
||||
#define EXT_G1_MDIO_CTRL_DATA 0x22
|
||||
#define EXT_G0_MDIO_LINK_STAT 0x20
|
||||
#define EXT_G1_MDIO_LINK_STAT 0x24
|
||||
#define EXT_G0_MDIO_RD_STAT 0x1F
|
||||
#define EXT_G1_MDIO_RD_STAT 0x23
|
||||
|
||||
#define INT_MDIO_CTRL_ST_POS 0
|
||||
#define INT_MDIO_CTRL_OP_POS 2
|
||||
#define INT_MDIO_CTRL_PHYADDR_POS 4
|
||||
#define INT_MDIO_CTRL_DEVTYPE_POS 9
|
||||
#define INT_MDIO_CTRL_TA_POS 14
|
||||
#define INT_MDIO_CTRL_MIIM_POS 16
|
||||
#define INT_MDIO_CTRL_LOAD_POS 19
|
||||
#define INT_MDIO_CTRL_XDIV_POS 21
|
||||
#define INT_MDIO_CTRL_MCDIV_POS 28
|
||||
#define INT_MDIO_CTRL_RST 0x40000000
|
||||
#define INT_MDIO_CTRL_SMP 0x00100000
|
||||
#define INT_MDIO_CTRL_CMD_LOAD 0x00080000
|
||||
|
||||
#define INT_MDIO_RD_STAT_MASK 0x0000FFFF
|
||||
#define INT_MDIO_STAT_LFV 0x00010000
|
||||
#define INT_MDIO_STAT_SC 0x00020000
|
||||
#define INT_MDIO_STAT_SM 0x00040000
|
||||
#define INT_MDIO_STAT_MIILFS 0x00080000
|
||||
#define INT_MDIO_STAT_MBSY 0x00100000
|
||||
|
||||
#define EXT_G_MDIO_CLOCK_DIV_4 0
|
||||
#define EXT_G_MDIO_CLOCK_DIV_2 1
|
||||
#define EXT_G_MDIO_CLOCK_DIV_1 2
|
||||
#define EXT_G_MDIO_REGADDR_POS 5
|
||||
#define EXT_G_MDIO_PHYADDR_POS 10
|
||||
#define EXT_G_MDIO_CMD_SP 0x00008000
|
||||
#define EXT_G_MDIO_CMD_PSIA 0x00010000
|
||||
#define EXT_G_MDIO_CMD_LCD 0x00020000
|
||||
#define EXT_G_MDIO_CMD_RDS 0x00040000
|
||||
#define EXT_G_MDIO_CMD_SC 0x00080000
|
||||
#define EXT_G_MDIO_MMRST 0x00100000
|
||||
#define EXT_G_MDIO_DIV 0x0000001E
|
||||
|
||||
#define EXT_G_MDIO_RD_STAT_MASK 0x0000FFFF
|
||||
#define EXT_G_MDIO_STAT_LFV 0x00010000
|
||||
#define EXT_G_MDIO_STAT_SC 0x00020000
|
||||
#define EXT_G_MDIO_STAT_SM 0x00040000
|
||||
#define EXT_G_MDIO_STAT_MIILFS 0x00080000
|
||||
#define EXT_G_MDIO_STAT_MBSY 0x80000000
|
||||
#define MDIO_OP_CMD_READ 0x10
|
||||
#define MDIO_OP_CMD_WRITE 0x01
|
||||
|
||||
#if !defined(LOCORE) && !defined(__ASSEMBLY__)
|
||||
|
||||
int nlm_int_gmac_mdio_read(uint64_t, int, int, int, int, int);
|
||||
int nlm_int_gmac_mdio_write(uint64_t, int, int, int, int, int, uint16_t);
|
||||
int nlm_int_gmac_mdio_reset(uint64_t, int, int, int);
|
||||
int nlm_gmac_mdio_read(uint64_t, int, int, int, int, int);
|
||||
int nlm_gmac_mdio_write(uint64_t, int, int, int, int, int, uint16_t);
|
||||
int nlm_gmac_mdio_reset(uint64_t, int, int, int);
|
||||
|
||||
#endif /* !(LOCORE) && !(__ASSEMBLY__) */
|
||||
#endif
|
||||
646
sys/mips/nlm/hal/nae.h
Normal file
646
sys/mips/nlm/hal/nae.h
Normal file
|
|
@ -0,0 +1,646 @@
|
|||
/*-
|
||||
* Copyright (c) 2003-2012 Broadcom Corporation
|
||||
* All Rights Reserved
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY BROADCOM ``AS IS'' AND ANY EXPRESS OR
|
||||
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
* ARE DISCLAIMED. IN NO EVENT SHALL BROADCOM OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
|
||||
* BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
|
||||
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
|
||||
* OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
|
||||
* IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
* $FreeBSD$
|
||||
*/
|
||||
|
||||
#ifndef __NLM_NAE_H__
|
||||
#define __NLM_NAE_H__
|
||||
|
||||
/**
|
||||
* @file_name nae.h
|
||||
* @author Netlogic Microsystems
|
||||
* @brief Basic definitions of XLP Networt Accelerator Engine
|
||||
*/
|
||||
|
||||
/* NAE specific registers */
|
||||
#define NAE_REG(blk, intf, reg) (((blk) << 11) | ((intf) << 7) | (reg))
|
||||
|
||||
/* ingress path registers */
|
||||
#define NAE_RX_CONFIG NAE_REG(7, 0, 0x10)
|
||||
#define NAE_RX_IF_BASE_CONFIG0 NAE_REG(7, 0, 0x12)
|
||||
#define NAE_RX_IF_BASE_CONFIG1 NAE_REG(7, 0, 0x13)
|
||||
#define NAE_RX_IF_BASE_CONFIG2 NAE_REG(7, 0, 0x14)
|
||||
#define NAE_RX_IF_BASE_CONFIG3 NAE_REG(7, 0, 0x15)
|
||||
#define NAE_RX_IF_BASE_CONFIG4 NAE_REG(7, 0, 0x16)
|
||||
#define NAE_RX_IF_BASE_CONFIG5 NAE_REG(7, 0, 0x17)
|
||||
#define NAE_RX_IF_BASE_CONFIG6 NAE_REG(7, 0, 0x18)
|
||||
#define NAE_RX_IF_BASE_CONFIG7 NAE_REG(7, 0, 0x19)
|
||||
#define NAE_RX_IF_BASE_CONFIG8 NAE_REG(7, 0, 0x1a)
|
||||
#define NAE_RX_IF_BASE_CONFIG9 NAE_REG(7, 0, 0x1b)
|
||||
#define NAE_RX_IF_VEC_VALID NAE_REG(7, 0, 0x1c)
|
||||
#define NAE_RX_IF_SLOT_CAL NAE_REG(7, 0, 0x1d)
|
||||
#define NAE_PARSER_CONFIG NAE_REG(7, 0, 0x1e)
|
||||
#define NAE_PARSER_SEQ_FIFO_CFG NAE_REG(7, 0, 0x1f)
|
||||
#define NAE_FREE_IN_FIFO_CFG NAE_REG(7, 0, 0x20)
|
||||
#define NAE_RXBUF_BASE_DPTH_ADDR NAE_REG(7, 0, 0x21)
|
||||
#define NAE_RXBUF_BASE_DPTH NAE_REG(7, 0, 0x22)
|
||||
#define NAE_RX_UCORE_CFG NAE_REG(7, 0, 0x23)
|
||||
#define NAE_RX_UCORE_CAM_MASK0 NAE_REG(7, 0, 0x24)
|
||||
#define NAE_RX_UCORE_CAM_MASK1 NAE_REG(7, 0, 0x25)
|
||||
#define NAE_RX_UCORE_CAM_MASK2 NAE_REG(7, 0, 0x26)
|
||||
#define NAE_RX_UCORE_CAM_MASK3 NAE_REG(7, 0, 0x27)
|
||||
#define NAE_FREEIN_FIFO_UNIQ_SZ_CFG NAE_REG(7, 0, 0x28)
|
||||
#define NAE_RX_CRC_POLY0_CFG NAE_REG(7, 0, 0x2a)
|
||||
#define NAE_RX_CRC_POLY1_CFG NAE_REG(7, 0, 0x2b)
|
||||
#define NAE_FREE_SPILL0_MEM_CFG NAE_REG(7, 0, 0x2c)
|
||||
#define NAE_FREE_SPILL1_MEM_CFG NAE_REG(7, 0, 0x2d)
|
||||
#define NAE_FREEFIFO_THRESH_CFG NAE_REG(7, 0, 0x2e)
|
||||
#define NAE_FLOW_CRC16_POLY_CFG NAE_REG(7, 0, 0x2f)
|
||||
#define NAE_EGR_NIOR_CAL_LEN_REG NAE_REG(7, 0, 0x4e)
|
||||
#define NAE_EGR_NIOR_CRDT_CAL_PROG NAE_REG(7, 0, 0x52)
|
||||
#define NAE_TEST NAE_REG(7, 0, 0x5f)
|
||||
#define NAE_BIU_TIMEOUT_CFG NAE_REG(7, 0, 0x60)
|
||||
#define NAE_BIU_CFG NAE_REG(7, 0, 0x61)
|
||||
#define NAE_RX_FREE_FIFO_POP NAE_REG(7, 0, 0x62)
|
||||
#define NAE_RX_DSBL_ECC NAE_REG(7, 0, 0x63)
|
||||
#define NAE_FLOW_BASEMASK_CFG NAE_REG(7, 0, 0x80)
|
||||
#define NAE_POE_CLASS_SETUP_CFG NAE_REG(7, 0, 0x81)
|
||||
#define NAE_UCORE_IFACEMASK_CFG NAE_REG(7, 0, 0x82)
|
||||
#define NAE_RXBUF_XOFFON_THRESH NAE_REG(7, 0, 0x83)
|
||||
#define NAE_FLOW_TABLE1_CFG NAE_REG(7, 0, 0x84)
|
||||
#define NAE_FLOW_TABLE2_CFG NAE_REG(7, 0, 0x85)
|
||||
#define NAE_FLOW_TABLE3_CFG NAE_REG(7, 0, 0x86)
|
||||
#define NAE_RX_FREE_FIFO_THRESH NAE_REG(7, 0, 0x87)
|
||||
#define NAE_RX_PARSER_UNCLA NAE_REG(7, 0, 0x88)
|
||||
#define NAE_RX_BUF_INTR_THRESH NAE_REG(7, 0, 0x89)
|
||||
#define NAE_IFACE_FIFO_CFG NAE_REG(7, 0, 0x8a)
|
||||
#define NAE_PARSER_SEQ_FIFO_THRESH_CFG NAE_REG(7, 0, 0x8b)
|
||||
#define NAE_RX_ERRINJ_CTRL0 NAE_REG(7, 0, 0x8c)
|
||||
#define NAE_RX_ERRINJ_CTRL1 NAE_REG(7, 0, 0x8d)
|
||||
#define NAE_RX_ERR_LATCH0 NAE_REG(7, 0, 0x8e)
|
||||
#define NAE_RX_ERR_LATCH1 NAE_REG(7, 0, 0x8f)
|
||||
#define NAE_RX_PERF_CTR_CFG NAE_REG(7, 0, 0xa0)
|
||||
#define NAE_RX_PERF_CTR_VAL NAE_REG(7, 0, 0xa1)
|
||||
|
||||
/* NAE hardware parser registers */
|
||||
#define NAE_L2_TYPE_PORT0 NAE_REG(7, 0, 0x210)
|
||||
#define NAE_L2_TYPE_PORT1 NAE_REG(7, 0, 0x211)
|
||||
#define NAE_L2_TYPE_PORT2 NAE_REG(7, 0, 0x212)
|
||||
#define NAE_L2_TYPE_PORT3 NAE_REG(7, 0, 0x213)
|
||||
#define NAE_L2_TYPE_PORT4 NAE_REG(7, 0, 0x214)
|
||||
#define NAE_L2_TYPE_PORT5 NAE_REG(7, 0, 0x215)
|
||||
#define NAE_L2_TYPE_PORT6 NAE_REG(7, 0, 0x216)
|
||||
#define NAE_L2_TYPE_PORT7 NAE_REG(7, 0, 0x217)
|
||||
#define NAE_L2_TYPE_PORT8 NAE_REG(7, 0, 0x218)
|
||||
#define NAE_L2_TYPE_PORT9 NAE_REG(7, 0, 0x219)
|
||||
#define NAE_L2_TYPE_PORT10 NAE_REG(7, 0, 0x21a)
|
||||
#define NAE_L2_TYPE_PORT11 NAE_REG(7, 0, 0x21b)
|
||||
#define NAE_L2_TYPE_PORT12 NAE_REG(7, 0, 0x21c)
|
||||
#define NAE_L2_TYPE_PORT13 NAE_REG(7, 0, 0x21d)
|
||||
#define NAE_L2_TYPE_PORT14 NAE_REG(7, 0, 0x21e)
|
||||
#define NAE_L2_TYPE_PORT15 NAE_REG(7, 0, 0x21f)
|
||||
#define NAE_L2_TYPE_PORT16 NAE_REG(7, 0, 0x220)
|
||||
#define NAE_L2_TYPE_PORT17 NAE_REG(7, 0, 0x221)
|
||||
#define NAE_L2_TYPE_PORT18 NAE_REG(7, 0, 0x222)
|
||||
#define NAE_L2_TYPE_PORT19 NAE_REG(7, 0, 0x223)
|
||||
#define NAE_L3_CTABLE_MASK0 NAE_REG(7, 0, 0x22c)
|
||||
#define NAE_L3_CTABLE_MASK1 NAE_REG(7, 0, 0x22d)
|
||||
#define NAE_L3_CTABLE_MASK2 NAE_REG(7, 0, 0x22e)
|
||||
#define NAE_L3_CTABLE_MASK3 NAE_REG(7, 0, 0x22f)
|
||||
#define NAE_L3CTABLE0 NAE_REG(7, 0, 0x230)
|
||||
#define NAE_L3CTABLE1 NAE_REG(7, 0, 0x231)
|
||||
#define NAE_L3CTABLE2 NAE_REG(7, 0, 0x232)
|
||||
#define NAE_L3CTABLE3 NAE_REG(7, 0, 0x233)
|
||||
#define NAE_L3CTABLE4 NAE_REG(7, 0, 0x234)
|
||||
#define NAE_L3CTABLE5 NAE_REG(7, 0, 0x235)
|
||||
#define NAE_L3CTABLE6 NAE_REG(7, 0, 0x236)
|
||||
#define NAE_L3CTABLE7 NAE_REG(7, 0, 0x237)
|
||||
#define NAE_L3CTABLE8 NAE_REG(7, 0, 0x238)
|
||||
#define NAE_L3CTABLE9 NAE_REG(7, 0, 0x239)
|
||||
#define NAE_L3CTABLE10 NAE_REG(7, 0, 0x23a)
|
||||
#define NAE_L3CTABLE11 NAE_REG(7, 0, 0x23b)
|
||||
#define NAE_L3CTABLE12 NAE_REG(7, 0, 0x23c)
|
||||
#define NAE_L3CTABLE13 NAE_REG(7, 0, 0x23d)
|
||||
#define NAE_L3CTABLE14 NAE_REG(7, 0, 0x23e)
|
||||
#define NAE_L3CTABLE15 NAE_REG(7, 0, 0x23f)
|
||||
#define NAE_L4CTABLE0 NAE_REG(7, 0, 0x250)
|
||||
#define NAE_L4CTABLE1 NAE_REG(7, 0, 0x251)
|
||||
#define NAE_L4CTABLE2 NAE_REG(7, 0, 0x252)
|
||||
#define NAE_L4CTABLE3 NAE_REG(7, 0, 0x253)
|
||||
#define NAE_L4CTABLE4 NAE_REG(7, 0, 0x254)
|
||||
#define NAE_L4CTABLE5 NAE_REG(7, 0, 0x255)
|
||||
#define NAE_L4CTABLE6 NAE_REG(7, 0, 0x256)
|
||||
#define NAE_L4CTABLE7 NAE_REG(7, 0, 0x257)
|
||||
#define NAE_IPV6_EXT_HEADER0 NAE_REG(7, 0, 0x260)
|
||||
#define NAE_IPV6_EXT_HEADER1 NAE_REG(7, 0, 0x261)
|
||||
#define NAE_VLAN_TYPES01 NAE_REG(7, 0, 0x262)
|
||||
#define NAE_VLAN_TYPES23 NAE_REG(7, 0, 0x263)
|
||||
|
||||
/* NAE Egress path registers */
|
||||
#define NAE_TX_CONFIG NAE_REG(7, 0, 0x11)
|
||||
#define NAE_DMA_TX_CREDIT_TH NAE_REG(7, 0, 0x29)
|
||||
#define NAE_STG1_STG2CRDT_CMD NAE_REG(7, 0, 0x30)
|
||||
#define NAE_STG2_EHCRDT_CMD NAE_REG(7, 0, 0x32)
|
||||
#define NAE_EH_FREECRDT_CMD NAE_REG(7, 0, 0x34)
|
||||
#define NAE_STG2_STRCRDT_CMD NAE_REG(7, 0, 0x36)
|
||||
#define NAE_TXFIFO_IFACEMAP_CMD NAE_REG(7, 0, 0x38)
|
||||
#define NAE_VFBID_DESTMAP_CMD NAE_REG(7, 0, 0x3a)
|
||||
#define NAE_STG1_PMEM_PROG NAE_REG(7, 0, 0x3c)
|
||||
#define NAE_STG2_PMEM_PROG NAE_REG(7, 0, 0x3e)
|
||||
#define NAE_EH_PMEM_PROG NAE_REG(7, 0, 0x40)
|
||||
#define NAE_FREE_PMEM_PROG NAE_REG(7, 0, 0x42)
|
||||
#define NAE_TX_DDR_ACTVLIST_CMD NAE_REG(7, 0, 0x44)
|
||||
#define NAE_TX_IF_BURSTMAX_CMD NAE_REG(7, 0, 0x46)
|
||||
#define NAE_TX_IF_ENABLE_CMD NAE_REG(7, 0, 0x48)
|
||||
#define NAE_TX_PKTLEN_PMEM_CMD NAE_REG(7, 0, 0x4a)
|
||||
#define NAE_TX_SCHED_MAP_CMD0 NAE_REG(7, 0, 0x4c)
|
||||
#define NAE_TX_SCHED_MAP_CMD1 NAE_REG(7, 0, 0x4d)
|
||||
#define NAE_TX_PKT_PMEM_CMD0 NAE_REG(7, 0, 0x50)
|
||||
#define NAE_TX_PKT_PMEM_CMD1 NAE_REG(7, 0, 0x51)
|
||||
#define NAE_TX_SCHED_CTRL NAE_REG(7, 0, 0x53)
|
||||
#define NAE_TX_CRC_POLY0 NAE_REG(7, 0, 0x54)
|
||||
#define NAE_TX_CRC_POLY1 NAE_REG(7, 0, 0x55)
|
||||
#define NAE_TX_CRC_POLY2 NAE_REG(7, 0, 0x56)
|
||||
#define NAE_TX_CRC_POLY3 NAE_REG(7, 0, 0x57)
|
||||
#define NAE_STR_PMEM_CMD NAE_REG(7, 0, 0x58)
|
||||
#define NAE_TX_IORCRDT_INIT NAE_REG(7, 0, 0x59)
|
||||
#define NAE_TX_DSBL_ECC NAE_REG(7, 0, 0x5a)
|
||||
#define NAE_TX_IORCRDT_IGNORE NAE_REG(7, 0, 0x5b)
|
||||
#define NAE_IF0_1588_TMSTMP_HI NAE_REG(7, 0, 0x300)
|
||||
#define NAE_IF1_1588_TMSTMP_HI NAE_REG(7, 0, 0x302)
|
||||
#define NAE_IF2_1588_TMSTMP_HI NAE_REG(7, 0, 0x304)
|
||||
#define NAE_IF3_1588_TMSTMP_HI NAE_REG(7, 0, 0x306)
|
||||
#define NAE_IF4_1588_TMSTMP_HI NAE_REG(7, 0, 0x308)
|
||||
#define NAE_IF5_1588_TMSTMP_HI NAE_REG(7, 0, 0x30a)
|
||||
#define NAE_IF6_1588_TMSTMP_HI NAE_REG(7, 0, 0x30c)
|
||||
#define NAE_IF7_1588_TMSTMP_HI NAE_REG(7, 0, 0x30e)
|
||||
#define NAE_IF8_1588_TMSTMP_HI NAE_REG(7, 0, 0x310)
|
||||
#define NAE_IF9_1588_TMSTMP_HI NAE_REG(7, 0, 0x312)
|
||||
#define NAE_IF10_1588_TMSTMP_HI NAE_REG(7, 0, 0x314)
|
||||
#define NAE_IF11_1588_TMSTMP_HI NAE_REG(7, 0, 0x316)
|
||||
#define NAE_IF12_1588_TMSTMP_HI NAE_REG(7, 0, 0x318)
|
||||
#define NAE_IF13_1588_TMSTMP_HI NAE_REG(7, 0, 0x31a)
|
||||
#define NAE_IF14_1588_TMSTMP_HI NAE_REG(7, 0, 0x31c)
|
||||
#define NAE_IF15_1588_TMSTMP_HI NAE_REG(7, 0, 0x31e)
|
||||
#define NAE_IF16_1588_TMSTMP_HI NAE_REG(7, 0, 0x320)
|
||||
#define NAE_IF17_1588_TMSTMP_HI NAE_REG(7, 0, 0x322)
|
||||
#define NAE_IF18_1588_TMSTMP_HI NAE_REG(7, 0, 0x324)
|
||||
#define NAE_IF19_1588_TMSTMP_HI NAE_REG(7, 0, 0x326)
|
||||
#define NAE_IF0_1588_TMSTMP_LO NAE_REG(7, 0, 0x301)
|
||||
#define NAE_IF1_1588_TMSTMP_LO NAE_REG(7, 0, 0x303)
|
||||
#define NAE_IF2_1588_TMSTMP_LO NAE_REG(7, 0, 0x305)
|
||||
#define NAE_IF3_1588_TMSTMP_LO NAE_REG(7, 0, 0x307)
|
||||
#define NAE_IF4_1588_TMSTMP_LO NAE_REG(7, 0, 0x309)
|
||||
#define NAE_IF5_1588_TMSTMP_LO NAE_REG(7, 0, 0x30b)
|
||||
#define NAE_IF6_1588_TMSTMP_LO NAE_REG(7, 0, 0x30d)
|
||||
#define NAE_IF7_1588_TMSTMP_LO NAE_REG(7, 0, 0x30f)
|
||||
#define NAE_IF8_1588_TMSTMP_LO NAE_REG(7, 0, 0x311)
|
||||
#define NAE_IF9_1588_TMSTMP_LO NAE_REG(7, 0, 0x313)
|
||||
#define NAE_IF10_1588_TMSTMP_LO NAE_REG(7, 0, 0x315)
|
||||
#define NAE_IF11_1588_TMSTMP_LO NAE_REG(7, 0, 0x317)
|
||||
#define NAE_IF12_1588_TMSTMP_LO NAE_REG(7, 0, 0x319)
|
||||
#define NAE_IF13_1588_TMSTMP_LO NAE_REG(7, 0, 0x31b)
|
||||
#define NAE_IF14_1588_TMSTMP_LO NAE_REG(7, 0, 0x31d)
|
||||
#define NAE_IF15_1588_TMSTMP_LO NAE_REG(7, 0, 0x31f)
|
||||
#define NAE_IF16_1588_TMSTMP_LO NAE_REG(7, 0, 0x321)
|
||||
#define NAE_IF17_1588_TMSTMP_LO NAE_REG(7, 0, 0x323)
|
||||
#define NAE_IF18_1588_TMSTMP_LO NAE_REG(7, 0, 0x325)
|
||||
#define NAE_IF19_1588_TMSTMP_LO NAE_REG(7, 0, 0x327)
|
||||
#define NAE_TX_EL0 NAE_REG(7, 0, 0x328)
|
||||
#define NAE_TX_EL1 NAE_REG(7, 0, 0x329)
|
||||
#define NAE_EIC0 NAE_REG(7, 0, 0x32a)
|
||||
#define NAE_EIC1 NAE_REG(7, 0, 0x32b)
|
||||
#define NAE_STG1_STG2CRDT_STATUS NAE_REG(7, 0, 0x32c)
|
||||
#define NAE_STG2_EHCRDT_STATUS NAE_REG(7, 0, 0x32d)
|
||||
#define NAE_STG2_FREECRDT_STATUS NAE_REG(7, 0, 0x32e)
|
||||
#define NAE_STG2_STRCRDT_STATUS NAE_REG(7, 0, 0x32f)
|
||||
#define NAE_TX_PERF_CNTR_INTR_STATUS NAE_REG(7, 0, 0x330)
|
||||
#define NAE_TX_PERF_CNTR_ROLL_STATUS NAE_REG(7, 0, 0x331)
|
||||
#define NAE_TX_PERF_CNTR0 NAE_REG(7, 0, 0x332)
|
||||
#define NAE_TX_PERF_CNTR1 NAE_REG(7, 0, 0x334)
|
||||
#define NAE_TX_PERF_CNTR2 NAE_REG(7, 0, 0x336)
|
||||
#define NAE_TX_PERF_CNTR3 NAE_REG(7, 0, 0x338)
|
||||
#define NAE_TX_PERF_CNTR4 NAE_REG(7, 0, 0x33a)
|
||||
#define NAE_TX_PERF_CNTR0_CTL NAE_REG(7, 0, 0x333)
|
||||
#define NAE_TX_PERF_CNTR1_CTL NAE_REG(7, 0, 0x335)
|
||||
#define NAE_TX_PERF_CNTR2_CTL NAE_REG(7, 0, 0x337)
|
||||
#define NAE_TX_PERF_CNTR3_CTL NAE_REG(7, 0, 0x339)
|
||||
#define NAE_TX_PERF_CNTR4_CTL NAE_REG(7, 0, 0x33b)
|
||||
#define NAE_VFBID_DESTMAP_STATUS NAE_REG(7, 0, 0x380)
|
||||
#define NAE_STG2_PMEM_STATUS NAE_REG(7, 0, 0x381)
|
||||
#define NAE_EH_PMEM_STATUS NAE_REG(7, 0, 0x382)
|
||||
#define NAE_FREE_PMEM_STATUS NAE_REG(7, 0, 0x383)
|
||||
#define NAE_TX_DDR_ACTVLIST_STATUS NAE_REG(7, 0, 0x384)
|
||||
#define NAE_TX_IF_BURSTMAX_STATUS NAE_REG(7, 0, 0x385)
|
||||
#define NAE_TX_PKTLEN_PMEM_STATUS NAE_REG(7, 0, 0x386)
|
||||
#define NAE_TX_SCHED_MAP_STATUS0 NAE_REG(7, 0, 0x387)
|
||||
#define NAE_TX_SCHED_MAP_STATUS1 NAE_REG(7, 0, 0x388)
|
||||
#define NAE_TX_PKT_PMEM_STATUS NAE_REG(7, 0, 0x389)
|
||||
#define NAE_STR_PMEM_STATUS NAE_REG(7, 0, 0x38a)
|
||||
|
||||
/* Network interface interrupt registers */
|
||||
#define NAE_NET_IF0_INTR_STAT NAE_REG(7, 0, 0x280)
|
||||
#define NAE_NET_IF1_INTR_STAT NAE_REG(7, 0, 0x282)
|
||||
#define NAE_NET_IF2_INTR_STAT NAE_REG(7, 0, 0x284)
|
||||
#define NAE_NET_IF3_INTR_STAT NAE_REG(7, 0, 0x286)
|
||||
#define NAE_NET_IF4_INTR_STAT NAE_REG(7, 0, 0x288)
|
||||
#define NAE_NET_IF5_INTR_STAT NAE_REG(7, 0, 0x28a)
|
||||
#define NAE_NET_IF6_INTR_STAT NAE_REG(7, 0, 0x28c)
|
||||
#define NAE_NET_IF7_INTR_STAT NAE_REG(7, 0, 0x28e)
|
||||
#define NAE_NET_IF8_INTR_STAT NAE_REG(7, 0, 0x290)
|
||||
#define NAE_NET_IF9_INTR_STAT NAE_REG(7, 0, 0x292)
|
||||
#define NAE_NET_IF10_INTR_STAT NAE_REG(7, 0, 0x294)
|
||||
#define NAE_NET_IF11_INTR_STAT NAE_REG(7, 0, 0x296)
|
||||
#define NAE_NET_IF12_INTR_STAT NAE_REG(7, 0, 0x298)
|
||||
#define NAE_NET_IF13_INTR_STAT NAE_REG(7, 0, 0x29a)
|
||||
#define NAE_NET_IF14_INTR_STAT NAE_REG(7, 0, 0x29c)
|
||||
#define NAE_NET_IF15_INTR_STAT NAE_REG(7, 0, 0x29e)
|
||||
#define NAE_NET_IF16_INTR_STAT NAE_REG(7, 0, 0x2a0)
|
||||
#define NAE_NET_IF17_INTR_STAT NAE_REG(7, 0, 0x2a2)
|
||||
#define NAE_NET_IF18_INTR_STAT NAE_REG(7, 0, 0x2a4)
|
||||
#define NAE_NET_IF19_INTR_STAT NAE_REG(7, 0, 0x2a6)
|
||||
#define NAE_NET_IF0_INTR_MASK NAE_REG(7, 0, 0x281)
|
||||
#define NAE_NET_IF1_INTR_MASK NAE_REG(7, 0, 0x283)
|
||||
#define NAE_NET_IF2_INTR_MASK NAE_REG(7, 0, 0x285)
|
||||
#define NAE_NET_IF3_INTR_MASK NAE_REG(7, 0, 0x287)
|
||||
#define NAE_NET_IF4_INTR_MASK NAE_REG(7, 0, 0x289)
|
||||
#define NAE_NET_IF5_INTR_MASK NAE_REG(7, 0, 0x28b)
|
||||
#define NAE_NET_IF6_INTR_MASK NAE_REG(7, 0, 0x28d)
|
||||
#define NAE_NET_IF7_INTR_MASK NAE_REG(7, 0, 0x28f)
|
||||
#define NAE_NET_IF8_INTR_MASK NAE_REG(7, 0, 0x291)
|
||||
#define NAE_NET_IF9_INTR_MASK NAE_REG(7, 0, 0x293)
|
||||
#define NAE_NET_IF10_INTR_MASK NAE_REG(7, 0, 0x295)
|
||||
#define NAE_NET_IF11_INTR_MASK NAE_REG(7, 0, 0x297)
|
||||
#define NAE_NET_IF12_INTR_MASK NAE_REG(7, 0, 0x299)
|
||||
#define NAE_NET_IF13_INTR_MASK NAE_REG(7, 0, 0x29b)
|
||||
#define NAE_NET_IF14_INTR_MASK NAE_REG(7, 0, 0x29d)
|
||||
#define NAE_NET_IF15_INTR_MASK NAE_REG(7, 0, 0x29f)
|
||||
#define NAE_NET_IF16_INTR_MASK NAE_REG(7, 0, 0x2a1)
|
||||
#define NAE_NET_IF17_INTR_MASK NAE_REG(7, 0, 0x2a3)
|
||||
#define NAE_NET_IF18_INTR_MASK NAE_REG(7, 0, 0x2a5)
|
||||
#define NAE_NET_IF19_INTR_MASK NAE_REG(7, 0, 0x2a7)
|
||||
#define NAE_COMMON0_INTR_STAT NAE_REG(7, 0, 0x2a8)
|
||||
#define NAE_COMMON0_INTR_MASK NAE_REG(7, 0, 0x2a9)
|
||||
#define NAE_COMMON1_INTR_STAT NAE_REG(7, 0, 0x2aa)
|
||||
#define NAE_COMMON1_INTR_MASK NAE_REG(7, 0, 0x2ab)
|
||||
|
||||
/* Network Interface Low-block Registers */
|
||||
#define NAE_PHY_LANE0_STATUS(block) NAE_REG(block, 0xe, 0)
|
||||
#define NAE_PHY_LANE1_STATUS(block) NAE_REG(block, 0xe, 1)
|
||||
#define NAE_PHY_LANE2_STATUS(block) NAE_REG(block, 0xe, 2)
|
||||
#define NAE_PHY_LANE3_STATUS(block) NAE_REG(block, 0xe, 3)
|
||||
#define NAE_PHY_LANE0_CTRL(block) NAE_REG(block, 0xe, 4)
|
||||
#define NAE_PHY_LANE1_CTRL(block) NAE_REG(block, 0xe, 5)
|
||||
#define NAE_PHY_LANE2_CTRL(block) NAE_REG(block, 0xe, 6)
|
||||
#define NAE_PHY_LANE3_CTRL(block) NAE_REG(block, 0xe, 7)
|
||||
|
||||
/* Network interface Top-block registers */
|
||||
#define NAE_LANE_CFG_CPLX_0_1 NAE_REG(7, 0, 0x780)
|
||||
#define NAE_LANE_CFG_CPLX_2_3 NAE_REG(7, 0, 0x781)
|
||||
#define NAE_LANE_CFG_CPLX_4 NAE_REG(7, 0, 0x782)
|
||||
#define NAE_LANE_CFG_SOFTRESET NAE_REG(7, 0, 0x783)
|
||||
#define NAE_1588_PTP_OFFSET_HI NAE_REG(7, 0, 0x784)
|
||||
#define NAE_1588_PTP_OFFSET_LO NAE_REG(7, 0, 0x785)
|
||||
#define NAE_1588_PTP_INC_DEN NAE_REG(7, 0, 0x786)
|
||||
#define NAE_1588_PTP_INC_NUM NAE_REG(7, 0, 0x787)
|
||||
#define NAE_1588_PTP_INC_INTG NAE_REG(7, 0, 0x788)
|
||||
#define NAE_1588_PTP_CONTROL NAE_REG(7, 0, 0x789)
|
||||
#define NAE_1588_PTP_STATUS NAE_REG(7, 0, 0x78a)
|
||||
#define NAE_1588_PTP_USER_VALUE_HI NAE_REG(7, 0, 0x78b)
|
||||
#define NAE_1588_PTP_USER_VALUE_LO NAE_REG(7, 0, 0x78c)
|
||||
#define NAE_1588_PTP_TMR1_HI NAE_REG(7, 0, 0x78d)
|
||||
#define NAE_1588_PTP_TMR1_LO NAE_REG(7, 0, 0x78e)
|
||||
#define NAE_1588_PTP_TMR2_HI NAE_REG(7, 0, 0x78f)
|
||||
#define NAE_1588_PTP_TMR2_LO NAE_REG(7, 0, 0x790)
|
||||
#define NAE_1588_PTP_TMR3_HI NAE_REG(7, 0, 0x791)
|
||||
#define NAE_1588_PTP_TMR3_LO NAE_REG(7, 0, 0x792)
|
||||
#define NAE_TX_FC_CAL_IDX_TBL_CTRL NAE_REG(7, 0, 0x793)
|
||||
#define NAE_TX_FC_CAL_TBL_CTRL NAE_REG(7, 0, 0x794)
|
||||
#define NAE_TX_FC_CAL_TBL_DATA0 NAE_REG(7, 0, 0x795)
|
||||
#define NAE_TX_FC_CAL_TBL_DATA1 NAE_REG(7, 0, 0x796)
|
||||
#define NAE_TX_FC_CAL_TBL_DATA2 NAE_REG(7, 0, 0x797)
|
||||
#define NAE_TX_FC_CAL_TBL_DATA3 NAE_REG(7, 0, 0x798)
|
||||
#define NAE_INT_MDIO_CTRL NAE_REG(7, 0, 0x799)
|
||||
#define NAE_INT_MDIO_CTRL_DATA NAE_REG(7, 0, 0x79a)
|
||||
#define NAE_INT_MDIO_RD_STAT NAE_REG(7, 0, 0x79b)
|
||||
#define NAE_INT_MDIO_LINK_STAT NAE_REG(7, 0, 0x79c)
|
||||
#define NAE_EXT_G0_MDIO_CTRL NAE_REG(7, 0, 0x79d)
|
||||
#define NAE_EXT_G1_MDIO_CTRL NAE_REG(7, 0, 0x7a1)
|
||||
#define NAE_EXT_G0_MDIO_CTRL_DATA NAE_REG(7, 0, 0x79e)
|
||||
#define NAE_EXT_G1_MDIO_CTRL_DATA NAE_REG(7, 0, 0x7a2)
|
||||
#define NAE_EXT_G0_MDIO_RD_STAT NAE_REG(7, 0, 0x79f)
|
||||
#define NAE_EXT_G1_MDIO_RD_STAT NAE_REG(7, 0, 0x7a3)
|
||||
#define NAE_EXT_G0_MDIO_LINK_STAT NAE_REG(7, 0, 0x7a0)
|
||||
#define NAE_EXT_G1_MDIO_LINK_STAT NAE_REG(7, 0, 0x7a4)
|
||||
#define NAE_EXT_XG0_MDIO_CTRL NAE_REG(7, 0, 0x7a5)
|
||||
#define NAE_EXT_XG1_MDIO_CTRL NAE_REG(7, 0, 0x7a9)
|
||||
#define NAE_EXT_XG0_MDIO_CTRL_DATA NAE_REG(7, 0, 0x7a6)
|
||||
#define NAE_EXT_XG1_MDIO_CTRL_DATA NAE_REG(7, 0, 0x7aa)
|
||||
#define NAE_EXT_XG0_MDIO_RD_STAT NAE_REG(7, 0, 0x7a7)
|
||||
#define NAE_EXT_XG1_MDIO_RD_STAT NAE_REG(7, 0, 0x7ab)
|
||||
#define NAE_EXT_XG0_MDIO_LINK_STAT NAE_REG(7, 0, 0x7a8)
|
||||
#define NAE_EXT_XG1_MDIO_LINK_STAT NAE_REG(7, 0, 0x7ac)
|
||||
#define NAE_GMAC_FC_SLOT0 NAE_REG(7, 0, 0x7ad)
|
||||
#define NAE_GMAC_FC_SLOT1 NAE_REG(7, 0, 0x7ae)
|
||||
#define NAE_GMAC_FC_SLOT2 NAE_REG(7, 0, 0x7af)
|
||||
#define NAE_GMAC_FC_SLOT3 NAE_REG(7, 0, 0x7b0)
|
||||
#define NAE_NETIOR_NTB_SLOT NAE_REG(7, 0, 0x7b1)
|
||||
#define NAE_NETIOR_MISC_CTRL0 NAE_REG(7, 0, 0x7b2)
|
||||
#define NAE_NETIOR_INT0 NAE_REG(7, 0, 0x7b3)
|
||||
#define NAE_NETIOR_INT0_MASK NAE_REG(7, 0, 0x7b4)
|
||||
#define NAE_NETIOR_INT1 NAE_REG(7, 0, 0x7b5)
|
||||
#define NAE_NETIOR_INT1_MASK NAE_REG(7, 0, 0x7b6)
|
||||
#define NAE_GMAC_PFC_REPEAT NAE_REG(7, 0, 0x7b7)
|
||||
#define NAE_XGMAC_PFC_REPEAT NAE_REG(7, 0, 0x7b8)
|
||||
#define NAE_NETIOR_MISC_CTRL1 NAE_REG(7, 0, 0x7b9)
|
||||
#define NAE_NETIOR_MISC_CTRL2 NAE_REG(7, 0, 0x7ba)
|
||||
#define NAE_NETIOR_INT2 NAE_REG(7, 0, 0x7bb)
|
||||
#define NAE_NETIOR_INT2_MASK NAE_REG(7, 0, 0x7bc)
|
||||
#define NAE_NETIOR_MISC_CTRL3 NAE_REG(7, 0, 0x7bd)
|
||||
|
||||
/* Network interface lane configuration registers */
|
||||
#define NAE_LANE_CFG_MISCREG1 NAE_REG(7, 0xf, 0x39)
|
||||
#define NAE_LANE_CFG_MISCREG2 NAE_REG(7, 0xf, 0x3A)
|
||||
|
||||
/* Network interface soft reset register */
|
||||
#define NAE_SOFT_RESET NAE_REG(7, 0xf, 3)
|
||||
|
||||
/* ucore instruction/shared CAM RAM access */
|
||||
#define NAE_UCORE_SHARED_RAM_OFFSET 0x10000
|
||||
|
||||
#define PORTS_PER_CMPLX 4
|
||||
#define NAE_CACHELINE_SIZE 64
|
||||
|
||||
#define PHY_LANE_0_CTRL 4
|
||||
#define PHY_LANE_1_CTRL 5
|
||||
#define PHY_LANE_2_CTRL 6
|
||||
#define PHY_LANE_3_CTRL 7
|
||||
|
||||
#define PHY_LANE_STAT_SRCS 0x00000001
|
||||
#define PHY_LANE_STAT_STD 0x00000010
|
||||
#define PHY_LANE_STAT_SFEA 0x00000020
|
||||
#define PHY_LANE_STAT_STCS 0x00000040
|
||||
#define PHY_LANE_STAT_SPC 0x00000200
|
||||
#define PHY_LANE_STAT_XLF 0x00000400
|
||||
#define PHY_LANE_STAT_PCR 0x00000800
|
||||
|
||||
#define PHY_LANE_CTRL_DATA_POS 0
|
||||
#define PHY_LANE_CTRL_ADDR_POS 8
|
||||
#define PHY_LANE_CTRL_CMD_READ 0x00010000
|
||||
#define PHY_LANE_CTRL_CMD_WRITE 0x00000000
|
||||
#define PHY_LANE_CTRL_CMD_START 0x00020000
|
||||
#define PHY_LANE_CTRL_CMD_PENDING 0x00040000
|
||||
#define PHY_LANE_CTRL_ALL 0x00200000
|
||||
#define PHY_LANE_CTRL_FAST_INIT 0x00400000
|
||||
#define PHY_LANE_CTRL_REXSEL_POS 23
|
||||
#define PHY_LANE_CTRL_PHYMODE_POS 25
|
||||
#define PHY_LANE_CTRL_PWRDOWN 0x20000000
|
||||
#define PHY_LANE_CTRL_RST 0x40000000
|
||||
#define PHY_LANE_CTRL_RST_XAUI 0xc0000000
|
||||
#define PHY_LANE_CTRL_BPC_XAUI 0x80000000
|
||||
|
||||
#define LANE_CFG_CPLX_0_1 0x0
|
||||
#define LANE_CFG_CPLX_2_3 0x1
|
||||
#define LANE_CFG_CPLX_4 0x2
|
||||
|
||||
#define MAC_CONF1 0x0
|
||||
#define MAC_CONF2 0x1
|
||||
#define MAX_FRM 0x4
|
||||
|
||||
#define NETIOR_GMAC_CTRL1 0x7F
|
||||
#define NETIOR_GMAC_CTRL2 0x7E
|
||||
#define NETIOR_GMAC_CTRL3 0x7C
|
||||
|
||||
#define SGMII_CAL_SLOTS 3
|
||||
#define XAUI_CAL_SLOTS 13
|
||||
#define IL8_CAL_SLOTS 26
|
||||
#define IL4_CAL_SLOTS 10
|
||||
|
||||
#define NAE_DRR_QUANTA 2048
|
||||
|
||||
#define XLP3XX_STG2_FIFO_SZ 512
|
||||
#define XLP3XX_EH_FIFO_SZ 512
|
||||
#define XLP3XX_FROUT_FIFO_SZ 512
|
||||
#define XLP3XX_MS_FIFO_SZ 512
|
||||
#define XLP3XX_PKT_FIFO_SZ 8192
|
||||
#define XLP3XX_PKTLEN_FIFO_SZ 512
|
||||
|
||||
#define XLP3XX_MAX_STG2_OFFSET 0x7F
|
||||
#define XLP3XX_MAX_EH_OFFSET 0x1f
|
||||
#define XLP3XX_MAX_FREE_OUT_OFFSET 0x1f
|
||||
#define XLP3XX_MAX_MS_OFFSET 0xF
|
||||
#define XLP3XX_MAX_PMEM_OFFSET 0x7FE
|
||||
|
||||
#define XLP3XX_STG1_2_CREDIT XLP3XX_STG2_FIFO_SZ
|
||||
#define XLP3XX_STG2_EH_CREDIT XLP3XX_EH_FIFO_SZ
|
||||
#define XLP3XX_STG2_FROUT_CREDIT XLP3XX_FROUT_FIFO_SZ
|
||||
#define XLP3XX_STG2_MS_CREDIT XLP3XX_MS_FIFO_SZ
|
||||
|
||||
#define XLP8XX_STG2_FIFO_SZ 2048
|
||||
#define XLP8XX_EH_FIFO_SZ 4096
|
||||
#define XLP8XX_FROUT_FIFO_SZ 4096
|
||||
#define XLP8XX_MS_FIFO_SZ 2048
|
||||
#define XLP8XX_PKT_FIFO_SZ 16384
|
||||
#define XLP8XX_PKTLEN_FIFO_SZ 2048
|
||||
|
||||
#define XLP8XX_MAX_STG2_OFFSET 0x7F
|
||||
#define XLP8XX_MAX_EH_OFFSET 0x7F
|
||||
#define XLP8XX_MAX_FREE_OUT_OFFSET 0x7F
|
||||
#define XLP8XX_MAX_MS_OFFSET 0x1F
|
||||
#define XLP8XX_MAX_PMEM_OFFSET 0x7FE
|
||||
|
||||
#define XLP8XX_STG1_2_CREDIT XLP8XX_STG2_FIFO_SZ
|
||||
#define XLP8XX_STG2_EH_CREDIT XLP8XX_EH_FIFO_SZ
|
||||
#define XLP8XX_STG2_FROUT_CREDIT XLP8XX_FROUT_FIFO_SZ
|
||||
#define XLP8XX_STG2_MS_CREDIT XLP8XX_MS_FIFO_SZ
|
||||
|
||||
#define MAX_CAL_SLOTS 64
|
||||
#define XLP_MAX_PORTS 18
|
||||
#define XLP_STORM_MAX_PORTS 8
|
||||
|
||||
#if !defined(LOCORE) && !defined(__ASSEMBLY__)
|
||||
|
||||
#define nlm_read_nae_reg(b, r) nlm_read_reg_xkphys(b, r)
|
||||
#define nlm_write_nae_reg(b, r, v) nlm_write_reg_xkphys(b, r, v)
|
||||
#define nlm_get_nae_pcibase(node) \
|
||||
nlm_pcicfg_base(XLP_IO_NAE_OFFSET(node))
|
||||
#define nlm_get_nae_regbase(node) \
|
||||
nlm_xkphys_map_pcibar0(nlm_get_nae_pcibase(node))
|
||||
|
||||
#define MAX_POE_CLASSES 8
|
||||
#define MAX_POE_CLASS_CTXT_TBL_SZ ((NUM_CONTEXTS / MAX_POE_CLASSES) + 1)
|
||||
#define TXINITIORCR(x) (((x) & 0x7ffff) << 8)
|
||||
|
||||
enum XLPNAE_TX_TYPE {
|
||||
P2D_NEOP = 0,
|
||||
P2P,
|
||||
P2D_EOP,
|
||||
MSC
|
||||
};
|
||||
|
||||
enum nblock_type {
|
||||
SGMIIC = 1,
|
||||
XAUIC = 2,
|
||||
ILC = 3
|
||||
};
|
||||
|
||||
enum nae_interface_type {
|
||||
GMAC_0 = 0,
|
||||
GMAC_1,
|
||||
GMAC_2,
|
||||
GMAC_3,
|
||||
XGMAC,
|
||||
INTERLAKEN,
|
||||
PHY = 0xE,
|
||||
LANE_CFG = 0xF,
|
||||
};
|
||||
|
||||
enum {
|
||||
LM_UNCONNECTED = 0,
|
||||
LM_SGMII = 1,
|
||||
LM_XAUI = 2,
|
||||
LM_IL = 3,
|
||||
};
|
||||
|
||||
enum nae_block {
|
||||
BLOCK_0 = 0,
|
||||
BLOCK_1,
|
||||
BLOCK_2,
|
||||
BLOCK_3,
|
||||
BLOCK_4,
|
||||
BLOCK_5,
|
||||
BLOCK_6,
|
||||
BLOCK_7,
|
||||
};
|
||||
|
||||
enum {
|
||||
PHYMODE_NONE = 0,
|
||||
PHYMODE_HS_SGMII = 1,
|
||||
PHYMODE_XAUI = 1,
|
||||
PHYMODE_SGMII = 2,
|
||||
PHYMODE_IL = 3,
|
||||
};
|
||||
|
||||
static __inline int
|
||||
nae_num_complex(uint64_t nae_pcibase)
|
||||
{
|
||||
return (nlm_read_reg(nae_pcibase, XLP_PCI_DEVINFO_REG0) & 0xff);
|
||||
}
|
||||
|
||||
static __inline int
|
||||
nae_num_context(uint64_t nae_pcibase)
|
||||
{
|
||||
return (nlm_read_reg(nae_pcibase, XLP_PCI_DEVINFO_REG5));
|
||||
}
|
||||
|
||||
/* per port config structure */
|
||||
struct nae_port_config {
|
||||
int num_channels;
|
||||
int num_free_descs;
|
||||
int free_desc_sizes;
|
||||
int ucore_mask;
|
||||
int loopback_mode; /* is complex is in loopback? */
|
||||
uint32_t freein_spill_size; /* Freein spill size for each port */
|
||||
uint32_t free_fifo_size; /* (512entries x 2desc/entry)1024desc */
|
||||
uint32_t iface_fifo_size;/* 256 entries x 64B/entry = 16KB */
|
||||
uint32_t pseq_fifo_size; /* 1024 entries - 1 pktlen/entry */
|
||||
uint32_t rxbuf_size; /* 4096 entries x 64B = 256KB */
|
||||
uint32_t rx_if_base_config;
|
||||
uint32_t rx_slots_reqd;
|
||||
uint32_t tx_slots_reqd;
|
||||
uint32_t stg2_fifo_size;
|
||||
uint32_t eh_fifo_size;
|
||||
uint32_t frout_fifo_size;
|
||||
uint32_t ms_fifo_size;
|
||||
uint32_t pkt_fifo_size;
|
||||
uint32_t pktlen_fifo_size;
|
||||
uint32_t max_stg2_offset;
|
||||
uint32_t max_eh_offset;
|
||||
uint32_t max_frout_offset;
|
||||
uint32_t max_ms_offset;
|
||||
uint32_t max_pmem_offset;
|
||||
uint32_t stg1_2_credit;
|
||||
uint32_t stg2_eh_credit;
|
||||
uint32_t stg2_frout_credit;
|
||||
uint32_t stg2_ms_credit;
|
||||
uint32_t vlan_pri_en;
|
||||
uint32_t txq;
|
||||
uint32_t rxfreeq;
|
||||
uint32_t ieee1588_inc_intg;
|
||||
uint32_t ieee1588_inc_den;
|
||||
uint32_t ieee1588_inc_num;
|
||||
uint64_t ieee1588_userval;
|
||||
uint64_t ieee1588_ptpoff;
|
||||
uint64_t ieee1588_tmr1;
|
||||
uint64_t ieee1588_tmr2;
|
||||
uint64_t ieee1588_tmr3;
|
||||
};
|
||||
|
||||
void nlm_nae_flush_free_fifo(uint64_t nae_base, int nblocks);
|
||||
void nlm_program_nae_parser_seq_fifo(uint64_t, int, struct nae_port_config *);
|
||||
void nlm_setup_rx_cal_cfg(uint64_t, int, struct nae_port_config *);
|
||||
void nlm_setup_tx_cal_cfg(uint64_t, int, struct nae_port_config *cfg);
|
||||
void nlm_deflate_frin_fifo_carving(uint64_t, int);
|
||||
void nlm_reset_nae(int);
|
||||
int nlm_set_nae_frequency(int, int);
|
||||
void nlm_setup_poe_class_config(uint64_t nae_base, int max_poe_classes,
|
||||
int num_contexts, int *poe_cl_tbl);
|
||||
void nlm_setup_vfbid_mapping(uint64_t);
|
||||
void nlm_setup_flow_crc_poly(uint64_t, uint32_t);
|
||||
void nlm_setup_iface_fifo_cfg(uint64_t, int, struct nae_port_config *);
|
||||
void nlm_setup_rx_base_config(uint64_t, int, struct nae_port_config *);
|
||||
void nlm_setup_rx_buf_config(uint64_t, int, struct nae_port_config *);
|
||||
void nlm_setup_freein_fifo_cfg(uint64_t, int, struct nae_port_config *);
|
||||
int nlm_get_flow_mask(int);
|
||||
void nlm_program_flow_cfg(uint64_t, int, uint32_t, uint32_t);
|
||||
void xlp_ax_nae_lane_reset_txpll(uint64_t, int, int, int);
|
||||
void xlp_nae_lane_reset_txpll(uint64_t, int, int, int);
|
||||
void xlp_nae_config_lane_gmac(uint64_t, int);
|
||||
void config_egress_fifo_carvings(uint64_t, int, int, int, int,
|
||||
struct nae_port_config *);
|
||||
void config_egress_fifo_credits(uint64_t, int, int, int, int,
|
||||
struct nae_port_config *);
|
||||
void nlm_config_freein_fifo_uniq_cfg(uint64_t, int, int);
|
||||
void nlm_config_ucore_iface_mask_cfg(uint64_t, int, int);
|
||||
int nlm_nae_init_netior(uint64_t nae_base, int nblocks);
|
||||
void nlm_nae_init_ingress(uint64_t, uint32_t);
|
||||
void nlm_nae_init_egress(uint64_t);
|
||||
uint32_t ucore_spray_config(uint32_t, uint32_t, int);
|
||||
void nlm_nae_init_ucore(uint64_t nae_base, int if_num, uint32_t ucore_mask);
|
||||
int nlm_nae_open_if(uint64_t, int, int, int, uint32_t);
|
||||
void nlm_mac_enable(uint64_t, int, int, int);
|
||||
void nlm_mac_disable(uint64_t, int, int, int);
|
||||
uint64_t nae_tx_desc(u_int, u_int, u_int, u_int, uint64_t);
|
||||
void nlm_setup_l2type(uint64_t, int, uint32_t, uint32_t, uint32_t,
|
||||
uint32_t, uint32_t, uint32_t);
|
||||
void nlm_setup_l3ctable_mask(uint64_t, int, uint32_t, uint32_t);
|
||||
void nlm_setup_l3ctable_even(uint64_t, int, uint32_t, uint32_t, uint32_t,
|
||||
uint32_t, uint32_t);
|
||||
void nlm_setup_l3ctable_odd(uint64_t, int, uint32_t, uint32_t, uint32_t,
|
||||
uint32_t, uint32_t, uint32_t);
|
||||
void nlm_setup_l4ctable_even(uint64_t, int, uint32_t, uint32_t, uint32_t,
|
||||
uint32_t, uint32_t, uint32_t);
|
||||
void nlm_setup_l4ctable_odd(uint64_t, int, uint32_t, uint32_t, uint32_t, uint32_t);
|
||||
void nlm_enable_hardware_parser(uint64_t);
|
||||
void nlm_enable_hardware_parser_per_port(uint64_t, int, int);
|
||||
void nlm_prepad_enable(uint64_t, int);
|
||||
void nlm_setup_1588_timer(uint64_t, struct nae_port_config *);
|
||||
|
||||
#endif /* !(LOCORE) && !(__ASSEMBLY__) */
|
||||
|
||||
#endif
|
||||
352
sys/mips/nlm/hal/poe.h
Normal file
352
sys/mips/nlm/hal/poe.h
Normal file
|
|
@ -0,0 +1,352 @@
|
|||
/*-
|
||||
* Copyright (c) 2003-2012 Broadcom Corporation
|
||||
* All Rights Reserved
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY BROADCOM ``AS IS'' AND ANY EXPRESS OR
|
||||
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
* ARE DISCLAIMED. IN NO EVENT SHALL BROADCOM OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
|
||||
* BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
|
||||
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
|
||||
* OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
|
||||
* IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
* $FreeBSD$
|
||||
*/
|
||||
|
||||
#ifndef __NLM_POE_H__
|
||||
#define __NLM_POE_H__
|
||||
|
||||
/**
|
||||
* @file_name poe.h
|
||||
* @author Netlogic Microsystems
|
||||
* @brief Basic definitions of XLP Packet Order Engine
|
||||
*/
|
||||
|
||||
/* POE specific registers */
|
||||
#define POE_CL0_ENQ_SPILL_BASE_LO 0x0
|
||||
#define POE_CL1_ENQ_SPILL_BASE_LO 0x2
|
||||
#define POE_CL2_ENQ_SPILL_BASE_LO 0x4
|
||||
#define POE_CL3_ENQ_SPILL_BASE_LO 0x6
|
||||
#define POE_CL4_ENQ_SPILL_BASE_LO 0x8
|
||||
#define POE_CL5_ENQ_SPILL_BASE_LO 0xa
|
||||
#define POE_CL6_ENQ_SPILL_BASE_LO 0xc
|
||||
#define POE_CL7_ENQ_SPILL_BASE_LO 0xe
|
||||
#define POE_CL0_ENQ_SPILL_BASE_HI 0x1
|
||||
#define POE_CL1_ENQ_SPILL_BASE_HI 0x3
|
||||
#define POE_CL2_ENQ_SPILL_BASE_HI 0x5
|
||||
#define POE_CL3_ENQ_SPILL_BASE_HI 0x7
|
||||
#define POE_CL4_ENQ_SPILL_BASE_HI 0x9
|
||||
#define POE_CL5_ENQ_SPILL_BASE_HI 0xb
|
||||
#define POE_CL6_ENQ_SPILL_BASE_HI 0xd
|
||||
#define POE_CL7_ENQ_SPILL_BASE_HI 0xf
|
||||
#define POE_CL0_DEQ_SPILL_BASE_LO 0x10
|
||||
#define POE_CL1_DEQ_SPILL_BASE_LO 0x12
|
||||
#define POE_CL2_DEQ_SPILL_BASE_LO 0x14
|
||||
#define POE_CL3_DEQ_SPILL_BASE_LO 0x16
|
||||
#define POE_CL4_DEQ_SPILL_BASE_LO 0x18
|
||||
#define POE_CL5_DEQ_SPILL_BASE_LO 0x1a
|
||||
#define POE_CL6_DEQ_SPILL_BASE_LO 0x1c
|
||||
#define POE_CL7_DEQ_SPILL_BASE_LO 0x1e
|
||||
#define POE_CL0_DEQ_SPILL_BASE_HI 0x11
|
||||
#define POE_CL1_DEQ_SPILL_BASE_HI 0x13
|
||||
#define POE_CL2_DEQ_SPILL_BASE_HI 0x15
|
||||
#define POE_CL3_DEQ_SPILL_BASE_HI 0x17
|
||||
#define POE_CL4_DEQ_SPILL_BASE_HI 0x19
|
||||
#define POE_CL5_DEQ_SPILL_BASE_HI 0x1b
|
||||
#define POE_CL6_DEQ_SPILL_BASE_HI 0x1d
|
||||
#define POE_CL7_DEQ_SPILL_BASE_HI 0x1f
|
||||
#define POE_MSG_STORAGE_BASE_ADDR_LO 0x20
|
||||
#define POE_MSG_STORAGE_BASE_ADDR_HI 0x21
|
||||
#define POE_FBP_BASE_ADDR_LO 0x22
|
||||
#define POE_FBP_BASE_ADDR_HI 0x23
|
||||
#define POE_CL0_ENQ_SPILL_MAXLINE_LO 0x24
|
||||
#define POE_CL1_ENQ_SPILL_MAXLINE_LO 0x25
|
||||
#define POE_CL2_ENQ_SPILL_MAXLINE_LO 0x26
|
||||
#define POE_CL3_ENQ_SPILL_MAXLINE_LO 0x27
|
||||
#define POE_CL4_ENQ_SPILL_MAXLINE_LO 0x28
|
||||
#define POE_CL5_ENQ_SPILL_MAXLINE_LO 0x29
|
||||
#define POE_CL6_ENQ_SPILL_MAXLINE_LO 0x2a
|
||||
#define POE_CL7_ENQ_SPILL_MAXLINE_LO 0x2b
|
||||
#define POE_CL0_ENQ_SPILL_MAXLINE_HI 0x2c
|
||||
#define POE_CL1_ENQ_SPILL_MAXLINE_HI 0x2d
|
||||
#define POE_CL2_ENQ_SPILL_MAXLINE_HI 0x2e
|
||||
#define POE_CL3_ENQ_SPILL_MAXLINE_HI 0x2f
|
||||
#define POE_CL4_ENQ_SPILL_MAXLINE_HI 0x30
|
||||
#define POE_CL5_ENQ_SPILL_MAXLINE_HI 0x31
|
||||
#define POE_CL6_ENQ_SPILL_MAXLINE_HI 0x32
|
||||
#define POE_CL7_ENQ_SPILL_MAXLINE_HI 0x33
|
||||
#define POE_MAX_FLOW_MSG0 0x40
|
||||
#define POE_MAX_FLOW_MSG1 0x41
|
||||
#define POE_MAX_FLOW_MSG2 0x42
|
||||
#define POE_MAX_FLOW_MSG3 0x43
|
||||
#define POE_MAX_FLOW_MSG4 0x44
|
||||
#define POE_MAX_FLOW_MSG5 0x45
|
||||
#define POE_MAX_FLOW_MSG6 0x46
|
||||
#define POE_MAX_FLOW_MSG7 0x47
|
||||
#define POE_MAX_MSG_CL0 0x48
|
||||
#define POE_MAX_MSG_CL1 0x49
|
||||
#define POE_MAX_MSG_CL2 0x4a
|
||||
#define POE_MAX_MSG_CL3 0x4b
|
||||
#define POE_MAX_MSG_CL4 0x4c
|
||||
#define POE_MAX_MSG_CL5 0x4d
|
||||
#define POE_MAX_MSG_CL6 0x4e
|
||||
#define POE_MAX_MSG_CL7 0x4f
|
||||
#define POE_MAX_LOC_BUF_STG_CL0 0x50
|
||||
#define POE_MAX_LOC_BUF_STG_CL1 0x51
|
||||
#define POE_MAX_LOC_BUF_STG_CL2 0x52
|
||||
#define POE_MAX_LOC_BUF_STG_CL3 0x53
|
||||
#define POE_MAX_LOC_BUF_STG_CL4 0x54
|
||||
#define POE_MAX_LOC_BUF_STG_CL5 0x55
|
||||
#define POE_MAX_LOC_BUF_STG_CL6 0x56
|
||||
#define POE_MAX_LOC_BUF_STG_CL7 0x57
|
||||
#define POE_ENQ_MSG_COUNT0_SIZE 0x58
|
||||
#define POE_ENQ_MSG_COUNT1_SIZE 0x59
|
||||
#define POE_ENQ_MSG_COUNT2_SIZE 0x5a
|
||||
#define POE_ENQ_MSG_COUNT3_SIZE 0x5b
|
||||
#define POE_ENQ_MSG_COUNT4_SIZE 0x5c
|
||||
#define POE_ENQ_MSG_COUNT5_SIZE 0x5d
|
||||
#define POE_ENQ_MSG_COUNT6_SIZE 0x5e
|
||||
#define POE_ENQ_MSG_COUNT7_SIZE 0x5f
|
||||
#define POE_ERR_MSG_DESCRIP_LO0 0x60
|
||||
#define POE_ERR_MSG_DESCRIP_LO1 0x62
|
||||
#define POE_ERR_MSG_DESCRIP_LO2 0x64
|
||||
#define POE_ERR_MSG_DESCRIP_LO3 0x66
|
||||
#define POE_ERR_MSG_DESCRIP_HI0 0x61
|
||||
#define POE_ERR_MSG_DESCRIP_HI1 0x63
|
||||
#define POE_ERR_MSG_DESCRIP_HI2 0x65
|
||||
#define POE_ERR_MSG_DESCRIP_HI3 0x67
|
||||
#define POE_OOO_MSG_CNT_LO 0x68
|
||||
#define POE_IN_ORDER_MSG_CNT_LO 0x69
|
||||
#define POE_LOC_BUF_STOR_CNT_LO 0x6a
|
||||
#define POE_EXT_BUF_STOR_CNT_LO 0x6b
|
||||
#define POE_LOC_BUF_ALLOC_CNT_LO 0x6c
|
||||
#define POE_EXT_BUF_ALLOC_CNT_LO 0x6d
|
||||
#define POE_OOO_MSG_CNT_HI 0x6e
|
||||
#define POE_IN_ORDER_MSG_CNT_HI 0x6f
|
||||
#define POE_LOC_BUF_STOR_CNT_HI 0x70
|
||||
#define POE_EXT_BUF_STOR_CNT_HI 0x71
|
||||
#define POE_LOC_BUF_ALLOC_CNT_HI 0x72
|
||||
#define POE_EXT_BUF_ALLOC_CNT_HI 0x73
|
||||
#define POE_MODE_ERR_FLOW_ID 0x74
|
||||
#define POE_STATISTICS_ENABLE 0x75
|
||||
#define POE_MAX_SIZE_FLOW 0x76
|
||||
#define POE_MAX_SIZE 0x77
|
||||
#define POE_FBP_SP 0x78
|
||||
#define POE_FBP_SP_EN 0x79
|
||||
#define POE_LOC_ALLOC_EN 0x7a
|
||||
#define POE_EXT_ALLOC_EN 0x7b
|
||||
#define POE_DISTR_0_DROP_CNT 0xc0
|
||||
#define POE_DISTR_1_DROP_CNT 0xc1
|
||||
#define POE_DISTR_2_DROP_CNT 0xc2
|
||||
#define POE_DISTR_3_DROP_CNT 0xc3
|
||||
#define POE_DISTR_4_DROP_CNT 0xc4
|
||||
#define POE_DISTR_5_DROP_CNT 0xc5
|
||||
#define POE_DISTR_6_DROP_CNT 0xc6
|
||||
#define POE_DISTR_7_DROP_CNT 0xc7
|
||||
#define POE_DISTR_8_DROP_CNT 0xc8
|
||||
#define POE_DISTR_9_DROP_CNT 0xc9
|
||||
#define POE_DISTR_10_DROP_CNT 0xca
|
||||
#define POE_DISTR_11_DROP_CNT 0xcb
|
||||
#define POE_DISTR_12_DROP_CNT 0xcc
|
||||
#define POE_DISTR_13_DROP_CNT 0xcd
|
||||
#define POE_DISTR_14_DROP_CNT 0xce
|
||||
#define POE_DISTR_15_DROP_CNT 0xcf
|
||||
#define POE_CLASS_0_DROP_CNT 0xd0
|
||||
#define POE_CLASS_1_DROP_CNT 0xd1
|
||||
#define POE_CLASS_2_DROP_CNT 0xd2
|
||||
#define POE_CLASS_3_DROP_CNT 0xd3
|
||||
#define POE_CLASS_4_DROP_CNT 0xd4
|
||||
#define POE_CLASS_5_DROP_CNT 0xd5
|
||||
#define POE_CLASS_6_DROP_CNT 0xd6
|
||||
#define POE_CLASS_7_DROP_CNT 0xd7
|
||||
#define POE_DISTR_C0_DROP_CNT 0xd8
|
||||
#define POE_DISTR_C1_DROP_CNT 0xd9
|
||||
#define POE_DISTR_C2_DROP_CNT 0xda
|
||||
#define POE_DISTR_C3_DROP_CNT 0xdb
|
||||
#define POE_DISTR_C4_DROP_CNT 0xdc
|
||||
#define POE_DISTR_C5_DROP_CNT 0xdd
|
||||
#define POE_DISTR_C6_DROP_CNT 0xde
|
||||
#define POE_DISTR_C7_DROP_CNT 0xdf
|
||||
#define POE_CPU_DROP_CNT 0xe0
|
||||
#define POE_MAX_FLOW_DROP_CNT 0xe1
|
||||
#define POE_INTERRUPT_VEC 0x140
|
||||
#define POE_INTERRUPT_MASK 0x141
|
||||
#define POE_FATALERR_MASK 0x142
|
||||
#define POE_IDI_CFG 0x143
|
||||
#define POE_TIMEOUT_VALUE 0x144
|
||||
#define POE_CACHE_ALLOC_EN 0x145
|
||||
#define POE_FBP_ECC_ERR_CNT 0x146
|
||||
#define POE_MSG_STRG_ECC_ERR_CNT 0x147
|
||||
#define POE_FID_INFO_ECC_ERR_CNT 0x148
|
||||
#define POE_MSG_INFO_ECC_ERR_CNT 0x149
|
||||
#define POE_LL_ECC_ERR_CNT 0x14a
|
||||
#define POE_SIZE_ECC_ERR_CNT 0x14b
|
||||
#define POE_FMN_TXCR_ECC_ERR_CNT 0x14c
|
||||
#define POE_ENQ_INSPIL_ECC_ERR_CNT 0x14d
|
||||
#define POE_ENQ_OUTSPIL_ECC_ERR_CNT 0x14e
|
||||
#define POE_DEQ_OUTSPIL_ECC_ERR_CNT 0x14f
|
||||
#define POE_ENQ_MSG_SENT 0x150
|
||||
#define POE_ENQ_MSG_CNT 0x151
|
||||
#define POE_FID_RDATA 0x152
|
||||
#define POE_FID_WDATA 0x153
|
||||
#define POE_FID_CMD 0x154
|
||||
#define POE_FID_ADDR 0x155
|
||||
#define POE_MSG_INFO_CMD 0x156
|
||||
#define POE_MSG_INFO_ADDR 0x157
|
||||
#define POE_MSG_INFO_RDATA 0x158
|
||||
#define POE_LL_CMD 0x159
|
||||
#define POE_LL_ADDR 0x15a
|
||||
#define POE_LL_RDATA 0x15b
|
||||
#define POE_MSG_STG_CMD 0x15c
|
||||
#define POE_MSG_STG_ADDR 0x15d
|
||||
#define POE_MSG_STG_RDATA 0x15e
|
||||
#define POE_DISTR_THRESHOLD_0 0x1c0
|
||||
#define POE_DISTR_THRESHOLD_1 0x1c1
|
||||
#define POE_DISTR_THRESHOLD_2 0x1c2
|
||||
#define POE_DISTR_THRESHOLD_3 0x1c3
|
||||
#define POE_DISTR_THRESHOLD_4 0x1c4
|
||||
#define POE_DISTR_THRESHOLD(i) (0x1c0 + (i))
|
||||
#define POE_DISTR_EN 0x1c5
|
||||
#define POE_ENQ_SPILL_THOLD 0x1c8
|
||||
#define POE_DEQ_SPILL_THOLD 0x1c9
|
||||
#define POE_DEQ_SPILL_TIMER 0x1ca
|
||||
#define POE_DISTR_CLASS_DROP_EN 0x1cb
|
||||
#define POE_DISTR_VEC_DROP_EN 0x1cc
|
||||
#define POE_DISTR_DROP_TIMER 0x1cd
|
||||
#define POE_ERROR_LOG_W0 0x1ce
|
||||
#define POE_ERROR_LOG_W1 0x1cf
|
||||
#define POE_ERROR_LOG_W2 0x1d0
|
||||
#define POE_ERR_INJ_CTRL0 0x1d1
|
||||
#define POE_TX_TIMER 0x1d4
|
||||
|
||||
#define NUM_DIST_VEC 16
|
||||
#define NUM_WORDS_PER_DV 16
|
||||
#define MAX_DV_TBL_ENTRIES (NUM_DIST_VEC * NUM_WORDS_PER_DV)
|
||||
#define POE_DIST_THRESHOLD_VAL 0xa
|
||||
|
||||
/*
|
||||
* POE distribution vectors
|
||||
*
|
||||
* Each vector is 512 bit with msb indicating vc 512 and lsb indicating vc 0
|
||||
* 512-bit-vector is specified as 16 32-bit words.
|
||||
* Left most word has the vc range 511-479 right most word has vc range 31 - 0
|
||||
* Each word has the MSB select higer vc number and LSB select lower vc num
|
||||
*/
|
||||
#define POE_DISTVECT_BASE 0x100
|
||||
#define POE_DISTVECT(vec) (POE_DISTVECT_BASE + 16 * (vec))
|
||||
#define POE_DISTVECT_OFFSET(node,cpu) (4 * (3 - (node)) + (3 - (cpu)/8))
|
||||
#define POE_DISTVECT_SHIFT(node,cpu) (((cpu) % 8 ) * 4)
|
||||
|
||||
#if !defined(LOCORE) && !defined(__ASSEMBLY__)
|
||||
|
||||
#define nlm_read_poe_reg(b, r) nlm_read_reg(b, r)
|
||||
#define nlm_write_poe_reg(b, r, v) nlm_write_reg(b, r, v)
|
||||
#define nlm_read_poedv_reg(b, r) nlm_read_reg_xkphys(b, r)
|
||||
#define nlm_write_poedv_reg(b, r, v) nlm_write_reg_xkphys(b, r, v)
|
||||
#define nlm_get_poe_pcibase(node) \
|
||||
nlm_pcicfg_base(XLP_IO_POE_OFFSET(node))
|
||||
#define nlm_get_poe_regbase(node) \
|
||||
(nlm_get_poe_pcibase(node) + XLP_IO_PCI_HDRSZ)
|
||||
#define nlm_get_poedv_regbase(node) \
|
||||
nlm_xkphys_map_pcibar0(nlm_get_poe_pcibase(node))
|
||||
|
||||
static __inline int
|
||||
nlm_poe_max_flows(uint64_t poe_pcibase)
|
||||
{
|
||||
return (nlm_read_reg(poe_pcibase, XLP_PCI_DEVINFO_REG0));
|
||||
}
|
||||
|
||||
/*
|
||||
* Helper function, calculate the distribution vector
|
||||
* cm0, cm1, cm2, cm3 : CPU masks for nodes 0..3
|
||||
* thr_vcmask: destination VCs for a thread
|
||||
*/
|
||||
static __inline void
|
||||
nlm_calc_poe_distvec(uint32_t cm0, uint32_t cm1, uint32_t cm2, uint32_t cm3,
|
||||
uint32_t thr_vcmask, uint32_t *distvec)
|
||||
{
|
||||
uint32_t cpumask = 0, val;
|
||||
int i, cpu, node, startcpu, index;
|
||||
|
||||
thr_vcmask &= 0xf;
|
||||
for (node = 0; node < XLP_MAX_NODES; node++) {
|
||||
switch (node) {
|
||||
case 0: cpumask = cm0; break;
|
||||
case 1: cpumask = cm1; break;
|
||||
case 2: cpumask = cm2; break;
|
||||
case 3: cpumask = cm3; break;
|
||||
}
|
||||
|
||||
for (i = 0; i < 4; i++) {
|
||||
val = 0;
|
||||
startcpu = 31 - i * 8;
|
||||
for (cpu = startcpu; cpu >= startcpu - 7; cpu--) {
|
||||
val <<= 4;
|
||||
if (cpumask & (1U << cpu))
|
||||
val |= thr_vcmask;
|
||||
}
|
||||
index = POE_DISTVECT_OFFSET(node, startcpu);
|
||||
distvec[index] = val;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
static __inline int
|
||||
nlm_write_poe_distvec(uint64_t poedv_base, int vec, uint32_t *distvec)
|
||||
{
|
||||
uint32_t reg;
|
||||
int i;
|
||||
|
||||
if (vec < 0 || vec >= NUM_DIST_VEC)
|
||||
return (-1);
|
||||
|
||||
for (i = 0; i < NUM_WORDS_PER_DV; i++) {
|
||||
reg = POE_DISTVECT(vec) + i;
|
||||
nlm_write_poedv_reg(poedv_base, reg, distvec[i]);
|
||||
}
|
||||
|
||||
return (0);
|
||||
}
|
||||
|
||||
static __inline void
|
||||
nlm_config_poe(uint64_t poe_base, uint64_t poedv_base)
|
||||
{
|
||||
uint32_t zerodv[NUM_WORDS_PER_DV];
|
||||
int i;
|
||||
|
||||
/* First disable distribution vector logic */
|
||||
nlm_write_poe_reg(poe_base, POE_DISTR_EN, 0);
|
||||
|
||||
memset(zerodv, 0, sizeof(zerodv));
|
||||
for (i = 0; i < NUM_DIST_VEC; i++)
|
||||
nlm_write_poe_distvec(poedv_base, i, zerodv);
|
||||
|
||||
/* set the threshold */
|
||||
for (i = 0; i < 5; i++)
|
||||
nlm_write_poe_reg(poe_base, POE_DISTR_THRESHOLD(i),
|
||||
POE_DIST_THRESHOLD_VAL);
|
||||
|
||||
nlm_write_poe_reg(poe_base, POE_DISTR_EN, 1);
|
||||
|
||||
/* always enable local message store */
|
||||
nlm_write_poe_reg(poe_base, POE_LOC_ALLOC_EN, 1);
|
||||
|
||||
nlm_write_poe_reg(poe_base, POE_TX_TIMER, 0x3);
|
||||
}
|
||||
#endif /* !(LOCORE) && !(__ASSEMBLY__) */
|
||||
#endif
|
||||
217
sys/mips/nlm/hal/sgmii.h
Normal file
217
sys/mips/nlm/hal/sgmii.h
Normal file
|
|
@ -0,0 +1,217 @@
|
|||
/*-
|
||||
* Copyright (c) 2003-2012 Broadcom Corporation
|
||||
* All Rights Reserved
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY BROADCOM ``AS IS'' AND ANY EXPRESS OR
|
||||
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
* ARE DISCLAIMED. IN NO EVENT SHALL BROADCOM OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
|
||||
* BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
|
||||
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
|
||||
* OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
|
||||
* IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
* $FreeBSD$
|
||||
*/
|
||||
|
||||
#ifndef __NLM_SGMII_H__
|
||||
#define __NLM_SGMII_H__
|
||||
|
||||
/**
|
||||
* @file_name sgmii.h
|
||||
* @author Netlogic Microsystems
|
||||
* @brief Basic definitions of XLP SGMII ports
|
||||
*/
|
||||
|
||||
#define SGMII_MAC_CONF1(block, i) NAE_REG(block, i, 0x00)
|
||||
#define SGMII_MAC_CONF2(block, i) NAE_REG(block, i, 0x01)
|
||||
#define SGMII_IPG_IFG(block, i) NAE_REG(block, i, 0x02)
|
||||
#define SGMII_HLF_DUP(block, i) NAE_REG(block, i, 0x03)
|
||||
#define SGMII_MAX_FRAME(block, i) NAE_REG(block, i, 0x04)
|
||||
#define SGMII_TEST(block, i) NAE_REG(block, i, 0x07)
|
||||
#define SGMII_MIIM_CONF(block, i) NAE_REG(block, i, 0x08)
|
||||
#define SGMII_MIIM_CMD(block, i) NAE_REG(block, i, 0x09)
|
||||
#define SGMII_MIIM_ADDR(block, i) NAE_REG(block, i, 0x0a)
|
||||
#define SGMII_MIIM_CTRL(block, i) NAE_REG(block, i, 0x0b)
|
||||
#define SGMII_MIIM_STAT(block, i) NAE_REG(block, i, 0x0c)
|
||||
#define SGMII_MIIM_IND(block, i) NAE_REG(block, i, 0x0d)
|
||||
#define SGMII_IO_CTRL(block, i) NAE_REG(block, i, 0x0e)
|
||||
#define SGMII_IO_STAT(block, i) NAE_REG(block, i, 0x0f)
|
||||
#define SGMII_STATS_MLR(block, i) NAE_REG(block, i, 0x1f)
|
||||
#define SGMII_STATS_TR64(block, i) NAE_REG(block, i, 0x20)
|
||||
#define SGMII_STATS_TR127(block, i) NAE_REG(block, i, 0x21)
|
||||
#define SGMII_STATS_TR255(block, i) NAE_REG(block, i, 0x22)
|
||||
#define SGMII_STATS_TR511(block, i) NAE_REG(block, i, 0x23)
|
||||
#define SGMII_STATS_TR1K(block, i) NAE_REG(block, i, 0x24)
|
||||
#define SGMII_STATS_TRMAX(block, i) NAE_REG(block, i, 0x25)
|
||||
#define SGMII_STATS_TRMGV(block, i) NAE_REG(block, i, 0x26)
|
||||
#define SGMII_STATS_RBYT(block, i) NAE_REG(block, i, 0x27)
|
||||
#define SGMII_STATS_RPKT(block, i) NAE_REG(block, i, 0x28)
|
||||
#define SGMII_STATS_RFCS(block, i) NAE_REG(block, i, 0x29)
|
||||
#define SGMII_STATS_RMCA(block, i) NAE_REG(block, i, 0x2a)
|
||||
#define SGMII_STATS_RBCA(block, i) NAE_REG(block, i, 0x2b)
|
||||
#define SGMII_STATS_RXCF(block, i) NAE_REG(block, i, 0x2c)
|
||||
#define SGMII_STATS_RXPF(block, i) NAE_REG(block, i, 0x2d)
|
||||
#define SGMII_STATS_RXUO(block, i) NAE_REG(block, i, 0x2e)
|
||||
#define SGMII_STATS_RALN(block, i) NAE_REG(block, i, 0x2f)
|
||||
#define SGMII_STATS_RFLR(block, i) NAE_REG(block, i, 0x30)
|
||||
#define SGMII_STATS_RCDE(block, i) NAE_REG(block, i, 0x31)
|
||||
#define SGMII_STATS_RCSE(block, i) NAE_REG(block, i, 0x32)
|
||||
#define SGMII_STATS_RUND(block, i) NAE_REG(block, i, 0x33)
|
||||
#define SGMII_STATS_ROVR(block, i) NAE_REG(block, i, 0x34)
|
||||
#define SGMII_STATS_RFRG(block, i) NAE_REG(block, i, 0x35)
|
||||
#define SGMII_STATS_RJBR(block, i) NAE_REG(block, i, 0x36)
|
||||
#define SGMII_STATS_TBYT(block, i) NAE_REG(block, i, 0x38)
|
||||
#define SGMII_STATS_TPKT(block, i) NAE_REG(block, i, 0x39)
|
||||
#define SGMII_STATS_TMCA(block, i) NAE_REG(block, i, 0x3a)
|
||||
#define SGMII_STATS_TBCA(block, i) NAE_REG(block, i, 0x3b)
|
||||
#define SGMII_STATS_TXPF(block, i) NAE_REG(block, i, 0x3c)
|
||||
#define SGMII_STATS_TDFR(block, i) NAE_REG(block, i, 0x3d)
|
||||
#define SGMII_STATS_TEDF(block, i) NAE_REG(block, i, 0x3e)
|
||||
#define SGMII_STATS_TSCL(block, i) NAE_REG(block, i, 0x3f)
|
||||
#define SGMII_STATS_TMCL(block, i) NAE_REG(block, i, 0x40)
|
||||
#define SGMII_STATS_TLCL(block, i) NAE_REG(block, i, 0x41)
|
||||
#define SGMII_STATS_TXCL(block, i) NAE_REG(block, i, 0x42)
|
||||
#define SGMII_STATS_TNCL(block, i) NAE_REG(block, i, 0x43)
|
||||
#define SGMII_STATS_TJBR(block, i) NAE_REG(block, i, 0x46)
|
||||
#define SGMII_STATS_TFCS(block, i) NAE_REG(block, i, 0x47)
|
||||
#define SGMII_STATS_TXCF(block, i) NAE_REG(block, i, 0x48)
|
||||
#define SGMII_STATS_TOVR(block, i) NAE_REG(block, i, 0x49)
|
||||
#define SGMII_STATS_TUND(block, i) NAE_REG(block, i, 0x4a)
|
||||
#define SGMII_STATS_TFRG(block, i) NAE_REG(block, i, 0x4b)
|
||||
#define SGMII_STATS_CAR1(block, i) NAE_REG(block, i, 0x4c)
|
||||
#define SGMII_STATS_CAR2(block, i) NAE_REG(block, i, 0x4d)
|
||||
#define SGMII_STATS_CAM1(block, i) NAE_REG(block, i, 0x4e)
|
||||
#define SGMII_STATS_CAM2(block, i) NAE_REG(block, i, 0x4f)
|
||||
#define SGMII_MAC_ADDR0_LO(block, i) NAE_REG(block, i, 0x50)
|
||||
#define SGMII_MAC_ADDR0_HI(block, i) NAE_REG(block, i, 0x51)
|
||||
#define SGMII_MAC_ADDR1_LO(block, i) NAE_REG(block, i, 0x52)
|
||||
#define SGMII_MAC_ADDR1_HI(block, i) NAE_REG(block, i, 0x53)
|
||||
#define SGMII_MAC_ADDR2_LO(block, i) NAE_REG(block, i, 0x54)
|
||||
#define SGMII_MAC_ADDR2_HI(block, i) NAE_REG(block, i, 0x55)
|
||||
#define SGMII_MAC_ADDR3_LO(block, i) NAE_REG(block, i, 0x56)
|
||||
#define SGMII_MAC_ADDR3_HI(block, i) NAE_REG(block, i, 0x57)
|
||||
#define SGMII_MAC_ADDR_MASK0_LO(block, i) NAE_REG(block, i, 0x58)
|
||||
#define SGMII_MAC_ADDR_MASK0_HI(block, i) NAE_REG(block, i, 0x59)
|
||||
#define SGMII_MAC_ADDR_MASK1_LO(block, i) NAE_REG(block, i, 0x5a)
|
||||
#define SGMII_MAC_ADDR_MASK1_HI(block, i) NAE_REG(block, i, 0x5b)
|
||||
#define SGMII_MAC_FILTER_CONFIG(block, i) NAE_REG(block, i, 0x5c)
|
||||
#define SGMII_HASHTBL_VEC_B31_0(block, i) NAE_REG(block, i, 0x60)
|
||||
#define SGMII_HASHTBL_VEC_B63_32(block, i) NAE_REG(block, i, 0x61)
|
||||
#define SGMII_HASHTBL_VEC_B95_64(block, i) NAE_REG(block, i, 0x62)
|
||||
#define SGMII_HASHTBL_VEC_B127_96(block, i) NAE_REG(block, i, 0x63)
|
||||
#define SGMII_HASHTBL_VEC_B159_128(block, i) NAE_REG(block, i, 0x64)
|
||||
#define SGMII_HASHTBL_VEC_B191_160(block, i) NAE_REG(block, i, 0x65)
|
||||
#define SGMII_HASHTBL_VEC_B223_192(block, i) NAE_REG(block, i, 0x66)
|
||||
#define SGMII_HASHTBL_VEC_B255_224(block, i) NAE_REG(block, i, 0x67)
|
||||
#define SGMII_HASHTBL_VEC_B287_256(block, i) NAE_REG(block, i, 0x68)
|
||||
#define SGMII_HASHTBL_VEC_B319_288(block, i) NAE_REG(block, i, 0x69)
|
||||
#define SGMII_HASHTBL_VEC_B351_320(block, i) NAE_REG(block, i, 0x6a)
|
||||
#define SGMII_HASHTBL_VEC_B383_352(block, i) NAE_REG(block, i, 0x6b)
|
||||
#define SGMII_HASHTBL_VEC_B415_384(block, i) NAE_REG(block, i, 0x6c)
|
||||
#define SGMII_HASHTBL_VEC_B447_416(block, i) NAE_REG(block, i, 0x6d)
|
||||
#define SGMII_HASHTBL_VEC_B479_448(block, i) NAE_REG(block, i, 0x6e)
|
||||
#define SGMII_HASHTBL_VEC_B511_480(block, i) NAE_REG(block, i, 0x6f)
|
||||
|
||||
#define SGMII_NETIOR_VLANTYPE_FILTER(block, i) NAE_REG(block, i, 0x76)
|
||||
#define SGMII_NETIOR_RXDROP_CNTR(block, i) NAE_REG(block, i, 0x77)
|
||||
#define SGMII_NETIOR_PAUSE_QUANTAMULT(block, i) NAE_REG(block, i, 0x78)
|
||||
#define SGMII_NETIOR_MAC_CTRL_OPCODE(block, i) NAE_REG(block, i, 0x79)
|
||||
#define SGMII_NETIOR_MAC_DA_H(block, i) NAE_REG(block, i, 0x7a)
|
||||
#define SGMII_NETIOR_MAC_DA_L(block, i) NAE_REG(block, i, 0x7b)
|
||||
#define SGMII_NET_IFACE_CTRL3(block, i) NAE_REG(block, i, 0x7c)
|
||||
#define SGMII_NETIOR_GMAC_STAT(block, i) NAE_REG(block, i, 0x7d)
|
||||
#define SGMII_NET_IFACE_CTRL2(block, i) NAE_REG(block, i, 0x7e)
|
||||
#define SGMII_NET_IFACE_CTRL(block, i) NAE_REG(block, i, 0x7f)
|
||||
|
||||
#if !defined(LOCORE) && !defined(__ASSEMBLY__)
|
||||
/* speed */
|
||||
enum nlm_sgmii_speed {
|
||||
NLM_SGMII_SPEED_10,
|
||||
NLM_SGMII_SPEED_100,
|
||||
NLM_SGMII_SPEED_1000,
|
||||
NLM_SGMII_SPEED_RSVD
|
||||
};
|
||||
|
||||
/* duplexity */
|
||||
enum nlm_sgmii_duplex_mode {
|
||||
NLM_SGMII_DUPLEX_AUTO,
|
||||
NLM_SGMII_DUPLEX_HALF,
|
||||
NLM_SGMII_DUPLEX_FULL
|
||||
};
|
||||
|
||||
/* stats */
|
||||
enum {
|
||||
nlm_sgmii_stats_mlr,
|
||||
nlm_sgmii_stats_tr64,
|
||||
nlm_sgmii_stats_tr127,
|
||||
nlm_sgmii_stats_tr255,
|
||||
nlm_sgmii_stats_tr511,
|
||||
nlm_sgmii_stats_tr1k,
|
||||
nlm_sgmii_stats_trmax,
|
||||
nlm_sgmii_stats_trmgv,
|
||||
nlm_sgmii_stats_rbyt,
|
||||
nlm_sgmii_stats_rpkt,
|
||||
nlm_sgmii_stats_rfcs,
|
||||
nlm_sgmii_stats_rmca,
|
||||
nlm_sgmii_stats_rbca,
|
||||
nlm_sgmii_stats_rxcf,
|
||||
nlm_sgmii_stats_rxpf,
|
||||
nlm_sgmii_stats_rxuo,
|
||||
nlm_sgmii_stats_raln,
|
||||
nlm_sgmii_stats_rflr,
|
||||
nlm_sgmii_stats_rcde,
|
||||
nlm_sgmii_stats_rcse,
|
||||
nlm_sgmii_stats_rund,
|
||||
nlm_sgmii_stats_rovr,
|
||||
nlm_sgmii_stats_rfrg,
|
||||
nlm_sgmii_stats_rjbr,
|
||||
nlm_sgmii_stats_rdummy, /* not used */
|
||||
nlm_sgmii_stats_tbyt,
|
||||
nlm_sgmii_stats_tpkt,
|
||||
nlm_sgmii_stats_tmca,
|
||||
nlm_sgmii_stats_tbca,
|
||||
nlm_sgmii_stats_txpf,
|
||||
nlm_sgmii_stats_tdfr,
|
||||
nlm_sgmii_stats_tedf,
|
||||
nlm_sgmii_stats_tscl,
|
||||
nlm_sgmii_stats_tmcl,
|
||||
nlm_sgmii_stats_tlcl,
|
||||
nlm_sgmii_stats_txcl,
|
||||
nlm_sgmii_stats_tncl,
|
||||
nlm_sgmii_stats_tjbr,
|
||||
nlm_sgmii_stats_tfcs,
|
||||
nlm_sgmii_stats_txcf,
|
||||
nlm_sgmii_stats_tovr,
|
||||
nlm_sgmii_stats_tund,
|
||||
nlm_sgmii_stats_tfrg,
|
||||
nlm_sgmii_stats_car1,
|
||||
nlm_sgmii_stats_car2,
|
||||
nlm_sgmii_stats_cam1,
|
||||
nlm_sgmii_stats_cam2
|
||||
};
|
||||
|
||||
void nlm_configure_sgmii_interface(uint64_t, int, int, int, int);
|
||||
void nlm_sgmii_pcs_init(uint64_t, uint32_t);
|
||||
void nlm_nae_setup_mac(uint64_t, int, int, int, int, int, int, int);
|
||||
void nlm_nae_setup_rx_mode_sgmii(uint64_t, int, int, int, int, int,
|
||||
int, int);
|
||||
void nlm_nae_setup_mac_addr_sgmii(uint64_t, int, int, int, uint8_t *);
|
||||
|
||||
#endif /* !(LOCORE) && !(__ASSEMBLY__) */
|
||||
|
||||
#endif
|
||||
141
sys/mips/nlm/hal/ucore_loader.h
Normal file
141
sys/mips/nlm/hal/ucore_loader.h
Normal file
|
|
@ -0,0 +1,141 @@
|
|||
/*-
|
||||
* Copyright (c) 2003-2012 Broadcom Corporation
|
||||
* All Rights Reserved
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY BROADCOM ``AS IS'' AND ANY EXPRESS OR
|
||||
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
* ARE DISCLAIMED. IN NO EVENT SHALL BROADCOM OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
|
||||
* BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
|
||||
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
|
||||
* OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
|
||||
* IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
* $FreeBSD$
|
||||
*/
|
||||
|
||||
#ifndef __NLM_UCORE_LOADER_H__
|
||||
#define __NLM_UCORE_LOADER_H__
|
||||
|
||||
/**
|
||||
* @file_name ucore_loader.h
|
||||
* @author Netlogic Microsystems
|
||||
* @brief Ucore loader API header
|
||||
*/
|
||||
|
||||
#define CODE_SIZE_PER_UCORE (4 << 10)
|
||||
|
||||
static __inline__ void
|
||||
nlm_ucore_load_image(uint64_t nae_base, int ucore)
|
||||
{
|
||||
uint64_t addr = nae_base + NAE_UCORE_SHARED_RAM_OFFSET +
|
||||
(ucore * CODE_SIZE_PER_UCORE);
|
||||
uint32_t *p = (uint32_t *)ucore_app_bin;
|
||||
int i, size;
|
||||
|
||||
size = sizeof(ucore_app_bin)/sizeof(uint32_t);
|
||||
for (i = 0; i < size; i++, addr += 4)
|
||||
nlm_store_word_daddr(addr, p[i]);
|
||||
|
||||
/* add a 'nop' if number of instructions are odd */
|
||||
if (size & 0x1)
|
||||
nlm_store_word_daddr(addr, 0x0);
|
||||
}
|
||||
|
||||
static __inline int
|
||||
nlm_ucore_write_sharedmem(uint64_t nae_base, int index, uint32_t data)
|
||||
{
|
||||
uint32_t ucore_cfg;
|
||||
uint64_t addr = nae_base + NAE_UCORE_SHARED_RAM_OFFSET;
|
||||
|
||||
if (index > 128)
|
||||
return (-1);
|
||||
|
||||
ucore_cfg = nlm_read_nae_reg(nae_base, NAE_RX_UCORE_CFG);
|
||||
/* set iram to zero */
|
||||
nlm_write_nae_reg(nae_base, NAE_RX_UCORE_CFG,
|
||||
(ucore_cfg & ~(0x1 << 7)));
|
||||
|
||||
nlm_store_word_daddr(addr + (index * 4), data);
|
||||
|
||||
/* restore ucore config */
|
||||
nlm_write_nae_reg(nae_base, NAE_RX_UCORE_CFG, ucore_cfg);
|
||||
return (0);
|
||||
}
|
||||
|
||||
static __inline uint32_t
|
||||
nlm_ucore_read_sharedmem(uint64_t nae_base, int index)
|
||||
{
|
||||
uint64_t addr = nae_base + NAE_UCORE_SHARED_RAM_OFFSET;
|
||||
uint32_t ucore_cfg, val;
|
||||
|
||||
ucore_cfg = nlm_read_nae_reg(nae_base, NAE_RX_UCORE_CFG);
|
||||
/* set iram to zero */
|
||||
nlm_write_nae_reg(nae_base, NAE_RX_UCORE_CFG,
|
||||
(ucore_cfg & ~(0x1 << 7)));
|
||||
|
||||
val = nlm_load_word_daddr(addr + (index * 4));
|
||||
|
||||
/* restore ucore config */
|
||||
nlm_write_nae_reg(nae_base, NAE_RX_UCORE_CFG, ucore_cfg);
|
||||
|
||||
return val;
|
||||
}
|
||||
|
||||
static __inline__ int
|
||||
nlm_ucore_load_all(uint64_t nae_base, uint32_t ucore_mask, int nae_reset_done)
|
||||
{
|
||||
int i, count = 0;
|
||||
uint32_t mask;
|
||||
uint32_t ucore_cfg = 0;
|
||||
|
||||
mask = ucore_mask & 0xffff;
|
||||
|
||||
/* Stop all ucores */
|
||||
if (nae_reset_done == 0) { /* Skip the Ucore reset if NAE reset is done */
|
||||
ucore_cfg = nlm_read_nae_reg(nae_base, NAE_RX_UCORE_CFG);
|
||||
nlm_write_nae_reg(nae_base, NAE_RX_UCORE_CFG,
|
||||
ucore_cfg | (1 << 24));
|
||||
|
||||
/* poll for ucore to get in to a wait state */
|
||||
do {
|
||||
ucore_cfg = nlm_read_nae_reg(nae_base,
|
||||
NAE_RX_UCORE_CFG);
|
||||
} while ((ucore_cfg & (1 << 25)) == 0);
|
||||
}
|
||||
|
||||
for (i = 0; i < sizeof(ucore_mask) * NBBY; i++) {
|
||||
if ((mask & (1 << i)) == 0)
|
||||
continue;
|
||||
nlm_ucore_load_image(nae_base, i);
|
||||
count++;
|
||||
}
|
||||
|
||||
/* Enable per-domain ucores */
|
||||
ucore_cfg = nlm_read_nae_reg(nae_base, NAE_RX_UCORE_CFG);
|
||||
|
||||
/* write one to reset bits to put the ucores in reset */
|
||||
ucore_cfg = ucore_cfg | (((mask) & 0xffff) << 8);
|
||||
nlm_write_nae_reg(nae_base, NAE_RX_UCORE_CFG, ucore_cfg);
|
||||
|
||||
/* write zero to reset bits to pull them out of reset */
|
||||
ucore_cfg = ucore_cfg & (~(((mask) & 0xffff) << 8)) & ~(1 << 24);
|
||||
nlm_write_nae_reg(nae_base, NAE_RX_UCORE_CFG, ucore_cfg);
|
||||
|
||||
return (count);
|
||||
}
|
||||
#endif
|
||||
193
sys/mips/nlm/hal/xaui.h
Normal file
193
sys/mips/nlm/hal/xaui.h
Normal file
|
|
@ -0,0 +1,193 @@
|
|||
/*-
|
||||
* Copyright (c) 2003-2012 Broadcom Corporation
|
||||
* All Rights Reserved
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY BROADCOM ``AS IS'' AND ANY EXPRESS OR
|
||||
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
* ARE DISCLAIMED. IN NO EVENT SHALL BROADCOM OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
|
||||
* BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
|
||||
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
|
||||
* OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
|
||||
* IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
* $FreeBSD$
|
||||
*/
|
||||
#ifndef __NLM_XAUI_H__
|
||||
#define __NLM_XAUI_H__
|
||||
|
||||
/**
|
||||
* @file_name xaui.h
|
||||
* @author Netlogic Microsystems
|
||||
* @brief Basic definitions of XLP XAUI ports
|
||||
*/
|
||||
#define XAUI_CONFIG0(block) NAE_REG(block, 4, 0x00)
|
||||
#define XAUI_CONFIG1(block) NAE_REG(block, 4, 0x01)
|
||||
#define XAUI_CONFIG2(block) NAE_REG(block, 4, 0x02)
|
||||
#define XAUI_CONFIG3(block) NAE_REG(block, 4, 0x03)
|
||||
/*
|
||||
#define XAUI_MAC_ADDR0_LO(block) NAE_REG(block, 4, 0x04)
|
||||
#define XAUI_MAC_ADDR0_HI(block) NAE_REG(block, 4, 0x05)
|
||||
*/
|
||||
#define XAUI_MAX_FRAME_LEN(block) NAE_REG(block, 4, 0x08)
|
||||
#define XAUI_REVISION_LVL(block) NAE_REG(block, 4, 0x0b)
|
||||
#define XAUI_MII_MGMT_CMD(block) NAE_REG(block, 4, 0x10)
|
||||
#define XAUI_MII_MGMT_FIELD(block) NAE_REG(block, 4, 0x11)
|
||||
#define XAUI_MII_MGMT_CFG(block) NAE_REG(block, 4, 0x12)
|
||||
#define XAUI_MIIM_LINK_FALL_VEC(block) NAE_REG(block, 4, 0x13)
|
||||
#define XAUI_MII_MGMT_IND(block) NAE_REG(block, 4, 0x14)
|
||||
#define XAUI_STATS_MLR(block) NAE_REG(block, 4, 0x1f)
|
||||
#define XAUI_STATS_TR64(block) NAE_REG(block, 4, 0x20)
|
||||
#define XAUI_STATS_TR127(block) NAE_REG(block, 4, 0x21)
|
||||
#define XAUI_STATS_TR255(block) NAE_REG(block, 4, 0x22)
|
||||
#define XAUI_STATS_TR511(block) NAE_REG(block, 4, 0x23)
|
||||
#define XAUI_STATS_TR1K(block) NAE_REG(block, 4, 0x24)
|
||||
#define XAUI_STATS_TRMAX(block) NAE_REG(block, 4, 0x25)
|
||||
#define XAUI_STATS_TRMGV(block) NAE_REG(block, 4, 0x26)
|
||||
#define XAUI_STATS_RBYT(block) NAE_REG(block, 4, 0x27)
|
||||
#define XAUI_STATS_RPKT(block) NAE_REG(block, 4, 0x28)
|
||||
#define XAUI_STATS_RFCS(block) NAE_REG(block, 4, 0x29)
|
||||
#define XAUI_STATS_RMCA(block) NAE_REG(block, 4, 0x2a)
|
||||
#define XAUI_STATS_RBCA(block) NAE_REG(block, 4, 0x2b)
|
||||
#define XAUI_STATS_RXCF(block) NAE_REG(block, 4, 0x2c)
|
||||
#define XAUI_STATS_RXPF(block) NAE_REG(block, 4, 0x2d)
|
||||
#define XAUI_STATS_RXUO(block) NAE_REG(block, 4, 0x2e)
|
||||
#define XAUI_STATS_RALN(block) NAE_REG(block, 4, 0x2f)
|
||||
#define XAUI_STATS_RFLR(block) NAE_REG(block, 4, 0x30)
|
||||
#define XAUI_STATS_RCDE(block) NAE_REG(block, 4, 0x31)
|
||||
#define XAUI_STATS_RCSE(block) NAE_REG(block, 4, 0x32)
|
||||
#define XAUI_STATS_RUND(block) NAE_REG(block, 4, 0x33)
|
||||
#define XAUI_STATS_ROVR(block) NAE_REG(block, 4, 0x34)
|
||||
#define XAUI_STATS_RFRG(block) NAE_REG(block, 4, 0x35)
|
||||
#define XAUI_STATS_RJBR(block) NAE_REG(block, 4, 0x36)
|
||||
#define XAUI_STATS_TBYT(block) NAE_REG(block, 4, 0x38)
|
||||
#define XAUI_STATS_TPKT(block) NAE_REG(block, 4, 0x39)
|
||||
#define XAUI_STATS_TMCA(block) NAE_REG(block, 4, 0x3a)
|
||||
#define XAUI_STATS_TBCA(block) NAE_REG(block, 4, 0x3b)
|
||||
#define XAUI_STATS_TXPF(block) NAE_REG(block, 4, 0x3c)
|
||||
#define XAUI_STATS_TDFR(block) NAE_REG(block, 4, 0x3d)
|
||||
#define XAUI_STATS_TEDF(block) NAE_REG(block, 4, 0x3e)
|
||||
#define XAUI_STATS_TSCL(block) NAE_REG(block, 4, 0x3f)
|
||||
#define XAUI_STATS_TMCL(block) NAE_REG(block, 4, 0x40)
|
||||
#define XAUI_STATS_TLCL(block) NAE_REG(block, 4, 0x41)
|
||||
#define XAUI_STATS_TXCL(block) NAE_REG(block, 4, 0x42)
|
||||
#define XAUI_STATS_TNCL(block) NAE_REG(block, 4, 0x43)
|
||||
#define XAUI_STATS_TJBR(block) NAE_REG(block, 4, 0x46)
|
||||
#define XAUI_STATS_TFCS(block) NAE_REG(block, 4, 0x47)
|
||||
#define XAUI_STATS_TXCF(block) NAE_REG(block, 4, 0x48)
|
||||
#define XAUI_STATS_TOVR(block) NAE_REG(block, 4, 0x49)
|
||||
#define XAUI_STATS_TUND(block) NAE_REG(block, 4, 0x4a)
|
||||
#define XAUI_STATS_TFRG(block) NAE_REG(block, 4, 0x4b)
|
||||
#define XAUI_STATS_CAR1(block) NAE_REG(block, 4, 0x4c)
|
||||
#define XAUI_STATS_CAR2(block) NAE_REG(block, 4, 0x4d)
|
||||
#define XAUI_STATS_CAM1(block) NAE_REG(block, 4, 0x4e)
|
||||
#define XAUI_STATS_CAM2(block) NAE_REG(block, 4, 0x4f)
|
||||
#define XAUI_MAC_ADDR0_LO(block) NAE_REG(block, 4, 0x50)
|
||||
#define XAUI_MAC_ADDR0_HI(block) NAE_REG(block, 4, 0x51)
|
||||
#define XAUI_MAC_ADDR1_LO(block) NAE_REG(block, 4, 0x52)
|
||||
#define XAUI_MAC_ADDR1_HI(block) NAE_REG(block, 4, 0x53)
|
||||
#define XAUI_MAC_ADDR2_LO(block) NAE_REG(block, 4, 0x54)
|
||||
#define XAUI_MAC_ADDR2_HI(block) NAE_REG(block, 4, 0x55)
|
||||
#define XAUI_MAC_ADDR3_LO(block) NAE_REG(block, 4, 0x56)
|
||||
#define XAUI_MAC_ADDR3_HI(block) NAE_REG(block, 4, 0x57)
|
||||
#define XAUI_MAC_ADDR_MASK0_LO(block) NAE_REG(block, 4, 0x58)
|
||||
#define XAUI_MAC_ADDR_MASK0_HI(block) NAE_REG(block, 4, 0x59)
|
||||
#define XAUI_MAC_ADDR_MASK1_LO(block) NAE_REG(block, 4, 0x5a)
|
||||
#define XAUI_MAC_ADDR_MASK1_HI(block) NAE_REG(block, 4, 0x5b)
|
||||
#define XAUI_MAC_FILTER_CFG(block) NAE_REG(block, 4, 0x5c)
|
||||
#define XAUI_HASHTBL_VEC_B31_0(block) NAE_REG(block, 4, 0x60)
|
||||
#define XAUI_HASHTBL_VEC_B63_32(block) NAE_REG(block, 4, 0x61)
|
||||
#define XAUI_HASHTBL_VEC_B95_64(block) NAE_REG(block, 4, 0x62)
|
||||
#define XAUI_HASHTBL_VEC_B127_96(block) NAE_REG(block, 4, 0x63)
|
||||
#define XAUI_HASHTBL_VEC_B159_128(block) NAE_REG(block, 4, 0x64)
|
||||
#define XAUI_HASHTBL_VEC_B191_160(block) NAE_REG(block, 4, 0x65)
|
||||
#define XAUI_HASHTBL_VEC_B223_192(block) NAE_REG(block, 4, 0x66)
|
||||
#define XAUI_HASHTBL_VEC_B255_224(block) NAE_REG(block, 4, 0x67)
|
||||
#define XAUI_HASHTBL_VEC_B287_256(block) NAE_REG(block, 4, 0x68)
|
||||
#define XAUI_HASHTBL_VEC_B319_288(block) NAE_REG(block, 4, 0x69)
|
||||
#define XAUI_HASHTBL_VEC_B351_320(block) NAE_REG(block, 4, 0x6a)
|
||||
#define XAUI_HASHTBL_VEC_B383_352(block) NAE_REG(block, 4, 0x6b)
|
||||
#define XAUI_HASHTBL_VEC_B415_384(block) NAE_REG(block, 4, 0x6c)
|
||||
#define XAUI_HASHTBL_VEC_B447_416(block) NAE_REG(block, 4, 0x6d)
|
||||
#define XAUI_HASHTBL_VEC_B479_448(block) NAE_REG(block, 4, 0x6e)
|
||||
#define XAUI_HASHTBL_VEC_B511_480(block) NAE_REG(block, 4, 0x6f)
|
||||
|
||||
#define XAUI_NETIOR_XGMAC_MISC0(block) NAE_REG(block, 4, 0x76)
|
||||
#define XAUI_NETIOR_RX_ABORT_DROP_COUNT(block) NAE_REG(block, 4, 0x77)
|
||||
#define XAUI_NETIOR_MACCTRL_PAUSE_QUANTA(block) NAE_REG(block, 4, 0x78)
|
||||
#define XAUI_NETIOR_MACCTRL_OPCODE(block) NAE_REG(block, 4, 0x79)
|
||||
#define XAUI_NETIOR_MAC_DA_H(block) NAE_REG(block, 4, 0x7a)
|
||||
#define XAUI_NETIOR_MAC_DA_L(block) NAE_REG(block, 4, 0x7b)
|
||||
#define XAUI_NETIOR_XGMAC_STAT(block) NAE_REG(block, 4, 0x7c)
|
||||
#define XAUI_NETIOR_XGMAC_CTRL3(block) NAE_REG(block, 4, 0x7d)
|
||||
#define XAUI_NETIOR_XGMAC_CTRL2(block) NAE_REG(block, 4, 0x7e)
|
||||
#define XAUI_NETIOR_XGMAC_CTRL1(block) NAE_REG(block, 4, 0x7f)
|
||||
|
||||
#define LANE_RX_CLK (1 << 0)
|
||||
#define LANE_TX_CLK (1 << 6)
|
||||
|
||||
#define XAUI_LANE_FAULT 0x400
|
||||
#define XAUI_CONFIG_0 0
|
||||
|
||||
#define XAUI_CONFIG_MACRST 0x80000000
|
||||
#define XAUI_CONFIG_RSTRCTL 0x00400000
|
||||
#define XAUI_CONFIG_RSTRFN 0x00200000
|
||||
#define XAUI_CONFIG_RSTTCTL 0x00040000
|
||||
#define XAUI_CONFIG_RSTTFN 0x00020000
|
||||
#define XAUI_CONFIG_RSTMIIM 0x00010000
|
||||
|
||||
#define XAUI_CONFIG_1 1
|
||||
|
||||
#define XAUI_CONFIG_TCTLEN 0x80000000
|
||||
#define XAUI_CONFIG_TFEN 0x40000000
|
||||
#define XAUI_CONFIG_RCTLEN 0x20000000
|
||||
#define XAUI_CONFIG_RFEN 0x10000000
|
||||
#define XAUI_CONFIG_DRPLT64 0x00000020
|
||||
#define XAUI_CONFIG_LENCHK 0x00000008
|
||||
#define XAUI_CONFIG_GENFCS 0x00000004
|
||||
#define XAUI_CONFIG_PAD_0 0x00000000
|
||||
#define XAUI_CONFIG_PAD_64 0x00000001
|
||||
#define XAUI_CONFIG_PAD_COND 0x00000002
|
||||
#define XAUI_CONFIG_PAD_68 0x00000003
|
||||
|
||||
#define XAUI_PHY_CTRL_1 0x00
|
||||
|
||||
#define NETIOR_XGMAC_CTRL1 0x7F
|
||||
#define NETIOR_XGMAC_CTRL3 0x7D
|
||||
|
||||
#define NETIOR_XGMAC_VLAN_DC_POS 28
|
||||
#define NETIOR_XGMAC_PHYADDR_POS 23
|
||||
#define NETIOR_XGMAC_DEVID_POS 18
|
||||
#define NETIOR_XGMAC_STATS_EN_POS 17
|
||||
#define NETIOR_XGMAC_TX_PFC_EN_POS 14
|
||||
#define NETIOR_XGMAC_RX_PFC_EN_POS 13
|
||||
#define NETIOR_XGMAC_SOFT_RST_POS 11
|
||||
#define NETIOR_XGMAC_TX_PAUSE_POS 10
|
||||
|
||||
#define NETIOR_XGMAC_STATS_CLR_POS 16
|
||||
|
||||
#if !defined(LOCORE) && !defined(__ASSEMBLY__)
|
||||
|
||||
void nlm_xaui_pcs_init(uint64_t, int);
|
||||
void nlm_nae_setup_rx_mode_xaui(uint64_t, int, int, int, int, int, int, int);
|
||||
void nlm_nae_setup_mac_addr_xaui(uint64_t, int, int, int, unsigned char *);
|
||||
void nlm_config_xaui_mtu(uint64_t, int, int, int);
|
||||
void nlm_config_xaui(uint64_t, int, int, int, int);
|
||||
|
||||
#endif /* !(LOCORE) && !(__ASSEMBLY__) */
|
||||
|
||||
#endif
|
||||
|
|
@ -32,6 +32,13 @@
|
|||
#ifndef _NLM_MSGRING_H
|
||||
#define _NLM_MSGRING_H
|
||||
#define CMS_DEFAULT_CREDIT 50
|
||||
/*
|
||||
* packets are sent to VC 0 of a thread
|
||||
* freebacks are sent to VC 3 of a thread
|
||||
*/
|
||||
#define XLPGE_RX_VC 0
|
||||
#define XLPGE_FB_VC 3
|
||||
|
||||
extern uint32_t xlp_msg_thread_mask;
|
||||
|
||||
struct nlm_fmn_msg;
|
||||
|
|
|
|||
Loading…
Reference in a new issue