From 348efb140e10e96e6bd0b25878578d4ecf246434 Mon Sep 17 00:00:00 2001 From: Alexander Motin Date: Fri, 15 Nov 2019 23:01:09 +0000 Subject: [PATCH] Initialize *comp_update with valid value. I've noticed that sometimes with enabled DMAR initial write from device to this address is somehow getting delayed, triggering assertion due to zero default being invalid. MFC after: 2 weeks Sponsored by: iXsystems, Inc. --- sys/dev/ioat/ioat.c | 11 +++++------ 1 file changed, 5 insertions(+), 6 deletions(-) diff --git a/sys/dev/ioat/ioat.c b/sys/dev/ioat/ioat.c index 7366c294200..d6385ff1f96 100644 --- a/sys/dev/ioat/ioat.c +++ b/sys/dev/ioat/ioat.c @@ -642,10 +642,9 @@ ioat3_attach(device_t device) dma_hw_desc->next = RING_PHYS_ADDR(ioat, i + 1); } - ioat->head = 0; - ioat->tail = 0; - ioat->last_seen = 0; - *ioat->comp_update = 0; + ioat->tail = ioat->head = 0; + *ioat->comp_update = ioat->last_seen = + RING_PHYS_ADDR(ioat, ioat->tail - 1); return (0); } @@ -1751,8 +1750,8 @@ ioat_reset_hw(struct ioat_softc *ioat) * at zero as well. */ ioat->tail = ioat->head = 0; - ioat->last_seen = 0; - *ioat->comp_update = 0; + *ioat->comp_update = ioat->last_seen = + RING_PHYS_ADDR(ioat, ioat->tail - 1); ioat_write_chanctrl(ioat, IOAT_CHANCTRL_RUN); ioat_write_chancmp(ioat, ioat->comp_update_bus_addr);